µPD78011B, 78012B, 78013, 78014
Contents
1. 18 5 3 TIMER EVENT COUNTER eene nnne U U e u E RS ENS EAR AR 19 54 CLOCK OUTPUT CONTROL CIRCUIT u u u 22 5 5 BUZZER OUTPUT CONTROL CIRCUIT U 22 5 6 A D CONVERTOR U U U U U u I I u u U I IIR IR uu uuu u uuu u Q 23 5 7 SERIAL INTERFACES ee 24 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 26 6 1 INTERRUPT FUNCTIONS nene ree e U u AR EAR A E E A I IE EA ER E IR 26 6 2 TEST FUNCTIONS 29 7 EXTERNAL DEVICE EXPANTION FUNCTIONS T T 30 8 STANDBY FUNCTIONS J I U u U U u U uuu u Q uu uuu u uu QQ 30 9 FUNCTIONS U U U U U U U U uu u u U uuu uuu u u Q Q 30 10 INSTRUCTION SET 31 11 ELECTRICAL SPECIFICATIONS U U U U U u u uu uu2. NOTES 1 Each lead centerline is located within 0 25 mm 0 01 inch of its true position T P at maximum material condition 2 Item to center of leads when formed parallel 0 159 P64D 70 750A1 MILLIMETERS INCHES 58 16 MAX 2 290 MAX B 1 521 MAX 0 060 MAX C 1 778 0 070 0 46 50 05 0 018 0 002 F 0 8 MIN 0 031 MIN G 3 5 0 3 0 138 0 012 H 1 02 MIN 0 040 MIN 3 14 0 124 5 08 0 200 K 19 05 T P 0 750 T P L 18 8 0 740 M 0 25 0 05 0 01070 003 N 0 25 0 01 uPD78011B 780128 78013 78014 DRAWINGS ES PRODUCT PACKAGES 2 2 64 PIN CERAMIC QFP 14 x 14 FOR ES 1 L l1 Lll 1 L Ill L a U 1 L _ L Ill 1 s l a L Il1 La Lll ua Lo __ L Ill 1 pL LL 1 T Y K ES T a 64 80 1 Bottom View ITEM MILLIMETERS INCHES A 22 0 0 4 0 866 0 016 14 0 0 551 G 14 0 0 551 D 22 0 0 4 0 866 0 016 F 1 0 0 039 G 1 0 0 039 H 0 32 0 013 J 0 8 T P 0 031 T P K 4 0 0 15 0 157100 M 0 25 0 01 Q 3 0 MAX 0 119 MAX T 0 55 0 022 U 1 0 0 039 V 1 2 0 047 78011 780128 78013 78014 14
3. 34 12 CHARACTERISTIC CURVE REFERENCE VALUES 58 13 PACKAGE INFORMATION U U U U I U U U QQ uu QQ u u QQ Q J Q 63 14 RECOMMENDED SOLDERING CONDITIONS J T Q Q Q 67 APPENDIX A DEVELOPMENT TOQOLS U U U nun U U U U uu uuu QQ Q 69 APPENDIX RELATED DOCUMENTS eere nnn U U U U U U U u Q u u u uu Q 71 uPD78011B 780128 78013 78014 1 CONFIGURATION View 64 Pin Plastic Shrink DIP 750 mil 20 511 21 501 P22 SCK1 P23 STB P24 BUSY 25 510 5 0 26 500 5 1 P27 SCKO P30 TOO P31 TO1 P32 TO2 1 4 12 P35 PCL P36 BUZ P37 Vss P40 ADO P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 Vss OO O O O O O O O O OO O O O OO O O O O O O O O O O O O ON O N PF 2 cg U U Ny W H 88 x x X x Xx x x x NOtT08 qdri MOS8CT108 Qd O O O O O O O O O O O O Q O O O O O O O O O O O O O O O O O O AVREF AVpp P17 ANI7 P16 ANI6 P15 ANI5 P14 ANI4 P13 ANI3 P12 ANI2 P11 ANI1 P10 ANIO AVss 4 1 2 1 X1 2 Von PO2 INTP2 POL INTP1 POO INTPO TIO RES
4. Electronic Notebook 744 1301 Development Tools Documents User s Manual Document Name RA78K Series Assembler Package Document No Document No J apanese English Operation EEU 809 EEU 1399 Language EEU 815 EEU 1404 RA78K Series Structured Assembler Preprocessor EEU 817 EEU 1402 CC78K Series C Compiler Operation EEU 656 EEU 1280 Language EEU 655 EEU 1284 PG 1500 PROM Programmer EEU 651 EEU 1335 PG 1500 Controller EEU 704 EEU 1291 IE 78000 R EEU 810 EEU 1398 IE 78000 R BK EEU 867 EEU 1427 IE 78014 R EM EEU 805 EEU 1400 SD78K 0 Screen Debugger Basic EEU 852 EEU 1414 Reference EEU 816 EEU 1413 Caution The contents of the above related documents are subject to change without notice The latest documents should be used for design etc 71 78011 780128 78013 78014 Embedded Software Documents User s Manual Document Name Fuzzy Knowledge Data Creation Tool Document No J apanese EEU 829 Document No English EEU 1438 78K 0 78 87AD Series Fuzzy Inference Development Support System Translator Other Documents Document Name Package Manual EEU 862 Document No J apanese IEI 635 EEU 1444 Document No English IEI 1213 Semiconductor Device Mounting Technology Manual IEI 616 IEI 1207 Quality Grade on NEC Semiconduct
5. 5 MOS INTEGRATED CIRCUIT 78011 78012B 78013 78014 8 SINGLE CHIP MICROCOMPUTER DESCRIPTION uPD78011B 78012B 78013 78014 are the prodcts the 78014 subseries within the 78K 0 Series The uPD78011B 78012B 78013 78014 have 8 bit resolution A D converter timer serial interface interrupt control and many other peripheral hardware functions A one time PROM or EPROM product uPD78P014 capable of operating the same power supply voltage range as of the mask ROM product and other development tools are also provided Functions are described in detail in the following User s Manual which should be read when carring out design work 78014 78014Y Series User s Manual IEU 1343 FEATURES Large on chip ROM amp RAM Data Memory Internal High Product Name ROM Speed RAM Program Memory Buffer RAM 78011 8K bytes 512 bytes 32 bytes e 64 pin plastic shrink DIP 750 mil 78012 16K bytes e 64 pin plastic QFP 14 mm 78013 24K bytes 1024bytes uPD78014 32K bytes External memory expansion space 64K bytes e Instruction execution time can be varied from high speed 0 4 us to ultra low speed 122 us e ports 53 N ch open drain 4 e 8 bit resolution A D converter 8 channels e Serial interface 2 channels Timer 5 channels Operating voltage range 2 7 to 6 0 V Ap
6. Register 0 5023 lt Selector etection lt 00 Circuit oe 16 Bit Capture Register 01 Intemal Bus Fig 5 3 8 bit Timer Enent Counter Block Diagram Intemal Bus e gt INTIM1 8 Bit Compare Register CR10 8 Bit Compare Register CR20 Output Match Selector Control HO TO2 P32 Circuit fx 22 fx 210 S 2 8 Ti it Timer Register 2 TM 2 6422 522 Clear 422 Selector Ti2 P34 Output TO1 P31 Circuit Intemal Bus 78011 780128 78013 78014 Fig 5 4 Watch Timer Block Diagram 5 Bit Counter 528 Selecto Prescaler INTWT fw 24 Selector gt Fig 5 5 Watchdog Timer Block Diagram fx fx INTWDT u 28 29 us 2 Maskable Interrupt Request Control Selector 8 Bit Counter Circuit RESET INTWDT Non Maskable Interrupt Request 21 78011 780128 78013 78014 54 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for clock output 39 1 2 78 1 2 156 2 313 2 625 2 1 25 MHz Main system clock at 10 0 MHz operation 32 768 kHz Subsystem clock at 32 768 kHz operation H gt 5 24 5 5 gt 28 5 5 5 BUZZER OUTPUT CONTROL CIRCUIT
7. 4 0 PORT1 2 i PORT3 PORT4 L PORT5 i PORT6 EXTERNAL ACCESS Intemal ROM amp RAM capacity varies depending on the product ii PO1 P03 P04 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 ADO P40 AD7 P47 A8 P50 A15 P57 ORD P64 O WR P65 O WAIT P66 O ASTB P67 JAN ELOSZ AZLOSZ 78011 780128 78013 78014 3 31 PORT PINS 1 2 04 1 Function Port 0 Input only After Reset Dual Function Pin INTPO TIO 5 bit I O port Input output can be specified bit wise When used as an input port pull up resistor can be used by software INTP1 INTP2 Input only XT1 P10 to P17 Port 1 8 bit input output port Input output can be specified bit wise When used as an input port pull up resistor can be used by software 2 ANIO to ANI7 Port 2 8 bit input output port Input output can be specified bit wise When used as an input port pull up resistor can be used by software 511 501 SCK1 STB BUSY 510 580 500 581 SCKO P37 Port 3 8 bit input output port Input output can be specified in 1 bit units When used as an input
8. Standby Release Signal Remarks 1 IF Testinput flag 2 MK Test mask flag uPD78011B 780128 78013 78014 7 EXTERNAL DEVICE EXPANSION FUNCTIONS The external device expansion function is used to connect external devices to areas other than the internal ROM RAM and SFR Ports 4 to 6 are used for connection with external devices 8 STANDBY FUNCTIONS There are the following two standby functions to reduce the current dissipation HALT mode The CPU operating clock is stopped The average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode STOP mode The main system clock oscillation is stopped The whole operation by the main system clock is stopped so that the system operates withultra low power consumption using only the subsystem clock Fig 8 1 Standby Functions Main System e Subsystem Clock ion Clock Operation 65 0 5 Als Instruction Instruction Instruction Interrupt Interrupt Request Request STOP Mode Main system clock oscillation stopped HALT Mode Clock supply to CPU is stopped oscillation HALT Mode Clock supply to CPU is stopped oscillation The power consumption can be reduced by stopping the main system clock When the CPU is operating on the subsystem clock set the MCC to stop the main system cloc
9. 4 5 to 6 0 V 800 3200 SCK high low level width 4 5 to 6 0 V tkcv1 2 50 tkcv1 2 150 SI setup time to SCKT 100 SI hold time from SCKT 400 SO output delay time from SCKL C 100 4 5 to 6 0 V Cis the load capacitance of SO output line b 3 wire serial I O mode SCK External clock input Parameter SCK cycle time Test Conditions 4 5 to 6 0 V SCK high low level width 4 5 to 6 0 V SI setup time to SCKT SI hold time from SCKT SO output delay time from SCKL 4 5 to 6 0 V C 100 pF SCK rise fall time When serial interface channel 0 is used When external device expansion function is used When 16 bit timer output function is When external used device expansion When 16 bit timer output function is function is not used not used SCK rise fall time When serial interface channel 1 is used When external device expansion function is used When external device expansion function is not used Cis the load capacitance of SO output line 78011 780128 78013 78014 SBI mode SCK Internal clock output Parameter SCK cycle time Test Conditions Vpop 4 5 to 6 0 V 800 3200 SCK high low level width 4 5 to 6 0 V tkcy3 2 50 tkcv3
10. n combination with bits 0 5 50 and 1 SCS1 of sampling clock select register selection of am is possible between fx 2N 1 fx 64 and fx 128 when 0 to 4 41 uPD78011B 780128 78013 78014 78011 780128 78013 78014 uPD78P014 Reference Tcv vs At main system clock operation Tcv vs At main system clock operation 60 a a gt gt 10 U i Guaranteed tion G reet peration Guarantee gt gt 20 1 0 0 0 1 2 3 4 5 6 Supply Voltage Vo V Supply Voltage Voo V Remarks indicates Ta 40 to 440 indicates 40 to 480 Caution The operation guaranteed range of the 78011 780128 78013 and 78014 differs from that of the uPD78PO14 uPD78011B 78012B 78013 78014 2 Read Write Operation Ta 40 to 85 Voo 2 7 to 6 0 V Parameter ASTB high level width Test Conditions O 5tcv Address setup time 0 5tcy 30 Address hold time Load resistor gt 5 10 Data input time from address 2420 50 tADD2 342n tcv 100 Data input time from RD Depp 142n tcv 25 tRDD2 2 542n tcv
11. tkcv7 2 150 SI setup time to SCKT 100 SI hold time from SCKT SO output delay time 4 5 to 6 0 V from SCKL C 100 pF STBT from SCKT 400 Strobe signal high level width tKcv7 30 tkcv7430 Busy signal setup time to busy signal detection timing Busy signal hold time from busy signal detection timing SCK from busy inactive 2tkcv7 Cisthe load capacitance of the SO output line 78011 780128 78013 78014 h 3 wire serial I O mode with automatic transmit receive function SCK External clock input Parameter Test Conditions SCK cycle time Vpp 4 5 to 6 0 V SCK high low level width 4 5 to 6 0 V SI setup time to SCKT SI hold time from 5 SO output delay time Vpp 4 5 to 6 0 V from SCK SCK rise fall time When external device expansion function function is used When external device expansion function is not used Cis the load capacitance of the SO output line 78011 780128 78013 78014 4 A D converter characteristics 40 to 85 C Vpp 2 7 to 6 0 AVss Vss 0 Parameter Resolution Test Conditions Overall Conversion time Sampling time Analog input voltage Reference voltage current
12. 5 08 MAX 0 200 MAX K 19 05 0 750 T P L 17 0 0 669 u ee N 0 17 0 007 R 0 15 0 15 64 70 750 1 Caution Dimensions and materials of ES products are different from those mass production products Refer x to DRAWINGS OF ES PRODUCT PACKAGES 1 2 78011 78012 78013 78014 DRAWINGS MASS PRODUCTION PRODUCT PACKAGES 2 2 64 PIN PLASTIC QFP 14 E ar I i d P64GC 80 AB8 3 NOTE MILLIMETERS INCHES Each lead centerline is located within 0 15 mm 0 006 inch of its true position T P at A 17 6 0 4 0 693 0 016 maximum material condition B 14 0 0 2 0 551 9 009 14 0 0 2 0 55 119 009 17 6 0 4 0 693 0 016 1 0 0 039 G 1 0 0 039 H 0 35 0 10 0 014 2 00 0 15 0 006 0 8 0 031 K 1 8 0 2 0 071 0 008 L 0 8 0 2 0 031 0 008 M 0 1599 0 006 2 004 0 10 0 004 2 55 0 100 Q 0 1 0 1 0 004 0 004 5 2 85 0 112 detail of lead end Caution Dimensions and materials of ES products are different from those of mass production products Refer to DRAWINGS OF ES PRODUCT PACKAGES 2 2 64 78011 780128 78013 78014 DRAWINGS ES PRODUCT PACKAGES 1 2 64PIN CERAMIC SHRINK DIP SEAM WELD 750 mil
13. Interrupt Priority Control Request Circuit Standby Release Signal B Internal Maskable Interrupt Internal Bus Vector Table Address Generator Interrupt Request Priority Control Circuit Standby Release Signal C Extemal Maskable Interrupt INTPO Intemal Bus Sampling Clock Select Register SCS Extemal Interrupt Mode Register INTM O Vector Table Address Generator Standby Release Signal 27 uPD78011B 780128 78013 78014 Fig 6 1 Basic Interrupt Function Configuration 2 2 0 Extemal Maskable Interrupt Except Internal Bus Extemal Interrupt Mode Register INTM 0 Vector Table Interrupt Edge Address Request Detector Generator gt Standby Release Signal E Software Interrupt Intemal Bus Interrupt Priority Control circul Generator Remarks 1 IF Interrupt request flag 2 IE Interrupt enable flag ISP In service priority flag 4 MK Interrupt mask flag 5 PR Priority spcification flag 78011 780128 78013 78014 62 TEST FUNCTIONS There are two test functions as shown in Table 6 2 Table 6 2 Test Source List Test Source Internal External Name Trigger INTWT Watch timer overflow Internal INTPT4 Port 4 falling edge detection External Fig 6 2 Test Function Basic Configuration Intemal Bus
14. gt gt Dem 5 lt TASTRD RD lt troL2 E p lt twps lt gt 4 twowr WR m Deng Br ant Le LWRADH gt WAIT tRDWT2 a La gt lt gt lt gt twRwT twr twrwe 53 uPD78011B 780128 78013 78014 Serial Transfer Timing 3 wire serial I O m ode tkcv 12 SCK Sl 50 SBI mode Bus release signal transfer SCK tsik3 4 tksi3 4 lt q s SBO SB1 SBI Mode command signal transfer tkcy3 4 tkH3 4 SCK tksi3 4 SBO SB1 78011 780128 78013 78014 2 serial I O mode SCK tks s 6 580 581 3 wire serial I O mode with automatic transmit receive function 50 Sl tkso7 8 SCK STB 3 wire serial I O mode with automatic transmit receive function busy processing SCK BUSY Active High The signal is not actually driven low here it is shown as such to indicate the timing 55 uPD78011B 780128 78013 78014 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 40 to 85 Parameter Data retention supply voltage Test Conditions Data retention supply current Vpppr 2 0 V Subsystem clock stop and feed back resister disconnected Release signal set time Oscillation st
15. 0 series common system simulator DF78014 245 uPD78014 subseries device file Real Time OS 78 2 3 78 0 series common real time OS 78 0 2 3 6 78K 0 series common OS Fuzzy Inference Devieopment Support System FE9000 1 FE9200 5 Fuzzy knowledge data creation tool 9080 9085 2 Translator FI78KO 2 Fuzzy inference module FD78K0 2 Fuzzy inference debugger 1 9800 series MS DOS based 2 IBM PC AT PC DOS based 3 9000 series 3007 HP9000 series 700 HP UX based SPARCstation SunOS based 5 4800 series EWS UX V based 69 78011 780128 78013 78014 4 9800 series MS DOS Windows based 5 IBM PC AT PC DOS Windows based 6 Under development Remarks 1 For development tools manufactured by a third party see the 78 0 Series Selection Guide IF 1185 2 RA78K 0 CC78K 0 SD78K 0 5 78 0 are used in combination with DF78014 78011 780128 78013 78014 APPENDIX RELATED DOCUMENTS Device Related Documents Document Name User s Manual Document No Document No J apanese English 1 780 IEU 1314 78 0 Series User s Manual Instruction IEU 849 IEU 1372 Application Note Basic IEA 715 1288 Basic Il 740 1299 Floating Point Arithmetic 718 IEA 1289 Program
16. 14 mm 78014 8 64 Pin Plastic QFP 14 mm Soldering Method Infrared reflow Soldering Conditions Package peak temperature 235 C Duration 30 sec max at 210 C or above Number of times Twice lt Points to note gt 1 Start the second reflow after the device temprature by the first reflow returns to normal 2 Flux washing by the water after the first reflow should be avoided Recommended Condition Symbol IR35 00 2 Package peak temperature 215 C Duration 40 sec max at 200 C or above Number of times Twice lt Points to note gt 1 Start the second reflow after the device temprature by the first reflow returns to normal 2 Flux washing by the water after the first reflow should be avoided VP15 00 2 Wave soldering Solder bath temperature 260 C max Duration 10 sec max Number of times Once Preliminary heat temperature 120 C max Package surface temperature WS60 00 1 Pin part heating Pin temperature 300 C max Duration 3 sec max per device side Caution Use more than one soldering method should be avoided except in the case of pin part heating 67 78011 780128 78013 78014 Table 14 2 Insertion Soldering Conditions LuPD78011BCW xx 64 Pin Plastic Shrink DIP 750 mil 78012 64 Pin Plastic Shrink DIP 750 mil UPD78013CW xxx 64 Pin Plastic Shrink DIP 750 mil UP
17. Oscillator Voltage Range pF C2 pF R1 kQ MIN V MAX V 5 1 01 to 1 25 CSAx xxxMK 1 26 to 1 79 CSAx xxMG CSTx xxMG 1 80 to 2 44 CSAx xxMG CSTx GW 2 45 to 4 18 CSAx xxMG CSTx 4 19 to 6 00 CSAx xxMT CSTx xxMTW 6 01 to 10 0 Kyocera KBR 4 19MWS KBR 4 19M KS KBR 4 19MSA PBRCA 19A KBR 10 0M KBR 1000F KBR 1000Y uPD78013 78014 Manufacture Murata Mfg Co Ltd Remarks x x indicate frequency Product Name CSB1000 Frequency MHz 1 00 Recommended Circuit Constant Oscillator Voltage Range pF C2 pF R1 kQ MIN V MAX V 5 1 01 to 1 25 CSAx xxxMK 1 26 to 1 79 CSAx xxMG CSTx xxMG 1 80 to 2 44 CSAx xxMG CSTx GW 2 45 to 4 18 CSAx xxMG CSTx 4 19 to 6 00 CSAx xxMT CSTx xxMTW 6 01 to 10 0 37 uPD78011B 780128 78013 78014 Subsystem clock Cristal resonator 40 to 60 78011 780128 Manufacture Daishinku Products DT 38 1TA632 E00 load capacitance 6 3 pF uPD78013 78014 Manufacture Daishinku Product Name DT 38 1TA632 load capacitance 6
18. gt pullup pullup enable Von data Ph output ALL E Kou IN OUT disable outpu N ch disable E enable enable 15 IN OUT output disable 3 HI input ch IN OUT Vo gt EI Vpp D ER IN OUT N ch P ch _ 777 L hreshold Voltage Mask 2 Option 3 oIN OUT pullup enable Vo 558 ms M iddle High Voltage Input Buffer feedback cut off P ch ANN IN OUT output disable 78011 780128 78013 78014 4 5 The memory map of uPD78011B 78012B 78013 78014 is shown 4 1 i FFFFH Space FABFH FA80H Program Memory Space nnnnH 1 nnnnH 0000H mmmmH 1 Use Prohibited FAEOH Data FADFH Memory Buffer RAM 32 x 8 Bits FACOH Use Prohibited External Memory Internal ROM Fig 4 1 Memory Map Special Function Registers SFR 256 x 8 Bits FFOOH FEFFH General Registers FEEOH 32 x 8 Bits FEDFH Internal High Speed RAM mmmmH nnnnH Program Area 1000H OFFFH CALLF Entry Area 0800H O7FFH Program Area 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area 0000H
19. 100 pin package added LCD controller driver External expansion function Y series products are compatible with bus UART added enhanced 16 bit timer event counter function enhanced Lu PD78054Y SubSeries 78054 SubSeries 80 pin package UART D A converter Real time output port added 16 bit timer event counter function enhanced 80 pin package IEBus controller added UART A D converter 8 bit timer event counter function enhanced Low voltage high speed operation possible 64 pin package A D converter 16 bit timer event counter function Ee automatic transmit receive function 1 780208 SubSeries Multiplication division instruction added FIP controller driver function enhanced 80 pin package Automatic transmit receive function added 6 bit up down counter added FIP controller driver function enhanced 78024 SubSeries L1 PD78002Y SubSeries 64 pin package A D converter 16 bit timer event counter FIB controller driver 64 pin package Multiplication division instruction added 78002 SubSeries uPD78011B 780128 78013 78014 OVERVIEW OF FUNCTION 1 2 Product Name ROM uPD78011B uPD78012B uPD78013 uPD78014 8K bytes 16K bytes 24K bytes 32K bytes Internal high speed RAM Internal memory 512 bytes 1024 bytes Buffer RAM 32 bytes Memory space 64K bytes General registers 8 bits
20. Overroll error excluding quantization error 1 2 LSB It is indicated as a ratio to the full scale value 78011 780128 78013 78014 Timing Test Point Excluding X1 XT1 Input 0 8 0 8 0 2 2 Test Polis ad 0 2 Clock Timing X1 Input XT1 Input Timing l fn tn thy 0 2 51 78011 780128 78013 78014 Read Write Operation Extemal fetch No wait 8 15 ADO AD7 ASTB Upper 8 Bit Address Extemal fetch Wait insertion 8 15 ADO AD7 ASTB WAIT Upper 8 Bit Address Lei gt Lower 8 Bit Address taps lt gt lt gt tRDD1 tasTH lt Lower 8 Bit Address taps gt 4 trop gt Le tRDADH gt TADH Dem Le lRDAST 5 4 USTD 4 tRDL1 gt amp gt lwTRD trow 3 twr L tapast gt uPD78011B 780128 78013 78014 Extemal data access wait 8 15 Upper 8 Bit Address Lower 8 Bit Address N ADO AD7 taps gt Dem 5 RD WR twos a gt lt a twRaDH Extemal data access Wait insertion A8 A15 Upper 8 Bit Address Lower 8 Bit Address 4 ADO AD7 ME dz taps lt
21. P50 to P57 P60 to P67 RESET X1 X2 XT1 P04 XT2 P60 to P63 Input leakage current low POO to P10 to P17 P20 to P27 P30 to P37 P40 P64 to P47 P50 to P57 to P67 RESET X1 X2 XT1 P04 XT2 P60 to P63 1 Other than above 1 When memory expansion mode is used by the memory expansion mode register MM with no on chip pull up resistor by mask option 2 When pull up resistors are not used Specified by mask option the low level input leakage current increases with 200 uA MAX under either of the following conditions 1 When the external device expansion function is used and a low level is input to the pin 2 During the 3 clock period when a read instruction is executed on port 6 P6 and the port mode registor PM 6 Remarks The characteristics of a dual function pin and a port pin are the same unless specified otherwise 39 78011 780128 78013 78014 DC Characteristics Ta 40 to 85 C Vpp 2 7 to 6 0 V Parameter Test Conditions Output leakage current high Output leakage Vour 20V current low Mask option pull ViN 0 V P60 to P63 up resister Software pull Vin 0 V 1 to up resister P10 to P17 P20to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 2 7 V lt Vpp lt 4 5 V 4 5 V lt 6 0 V Power supply p oo Mi Vpp 5 0 V 10 Crystal os
22. 0 V 1600 3800 SCK high level width 1 C 100 pF 5 2 50 SCK low level width tkcv5 2 50 SBO 581 setup time to SCKT 300 SBO 581 hold time from SCKT SBO SB1 output delay time 1 4 5 to 6 0 V from SCKL C 100 pF Rand Care the load resistors and load capacitance of the 5 580 and 581 output line 46 78011 780128 78013 78014 f 2 wire serial I O mode SCK External clock input Parameter SCK cycle time Test Conditions 4 5 to 6 0 V SCK high level width SCK low level width SBO 581 setup time to SCKT SBO 581 hold time from SCKT SBO SB1 output delay time from SCKL R 1 Voo 4 5 to 6 0 V C 100 pF SCK rise fall time When external device expansion function is used When 16 bit timer When external output function is device expansion used function is not When 16 bit timer used output function is not used Rand Care the load resistors and load capacitance of the SCK0 580 581 output line 47 uPD78011B 780128 78013 78014 g 3 wire serial I O mode with automatic transmit receive function SCK Internal clock output Parameter Test Conditions SCK cycle time 4 5 to 6 0 V 800 3200 SCK high low level width Vpp 4 5 to 6 0 V tkcy7 2 50
23. 100 Read data hold time tRDH 0 RD low level width tRDL1 1 542n tcv 20 tRDL2 2 542n tcv 20 WAIT input time from RD tRDWT1 0 5tcy tRDWT2 1 5tcy WAIT input time from WR twRwT 0 5tcy WAIT low level width 0 542n tcv 10 242n tcv Write data setup time 100 Write data hold time 5 WR low level width twRL1 2 542n tcy 20 RD delay time from ASTBL tasTRD 0 5tcy 30 WR delay time from 5 tASTWR 1 5tcy 30 ASTBT delay time from in external fetch tRDAST tcv 10 Address hold time from RDT in external fetch tRDADH tcy Write data output time from RDT tRDWD 10 WR delay time from write data 4 5 to 6 0 V 0 5tcy 120 O 5tcv O 5tcv 170 0 5tcy Address hold time from WRT 4 5 to 6 0 V tcy tcy 60 tcy 100 delay time from WAITT 2 5tcy 80 WRT delay time from WAITT Remarks 1 tcv Tcv 4 2 5tcy 80 2 nindicates number of waits 3 CL 100 pF C indicates load capacitance of P40 ADO to P47 AD7 P50 A8 57 15 P64 RD P65 WR P66 WAIT P67 ASTB pins 78011 780128 78013 78014 3 Serial Interface Ta 40 to 85 C 2 7 to 6 0 a 3 wire serial I O mode SCK Internal clock output Parameter SCK cycle time Test Conditions
24. 25 C 5 6 4 V lt 8 z 6 2 2 5 5 5 0 0 5 1 0 Output Voltage Low Vox V Vor vs lo Port 1 25 VVop 5 V lt 2 2 2 5 5 5 0 0 5 1 0 Output Voltage Low Vo V 61 178011 780128 78013 78014 62 vs lot P60 to P63 Ta 25 C 30 Vpp 5 V Vpp 4 V lt 3 20 2 5 21 5 5 5 10 0 0 5 1 0 Output Voltage Low Vo V vs Port 0 to 5 P64 to P67 Ta 25 C t Vpp 5 V 4 V 5 5 5 5 0 5 1 0 Output Voltage High Voo Vor V uPD78011B 780128 78013 78014 13 PACKAGE INFORMATION DRAWINGS OF MASS PRODUCTION PRODUCT PACKAGES 1 2 64 PIN PLASTIC SHRINK DIP 750 mil K L R NOTE ITEM MILLIMETERS INCHES 1 Each lead centerline is located within 0 17 mm 0 007 inch of A 58 68 2 311 its true position T P at maximum material condition 1 78 MAX 0 070 MAX 1 778 T P 0 070 T P 2 Item K to center of leads when formed parallel 0 004 0 50 0 10 0 020 0 004 B C D 0 0 9 0 035 G 3 250 3 0 126 0 012 0 51 MIN 0 020 MIN 4 31 0 170
25. Oscillation 0 5 lt 2 5 9 0 1 gt 0 05 HALT X1 Stop XT1 Oscillation STOP X1 Stop XT1 Oscillation 0 01 fx24 19MHz 0 005 fxr232 768kHz 0 001 Supply Voltage Ven V 58 78011 780128 78013 78014 lob vs Main System Clock 4 19 MHz Ta 25 C 10 0 5 0 PCC 00H PCC 01H PCC 02H PCC 03H PCC 04H PCC 30H HALT X1 Oscillation 1 0 XT1 Oscillation 0 5 lt 8 2 5 9 0 1 2 PCC B0H 0 05 HALT X1 Stop XT1 Oscillation STOP X1 Stop XT1 Oscillation 0 01 x24 19MHz 0 005 fxt 32 768kHz 0 001 Supply Voltage Von V 59 178011 780128 78013 78014 60 Supply Current lop mA vs fx V Ta 25 02H 03H 04 3 4 5 6 7 8 Clock Oscillator Frequency fx vs fx HALT X1 Oscillation Voo 5 V Ta 25 C Supply Current lop mA 02H 03H 04 HALT 1 Oscillation 3 4 5 6 7 8 Clock Oscillator Frequency fx 78011 780128 78013 78014 vs lot Port 0 2 to 5 P64 to P67 Ta
26. RECOMMENDED SOLDERING CONDITIONS The uPD78011B 78012B 78013 78014 should be soldered and mounted under the conditions recommended in the table below For detail of recommended soldering conditions refer to the information document Semiconductor Device Mounting Technology Manual 1207 For soldering methods and conditions other than those recommended below contact our salespersonnel Table 14 1 Surface Mounting Type Soldering Conditions 1 78011 8 64 Pin Plastic 14 mm 78012 8 64 Pin Plastic QFP 14 mm Soldering Method Infrared reflow Soldering Conditions Package peak temperature 235 C Duration 30 sec max at 210 C or above Number of times Twice max lt Points to note gt 1 Start the second reflow after the device temprature by the first reflow returns to normal 2 Flux washing by the water after the first reflow should be avoided Recommended Condition Symbol IR35 00 2 Package peak temperature 215 C Duration 40 sec max at 200 C or above Number of times Twice max lt Points to note gt 1 Start the second reflow after the device temprature by the first reflow returns to normal 2 Flux washing by the water after the first reflow should be avoided VP15 00 2 Pin part heating Pin temperature 300 C max Duration 3 sec max per device side 2 78013 8 64 Pin Plastic QFP
27. Remarks Shaded area indicates internal memory ntermal ROM and internal high speed RAM capacities vary depending on the product see the table below Intenal ROM End Address nnnnH Product Name uPD78011B uPD78012B Internal High Speed RAM StartAddress mmmmH uPD78013 uPD78014 16 78011 780128 78013 78014 5 PERIPHERAL HARDWARE FUNCTION FEATURES 5 1 PORTS The I O port has the following three types CMOS input P04 02 CMOS input output PO1 to port 1 to port 5 P64 to P67 47 N ch open drain input output 15V withstand voltage P60 to P63 4 Total 53 Table 5 1 Functions of Ports Port Name Pin Name Function POO P04 Dedicated Input port 1 to Input output ports Input output can be specified bit wise When used as an input port pull up resistor can be used by software P10 to P17 Input output ports Input output can be specified bit wise When used as an input port pull up resistor can be used by software P20 to P27 Input output ports Input output can be specified bit wise When used as an input port pull up resistor can be used by software P30 to P37 Input output ports Input output can be specified bit wise When used as an input port pull up resistor can be used by software P40 to P47 Input output ports Input output can be specified in 8 bit units When used as an input port pull up resistor can be used by softwar
28. x 32 registers 8 bits x 8 registers x 4 banks Instruction cycle On chip instruction execution time cycle modification function When main system clock selected 0 4 5 0 8 5 1 6 5 3 2 5 6 4 at 10 0 MHz operation When subsystem clock selected 122 at 32 768 kHz operation Instruction set 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test boolean operation BCD correction etc ports Total 253 CMOS input e CMOS UO 47 e N channel open drain UO 15 withstand voltage 4 A D converter 8 bit resolution 8 channels e Operable over wide power supply voltage range 2 7 to 6 0 V Serial interface 3 wire SBI 2 wire mode selectable 1 channel 3 wire mode on chip max 32 bytes automatic data transmit receive function 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output 14 bit PWM output x 1 Clock output 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz at main system clock 10 0 MHz operation 32 768 kHz at subsystem clock 32 768 kHz operation Buzzer output 2 4 kHz 4 9 kHz 9 8 kHz at main system clock 10 0 MHz operation Maskable interrupts Vectored interrupts Internal 8 External 4 Non mask
29. 2 150 SBO 581 setup time to SCKT Vpp 4 5 to 6 0 V 100 300 SBO 581 hold time from SCKT tkcv3 2 SBO SBloutput delay time from SCKL R 1kQ 4 5 to 6 0 V C 100 pF 580 5814 from SCKT SCK from 580 Spil SBO SB1 high level width SBO SB1 low level width Rand Care the load resistors and load capacitance of the SBO 581 output line 78011 780128 78013 78014 d SBI mode SCK External clock output Parameter Test Conditions SCK cycle time Vpop 4 5 to 6 0 V 800 3200 SCK high low level width 4 5 to 6 0 V 400 1600 SBO 581 setup time to 4 5 to 6 0 V 100 SCKT 300 SBO 581 hold time from SCKT 4 2 SBO SB1 output delay time R 1kQ Vpp 4 5 to 6 0 V from SCKL C 100 pF SBO 5814 from SCKT SCKJ from 580 Spil SBO SB1 high level width SBO SB1 low level width SCK rise fall time When external device expansion function is used When 16 bit timer output function is When external device used expansion function is not used When 16 bit timer output function is not used Rand Care the load resistors and load capacitance of the 580 581 output line 2 wire serial I O mode SCK Internal clock output Parameter Test Conditions SCK cycle time 4 5 to 6
30. 3 TIO to 2 TOO to TO2 SBO SB1 510 511 500 501 5 5 1 PCL BUZ STB BUSY Port 0 Port 1 Port 2 Port Port 4 Port 5 Port 6 Interrupt From Peripherals Timer Input Timer Output Serial Bus Serial Input Serial Output Serial Clock Programmable Clock Buzzer Clock Strobe Busy ADO to AD7 A8 to A15 RD WR WAIT ASTB X1 X2 XT1 XT2 RESET ANIO to ANI7 AVss AVREF Address Data Bus Address Bus Read Strobe Write Strobe Wait Address Strobe Crystal Main System Clock Crystal Subsystem Clock Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Ground Internally Connected PROGRAM MEMORY GENERAL REG K DECODE AND CONTROL DATA MEMORY 16 bit TIMER EVENT COUNTER 1 8bit IMER mp EVENT COUNTER 1 2 2 8bit TMER T2P34 EVENTCOUNTER 2 WATCHDOGTIMER WATCH TIMER SIO SBO P25 2 500 5 1 26 0 5 27 S 1 P20 SERIAL SCK1P22 INTERFACE 1 5 23 BUSY P24 10 AN7P17 A D CONVERTER INTERRUPT 9 CONTROL CLOCK OUTPUT CONTROL BUZ P36 Remarks STAND BY CONTROL CLOCK GENERATOR DIVIDER MAIN
31. 3 pF Frequency MHz Frequency M Hz Recommended Circuit Constant Oscillator Voltage Range pF Recommended Circuit Constant Oscillator Voltage Range pF MAX V 78011 780128 78013 78014 DC Characteristics Ta 40 to 85 2 7 to 6 0 V Parameter Input voltage high Test Conditions P10 to P17 P21 P23 P30 to P32 P35 to P37 P40 to P47 P50 to P57 P64 to P67 lt POO to P20 P22 P24 to P27 P33 P34 RESET P60 to P63 Open drain X1 X2 XT1 P04 2 4 5 to 6 0 V el lt lt lt Input voltage low P10 to P17 P21 P23 P30 to P32 P35 to P37 P40 to P47 P50 to P57 P64 to P67 lt to P20 P22 P24 to P27 P33 P34 RESET P60 to P63 Vpop 4 5 to 6 0 V X1 X2 XT1 P04 XT2 Voo 4 5 to 6 0 V Output voltage high 4 5 to 6 0 1 loH 100 wm lt e oS Output voltage low P50 to P57 P60 to P63 4 5 to 6 0 V lo 15 mA lt POL to P10 to P17 P20 to P27 P30 to P37 P40 to P47 P64 to P67 4 5 to 6 0 V lo 1 6 mA SBO 581 5 4 5 to 6 0 V open drain pulled up 1 KQ lo 400 uA Input leakage current high POO to P10 to P17 P20 to P27 P30 to P37 P40 to P47
32. D78014CW xxx 64 Pin Plastic Shrink DIP 750 mil Soldering Method Soldering Conditions Wave soldering Solder bath temperature 260 C max pin only Duration 10 sec max Pin part heating Pin temperature 300 C max Duration 3 sec max per pin Caution Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly 78011 780128 78013 78014 APPENDIX DEVEROPMENT TOOLS The following development tools are available for system development using the uPD78011B 78012B 78013 78014 Language Processing Software 78 0 2 3 78 0 series common assembler package CC78K 0 2 3 78 0 series common C compiler package DF78014 2 3 uPD78014 subseries device file CC78K 0 L 2 3 78K 0 series common C compiler library source file PROM Writting Tools PG 1500 PROM programmer PA 78P014CW Programmer adapter connected to PG 1500 PA 78P014GC PG 1500 controller 2 PG 1500 control program Debugging Tool IE 78000 R 78 0 series common in circuit emulator IE 78000 R BK 78 0 series common break board IE 78014 R EM 78002 78014 subseries evaluation emulation board EP 78240CW R Emulation probe common to uPD78244 subseries EP 78240GC R EV 9200GC 64 Socket to be mounted on user system board created for the 64 pin plastic QFP 5078 0 2 78000 screen debugger SM 78 0 5 6 78
33. ET P67 ASTB P66 WAIT P65 WR P64 RD P63 P62 P61 P60 P57 A15 P56 A14 Caution 1 Always connect the IC Internally Connected pin to Vss directly 2 Always connect the AVpp pin to 3 Always connect the AVss pin to Vss uPD78011B 780128 78013 78014 64 Pin Plastic QFP 14 g E 2h z oof 5 F O O 2d z Z Z 2 gt s S lt lt lt lt lt p lt N E a N N NN NN gt gt d o d 11111111 P30 TOO 0 11 P10 ANIO P32 TO2 AVss baam PO4 XT1 4 112 2 UU g g P35 PCL O 9999 5555 P36 BUZ O rp 1 58065 P37 2 Vss O x x 1 x x X X P40 AD0 x x X X PO3 INTP3 P P 4 41 56 L PO2 INTP2 PA2 AD2 5 5 1 1 P43 AD3 POO INTPO TIO PAJADA Q RESET P45 AD5 P67 ASTB P46 AD6 Q P66 WAIT GE UT COCO COCO lt lt lt lt lt 7 lt 8 8 8 Dm N M FT A N 4 N m N N aN o a n a Caution 1 Always connect the IC Intemally Connected pin to Vss directly 2 Always connect the AVpp pin to 3 Always connect the AVss pin to Vss 78011 780128 78013 78014 POO to 4 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 INTPO to INTP
34. Serial Interface Channel 1 3 wire serial 1 mode 2 MSB LSB first switchable MSB LSB first switchable 3 wire serial I O mode with automatic data transmit MSB LSB first switchable receive function SBI Serial Bus Interface mode MSB first 2 wire serial UO mode MSB first Fig 5 9 Serial Interface Channel 0 Block Diagram Intemal Bus SIO SBO P25 D gt 500 581 26 5 Serial I O Shift Register 0 5100 Busy Acknowlede Output Circuit Selector Bus Release Command Acknowledge Detection Circuit Interrupt INTCSIO Serial Counter 9 522 429 Serial Clock Control Circuit SCKO P27 0 TO2 A V AAV 78011 780128 78013 78014 Fig 5 10 Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit Receive Address Pointer Buffer RAM 511 20 0 Serial I O Shift Register 1 5100 5 1 21 Handshake Control STB P23 BUSY P24 Circuit SCK P22 Interrupt Request Signal Generator fx 2 fx 29 Selector TO2 INTCSI1 Serial Counter Serial Clock Control Circuit 25 78011 780128 78013 78014 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6 1 INTERRUPT FUNCTIONS There are the 14 interrupt functions of 3 different kin
35. The clock with the following frequencies can be output for buzzer output 2 4 kHz 4 9 kHz 9 8 kHz Main system clock at 10 0 MHz operation f 210 fx 41 5 2 Fig 5 6 Clock Output Control Block Diagram Selector Synchronization Circuit L Output Control Circuit Fig 5 7 Buzzer Output Control Block Diagram Selector Circuit Output Control BUZ P36 PCL P35 78011 780128 78013 78014 5 6 A D CONVERTER The A D converter has on chip eight 8 bit resolution channels There are the following two method to start A D conversion Hardware starting Software starting Fig 5 8 A D Converter Block Diagram Series Resistor String ANIO P10 Sample amp Hold Circuit ANI1 P11 0 Voltage Comparator 2 12 O AMI Gand ANI4 P14 O ANI5 P15 O 16 0 Succesive Approxmation 7 17 i us EN ES AVss INTP3 PO3 5 Detector gt INTP3 Conversion Result Register ADCR Internal Bus 78011 780128 78013 78014 57 SERIAL INTERFACES There are two on chip clocked serial interfaces as follows Serial Interface channel 0 Serial Interface channel 1 Table 5 3 Type and Function of Serial Interface Function Serial Interface Channel 0
36. abilization wait time Release by RESET 218 fx Release by interrupt n combination with bit 0 to bit 2 OSTSO to 05752 of oscillation stabilization time select register selection of 2134 and 215 fx to 218 fx is possible Data Retention Timing STOP Mode Release by RESET Internal Reset Operation STOP Mode Von A STOP Instruction Execution Data Retension Mode lt gt lt HALT Mode gt lt Operating Mode Le twat gt Data Retention Timing Standby Release Signal STOP Mode Release by Interrupt Signal 1 STOP Instruction Execution HALT Mode STOP Mode lt Retension M ode gt lt Operating Mode Standby Release Signal Interrupt Request 4 gt uPD78011B 780128 78013 78014 Interrupt Input Timing gt Le tiNTH INTPO INTP2 tint INTP3 RESET Input Timing tRSL RESET 57 178011 780128 78013 78014 12 CHARACTERISTIC CURVE REFERENCE VALUES vs Main System Clock 8 38 MHz Ta 25 C 10 0 5 0 00 01 02 04 HALT 1 Oscillation 1 0 XT1
37. able interrupt Internal 1 Software interrupt Internal 1 78011 780128 78013 78014 OVERVIEW FUNCTION 2 2 uPD78011B uPD78012B uPD78013 uPD78014 Product Name Test input Internal 1 External 1 Operating voltage range 2 7 to 6 0 V Operating temperature range Package 64 pin plastic shrink DIP 750 mil e 64 pin plastic QFP 14 mm 40 to 85 C uPD78011B 780128 78013 78014 5 1 CONFIGURATION TOP VIEVN J 6 uu eU 9 FUNCTIONS H 10 3 1 PORT PINS 10 3 2 OTHER PORTS 11 3 3 PIN CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PING 13 4 MEMORY SPACE U U U U U U u u U uuu uu U Q uu uuu Qu 16 5 PERIPHEL HARDWARE FUNCTION FEATURES Q J Q Q 17 5 1 al 17 5 2 CLOCK GENERATOR
38. bsystem clock trimming P35 BUZ Output Buzzer output P36 ADO to AD7 Input output Low order address data bus at external memory expansion P40 to P47 A8 to 15 Output High order address bus at external memory expansion P50 to P57 RD Output External memory read operation strobe signal output External memory write operation strobe signal output P64 Input Wait insertion at external memory access Output Strobe output which latches the address information output at port 4 and port 5 to access external memory ANIO to ANI7 Input A D converter analog input P10 to P17 AVREF Input A D converter reference voltage input AVDD A D converter analog power supply Connected to AVss A D converter ground potential Connected to Vss RESET System reset input X1 Main system clock oscillation crystal connection Subsystem clock oscillation crystal connection Positive power supply Ground potential Internal connection Connected to Vss directly 78011 780128 78013 78014 3 3 CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The input output circuit type of each pin and recommended connection of unused pins are shown in Table 3 1 For the input output circuit configuration of each type see Fig 3 1 Table 3 1 Input Output Circuit Typ
39. ci operating m Vpp 3 0 V 10 current 5 8 38 MHz 5 0 V 10 Crystal osci HALT mode Vpp 3 0 V 10 32 768 kHz Vpp 5 0 V 10 Crystal oscillation operating mode Vpp 3 0 V 10 32 768 kHz 5 0 V 10 Crystal oscillation HALT mode Vpp 3 0 V 10 1 0V STOP mode 5 0 V 10 When feedback resister is used Vpp 3 0 V 10 1 STOP mode 5 0 V 10 When feedback resister is unused Vpp 3 0 V 10 3 Operating in high speed mode when set the processor clock control register to 00H 4 Operating in low speed mode when set the processor clock control register to 04H 5 AVre current and port current are excluded Remarks characteristics of a dual function pin and a port pin the same unless specified otherwise 78011 780128 78013 78014 Characteristics 1 Basic Operation 40 to 85 2 7 to 6 0 V Parameter Test Conditions Cycle time Operating on main 4 5 to 6 0 V Min instruction system clock execution time Operationg on subsystem clock Tl input 4 5 to 6 0 V frequency input high 4 5 to 6 0 V low level width 18 Interrupt input INTPO 8 fsam high low level width INTP1 to INTP3 10 KRO to KR7 10 RESET low level width 10
40. cillator Function Prescaler X1 Main Clockt System ock to Clock Prescaler Peripheral X2 Osicillator Hardware fx fx 22 23 5 Standby Wait CPU Clock Control Control fceu Circuit Circuit INTPO Sampling Clock 78011 780128 78013 78014 5 3 TIMER EVENT COUNTER The following five channels are incorporated in the timer event counter 16 bit timer event counter 8 bit timer event counter Watch timer Watchdog timer Type 1 channel 2 channels 1 channel 1 Table 5 2 Types Features of Timer Event Counter Interval timer 16 bit Timer Event Counter 1 channel 8 bit Timer Event Counter 2 channels Watch Timer 1 Watchdog Timer 1 channel Externanal event counter 1 channel 2 channels Functions Timer output 1 output 2 outputs PWM output 1 output Pulse width mesurement 1 input Sqare wave output 1 output 2 outputs Interrupt request 2 2 19 uPD78011B 780128 78013 78014 Fig 5 2 16 bit Timer Enent Counter Block Diagram Intemal Bus 16 Bit Compare Register CROO e e gt INTTMO PWM Pulse Output Output Control 0 Control Circuit 52 Circuit 16 Bit Timer fx 2 Select
41. d as shown below Non maskable interrupt 1 Maskable interrupt 12 Software interrupt amp od Table 6 1 Interrupt Source List Interrupt Source Interrupt Type Default Priority 1 Trigger Non maskable Watchdog timer overflow with non maskable interrupt selected Maskable INTWDT Watchdog timer overflow with interval timer selected Internal External Internal Vector Table Address Basic 2 Configuratin Type INTPO Pin input edge detection INTP1 INTP2 INTP3 External INTCSIO Serial interface channel 0 transfer end 511 Serial interface channel 1 transfer INTTM3 Reference time interval signal from watch timer INTTMO 16 bit timer event counter match signal generation 8 bit timer event counter 1 match signal generation 8 bit timer event counter 2 match signal generation A D converter conversion end Internal Software BRK instruction execution Internal 1 The default pririty is the priority applicable when more than one maskable interrupt is generated 0 is the highest priority and 11 the lowest 2 Basic configuration types A to E correspond to A to E on the next page 78011 780128 78013 78014 Fig 6 1 Basic Interrupt Function Configuration 1 2 A Internal Non Maskable Interrupt Intemal Bus Vector Table Address Generator
42. e Test input flag KRIF is set to 1 by falling edge detection P50 to P57 Input output ports Input output can be specified bit wise When used as an input port pull up resistor can be used by software LED can be driven directly P60 to P63 N ch open drain input output port Input output can be specified bit wise On chip pull up resistor can be specified by mask option LED can be driven directly P64 to P67 Input output ports Input output can be specified bit wise When used as an input port pull up resistor can be used by software Caution When pull up resistors are not used specified by mask option low level input leak current increases with 200 mA MAX under either of the following conditions 1 When the extemal device expansion function is used and a low level is input to the pin 2 During the 3 clock period when a read instruction is executed on port 6 and the port mode register PM6 17 78011 780128 78013 78014 52 There two types of clock generator main system clock and subsystem clock The instruction exection time can be changed 0 4us 0 8us 1 6us 3 2us 6 4us Main system clock at 10 0 MHz operation 122us Subsystem clock at 32 768 KHz operation Fig 5 1 Clock Generator Block Diagram 1 4 Subsystem fic Watch Timer Clock gt Clock Output Osi
43. e of Each Pin 1 2 Input output Circuit Recommended Connection when Not Used POO INTPO TIO Input Connected to Vss PO1 INTP1 Input output Input Connected to Vss PO2 INTP2 Output Leave open PO3 INTP3 4 1 Input Connected to Vss P10 ANIO to P17 ANI7 Input output Input Connected to or Vss Output Leave open 20 511 Input output Input Connected to or Vss 21 501 Output Leave open P22 SCK1 P23 STB P24 BUSY 25 510 580 26 5 0 581 27 5 Input output Connected to Vpp Vss P31 TO1 Leave open P32 TO2 P33 TI1 12 P35 PCL P36 BUZ P37 P40 ADO to P47 AD7 Input output Input Connected to Vpp Vss Output Leave open P50 A8 to P57 A15 Input output Input Connected to Vss P60 to P63 Output Leave open P64 RD P65 WR P66 WAIT P67 ASTB 78011 780128 78013 78014 Table 3 1 Input Output Circuit of Each Pin 2 2 Input Output a Recommended Connection when Not Used Circuit Type Pin Name Leave open Connected to Vss Connected to VDD Connected to Vss Connected to Vss directly 78011 780128 78013 78014 Fig 3 1 Pin Input Output Circuits pullup enable open drain output disable Vo
44. ise etc hence causing malfunction CMOS devices behave differently than Bipolaror NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if itis considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function 73 78011 780128 78013 78014 No part of this document may be copied reproduced form or means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arisi
45. k The STOP instruction cannot be used Caution When the main system clock is stopped and the system is operated by the subsystem clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program 9 RESET FUNCTIONS There are the following two reset methods External reset input by RESET pin Internal reset by watchdog timer runaway time detection 78011 780128 78013 78014 10 INSTRUCTION SET 1 8 Bit Instruction MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC RORA ROL4 PUSH POP DBNZ 2nd Operand HL4byte 16 HL B adder16 1st AC ri sfr sadder ladder16 PSW DE HL HL byte HL4C X G Except 31 uPD78011B 780128 78013 78014 2 16 Bit Instruction MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand 16 1st Operand rp INCW DECW PUSH POP sfrp sadderp adder16 SP Only when DE HL 3 Bit Manipulation Instruction MOV1 AND XOR1 SET1 CLR1 NOTI BF BTCLR 2nd Operand sfr bit saddr bit PWS bit HL bit addr16 1st Operand saddr bit PSW bit HL bi
46. lowing conditions 1 When the extemal device expansion function is used and a low level is input to the pin 2 During the 3 clock period when a read instruction is executed on port 6 P6 and the port mode register 3 2 OTHER PORTS 1 2 Dual Function Pin POO TIO Pin Name Function After Reset External interrupt input by which the effective edge rising edge falling edge or both rising edge and falling edge can be 1 specified 2 Falling edge detection external interrupt input Input Serial interface serial data input P25 SBO P20 Output Serial interface serial data output P26 SB1 P21 Input Serial interface serial data input output P25 SIO output P26 SO0 Input Serial interface serial clock input output P27 output P22 Output Serial interface automatic transmit receive strobe output P23 Input Serial interface automatic transmit receive busy input P24 1 78011 780128 78013 78014 3 2 OTHER PORTS 2 2 Pin Name Function External count clock input to 16 bit timer TM 0 External count clock input to 8 bit timer TM 1 External count clock input to 8 bit timer TM 2 After Reset Dual Function Pin POO INTPO 01 2 16 bit timer output shared as 14 bit PWM output 8 bit timer output P32 PCL Output Clock output for main system clock su
47. ng from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others The devices listed in this document are not suitable for use in aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to use NEC devices for above applications or they intend to use Standard quality grade NEC devices for applications not intended by NEC please contact our sales people in advance Application examples recommended by NEC Corporation Standard Computer Office equipment Communication equipment Test and Measurement equipment Machine tools Industrial robots Audio and Visual equipment Other consumer products etc Special Automotive Transportation equipment Traffic control systems Antidisastersystems Anticrime systems etc M4 92 6 FIP is a registered trademark of NEC Corporation IEBus is a trademark of NEC Corporation MS DOS and Windows are trademarks of Microsoft Corporation PC AT and PC DOS are trademarks of IBM Corporation HP9000 Series 300 HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a tradmark of SPARC International Inc SunOS is a tradmark of Sun Microsystems Inc
48. or Devices IEI 620 IEI 1209 Semiconductor Devices Quality Guarantee Guide MEI 603 1202 Caution contents of the above related documents subject to change without notice The latest documents should be used for design etc 78011 780128 78013 78014 NOTES FOR CMOS DEVICES OD PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environ mental control must be adequate When itis dry humidifier should be used Itis recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to no
49. plication Telephone VCR audio camera home appliances etc The information in this document is subject to change without notice Document IC 3179D O D No 8201 Date Published 1995 Printed in J NEC Corporation 1992 The mark shows major revised points uPD78011B 780128 78013 78014 ORDERING INFORMATION Ordering Code Package Quality Grade 78011 64 plastic shrink DIP 750 mil Standard 78011 8 64 plastic QFP 14 mm Standard 78012 64 plastic shrink DIP 750 mil Standard 78012 8 64 plastic QFP 14 mm Standard uPD78013CW xxx 64 pin plastic shrink DIP 750 mil Standard 78013 8 64 plastic QFP 114 mm Standard uPD78014CW xxx 64 pin plastic shrink DIP 750 mil Standard 78014 8 64 plastic QFP 114 mm Standard Remarks indicates ROM code Please refer to Quality grade on NEC Semiconductor Devices Document number 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 78 0 SERIES DEVELOPMENT 78078 SubSeries Products in Volume Production ea 2 g ESF SSS E L1 PD78064 SubSeries 100 pin package 1 7 Products under Development 8 bit timer event counter See ee ee ee
50. port pull up resistor can be used by software TOO TO1 TO2 TI TI2 PCL BUZ P40 to P47 Port 4 8 bit input output port Input output can be specified in 8 bit unit When used as an input port pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection ADO to AD7 1 When using the P04 XT1 pins as an input port set 1 to bit 6 REC of the processor control register Do not use the on chip feedback register of the subsystem clock oscillator 2 When using the P10 ANIO to P17 ANI7 pins as the A D converter analog input pull up resistor is auto matically unused uPD78011B 780128 78013 78014 3 1 PORT PINS 2 2 Dual Function Pin Pin Name Function After Reset P50 to P57 Port 5 A8 to 15 8 bit input output port LED can be driven directly Input output can be specified bit wise When used as an input port pull up resistor can be used by software Port 6 N ch open drain input output port 8 bit input output port On chip pull up resistor can be Input output can be specified specified by mask option bit wise LED can be driven directly When used as an input port pull up resistor can be used by software Caution When pull up resistors are not used specified by mask option the low level input leak current increases with 200 vA MAX under either of the fol
51. scillation 4 5 to 6 0 V stabilization time 2 External XT1 input clock frequency XT1 input high low level width txTH txt 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after Von reaches oscillator voltage MIN Caution 1 When using the subsystem clock oscillator wiring the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillator capacitor ground should be the same as Vss Do not ground wiring to a ground pattem in which a high current flows Do not fetch a signal from the oscillator 2 The subsystem clock oscillation circuit is a circuit with a low amplification level more prone to misoperation due to noise than the main system clock Particular care is therefore required with the wiring method when the subsystem clock is used uPD78011B 780128 78013 78014 Recommended Oscillation Circuit Constant Main system clock Ceramic resonator Ta 40 to 85 C uPD78011B 780128 Manufacture Murata Mfg Co Ltd Product Name CSB1000 Frequency MHz 1 00 Recommended Circuit Constant
52. stal Oscillator resonator frequency fx 1 Oscillation Von 4 5 to 6 0 V stabilization time 2 External X1 input clock frequency fx 1 X1 input HPD74HCU04 high low level width txL 1 Indicates only oscillation circuit characteristics Refer to Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Caution 1 When using the main system clock oscillator wirinin the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillator capacitor groundshould be the same as Vss Do not ground wiring to a ground pattem in which a high current flows Do not fetch a signal from the oscillator 2 When the main system clock is stopped and the system is operated by the subsystem clock the subsystem clock should be switched again to the main system clock afterthe oscillation stabilization time is secured by the program 35 uPD78011B 780128 78013 78014 Subsystem Clock Oscillation Circuit Characteristics 40 to 85 C 2 7 to 6 0 V Resonator Gelee Parameter Test Conditions Circuit Crystal Oscillator resonator frequency fxr 1 O
53. t uPD78011B 780128 78013 78014 4 Call Instruction Branch Instruction CALL CALLF CALLT BR BC BNC BZ BT DBNZ 2nd Operand 1st Operand Basic instruction 16 CALL 1 addr5 BZ BNZ Compound instruction 5 Other Instruction BT BF BTCLR DBNZ BA BS BRK RET RETB SEL NOP El DI HALT STOP 78011 780128 78013 78014 11 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 25 C Parameter Test Conditions Supply voltage 0 3 to 7 0 0 3 to 0 3 0 3 to 0 3 0 3 to 0 3 Input voltage to P04 P10 to P17 P20 to P27 P30 toP37 toP47 P50 to P57 P64 to P67 X1 X2 XT2 0 3 to 0 3 to P67 Open drain 0 3 to 16 Output voltage 0 3 to 0 3 Analog input P10 to P17 Analog input pin AVss 0 3 to AVREF 0 3 voltage Output 1 pin 10 current high P10 to P17 P20 to P27 P30 to P37 total 15 1 to P40 to P47 P50 to P57 P60 to P67 total 15 Output Peak value 30 1 pin current low Effective va 15 P40 to P47 P50 to P55 total Peak value Effective va to P56 P57 Peak value to P67 total Effective va 70 to Peak value 50 to P67 total Effective
54. va 20 to P17 P20 to P27 P30 to P37 Peak value 50 Effective va 20 Operating 40 to 485 temperature Storage temperature 65 to 150 Effective value should be calculated as follows Effective value Peak value x duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily That is the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded 78011 780128 78013 78014 Capacitance Ta 25 Vss 20V Parameter Test Conditions Input capacitance f 1 MHz Unmeasured pins returned to 0 V capacitance 1 to P10 to P17 f 1 MHz Unmeasured P20 to P27 P30 toP37 pins returned to 0 V P40 toP47 P50 to P57 P64 to P67 P60 to P63 Remarks The characteristics of a dual function pin and a port pin are the same unless specified otherwise Main System Clock Oscillation Circuit Characteristics 40 to 85 C Vpp 2 7 to 6 0 Recommended iri Test Conditions Resonator Circuit Parameter Ceramic Oscillator Vpp Oscillator resonator frequency fx 1 voltage range Oscillation After Vpp reaches oscil stabilization time 2 lator voltage range MIN Cry
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