KAI-1003 Imager Board User`s Manual
Contents
1. lt lt lt H2A clock lt x re a eS lt Y vise lt lt 0 1 2 4 a Fast Dump clock lt V3RD E oo 0 1 24 m GN V1 Clock 3d level Semiconductor Components Industries LLC 2014 September 2014 Rev 2 0 1 2 4 ov Electronic Shutter Publication Order Number EVBUM2269 D EVBUM2269 D KAI 1003 IMAGER BOARD ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the KAI 1003 Imager board Refer to Figure 1 Power Filtering and Regulation Power is supplied to the Imager Board via the J3 interface connector The power supplies are de coupled and filtered with ferrite beads and capacitors to suppress noise Voltage regulators are used to create the 15 V and 15 V supplies from the VPLUS and VMINUS supplies LVDS Receivers TTL Buffers LVDS timing signals are input to the Imager Board via the J3 interface connector These signals are shifted to TTL levels before being sent to the CCD clock drivers CCD Pixel Rate Clock Drivers H1 H2 amp Reset Clocks The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL level input clock signals to the voltage levels required by the CCD The low and high levels of the reset CCD clock are set by potentiometers Please note that the silkscreen text has been removed near H1A H2A and H2B as it was incorrect The silkscreen for the Test Points is cor2. 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 eee Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2269 D
3. 0 Output Amplifier Return VSS aa ae Output Gate VOG Reset Drain VRD 11 0 Ground P Well GND lt 2 2 lt Substrate Disable ESD Protection Output Amplifier Load Gate V Clock Voltages Table 5 were correct at the time of this document s The following clock voltage levels are fixed or adjusted publication but may be subject to change refer to the with a potentiometer as noted The nominal values listed in KAI 1003 device specification Table 5 CLOCK VOLTAGES Horizontal CCD Clocks Hxx CCD Low 6 0 5 5 ov Vertical CCD Clock V1 V1i CCD Low 90 8 5 8 0 ESE lt lt lt lt Vertical CCD Clock V2 V2_CCD Low iji oj alo e S 2 olo M lt Reset Clock RESET CCD Low EM TBS 5 0 Electronic Shutter Pulse VES CCD Ea 40 45 http onsemi com 3 J2 SMB LINE LINE lt q EMITTER q EMITTER __p O DRIVER FOLLOWER FOLLOWER DRIVER V tional VOUT B VOUTA Optional CHANNEL 2 CHANNEL 1 RCLK RCLK m Vl r DRIVER 1SHOT DRIVER CCD SENSOR L DRIVER KC VESCKT 4 4 EVBUM2269 D BLOCK DIAGRAM AND PERFORMANCE DATA V3RD DRIVER H1A H2A H1B H2B DRIVER DRIVER DRIVER DRIVER i tf LVDS BUFFERS 15V REGULATOR 15V AA AAA A LVDS RECEIVERS AA AAA
4. A REGULATOR J3 BOARD INTERFACE CONNECTOR Figure 1 KAI 1003 Imager Board Block Diagram 100000 10000 LINEARITY 1000 100 10 SIGNAL MEAN ELECTRONS 0 1 MEASURED FIT DEVIATION FROM FIT 0 01 0 01 0 1 1 10 INTEGRATION TIME SECONDS Figure 2 Measured Performance Linearity http onsemi com 4 n SMB Noise A D counts EVBUM2269 D Photon Transfer 3 Slope el Adu 39 18 electrons 100 Noise floor 1 61 counts 63 1 electrons LVSAT 135680 electrons VSAT 156015 electrons E 1 10 100 1000 10000 100000 1000000 Signal Mean Electrons Figure 3 Measured Performance Dynamic Range and Noise Floor http onsemi com 5 EVBUM2269 D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J1 and J2 The emitter follower buffered CCD_VOUT signals are 75 Q should be used to connect the imager board to the driven from the Imager Board via the SMB connectors J1 Timing Generator Board to match the series and terminating and J2 Coaxial cable with a characteristic impedance of resistors used on these boards Table 6 J4 INTERFACE CONNECTOR PIN AS
5. EVBUM2269 D KAI 1003 Imager Board User s Manual KAI 1003 Imager Evaluation Board Description The KAI 1003 Imager Evaluation Board referred to in this document as the Imager Board is designed to be used as part of a two board set used in conjunction with a Timing Generator Board ON Semiconductor offers an Imager Board Timing Generator Board package that has been designed and configured to operate with the KAI 1003 Image Sensor The Timing Generator Board generates the timing signals necessary to operate the CCD and provides the power required by the Imager Board The timing signals in LVDS format and the power are provided to the Imager Board via the interface connector J3 In addition the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL The KAI 1003 Imager Board has been designed to operate the KAI 1003 with the specified performance at 20MHz pixel clocking rate and nominal operating conditions See the KAI 1003 performance specification for details For testing and calibration purposes the KAI 1003 Imager board provides the ability to adjust the CCD substrate bias voltages and Reset Low CCD clock level voltage by adjusting potentiometers on the board IMAGER BOARD INPUT REQUIREMENTS Table 1 POWER REQUIREMENTS Table 2 SIGNAL LEVEL REQUIREMENTS H1A clock H1B clock
6. MINUS supplies onto the Substrate voltage This creates the necessary potential to clear all charge from the photodiodes thereby acting as an electronic shutter to control exposure CCD Bias Voltages All CCD bias voltages are fixed on the KAI 1003 Imager Board except VSUB which can be set by a potentiometer CCD Image Sensor This evaluation board supports the KAI 1003 Image Sensor Emitter Follower The VOUT CCD signals are buffered using bipolar junction transistors in an emitter follower configuration that also provides the necessary 5 mA current sink for the CCD output circuits Line Drivers The buffered VOUT CCD signals are AC coupled and driven from the Imager Board by operational amplifiers in a non inverting configuration The operational amplifiers are configured to have a gain of 1 25 to correctly drive 75 Q video coaxial cabling from the SMB connectors http onsemi com 2 EVBUM2269 D KAI 1003 OPERATIONAL SETTINGS The Imager board is configured to operate the KAI 1003 were correct at the time of this document s publication but CCD image sensor under the following operating may be subject to change refer to the KAI 1003 device conditions specification Bias Voltages The following voltages are fixed or adjusted with a potentiometer as noted The nominal values listed in Table 4 Table 4 BIAS VOLTAGES C Deenpton f smeo mn Nam wax uns Poemon Output Amplifier Supply VDD 12 0 15 0 15
7. SIGNMENTS Pin Signal Pin Signal 1 N C N C AGND V3RD 11 13 s 7 19 21 23 VES AGND AGND ooo 25 27 29 31 V2 1 R V AGND AGND 2 jme ea m 26 28 30 32 56 58 60 62 64 BENE ANN pl por ord AGND H2A AGND 3 5 7 9 1 en 51 53 a 3 3 3 3 4 4 4 4 4 55 N C 57 AGND 59 N C 61 5 V_MTR VMINUS_MTR C N AGND N C 5 V MTR 63 N AGND N N N C C 5 V MTR C C C AGND VPLUS MTR N VPLUS MTR C 65 67 C n E 75 C 77 3 9 C 7 http onsemi com 6 EVBUM2269 D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer Please address all inquiries and purchase orders to damage to the Imager Board or Imager Board electronics The customer assumes responsibility and care must be taken Truesense Imaging Inc when probing modifying or integrating the 1964 Lake Avenue ON Semiconductor Evaluation Board Kits Rochester New York 14615 Phone 585 784 5500 When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of an Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semicond
8. hnical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone
9. rect and may be used to probe the pixel rate clocks as shown in Table 3 Table 3 PIXEL RATE CLOCK TEST POINT LOCATIONS Testpoint Pixel Rate Clock TP8 H2A CCD TP10 H1B CCD TP12 H2B CCD TP13 H1A CCD Reset Clock One Shot U9 not populated The pulse width of the RESET CCD clock used to be set by a programmable One Shot It was configured to provide a pulse width from 5 ns to 15 ns Now the pulse width control functionality is provided by the KSC 1000 based Timing Generator Board and the one shot has been bypassed by removing U9 and inserting a shorting resistor on pads 1 and 2 of U9 CCD VCLK Drivers The vertical clock VCLK drivers consist of MOSFET driver IC s These drivers are designed to translate the TTL level clock signals to the voltage levels required by the CCD The current sources for these voltage levels are high current up to 600 mA transistors The V2 CCD high level clock voltage is switched from V MID to V HIGH once per frame to transfer the charge from the photodiodes to the vertical CCDs CCD FDG Driver The KAI 1003 does not use a Fast Dump Gate FDG circuit The FDG signal is located on the interface connector but is not connected beyond the TTL buffer IC VES Circuit The quiescent CCD substrate voltage VSUB is set by a potentiometer For electronic shutter operation the VES signal drives a transistor amplifier circuit that AC couples the voltage difference between the VPLUS and V
10. uctor can only support firmware developed by and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer E mail info truesenseimaging com ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate ON Semiconductor and the ON are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s tec
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