the user manual for the OPTO32C
Contents
1. 2 3 3 2 J9 Channels 00 07 GND Jumper J9 controls grounding of the Channel HI Pins for input Channels 00 through 07 Jumper Absent is for normal OPTO Isolator Operation Jumper Present is for 12V CONTACT operation ONLY Rin and Rin OPT MUST be removed before the jumper is installed Figure 7 Jumper J9 INCHOOHI 1 pe 2 Gnd WOH DH 3 Jee 4 Gnd INCHO2HI 5 79 6 Gnd INCHO3H 7 C 8 Gnd INCHO4HI 9 9 9 10 Gnd INCHO5HI 11 mei 12 Gnd IN CHO6 HI 13 CO 14 Gnd IN CHO7HI 15 eil 16 Gnd J9 User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 19 2 3 3 3 J10 Channels 08 15 GND Jumper J10 controls grounding of the Channel HI Pins for input Channels 08 through 15 Jumper Absent is for normal OPTO Isolator Operation Jumper Present is for 12V CONTACT operation ONLY Rin MUST be removed before the jumper is installed Figure 8 Jumper J10 INCHOBHI 1 mei 2 Gnd INCHOOH 3 C O 4 Gnd INCH10HI 5 C 6 Gnd INCH11H 7 C 8 Gnd INCH12HI 9 S 10 Gnd INCH 13HI 11 ei 12 Gnd INCH14HI 13 C O 14 Gnd IN CH15HI 15 G 16 Gnd J10 2 3 3 4 JLI Channels 16 23 GND Jumper J11 controls grounding of the Channel HI Pins for input Channels 16 through 23 Jumper Absent is for normal OPTO Isolator Operation Jumper Present is for 12V CONTACT operation ONLY Rin MUST be removed be2. 2 31 0 Test Register 2 Can be used for anything User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 26 4 PEX 8311 Notes The PCIe OPTO32C uses the PLX Technologies PEX8311AA Interface chip In the System Devices list this chip will show up as 2 devices a 8311 PCIe to PCI bridge and a 9056 PCI to local bus adapter 4 1 Initialization When the PEX8311 is reset the 9056 part of the chip will initialize itself from an on board serial EEPROM that is programmed at General Standards A brief description of some of the Registers follows Table 4 17 EEPROM Register Initialization Eeprom Addr PCI Addr Description Value After Reset 0x10 Ox7c Mailbox 1 0x80010000 Standard 0x80010001 Contact 0x80010002 8x28v Oxl4 Space 0 range PCI to Local OxffffffSO xl Space 0 Base Address remap 0x00000001 A list of the full EEPROM contents is located in Appendix B 4 1 1 Device ID Vendor ID Device ID and Vendor ID are used to identify the PLX Device during configuration cycles Table 4 18 Device ID Vendor ID Register Description Field Description Value After Reset After Reset 15 00 Vendor ID Identifies the manufacturer of the device Defaults to the PCI Ox10B5 SIG issued vendor ID of PLX 31 16 Device ID Identifies the particular device Defaults to the PLX part number 0x9056 for
3. Basic Clock Counter will always divide by 4 200 Ns Values of 0x0000 or 0x0001 will not alter this When the clock divider is loaded with a larger value then the clock division will be count 2 2 The Total debounce time will be 3 X clock division time For Example for a 15ms debounce time Clock period should be Sms 5ms 50 Ns 100000 2 99998 99998 2 49999 0x0c34f Hex User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 25 3 2 9 Output Data Register Board Offset 0x01c 8 bits Read Write Reset to Zero The 8 bit output data register Reset to All Zero s Writing a 1 to a bit will make that opto output conductive and current will flow from HT to LO Writing a 0 will turn the opto off and the output will be Non Conductive from HT to LO Table 3 14 Output Data Register 07 00 Output Data Register Controls the Opto Isolated Outputs Reserved Undefined 3 2 10 Test Register 1 32 Bits Read Write Reset to Zero 32 bit Register does not do anything It was added to test 8 16 and 32 Bit Reads and Writes Table 3 15 Test Register 1 Description Test Register 1 Can be used for anything 3 2 11 Test Register 2 32 Bits Read Write Reset to Zero 32 bit Register does not do anything It was added to test 8 16 and 32 Bit Reads and Writes Table 3 16 Test Register
4. Clock New for the PCle OPTO32C ooo User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 22 3 22 Board Control Register Board Offset 0x00 8 Bits write only Table 3 7 Board Control Register NOTE Bits 0 4 are self clearing pulses that are written as a 1 to clear the interrupt source The bits will then self clear so that another host operation is not required NOTE The Clear COS Bytes or the Master Clear bit 4 will clear ANY COS register bit that is set regardless of the bits Interrupt Enable Status For Individual COS bit clearing Write a 1 to the COS bit you wish to clear Event Overflow status will only be cleared by Clear Event Overflow or by Master Clear Bit 4 Loading the Event Counter WILL NOT clear out the event overflow status 3 2 3 Received Data Register Board Offset 0x04 24 bits Debounced Receive data bits 0 23 Read ONLY The Input Data Bits After they have been Debounced Table 3 8 Received Data Register 23 00 Debounced Receive Data bits 0 23 Read ONLY The Debounced Input Data Bits 31 24 Reserved Undefined User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 23 3 2 4 Change of State Register Board Offset 0x08 24 bits Change of State Detected Polari
5. OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 10 1 2 Card Features 24 optically isolated inputs e Selectable input voltage range thru use of field replaceable bias resistors e Industry Standard 8 Pin Sip Resistors 770 83 Rxx Series 8 optically isolated outputs 4 normal 4 Diode Clamped Software Programmable clock debounce rate Software Programmable Change of State detection Rising edge or falling edge per input channel Software Programmable Interrupts on any or all Change of State bit s Software Pre loadable Event counter on Input Bit 23 Programmable Interrupt on Event Counter Overflow Built in Self Test Features e Registers are Read Write e Ability to monitor the Debounce Clock The board uses the PEX 8311 PCIe single lane interface chip to provide the advanced features of the PCIe interface environment These features include Programmable Little Endian Big Endian swapping PCle cycles Asynchronous to local bus cycles Software Programmable board base address The PCIe OPTO32C offers the same operating modes as the PCI OPTO32B These include Standard OPTO32 Operation same as the PCI OPTO32B and the PMC OPTO32A 12V Contact and 12V CONTACT 8x28V Operation same at the PCI OPTO32B Same Cable Pin out as the PCI OPTO32B Optional Higher current resistors on channels 0 7 Jumpers for Grounding connector pins in the CONTACT c
6. PCI interface chip User Manual for the PCle OPTO32C 12V CONTACT Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 27 4 1 2 Sub System ID Vendor ID Sub System ID and Vendor ID are used to identify the PCIe OPTO32C during configuration cycles Table 4 19 Sub System ID and Vendor ID Register Description Value After Reset 15 00 Vendor ID Identifies the manufacturer of the device Defaults to the PCI 0x10B5 SIG issued vendor ID of PLX 31 16 Sub System ID Identifies the particular device Sub System ID Assigned to 0x3471 the OPTO32C by PLX 4 1 3 Class Code Revision When loaded from the EE Prom this register will identify the device Base Class Code Sub Class Code and Revision of the PLX Device PLX Revision is hard coded in the device Table 4 20 Class Code Revision Register 4 1 4 Mailbox 0 When loaded from the EE Prom this mailbox is used to contain values to identify the PLD revision and EE Prom Revision levels of this board Table 4 21 Mailbox 0 Value After Reset 15 00 PLD Revision Level Revision Level of the FPGA on the OPTO32C 0x0001 Currently 0x0001 Rev 0 NR 31 16 EE Prom Revision Level Revision Level of the PLX EEPROM contents 0x0001 Currently 0x0001 Rev 0 NR User Manual for the PCle OPTO32C 12V CONTACT Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Hun
7. Ge Ge Ge Ge Gee 24 Table E dE 25 Table 3 13 Clock Division Reeister esse esse ses ee es de es N Ged Die ke ed so seo a de NUS 25 Table 3 14 Output Data Register eese eese eerie RegS KEER ES be de ek ee Ge ER NEE ede de ig 26 Table 3 15 Test Register di esse ie Nee e ee de n eii ona no eiae 26 Table 3 16 Test Repister 2e ese e ee Ge AG Re oe we de DS Dk gs 26 Table 4 17 EEPROM Register Initialization see esse ee see see ee ee Gee Ge tnn Ge ee tna 27 Table 4 18 Device ID Vendor ID Register Description e esse Ge ee eene Ge Gee 27 Table 4 19 Sub System ID and Vendor ID Register Description eee eee eerte nne 28 Table 4 20 Class Code Revision Register sesse sesse sesse ee e eee ee eene Ge netten Ge Ge Gee Gee 28 Table 4 21 Mailbox Ds ede etti ee tede idea ehe etian edu DUE M Uri eR EN Pe du 28 Table 4 22 Mailbox tos ET OAR EG 29 Table 4 23 Space 0 Range PCI to Local eee esse sesse sesse ee ee Ge Ge enne enne esee Ge Gee ee 29 Table 4 24 Address Space 0 Base Address Renrdp ssccecrcssesscssssscssscccssssccsssccsscssssscssescesoes 29 Table B 25 PLX EEPROM E 32 User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 SECTION 1 1 Introduction The PCIe OPTO32C board is a high performance Single Lane PCI Express card offering 24 Opto Isolated inputs and 8 Opto Isolated o
8. O32C is available in 3 different configurations e Asa Standard OPTO32 Board with 24 input Channels e Asa OPTO32C I2V CONTACT which is designed to sense contact closures on all 24 inputs The high side of the Opto Isolator is connected to 12V through a Current Limiting Resistor See the PCIe OPTO32C 12V CONTACT Manual e Asa OPTO32C 12V CONTACT 8x28V which has channels 0 through 7 configured as standard OPTO Inputs and channels 8 through 23 are configured to sense contact closures See the PCIe OPTO32C 12V CONTACT Manual 2 3 1 Standard OPTO32 Input Configuration Selectable input voltage range thru use of field replaceable bias resistors labeled RIN using standard 8 pin SIP isolation resistors These bias resistor packages are socketed for easy replacement One bias resistor package will affect the input channels on nibble boundaries as follows Table 2 2 Input Channels Bias Resistors Locations IN CH12 thru IN CHI5 IN CH16 thru IN CHI9 IN CH20 thru IN CH23 Current Limiting Resistor Values should be chosen to provide a Minimum input current of 2 3 mA Typical resistor values for input voltage levels are as follows Table 2 3 Input Channels Bias Resistor Values The PCIe OPTO32C also has the Option of an additional input resistor in parallel with the Standard Resistor for channels INOO through INO7 ONLY This additional resistor is provided for higher current applications Maximum rated Input Current is 80ma Table 2 4 Additi
9. PCle OPTO32C User s Manual 24 Input Bits 8 Output Bits Opto lsolator Board General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail support generalstandards com Preliminary User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 PREFACE General Standards Corporation Copyright C 2011 General Standards Corp Additional copies of this manual or other literature may be obtained from General Standards Corporation 8302A Whitesburg Dr Huntsville Alabama 35802 Tele 256 880 8787 FAX 256 880 8788 E mail support generalstandards com The information in this document is subject to change without notice General Standards Corp makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corp assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this d
10. R Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 17 2 3 2 2 Diode Clamped Outputs Bits 4 7 Isolation Voltage 5000 V VCEO Max 60 V Maximum Current 100 ma Typical Ton Toff 3 5 uSec Figure 5 Diode Clamped Outputs Bits 4 7 VEE SIP 470 DTA OUTS gt PS2501 4 User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 lt _ PWR OUT CLAMP 6 MUR120 SAZBA lt ___ PWR OUT CHE HI MPSADS c PWR OUT CH6 LO 18 2 3 3 Jumpers The PCIe OPTO32C board contains jumpers to support System Configuration and Troubleshooting The PCIe OPTO32C also contains jumpers to provide Ground pins to the connector as the return path for the 12V when the board is used in the PCIe OPTO32C 12V CONTACT configuration These jumpers will NEVER be installed for operation as Standard Opto Isolated inputs Rin and Rin OPT MUST ALWAYS be removed for the jumpers and Rcon 12V are installed 2 3 3 1 J6 PLX and FPGA Support Jumper J6 is provided for Factory Troubleshooting and Support of the PLX Interface Chip and the FPGA on the board All 4 Jumpers should always be installed for proper board operation Figure 6 Jumper J6 PLX EEDIO 1 2 PROM EEDIO PLX RESET 3 97 4 LOC RESET FPGA CSO 5 L ei 6 EP CSO FGA ASDO 7 9 8 EP ASDO
11. al Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 29 Appendix A INTERRUPTS For Interrupt Operation the Desired Interrupts are Enabled on the Opto isolator board AND Interrupts MUST be enabled At Thru the PLX Interface chip To enable Event Counter Overflow Interrupts Bit 6 of the Board Control Register must be set to a 1 outportb Opto register base address 0x00 Oxc0 Byte write Turn LED off Enable Event Overflow Interrupt outportl Opto_register_base_address OxOc OxOfffe Long word write Event Counter 2 The Second Rising Edge detected will generate the Interrupt To Enable COS Interrupts Any All Desired COS Interrupt bit s are enabled thru the COS Interrupt Enable Register outportl Opto register base address 0x010 0x08421 Long word write Offset 0x010 Enable Interrupts on COS Bit s 0 5 10 and 15 All other Machine dependent actions should be taken before the final steps in the process Make ABSOLUTELY sure that there is NO Pending status laying around that is already setting an interrupt action Either use the master clear s outportb Opto register base address 0x00 Oxdf Byte write Turn LED off Enable Event Overflow Interrupt Master Clear All COS and Clear the Event Counter overflow NOTE NOTE NOTE NOTE The Master Clear will Clear ALL COS Bits The Byte Clear s will ALSO Clear ALL COS Bits in that Byt
12. ame Cable Pinout as the PCI OPTO32B For Other Configurations see the See the PCIe OPTO32C 12V CONTACT Manual The following table lists the cable pin out for the standard 24 input board Table 2 1 Input Output Cable Pin Assignments PIN NUMBER SIGNAL IN CHOO HI IN CH00 LO IN CH01 HI IN CH01 LO IN CH02 HI IN CH02 LO IN CH03 HI IN CH03 LO IN CH04 HI IN CH04 LO IN CH05 HI IN CH05 LO IN CH06 HI IN CH06 LO IN CH07 LO IN CH08 LO IN CH09 LO IN CH10 HI IN CH10 LO IN CH11 HI IN CH11 LO IN CH12 HI IN CH12 LO IN CH13 LO IN CH14 HI IN CH14 LO IN CH15 HI IN CH15 LO IN CH16 HI IN CH16 LO IN CH07 HI IN CH08 HI IN CH09 HI IN CH13 HI PIN NUMBER 60 C SIGNAL IN CH17 HI IN CH17 LO IN CH18 HI IN CH18 LO IN CH19 HI IN CH19 LO IN CH20 HI IN CH20 LO IN CH21 HI IN CH21 LO IN CH22 HI IN CH22 LO IN CH23 HI IN CH23 LO LOG OUT CHO HI LOG OUT CHO LO LOG OUT CH1 HI LOG OUT CHI LO LOG OUT CH2 HI LOG OUT CH2 LO LOG OUT CH3 HI LOG OUT CH3 LO PWR OU PWR OU PWR OU PWR OU PWR OU PWR OU PWR OU PWR OU PWR OU PWR OU PWR OU T CH4 HI T CH4 LO T CLAMP 4 T CH5 T CH5 T CLAMP 5 T CLAMP 6 T CH6 T CH6 T CLAMP 7 T CH7 HI EI SIE E t o 68 PWR OUT CH7 LO User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 13 2 3 System Configuration The PCIe OPT
13. board operations 2 3 4 3 D5 Board Fail LED Red LED D5 is under software control through the Board Control Register Section 3 2 2 Bit 7 The default is that this LED will Reset to the ON State Writing a l to Board Control Register Bit 7 will turn this LED OFF This LED is located along the top near the middle of the board between the back edge and the cable connector At Board Reset This LED will flicker OFF and then turn ON after the FPGA is configured After configuration this LED is under Software Control and may be either ON or OFF User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 21 SECTION 3 3 CONTROL SOFTWARE 3 1 Introduction 3 2 Board Register Descriptions Table 3 5 Register Address Map 3 2 1 Board Status Register Board Offset 0x00 32 Bits read only New with the PCIe OPTO32C this Register expanded to 32 Bits with Fields to Identify the Firmware Revision Level and the Board ID Bits 0 7 are the same as the PCI and PMC OPTO32 s Table 3 6 Board Status Register Bit 0 Int Byte LO Out H bits 7 0 COS interrupt status Bit 1 Int Byte MD Out H bits 15 8 COS interrupt status Bit 2 Int Byte HI Out H bits 23 16 COS interrupt status Bit 3 Rx Event Overflow H Event Overflow status Bit 4 Master Int Out Master Interrupt Status 1 Interrupt into the PLX Bit 5 Slow Debounce
14. e To Only Clear the Bit generating the Interrupt you must use the individual Clear s as Described below Or Individual Clears for the COS and Event Overflow Outportl Opto register base address 0x08 0x08421 Long word write Offset 0x08 COS register Clear COS Bit s 0 5 10 and 15 If they are set Outportb Opto register base address 0x00 Oxc8 Byte write Turn LED off Enable Event Overflow Interrupt Clear Event Overflow The final step is the write to the PLX interface that will enable it to generate Interrupts onto the PCI bus Outportl PLX io base address 0x068 0x00900 Long word write PLX interrupt control register Bit s 8 and 11 Enable Local input to generate PCI interrupts User Manual for the PCle OPTO32C 12V CONTACT Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 30 In the Interrupt Handler there is NO action required to with the PLX Interface chip The only requirement to remove the Asserted interrupt is to remove the Local source of the interrupt Which would be the COS bit or the event overflow temp inportb Opto register base address 0x00 Read the OPTO Board Status register if temp amp 0x010 0x010 Master Interrupt bit will be set in the Board Status Register if this board generated the Interrupt Status Bits 0 thru 3 could also be examined to Determine Wh
15. esse tasse tasse toss tensa tease tens sese ens asses sens E EEES 27 4 1 1 Device ID 7 Vendor ID 5 p one ERE RE iU E e RR RH LA ee 27 4 12 Sub Systein ID Vendor ID EER See Bee O Di 28 4 1 3 Class Code PREVISION t enin epe ete DEED n rtr ttd ae Pe EE 28 2 L4 Mailbox 0 nere eret m a a diee ERR eina mae Re i 28 WEE 29 4 1 6 Address Space 0 Range PCI to Local sessi 29 4 1 7 Address Space 0 Base Address Remap ea RA Re Re RA RA Re Re Re enne nnne 29 Appendix A odii 31 Appendix B PLX EEPROM Conte ntts csccssssssssscssscsssssssssssssesssessscsssssssssssscsscesssnsssssscsssessosscssssssessessssonees 33 User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Figures Figure 1 Board LG yOu se Ns ee ke a N eN GE Ge YEAR RD Se Ge N ee ee ee SG Ee 12 Figure 2 Input Channels 0 7 Typictll svicsiscccsiesssecssssseviscossavessaassedvasssusatavavatcvasssecvadonsshesevvensssnses 15 Figure 3 Input Channels 8 22 Typical scsissscsssancossarsssonestsussdecdussvesssucusacesudeveossavebuenbosssessuasseastass 16 Figure 4 Normal Outputs Bits 0 3 ccssccocasisvceseeeacdissesotbedearss
16. fore the jumper is installed Figure 9 Jumper J11 INCH16HI 1 C 2 Gnd INCH17H 3 Jee 4 Gnd INCH18HI 5 mei 6 Gnd INCH19H 7 8 Gnd INCH20H 9 10 Gnd INCH21HI 11 9 9 12 Gnd INCH22HI 13 C 9 14 Gnd INCH23HI 15 16 Gnd J11 User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 20 2 3 4 Board LED s The PCIe OPTO32C 12V CONTACT Board provides several LED s for monitoring Board Status The LED s are not required for normal board operation All LED s are located along the Top edge of the board 2 3 4 1 DI PLX PCIe Link Status Green LED D1 is connected to the GPIOO line from the PLX PCIe Interface Chip The Default Power Up function of this line is to Indicate that the PCIe bus link is Good It can also be placed under Software Control through the PLX 8311 control registers Default is that this LED is Installed and that GREEN ONT indicates that the PCIe Link is Good This LED will always be ON during normal board operations 2 3 4 2 D6 FPGA Configuration Red LED D6 will be ON when the FPGA is NOT Configured After a successful Configuration this LED will Turn OFF In Normal Operation this LED will be OFF This LED is located along the top near the back edge of the board farthest from the cable connector At Board Reset This LED will flicker ON and then turn OFF during normal
17. he PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 24 3 2 7 COS Polarity Register Board Offset 0x014 24 bits Read Write Reset to Zero When the corresponding bit is zero the COS detection for that bit will be set by a detected High to Low transition When Set to a 1 the COS detection for that bit will look for Low to High transitions Reset to all zeros Table 3 12 COS Polarity Register 23 00 COS Polarity Register 1 Low to Hi will set COS Bit 0 Hi to Low will set COS Per Bit 31 24 Reserved Undefined 3 2 8 Clock Division Register Board Offset 0x018 24 bits Read Write Reset to Zero Table 3 13 Clock Division Register 23 00 Clock Division Register Sets the Clock Division Rate 31 24 Reserved Undefined NOTE gt gt gt gt when altering this register disable all interrupts and expect unusual results in the COS Detection register A 24 Bit clock divider is provided for programmable Debounce delays The debounce circuit registers the incoming data 3 times in a daisy chain When ALL 3 registers are high the incoming data is a high When the debounced data register contains a 1 then ALL three registers must contain zero for the debounced data to transition back to a zero The clock for these holding registers is programmable thru the clock divider The Basic clock of the board is 20 MHz 50 Ns The
18. ich Byte generated the Interrupt Or if the Event Counter Overflow generated The Interrupt Finished processing Now It s time to clear the Pending Interrupt Outportl Opto register base address 0x08 0x08421 Long word write Offset 0x08 COS register Clear COS Bit s 0 5 10 and 15 If they are set Outportb Opto register base address 0x00 Oxc8 Byte write Turn LED off Enable Event Overflow Interrupt Clear Event Overflow j To Disable All Interrupt s From the OPTO board write to the PLX interface Chip Outportl PLX 1o base address 0x068 0x0000 Long word write PLX interrupt control register Clear Bit s 8 and 11 disable All PCI interrupts User Manual for the PCIe OPTO32C 12V CONTACT Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 31 Appendix B PLX EEPROM Contents The Full contents of the OPTO32C EEPROM for the 9056 portion of the interface chip are as follows Table B 25 PLX EEPROM Contents Addr Mailbox 1 User defined 0x80010000 Standard 0x80010001 Contact 0x80010002 8x28v User Manual for the PCle OPTO32C 12V CONTACT Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 32
19. ocument General Standards Corp does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corp assumes no responsibility for any consequences resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corp reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corp This user s manual provides information on the specifications theory of operation register level programming installation of the board and information required for customized hardware software development User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 RELATED PUBLICATIONS The following manuals and specifications provide the necessary information for in depth understanding of the specialized parts used on this board EIA Standard for the RS 422A Interface EIA order number EIA RS 422A PCI Local Bus Specification Revision 2 1 June 1 1995 Questions regarding the PCI specification be forwarded to PCI Special Interest Gr
20. onal Input Channels Bias Resistors Locations Input Channels IN CHOO thru IN CHO3 IN CH04 thru IN CH07 User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 14 2 3 1 1 Channels 0 7 Isolation Voltage 5000 V Current Transfer Ratio 80 600 Min Input Current 2 3 mA Max Input Current 80 mA Typical Ton Toff 3 5 uSec Input channels 00 07 can be configured in 3 different ways through the use of optional resistors RIN is used for standard OPTO32C configurations RIN OPT is used along with RIN for higher current applications Rcon 12V is only used for CONTACT applications It is NEVER used with RIN or RIN OPT It is NEVER used in 12V CONTACT 8x28V applications When configured as a 12V CONTACT 8x28V Board RIN Only is used and is a 2 7K 400mw Resistor If the 2 7K 400mw is not available then 2 x 5 6K 200mw resistors will be used in parallel and will be installed in RIN and RIN OPT When configured as a 12V CONTACT Board Rcon 12V is used and is a 1 2K Ohms 200 mw Resistor Package Figure 2 Input Channels 0 7 Typical Rcon 12V 1 2 VODH2VL i Rin Opt 770 83 RVDD ND 770 83 ROPT ND IN CH0D HUL RP24A ERAN 2 2K SMT 770 83 RGOO ND SEE RIN TABLE IN CHD LO P 2501 4 ND GND User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corp
21. onfiguration User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 11 SECTION 2 2 INSTALLATION AND MAINTENANCE 2 1 Card Configuration Figure 1 Board Layout D21 e 022 025 e 026 1 RP3 D Kj Sn Neooo9099 X 90 0 0 0 O O T wf pre RT meeeecece Ge MT ARE Heeeeeee EES Siet t e Ek SS 91 Te RI amp Kg 3 eeeseoeeeo HH sa US gis t ij s i o SS Sp a Ej RPS Caas ee le Ee HOE Let ae WAN P27 T ee gege UU Ak RE REELE IN d bunn m PP25 Em ee RP21 RP2A RP22 HEWe om BORED Ge m ooc c ee0e0 ER f E E wen oooooooe noccccc0 s5 d A mg Bim DEZ bis um s AIR riti 1 d 023 e 024 027 e 028 e EI 4 n ES ek deg gengp O I Wi WE User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 2 2 Installation 2 2 1 Physical Installation Selectable input voltage range thru use of field replaceable bias resistors using standard 8 pin SIP isolation resistors These bias resistor packages are socketed for easy replacement One bias resistor package will affect the input channels on nibble boundaries 2 2 2 Input Output Cable Connectors The PCIe OPTO32C has the Same Cable Connector and the S
22. oration 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 15 2 3 1 2 Channels 8 23 Isolation Voltage 5000 V Current Transfer Ratio 80 600 Min Input Current 2 3 mA Max Input Current 80 mA Typical Ton Toff 3 5 uSec Input channels 08 23 can be configured in 2 different ways through the use of optional resistors RIN is used for standard OPTO32C configurations Rcon 12V is only used for CONTACT applications It is NEVER used with RIN When configured as a 12V CONTACT Board Rcon 12V is used and is a 1 2K Ohms 200 mw Resistor Package Figure 3 Input Channels 8 22 Typical Rcon 12V 1 2 770 83 RVDD ND RP20A EXB 83222JV 2 2K SMT Rin weus ul gt lt IN_DTA 08 770 83 RI00GND SEE RIN TABLE IN cH08 Lol P32501 4 ND GND User Manual for the PCle OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 16 2 3 2 Opto Isolated Outputs 2 3 2 1 Normal Outputs Bits 0 3 Output Bits 0 3 contain an Optional Pullup resistor to VCC that is not normally installed Isolation Voltage 5000 V VCEO Max 60 V Maximum Current 100 ma Typical Ton Toff 3 5 uSec Figure 4 Normal Outputs Bits 0 3 VEL VEL SIP 100K ISOL OPTIONAL SIP 470 lt _ LOG OUT CHO HI MPSADS pTAQUTO PS2601 4 lt __ LOG OUT CHO LO User Manual for the PCIe OPTO32C Card Rev N
23. oup P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 PCle OPTO32C Documentation History Alterations for PCle OPTO32C Board Assembly Created from PCIe OPTO32C 12V CONTACT baseline manual Explained CONTACT configurations better Explained Resistor Values used in the CONTACT Configurations Emphasize Standard Board Configuration Added Standard Cable Pinout Table User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Contents Ty ANUP O E 10 1 1 Differences From OPTO32 Family ccsssccssssscccsccscsscseccscccsscscsescsscscsssssssesscsesssccssessccssescess 10 1 2 Card Features E MM 11 2 INSTALLATION AND MAINTENAN UQE ecce sesse sesse ee sesse ees Gees Gee RR Rees eaae eeo 12 2 1 Card Configuration or Ionio eterne tio trea de rna Se ie eie dd ee de eg de oe go eb ge Rade Rd 12 2 2 Ee NE DU OE EE OE EE OE ER EE EN N 13 2 2 Physical Installation uie eee e estt oe eee Ri m iata epe ee es e THRE 13 222 Input Output Cable Connectors herr eoe dero e EEN 13 2 3 System Configuration eee ae Ge eene neenon Ge GE Ge Ge estne sets a
24. sses ESE Ga 14 2 3 1 Standard OPTO32 Input Configuration ee ek ee Re AR AR AR Re nnne ener nnne 14 2 3 2 Opto Isolated AO De sce teste EE Gr d ee REA HE EE EGRE CERE EE dde 17 2 3 3 an 19 DS As Board UR DEE 21 SEENEN 22 KA Boni H 22 3 2 Board Register Description esse sesse sesse ee Ge eene eerte GE Ge Ge Ge Ge EG EG EG Ee 22 3 2 1 Board Status Register Board Offset OO 22 3 2 2 Board Control Register Board Offset 0x00 sess eene nnn 23 3 2 3 Received Data Register Board Offset 0x04 ee RR RA RA Re eren 23 3 2 4 Change of State Register Board Offset OO 24 3 2 5 Receive Event Counter Board Offset OxOc ese ese ese ee ee ee ee ee ee GR tnetneteeteethr enne 24 3 2 6 COS Interrupt Enable Register Board Offset Ox010 sse eene 24 3 2 7 COS Polarity Register Board Offset Os l ee ee RR Re RA Re Re Re ee enne nne 25 3 2 8 Clock Division Register Board Offset 0x018 sese enne 25 3 2 9 Output Data Register Board Offset OXxO1C ee RR RR RA Re Ge Re nennen enne enne 26 3 2 10 Test Register E GREG TO A ON e edd 26 3 2 TH Test Register 2 vas Er eb dtd tuo GbR tec oett riter tere np o ba Saad 26 4d PEX 6311 NOUS suisse pa Vet C IER UR ERR E REVISE SIRE M EVA EH B UN RUE Ee TEE E EM d 27 4 1 Initialization 1 eerie eee e e eese nete eee tentent enata setas st
25. tsville AL 35802 Phone 256 880 8787 28 4 1 5 Mailbox 1 When loaded from the EE Prom this mailbox register is used to identify the overall Board assembly level and to Identify this Assembly Table 4 22 Mailbox 1 Assembly Identifier 0x0000 Standard 0x0000 Identifies the OPTO32C base board 0x0001 Contact 0x0001 Identifies the OPTO32C 12V CONTACT 0x0002 8x28V 0x0002 Identifies the OPTO32C 12V CONTACT 8x28V For Legacy Reasons the Assembly Identifier must be 0x0000 for the base OPTO32C Board 31 16 Board Assembly Revision Level 0x8001 Currently 0x8001 Rev NR of the PCIe OPTO32C 4 1 6 Address Space 0 Range PCI to Local Size of the Address Space required for the OPTO32C The OPTO32C uses 128 Bytes of Memory Space Table 4 23 Space 0 Range PCI to Local Address Space 0 Range Zero s indicate the size in Bytes of the Address Oxffffff80 Space to be reserved for the Board Bit 0 Indicates the Board is mapped into Memory Space The OPTO32C uses 128 Bytes of Memory Space 4 1 7 Address Space 0 Base Address Remap There is no address space Remap for the Board Bit Zero indicates that Address Space 0 is Active for writing to Local Registers on the Board Table 4 24 Address Space 0 Base Address Remap Value After Reset 31 00 Address Space 0 Base Address Remap 0x01 0x00000001 Bit 0 Indicates that Address Space 0 is Active User Manual for the PCle OPTO32C 12V CONTACT Card Rev NR Manu
26. ty programmed thru COS Polarity register 0x014 If a COS bit is set then it will stay set until cleared by the host A COS bit can be cleared by writing a 1 to a COS bit that is set Writing a zero will have no effect Writing a Ito a bit that is 0 will do nothing COS bits may also be cleared by using the board control register Byte clears or using the board control master clear Table 3 9 Change of State register 23 00 Change of State Data bits 0 23 Writing a 1 will clear a bit that 1s set 31 24 Reserved Undefined 3 2 5 Receive Event Counter Board Offset 0x0c 16 bits Read Write Reset to Zero This counter may be read at any time by the host Counter will increment once for every Debounced Rising edge detected on input data bit 23 When the counter is OxOffff and increments the Rx event overflow status bit will be set and can be used to generate an interrupt Table 3 10 Receive Event Counter 31 16 Reserved Undefined 3 2 6 COS Interrupt Enable Register Board Offset 0x010 24 bits Read Write Reset to Zero Each bit will be bitwise ANDED with the COS register and all of the results OR ed together to generate an Interrupt A 1 will enable the corresponding interrupt A 0 will disable that bit from generating an interrupt Table 3 11 COS Interrupt Enable Register 23 00 COS Interrupt Enable Register 1 Enable Interrupt for that corresponding COS bit 31 24 Reserved Undefined User Manual for t
27. uesivvsasesudasssuessnonbaducta deietesuevussvivbusaievs 17 Figure 5 Diode Clamped Outputs Bits 4 7 sesse sesse ee EG EG seen Ge Ge GE EE l Figure be E 19 Figure T E 19 Figure 8 J mper ELE EE OE EE EE ee 20 FUSED suier JI EE 20 User Manual for the PCIe OPTO32C Card Rev NR Manual Rev NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Tables Table 2 1 Input Output Cable Pin ASsigniments cscccccocccesscsscsscssssscssscccssssccscsscsssssesssssesssoes 13 Table 2 2 Input Channels Bias Resistors Locations esse Ge eee Ge Ga 14 Table 2 3 Input Channels Bias Resistor Values s ssscccecscscesscsscsscsscsccssssccscsscsssssssscssessescsssors 14 Table 2 4 Additional Input Channels Bias Resistors Locations ese Ge EG ee 14 Table 3 5 Register Address Map eiie es oa oe ke ewe ge ee we ee ee SUE de ei se AN dee be de 22 Table 3 6 Board Status eet engen eege eer NE Da ER Ev Ge RR NN SEU NDS o eux EN Poe Tema VR EV 22 Table 3 7 Board TEE 23 Table 3 8 Received Data Register eee ene tte tte b o o ad verto se es epa Von eae ed ede a vau 23 Table 3 9 Change Of Slate veglster i sees se taa eras nota oo eR Se ve de Ee de N SR ee eg de ee de 24 Table 3 10 Receive Event COWBIer sisicssccticelesassssoadscasshoisseatenued ss soe de ede ek od ae Seg ee Ee ed 24 Table 3 11 COS Interrupt Enable Register sesse esse Ge AG
28. utputs It is based on the PCI OPTO32B and Offers the same cable interface options and the same cable pin outs as the PCI OPTO32B The PCIe OPTO32C is available in the same 3 configurations as the PCI OPTO32B with the same cable pin outs e Asa Standard OPTO32 Board with 24 input Channels e Asa OPTO32C I2V CONTACT which is designed to sense contact closures on all 24 inputs The high side of the Opto Isolator is connected to 12V through a Current Limiting Resistor See the PCIe OPTO32C 12V CONTACT Manual e Asa OPTO32C I2V CONTACT 8x28V which has channels 0 through 7 configured as normal OPTO Inputs but channels 8 through 23 are configured to sense contact closures See the PCle OPTO32C 12V CONTACT Manual 1 1 Differences From OPTO32 Family The PCIe OPTO32C is based on the PCI OPTO32B family It was designed to provide a migration path for the OPTO32 family to the PCIe Bus It uses the same cable connector and the same cable Pin out as other members of the OPTO32 Family e Output Bits 0 7 are the same as the OPTO32 Family e Input Bits 0 22 are the same as the OPTO32 Family The following differences exist between the OPTO32 Family and the PCIe OPTO32C e Special Schmidt Trigger Input has been removed from Input Channel 23 All Inputs are the same e Input 23 is now the same as Input Channels 00 22 e True PCle Form factor e Uses the PLX PEX 83111 PCIe Bus Interface e Card is mapped into PCIe Memory Space User Manual for the PCle
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