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RTU94 Real Time Unit 1994
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1. wait for flag tf47 1 terminate wait for flag tf48 1 terminate 57 while 1 int 50 define size50 128 char stack50 size50 void t50_main void while 1 int t 51 define size51 128 char stack51 size51 void t51_main void while 1 int 452 define size52 128 char stack52 size52 void t52 main void while 1 int 453 define size53 128 char stack53 size53 void t53_main void while 1 wait for flag tf49 1 terminate wait for flag tf50 1 terminate wait for flag tf51 1 terminate wait for flag tf52 1 terminate 58 wait for flag tf53 1 terminate define size54 128 char stack54 size54 void 54 main void int 1 1 0 outstr 1 n rChecking Event flag again while 1 set or reset flag 0 tf47 0 tf48 0 tf49 0 tf50 0 for 1 471 lt 50 activate 1 while task_status 47 3 II task_status 48 3 ll task status 49 3 ll task status 50 3 set or reset flag 1 while task_status 47 0 II task_status 48 0 Il task_status 49 0 II task_status 50 0 if tf47 0 II tf48 0 II tf49 0 II tf50 0 outstr 1 n rEvent flag again is not OK l 1 set_or_reset_flag 0 tf50 0 tf5 1 0 tf52 0 tf53 0 for 1 50 1 lt 53 1 activate i while task status 50 23 ll task status 51 3 ll task sta
2. IRO IN3 External interrupt TIME SYNC Test pin CS N Chip select Com to external chip 16 DE Com to external NC Test pin chip 17 D12 Com to external NC Test pin chip 18 D4 Com to external NC Test pin chip 19 Dii Com to external NC Test pin IRQ2 Taskswitch chip irq6 20 D3 Com to external NC Test pin IRQ1 Taskswitch chip irq5 21 GND Coi to external NC Test pin IRQO Taskswitch Chit irq4 66 Appendix D This appendix describes a performance analysis on RTU94 compared with a commercial realtime kernel RTK in software The comparison is analytic based on data sheets and practical measurings It is difficult to compare different realtime kernels because of the big variation of methods of mesuring performance Different cpu structures gives problems e g cpu using cache and or pipeline The time behaviour on a program can vary a lot if a cpu e g get cache misses Similar problems is it with pipeline cpus Cache increase the performance on applications which often uses the same code part In realtime systems the executing code is often changing lot therefore the performance is sometimes decreasing when using cache in realtime systems Figur 4 RTU94 consists of an Interface 2 and a Real Time Unit 3 The performance on R TU94 is dependent on how fast the bus 5 can transfer data from cpus 1 to the interface 2 The data is transfered within 1 clock cycle from the
3. VHDL f r konstruktion 360 pages LLindh and S Sj holm Studentlitteratur ISBN 91 44 47781 3 1994 From Single to Multiprocessor Real Time Kernels in Hardware LLindh J Starner and J Furun s IEEE Real Time Technology and Applications Symposium Chicago May 15 17 1995 From Single to Multiprocessor Real Time Kernels in Hardware LLindh J Starner and J Furun s SNART 95 Svenska Nationella Realtidsf reningen G teborg 22 23 augusti 1995 1995 VHDL f r konstruktion ca 600 pages LLindh and S Sj holm Studentlitteratur Dec 1995 VHDL for Design about 500 pages LLindh and S Sj holm Prentice Hall V ren 1996 References 77 Microtec Microtec manuals which are relevant to this document Microtec Research Software Development Tools XRAY68K Debugger ASM68K Assembler MCC68K C Compiler FORCE FORCE manuals which are relevant to this document SYS68K CPU 3VA Hardware user s manual SYS68K DRAM 1 2 user s manual 78
4. CpuNr N U Not Used Init period time Description Initiates the periodic time for the task Arguments Cpu Nr a cpu number from 0 to 2 Period Time a periodic time number that corespond to following bitpattern when time sync s period time is set to 2 ms 00001 1 gt 2 ms 00010 2 gt 10 ms 00100 4 gt 100 ms 01000 8 gt 1000 ms 10000 16 gt 10 Note The period time can change changing the clock frequency time sync Only task 0 32 can be initiated to be periodic Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 PeriodTime CpuNr N U Not Used Wait for next period Description Place the task in the periodic waiting queue until its periodic time has expired which is initiated by init period time Argument Cpu Nr a cpu number from 0 to 2 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 N U Not Used Off period start Description Disable periodic start for the task Argument Cpu Nr a cpu number from 0 to 2 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 Cp Nr N U Not Used 16 Delay Description Place the task the delay waiting queue until the delay time has expired Arguments Cpu Nr a cpu number from 0 to 2 Delay Time a delay time number 0 to 31 when time sync s period time is set to 2 ms 0 gt trig start synchronization with time sync 1 gt 2ms 2 gt 4ms 31 gt
5. within 4 clock periods 1 RTK and 2 are presented with us i e change priority on a task is performed within 65 us Ex1 and 127 1 us Ex2 Service Calls RTU94 S RTU94 M Ex RTK Ex2 RTK Task Management Functions Enable disable taskswitch 1 1 3 Initialize a task 4 4 12 65 Change priority 4 4 12 60 127 1 Activate a Task 4 4 12 50 109 Terminate a task 4 4 12 80 130 2 Switch task 4 4 12 81 142 8 Deadline control 0 0 Time Functions Timer on off 4 4 12 Initialize the periodic time 4 4 12 Wait for next period 4 4 12 Disable periodic start 4 4 12 Delay 4 4 12 Watch Dog Functions Initialize a watchdog 4 4 12 Reset a watchdog timer 4 4 12 Flag Functions Wait for semafore free 5 5 15 33 59 9 wait 5 5 15 33 free wait 5 5 15 85 161 6 Release semafore no waiting tasks 4 4 12 35 53 7 69 calling task not preempts 4 4 12 56 89 4 calling task preempts 4 4 12 75 147 9 Wait for flag free 5 5 15 47 2 wait 5 5 15 free wait 5 5 15 143 5 Set reset flag no waiting tasks 4 4 12 56 6 calling task not preempts 4 4 12 98 6 calling task preempts 4 4 12 157 4 Context switch no register save 4 4 12 7 58 6 Reg save Time period 10 10 Ims ms Summary The processing time in a commercial R TK is approx 10 to 20 times longer than for the RTU In multiprocessor sy
6. Jumper 16 1 2 3 4 Connection between Various settings Function BCLR is enabled SYSCLK is driven to the VMEbus Note SYSCLK must be disabled if an external arbiter wich usually drives the SYSCLK is used else it must be enabled Jumper B17 Open Inserted B19 Open Inserted Connection between Function SYSRESET is not driven to the VMEbus SYSRESET is driven to the VMEbus SYSRESET is not received from the VMEbus SYSRESET is received from the VMEbus For more information about jumper settings and jumpers see FORCE SYS68K CPU 3 V hardware user s manual Storage Capacity Word Length Page Boundaries Control Access Times Operating Modes Power Requirements Standby Power Req Operating Temperature Storage Temperature Relative Humidity Board Dimensions SYS68K DRAM 1 Specification 512K Bytes 8 Bit with 1 Parity Bit 16 Bit with 2 Parity Bits Free Jumper Selectable Base Address 256K Byte Pages Address Modifier Decoding Control and Status Register for Multi Mode Control Write Access 190 ns typ Write Access 210 ns max Read Access 300 ns typ Read Access 320 ns max Write cycle 355 ns max Read cycle 400 ns max Write Word or Byte Read Word or Byte Read Modify Write Word or Byte Read Write protection jumper selectable or software programmable Standby Power Mode for Data Saving at Main Power Down 5V 2 0A max Operating Mode 5V 1 8A
7. char stack25 size25 void 25 main void while 1 stop 0 time 0 init period time 8 wait for next period off period start stop 1 time8 time activate 26 48 terminate define size26 128 char stack26 size26 void t26 main void while 1 if time 1 lt time8 outstr 1 n rWait for next period again is OK else outstr 1 n rWait for next period again is not OK finish 1 terminate define size27 128 char stack27 size27 void t27 main void while finish 1 while stop 0 time activate 28 terminate sese ske oe 2 ok ok ok Wait for next per task s 28 28 2 kkk eee e ae 78 7 ke sk oF ee ee 9 fe tasks k k K define size28 128 char stack28 size28 void t28 main void outstr 1 n rChecking Delay again finish 0 stop 0 activate 30 while 1 49 deltime 0 delay 0 deltime0 deltime deltime 0 delay 1 deltime1 deltime deltime 0 delay 2 deltime2 deltime deltime 0 delay 3 deltime3 deltime deltime 0 delay 4 deltime4 deltime stop 1 activate 29 terminate define size29 128 char stack29 size29 void t29 main void while 1 stop 0 deltime 0 delay 30 deltime30 deltime deltime 0 delay 31 deltime3 1 deltime deltime 0 stop 1 if deltime0 lt deltime 1 amp amp delti
8. A simple handshake protocol to get a safe communication between the CPU and the RTU94 when a service call 1 performed Taskswitch Irq protocol Operation 1 RTU94 sets IRQ TSW FLAG on CPU STATUS REG and interrupt the cpu 2 The cpu must check if IRQ TSW FLAG is set if it is not set ignore interrupt and acknowledge the interrupt by setting bit TSW FLAG on CPU CONTROL REG 3 RTU94 clear IRQ TSW FLAG clear the interrupt and place next task id on NEXT TASK ID 4 The cpu must waits until IRQ TSW FLAG is cleared and then it gets new task id to switch to by reading NEXT TASK ID After reading next task id the cpu must clear TSW ACK FLAG to finish the taskswitch procedure CPU RTU94 CTT TT ceu status REG CPU re seg RTU94 CTT TT eru stATUS REG CTT TTT eru REG CPU NEXT TASK READY 94 T Jo Cru STATUS REG NEXT TASK NEXT TASK ID CPU cernewrask RTU94 NEXT TASK NEXT TASK ID ITT 9 CRU CONTROL REG 12 Terminate protocol Operation 1 The cpu must set TSW FLAG CONTROL on CPU CONTROL REG to make sure that no taskswitch from RTU94 is comming and then set CALL NEXT TASK ID on CPU CONTROL REG 2 RTU94 sets ACK NEXT TASK ID on CPU STATUS REG to acknowledge the call for next task id 3 The cpu must wait until ACK NEXT TASK ID is set and then clear CALL NEXT TASK ID 4 RTU94 clear ACK NEXT TASK ID and place next task id on NEXT TASK ID 5 The cpu must wait
9. INDICATORS 75 Appendix In this appendix list of RTU94 related publications are adressed Thesis Lindh L Utilization of Hardware Parallelism in Realizing Real Time Kernels TRITA TDE 1994 1 ISSN 0280 4506 ISRN KTH TDE FR 94 1 SE Royal Institute of Technology Department of Electronics book about today s Real Time Systems Studentlitteratur Christer Eriksson and Lennart Lindh Realtidssystem grunderna f r styrsystem Studentlitteratur ISBN 91 44 28821 2 1989 Measuring and Analysing Real Time Kernel Performance H Berggren M Gustafsson and L Lindh Measuring and Analysing Real Time Kernel Performance Euromicro 92 Paris 14 17 September 1992 Compendium for design methodology L Lindh Utvecklingsmetodik f r h rdvara Sweden V ster s Department of Real Time Systems Internal 1989 The Idea of FASTCHART L Lindh F Stanischewski FASTCHART A Fast Time Deterministic CPU and Hardware Based Real Time Kernel TEEE press Real Time Workshop Paris 12 14 June 1991 Implementation of FASTCHART L Lindh F Stanischewski FASTCHART Idea and Implementation IEEE press International Conference on Computer Design ICCD Cambridge MIT USA 14 16 Oct 1991 Idea of FASTHARD L Lindh FASTHARD A Fast Time Deterministic Hardware Based Real Time Kernel TEEE press Real Time Workshop Athens 3 5 June 1992 Implementation of FASTHARD L Lindh FASTHA
10. either serial slave mode for serial link configuration or to parallell master mode for loading configuration data from an onboard mounted EPROM Xl is configured serially by X2 and the mode is always set to serial slave mode X2 shall have a 6116 RAM for storing scheduling data RESET and REPROGRAM from EPROM buttons in the frontpanel Jumper to set EPROM in constant tri state 73 Block scheme for 50k prototypeboard 74 E D LS XILINXI i D 645 R PENCIL 74 LS 645 clk gen CLK MODE FPGAMODE RESET REPROGRAM ASQN MODES 74 z ELS SSR svsekf P lt ny x E SRI 244 lt C IACKIN L NGT C mos gt K rd rf 4 BERR 4 D S IACKOUT 38 FPGA MODE XILINX2 EXTERN IRQ X4 RESET EXTERN O lg _ RAM_ LOAD M MR REPROGRAM Component placement 50k prototypeboard EPROM FOR STORING CONFIGURATION DATA ON BOARD 2X PROGRAMMABLE RAM FOR CLOCKS STORING FULLY BUFFERED SCHEDULING VME INTERFACE DATA ACCORDING TO SPECIFICATION JUMPER i SELECTABLE BASEADRESS je J5 JUMPERS FOR ONBOARD OR EXTERNAL CONTACT FOR SERIAL CONFIG DATA CONFIG RESET AND 14 USER REPROGRM POWER AND CONTROLLABLE SWITCHES CONFIGURATION DIAGNOSE LEDS
11. main void int 1 0 outstr 1 n rChecking Watch dog 0 to 2 while 1 activate 1 activate 2 kick 0 init watch dog 1 0 init watch dog 0 0 if kick 20000 outstr 1 n rWatch dog 0 is not OK 1 1 activate 3 activate 4 kick 0 mit watch dog 1 1 mit watch dog 0 1 if kick 20000 outstr 1 n rWatch dog 1 is not OK 1 1 activate 5 activate 6 activate 7 kick 0 37 init watch dog 1 2 init watch dog 0 2 if kick 30000 outstr 1 n rWatch dog 2 is not OK 1 1 if 1220 outstr 1 n rWatch dog 0 to 215 activate 8 terminate define sizel 128 char stack1 size1 void tl main void while kick lt 10000 kik dog 0 kick terminate define size2 128 char stack2 size2 void t2 main void while kick lt 20000 kik dog 0 kick terminate define size3 128 char stack3 size3 void t3 main void while kick lt 10000 kik dog 1 kick terminate define size4 128 38 char stack4 size4 void t4 main void while kick lt 20000 kik dog 1 kick terminate define size5 128 char stack5 size5 void t5 main void while kick lt 10000 kik dog 2 kick terminate define size6 128 char stack6 size6 void 6 main void while kick lt 20000 kik dog 2 kick terminate define size7 128
12. of the interrupt task classifies when the taskis going to be executed Figure 8 shows how the RTU does not interrupt the CPU if an interrupt with lower priority than the executing task has occured The only time the CPU gets interrupted is when the interrupt task has higher priority than the executing task The time from the external interrupt occurs until the interrupt task starts is the sum of 1 3 and 4 The scheduling of the interrupt task 1 is approx 0 6 6 25 5 running at 16 Mhz Time 3 is the interrupt handler time approx 10 i e saving registers on stack etc Restoring a task s registers is time 4 which is approx 10 20us on a fast CPU By adding 1 3 and 4 you get the contextswitch time for interrupt tasks when the interrupt task has higher priority than the running task In the multiprocessor case the same times are valid 71 EXT IRG RTU34 TASK A Time_CPU EXT IAQ RTU94 IRQ CPU TSW rutin TASK A IRQ_TASK Time CPU Figur 8 Top figure shows whats happening in the CPU when the interrupt has lower priority than the running task Bottom figure shows when the interrupt task has higher priority The table below shows the performance on interrupt handling on different RTK Service Anrop us RTU94 S RTU94 M EXI Ex2 Interrupt Handeling Function Walt for IRQ Return to IRQ task 36 30 36 30 79 3 Return to preemted task a 0 0 29 5 Note The C
13. priority based pre emptive algorithm The goal of the algorithm is to guarantee that the task which is executing on the processors at any point in time is the one with the highest priority among all tasks in the ready state A task can be executing ready or waiting There can only be one task executing on a CPU at a time so if we have three CPU s in the system there can be three executing tasks The RTU94 has four different ready queues one ready queue for each CPU A task any of these queues can only be executed on the corresponding CPU The last ready queue consists of tasks that can be executed on any of the connected CPU s The scheduler compares in parallel the own and common queue for each CPU in order for the scheduler to fulfil its goal There are two events that can change the executing task First the task itself can request a task switch Second the scheduler can interrupt the executing task if there is a task with higher priority in the ready queue Delay Holds a task in the delay queue until the delay time has expired then the task is send to the redy queue Periodic start Holds a task in the periodic queue until the period time has expired then the task 15 send to the redy queue Watch dog Holds a task until the watch dog is not kicked within the watchdog time then the task is send to the ready queue Semafore Can hold four tasks in the semafore queue The first task in the queue get the semafore when
14. se ae ae k he k kk k k k k k K k k K K k k k k kk k kk k k Jf ke EK KK als ale KK ae ae ae ae he ae he he ak ak i a k k k Semafore tasks k int ts39 define size39 128 char stack39 size39 void t39_main void while 1 int ts40 define size40 128 char stack40 size40 void t40_main void while 1 int ts41 define size41 128 char stack4 1 size41 void t41_main void while 1 wait_for_semafore ts39 1 release_semafore terminate wait_for_semafore ts40 1 release_semafore terminate 54 int 542 define size42 128 char stack42 size42 void t42 main void while 1 int 543 define size43 128 char stack43 size43 void t43 main void while 1 int 1544 define size44 128 char stack44 size44 void 144 main void while 1 int 545 define size45 128 char stack45 size45 wait for semafore ts41 1 release semafore terminate wait for semafore ts42 1 release semafore terminate wait for semafore ts43 1 release semafore terminate wait for semafore ts44 1 release semafore terminate 55 void 45 main void while 1 wait for semafore ts45 1 release semafore terminate define size46 128 char stack46 size46 void t46 main void int 1 1 0 outstr 1 n rChecking Sema
15. tick interrupts to the cpu are needed The interrupt handler is implemented on the which means that external interrupts doesn t interupt high priority running tasks The response time decreases for all service calls because the is designed of parrallell hardware e g scheduling semafore handling etc are performed in parallell on the RTU Software development Easier software development because the code for the realtime kernel doesn t have to be executed by the cpu Easier understandability for the system because of separateing the realtime kernel from RAM more safe execution of the realtime kernel functions because of the functions are designed in physical separated parts And therefore no interference between the functions are possible No interrupt handler for external interrupts except the task switch interrupt has to be implemented in software It is easier to build multiprocessor systems since synchronisation between cpu s using flags load balancing and redundancy using watch dogs are supported by the RTU It is easier to debug a RTU based realtime system whithout affecting it since the service calls to it can be logged on the bus The motivation for using a RTU is almost the same as using a mathprocessor A mathprossesor helps the cpu to get better perfomance and the RTU does the same But a difference between a mathprocessor and a RTU is that the RTU is more complex Example of a
16. 1 wait for semafore ts57 1 release semafore terminate wait for semafore ts58 1 release_semafore terminate wait_for_semafore ts59 1 release_semafore terminate wait_for_semafore ts60 1 release_semafore terminate 61 void 61 main void while 1 wait for semafore ts61 1 release semafore terminate define size62 128 char stack62 size62 void t62_main void int 1 1 0 outstr 1 n rChecking Semafore again while 1 ts55 0 ts56 0 ts57 0 ts58 0 wait_for_semafore for 1 551 lt 58 activate 1 while task status 55 4 ll task status 56 4 ll task status 57 4 ll task status 58 4 release semafore while task_status 55 0 II task_status 56 0 ll task status 57 0 l task status 58 0 if ts55 0 II ts56 0 II ts57 0 II ts58 0 outstr 1 n rSemafore again is not OK ts58 0 ts59 0 ts60 0 ts6 1 0 wait_for_semafore for 1 58 i lt 61 i activate 1 while task status 58 4 ll task status 59 4 ll task status 60 4 l task status 61 4 release semafore while task_status 58 0 II task_status 59 0 ll task status 60 0 l task status 61 0 62 if 858 0 859 0 860 0 861 0 0 outstr 1 n rSemafore again is not OK else if 1 1 outstr 1 n rSem
17. 62ms Note Only task 0 32 can be delayed Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NU DelayTime CpuNr N UzNot Used Wait irq external Description Place the task in wait state for interrupt with number Irg Nr Arguments Cpu Nr a cpu number from 0 to 2 Irq Nr an interrupt number from 0 to 3 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 Cpu Nr N U Not Used Init watch dog Description Starts or stopps a watchdog with number Nr Arguments Cpu Nr a cpu number from 0 to 2 Nr a watchdog number from 0 to 2 On I to start watchdog and 0 to stop watchdog Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L1j0 O Oj On Nr N U Not Used 17 Kik dog Description Reset the counter in watchdog with number Nr Argument Nr watchdog number from 0 to 2 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 joe ONU N U Not Used Wait for semafore Description If the semafore is free the task takes it and continue the execution If the semafore is already taken the task is placed in the semafore queue until it gets the semafore Argument Cpu Nr a cpu number from 0 to 2 Affected register Bit SVC RETURN on RTU STATUS REG is set to 0 if the semafore got allocated else 1 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cp Nr N U Not Used Re
18. 7 main void while 1 wait for flag tf33 1 terminate wait for flag tf34 1 terminate wait for flag tf35 1 terminate wait for flag tf36 1 terminate 52 wait for flag tf37 1 terminate define size38 128 char stack38 size38 void t38 main void int 1 1 0 outstr 1 n rChecking Event flag while 1 set or reset flag 0 tf31 0 tf32 0 tf33 0 tf34 0 for 1 3 1 1 lt 34 1 activate 1 while task_status 31 3 II task_status 32 3 Il task_status 33 3 Il task_status 34 3 set_or_reset_flag 1 while task_status 31 0 II task_status 32 0 Il task_status 33 0 II task_status 34 0 if tf3 1 O II tf32 0 II tf33 0 II tf34 0 outstr 1 n rEvent flag is not OK l 1 set_or_reset_flag 0 tf34 0 tf35 0 tf36 0 tf37 0 for 1 34 1 lt 37 1 activate i while task_status 34 3 II task_status 35 3 ll task status 36 3 ll task status 37 3 set or reset flag 1 while task_status 34 0 II task_status 35 0 Il task_status 36 0 II task_status 37 0 if tf34 0 II tf3 5 0 II tf36 0 II tf3 7 0 amp amp 1 0 outstr 1 n rEvent flag is not OK 53 else if 1 1 outstr 1 n rEvent flag is OK activate 46 terminate Jf ke ae ae ae ae ae ae ak ak ak ak ak ak ak ak kkk End Event flag task s 4 3 3 sl se k k
19. Eurocard 234x160mm 9 2 x 6 3 Memory Map Start Vectors SYSTEM Area 32K Byte SRAM EPROM Area SYSTEM and USER LOCAL Devices Short I O Address Range VMEbus 33 Address Assignment of the I O Devices Address I O Device F40000 MPCC 68561 F40801 PIT 68230 F41801 RTC 58167A F45000 DMAC 68450 F46000 MMU 68451 Jumper Settings Time settings Jumper Connection between Function B7 7 8 Bus error timout is set to min 122000 us 1 10 Must be connected 1 9 Bus Mastership timeout is setto max 2 us Interrupt level settings Jumper Connection between Function B10 1 16 IRQI is enabled 2 15 IRQ2 is enabled 3 14 IRQ3 is enabled 4 13 IRQ4 is enabled Cpu 0 must have IRQ4 enabled 5 12 IRQS is enabled Cpu 1 must have IRQ5 enabled 6 11 IRQ6 is enabled Cpu 2 must have IRQ6 enabled 7 10 IRQT is enabled 8 9 Must be connected Note not inserted jumper is equalent to a disabled VMEbus IRO signal If a multi processor RTU system is used only one of IRQ4 to IRQ6 is allowed to be enabled on a cpu Because the RTU94 uses IRQ4 to IRQ6 to tell a cpu to perform a taskswitch Arbiter settings With on board arbiter and BR3 With external arbiter and BR3 Jumper Connection between Connection between B15 15 18 15 18 9 24 9 8 11 22 11 6 12 21 12 5 13 14 13 14 19 20 4 3 Note If the on board arbiter is used only one arbiter is allowed on the VMEbus the board must be placed in slot 1 34
20. PU load time is within paranthesis IACKL 0 0 12 5 13 IACKL is the maximum time an interrupt is disabled Summary Interrupt handling does not load the CPU when is used When the interrupt task has lower priority than the running task the CPU does not get interrupted if is used The interrupt handler on the RTU works in a similar way in a multiprocessor environment as in a single processor environment 72 Appendix This appendix describes FPGA prototype board which can be configured to work as a RTU94 on a VME board This board can also be used when new prototypes has to be implemented Hardwarespecification for 50k FPGA prototypeboard two FPGA s XILINX 4013 4025 two different onboardgenerated clockfrekvencies variable fastclock is generated by an EXO 3 jumper programmable clockoscillator slow clock time sync is generated by dividing 16mhz in 4 4bit binarycounters jumper selectable configuration either from a serial link or parallell from an onboard mounted EPROM the 16 datasignals are buffered by two bidirectional 74L S645 A A6 connects to X1 via 74LS244 buffers A23 AT7 are indirectly buffered by the comparator controlsignals out from the board are buffered by 74F39 adressdecode is implemented with a 74HCT688 comparator A23 A17 are compared with the 7bit jumper programmable baseadress together with AS for stabile CS out X2 s mode is jumper programmable to
21. RD Prototype A Real Time Kernel Implemented In One Chip IEEE press Real Time Workshop Oulu 3 5 June 1993 Survey of FASTHARD Real Time Kernel Implemented In special Hardware L Lindh Survey of FASTHARD Real Time Kernel Implemented In Special Hardware 93 rs Konferens om Realtidssystem Stockholm 25 26 Aug 1993 76 Prototyping with VHDL Design Experience L Lindh Rapid Prototyping with VHDL Design Experience EURO VHDL 91 Stockholm 8 11 September 1991 Sweden Design of a Real Time Unit in Hardware L Lindh amp F Stanischewski A Design of a Real Time Unit in Hardware Svenska Nationella Arbetsgruppen i Realtid SNART Uppsala 19 20 august 1991 Rapid Prototyping with VHDL and FPGAs L Lindh Prof M ller Glaser and H Rauch Rapid Prototyping With VHDL and International Workshop on Field Programmable Logic and Application Vienna Austria 31 august 2 September 1992 Rapid Prototyping with VHDL and FPGAs L Lindh Prof M ller Glaser and H Rauch Rapid Prototyping With VHDL and FPGAs Lecture notes in Computer Science 705 Springer Verlag ISBN 0 387 57091 8 or ISBN 3 540 57091 8 1993 Experiences with VHDL and FPGAs L Lindh J St rner and J Adomat VHDL Forum EUROPE Nantes France April 24 27 1995 Experiences with VHDL and FPGAs extended L Lindh J St rner and J Adomat Journal of System Architecture North Holland 1995
22. RTU not by the CPU Clocktick administration is for instance used for updating timequeues therefore the clockticks affects the resolution of the system time The resolution on RTU94 is 10 us compared to a comercial RTK which have approx 1 ms Summary A lot of time can be saved and easier time analysis can be performed when the is used as supervisor and clocktick administrator Clocktickadministration is not performed by the cpu or cpus a multiprocessor system when the is used 68 Service calls In this section a time table for the most common service calls are presented The table is organized in columns with different RTK RTU S RTU94 as a singel processor RTK The time consuming part is the parameter transefering between the tasks and the RTU The system consist of a M68000 16 MHz on a VME bus RTU M RTU94 as a multiprocessor RTK with three cpus with a common VME bus The maximum time within parenthesis is dependent on the shared VME bus The system consists of three M68000 16 MHz on a VME bus with a round robin arbitrer 1 commercial running on MC68020 20 Mhz In this case it is not stated if the cache is enabled or not The times presented is the average time for at least 100 service calls EX2 RTK a commercial RTK running on MC68000 16 7 MHz This system is similar to RTU S Note RTU S and RTU M are presented with clock periods i e initialize a task is performed
23. RTU94 Real Time Unit 1994 Reference Manual HESTE Ts STE LETE TETTE A 222 I 1 RTU94 This publication may be reproduced if the source is referered Lennart Lindh M lardalens University P O Box 883 S 721 23 V ster s Sweden e mail lennart lindh mdh se Contact Person Johan Furun s M lardalens University Box 883 S 721 23 V ster s Sweden e mail johan furunas mdh se Authors Joakim Adomat Johan Furun s Johan St rner and Lennart Lindh ver 1 7 960205 The RTU94 concept is patent pending Preface The RTU94 reference manual describes how to build a realtime system with RTU94 This manual contains the following chapters and appendices Chapter 1 Introduction provides a general overview of RTU94 Chapter 2 Communication describes the registers on RTU94 and how they are used in communication between a cpu and the R TU94 Chapter 3 Service calls describes the services RTU94 supports and how they are used and which instruction format they have Chapter 4 C interface describes C functions avalible for RTU94 Chapter 5 System configuration describes the configuration of a realtime system using the RTU94 and FORCE boards Chapter 6 Software development describes how to develop software on FORCE SYS68K CPU boards using Microtec Research 68K software development tools Appendix A VME boards a short description of some FORCE VME boa
24. ackl size Allocate stack void task void init task tcb 7 1 taskl stackl size 1 Note When task is initiated to run whichever cpu that has time to execute it the task code must be copied onto every initiated cpu The id number task id 63 is always the identity number of the idle task Activate a Task int activate inttask id This function activates a task with specified task id RTU94 gives a taskswitch interrupt if the activated task has a higher priority level than the running task Activate returns 0 if task id is already activated else 1 Example extern void task 1 void void task void activate 1 21 Terminate a task void terminate void This function terminates the running task The TCB and stack are reseted and if the task is activated again it will start from the beginning Example void task void terminate Switch task void taskswitch void This function switch the running task The TCB and stack are saved and if the task is activated again it will start from the place it where taskswitched Example void task void taskswitch 22 Time Functions Timer on off void timer on void This function turns on the time sync clock on the RTU94 The time sync period can be between 100us void timer off void This function turns off the time sync on the RTU94 Example void task void timer off section where the
25. afore again is OK outstr 1 n rChecking irq external outstr 1 n rWaiting for irq0 wait irq external 0 outstr 1 nwWaiting for irq1 wait irq external 1 outstr 1 nv Waiting for irq2 wait irq external 2 outstr 1 nv Waiting for irq3 wait irg external 3 outstr 1 nMrq external is OK outstr 1 nV Test is finished terminate Bag Semafore tasks 7 7 2 2 se se se se ae ae k k k k k k kk kk k k k k k K K K Fe task define sizeidle 10 char stackidle sizeidle void idle main void while 1 Jf ke 2 2 2 Idle task 7 k kk k k k k kk k k k k k k k k k k k k k kk K K K K K k k k k k kk k kk k k k void main void serinit init CPUNR init task tcb 0 0 t0 main stack0 size0 CPUNR init task tcb 1 1 t1 main stackl sizel CPUNR init task tcb 2 2 t2 main stack2 size2 CPUNR init task tcb 3 3 t3 main stack3 size3 CPUNR 63 init task tcb 4 4 t4 main stack4 size4 CPUNR init task tcb 5 5 t5 main stack5 size5 CPUNR init task tcb 6 6 t6 main stack6 size6 CPUNR init task tcb 7 7 t7 main stack7 size7 CPUNR init task tcb 0 8 t8 main stack8 size8 CPUNR init task tcb 1 9 t9 main stack9 size9 CPUNR init task tcb 2 10 t10 main stack10 size10 CPUNR init task tcb 3 11 t11 main stack11 size1l 1 CPUNR init task tcb 4 12 t12 ma
26. ate stop 0 deltime 0 delay 20 deltime20 deltime deltime 0 delay 21 deltime2 1 deltime deltime 0 delay 22 deltime22 deltime 45 int deltime25 int deltime26 int deltime27 int deltime28 int deltime29 define size21 128 char stack21 size21 void t21_main void while 1 int deltime30 int deltime31 define size22 128 char stack22 size22 void 122 main void deltime 0 delay 23 deltime23 deltime deltime 0 delay 24 deltime24 deltime stop 1 activate 21 terminate stop 0 deltime 0 delay 25 deltime25 deltime deltime 0 delay 26 deltime26 deltime deltime 0 delay 27 deltime27 deltime deltime 0 delay 28 deltime28 deltime deltime 0 delay 29 deltime29 deltime stop 1 activate 22 terminate 46 while 1 stop 0 deltime 0 delay 30 deltime30 deltime deltime 0 delay 31 deltime3 1 deltime deltime 0 stop 1 if deltime0 lt deltime1 amp amp deltime1 lt deltime2 amp amp deltime2 lt deltime3 amp amp deltime3 lt delti me4 amp amp deltime4 deltime5 amp amp deltime5 deltime6 amp amp deltime6 deltime7 amp amp deltime7 deltime8 amp amp deltime8 deltime9 amp amp deltime9 deltime10 amp amp deltime10 deltimel 1 amp amp deltime 1 1 lt deltime12 amp amp deltime I 2 lt deltime 13 amp amp deltime I 3 lt deltime 14 amp amp deltime 14 lt deltim
27. char stack7 size7 void t7 main void while kick lt 30000 kik dog 2 kick terminate sese ee Watch dog tasks 7 2 2 se se se k k ae ae see k k k K sese oF k sk ok ok ok ok SR o o o oe oe ole R oe fe Wall for next per taskg K int time int timel 39 int stop int finish define size8 128 char stack8 size8 void t8 main void outstr 1 n rChecking Wait for next period finish 0 stop 0 activate 15 while 1 int time2 define size9 128 char stack9 size9 void t9_main void while 1 int time4 define size10 128 char stack10 size10 void t10 main void while 1 time 0 init period time 1 wait for next period off period start stop 1 timel time activate 9 terminate stop 0 time 0 init period time 2 wait for next period off period start stop 1 time2 time activate 10 terminate stop 0 time 0 40 int time8 define size11 128 char stack1 1 517 1 1 void t11 main void while 1 int time16 define size12 128 char stack12 size12 void t12 main void while 1 define size13 128 char stack13 size13 void t13 main void init period time 4 wait for next period off period start stop 1 time4 time activate 11 terminate stop 0 time 0 init period time 8 wai
28. d debugger it is a ROM resident firmware placed on each cpu board See below for a brief description of how to use the assembler linker etc Assembler directives Assembly a source src file and generate an object obj file and a list 180 file Example ASM filename src The example above uses following batch file ASM BAT asm68k 1 gt 1 lst 1 sre Compiling directives Compiling a C c file and generate a source src file Example CC filename c The example above uses following batch file for relative addressing CC BAT mcc68k Gf g 1 Mcp Md5 nOc nOl S o461 src 1 The example above uses following batch file for absolute addressing CC BAT 8 Gf g 1 Mca Mda nOc nOI S o961 src 1 c Gf Generates fully qualified path name for input files g Generates debug information Generates a source listing with errors Mcp Directs the compiler to use PC relative addressing for all code references Md5 Directs the compiler to use A5 relative addressing for all static data references Mca Directs the compiler to use absolute addressing for all code references Mda Directs the compiler to use absolute addressing for all data references nOc Generates code to pop stack after every function call nOl Code hoisting and cross jump optimizations are disabled 0 l src 1 c Generate output file with src extension from the origin file with extension Linking direc
29. d the cpu must deallocate the SVC SEMAPHORE REG if it is a multiprocessor system and if you want other tasks to be scheduled on the cpu clear TSW FLAG CONTROL TSw OFF amp GET SVC SEM CPU amp SVC CALL RTUS4 CTT TTT eru cowrRou REG EIT s C_sEMAPHORE_REG SVC CALL SVC INSTRUCTION REG CPU SYC RTUS4 1111 status REG SVC RETURN CPU END 5 RTUS4 END SYC SVC INSTRUCTION REG CPU ACK END SVC RTUS4 L TT j RTU STATUS REG CPU TSw RTUS4 BIT J syvc SEMAPHORE REG C Tol CONTROL REG 14 3 Service calls In this chapter all the service calls to RTU94 are described and which instruction format they have As explained in the previous chapter the service calls are placed on the SVC INSTRUCTION REG Activate Description Activates a task with task id number Task Id Argument Task Id a task number from 0 to 63 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x 0 0 0 1 NU N UzNot Used Init task tcb Description Initiates a task with Priority and Task Id on Cpu Nr Arguments Priority a priority number from 0 highest priority to 7 lowest priority Task Id a task number from 0 to 63 Cpu Nr a cpu number from 0 to 2 or a 3 that specifies that the task can be scheduled to run on whichever cpu that is able to execute it Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x 0 0 1 0 NU Priority Taskld
30. debugger the abs file must be in IEEE 695 format xhm68k filename abs to be able to use this you must first download the XRAY debugger by writing xhm68k e 1 filename abs If using COM68000 the abs file must be in motorola S record format com68000 filename abs 32 Microprocessor DMA Controller Memory Management Serial I O Control Real Time Clock SRAM EPROM VMEbus Arbiter Firmware Power Requirements Operating Temperature Storage Temperature Relative Humidity Board Dimensions Address 000000 000007 000008 007FFF F00000 F3FFFF F40000 F4FFFF FF0000 FFFFFF Appendix A SYS68K CPU 3VA Specification 68010 CPU 10 MHz 68450 DMAC 10 MHz 68451 MMU 10 MHz with software programmable address translation paging and address range protection 68561 Multi Protocol Communication Controller with software selectable baud rate from 110 to 38400 baud and variable I O signal assignment 68230 PI T for local control and timer function 58167 RTC with Calendar and on board battery backup 32K bytes of static RAM 70ns 256 bytes of EPROM max JEDEC compatible devices Full VMEbus compatible interface with a slave bus arbitration Slot 1 Control functions 4 level prioritized bus arbiter with bus clear generation 32K bytes of monitor called SYS68K 3 MONITOR 5V 3 0A 12V 200mA max 12V 200mA max 0 to 50 degrees C 50 to 85 degrees C 0 95 non condensing Double
31. e 15 amp amp deltime 15 lt deltime16 amp amp deltime I 6 lt deltime 17 amp amp deltime 17 lt deltime18 amp amp deltime 1 8 lt deltime 19 amp amp deltime 19 lt deltime20 amp amp deltime20 lt deltime2 I amp amp deltime2 1 lt deltime22 amp amp deltime22 lt deltime 23 amp amp l deltime23 lt deltime24 amp amp deltime24 lt deltime25 amp amp deltime25 deltime26 amp amp deltime26 deltime 27 amp amp deltime27 deltime28 amp amp deltime28 deltime29 amp amp deltime29 deltime30 amp amp deltime30 deltime 31 outstr 1 n rDelay is OK outstr 1 n rDelay is not OK else finish 1 terminate define size23 128 char stack23 size23 void t23 main void 47 while finish 1 while stop 0 deltime activate 24 terminate sese ske 2 2 ok ok Delay task s 7 2 k se se se ae ae k kk k k k k k kk k kk k k K k k K K K Jf 7 ke eee ee ee eee k k T oe oe ak ak ak ak ak ak ak ak ak ak k kk Wait for next per task eee ee K K define size24 128 char stack24 size24 void 24 main void outstr 1 n rChecking Wait for next period again finish 0 stop 0 activate 27 while 1 time 0 init_period_time 1 wait_for_next_period off_period_start stop 1 time 1 time activate 25 terminate define size25 128
32. e two arbiters works are if a cpu board already has the bus and a cpu with higher priority wants it the priority arbiter sends a BCLR to the bus master the round robin arbiter don t acts on priority instead it searches for a bus request When a bus request is found the arbiter stops on the current request level And upon release of the bus the arbiter starts to search for a new bus grant on current request level minus one and if no request there decrease the level again When level 0 has been checked level 3 is entered and the search continues When a multiprocessor system is going to be built a round robin arbiter is preferbly used Figure 3 shows where each part of the system is placed 29 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot arbiter CPU 3VA CPU 3VA CPU 3VA BR1 BR2 bus Figure 3 30 6 Software development In this chapter the software development for FORCE SYS68K boards with Microtec Research Microtec tools on a PC is described The tools which are described are Microtec ASM68K assembler LNK68K linker XRAY68K debugger MCC68K ansi C compiler A serial cabel is used to download programs and XRAY68K debugger to the CPU boards from the PC note that COM68000 or other downloaders can be used to download programs when the on board debugger wants to be used COM68000 is a C program implemented of people working at M lardalens University IDt Department of Real Time Computer Systems FORCE on boar
33. eltime 0 delay 2 deltime2 deltime deltime 0 delay 3 deltime3 deltime deltime 0 delay 4 deltime4 deltime stop 1 activate 17 terminate stop 0 deltime 0 delay 5 deltime5 deltime deltime 0 delay 6 deltime6 deltime deltime 0 43 int deltime10 int deltimel 1 int deltime12 int deltime13 int deltime 14 define size18 128 char stack18 size18 void t18_main void while 1 int deltime 15 int deltime 16 int deltime17 int deltime 18 delay 7 deltime7 deltime deltime 0 delay 8 deltime8 deltime deltime 0 delay 9 deltime9 deltime stop 1 activate 18 terminate stop 0 deltime 0 delay 10 deltime 1 0 deltime deltime 0 delay 11 deltime 1 1 deltime deltime 0 delay 12 deltime 12 deltime deltime 0 delay 13 deltime 13 deltime deltime 0 delay 14 deltime 14 deltime stop 1 activate 19 terminate 44 int deltime19 define size19 128 char stack19 size19 void 19 main void while 1 int deltime20 int deltime21 int deltime22 int deltime23 int deltime24 define size20 128 char stack20 size20 void t20 main void while 1 stop 0 deltime 0 delay 15 deltime15 deltime deltime 0 delay 16 deltime16 deltime deltime 0 delay 17 deltime17 deltime deltime 0 delay 18 deltime 1 8 deltime deltime 0 delay 19 deltime 1 9 deltime stop 1 activate 20 termin
34. fore while 1 ts39 0 ts40 0 ts41 0 ts42 0 wait for semafore for 1 39 1 lt 42 1 activate 1 while task status 39 4 ll task status 40 4 ll task status 41 4 ll task status 42 4 release semafore while task_status 39 0 II task_status 40 0 ll task status 41 0 l task status 42 0 if t5339 0 II ts40 0 II ts41 0 I ts42 0 outstr 1 n rSemafore is not OK 1 1 ts42 0 ts43 0 ts44 0 ts45 0 wait for semafore for 1 42 1 lt 45 1 activate 1 while task status 42 4 ll task status 43 4 ll task status 44 4 ll task status 45 4 release semafore while task_status 42 0 II task_status 43 0 ll task status 44 0 ll task status 45 0 56 if ts42 0 II ts43 0 II ts44 0 II ts45 0 amp amp 1 0 outstr 1 n rSemafore is not OK 1 1 else if 1 1 outstr 1 n rSemafore is OK activate 54 terminate Jf ke ae ae ae ae ae ac ae ak ak ak ak ak ak k kkk k End Semafore tasks VOLES s k k KK k k K k k 2K 4 flag task s 7 2 2 2 se se se ae k kk k k k k k kk k k k k int tf47 define size47 128 char stack47 size47 void t47 main void while 1 int 448 define size48 128 char stack48 size48 void t48 main void while 1 int 449 define size49 128 char stack49 size49 void t49 main void
35. got set the task is scheduled into the system again and if it has the highest priority the RTU94 interrupt the cpu to switch to that task Example void task void wait for flag 27 Set reset flag void set or reset flag int set reset This function set or reset the event flag set reset gt set event flag 0 reset event flag Example void task void set or reset flag 1 set or reset flag 0 Help function Get status on a local task int task status int task id This function returns the status of a task that runs local task id task identity number an id number between 0 to 63 Status that a task can be in O Activated 2 Running 32Wait Event Flag 4 Wait For Semafore 5 Wait For Next Period 6 Delay 7 Wait Irg External Example void task void int a task status 1 gets the status of task 1 28 5 System configuration In this chapter gives an example of how to configure a realtime system using the RTU94 and FORCE VME boards The following configuration is only an example It is possible to use more or less VME boards or other VME boards than FORCE The system that we use consist of one VME box with three SYS68K CPU 3VA boards and one SYS68K DRAM 1 The IACKIN must be connected to IACKOUT with a jumper on the VMEbus on slots with no SYS68K cards inserted See appendix A for short information and jumper settings for the FORCE cpu and memory boards The board
36. in stack12 size12 CPUNR init task tcb 5 13 t13 main stack13 size13 CPUNR init task tcb 6 14 t14 main stack14 size14 CPUNR init task tcb 7 15 t15 main stack15 size15 CPUNR init task tcb 0 16 t16 main stack16 size16 CPUNR init task tcb 1 17 t17 main stack17 size17 CPUNR init task tcb 2 18 t18 main stack18 size18 CPUNR init task tcb 3 19 t19 main stack19 size19 CPUNR init task tcb 4 20 t20 main stack20 size20 CPUNR init task tcb 5 21 t21 main stack21 size21 CPUNR init task tcb 6 22 t22 main stack22 size22 CPUNR init task tcb 7 23 t23 main stack23 size23 CPUNR init task tcb 0 24 t24 main stack24 size24 CPUNR init task tcb 1 25 t25 main stack25 size25 CPUNR init task tcb 2 26 t26 main stack26 size26 CPUNR init task tcb 3 27 t27 main stack27 size27 CPUNR init task tcb 0 28 t28 main stack28 size28 CPUNR init task tcb 1 29 t29 main stack29 size29 CPUNR init task tcb 2 30 t30 main stack30 size30 CPUNR init task tcb 0 31 t31 main stack31 size31 CPUNR init task tcb 1 32 t32 main stack32 size32 CPUNR init task tcb 2 33 t33 main stack33 size33 CPUNR init task tcb 3 34 t34 main stack34 size34 CPUNR init task tcb 4 35 t35 main stack35 size35 CPUNR init task tcb 5 36 t36 main stack36 size36 CPUNR init task tcb 6 37 t37 main stack37 size37 CPUNR init task tcb 7 38 t38 main stack38 size38 CPUNR init task tcb 0 39 t39 main stack39 size39 CPUNR init task tcb 1 40 t40 main stack40 s
37. inserted in slot 1 on the VMEbus is configured as the system master i e it drives SYSCLK and handles the arbitration on the bus The other boards are configured as system slaves i e they do not drive SYSCLK and do not handles the arbitration We uses two types of arbiter to control the bus mastership on the VME bus One is a priority arbiter placed on a CPU 3VA board and one is a round robin arbiter implemented on a XILINX 4010 Both are 4 levels arbiters The arbiter uses the three bus request lines BRO BR3 the three bus grant out lines BGOOUT BG3OUT the bus clear line BCLR is not used on the XILNX arbiter the bus busy line BBSY to control the bus Each cpu board has a bus master timeout we use 1 5us for timeout and bus request level BRO BR3 A bus master realease the bus after the timeout time or after getting a BCLR signal from the arbiter When a cpu board wants the bus it drives its BRx low The arbiter detects the if the bus is free BBS Y is high the arbiter drives the BGxOUT low The bus grant then passes by cpu boards until it gets to one which is driving bus request on same level as the bus grant level this is usually called the bus grant daisy chain After getting a bus grant the cpu board drives BBSY low and realese BRx Because of the bus grant daisy chain the cpu card which is located closest to the arbiter which is located in the first slot has the highest priority The differences between how th
38. interface to the RTU 3 Clocktick interrupts Clocktick interrupts are a necessity for updating timequeues e g delay queues and controllfunctions e g watchdogs when using a realtime kernel in software The time resolution of the system is dependent on the clocktick frequency of the system In nowadays fast system with few tasks the time between clockticks are 1 to 2 ms RTK_IRQ IRA CPU RTK TASK Time CPU Figure 5 Clocktickadministration in Real Time Kernels implemented in software 67 clock tick interrupt is external interrupt from timer see fig 3 When interrupt reach the cpu it saves registers on the stack i e an overhead time approx 10 us 1 The realtime kernel starts to administrate 2 the cpu i e control the timequeues schedule tasks and in some cases check that time demands are fulfilled The administration time is hard to estimate since it s not stated in any of the commercial realtime kerenls that we have analysed data sheets This can be due to that a system needs different time to administrate few tasks and alot of tasks Some measurings on a commercial realtime kernel shows that an unloaded needs approx 200 us administration time 2 When the RTU is used the executing task is not interrupted until a task with higher priority is found by the RTU in the ready queue TASK A Time CPU Figur 6 Clocktickadministration is done by the
39. iodic start Delay 23 23 23 24 24 25 Interrupt Handling Function 25 Wait for interrupt 25 Watch Dog Functions 26 Initialize a watchdog 26 Reset a watchdog timer 26 Flag Functions 27 Wait for semafore 27 Release semafore 27 Wait for flag 27 Set reset flag 28 Help function 28 Get status on a local task 28 5 System configuration 29 Appendix A 33 SYS68K CPU 3VA 33 Specification 33 Memory Map 33 Address Assignment of the I O Devices 34 Jumper Settings 34 SYS68K DRAM 1 35 Specification 35 Jumper Settings 36 Appendix B 37 Testprogram 37 Appendix C 66 Appendix D 67 Clocktick interrupts 67 Service calls 69 Interrupt handling 71 Appendix E 73 Hardwarespecification for 50k FPGA prototypeboard 73 Block scheme for 50k FPGA prototypeboard 74 Component placement on 50k FPGA prototypeboard 75 Appendix F 76 References 77 1 Introduction Overview The RTU94 is a realtime kernel on a chip for use with VME microprocessor boards It can handle 1 to 3 processors 64 tasks and 8 priority levels VHDL were used as design language the advantage of using VHDL is that it s easy to change the functionallity of in this case the RTU94 e g change the scheduling algorithm to static instead of priority preemtive which is used now RTU94 has a VME interface used for communicating with the microprocessors and a scheduler and a set of services which are presen
40. is calculated by adding a base address to the address offset given in table 1 CPU STATUS REGISTER There are three cpu status registers in RTU94 one for each CPU It contains the status of respectively cpu ACK NEXT TASK ID IRO TSW FLAG TSW FLAG STATUS 5142 18 17 161 4 312 1101 RATTET ACK NEXT TASK ID 0 No acknowledge 1 CALL NEXT ID acknowledge IRQ TSW FLAG 0 No interrupt 1 Interrupt signal TSW request TSW FLAG STATUS 0 5 on 1 TSW off Not used RTU_STATUS_REGISTER It contains the R TU status Bit SVC RETURN is affected when an event flag or a semaphore wants to be allocated If itis set to Othe allocation succesed else it is set to 1 SVC RETURN SVC ACK FLAG Not used SVC RETURN SVC status See description of service calls for further information SVC ACK FLAG 0 No acknowledge 1 Service call acknowledge RTU CONTROL REGISTER Controls the on chip timer clock which is used by time dependent services e g wait for next period TIMER CONTROL Not used TIMER CONTROL 0 Timer clock enabled on 1 Timer clock disabled off NEXT TASK ID Holds information about the currently executing task id During taskswitch it is used to inform the CPU about the next task id to be executed There are three next task id registers in RTU94 one for each CPU TASK ID 54211019 817 6 15 4 312 110 EST m Not used SVC INSTRUCTION REGISTER The RTU perform
41. ize40 CPUNR init task tcb 2 41 t41 main stack41 size41 CPUNR init task tcb 3 42 t42 main stack42 size42 CPUNR init task tcb 4 43 t43 main stack43 size43 CPUNR init task tcb 5 44 t44 main stack44 size44 CPUNR init task tcb 6 45 t45 main stack45 size45 CPUNR init task tcb 7 46 t46 main stack46 size46 CPUNR init task tcb 0 47 t47 main stack47 sizeA7 CPUNR init task tcb 1 48 t48 main stack48 size48 CPUNR init task tcb 2 49 t49 main stack49 size49 CPUNR init task tcb 3 50 t50 main stack50 size50 CPUNR init task tcb 4 51 t51 main stack51 size51 CPUNR init task tcb 5 52 t52 main stack52 size52 CPUNR 64 init task tcb 6 53 t53 main stack53 size53 CPUNR init task tcb 7 54 t54 main stack54 size54 CPUNR init task tcb 0 55 t55 main stack55 size55 CPUNR init task tcb 1 56 t56 main stack56 size56 CPUNR init task tcb 2 57 t57 main stack57 size57 CPUNR init task tcb 3 58 t58 main stack58 size58 CPUNR init task tcb 4 59 t59 main stack59 size59 CPUNR init task tcb 5 60 t60 main stack60 size60 CPUNR init task tcb 6 61 t61 main stack61 size61 CPUNR init task tcb 7 62 t62 main stack62 size62 CPUNR init task tcb 7 63 idle main stackidle sizeidle CPUNR activate 0 while 1 8 65 Note No Connection 20 015 data bus A0 A3 address bus pre EE s 1 NC Com to external IRQ INO External chip interrupt IRQ IN1 External interrupt IRO IN2 External interrupt
42. lease_semafore Description Release the semafore and the first task in the semafore queue gets it Arguments None Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 mamawa N U Not Used o 2 18 Wait for flag Description If the event flag is not set the task will be placed in the event flag queue until the flag gets set If the event flag is set the task will continue the execution Argument Cpu Nr a cpu number from 0 to 2 Affected register Bit SVC RETURN on STATUS REG is set to 0 if the event flag got allocated else 1 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N U Not Used Set or reset flag Description Set or reset the event flag Arguments Cpu Nr cpu number from 0 to 2 Set I all event waiting tasks starts and 0 all tasks that wait for flag are placed in the event flag queue Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cpu Nr N U Not Used End svc Description Tells RTU94 that a service call is finished Arguments None Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N U Not Used 19 4 C interface In this chapter the C functions avalible for RTU94 are explained Initialise a cpu to work with RTU94 Init void init int cpu nr This function initialise variables tables and lists wich are used by the cpu The cpu nr specifies which cpu number the cpu will have i e which taskswitch in
43. me1 lt deltime2 amp amp deltime2 lt deltime3 amp amp deltime3 lt delti me4 amp amp deltime4 lt deltime30 amp amp deltime30 lt deltime31 outstr 1 n rDelay again is OK outstr 1 n rDelay again is not else finish 1 terminate 50 define size30 128 char stack30 size30 void t30_main void while finish 1 activate 38 terminate while stop 0 deltime sese o ok ok ok Delay tasks 2 2 2 se k k k ae k k ie k k K 4 sese sk oe e ae ae ae ae ae ae he fe he he ak ak ak ak kk B vent flag tasks 7 7 2 z se se se k ae k eee k fe ie k int t 31 define size31 128 char stack31 size31 void t31 main void while 1 int 32 define size32 128 char stack32 size32 void t32 main void while 1 int 433 define size33 128 char stack33 size33 void t33 main void wait for flag tf31 1 terminate wait for flag tf32 1 terminate 51 while 1 int 34 define size34 128 char stack34 size34 void t34 main void while 1 int 1435 define size35 128 char stack35 size35 void t35 main void while 1 int 36 define size36 128 char stack36 size36 void t36 main void while 1 int t 37 define size37 128 char stack37 size37 void t3
44. r 2 to be on on off 1 or off on off 0 and suspends the when on off 1 task until the watchdog timer has expired 25 ms when time sync s period time is set to 0 5 ms After25 ms has expired the task is scheduled into the system again and if it has the highest priority the RTU94 interrupt the cpu to switch to that task Example void task void mit watch dog 1 1 Suspend task until watchdog 1 timer has expired 25 ms Watchdog 1 has expired 25 ms because no task has kicked the dog init watch dog 0 1 Turn off watchdog timer 1 Reset a watchdog timer void kik dog int dog nr This function reset the watchdog timer on watchdog with number dog nr 0 1 or 2 Example void task void kik dog 2 Reset watchdog 2 timer 26 Flag Functions Wait for semafore void wait for semafore void This function suspends the executing task until it has got the semafore After getting the semafore the task is scheduled into the system again and if it has the highest priority the RTU 4 interrupt the cpu to switch to that task Example void task void wait for semafore j Release semafore void release semafore void This function release the semafore and the next task in the semafore queue gets the semafore Example void task void release semafore Wait flag void wait for flag void This function suspends the executing task until the event flag is set After event flag
45. rds and how they should be configured used in a realtime system based on RTU94 Appendix B Testprogram a testprogram is presented to test all services for one cpu with the RTU94 Appendix C RTU94 pin assignment Appendix D Performance analysis a performance comparcion between RTU94 and commercial RTKs software based Appendix E Prototype a prototype board is described which can be configured to work as a RTU94 on a VME board Appendix F a list of publications related to the RTU94 project References Contents Preface 1 Introduction Overview Internal structure of RTU94 2 Communication Nan Register model of RTU94 Communication protocols Taskswitch Irq protocol 12 Terminate protocol 13 Service Call protocol 14 3 Service calls Activate Init task tcb Init period time Wait for next period Off period start Delay Wait irq external Init watch dog Kik dog Wait for semafore Release semafore Wait for flag Set or reset flag End svc 4 C interface Initialise a cpu to work with RTU94 Init 15 15 15 16 16 16 17 17 17 18 18 18 19 19 19 20 20 20 Task Management Functions Enable disable taskswitch 20 20 Initialize a task Activate a Task 21 21 Terminate task Switch task 22 22 Time Functions Timer on off Initialize the periodic time Wait for next period Disable per
46. stems it is probably greater differences Parameter transfering is a overhead time for a CPU Since the uses a bus to transfer parameters it can be alot of overheadtime for the CPU in the RTU M case This can be solved by using separately processor buses which makes bus conflicts impossible Supervisor functions e g checking task deadlines can easily done in the without loading the CPU 70 Interrupt handling In this section a comparsion between comercial RTK interrupt handlers and the RTU interrupt handler are done Figure 7 shows the overhead time for the CPU when a commercial RTK is used when an interrupt occurs Time 1 is the interrupt handler time approx 10us i e saving registers on stack etc 2 shows the time which the RTK uses for scheduling and saving the interrupt in an event list The top fig shows the case when the interrupt task has lower priority than the running task The bottom fig shows the same event but with an interrupt task with higher priority Ext IRG IRQ CPU Ko ls RTK 18 T3 TASK amp 1 Time CPU EXT IRQ CPU I 1 TASK A 1 A IAGLTASK Time CPU Figur 7 Top figure shows whats happening in the CPU when the interrupt has lower priority than the running task Bottom figure shows when the interrupt task has higher priority Since the RTU has a interrupt handler all interrupt tasks can be scheduled as all other tasks The priority
47. system based on RTU94 The Real Time system configuration is see figure 1 One to three application processors These have contact with the VME bus and one interrupt each The interrupt is used to start the task switch routine in the processor Each processor has a local memory for local tasks The RTU94 is separate PCB board The RTU94 chip contains whole Real Time kernel and VME bus interface The only things needed outside the chip are some buffers and clock generators There are twelve 16 bit registers and one 8 bit for data communication between application processes and the RTU94 global memory for global tasks The global tasks are dynamically scheduled on all three processors the local tasks are locked to one processor and the local memory The analyser processor is for graphical display of system status and operation to provide developers with better visibility into their applications A PC is used for the graphical interface The analyser processor is optional Work station Analyzer Application Proceasor Processor Optional 0 External Interrupts Applicaton Processor 1 Application Processor Global Memory for global 2 tasks figure 1 System configuration Internal structure of RTU94 The RTU consists of a number of units which handles the different functions in the kernel see figure 2 Functions within R TU94 Scheduler The scheduling concept on RTU94 is
48. t for next period off period start stop 1 time8 time activate 12 terminate stop 0 time 0 mit period time 16 wait for next period off period start stop 1 time16 time activate 13 terminate 41 while 1 if time1 time2 amp amp time2 time4 amp amp time4 time8 amp amp time8 timel6 outstr 1 n rWait for next period is OK else outstr 1 n rWait for next period is not OK activate 14 terminate define 17 14 128 char stack14 size14 void t14 main void while 1 finish 1 terminate define size15 128 char stack15 size15 void t15 main void while finish 1 while stop 0 time activate 16 terminate Jf ke oe oe teteteteteteteteteteteres Bag Wait for next per task s 28 2 kkk eee Jf ke eee eee ee ee eee he se TER taskg deltime int deltime0 int deltimel int deltime2 int deltime3 int deltime4 42 define size16 128 char stack16 size16 void t16_main void outstr 1 n rChecking Delay finish 0 stop 0 activate 23 while 1 int deltime5 int deltime6 int deltime7 int deltime8 int deltime9 define size17 128 char stack17 size17 void t17 main void while 1 deltime 0 delay 0 deltime0 deltime deltime 0 delay 1 deltime 1 deltime d
49. ted in Chapter 3 Since RTU94 schedule each task no clock ticks are needed on the microprocessors But each microprocessor must be able to handle one external interrupt the taskswitch interrupt from RTU94 and be able to communicate over bus Three microprocessors can be served and tasks can be initiated to be scheduled to run on a specific cpu or whichever cpu that have time to execute it Advantages of using a hardware kernel Moveable The RAM which RTU94 use is implemented on the chip The instruction format doesn t change If the cpu can communicate over a bus similar to e g bus can be connected to serve it The only software segment which must rewritten on a new cpu type is the assembler code for task switch Performance and determininism The performance increases and in some cases the time for R TU services can be neglected except the taskswitch routine which is implemented in software E g scheduling of a task is done within 5 to 80 clock cycles 1 5 u seconds with a 16 Mhz clock in the worst case and furthermore the scheduling doesn t load the cpu Deterministisc execution of the service instructions The RTU takes of the scheduling queues clocktick administration Therefore it s easier to calculate the execution time for a system The cpu load is dependent on how many active tasks and in which state they are in when a software kernel is used No clock
50. terrupt level it must respond to cpu nr 0 cpu responds to RTU taskswitch interrupt at level 4 1 cpu responds to taskswitch interrupt at level 5 2 cpu responds to RTU taskswitch interrupt at level 6 Example void main void init 0 Initiate cpu to work as cpu 0 i e respond to taskswitch interrupt at level 4 Task Management Functions Enable disable taskswitch void on tsw void This function makes RTU taskswitch enabled on a cpu void off tsw void This function makes RTU taskswitch disabled on a cpu Example void task void off tsw section where RTU taskswitch is not allowed on tsw 20 Initialize task void init task tcb int prio inttask id void task char stack int stacksize int cpu nr This function initialise a tasks TCB and on which cpu specified by cpu nr it will run on cpu nr 0 the task is running on cpu 0 I the task is running on cpu 1 2 the task is running on cpu 2 3 the task is running on whichever cpu that has time to execute it prio task priority a number between 0 high priority to 7 low priority task id task identity number an id number between 0 to 63 se note about id number 63 task pointer to the start address of the task stack pointer to an allocated stack for the task stacksize size of the stack which is allocated for the task Example extern void task 1 void define size 1024 Stack size char st
51. the semafore get released When a task get the semafore it is send to the redy queue and the tasks in the queue moves one step ahead Flag Can hold four tasks in the event flag queue When the flag get set all tasks in the queue are send to the ready queue External interrupt Holds a task until an interrupt corresponding to the task s interrupt level occurs then the task is send to the ready queue VME interface Is the I O between the realtime functions and the VME bus Consists of thirteen registers see chapter 2 TIME OUT Taskswitch interrupt I CPU BUS figure 2 Internal structure of RTU94 2 Communication In this chapter the registers 94 are first described and then the communication protocols to RTU94 are explained Register model of RTU94 Table 1 shows the register set RTU94 Each CPU have three dedicated registers cpu status register next task id and cpu control register There are two registers that holds the overall RTU information rtu status register and rtu control register Finally there are two service call SVC registers svc instruction register and svc semaphore register Register name Address offset Read Size hex Write to 2 STATUS REGISTER 6 16bit RTU CONTROL REGISTER 8 NEXT TASK ID 0 to 2 SVC INSTRUCTION 10 R w E E CPU CONTROL REGISTER 16 18 1A 16 bit 0 to 2 Table 1 The register address
52. the service which are written to this register Bit 12 to 15 are reserved for the service code and bit 0 to 10 are used for service call data see chapter 3 for more details about service calls SVC OPERATION CODE SVC DATA Not used SVC SEMAPHORE REGISTER 10 This register is used to protect the svc instruction register in a multiprocessor enviroment Any task that wants to use the svc instruction register must take the semaphore The semaphore is taken by writing 1 to bit 7 SVC SEMAPHORE 17 1615 14 3121101 Eq ot used SVC SEMAPHORE 0 SVC semaphore cleared 1 SVC semaphore set CPU CONTROL REGISTER There are three cpu control registers in RTU94 one for each CPU Each register controls taskswitch on off and acknowledge and also the call for a new task for respectively cpu TSW FLAG CONTROL CALL NEXT TASK ID TSW ACK FLAG 5142 918 17 161 4 312 110 AAG ERA Py EA TSW FLAG CONTROL 0 Set TSW on 1 Set TSW off CALL NEXT TASK ID 0 No request 1 Reguest new task id TSW ACK FLAG 0 No acknowledge 1 TSW acknowledge Not used 11 Communication protocols The communication with the RTU94 is done in three different ways Task switch Irq The activates the interrupt to the processor card to interrupt the running task and start the task switch routine Terminate task The service call terminates and activates the RTU94 to give next task id to run Service call
53. time functions are not allowed timer on Note The timer off turns off the time sync clock and all the functions which use that clock will be out of function Therefore you must be aware of what you are doing with the system because one cpu might want to use time functions Initialize the periodic time void init period time int per time This function initialise the periodic time per time for a task per time when time sync s period time is set to 0 5 ms gt 0 5 ms period time 2 gt 2 5 ms period time 4 gt 25 ms period time 8 gt 250 ms period time 16 gt 2 5 s period time Note The period time can be change by changing the clock frequency on time sync Only task 0 32 can be initiated to be periodic Example void task void init period time 4 Initialise the period time to 25 ms when time sync s period time is set to 0 5 ms 23 Wait next period void wait for next period void This function suspends the executing task until the period time has expired After expired period time the task is scheduled into the system again and if it has the highest priority the RTU94 mterrupt the cpu to switch to that task Example void task void init period time 2 Initialise the period time to 2 5 ms when time sync s period time is set to 0 5 ms wait for next period the task until the period time has expired Note Initializeing of period time m
54. tives 31 Links the object obj files specified in the command cmd file and generate absolute abs file and a map map file Example LINK filename cmd The example above uses following batch file LINK BAT Ink68k c 1 cmd o 1 abs m gt 1 map Linker command file CHIP 68010 Specifies target microprocessor LISTABS INTERNALS PUBLICS Is used when downloading with IEEE 695 format LISTMAP INTERNALS PUBLICS FORMAT 5 Is used when downloading with motorola S record format FORMAT IEEE Is used when downloading with IEEE 695 format PUBLIC STACKTOP 1000 Defines were the stack starts SECT local 1000 Address where local memory starts SECT global 100000 Address where global memory starts ORDER local KERNCODE KERNDATA code var vars literals strings const zerovars ocal is changed to global if global memory is used for the program INDEX A5 vars Used when relative addressing LOAD RF KER OBJ Routines for communicating with RTU94 and performing taskswitch LOAD CUSKCRIT KER Critical routines that RF KER uses LOAD any objects file LOAD BASINOUT OBJ Hardware dependent 1 routines LOAD INPOUT OBJ Hardware independent i o routines LOAD C MCC68K 68000 MCC68KAB LIB Used when absolute addressing LOAD C MCC68K 68000 MCC68KAS5S LIB Used when relative addressing END Downloading program to cpu board via serial cable If using XRAY68K
55. tus 52 23 ll task status 53 23 set or reset flag 1 while task status 50 20 ll task status 51 0 Il task_status 52 0 II task_status 53 0 if tf50 O II tf5 1 0 II tf52 0 II tf53 0 amp amp 0 outstr 1 n rEvent flag again is not OK 59 else if 1 1 outstr 1 n rEvent flag again is OK activate 62 terminate ese se sese ae KKR ae ae ae ae ae ae ak ak ak ak ak ak ak ak kkk End Event flag task s 4 3 3 sl se k k se ae ae k he k kk k k k k k K k k K K Jf ke eee ee eee he fe fe fe he k sese EK KK R ae ae ae ae he he he he ak ae a a a k k k Semafore tasks z z 2 2 ee ee kkk k int ts55 define size55 128 char stack55 size55 void t55_main void while 1 int ts56 define size56 128 char stack56 size56 void t56_main void while 1 int ts57 define size57 128 char stack57 size57 void t57_main void while 1 wait_for_semafore ts55 1 release_semafore terminate wait_for_semafore ts56 1 release_semafore terminate 60 int 558 define size58 128 char stack58 size58 void 58 main void while 1 int 559 define size59 128 char stack59 size59 void t59 main void while 1 int 560 define size60 128 char stack60 size60 void t60_main void while 1 int 561 define size61 128 char stack61 size6
56. typ 5V STDBY 1 0A max Standby Mode 0 to 50 degrees C 50 to 85 degrees C 0 95 non condensing Double Eurocard 234x160mm 9 2 x 6 3 35 Jumper Settings Base address settings Base Address Selection of the Control Status Register FFF000 Jumper Connection between BRI BR2 5 12 6 11 7 10 8 9 No jumpers connected Memory Areal settings start address 100000 end address 13FFFF Jumper connections between FA 1 FB1 FA 2 FB2 FA 3 FB3 5 5 FA 6 6 Memory 2 settings start address 140000 end address 17FFFF Jumper connections between KA 1 KB1 KA 2 KB 2 KA 3 KB 3 KA 5 KB 5 For more information about jumper settings and jumpers see FORCE SYS68K DRAM 1 2 user s manual 36 Appendix Testprogram In this appendix a testprogram is presented The testprogram tests all avalible services in a sequence on one cpu If the testis passed itis quite sure that the system is ok for one cpu To test different cpu s change the defined CPUNR include lt stdio h gt include sercom h include rf_ker h define CPUNR 2 CPU 2 is tested Change CPUNR to the cpu that is wanted to be tested 0 or 1 or 2 sese oF sk ok ok ok ok o o o o HE k k SEE GE R GE E EE k kk oe oe 7 ESSEN KER a KER SN taskg 4 k se se k k ae k ae ae ae ae fe fe k fe K k he ie ie k int kick define size0 128 char stackO size0 void t0
57. until ACK NEXT TASK ID is cleared and then it gets new task id to switch to by reading NEXT TASK ID After reading next task id the cpu must if you want other tasks to be scheduled on the cpu clear TSW FLAG CLEAR CALL NEXT TASK CPU amp TSW OFF RTUS4 LLHHI eru controL REG CPU ACKNEXTTASK RTU94 TOTTI CPU STATUS REG END CALL NEXT TASK RTU94 TT Jo CONTROL REG NEXT TASK READY RTU94 To cPULSTATUS REG NEXT TASK NEXT_TASK_ID GET NEW TASK CPU amp TSW_ON RTUS4 NEXT TASK NEXT_TASK_ID L T To cpu CONTROL 13 Service Call protocol Operation 1 The cpu must set TSW FLAG CONTROL on CPU CONTROL REG to make sure that no taskswitch from RTU94 is comming and then allocate the SVC SEMAPHORE REG if it is a multiprocessor system to make sure that no other cpu is gonna use the SVC INSTRUCTION REG After that the cpu can write the service call to SVC INSTRUCTION REG 2 RTU94 sets SVC ACK FLAG on STATUS REG when it start to perform the service When wait for semafore or wait for flag service is performed the SVC RETURN on RTU STATUS REG is affected 3 The cpu must wait until SVC ACK FLAG is set and then it write the end svc to SVC INSTRUCTION REG to inform RTU94 that its the end of the service call 4 RTU94 clear SVC ACK FLAG 5 The cpu must wait until SVC ACK FLAG is cleared to be sure that the service is performed After SVC ACK FLAG is cleare
58. ust done for the task before waiting for next period Disable periodic start void off period start void This function disables periodic start for the task Example void task void off period start 24 Delay void delay int delay time This function suspends the executing task until the delay time has expired After expired delay time the task is scheduled into the system again and if it has the highest priority the RTU94 interrupt the cpu to switch to that task delay time when time sync s period time is set to 0 5 ms 0 gt trig start synchronization with the time sync clock 1 gt 0 5 ms 2 gt 1 ms 31 gt 15 5 ms Example void task void delay 2 Suspend the task at least 1 ms when time sync s period time is set to 0 5 ms Note Only task 0 32 can be delayed Interrupt Handling Function Wait for interrupt void irq external int irq nr This function suspends the executing task until an interrupt with number irq nr 0 1 2 or 3 has occured After the interrupt has occured the task is scheduled into the system again and if it has the highest priority the RTU94 interrupt the cpu to switch to that task Example void task void wait irq external 1 Suspend task until interrupt 1 has occured 25 Watch Dog Functions Initialize a watchdog void init watch dog int on off int dog nr This function initialise a watchdog with number dog nr 0 1 o
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