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LDI Demonstration Kit User Manual
Contents
1. 10 TX BOARD JUMPER DEFAULT 0 11 LVDS MAPPING BY IDC CONNECTOR 12 Mapping TOF Old EERE Hed seg 12 Mapping for New tay E PEE 13 TX OPTIONAL PARALLEL TERMINATION FOR 14 BONSBIEEOFMATERIAES Ret e dE Koc n Ea e Md 15 16 RX BOARD JUMPER DEFINITION 0 EEEE 17 RX BOARD JUMPER DEFAULT 5 5 88 17 LVDS MAPPING BY IDC CONNECTOR 0 0 1 11 18 Mapping Tor Old M da eit e PE E Bra 18 Mapping for New 2 30 cao d s oes tutte usata dat eaedem oo 19 RX OPTIONAL SERIES TERMINATION FOR 20 BOM BILL OF MATERIALS rae te HER 21 JUMPER SETTING EXAMPLES 1 OLD MODE
2. Position Tolerance Unless Noted 0 00 Inch t 1 IEOR E Positioning Boss 2x Dimensions Reference only Ordering Information 1 210 Contact Quantity See Table TS 0755 06 Note Use M2 5x8mm screws to mount to panel with max thickness of 2 0 mm Sheet 2 of3 3M Interconnect Solutions Division 6801 River Place Blvd For technical sales or ordering information call Austin TX 78726 9000 800 225 5373 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 30 of 34 LDI Demonstration Kit User Manual 050 Mini D Ribbon Connectors Surface Mount Right Angle Receptacle Shielded 102XX 1210VE Series Contact Dimensions Quantity 002 002 002 Recommended Board Layout 14 930 23 64 500 12 70 1 325 8 26 20 1 081 27 45 650 16 51 475 02 viewed from connector side 26 1 230 31 26 800 20 32 625 15 88 Solder Pads for 40 1 581 40 15 1 1 150 2921 975 center spacing Solder Tail See 24 77 below for more detail 50 1 831 46 50 1 1 400 35 56 1 225 31421 center spacing 025 0008 4 016 0004 11813 01 122 093 0004 110 004 2 Screw Lock
3. nennen enhn anna annuus 22 18 BIT OR 24 BIT SINGLE PIXEL OLD 52 OR UO C I thee 22 18 BIT OR 24 BIT DUAL PIXEL OLD 23 JUMPER SETTING EXAMPLE 2 NEW MODE 24 18 BIT OR 24 BIT SINGLE PIXEL NEW MODE 253 itt ec tt 24 18 OR 24 BIT DUAL PIXEL NEW 25 26 ADDITIONAL 27 APPLICATION NOTES ie RERO te 27 26 MINI D RIBBON CABLE AND 20 rer rer ree ree rete rennen 28 TRANSMITTER AND RECEIVER 8 1 6 nnne nnne rrr 35 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 2 of 34 LDI Demonstration Kit User Manual Introduction National Semiconductor s Interface Products Group LDI demo kit contains a Transmitter Tx demo board and a Receiver Rx demo board along wit
4. QN9SQ 1 0 NLY div NZY WL di 1 Ne V QA NYY dev TE QA Qd uonisod 92 cc c ON 7 7 7 Am 2 RU NYY IU NSY IN9v dlv AOIAAC LXAN SHOLSIS3H NOLLVNIINSH3 L LNNOW 3 LON QN9 OND punoJ etj ser 82 pue 2 SUld 29 SLNdLNO 100 90 Jequieides AepsinuL p AJY XH CLL L89AEIQT ci JequinN 188A amp IG1 oneueuos pjeog oueq ONASA ONASH 1294018 ON 371139 118 31VHvdds OL LNO ATIVNOLLN3 LNI GALYOHS 002 gz p AJY XY cLL L89AEIQT 1ueuunoo CLL L88AE IQ 1 SAM 1531 1531 QN9 SQ 1 DOA
5. GND Vcc GND Vcc OFF Tx powers down ON Tx is operational BAL DC BALance OFF JP4 GND Vcc GND Vcc Old Mode DC Balance OFF New Mode DC Balance ON PLLSEL PLL SELect auto range o LOW HIGH JP5 GND Vcc GND Vcc LOW auto range OFF HIGH auto range ON FDE Rising or Falling Data Enable Rising o Falling JP6 GND Vcc GND Vcc DUAL DUAL single mode Single Dual JP7 GND Vcc GND Vcc When NO jumper is used itis in Single to Dual Mode 1 In Old Mode the R_FDE pin is ignored by both the Tx and Rx when operating in Single DUAL LOW or DUAL DUAL HIGH mode When the transmitter is operating in Single to Dual Mode DUAL 1 2 Vcc the R_FDE pin must be set HIGH if active data when DE signal is HIGH In New Mode R_FDE pins of both Tx and Rx boards MUST set to HIGH if DE signal is High during active data R_FDE pins must set to LOW when DE signal is LOW during active data National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 10 of 34 LDI Demonstration Kit User Manual Tx Board Jumper Default Settings The default setting for the Tx board is set to Old Mode Dual pixel mode and with pre emphasis Jumper Jumper Name Purpose Settings Number PRE PRE Emphasis o JP1 GND Vcc R FB Rising or Falling data strobe JP2 GND Vcc PD PowerDown JP3 GND Vcc BAL DC BALance Old Mode GND Vcc PLLSEL PLL SELelect auto range
6. 138 3 5 256 6 5 187 max 14 751 088 2 223 see notes below ockstand Solder Pad Outline PCB Ref Edge 0 079 804 2X Solder Tail Layout Detail 5 Correspond to Connector Contact Shown on Previous 7 6 5 4 3 2 1 w Connector Position Top Row 14 Pos Last 14 Pos 1 PCB O Position Bottom Row 10 2 1 V Connector Position 12 11 20 Pos Last 20 Pos O Position Bottom Row 17 16 15 14 13 PCB Ref Edge 19 18 1 v Connector Position Top Row 13 12 11 10 9 3 2 26 Pos Last Pos 26 25 24 23 22 21 PCB 20 19 18 Ref 17 16 15 14 Position Bottom Row Edge 40 Pos 20 19 18 17 16 15 14 13 12 11 1 V Connector Position 1 24 23 22 40 39 38 37 36 35 34 33 32 31 2 PCB Ref Edge 30 0 Position Bottom Row Last Pos 50 25 24 23 22 21 Pes Last 50 49 48 47 46 Pos 12 37 36 11 10 1 v 35 3
7. JP5 GND Vcc FDE Rising or Falling Data Enable JP6 GND Vcc DUAL DUAL single mode JP7 GND Vcc An adjustable potentiometer 2K ohm is mounted at location R48 This allows emphasis to be adjusted only if JP1 has a jumper to VCC Use a number 1 4mm jewelers screwdriver to adjust R48 Turning clockwise will increase the pre emphasis value Turning counterclockwise will decrease the pre emphasis value R48 should be adjusted to reduce overshoot If no jumper is used the pre emphasis value will be 0 7V See Tx Features and Explanations Page 6 Pre Emphasis for description of feature National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 11 of 34 LDI Demonstration Kit User Manual LVDS Mapping by IDC Connector The following two figures show how the Tx inputs are mapped to the IDC connector It is also printed on the demo boards and to each of the eight LVDS channels Note Refer to AN 1127 for suggested mapping schemes Mapping for Old Mode Transmitter Board 50 pin IDC Connector 50 pin IDC Connector Pin 1 Pin 16 15 14 A2 gnd B13 gnd B12 gnd B11 M gnd B10 gnd G17 G16 gnd G15 gnd G14 gnd G13 Al gnd G12 gnd G11 gnd Gio 0 gnd 16 R15 gnd R14 gnd
8. JP3 GND Vcc BAL DC BALance New Mode JP4 GND Vcc PLLSEL PLL SELelect auto range JP5 GND Vcc Rising or Falling Data Enable JP6 GND Vcc DUAL DUAL single mode JP7 GND Vcc An adjustable potentiometer 2K ohm is mounted at location R48 This allows emphasis to be adjusted only if JP1 has a jumper to VCC Use a number 1 4mm jewelers screwdriver to adjust R48 Turning clockwise will increase the pre emphasis value Turning counterclockwise will decrease the pre emphasis value R48 should be adjusted to reduce overshoot If no jumper is used the pre emphasis value will be 0 7V See Tx Features and Explanations Page 6 Pre Emphasis for description of feature 2 In Balanced Mode New Mode R_FDE pin pin 21 MUST be set to HIGH if DE signal pin 56 is HIGH during active data R_FDE pin must set to LOW when DE signal is LOW during active data Note A In single pixel mode only through TxOUT3 LVDS channels 0 and their associated inputs are active TxOUT4 through TxOUT7 and their associated inputs and CLK2 are disabled for power savings National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 24 of 34 LDI Demonstration Kit User Manual 18 bit or 24 bit Dual Pixel New Mode The jumper settings below are for New Mode Dual to Dual pixel application For Tx Board The Rx board jumper settings in this application is the same as the
9. PLLSEL pin 5 JP5 1 Auto range is selected by tying pin 5 HIGH 2 Low range is selected by tying pin 5 LOW DESKEW option pin 4 JP4 1 This function works in New Mode ONLY 2 In order for the DESKEW feature to be operational DESKEW HIGH a minimum of four clock cycles is required during blanking time 3 To set DESKEW feature OFF set jumper JP4 LOW DC Balance BAL pin 6 JP6 1 This feature prevents charging of a cable in one state e 9 all 1s or all Os for an extended period of time The benefit to this is to open up the LVDS eye pattern 2 This function works in New Mode ONLY 3 To disable this function pin 6 is tied LOW To enable this function pin 6 is tied HIGH 4 BAL pin 24 of the Tx JP4 on Tx board must also be tied HIGH to enable this function 5 In this mode the chipset is NOT backward compatible with existing FPD Link technology This feature must be turned off to be backward compatible with current FPD Link chipsets NOTE Refer to the Application Notes section on the back of the datasheet for complete description of each feature National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 7 of 34 LDI Demonstration Kit User Manual How to hook up the demo boards overview The Tx demo board TxIN has been laid out to accept data from the Video Graphics card through two 50 pin IDC connectors The TxOUT RxIN interface use
10. R13 AO 12 HSYNC R11 A2 VSYNC R10 J1 CLK1 0 X G10 X 15 R12 X Rit X R10 1 X X 915 X Gia X G13 X G12 X G11 2 C XA N DE XVSYNCXHSYNCX 815 Bi4 X X 812 C X X X X X X X _Ri7 X R16 4 620 X 25 X Re4 X R28 X R22 X R21 X R20 A5 X X B20 X 625 X Ge4 X Ge3 X G22 X 621 A6 CK X X B25 B24 B23 X B22 XC X 827 X 826 X CLK2 Previous Current Cycle Cycle National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 12 of 34 LDI Demonstration Kit User Manual Mapping for New Mode Transmitter Board 50 pin IDC Connector IDC Connector Pin 1 49 Pin 1 gnd R25 gnd R24 gnd R23 gnd 22 4 R21 gnd R20 gnd gnd 50 J1 CLK1 WOO NANS NEENES 0 Ro X R X R12 R14 615 X DCBAL 1 X X X G15 X DCBAL A2 Bio Bi X B12 815 X DCBAL A3 CX R17 X X G17 X X B17 A4 X R22 X R24 R25 X DCBAL 5 CX G2 X X G22 X X G24 X G25 X DCBAL 6 B20 B21 X B22 B23 X
11. Rx Board Jumper Default Settings on page 17 except the BAL pin JP6 which must be set to Vcc Jumper Jumper Name Purpose Settings Number PRE PRE Emphasis o JP1 GND Vcc R FB Rising or Falling data strobe JP2 GND Vcc PD PowerDown JP3 GND Vcc BAL DC BALance JP4 GND Vcc PLLSEL PLL SELelect auto range JP5 GND Vcc FDE Rising or Falling Data Enable JP6 GND Vcc DUAL DUAL single mode 7 GND Vcc 1 An adjustable potentiometer 2K ohm is mounted at location R48 This allows emphasis to be adjusted only if JP1 has a jumper to VCC Use a number 1 4mm jewelers screwdriver to adjust R48 Turning clockwise will increase the pre emphasis value Turning counterclockwise will decrease the pre emphasis value R48 should be adjusted to reduce overshoot If no jumper is used the pre emphasis value will be 0 7V See Tx Features and Explanations Page 6 Pre Emphasis for description of feature In Balanced Mode New Mode R_FDE pin pin 21 MUST set to HIGH if DE signal pin 56 is HIGH during active data R_FDE pin must set to LOW when DE signal is LOW during active data National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 25 of 34 Troubleshooting LDI Demonstration Kit User Manual If the demo boards are not performing properly use the following as a guide for quick solutions to common problems If the problem persists contact the hotline number listed
12. impedance of the USB pair is rated at 90 ohms Power Connections The Transmitter and Receiver boards can only be powered by supplying power externally through TP1 Vcc and TP2 GND The maximum voltage that should ever be applied to the LDI Transmitter or Receiver is 4V For the transmitter and the receiver to be operational PD must be tied to Vcc which is labeled as and JP1 respectively Note J4 on the Tx and J1 on the Rx provide the interface for LVDS signals National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 8 of 34 LDI Demonstration Kit User Manual Transmitter Board Vcc and Gnd MUST be applied externally here TxOUT LVDS signals 3M MDR26 1 Connector E O af a ke ob D 1 PRE PLLSEL R FDE National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 9 of 34 LDI Demonstration Kit User Manual Tx Board Jumper Definition Jumper Purpose Settings PRE PRE emphasis 0 ON JP 1 GND Vcc GND Vcc NONE NO pre emphasis ON pre emphasis is adjusted through R48 When NO jumper is used pre emphasis is at 0 7V value R_FB Rising or Falling data strobe Rising Falling JP2 GND Vcc GND Vcc PD PowerDown 9 OFF
13. under Additional Information section of this document Check the following 1 Power and Ground are connected to both Tx AND Rx boards 2 Supply voltage typical 3 3V and current It s around 200mA with clock and one data bit at 66MHz are correct Trouble shooting chart Input clock and input data It s best to start with one data bit to the Tx board Jumpers are set correctly or to default settings The 2 meter cable is connecting the Tx and Rx boards Make sure all of the connections are good Start with a low clock frequency 40 or 66 MHz and work from there Problem Solution There is only the output clock There is no output data Make sure the data scramble mapping is correct Make sure there is data input No output data and clock Make sure Power is on Input data and clock are active and connected correctly Make sure that the 2 meter cable is secured to both demo boards Power ground input data and input clock are connected correctly but no outputs Check the Power Down pins of both boards and make sure the devices are enabled PD ON for operation The devices are pulling more than 1A of current Check for shorts on the demo boards After powering up the demo boards the power supply reads less than 3V when it is set to 3 3V Use a larger power supply that will provide enough current for the demo boards National Semic
14. use of the Chipset Tx Rx in a Host to LCD Panel Interface Chipsets support up to 24 bit single pixel or 24 bit dual pixel AM TFT LCD Panels for any VGA 640X480 SVGA 800X600 XGA 1024X768 SXGA 1280X1024 or UXGA 1600X1200 Because of the non periodic nature of STN DD SHFCLK the Chipset may not work with all D STN panels The PLL CLK input of the Transmitter requires a free running periodic SHFCLK Most Graphics Controller can provide a separate pin with a free running clock In this case the STN DD SHFCLK can be sent as Data while the free running clock can be used as SHFCLK for the PLL ref CLK For example C amp T s 65550 s WEC Pin102 can be programmed to provide a free running clock using the BMP Bios Modification Program Please refer to STN Application using AN 1056 for more information Refer to the proper datasheet information on Chipsets Tx Rx provided on each board for more detailed information Note Refer to AN 1127 for suggested mapping schemes National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 5 of 34 LDI Demonstration Kit User Manual Features and Explanations Transmitter Pre emphasis PRE pin 14 JP1 1 BT This feature enables you to overcome cable capacitance through the LVDS interface This function provides additional instantaneous current during switching transitions NOTE This function does NOT affect Rx output drive This function
15. works in Old Mode or New Mode It affects Tx AO A7 and CLKs LVDS outputs only To disable this function pin 14 must be tied LOW LVDS output drive will then be at its standard value of 3 5mA The input will be pulled low 0 7V if no jumper is used To adjust the level of pre emphasis place a jumper on JP1 to Vcc R48 will now be connected R48 is a 2K potentiometer Use a number 1 4mm jewelers screwdriver to adjust R48 Turning clockwise will increase the pre emphasis value Turning counterclockwise will decrease the pre emphasis value R48 should be adjusted to reduce overshoot Too much pre emphasis can create an overshoot condition at the rising edge and an undershoot condition on the falling edge Icc will increase but allows you to drive longer cables Too little pre emphasis will not allow you to drive longer cables Monitor any one of the LVDS lines 0 7 or CLK1 for a visual confirmation of its effect It is recommended that you monitor the LVDS signals with a differential probe If a differential probe is not used a single ended probe can be used for a quick check PLL range select PLLSEL pin 15 JP5 1 2 3 Auto range is selected by tying pin 15 HIGH Low range is selected by tying pin 15 LOW This function works Old Mode or New Mode Dual Single Operation DUAL pin 23 JP7 1 This feature provides three different modes of operation The modes of operation are 1 Dual 112MHz TxIN Du
16. 4 33 32 31 30 29 28 27 26 PCB Ref Edge Positioning Hole Connector Position Position Bottom Row Recommended Panel Cut out Contact Quantity 14 D Note Panel thickness 079 2 00 1 10 19 9 931 23 64 20 26 94 23 8 1 081 2745 319 004 1 09 27 6 144 36 5 1231 3126 1 581 40 15 40 8 1 i 50 16914281 1 830 46 50 1 Notes 1 Plated through holes for 062 board thickness 2 Use mounting screws M2 5 to fasten to board 3M Interconnect Solutions Division 6801 River Place Blvd Austin TX 78726 9000 National Semiconductor Corporation Interface Products TS 0755 06 Sheet 3 of 3 For technical sales or ordering information call 800 225 5373 LDI3V8BT 112 UM Date 04 04 01 Page 31 of 34 LDI Demonstration Kit User Manual 050 Mini D Ribbon Cable Assembly High Speed Digital Data Transmission System 26 Position 14526 EZHB XXX 0QC Physical Connector Contact Plating Wiping Area Shell Color Material Cable Color Jacket Material Flammability Electrical Voltage Rating Current Rating Insulation Resistance Withstanding Voltage 10 shielded pairs plus 4 individual wires The solution for high speed datacom and telecom applications Each differential pair is shielded with foil e
17. 5 C2 C7 C9 C12 DS90CF388 Qty 1 U1 R0402 Optional R4 R5 R6 R7 R8 R9 R10 R11 R12 R23 Qty 55 See previous page R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 RES Qty 10 1000hm R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 Qty 5 10 R1 R2 R38 R39 R40 TESTPAD 2 X 2 TP1 TP2 Qty 2 CAP100P CAP100P 10uF C1 C13 C14 C15 Qty 4 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 21 of 34 LDI Demonstration Kit User Manual Jumper Setting Examples 1 Old Mode The LDI chipset supports up to 24 bit single pixel and 24 bit dual pixel formats The following examples show how to set the jumpers for a specific pixel format in Old Mode WARNING 18 bit or 24 bit Single Pixel Old Mode The jumper settings below are for Old Mode Single to Single pixel application For Tx board For Rx board jumper settings in this application see Rx Board Jumper Default Settings on page 17 Jumper Jumper Name Purpose Settings Number PRE PRE Emphasis o JP1 GND Vcc FB Rising or Falling data strobe o JP2 GND Vcc PD PowerDown JP3 GND Vcc BAL DC BALance GND Vcc PLLSEL PLL SELelect auto range JP5 GND Vcc Rising or Falling Data Enable JP6 GND Vcc DUAL DUAL single mode JP7 GND Vcc An adjustable potentiomete
18. B24 B25 X DCBAL A7 CX N 26 X R27 G26 X G27 826 827 X DCBAL CLK2 WOAS A OA Previous Current Cycle Cycle National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 13 of 34 LDI Demonstration Kit User Manual Tx Optional Parallel Termination for TxIN On the Tx demo board there are 50 inputs that have an 0402 pad on one side and the other side tied to ground These pads are unpopulated from the factory but are provided if the user needs to adjust the input termination to match the impedance of the input signal PAD1 TO PAD48 PAD50 to PAD52 are associated with the Tx data input lines PAD49 is associated with CLKIN Mapping for Transmitter Inputs for the Optional Parallel Termination Resistors Tx Pin Tx Pin Parallel Tx Pin Tx Pin Parallel Names Number Termination Names Number Termination Resistor Resistor 00 PAD23 CLKIN PAD49 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 14 of 34 LDI Demonstration Kit User Manual BOM Bill of Materials Bill of Materials LDI 112 MHz Tx Bom Type Pattern Value Designators 3M MDR D26 1 J4 Qty 1 3 PIN HEADER 1 spacing JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 Qty 10 JP10 25X2 CONN J1
19. IQ T oueq pepnoius uN o6avd Nid 1 8 NJN 44 ONASH ONASA va Qd gd aud IN m 00 o jo t N m m m m 002 15 Aepsuny p AJY XL CLL L88AE IQTI 1ueuunoo cLL L88AEIQ 1 Qvdlsal 1531 99 119 29A 11 H3QV3H AJY cLL LS8AEIQT JequinN IN a IN 9 A 9 T3STld Do po lt lt po po po SLO elo clo 0 9 1 4 SLY vla 0 145 SOATId 886120659 8194018 ON 5119 194018 ON 886420650 QN9SQ 1 WIN div dev ney dev QN9SQ 1 We wsv dsv W9v WIN div
20. J2 Qty 22 PAD 0402 Optional PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 Qty 52 See previous page PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 PAD32 PAD33 PAD34 PAD35 6 PAD37 PAD38 PAD39 PAD40 PAD41 PAD42 PAD43 PAD44 PAD45 PAD46 PAD47 PAD48 PAD49 50 51 52 0805 001uF C4 C10 Qty 2 CAP Qty 4 0805 01uF C5 C6 C8 C11 CAP Qty 5 0805 C1 C7 C9 C12 DS90C387 U1 Qty 1 POT 10Kohm R48 Qty 1 RES 10 R49 R50 R51 R52 R53 R54 R55 Qty 7 TESTPAD_ 2 X 2 TP1 2 Qty 2 CAP100P CAP100P 10uF C2 C13 C14 C15 Qty 4 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 15 of 34 LDI Demonstration Kit User Manual Receiver Board Vcc and Gnd MUST be J3 applied externally here R_FDE PowerDown bar Jumper RxIN LVDS signals 3M MDR26 1 connector J gnd gnd gnd gnd gnd gnd gnd CNTLE NC CNTLF NC STOPCLK HSYNC VSYNC DESKEW PLLSEL BAL j ni 2 o PM J4 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 16 of 34 LDI Demonstration Kit User M
21. LDI Demonstration Kit User Manual National Semiconductor Demonstration Kit User Manual LVDS Display Interface P N LDISV8BT 112 Rev 4 1 Interface Products Information contained in this document is subject to change National Semiconductor Corporation LDISV8BT 112 UM Interface Products Date 04 04 01 Page 1 of 34 LDI Demonstration Kit User Manual Table of Contents 95 aa CONTENTS OF DEMO 2 2 er 4 5 FEATURES AND EXPLANATIONS 6 TRANSMITTER toD eL E uen E DU 6 ee 7 HOW TO HOOK UP THE DEMO BOARDS OVERVIEW 8 POWER 225555 8 TRANSMITTER BOARD ice eee A ee ee A es ee ne ee ee 9 TX BOARD JUMPER DEFINITION
22. P5 GND Vcc FDE Rising or Falling Data Enable JP6 GND Vcc DUAL DUAL single mode 7 GND Vcc 1 An adjustable potentiometer 2K ohm is mounted at location R48 This allows emphasis to be adjusted only if JP1 has a jumper to VCC Use a number 1 4mm jewelers screwdriver to adjust R48 Turning clockwise will increase the pre emphasis value Turning counterclockwise will decrease the pre emphasis value R48 should be adjusted to reduce overshoot If no jumper is used the pre emphasis value will be 0 7V See Tx Features and Explanations Page 6 Pre Emphasis for description of feature In Old Mode FDE can be set HIGH or LOW National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 23 of 34 LDI Demonstration Kit User Manual Jumper Setting Example 2 New Mode The LDI chipset supports up to 24 bit single pixel and 24 bit dual pixel formats The following examples show how to set the jumper for a specific pixel format in New Mode 18 bit or 24 bit Single Pixel New Mode The jumper settings below are for New Mode Single to Single pixel application For Tx board The Rx board jumper settings in this application is the same as the Rx Board Jumper Default Settings on page 17 except the BAL pin JP6 which must be set to Vcc Jumper Jumper Name Purpose Settings Number PRE PRE Emphasis o JP1 GND Vcc FB Rising or Falling data strobe o JP2 GND Vcc PD PowerDown
23. Position Plug Both Ends Ordering Information 14526 EZHB XXX 0QC Length 100 1 meter 200 2meter 500 5 meter 00 10 meter 5 0891 05 Sheet 2 of 3 3M Interconnect Solutions Division 6801 River Place Blvd For technical sales or ordering information call Austin TX 78726 9000 800 225 5373 National Semiconductor Corporation LIT LDI8V8BT 112 UM Interface Products Date 04 04 01 Page 33 of 34 Transmitter 387 50 49 47 46 45 44 42 41 39 38 37 36 34 33 32 31 29 28 LDI Demonstration Kit User Manual 3M Preliminary LDI Cable Assembly Specification Cable 24 0 Connector D26 1 wiring diagram for cable assembly and board layout Plug type 10126 6000 MDR 26 position right angle surface mount receptacle 10226 1210 VE Note pad column represents actual position of solder pad on board layout pin column specifies corresponding receptacle contact Note Temporary pinout for LDI testing purposes only Transmitter receptacle pad pin 4 signal type 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 26 1 1 1 1 1 L 1 1 1 L 1 1 1 1 1 1 1 L 1 1 1 L 1 1 1 1 C 1 C C Extra 1 Extra 2 Extra 3 AOM AOP A1M A1P A2M A2P CLK1M CLK1P Control 1 Control 2 Control 3 Control 4 A3M A3P A4M A4P A5M A5P A6M A6P A7M A7P LVDS gnd Cable Assemb
24. R12 X R10 Al X X Bit X X X X X G12 2 X XVSYNCXHSYNCX B15 X X X 812 X NL X X X X X 4 C X 620 X 25 24 X R23 X 622 R21 X 820 5 X X B20 X 625 X G24 X Ges X G22 X 821 A6 CX NL 825 X B24 X B22 X OX XL 826 X R27 X R6 CLK2 Previous Curre nt C ycle Cycle National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 18 of 34 LDI Demonstration Kit User Manual Mapping for New Mode Receiver Board 50 pin IDC Connector 50 pin IDC Connector 50 B27 49 BOG and B25 gnd B24 gnd B23 gnd A6 B22 gnd B21 gnd B20 gnd CNTLE NC CNTLF NC STOPCLK HSYNC VSYNC CLKOut CLK1 A0 Xy X X X 15 XDCBAL A1 Gi X G13 X X 15 XDCBAL A2 X X X Bo X X B12 X X X B15 X X X Rte X X X X B17 XDCBAL X A A R20 X R21 X R22 R28 X R24 R25 X DCBAL AS X X X Gi X oe X aes X Gea X G25 XDCBAL A6 X X X Bo X B21 X Be X X B24 X B25 X DCBAL A7 X X A Re X Rz X Gee X X B26 X 27 XDCBAL cr Previous Current Cycl
25. al 112MHz TxOUT 23 HIGH jumper JP7 to Vcc 2 Single 170MHz TxIN Dual 85MHz TxOUT 23 Vcc 2 no jumper JP7 3 Single 112 2 TxIN Single 112MHz TxOUT 23 LOW jumper JP7 to GND This function works in Old Mode or New In Single to Single mode TxOUTO through TxOUTS and associated Tx inputs are active TxOUT4 through TxOUT7 and associated inputs are disabled to promote power savings on the part DC Balance BAL pin 24 JP4 1 This feature prevents charging of a cable in one state e g all 1s or all Os for an extended period of time The benefit to this is to open up the LVDS eye pattern Reducing the Inter Symbol Interference National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 6 of 34 LDI Demonstration Kit User Manual This function works in New Mode ONLY It affects Tx AO A7 and LVDS CLK outputs only To disable this function pin 24 is tied LOW To enable this function pin 24 is tied HIGH 5 BAL pin 6 of the Rx JP6 on Rx board must also be tied HIGH to enable this function 6 In this mode the part is NOT backward compatible with existing FPD Link technology This feature must be turned off to be backward compatible with current FPD Link chipsets TOI NOTE Refer to the Application Notes on back of the data sheet for complete description of each feature Receiver PLL range select
26. anual Rx Board Jumper Definition Jumper Purpose Settings PD PowerDown OFF 1 GND Vcc GND Vcc OFF Tx powers down ON Tx is operational FDE Rising or Falling Data Enable Falling hd Rising JP2 GND Vcc GND Vcc DESKEW DESKEW OFF 4 GND Vcc GND Vcc PLLSEL PLL SELect auto range OFF JP5 GND Vcc GND Vcc BAL DC BALance OFF JP6 GND Vcc GND Vcc Old Mode DC Balance OFF New Mode DC Balance ON Rx Board Jumper Default Settings Jumper Jumper Name Purpose Settings Number PD PowerDown ON Part is enabled JP1 GND Vcc Rising or Falling Data Enable JP2 GND Vcc DESKEW DESKEW JP4 GND Vcc PLLSEL PLL SELect auto range JP5 GND Vcc BAL DC BALance JP6 GND Vcc National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 17 of 34 LDI Demonstration Kit User Manual LVDS Mapping by IDC Connector The following two figures show how the Rx outputs are mapped to the IDC connector and to each of the eight LVDS channels Note Refer to AN 1127 for suggested mapping schemes Mapping for Old Mode Receiver Board 50 pin IDC Connector 50 pin IDC Connector Al A6 AS AT es A5 4 CNTLE NC A4 CNTLF NC STOPCLK HSYNC VSYNC 2 DE CLK1 0 X Gio X 5 R14 X
27. e Cycle National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 19 of 34 LDI Demonstration Kit User Manual Rx Optional Series Termination for RxOut On the Rx demo board there are 49 outputs that have an 0402 pad in series but shorted These pads are unpopulated from the factory but are provided if the user needs to adjust the output series termination to match the impedance of an input line the user must cut the short out before mounting a series resistor R6 R12 R24 R37 R41 R70 are associated with the DATA input lines R23 is associated with CLKOUT Rx Pin Rx Pin Parallel Rx Pin Rx Pin Parallel Names Number Termination Names Number Termination Resistor Resistor 8 43 9 46 CNTLF NC CNTLE NC CLKOUT National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 20 of 34 LDI Demonstration Kit User Manual BOM Bill of Materials Bill of Materials LDI 112 MHz Rx Bom Type Pattern Value Designators 2 PIN HEADER 1 spacing JP3 Qty 1 3M_MDR_D26 1 J2 Qty 1 3 HEADER spacing JP1 JP2 JP4 JP5 JP6 Qtys5 25X2 IDC R J3 J4 Qty 22 PAD 0402 Shorted PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 Qty 2 6 CAP Qty 22 0805 001uF C4 C10 Qty 24 0805 01uF C5 C6 C8 C11 Qty 2 5 080
28. h an interface cable This kit will demonstrate the chipsets interfacing from a graphics controller using Low Voltage Differential Signaling LVDS to a Liquid Crystal Display LCD flat panel The Transmitter board accepts 3V LVTLL CMOS RGB signals from a graphics controller along with the clock and control signals The LVDS Transmitter converts the LVTLL CMOS parallel lines into serialized LVDS pairs The serial data streams toggle at 3 5 times the clock speed The Receiver board accepts the LVDS serialized data and clock and converts them back into parallel LVTLL CMOS RGB signals for the Panel Timing Controller The user needs to provide the proper RGB inputs to the Transmitter and also to provide a proper interface from the Receiver output to the panel timing controller In some cases a cable conversion board or harness scramble may be necessary depending on type of cable connector interface used Warnings The maximum voltage that should ever be applied to the LDI Transmitter or Receiver Vcc is 4V The Transmitter and Receiver power supply pins Vccs are NOT 5V tolerant The Transmitter can however accept a 3 3V or 5V LVTLL CMOS level on the inputs The Transmitter inputs are tolerant The maximum voltage that can be applied to any input pin is 5 0V National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 3 of 34 LDI Demonstration Kit User Manual Contents of Demo Kit 1 One T
29. ly Receiver receptacle signal type LVDS gnd A7P A7M A6P A6M A5P A5M A4P A4M A3P A3M Control 4 Control 3 Control 2 Control 1 CLK1P CLK1M A2P A2M A1P Extra 3 Extra 2 Extra 1 National Semiconductor Corporation Interface Products RevA 3 3 99 LIT LDISV8BT 112 UM Date 04 04 01 Page 34 of 34 Receiver 388 pin pad e 79 25 80 12 82 24 83 131 84 23 85 86 22 87 89 2 90 Co 6 __ 91 92 5 1 94 17 L 95 96 16 97 98 15 L 99 4 vp XL 1 x lo 28 906Sd uonisod 92 145 dud ON WZW1O IN NGA div WAV Ste d9v d9v Wov WV dsv dav wsv car We AY dev dev om 28620650 dev Wev div WIN dov WOV 2 5 o 5 o n 9 md o 5 5 QN9 99 002 ez XL CLL LaSAEIQT JequinN ZLL L88A
30. ntire cable bundle is shielded with foil and braid Rugged MDR ribbon type contact Quick release latches tear TS 0891 05 Date Modified February 23 2000 Sheet 1 of 3 30u 0 76um Min Gold Parchment Beige Acrylonitrile Butadiene Styrene ABS Parchment Beige Polyvinyl Chloride PVC AWM VW 1 30V 1A gt 1 x 1080 at 100 350 Vrms for 1 minute Individually Shielded Twisted Pairs Characteristic Impedance Conductor Size Propogation Velocity Environmental Temperature Rating UL File No E86982 100 10Q USB 900 28 AWG Stranded 1 25 ns ft 4 1 ns m 209 to 75 C 3M Interconnect Solutions Division 6801 River Place Blvd Austin TX 78726 9000 For technical sales or ordering information call 800 225 5373 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 32 of 34 LDI Demonstration Kit User Manual 050 Mini D Ribbon Cable Assembly High Speed Digital Data Transmission System 26 Position 14526 EZHB XXX 0QC 26 Position High Density 26 Position High Density Mini D Ribbon MDR Mini D Ribbon MDR a Male Plug Male Cable See wiring diagram for cable construction 1 9 2X Squeeze Release p Latches 2X Squeeze Release Latches Length See ordering information MDR 26
31. on call 800 225 5373 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 29 of 34 LDI Demonstration Kit User Manual 050 Mini D Ribbon Connectors Surface Mount Right Angle Receptacle Shielded 102XX 1210VE Series Contact 3M Part Dimensions Quantity Number A 008 B 006 C 006 006 E 006 14 10214 1210 VE 1 16 29 5 93 23 64 47 12 70 33 8 26 50 12 6 20 10220 1210 VE 1 32 33 4 1 081 27 45 650 16 51 12 07 646 16 41 26 10226 1210 VE 1 50 38 2 1 231 31 26 800 20 32 4 15 88 795 20 2 40 10240 1210 VE 1 88 47 1 1 581 40 15 1 150 29 21 3 24 71 1 150 29 2 50 10250 1210 VE 2 06 52 41 1 831 46 50 1 400 35 56 1 225 31 12 1 40 35 5 A position below pos 1 position above D last position lt 025 0 635 last position position 2 V position 1 2X M2 5 Thread 010 nom e 0 25 B A NI 138 2X M2 5 Thread see note in ordering info 7 Iu 189 4 80 i last position
32. onductor Corporation LIT LDISV8BT 112 UM Date 04 04 01 Page 26 of 34 Interface Products LDI Demonstration Kit User Manual Additional Information For more information on FPD Link Transmitters Receivers refer to the National Semiconductor URL http www national com appinfo lvds Application Notes AN 971 An Overview of LVDS technology AN 1032 An Introduction to FPD Link e AN 1127 LVDS Display Interface TFT Data Mapping for Interoperability with FPD Link AN 1163 Data Mapping for Dual Pixel LDI Application Alternate A Color Map AN 1085 FPD Link PCB and Interconnect Design In Guidelines AN 977 LVDS Signal Quality Jitter measurement using Eye pattern AN 1056 STN Application using FPD Link AN 1059 High Speed Transmission with LVDS Devices Open LVDS Display Interface 01 Specification http www national com appinfo fpd 0 2132 228 00 html 5099 LDI Paper http www national com appinfo fpd files LDI SID padf Information also available on the Internet http www national com apnotes Analog FlatPanelDisplay html http www national com appinfo fpd Interface Hotline The Interface Hotline number is 408 721 8500 National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 27 of 34 LDI Demonstration Kit User Manual 3M 26 Mini D Ribbon cable and connector The next few pages provide a full description of the cable and connector For product reque
33. r 2K ohm is mounted at location R48 This allows emphasis to be adjusted only if JP1 has a jumper to VCC Use a number 1 4mm jewelers screwdriver to adjust R48 Turning clockwise will increase the pre emphasis value Turning counterclockwise will decrease the pre emphasis value R48 should be adjusted to reduce overshoot If no jumper is used the pre emphasis value will be 0 7V See Tx Features and Explanations Page 6 Pre Emphasis for description of feature 2 n Old Mode R_FDE can be set HIGH or LOW Note A Inthe single pixel mode only through TxOUT3 LVDS channels 0 and their associated inputs are active 4 through TxOUT7 and their associated inputs and CLK2 are disabled for power savings B Old Mode is backward compatible to existing FPD Link technology National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 22 of 34 LDI Demonstration Kit User Manual 18 bit or 24 bit Dual Pixel Old Mode Default Setting from the factory The jumper settings below are for Old Mode Dual to Dual pixel application For Tx board For Rx board jumper settings in this application see Rx Board Jumper Default Settings on page 17 Jumper Jumper Name Purpose Settings Number PRE PRE Emphasis o JP1 GND Vcc R FB Rising or Falling data strobe JP2 GND Vcc PD PowerDown JP3 GND Vcc BAL DC BALance JP4 GND Vcc PLLSEL PLL SELelect auto range J
34. ransmitter board with IDC connectors on Tx input DS90C387MTD 48 bit Transmitter 2 One Receiver board with IDC connectors on Rx output DS90CF388MTD 48 bit Receiver 3 One 2 meter LVDS Cable interface to connect to RxIN Note The MDR footprint has been set to accept a D26 1 pinout 4 AN1127 LVDS Display Interface TFT Data Mapping 5 Demonstration Kit Documentation 6 D890C387 DS90CF388 Datasheet Note The demo board trace layout is designed for minimum skew between channels It is not absolutely required in most applications but be aware that the skew margins will be reduced if your board layout is not optimized National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 4 of 34 LDI Demonstration Kit User Manual Applications Transmitter Receiver Board s LCD Panel Digital RGB TLL LVDS Interface from Graphics Cable Digital RGB Controller TLL to Panel Contents of Demo kit R Graphics Note Demo Kit does not include the IDC AGP PCI ISA Bus cables Graphics Card or Panel Application The diagram above illustrates the
35. s the connector and 3M MDR cable with a D26 1 pin out This combination provides minimal skew between LVDS channels The receiver board RxOUT is laid out generically and must be mapped correctly to the panel being used 1 Connect one end of the D26 1 MDR cable to the transmitter board and the other end to the receiver board This is a standard pinout cable longer lengths are available for purchase from see http www mmm com Jumpers have been configured from the factory Refer to Tx and Rx Jumper Default Settings on pages 11 and 17 to run in normal mode with Deskew function OFF and with pre emphasis ON Jumpers are also provided on both boards so make sure that they are positioned correctly See Jumper Setting Examples on page 22 and page 25 for different application configurations 3 From the Graphics card connect the appropriate IDC cable to the transmitter board and connect two 50 pin IDC cables from the receiver boards to the panel Note Refer to AN 1127 for suggested mapping schemes Note that pin 1 on the connector should be connected to pin 1 of the cable Power for the Tx and Rx boards are supplied externally through Test Pad TP TP1 Grounds for both boards are connected through TP2 5 Turn on the PC first then power up the panel 4 7 Warning Clock 2 is brought over to the Rx board through the USB pair which are not matched in length with Clock 1 or LVDS data lines Also the differential
36. st please contact 3M Cable and Connector Data is available at http www mmm com Interconnects National Semiconductor Corporation LIT LDISV8BT 112 UM Interface Products Date 04 04 01 Page 28 of 34 LDI Demonstration Kit User Manual 050 Mini D Ribbon Connectors Surface Mount Right Angle Receptacle Shielded 102XX 1210VE Series 8 Physical Insulation Material Flammability Color Contact Material Plating Underplate Wiping Area Shroud and Latch Hook Material Plating Screw Lock Material Plating Marking Electrical Current Rating Insulation Resistance Withstanding Voltage Surface mount right angle shielded receptacle digital LCD interface 20 and 26 position Ultra low signal skew design for high data rate transmission Ribbon type contact industry preferred Reliable repetitive plugging unplugging Latch design for easy use Positions 14 20 26 40 and 50 5 0755 06 Date Modified August 2 1999 Sheet 1 of 3 Glass Reinforced Polyester PCT UL 94V 0 Beige Copper Alloy C521 80 u 2 0 um Nickel QQ N 290 Class 2 20 u 0 50 um Min Gold MIL G 45204 Type II Grade Steel Nickel Copper Alloy C521 Tin 3M Logo and Part Number 1A gt 5 x 108Q at 500 VDC 500 Vrms for 1 Minute 3M Interconnect Solutions Division 6801 River Place Blvd Austin TX 78726 9000 For technical sales or ordering informati
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