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ChipScope Software and ILA Cores User Manual

1. Figure 43 Changing Bus and Signal Names v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Bus Radix Display Buses can be configured individually to display different radixes in the wave display window Available bus display options are hexadecimal binary signed decimal unsigned decimal octal ASCII and Token By default bus values are displayed in hexadecimal ASCII is only available when the bus specified is exactly 8 bits wide To set the radix for a bus select a bus in the ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 Bus Signal panel then select Bus Signal gt Show As The menu popup Figure 44 allows you to choose from the available bus radix options ChipScope Analyzer demo Unit O Of x File Communication Configure Rurnstop Data Window Help Ungroup From Bus B Move Up D width Count fi M1 Width Count Trigger Capture One Shot On Trigger Po Rename Out Sample Buffer FIJLL m owes e Bus Bit Ordering Binary hove Down b DOC Channel Numbers Signed Decimal Color Unsigned Decimal Load Tokens Octal Import Signal Names pata _Bignal_4 1 1 1 0 o o a 1 a Signal Signal_6 Signal_7 LC e Signal_8 Signal_9 Signal_10 Sianal 11 dul dla a ju pload DONE Figure 44 Changing Bus Display Radix 4 33
2. Capture One Figure 49 Selecting a Waveform Color ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 37 ChipScope Software and ILA Cores User Manual 9 XILINX Navigating the Waveform Window s Centering the Waveform Center the waveform display around a specific point in the waveform by selecting Data gt Go To then centering the waveform display around the X and O markers as well as the first trigger position Figure 50 ChipScope Analyzer demo Unit O Al ES File Communication Configure Bus sigrial Runistop Window Help ajjaj gt aft ojele ple S Trigger Setup Go To 1 hHarker mo Ex x x o o o o Mal Ek x z x xx xx S a mu wiat feou foon El E eee Mi Width Count ji Trigger Condition jboolean ay 2 Zoom In 2 Trigger Capture One shot On Trigger Position 0 2047 he 2 Zoom Out ULL Bus Siqnal Wi Zoom Area 542 Signal_0 GE Fit Window a Toggle Time State Display set Clock Period Plot Values Demo Waveform RSS pe cal ge el ee ES Signal _ Bignal_2 _ Bignal_3 _Bignal_4 Signal_5 _ Bignal_B _ Bignal_T _ Bignal_8 Signal _ Bignal_10 _Bignal_11 _ Bignal_12 _ Bignal_13 _Bignal_4 _Signal_15 A A FR FO FO FOO fF oO oO OOO O F eS Upload DONE Figure 50 Centering the Waveform Display 4 38 v2 0 December 15 2000 Xilinx Development System 2 XILINX Using the ChipScope Analyzer Zooming In and Out Select Data gt Zoom In to z
3. ChipScope Software and ILA Cores User Manual 9 XILINX Using Tokens Tokens are string labels that can be assigned to a particular bus value These labels can be very useful in such applications as address decoding and state machines Tokens are defined in a separate ASCII file and loaded into the ChipScope Analyzer when appropriate The token file itself tok extension has a very simple format and can be created or edited in any text editor An example token file is provided in the token directory in the ChipScope install path Figure 45 Bj token_sample tok Notepad _ OP xl File Edit Search Help ChipScope Example Token File Tokens are in the form HAHE UALVE where HAHE is the token name and VALUE is the token value hex binary or decimal append b binary u unsigned decimal 4h hex to the value So valid token definitions would be HEM WRITE c5S h HEM_READ 11674b o H H H H H Values are hex by default To specify a radix for the value H H H H H GFILE VERSI0OH 1 B6 0 H Begin token definitions SEVEN 111Ab EIGHT 1 6664 b HIHE 9h Figure 45 Example Token File Tokens are chosen by selecting a bus then choosing Bus Signal gt Load Tokens A dialog opens and the user can choose the token file Once the tokens are loaded selecting Bus Signal gt Show As gt Token enables the tokens for that particular bus If the bus is wider than the tokens specify such as choosing 4 bit tokens for an
4. Save Project As Unit 1 Import Waveform Unit 2 Ekpar ioare km E nit 3 Close Limit 4 Exit Unit 5 tE Unit 7 Unit 8 Unit 9 Unit 10 Unit 14 Unit 12 Unit 13 Unit 14 Successfully opened Parallel Cable ipart LPT1 DONE Figure 10 Selecting New ILA Unit If the Boundary Scan chain contains multiple devices that can serve as ILA targets then select communication to one of the 15 possible ILA units in the target device using File gt New ILA Unit gt Device m gt Device m Unit n where m is the target device number n is the ILA unit number Note that the ILA unit number corresponds to the control port number of the ICON unit to which the ILA component is connected or the Unit number in the case of Core Insertion Figure 11 shows how to select ILA Unit 0 in target Device 1 If the trigger setup toolbar is not present in the current ChipScope window then selecting a new ILA unit using this method simply refocuses the current window to the new ILA unit However if you select a new ILA unit after you have set up the trigger for the current one a new ChipScope window opens 4 2 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer This feature allows you to view the waveforms of multiple ILA units at the same time ChipScope Analyzer demo Unit O Of x MultiLing Configure Bus isignal Runfstop Data Window Help New ILA Unit Device toel e el il Open Pro
5. Synthesis Insertion Requirements Users can modify many options in the ILA and ICON cores without resynthesizing in the case of the core generator or re inserting in the case of the core inserter However after changing selectable parameters such as width of the data port or the depth of the sample buffer the design must be resynthesized either with new cores or with the cores re inserted Table 1 6 describes which design changes require this Table 1 6 Design Parameter Changes Requiring Resynthesis Resynthesis Design Parameter Change Be dngedion Required Change trigger pattern No Running and stopping the trigger No Enabling the external triggers No Changing the trigger signal source Yes Changing the data signal source Yes Changing the ILA clock signal Yes Changing the sample buffer depth Yes a This feature is supported by the Alliance Series 3 11 FPGA Editor and Foundation Series 3 11 FPGA Editor System Requirements 1 8 Communications Requirements ChipScope software Analyzer uses either the MultiLINX or Parallel Cable III download cable to communicate with the target devices in Boundary Scan chain of the board under test The MultiLINX cable uses the USB port found on newer PCs and downloads at speeds up to 12 Mb s throughput The MultiLINX cable also supports communication through the PC s RS 232 serial port at speeds up to 57 6 kb s MultiLINX also features an adjustable voltage
6. Sample Depth 2048 ILA Core Version 1 2 extended Figure 36 Selecting On Trigger Capture Mode Window 4 26 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Enabling External Trigger Output Each ILA unit can drive out its overall trigger condition as an external trigger output to the ICON unit There it is logically OR ed with the external trigger output of all the other ILA units in the target device However you can disable the ILA unit from driving out its overall trigger condition and drive a logical 0 instead by deselecting the Ext Out field in the trigger setup toolbar Selecting the Ext Out field enables the ILA unit s individual external trigger output Figure 37 ChipScope Analyzer demo Unit 0 _ OR ES File Communication Configure E EA Data Window Help Capture One Shot Shot On Trigger Position 0 2047 0 A dT Ext Ext Out 4 Sample Buffer EMPTY External Trigger Output Trigger Immediate DONE Figure 37 Enabling the External Trigger Output ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 27 ChipScope Software and ILA Cores User Manual 9 XILINX Capture Status Window After you arm the trigger by selecting Run Stop gt Run the status of the ILA unit appears in the Sample Buffer display area with one of the following values ARMED The trigger is currently armed and waiting for an occurrence of the trigger
7. The ID codes are displayed in a small dialog box Figure 26 Chip5cope Unit O Ea Ci IDCODE 20620093 Figure 26 Viewing User Defined ID Code ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 15 ChipScope Software and ILA Cores User Manual 9 XILINX Opening the Trigger Setup Toolbar To set up the trigger for a device that has already been configured with a design containing an ILA core select Data gt Trigger Setup Figure 27 lel Es ChipScope Analyzer demo Unit 0 File Communication Configure Busisignal Runfstop Window Help cic Wie la A aot at E oom ated Al cae Whilst Mepla Sence ari Blot Sees Demo Waveform Successfully opened Parallel Cable ipart LPT1 DONE Figure 27 Opening the Trigger Setup Toolbar After you select Trigger Setup the ChipScope program queries the ILA unit to determine the proper settings for the trigger setup If the device has just been configured then it is queried and the Trigger Setup toolbar appears automatically 4 16 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer The parameters associated with the ILA unit appear at the bottom of the ChipScope Analyzer window see Figure 28 for example of Trigger Width 8 Signal Count 16 Data Depth 2048 ILA Core Version 1 1 extended match units The Trigger Width Signal Count Data Depth and Extended Features parameters correspond to
8. 8 bit bus the upper bits are assumed O for the tokens to 4 34 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer apply Figure 46 shows such a waveform with the example file in Figure 45 applied to a 5 bit bus File Communication Configure OEA Data Window Help Mi WidthfCountf Width Countf e st Bl HO 40D END Capture One Shot Shot On Trigger Position 0 2047 vq Ext Out Ext Out Sample Buffer FULL Buffer FULL CTE KIF ZERO X ONE X TWO YTHREEY FOUR FIVE Y f STE Signal_6 Figure 46 Example Waveform with Tokens Bus Bit Ordering The bits in each bus can be ordered top to bottom or bottom to top when computing their value in the wave display window To place the most significant bit at the bottom select Bus Signal gt Bus Bit Ordering gt Bottom MSB To Top LSB To place the most significant bit at the top select Bus Signal gt Bus Bit Ordering gt Top MSB To Bottom LSB The default bit ordering is bottom to top Figure 47 ChipScope Analyzer demo Unit 0 File communication Rurnstop Data Window Help ra n Bone En Lingroup From Bus 30 OIT e oe z jo Width Count fr Mi Width Count j1 Mi WidthfCount fe Trigger Move Down Capture One Shot On Trigger Po Rename t Out Sample Buffer FUL show As 7 x 0 Bus Bit Ordering k v Bottorm iS Br To Top LSB Ma Channel Numbers Topi
9. asking if you want to store the current waveform before closing exiting If you select Yes another dialog box opens from which you can save the waveform The difference between closing and exiting is closing closes the current ChipScope window exiting closes all ChipScope windows and ends the program However if only one ChipScope window is open closing and exiting have the same effect Opening and Closing a MultiLINX Connection You can connect the MultiLINX cable to the host computer by using a serial communications port e g COM1 the USB Universal Serial Bus port connection or both However only one connection to the MultiLINX cable is supported at a time v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Opening a Serial Port MultiLINX Connection If the MultiLINX cable connects to the host computer by way of the serial port then select Communication gt Open Serial Port Figure 15 ChipScope Analyzer demo Oy ES File enti Configure Bus Signal RunfStop Data window Help Serial MultiLINx Cable USB MultiLIN Cable Parallel Cable Abe ont Geran loreto Aedes Reading projectfile CiProgram Filesiilindichipscope Betaldermo cpj Figure 15 Opening a Serial Port Connection to MultiLINX After you select Communication gt Open Serial Port a small dialog box opens Figure 16 Enter the proper serial port name select the baud rate for the serial port connected
10. bus functionality User selectable sample buffers ranging in size from 256 to 4096 samples Large sample size increases accuracy and probability of capturing infrequent events Separate bus trigger with user selectable width of 1 64 bits Separate trigger bus reduces need for sample storage All data and trigger operations are synchronous to user clock up to 155 MHz Capable of high speed data capture Trigger conditions are in system changeable without affecting user logic No need to single step or stop a design for logic analysis Can write waveforms to VCD FBDF and ASCII formats Compatible with Agilent Technologies and other waveform viewers Easy to use graphical interface Guides users through selecting the correct options Up to 15 independent ILA capture cores per device Can segment logic and test smaller sections of a large design for greater accuracy Multiple trigger settings Records duration and number of events along with matches and ranges for greater accuracy and flexibility Downloadable from the Xilinx website Tools are easily accessible from the ChipScope Suite ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 1 3 ChipScope Software and ILA Cores User Manual Design Flow XILINX The ChipScope Tools design flow Figure 2 merges easily with any standard FPGA design flow that uses a standard HDL synthesis tool and the A
11. contiguous event count trigger match conditions over a number of clock cycles v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Core Inserter e Enabling usage in conjunction with other trigger match units to build the trigger condition boolean equation using AND OR e Enabling usage in conjunction with other trigger match units to build the trigger condition macro equation using IF THEN Basic Matching If Extended Matching is not checked a subset of the above features are available for all match units saving CLB usage of the ILA core These options include e Finding only one occurrence of an exact match of a trigger value or edge e Enabling usage in conjunction with other trigger match units to build trigger condition boolean equation using AND OR Match Units The number of match units can be set to one or two Selecting two units allows a more flexible trigger condition equation to be a combination of both match units Selecting one match unit conserves resources while allowing some flexibility in triggering Figure 6 shows a sample of the ILA parameters and options Select Internal Logic Analyzer Options Trigger Settings Trigger Same As Data Trigger Width ls ata Settings Data Depth 256 Data width 116 m E atch Settings M Extended Matching Match Units 2 Figure 6 ILA Options and Parameters Choosing Net Connections for ILA Signals The Net Connect
12. interface that enables it to communicate with systems and I Os operating at 5V 3 3V or 2 5V The MultiLINX cable is available from Silicon Xpresso Cafe from www xilinx com choose Purchase gt Programming Cables v2 0 December 15 2000 Xilinx Development System XILINX Introduction The Parallel Cable III uses the parallel port 1 e printer port to communicate with the Boundary Scan chain of the board under test The Parallel Cable III supports only JTAG configuration of target FPGA devices and does not support slave serial configuration The Parallel Cable III is also available from Silicon Xpresso Cafe from www xilinx com choose Purchase gt Programming Cables Board Requirements For the ChipScope Analyzer and download cable to work properly with the board under test the following board level requirements must be met One or more Virtex Virtex E or Spartan II target devices must be connected to a JTAG header that contains the TDI TMS TCK and TDO pins If another device would normally drive the TDI TMS or TDI pins of the JTAG chain containing the target device s then jumpers on these signals are required to disable these sources preventing contention with the download cable If using the MultiLINX download cable Vcc 2 5 5 0V and GND headers must be available for powering the MultiLINX cable If using the Parallel Cable III download cable Vcc 2 5 3 3V and GND headers must be available for powering the P
13. the ILA core parameters used when the core is generated rigger Vidth 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 1 extended Figure 28 Viewing the Trigger Setup Toolbar Setting Up the Trigger The trigger mechanism inside each ILA core can be modified at run time without having to re compile the design The following sections describe how to modify the various components that make up the trigger mechanism Basic Match Unit Comparison Values The match units are called Mn where n is O or 1 depending on the number of trigger match units in the ILA core and can be one of two types basic or extended If the match units are basic then you can change only the comparison value Figure 29 You can set each bit of the match unit to one of the following values e X Any value logical zero or logical one e 0 Logical zero only e 1 Logical one only e R Rising edge only e F Falling edge only e B Both edges rising edge or falling edge You can set match word values by clicking on each bit until the desired value appears or by clicking on the bit value and typing the desired value Moving ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 17 ChipScope Software and ILA Cores User Manual 9 XILINX the cursor over but not clicking on a bit in the match word causes a tool tip window to appear that indicates the bit position and current match value ChipScope Analyzer demo Unit O I
14. 2 XILINX ChipScope Software and ILA Cores User Manual 0401884 v2 0 December 15 2000 Software v2001 1 ChipScope Software and ILA Cores User Manual 0401884 v2 0 Printed in U S A ChipScope Software and ILA Cores User Manual 0401884 v2 0 O The Xilinx logo shown above is a registered trademark of Xilinx Inc ASYL FPGA Architect FPGA Foundry NeoCAD NeoCAD EPIC NeoCAD PRISM NeoROUTE Timing Wizard TRACE XACT XILINX XC2064 XC3090 XC4005 XC5210 and XC DS501 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc All XC prefix product designations A K A Speed Alliance Series AllianceCORE BITA CLC Configurable Logic Cell CoolRunner CORE Generator CoreLINX Dual Block EZTag FastCLK FastCONNECT FastFLASH Fast Map Fast Zero Power Foundation HardWire IRL LCA LogiBLOX Logic Cell LogiCORE LogicProfessor Mi croVia MultiLINX PLUSASM PowerGuide PowerMaze QPro RealPCI RealPCI 64 66 Selectl O SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch Smartspec SMART Switch Spartan TrueMap UIM VectorMaze VersaBlock VersaRing Virtex WebFitter WebLINX WebPACK XABEL XACT step XACT step Advanced XACTstep Foundry XACT Floorplanner XACT Performance XAM XAPP X BLOX X BLOX plus XChecker XDM XDS XEPLD Xilinx Foundation Series XPP XSI and ZERO are trademarks of Xilinx Inc The Programmable Logic Compan
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16. 49 690 5 949 712 5 949 983 5 949 987 5 952 839 5 952 846 5 955 888 5 956 748 5 958 026 5 959 821 5 959 881 5 959 885 5 961 576 5 962 881 5 963 048 5 963 050 5 969 539 5 969 543 5 970 142 5 970 372 5 971 595 5 973 506 5 978 260 5 986 958 5 990 704 5 991 523 5 991 788 5 991 880 5 991 908 5 995 419 5 995 744 5 995 988 5 999 014 5 999 025 6 002 282 and 6 002 991 Re 34 363 Re 34 444 and Re 34 808 Other U S and foreign patents pending Xilinx Inc does not represent that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited Copyright 1991 2000 Xilinx Inc All Rights Reserved ChipScope Software and ILA Cores User Manual 0401884 v2 0 ChipScope Software and ILA Cores User Manual 0401884 v2 0 Xilinx Development System gt XILINX Chapter 1 Introduction ChipScope Tools Overview As the density of FPGA devices increases so does the impractic
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18. MSB To BottornLsBr i oignal 4 1l 1l om ee Color D Signal a Load Tokens ed Sade 1 qt Import Signal Mames i Diarnal T Figure 47 Changing Bus Bit Ordering ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 35 ChipScope Software and ILA Cores User Manual 4 36 Signal Channel Number Display XILINX Channel number display can be toggled to identify which of the ILA core data channels is connected to each of the signals in the waveform display To toggle the display select Bus Signal gt Channel Numbers By default channel number display is turned off Figure 48 ChipScope Analyzer demo Unit 0 File Communication Configure Runfatop Dal p po m T o ra ai Bone Ungroup From Bus oo000 z mof exxxfo 00 omi ave yy Ma Width Count f Trigger Capture One Shot On Trigger Po hove Down Rename Show As j Bus Sauna a a Bus Bit Ordering Signal_4 da Jee lo EN Channel Numbers e ee l Color e pe Ae Load Tokens aale aa a Import Signal Mames i Cianal T co A ChipScope Analyzer demo Unit O File Communication Configure Bu eae aft JE Bus Signal ew H4 Signal _4 CH5 Signal_5 CH6 Signal_6 Figure 48 Enabling Signal Channel Number Display Bus and Signal Coloring Separate colors can be assigned to each bus and signal in the waveform display To c
19. O AND Capture One Shot One Shot On Trigger Position O Capture One Shot On Trigger Position 0 2047 a Ext Out Ext Out T Sample Buffer rigger Width 8 Signal Count 16 sample Depth 2048 ILA Core Version 1 2 basic Figure 33 Selecting the Boolean Trigger Condition ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 23 ChipScope Software and ILA Cores User Manual 9 XILINX Setting Up a Macro Trigger Condition Only the extended trigger match units can build 1f then macro equations out of the available match units and the external trigger input to form the overall trigger condition Select the macro trigger condition type by selecting the macro type from the pull down menu An example of the 1f then macro condition is if MO is satisfied and then EXT is satisfied then the overall trigger condition is satisfied To designate the macro equation click on the buttons to the immediate right of the Trigger Condition field in the trigger setup toolbar For instance 1f you want the trigger condition boolean equation to be MO then not EXT Figure 34 do the following e Click the third button four times to select EXT 1 e not EXT e Click the first button one time to select MO e The middle button is automatically set to THEN Clicking the first and or third button until 1t is blank effectively removes the match condition or external trigger input from the macr
20. Output Directory E projectsiilaiusage_test Browse Next gt 4 Figure 4 Core Inserter Project with Files Specified Choosing ICON Options The first options that need to be specified are for the ICON core The ICON core is the controller core that all ILA units connect to The ICON core has the options shown in Figure 5 Enable External Trigger Input This option causes a PAD to be added to the design the pin location specified in Figure 5 is added in the output UCF file specified in Figure 4 This signal is a logical OR d condition of all the trigger states of all ILA cores in the design Enable External Trigger Output This option causes a PAD to be added to the design the pin location specified in Figure 5 is added in the output UCF file specified in Figure 4 This signal can be used in the ChipScope Analyzer to trigger the ILA cores 3 4 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Core Inserter Disable JTAG Clock BUFG Insertion The ICON core communicates to the outside world via the USER1 JTAG scan chain that is clocked by the JTAG clock TCK By default this clock 1s placed on a global clock resource BUFG To disable this insertion check the Disable JTAG Clock BUFG Insertion box This should only be done if global resources are very scarce placing the JTAG clock on regular routing even high speed backbone routing introduces skew Ma
21. Scope Analyzer Configuring the Target Device s You can use ChipScope software with one or more target devices Virtex Virtex E or Spartan II FPGAs The first step is to set up all of the devices in the Boundary Scan chain Setting Up the Boundary Scan Chain Once ChipScope has successfully communicated with a download cable it automatically queries the JTAG chain to find its composition All Xilinx Virtex E EM Spartan II Spartan XL 9500 XL XV 4000XL XLA and 18V00 devices are automatically detected The entire IDCODE can be verified for Virtex Virtex E Virtex EM and Spartan II devices To view the chain composition select Configure gt Boundary Scan Setup A dialog appears with all detected devices in order For devices that are not automatically detected the IR Instruction Register length must be specified to insure proper communication to the ILA and ICON cores This information can be found in the device s BSDL file The following example has a CoolRunner CPLD XC18V02 PROM and Virtex V150 in a chain A non zero IR length must be specified for the unknown CoolRunner device in order to close the dialog see Figure 20 ChipS cope x Scan Chain Device Order Device Mame IR Length Device ID ss 040402 1 eeo ejosooeosa 2 ews IE TATTOO O O Fead User lOs Figure 20 Boundary Scan Setup Window UserID s can be read out of the ILA target devices only the XCV 150 in this example by selecting Re
22. TTT TT CA Fit Window de a sigrial_1 o Wo LL Togale Time state Display _Bignal_2 lol pmmmmnnnnnnn Set Clock Period Signal_3 o lo lan Signal_4 1 qo T LT LLI L Dermo Waveform Signal_5 a _ Bignal_B o fo 2S ee _ Bignal_T a A OOOO OOOO ocio Signal_8 1 Mo _Bignal_ ofo AN _Bignal_10 ola _Bignal_11 o lo _Bignal_12 i ffi _ Bignal_13 o lo Signal_14 a Signal_15 la dll a new waveform x sz 1 or rea 1 e Upload DONE Figure 52 Zooming in to the X Marker of the Waveform Display 4 40 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer To zoom out from a waveform use Data gt Zoom Out Figure 53 x ChipScope Analyzer demo Unit 0 o Zoom Out Bus Signal signal_0 Signal _ Bignal_2 _ Bignal_3 _Bignal_4 Signal_5 _ Bignal_B _ Bignal_T _Bignal_8 Signal _Bignal_10 _Bignal_11 _ Bignal_12 _ Bignal_13 _Bignal_14 _Signal_15 aS Se eS Se Se ee eS ee Sa eS ea ea eS eS ae Figure 53 Zooming out from the Waveform Display ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 4 ChipScope Software and ILA Cores User Manual 9 XILINX To view the entire waveform display select Data gt Fit Window Figure 54 ChipScope Analyzer demo Unit O Al ES File Communication Configure E Runfatop Window Help Trigger Setup Go To ba aii Ma Width Count ji Trigger Condition boolean E a Zoom In Capture One shot On Trigg
23. ad User IDs Device Configuration The method for configuring the target device depends on how the programming device connects to the download cable Currently only JTAG and Slave Serial programming modes are supported for the MulitLINX cable by the ChipScope software Only JTAG programming mode is supported for ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 11 ChipScope Software and ILA Cores User Manual XILINX the Parallel Cable I download cable If the target device is to be programmed using the MultiLINX cable by way of the Slave Serial port select Configure gt Slave Serial Mode Figure 21 ChipScope Device 0 Unit O OO ES File MultiLinc Bus signal Runfstop Data Window Help Boundary Scan Setup JTag Mode Slave Serial Mode show IDCODE Show USRCODE Tag Chain Info DONE Figure 21 Configuring Using Slave Serial Mode 4 12 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer If the target device is to be programmed using the MultiLINX or Parallel Cable III download cable by way of the JTAG port select Configure gt JTag Mode Figure 22 ChipScope Analyzer demo Unit 0 Al ES Bus Signal Run Stop Data Window Help File communication Boundary Scan Setup JTAG Configuration aia Enri show IDCODE Show USRCODE Successfully opened Parallel Cable ipart LPT1 DONE Figure 22 Configuring JTAG Mode W
24. ality of attaching test equipment probes to these devices under test The ChipScope Analyzer integrates key logic analyzer hardware components with the target design inside the Virtex device The ChipScope Tools communicate with these components and provide the designer with a complete logic analyzer without the need for cumbersome probes or expensive test equipment ChipScope Tools Description The ChipScope Tools include e the ChipScope Core Generator e the ChipScope Core Inserter and e the ChipScope Analyzer The Core Generator provides netlists and instantiation templates for the Integrated CONtroller ICON core and the Integrated Logic Analyzer ILA core The Core Inserter automatically inserts these two cores into the user s synthesized design The Analyzer allows setup and trace display for the ILA core The ILA core provides the trigger and trace capture capability The ICON core communicates to the dedicated Boundary Scan pins The Analyzer supports both the Xilinx MultiLINX M and Parallel Cable HI download cables for communication between the PC and FPGA s The MultiLINX cable supports both USB Windows 98 and Windows 2000 and RS 232 serial communication from the PC Figure 1 The Parallel Cable HI ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 1 1 1 2 ChipScope Software and ILA Cores User Manual XILINX supports only parallel port communication from the PC to the Boundary Scan cha
25. arallel Cable III cable If the slave serial configuration mode is to be used by the MultiLINX cable then a header containing the DIN CCLK INIT PROGRAM and DONE signals is required Note that the Parallel Cable II should only be used in JTAG configura tion mode The slave serial flying wires should not be attached to the Parallel Cable III device when used in conjunction with ChipScope Analyzer ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 1 9 ChipScope Software and ILA Cores User Manual XILINX 1 10 Host System Requirements The ChipScope Analyzer runs on any of the following PC systems having these minimum requirements e Windows 98 Windows 98 SE or Windows 2000 OS 32 MB of memory RS 232 port MultiLINX USB port MultiLINX or parallel port Parallel Cable III e Windows NT 4 0 64 MB of memory RS 232 port MultiLINX or parallel port Parallel Cable IIT e Java Run time Environment version 1 1 8 available for downloading from the ChipScope Suite Note In order to use the MultiLINX USB interface under Windows 98 Second Edition or Windows 2000 the correct driver must be used The updated driver is included in all versions of Xilinx software beginning with 3 11 Service Pack 1 Installing ChipScope Tools The ChipScope Tools include three separate programs the ChipScope Core Inserter the ChipScope Core Generator and the ChipScope Analyzer After downloading the tools in the f
26. ately constrained v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Core Generator Including Boundary Scan Ports The BSCAN_VIRTEX primitive has two sets of ports USER1 and USER2 These provide an interface to the Boundary Scan TAP controller of the Virtex or Virtex E device Since the ICON core uses only the USER1 port for communication purposes the USER2 port signals are available To use the USER2 interface to the BSCAN_VIRTEX primitive click the Include Boundary Scan Ports check box Note The Boundary Scan ports should be included only if the design needs them If they are included and not used some synthesis tools do not connect the ICON core properly which causes errors during the synthesis and implementation stages of development Choosing the Instantiation Template After choosing the parameters for the ICON core you can construct an instantiation template Click Next to view the Sample Code Generation Options then choose which synthesis tool and language to use The synthesis tools supported are e Exemplar LeonardoSpectrum e Synopsys FPGA Compiler e Synopsys FPGA Compiler II e Synopsys FPGA Express e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the instantiation template for the various synthesis tools To generate the ICON core without any example files deselect the Generate Example Files c
27. condition lt value gt A number lt value gt between 1 and Sample Depth 1 that represents how many data samples have currently been captured FULL The capture storage is full and the capture process has ended STOPPED The ILA unit has been halted by the act of stopping the acquisition During One Shot capture mode once the ILA unit progresses from the ARMED state to the FULL state ChipScope program automatically displays the captured data in the waveform window Figure 38 Note that the X axis of the waveform is measured in number of data samples Data sample 0 is always at the location of the trigger condition 4 28 ChipScope Analyzer demo Unit O File Communication Configure E see Data Window Help lel ES M4 WidthfCount ff Width Countf A T A Mo 400 AML Capture One Shot On Trigger Position 0 2047 0 Shot On Trigger Position 0 2047 lo Ext Ext Out 4 Sample Buffer FULL Ss ignal_0 Signal_1 _ Bignal_2 _ Bignal_3 _Bignal_4 Signal_5 Signal FO e CO Ga G O G Signal _7 i enal O boa Upload DONE Figure 38 Viewing the One Shot Capture Mode Waveform v2 0 December 15 2000 Xilinx Development System 2 XILINX Using the ChipScope Analyzer During On Trigger capture mode once the ILA unit progresses from the ARMED state to the FULL state the ChipScope program automatically displays the captured data in the wave
28. ct To create a new project select Create a new Project Figure 12 and click OK In the Choose New Project File dialog box Figure 13 enter a new project filename name using the cpj extension and click Open ChipScope Choose New Project File Ma ES Look in E example e El 3 Counter 6 cpj Random cp Files of type E Files Cancel Figure 13 Creating a New Project 4 4 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Opening An Existing Project To open an existing project select 1t from the list of recently opened projects To browse through all available project files select More Projects When you locate the desired project click Open Saving Projects Projects are automatically saved when you exit the ChipScope software To rename the current project or to save a copy to another filename select File gt Save Project As Figure 14 type the new name in the dialog box and click Save ChipS cope Analyzer Chip5cope Choose New Project File HE MES Communication flack an Germ El mie i es E El Mew ILA Unit Save Project As a Counter 6 cpi Import Waveform a Fandom cp Export vaver arr 5 ee H T Bignal_0 0 Signal_1 1 EE Femme A 3 Files of type EJ Files Cancel Figure 14 Saving a Project Importing and Exporting Only VCD waveforms can be imported You can import the wavefo
29. e net has been found click Select to choose it and return to the main Core Inserter window 3 8 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Core Inserter All the nets for Trigger and Data must be chosen in this fashion Once all the nets have been chosen for a given bus the ILA bus name changes from red to black see Figure 9 DATA HETS CHO icounter 8 CH1 Icounter a Figure 9 Specifying Data Connections Once all the Clock Trigger and Data nets are specified click Next A dialog appears asking if you want to proceed with Core Insertion If Yes is chosen the cores will be generated inserted into the netlist and a ngo file is created by running the edif2ngd program Details of this process can be viewed in the Messages panel at the bottom of the window A Core Generation Complete message in the Messages panel signals success Adding ILA Units Each device can support up to 15 ILA units the number of units may also be restricted by block RAM availability and ILA unit parameters Additional units can be added to the project by selecting Edit gt New ILA Unit or going to the ICON Options window by clicking on ICON in the tree on the left panel see Figure 5 and selecting the New ILA Unit button Parameters for the additional ILA units are set up using the same procedure as above ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 3 9 ChipScope Software a
30. elp Capture One Shot On Trigger AEA 1000 Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 extended Figure 35 Selecting One Shot Capture Mode ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 25 ChipScope Software and ILA Cores User Manual 9 XILINX Selecting On Trigger Capture Mode The On Trigger capture mode continues capturing data after each trigger condition is satisfied until the entire sample buffer is full You can set the number of samples captured per trigger to any value from 1 to 16 To select this mode click On Trigger in the trigger toolbar Figure 36 Select the number of samples per trigger from the Samples per Capture scrolling list box on the trigger toolbar Figure 36 For example 1f you select the trigger position 8 then 8 data samples are captured after each occurrence of the trigger condition until the ILA unit s capture storage resources are completely full In some cases the last occurrence of the trigger condition might result in fewer samples stored depending on the value of the Samples per Capture setting and the sample depth of the ILA unit ChipScope Analyzer demo Unit 0 Al ES File Communication Configure Busisignal Runfstop Data Window Help f S PP MIT amp Cu f Es o T m If o 1 oJo o m Trigger Condition boolean Mo j 0D me sampieBueter 1 al rigger Width 8 Signal Count 16
31. en trigger macros No Yes External Trigger Description The ChipScope software Analyzer can accept a trigger input signal and generate a trigger output signal for use with external test equipment An external trigger input signal must enter the device on a normal input pin connected to the ICON core unit where it is distributed to each of 15 possible ILA components in the design Similarly each ILA core unit can generate an output signal that is connected to the ICON unit The ICON unit then logically OR s all of the external trigger output signals and drives them to a single output pin on the device Users can enable each ILA core component to drive each respective external trigger output signal to the ICON core component without having to resynthesize the design ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 1 5 ChipScope Software and ILA Cores User Manual XILINX Capture Modes Each ILA core can capture data independently from all other ILA cores in the design Furthermore the ILA core can capture data using one of two capture modes one shot and on trigger The one shot capture mode uses a single trigger event such as a boolean or macro combination of the individual trigger match unit events to collect enough data to fill the sample buffer up to 4096 samples The trigger position can be set to the beginning of the sample buffer trigger first then collect the end of the sample buffer collec
32. er Position 0 2047 he 2 Zoom Out LL Bus Signal xo A Al eee H Zoom Area wwo p Signal_0 o 1l MTT TTT Fit vind ow y Signal o jo LL Togale Time state Display Signal 2 lo nnannnnannann SetClockPeriod Signal_3 o lo lan Signal_4 1 fo T LS LT L Derma wavetirm Signals i lho _Signal_6 o lo Signal i E eee Signal_8 A Signal o lo Ee _Bignal_10 ola _Bignal_11 o lo Signal_12 O aa _Bignal_13 o lo Signal_14 IA O Signal_15 A ee a TT EJE JE Ex Figure 54 Fitting the Waveform Display in the Window Toggling Time State Display The x axis of the waveform can be displayed as the sample number relative to the trigger event default or by a time unit per sample starting at the first sample captured By default the time unit 1s 5ns sample Setting a Sample Clock Period When the waveform is viewed with the x axis in time units the sample clock period can be modified with this option Units are always in ns 4 42 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Plot Values This option brings up a separate window with a bus or buses plotted in an x y format Two line types can be chosen a scatter plot which plots a single dot at each data point and a line plot which connects all the data points together with a line Separate buses are displayed in separate colors see Figure 55 with line graph chosen WY Pl
33. form window Figure 39 Data sample 0 is always at the location of the first trigger condition ChipScope Analyzer demo Unit O Al ES File Communication Configure BAS BEA Data Window Help Mi Mi width count fi Countf A A E mo 600 Capture One Shot On Trigger Position 0 2047 Ext Out Sample Buffer FULL Buffer eun Bus Signal Ss ignal_0 Signal _ Bignal_2 _ Bignal_3 Signal_4 Signal Signal_6 E signal_7 i Signal_5 0 tick 43 i Sinnal A 1 a Upload DONE Foro o oO CO Oo s PF Oo FO OOO O gs Figure 39 Viewing the On Trigger Capture Mode Waveform ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 29 ChipScope Software and ILA Cores User Manual 9 XILINX 4 30 Running and Stopping the Trigger Running Arming the Trigger After setting up the trigger select Run Stop gt Run to arm it The trigger stays armed until the trigger condition is satisfied or the user disarms the trigger Once the trigger condition is satisfied the trigger automatically disarms and the captured data appears in the waveform window To force the trigger select Run Stop gt Trigger Immediate This causes the ILA unit to ignore the trigger condition and trigger immediately After the sample buffer fills with data the trigger disarms and the captured data appears in the waveform window Stopping Disarming the Trigger To disarm the trigger select Run Stop gt Stop Acquisition If the tri
34. g File gt New Opening an Existing Project To open an existing project select 1t from the list of recently opened projects or select File gt Open Project and browse to the project location When the desired project is located double click on 1t or select Open Saving Projects If a project has changed during the course of a session the user will be prompted to save the project upon exiting the Core Inserter A project can also be saved by selecting File gt Save To rename the current project or save 1t to another filename select File gt Save As type in the new name and click Save Exiting the Core Inserter To exit the ChipScope Core Inserter select File gt Exit If the current project has not been saved the user will be prompted to save or quit v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Core Inserter Inserting and Removing ILA Units New ILA units can be inserted into the project by selecting Edit gt New ILA Unit An ILA unit can be removed by selecting Edit gt Remove Unit after selecting which ILA unit to delete Setting Preferences Three external programs Design Manager ChipScope Analyzer and Edif2Ngd can be called by the ChipScope Core Inserter The manner in which these programs are called can be altered by selecting Edit gt Preferences Inserting the Cores ICON and ILA Cores are inserted when the flow is completed or by selecting Insert gt Insert Core If all cha
35. gger condition has been satisfied at least once before the acquisition is stopped the ChipScope program disarms the trigger and displays the captured data Subsequent selections of Run Stop gt Run cause the trigger to re arm Using Buses and Signals Grouping Signals Into a Bus You can group up to 64 signals to form a bus Hold down the shift key and use the mouse to select one or more ungrouped signals in the Bus Signal display then select Bus Signal gt Group Into Bus When the text input box opens enter a name for the new bus then click Enter Names must be unique and may contain only letters numbers and underscores Figure 40 ChipScope Analyzer demo Unit O ChipScope Analyzer demo Unit O File Communication Configure MENE ASPE Run stop Data Fie Communication Configure Bu ajjaj gt aft JE Map Capture One Shot On Trigger Positi eae aft pe Ontario ler mof elo 1 0J0 00 ojm peo Mi Width Count fi Trigger Capture One shotf on Trigger Sa MOE RENAmEe SOS Alle Bit rdering EU ne x 0 Channel Numbers m CE 2 E An i Signal a l l ill Color Eoad Tokens Import Signal Mames v2 0 December 15 2000 Xilinx Development System XILINX Ungrouping Signals From a Bus Using the ChipScope Analyzer To ungroup a signal from a bus highlight a bus in the Bus Signal display window then select Bus Signal gt Ungroup From Bus This removes the bus and places all its sig
36. grated Logic Analyzer ILA units in VHDL and Verilog designs The easy to use interface allows users to customize control ports the number of ILA cores to be connected to the ICON core and control whether or not to use USER2 Boundary Scan port signals After the Core Generator validates the user defined parameters it generates an EDIF netlist edn and example code in VHDL and Verilog specific to the synthesis tool used Users can easily generate the netlist and code examples for use in normal Virtex Virtex E and Spartan II design flows The first screen in the Core Generator offers users the choice to generate either an ICON core or an ILA core Choose ICON Integrated Controller core and click Next Choosing the File Destination The destination for the ICON EDIF file icon edn is displayed in the Output Netlist field The default directory is the Core Generator install path To ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 2 1 ChipScope Software and ILA Cores User Manual XILINX 2 2 change it the user can either type a new path in the field or select Browse to navigate to a new destination Entering the Number of Control Ports The ICON core can communicate with up to 15 ILA core units at any given time However no ILA core unit may share its control port with any other ILA unit Therefore the ICON core needs up to 15 distinct control ports to handle this requirement Users can selec
37. h Duration click Width Figure 31 The match condition is true only if the match condition value is detected for at least n clock cycles in a row where n can be any value from 1 to 65 536 For a subsequent occurrence of the match condition to become satisfied the match condition pulse must return to its non active state in order to reset the Pulse Width Duration detection logic ChipScope Analyzer demo Unit O Al ES File communication a SU Data Window Help Mt ich J count fr Mt ich J count fr Countfi Se AAA A HO AND ca width Duration Capture One Shot On Trigger Position 0 2047E 1000 rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 1 extended Figure 31 Selecting the Pulse Width Duration ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 2 ChipScope Software and ILA Cores User Manual 9 XILINX To measure the Trigger Event Count click Count Figure 32 The match condition is true only 1f the match condition value is detected for at least n clock cycles not necessarily in a row where n can be any value from 1 to 65 536 The match condition Trigger Event Count automatically resets after the match condition is satisfied ChipScope Analyzer demo Unit 0 el File Communication Configure m SR Data Window Help hit Width Count ao Trigger eS 1 am A Capture One Shot On Trigger Position 0 2047 lo Ext Out 4 Sample Buffer rigger
38. heckbox Generating the Core After entering the ICON core parameters click Generate Core to create the netlist and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process The user can choose to either go back to respecify options or Start Over ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 2 3 ChipScope Software and ILA Cores User Manual XILINX Using the ICON Core To instantiate the example ICON core HDL files into your design use the following guidelines to connect the ICON core port signals to various signals in your design e Connect one of the ICON core s unused CONTROL port signals to a control port of only one ILA core instance in the design e Leave any unused CONTROL ports of the ICON core unconnected They are removed automatically during the implementation process Generating an ILA Core 2 4 The ChipScope Core Generator gives users the ability to define and generate a customized ILA capture core to use with VHDL and Verilog designs The easy to use interface allows users to customize the maximum number of data sample words stored by the ILA core the width of the data sample words and the width of the trigger word if different from the data word After the Core Generator validates the user defined parameters 1t generates an EDIF netlist edn and VHDL and Verilog example code
39. hoose a color highlight the signal or bus then select Bus Signal gt Color A color palette opens from which a discrete or customer v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer color can be chosen in a variety of ways A bus and its component signals can have different colors Figure 49 ChipScope Analyzer demo Unit O File communication Sample Buffer FULL Choose Color Swatches HSE Ree configure Trigger Condition boolean x 0 1 1 Signal mi o _Bignal_2 o lo _Signal_3 ofo Signal Y E ENEE FRun stop Date er a Bone manana eiam eis hove Lip hove Down Rename Shue BUS Bitarderitd Channel Numbers liada keres Import Signal Mames el E PES E 6 Fl Ut Le Rees See __ mie eee eee eee eee ISR 1 1 14591 1 JSR 1 1 1144934 1 HI O See 1 1 1 1 10594 1 1 w RRS Cele 1 1 aa eee Pra i P EE E Peer 1 1 O 111111 eee aaa CCC MA aaa O O Sample Text Sample Text Ped Es O Sample Text Sample Text ChipScope Analyzer demo Unit O File communication Configure Trigger Condition boolean Sample Buffer FULL Bus Signal E 4ddress Signal_0 Signal_1 Signal_2 Signal_3 Poo OFF gs _Signal_4 Busisignal Runfstop Data Window EJE O AND p eleja
40. iProgram Filesiilimdichipscope Betaldermo cpj Figure 17 Opening a USB Connection to MultiLINX Closing the MultiLINX Connection Select Communication gt Close Port to close the connection to the MultiLINX cable You must re establish a connection to the MultiLINX cable before any communication between the ChipScope program and the ILA units in the target device can resume v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Getting MultiLINX Cable Information You can upload information pertaining to the MultiLINX cable such as the hardware version memory size etc by selecting Communication gt Get Cable Information See the sample dialog in Figure 18 for the MultiLINX cable information ES ChipScope Unit 0 G MultiLinx Information wHardwareversion 0001 wFirmwareversion 0100 wFPGAYersion 000C wAlgorthrersion 0000 dwlernorysize 00040000 wPostError 0000 dwPostData 00000000 dwPostData 06280000 Figure 18 Getting Cable Information Running MultiLINX Cable Diagnostics To verify that the MultiLINX cable is properly connected to and communicating with the host computer select Communication gt Run Diagnostics A dialog box opens reporting whether or not the cable is functioning properly You can also quickly verify that the MultiLINX cable is communicating with the host computer by turning the LED on the MultiLINX cable on and off To do this select the Co
41. idth of the trigger bus or the width of the Trigger Data bus when trigger is the same as data Valid numbers are even integers from 2 to 64 Data Depth The maximum number of data sample words that the ILA core can store is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit You can set the data depth to one of five values in the following list e Data Depth 256 samples data width of one block RAM 16 bits e Data Depth 512 samples data width of one block RAM 8 bits e Data Depth 1024 samples data width of one block RAM 4 bits e Data Depth 2048 samples data width of one block RAM 2 bits e Data Depth 4096 samples data width of one block RAM 1 bit Data Width if necessary The width of each data sample stored by the ILA core is called the data width If the data and trigger words are independent from each other the maximum allowable data width depends on the target device type and data depth with a maximum of 256 However 1f trigger data the data trigger width must be an even number between 2 and 64 Extended Matching If this option is checked a sophisticated set of match options is available for all match units The match options include e Finding one or more occurrences of an exact match of a trigger value or edge e Finding one or more occurrences of a range of trigger values e Detecting contiguous pulse width or non
42. in Target FPGA with ILA Cores User User Function Function PC with ChipScope Tools ChipScope Analyzer User Function wo JTAG Connection LS am AA a y Target Board cs_01_001204 MultiLINX or Parallel Cable III Figure 1 ChipScope Block Diagram Users can place the ILA and ICON cores into their design by generating the cores with the Core Generator and instantiating them into the source HDL code or inserting the cores into the post synthesis EDIF netlist using the Core Inserter The design is then placed and routed using the Xilinx Alliance Series or Foundation Series tools Next the user downloads the bitstream and analyzes the design with the ChipScope software Analyzer The ChipScope Analyzer contains many features that Xilinx FPGA designers need for thoroughly verifying their logic Table 1 1 User selectable data channels range from 1 to 256 and the number of sample sizes ranges from 256 to 4096 effectively doubling any FPGA logic analysis capability on the market today Users can change the triggers in real time without affecting v2 0 December 15 2000 Xilinx Development System Introduction their logic The easy to use ChipScope Analyzer leads designers through the process of modifying triggers and analyzing the data Table 1 1 ChipScope Features and Benefits Feature 1 to 256 user selectable data channels Benefit Accurately captures wide data
43. in to find 1ts composition Configure with Last Used Settings same as Configure gt JTAG or Configure gt Slave Serial whichever was last used Trigger Setup same as Data gt Trigger Setup Run same as Run Stop gt Run F5 Stop same as Run Stop gt Stop F9 Trigger Immediate same as Run Stop gt Trigger Immediate Ctrl F5 Go To X Marker same as Data gt Go To gt X Marker Go To O Marker same as Data gt Go To gt O Marker Go To Trigger same as Data gt Go To gt Trigger Zoom In same as Data gt Zoom In Zoom Out same as Data gt Zoom Out Zoom Area same as Data gt Zoom Area Fit Window same as Data gt Fit Window v2 0 December 15 2000 Xilinx Development System XILINX Revision History Using the ChipScope Analyzer The following table shows the revision history for this document Date 03 06 00 06 30 00 12 15 00 Version 1 0 1 1 2 0 Revision Initial release Deleted ILA Core 0 5 and Earlier section Added Parallel Cable III references Removed Tutorial old Chapter 4 Added Using the ChipScope Analyzer new Chapter 4 Defined ChipScope Tools and its components ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 45
44. indow After selecting the configuration mode the Configuration Selection dialog box Figure 23 opens This dialog reflects the configuration choice and defaults to a blank entry for the configuration file ChipScope supports MCS BIT and RBT files as inputs Chip5cope Unit O x Configuration Mode JTAG configuration File Directory Select Mew File Figure 23 Selecting a Part ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 13 4 14 ChipScope Software and ILA Cores User Manual 9 XILINX To select the BIT file to download click on Select New File The Open Configuration File dialog box Figure 24 opens Using the browser select the device file you want to use to configure the target device It is important to select a BIT file generated with the proper BitGen settings For example if the target device is configured using the JTAG port then use the BitGen option g StartupClk JtagClk when creating the configuration file Do not use this BitGen option if the target device is configured using slave serial mode Once you locate and select the proper device file click Open to return to the Configuration Selection dialog Open Configuration File Ma ES Look ir 3 synplicity ex laa lla_v300_jtag roce File name fila_w300 mes Files of type fall Files Cancel Figure 24 Opening a Configuration File Once the mode and BIT file have bee
45. ions box see Figure 7 under the Match Settings is where the user selects the signals that connect to the ILA core If trigger is separate from data then Clock Trigger and Data must be specified when trigger equals data only Clock and Trigger Data must be specified ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 3 7 ChipScope Software and ILA Cores User Manual 9 XILINX Double clicking on the Clock Net label or clicking on the plus sign next to it expands into the following only the Net Connections box is shown et Connections E ILA UNIT TRIGGER NETS DATA NETS Figure 7 ILA Core Clock Specification Modifying the Clock Connection can be achieved by double clicking on the CHO label or highlighting it and clicking Modify Connections The Select Net dialog box appears see Figure 8 ES Select Het Pattern Structure clk fe crt O cnt 1 cnt cnt 3 counte rii counter 0 counter 1 1 counter 1 2 counter 1 3 counter 1 4 counter 1 5 E d m PA mT Select Cancel Figure 8 Select Net Dialog This dialog provides an easy interface to choose nets to connect to the ILA core All the design s nets of the given hierarchical level appear in the Nets panel on the right and the structure of the design can be traversed using the Structure panel on the left Net names can be filtered for key phrases using the Pattern text box and Filter button Once th
46. ject Device 1 Unit 0 save Project Device 1 Unit 1 save Project As Device 1 Unit 2 Import Waveform Device 1 Unit 3 EXPONE none Device 1 Unit 4 Close Device 1 Units Exit Device 1 Unite Device 1 Unit Device 1 Unit Device 1 Unit 9 Device 1 Unit 10 Device 1 Unit 11 Device 1 Unit 12 Device 1 Unit 13 Device 1 Unit 14 Tag Chain Info Figure 11 Selecting New ILA Unit in Target Device 1 New ILA units are displayed in their own window and the Device Unit for a particular window is displayed in the title bar All the ILA units may be triggered at the same time by configuring each trigger in turn There is no current way to combine the waveform display or trigger setup amongst separate ILA units ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 3 ChipScope Software and ILA Cores User Manual 9 XILINX Working with Projects Projects hold important information about the ChipScope program state such as signal naming signal ordering bus configurations and trigger conditions They allow you to conveniently store and retrieve this information between Analyzer sessions When you first run the ChipScope Analyzer tool the Select Project dialog box Figure 12 opens allowing you to create a new project or open an existing project Chip5 cope Ea Select Project Open an Existing Project More Projects Clad example Create a new Project Figure 12 Selecting a Project Creating A New Proje
47. ke sure the design is adequately constrained to minimize this skew Figure 5 shows a sample of the ICON options When all ICON options have been set click Next ES ChipScope Core Inserter x File Edit Insert Tools Help oela eje al i 2 FA US Select Integrated Controller Options Parameters Y Enable External Trigger Input Pin Location jot 54 Y Enable External Trigger Output Pin Location vez Disable JTAG Clock BUFG Insertion lt Previous Next gt New ILA Unit A E Figure 5 ICON Options Choosing ILA Parameters and Options Notice that a new ILA unit has been created in the device hierarchy on the left The next step is to set up the ILA unit Figure 6 The top set of parameters specify the Trigger Settings Trigger Same as Data Use this option when the signals that you want to trigger on are exactly the same signals that you want captured This option also conserves CLB and routing resources in the ILA core but limits the data sample word width to the maximum trigger width of 64 bits This is the common mode with most ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 3 5 ChipScope Software and ILA Cores User Manual XILINX 3 6 logic analyzers Notice that when this option is checked the Data Width field disappears and Trigger Width is renamed to Trigger Data Width Trigger Width This specifies the w
48. llel Cable III to function properly If you have the Alliance Series or Foundation Series software on the system the driver is most likely installed If you need to install the driver follow these steps l Use Windows Explorer to locate the ChipScope installation usually C Program Files Xilinx ChipScope Open the cablelll folder in the ChipScope installation directory Run the cablelll installation by double clicking the Setup exe file in the cablelll folder Setup will guide you through the installation process ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 1 11 ChipScope Software and ILA Cores User Manual XILINX 1 12 v2 0 December 15 2000 Xilinx Development System 2 XILINX Using the ChipScope Core Generator Chapter 2 Using the ChipScope Core Generator Core Generator Overview The ChipScope Core Generator tool offers users an intuitive graphical user interface to generate the ILA controller core ICON and the analyzer ILA cores Once the cores are generated users can use the instantiation templates that are provided to quickly and easily insert the cores into their VHDL or Verilog design After completing the instantiation and running synthesis then users implement the design using the Xilinx implementation tools Generating an ICON Core The Core Generator gives users the ability to define and generate a customized Integrated CONtroller ICON unit to use with one or more Inte
49. lliance Series or Foundation Series implementation tools Generate Instantiate ICON and ILA ICON and ILA cores into the HDL source cores using the Core Generator Connect Synthesize buses and design internal signals Implement Design Download bitstream trigger and view waveforms using Chipscope Analyzer Synthesize design without ILA or ICON core instantiation Insert ICON and ILA cores into synthesized design EDIF netlist using Core Inserter ila_figure_2_flow sa_112900 Figure 2 ChipScope Tools Design Flow 1 4 v2 0 December 15 2000 Xilinx Development System 2 XILINX Introduction Trigger Settings The ILA core has two trigger modes basic and extended The basic trigger mode provides up to two trigger match units capable of detecting a single exact match for every trigger condition The extended trigger mode adds the ability to do range matching trigger pulse width duration measurement trigger event counting and if then trigger macros Table 1 2 compares the basic and extended trigger modes Table 1 2 Basic and Extended ILA Trigger Modes Basic Extended Trigger Mode Feature Mode Mode Up to two match units Yes Yes Trigger function combining all match units Yes Yes Match value and edge comparison Yes Yes Match range comparison such as gt 2 lt lt No Yes Trigger pulse duration measurement No Yes Trigger event count measurement No Yes If th
50. lues depend on the comparison type For instance when the comparison type is set to you can set each bit of the comparison value to one of the following e X Any value logical zero or logical one e 0 Logical zero only e 1 Logical one only e R Rising edge only e F Falling edge only e B Both edges rising edge or falling edge 6699 If the comparison type is set to something other than then you can set each bit of the comparison to one of the following e 0 Logical zero only e 1 Logical one only You can set the match word values by clicking on each bit until the desired value appears or by clicking on the bit value and typing the desired value If you move the cursor over a bit in the match word and do not click a tool tip dialog box opens displaying the bit position and current match value v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Setting Up Pulse Width and Event Count You can configure an extended match unit to find matches that occur over one or more clock cycles contiguously in a row or non contiguously not necessarily in a row If the match conditions must remain satisfied during a specific number of contiguous clock cycles then the match Pulse Width Duration must be measured If 1t only needs to occur for a specific number of clock cycles not necessarily in a row then the Match Event Count must be measured To measure the Pulse Widt
51. mmunication gt LED On and Communication gt LED Off respectively ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 9 ChipScope Software and ILA Cores User Manual 9 XILINX Opening a Parallel Cable Ill Connection ChipScope supports the Parallel Cable IN HW JTAG PC To open a connection to the Parallel Cable III make sure the cable is connected to one of the computer s parallel ports Select Communication gt Parallel Cable Figure 19 ChipScope prompts you for the port name Type the printer port name in the port selection box usually the default LPT 1 is correct and click OK If successful ChipScope queries the Boundary Scan chain to determine its composition see Configuring the Target Device s on page 11 If ChipScope returns the error message Failed to Open Communication Port verify that the Parallel Cable III is connected to the correct LPT port If you have not installed the Parallel Cable III driver follow the instructions in Installing the Parallel Cable III Driver on page 11 in Chapter 1 to install the required device driver software ChipScope Unit 0 File Bennie Configure 2 Parallel Port selection Bl Serial MUMILINX Cable Port LPT USB MultiLINX Cable Cancel Parallel Cable Agee Rone Game lhifahinavon Ases Figure 19 Opening a Parallel Cable lll Connection 4 10 v2 0 December 15 2000 Xilinx Development System 2 XILINX Using the Chip
52. n chosen click OK to configure the device Observing Configuration Progress While the device is being configured the status of the configuration is displayed at the bottom of the ChipScope window If using the MultiLINX cable first the cable is initialized for the type of configuration download being performed Next the progress of the bitstream download is displayed If the DONE status is not displayed a dialog box opens explaining the problem encountered during configuration If the download is successful the target device is automatically queried for the ILA core and the Trigger Setup toolbar is displayed v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Displaying JTAG ID Codes One method of verifying that the target device was configured correctly is to upload the device and user defined ID codes from the target device For instance to upload and display the user defined ID code 1 e the 8 digit hexadecimal code that can be set using the BitGen option g UserID select Configure gt Show USERCODE Figure 25 Use Configure gt Show IDCODE to display the fixed device ID code ChipScope Analyzer demo Unit 0 _ Oy ES Busisignal Runfstop Data Window Help File Communication Boundary Scan Setup JTAG Configuration art Enri show IDCODE show USRCODE successfully opened Parallel Cable port LPT1 CONE Figure 25 Uploading User Defined ID Code
53. nals in the root level Figure 41 ChipScope Analyzer demo Unit O File Communication Configure Mi Width Count f Trigger Capture One Shot On Trigger Po _ Bignal_4 Signal_5 Signal _ amp elos RunfStop Da ira a Bone Ungroup From Bus hove Lp hove Down Rename show As Bus Bit Ordering Channel Numbers Color Load Tokens Import Signal Mames ChipScope Analyzer demo Unit 0 File communication pee Bu Mit Width Count a Col Capture One Shot On Trigger Positic Ss ignal_0 Signal_1 y a Signal_2 Signal_3 Signal_4 Figure 41 Ungrouping Signals from a Bus Moving Buses and Signals To move buses and signals up and down in the display highlight a signal or bus then select Bus Signal gt Move Up or Bus Signal gt Move Down When the position of a signal in a bus is changed the bus values are recalculated and the new values appear in the wave display window Figure 42 Buses and signals can also be moved by dragging and dropping them in the left hand signal pane ChipScope Analyzer demo Unit O Communication Configure Mi Width Count mo A Capture One Shot On Trigger Po _Bignal_4 Signal_5 Signal_6 i Qinnal 7 ra i Bone Runfatop Dat Ungroup From Bus hove Lp Rename show As Bus Bit Ordering Channel Numbers Color Load Tokens Import Signal Mame
54. nd ILA Cores User Manual XILINX 3 10 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Chapter 4 Using the ChipScope Analyzer Analyzer Overview The ChipScope Analyzer tool interfaces directly to the ILA and ICON cores Users can configure their device choose triggers and view the results of the capture on the fly The waveforms and triggers can be manipulated in many ways providing an easy and intuitive interface to determine the functionality of the design Analyzer Menu Features Selecting a Device ILA Unit A single target device 1 e a Virtex Virtex E or Spartan II device can contain up to 15 ILA units The host communicates through a separate ChipScope Analyzer window for each ILA unit You can select the current ILA unit only after you connect to the download cable and detect the Boundary Scan chain Select File gt New ILA Unit gt Unit n where n is the ILA unit number to choose a specific ILA unit Note that the ILA unit number corresponds to the control port the ILA core is connected to in the case of instantiation or the Unit ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 ChipScope Software and ILA Cores User Manual 9 XILINX number in the case of Core Insertion Figure 10 shows how ILA Unit 1 is selected lel ES ChipScope Analyzer demo Unit O E communication Configure Busfsigral Runfstop Data Window Help Mew ILA Unit
55. nnels of all the ILA cores are not connected to valid signals an error message results Launching Related Tools Both the Xilinx Design Manager and the ChipScope Analyzer can be launched from the ChipScope Core Inserter by selecting Tools gt Design Manager or Tools gt ChipScope The locations of these programs can be specified in the Preferences Specifying Input and Output Files The ChipScope Core Inserter works in a step by step process The first screen you see Figure 3 shows what needs to be specified first the input design netlist and constraints file Click Browse to navigate to the directory where the netlist and constraint files are The Core Inserter will not write over the netlist or UCF files specified Instead a new netlist and UCF will be ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 3 3 ChipScope Software and ILA Cores User Manual 9 XILINX created with the _ila extension appended by default Figure 4 shows a project with input and output files specified When this step is completed click Next ES ChipScope Core Inserter A x File Edit Insert Tools Help oela 4 2 DERE Design Files Input Design Netlist Exprojectstlatusage_testibase edf Browse Input Constraints File Exprojectstlatusage_testibase ucf i i Output Design Netlist Exprojectstlatusage_testibase_ila ngo Browse Output Constraints File Exprojectsulalusage_testibase_ila ucf Browse
56. nx Development System XILINX Using the ChipScope Core Inserter Chapter 3 Using the ChipScope Core Inserter Core Inserter Overview The ChipScope Core Inserter is a post synthesis tool for users to generate a netlist that includes the user design as well as ICON and ILA cores parameterized accordingly The Core Inserter gives users the flexibility to quickly and easily use the ILA funtionality without resynthesizing the entire design and without any HDL instantiation ChipScope Core Inserter Menu Features Working with Projects Core Inserter projects hold all relevant information about source files destination files core parameters and core settings This allows the user to conveniently store and retrieve information about core insertion between Sessions ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 3 1 ChipScope Software and ILA Cores User Manual 9 XILINX 3 2 When the ChipScope Core Inserter is first opened all the relevant fields are completely blank ES ChipScope Core Inserter Al ES File Edit Insert Tools Help 2 Select Device Options esign Files Input Design Netlist Browse Input Constraints File WEAR Browse Output Design Netlist Browse Output Constraints File Browse Output Directory Browse Next 4 Figure 3 Blank Core Inserter Project The condition in Figure 3 can also be achieved by selectin
57. o equation However use the boolean equation if neither condition in the macro equation is used ChipScope Analyzer demo Unit 0 _ Oy ES File Communication RuwStop Data Window Help Capture One Shot On Trigger Postionto 20475 053 Ext Out Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 extended Figure 34 Selecting the Macro Trigger Condition 4 24 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Selecting One Shot Capture Mode The One Shot capture mode captures an entire sample buffer of data once the trigger condition is satisfied This capture method allows you to capture data both before and after the trigger condition 1s satisfied Click One Shot in the trigger toolbar Figure 35 to select the One Shot capture mode During the One Shot capture mode you can set the trigger position to anywhere from the beginning of the capture buffer Position 0 to the end of the capture buffer Position Sample Depth 1 To set the trigger position click inside the box to the right of the Position setting on the trigger toolbar Figure 35 For example if the trigger position is set to 1000 then the 1000 data samples captured before the trigger condition 1s satisfied are displayed along with 1047 samples captured after the trigger ChipScope Analyzer demo Unit O Al ES File Communication RuwStop Data Window H
58. ofs File Communication _ Renee Data Window Help a rono l Capture One Shot On Trigger Position 0 2047 roda Shot On Trigger Position 0 2047 fi 1000 Ext Out Sample Bufrer rigger width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 basic Figure 29 Setting the Basic Match Comparison Value 4 18 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Extended Match Unit Comparison Value If the match unit Mn where n is O or 1 depending on the number of trigger match units in the ILA core is an extended match unit then you can configure both the comparison type and value during trigger setup Figure 30 ChipScope Analyzer demo Unit 0 _ Oy x File Communication a eee Data Window Help se PERE recon l Capture One Shot On Trigger Position 0 2047 roda Shot On Trigger Position 0 2047 fi 1000 Ext Out Sample Bufter rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 basic Figure 30 Setting the Extended Match Comparison Type and Value The possible comparison types are e equal to e lt gt not equal to e gt greater than e gt greater than or equal to e lt less than e lt less than or equal to ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 19 4 20 ChipScope Software and ILA Cores User Manual XILINX The possible match comparison bit va
59. oom in to the center of the waveform display Figure 51 ChipScope Analyzer demo Unit 0 Data mo Elxxxx o 000 mij Elexxxfbxxx Tri Zoom In Bus Signal Ss ignal_0 Signal _Bignal_2 _Signal_3 _Bignal_4 Signal_5 Signal _ amp Signal 7 _ Bignal_8 Signal Signal_10 _Bignal_11 _Bignal_12 _ Bignal_13 _Bignal_14 _Bignal_15 aa ee A eso ete by E PrForoeregdorenaaodoocoooef G Figure 51 Zooming in to the Center of the Waveform Display ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 39 ChipScope Software and ILA Cores User Manual 9 XILINX You can also zoom in to a specific place in the waveform For example select Data gt Zoom In To gt X Marker to zoom in to the X cursor location Figure 52 Other zoom locations include the O cursor and first trigger position that is data sample 0 To zoom in to a specific area of the waveform select Data gt Zoom Area then click the left mouse button and drag to select an area of the waveform display Using this method the waveform display zooms in to the selected area LOL Es ChipScope Analyzer demo Unit O File Communication Configure Bus signal Runfstop Window Help a Pm TI Sl Slo amp Trigger Setup Go To j zoom In To Marker Mi Width Count f Trigger Condition boolean 2 Bae in Ea Bus Signal x o a Zoom Area ES Bignal_O owl
60. orm of a self extracting archive file ChipScopem n exe where m n denotes the current version 1 Select Start gt Run 2 Browse for ChipScopem n exe 3 Click Run 4 Follow the install wizard instructions The Analyzer can be installed separately from the Core Inserter and Core Generator Installing the Java Run time Environment If you have not already installed the Java Run time Environment 1 1 8 then download it from the ChipScope Suite the same way you downloaded the ChipScope Tools Next 1 Select Start gt Run to run the self extracting installation file 2 Browse for the jre1_1_8 win exe file you just downloaded v2 0 December 15 2000 Xilinx Development System XILINX 3 4 Introduction Click Run Follow the install wizard instructions Installing MultiLINX USB Driver for Windows 98 If you need to install the Multi_LINX cable under Windows 98 or Windows 2000 for USB 1 Make sure that the PWR and GND wires of the MultiLINX cable are connected to power and ground sources respectively 2 Plug the cable into the USB port of the host computer An installation dialog box opens 3 Click Have Disk 4 Browse the ChipScope Tools installation for the mltinx inf file This is typically installed in folder C Program Files Xilinx ChipScope data 5 Click OK and follow the installation wizard instructions Installing the Parallel Cable Ill Driver ChipScope requires a device driver for the Para
61. ot 311 460 409 350 307 256 204 153 102 a1 0 1000 795 591 386 181 24 228 433 636 42 1047 Figure 55 Example of X Y Plot Generating a Demo Waveform To generate a sample waveform for trying out various ChipScope features without using actual hardware select Data gt Demo Waveform Changing Waveform Window Focus If more than one ILA unit ChipScope window is open use Window gt Unit n where n is the ILA unit number to change focus between the windows Viewing the Help Pages The ChipScope help pages contain only the currently opened versions of the ChipScope software and each of the ILA core units Selecting Help gt About ChipScope Software displays the version of the ChipScope software Selecting Help gt About ILA Core displays the versions of all of the open ILA units ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 43 ChipScope Software and ILA Cores User Manual 9 XILINX ChipScope Main Toolbar Features In addition to the menu options other ChipScope commands are available on a toolbar residing directly below the ChipScope menu Figure 36 ChipS cope demo Unit 0 A ES File communication Configure BusiSignal Runfatop Data Window Help Figure 56 Main ChipScope Toolbar Display The toolbar buttons from left to right correspond to the following equivalent menu options 4 44 Open Cable Search JTAG Chain automatically detects the cable and queries the JTAG cha
62. pulse width or non contiguous event count trigger match conditions over a number of clock cycles Can be used in conjunction with other trigger match units to build the trigger condition boolean equation using AND OR Can be used in conjunction with other trigger match units to build the trigger condition macro equation using IF THEN For the ILA core that is being generated the Trigger Match Unit Type is selected for all match units at the same time Selecting the Number of Trigger Match Units The number of Trigger Match Units can be set to either one or two Selecting two trigger match units allows a more flexible trigger condition equation to be a combination of both match units Selecting one match unit conserves resources while still allowing some flexibility in triggering Selecting the Data Depth The maximum number of data sample words that the ILA core can store is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit You can set the data depth to one of five values 2 6 Data Depth 256 samples data width of one block RAM unit 16 bits Data Depth 512 samples data width of one block RAM unit 8 bits Data Depth 1024 samples data width of one block RAM unit 4 bits Data Depth 2048 samples data width of one block RAM unit 2 bits Data Depth 4096 samples data width of one block RAM unit 1 bits v2 0 December 15 2000 Xilin
63. r Type To generate the first part of the ILA core select one of the following trigger types e Trigger separate from data The trigger word is completely independent of the data word e Trigger same as data The trigger and data words are identical This mode is very common in most logic analyzers since users can trigger on any bit in the data word being collected This mode also conserves CLB and routing resources in the ILA core but limits the data sample word width to the maximum trigger width of 64 bits Selecting the Trigger Match Unit Type An ILA core trigger unit comprises one or more match units that contribute to the overall trigger condition by looking for a specific pattern on the trigger input The types of patterns and their occurrence over time that are looked for depend on the type of the match unit The ChipScope core generator handles basic and extended trigger match units The basic trigger match unit e Finds only one occurrence of an exact match of a trigger value or edge e Can be used in conjunction with other trigger match units to build the trigger condition boolean equation using AND OR ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 2 5 ChipScope Software and ILA Cores User Manual XILINX The extended trigger match unit Finds one or more occurrences of an exact match of a trigger value or edge Finds one or more occurrences of a range of trigger values Detects contiguous
64. rm display from a VCD file and export to VCD FBDF and ASCII files The VCD format is a common waveform viewer file format and the FBDF format is compatible with the Agilent Technologies 16700 Series logic analyzers The ASCII format is a text only list format that is well suited to a script parser or spreadsheet import To import a waveform select File gt Import Waveform A dialog box opens allowing you to browse for waveform files After locating and selecting the desired file click Open The waveform display in the ChipScope window now contains the imported waveform You can export a waveform file in a similar fashion To export the waveform to a VCD file select File gt Export Waveform gt VCD Export To export the ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 5 ChipScope Software and ILA Cores User Manual XILINX 4 6 waveform to a FBDF file select File gt Export Waveform gt FBDF Export To export the waveform to an ASCII file select File gt Export Waveform gt ASCII Export In each case a dialog box opens and you can browse for the desired storage folder location After finding the target location and entering the waveform file name click Save The waveform is now stored in the desired format Closing and Exiting ChipScope To close a ChipScope window select File gt Close To exit the ChipScope program select File gt Exit In both cases 1f you have not stored the waveform a dialog box opens
65. s ChipScope Analyzer demo Unit 0 File communication Bu z 2 gt mT E tas Mi Width Count m1 WidthfCount T Trigger Col Capture One Shot On Trigger Positic Bus Signal signal_4 _Bignal_5 Signal_6 fate Figure 42 Moving Buses and Signals ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 3 ChipScope Software and ILA Cores User Manual 4 32 Changing Bus and Signal Names XILINX To rename buses and signals anytime for easy identification click on the bus or signal to rename then select Bus Signal gt Rename A text input box Figure 43 opens prompting for the new name Names must be unique and Enter ChipScope Analyzer demo Unit 0 Communication Configure Rurndstop Dat ra ni Bue Ungroup From Bus hove Lp hove Dow Mt Width Count Capture One Shot On Trigger Po Bus Signal x cs ignal_4 1l show As Bus Bit Ordering Color Load Tokens Import Signal Mames _ Bignal_5 Signal_6 O 1 El Channel Numbers 1 I ational 7 ri may contain letters numbers or underscores Type the new name then click ChipScope Analyzer demo Unit File Communication Configure BL SESS hi Width Count M1 WwicthfCount Trigger Ec Capture One Shot On Trigger Positi Bus Signal x 0 cs ignal_4 al al Signal_5 iflill a Signal _ amp i
66. specific to the synthesis tool used Users can easily generate the netlist and code examples for use in normal Virtex Virtex E and Spartan II design flows The first screen in the Core Generator offers users the choice to generate either an ICON or ILA core Choose ILA Integrated Logic Analyzer and click Next Choosing the File Destination The destination for the ILA EDIF ila edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it the user can either type a new path in the field or select Browse to navigate to a new destination The user can choose from three types of names a long name in which the options are specified in the component name a short name ila edn or a custom name for the netlist the component name will be changed accordingly Either a long name or a custom name should be chosen if multiple ILA cores with different parameters are used in the design v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Core Generator The long file name indicates the various parameters specified for the ILA core Table 2 1 shows the meaning of the abbreviations Table 2 1 ILA Long Filename Abbreviations Abbreviation Meaning ddx Data Depth of size x dwx Data Width of size x twx Trigger Width of size x t_eq_d Trigger Equals Data ex or bx Extended or Basic Matching with x Units Selecting the Trigge
67. t the number of control ports from the Number of Control Ports pull down list Enabling the External Triggers Users can configure the ICON core to implement an external trigger input and an external trigger output 1 e two separate pins to trigger external test equipment To enable instantiation of the external input and output trigger pins select the appropriate Enable External Trigger Input and Enable External Trigger Output check box If the design does not require external triggers or if there are no usable pins for triggers be sure to not check these boxes If the pins are enabled then set their IOB location using the following steps 1 Find the external input and output trigger pad signals in the pad file produced by the place and route par tool The signals have the following suffixes U_icon_core ext_in_pad input e U_icon_core ext_out_pad output 2 Add pin LOC constraints to the ucf file so that par correctly places the external trigger pins Disabling JTAG Clock BUFG Insertion The ICON core communicates to the outside world via the USER1 JTAG scan chain that is clocked by the JTAG clock TCK By default this clock is placed on a global clock resource BUFG Checking this box disables that insertion This should be done only if global resources are very scarce placing the JTAG clock on regular routing even high speed backbone routing introduces skew To minimize this skew make sure the design is adequ
68. t until the trigger event or anywhere in between The on trigger capture mode uses multiple trigger events to perform repetitive measurements on the design under test Each trigger event can cause a capture of 1 to 16 data samples These repetitive measurements can continue until the captured data fills the sample buffer ILA and ICON Core Resource Usage Tables 1 3 1 4 and 1 5 show the ILA and ICON core resource usage Table 1 3 ICON Core CLB Resource Usage na LUTs Flops Slices Percentage pads p of XCV300 1 68 40 34 1 1 2 103 40 52 17 3 138 40 69 22 4 171 40 86 2 8 1 6 v2 0 December 15 2000 Xilinx Development System gt XILINX Introduction Table 1 4 ILA Core CLB Usage DataWidth LUTS Flops slices Or Xevsoo 2 57 103 52 17 4 60 111 56 1 8 8 66 127 64 l 16 78 159 80 2 6 32 105 225 113 3 7 64 154 355 178 5 8 a This table describes the ILA core with one match unit and the basic trigger function Table 1 5 ILA Core Block RAM Usage Trigger Data Samples Data Width 256 512 1024 2048 4096 2 1 1 1 1 2 4 1 1 1 2 4 8 1 1 2 4 8 16 1 2 4 8 16 32 2 4 8 16 32 64 4 8 16 32 64 a This table describes the ILA core with one match unit and the basic trigger function ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 l 7 ChipScope Software and ILA Cores User Manual XILINX
69. to the MultiLINX cable then click OK Make sure you select a port that is not in use by another resource Chip5cope D Serial Fort Selection Fot EOm11 Baud Rate Auto Figure 16 Selecting a Serial Port When the connection opens a success message appears in the status bar at the bottom of the ChipScope window At this point ChipScope queries the ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 4 7 ChipScope Software and ILA Cores User Manual 9 XILINX 4 8 Boundary Scan chain to determine its composition see Configuring the Target Device s on page 11 If the MultiLINX connection fails to open a dialog box opens notifying you of the problem Opening a USB Port MultiLINX Connection If the MultiLINX cable connects to the host computer by way of the USB port then select Communication gt Open USB Port Figure 17 When the connection opens a success message appears in the status bar at the bottom of the ChipScope window At this point ChipScope queries the Boundary Scan chain to determine its composition see Configuring the Target Device s on page 11 If the MultiLINX connection fails to open a dialog box opens notifying you of the problem ChipScope Analyzer demo _ Op ES File ent Configure BusiSignal Run Stop Data window Help Serial MultiLINs Cable JSB MoltiLiMNx Cable Parallel Cable Agee ont cata reido Uh Estes Reading projectfile C
70. vidth 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 1 extended Figure 32 Selecting the Trigger Event Count 4 22 v2 0 December 15 2000 Xilinx Development System XILINX Using the ChipScope Analyzer Setting Up a Boolean Trigger Condition The Trigger Condition field describes how the match units MO M1 and the external trigger input EXT can be combined to form an overall trigger condition Both basic and extended trigger match units can build boolean equations from the available match units and the external trigger input to form the overall trigger condition Select the boolean trigger condition type by choosing Boolean from the pull down menu not available in the basic trigger match type case To designate the equation click the buttons to the immediate right of the Trigger Condition field in the trigger setup toolbar For instance 1f you want the trigger condition boolean equation to be not MO or EXT Figure 33 do the following e Click twice on the first button to select MO 1 e not MO e Click once on the third button to select EXT e Click once on the middle button that reads AND to select OR Clicking the button until it is blank effectively removes the match condition or external trigger input out of the boolean equation ChipScope Analyzer demo Unit O la File Communication Configure A Data Window Help nr cn e o 0 00 Trigger Condition mo amt Ext Condition M
71. x Development System XILINX Using the ChipScope Core Generator Entering the Data Width The width of each data sample word stored by the ILA core is called the data width If the data and trigger words are independent from each other then the maximum allowable data width depends on the target device type and data depth However if the data and trigger words are the same then the data trigger width must be any even number in the range of 2 to 64 Selecting the Trigger Width The width of the trigger word used by the ILA core is called the trigger width If the data and trigger words are independent from each other then the trigger width can be any even integer in the range of 2 to 64 However if the data and trigger words are the same then both the data and trigger widths must be set to any even integer value in the range of 2 to 64 Choosing the Instantiation Template After choosing the parameters for the ILA core you can construct an instantiation template Click Next to view the Sample Code Generation Options then choose which synthesis tool and language to use The synthesis tools supported are e Exemplar LeonardoSpectrum e Synopsys FPGA Compiler e Synopsys FPGA Compiler II e Synopsys FPGA Express e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the instantiation template for the various synthesis tools To generate the ILA core without any e
72. xample files deselect the Generate Example Files checkbox Generating the Core After entering the ILA core parameters click Generate Core to create the netlist and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process The user can choose to either go back to respecify options or Start Over ChipScope Software and ILA Cores User Manual v2 0 December 15 2000 2 7 ChipScope Software and ILA Cores User Manual XILINX 2 8 Using the ILA Core To instantiate the example ILA core HDL files into your design use the following guidelines to connect the ILA core port signals to various signals in your design Connect the ILA core s CONTROL port signal to an unused control port of the ICON core instance in the design Connect all unused bits of the ILA core s data and trigger port signals to 1 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the imple mentation process If Trigger Same As Data is selected connect the data trigger signal s to the ILA core s DATA port signal The ILA core s TRIG port signal is disconnected in this case In the source code this port can be connected to the same bus as the DATA port or to all 1 s Make sure the data and trigger source signals are synchronous to the ILA clock signal v2 0 December 15 2000 Xili
73. y and The Programmable Gate Array Company are service marks of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx Inc devices and products are protected under one or more of the following U S Patents 4 642 487 4 695 740 4 706 216 4 713 557 4 746 822 4 750 155 4 758 985 4 820 937 4 821 233 4 835 418 4 855 619 4 855 669 4 902 910 4 940 909 4 967 107 5 012 135 5 023 606 5 028 821 5 047 710 5 068 603 5 140 193 5 148 390 5 155 432 5 166 858 5 224 056 5 243 238 5 245 277 5 267 187 5 291 079 5 295 090 5 302 866 5 319 252 5 319 254 5 321 704 5 329 174 5 329 181 5 331 220 5 331 226 5 332 929 5 337 255 5 343 406 5 349 248 5 349 249 5 349 250 5 349 691 5 357 153 5 360 747 5 361 229 5 362 999 5 365 125 5 367 207 5 386 154 5 394 104 5 399 924 5 399 925 5 410 189 5 410 194 5 414 377 5 422 833 5 426 378 5 426 379 5 430 687 5 432 719 5 448 181 5 448 49

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