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MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700

1. Symbol Parameter ae S Unit ta E Pia Port Pi data output delay time 80 ns ta AL E Address low order output delay time Note 15 ns tue pHa Data high order output delay time BYTE L 35 ns lp E ouz Data high order floating start delay time BYTE L o ns taam e Address middle order output delay time Note 15 ns taam ace Address middle order output delay time Note 5 ns tage otg Data low order output delay time 35 15 toxz E pLz _ Data low order floating start delay time oj ns taaH amp Address high order output delay time Note 15 ns taaH ate Address high order output delay time Note 5 ns tae output delay time 4 ns tw ALe ALE pulse width Note 22 nS tashe output delay time Note 20 ns taece e BLE output delay time Note 20 ns tarw E R W output delay time Note 20 ns ta e 91 output delay time 0 18 NnS thie aL Address low order hold time Note 18 ns tniace am Address middle order hold time BYTE 41 9 ns te oug Data high order hold time BYTE L Note 18 ns 2 Data high order floating release delay time BYTE L Note 20 ns te am X Address middle order hold time BYTE Note 18 ns tniace aH Address high order hold time 9 ns te o g Data low order hold time Note 18 ns lpxE D z Data low order floating release delay time Note 20 ns tE e
2. Address Register name Access characteristics State immediately after reset b7 b7 50 4016 Count start register RW 0016 4116 2 4216 start register 2 0 010 4316 4416 Up down register WO RW 0 0 0 0 010 NINN 4516 4616 RW Timer AO register 4716 2 RW 4816 RW Timer A1 register 4916 i RW 4 16 Note 1 2 4B16 Timer A2 register Note 1 3 4 16 Note 1 2 4016 Timer register Note 1 2 4E16 Note 1 AF 16 Timer A4 register Note 1 2 5016 Note 2 2 5116 Timer BO register Note 2 2 5216 Note 2 2 5316 Timer 1 register Note 2 2 5416 1 RW 2 5516 Timer 82 register RW 2 5616 Timer AO mode register RW 5716 Timer A1 mode register RW 5816 Timer A2 mode register RW 5916 Timer A3 mode register RW 16 4 mode register RW 5B16 Timer BO mode register RW 5 16 Timer B1 mode register RW Sse RW 5016 Timer B2 mode register RW Sete RW 5E16 Processor mode register 0 RW wolRw RW 16 Processor mode register 1 Notes 1 The access characteristics at addresses 4A16 to 4F16 vary according to Timer A s operating mode Refer to CHAPTER 8 2 The access characteristics at addresses 5016 to 5316 vary according to Timer B s operating mode Refer to CHAPTER 9 TIMER B 3 The access characteristic
3. APPENDIX Appendix 6 Machine instructions Addressing modes Processor status register L DIR L DIR Y ABS ABS ABS X ABS Y ABL ABL xX ABS ABS X STK RbR ABSbR sR SR Y 9 8 5 op 3 op op op op n it op op PL m 67 10 2 77 3 7D 3179 3 6F 7 7 4 63 73 42 12 3 42 42 42 42 42 42 42 67 77 7D 79 6F 63 73 27 10 2137 3D 39 23 33 42 3 42 42 42 42 42 42 42 27 37 3D 39 2F 3F 23 33 1E 0 pecifie comes 0 7721 Group User s Manual 17 43 APPENDIX Appendix 6 Machine instructions Functions Details Addressing modes R b DIR X D R Y DIR D s op op Note 2 X M Compares the contents of the index register X with the contents of the memory CPY Note 2 Y M Compares the contents of the index register Y with the contents of the memory DEC Note 1 Accc Acc 1 Decrements the contents of the accumlator or memory by DEX Xc X 1 Decrements the contents of
4. Inside dotted line not included Ports P8s TxDo P8z TxD 90 P92 DMAACK1 d Direction register P9 DMAACK2 ZI P104 CAS P10s RAS lt 1 Sod RA Mem BP 2 Databus 4 Portlatch internal perh Inside dotted line included Ports P5o TA2ovr P52 TA3ovr P54 TA4out Ports P60 RTPOo to P67 RTP 13 8 Direction register Databus 1 Portlatch 4 4 Latch T Q Timer underflow signal CK Fig 6 2 4 Port peripheral circuits 1 7721 Group User s Manual 6 5 INPUT OUTPUT PINS 6 2 Programmable I O ports Inside dotted line not included Ports 7 to P76 ANe Direction register h Inside dotted line included Port P77 AN7 ADrae Data bus 4 lt 4 Analog input Ports P80 CTSo RTSo P8 CLKo P84 CTS1 RTS 1 P8s CLK r Direction register n lt 1 Output e Data bus Port latch internal aero Port P103 TC 4 Direction register lt Output F Data bus 4 Port latch Te o i E output pin Fig 6 2
5. nnn nnn nnn nnn 17 2 Appendix Memo 8 anment in 17 3 Appendix 3 Control reqisters ccccccccsscssssseesecececsssseeeeeseacsseeeeeuenaueeseuseanaseseeaeauanaseseeneaneaesees 17 9 Appendix 4 Package outline 2 essen 4 1 14 acd nen dnu conu 17 40 ev 17 41 ei ta 17 42 e 17 56 17 59 17 65 Appendix 10 Differences betweer Loup 17 79 rupe 17 80 17 107 GLOSSARY 7721 Group User s Manual vii Table of contents MEMORANDUM 7721 Group User s Manual CHAPTER 1 DESCRIPTION 1 1 Performance overview 1 2 Pin configuration 1 3 Pin description 1 4 Block diagram DESCRIPTION 1 1 Performance overview 1 1 Performance overview Table 1 1 1 lists the performance overview of the M37721 Table 1 1 1 M37721 performance overview Parameters Number of basic instructions Functions 103 Instruction execution time 160 ns the minimum instruction at 25 MHz External clock input frequency f Xw 25 MHz maximum Memory sizes ROM External M37721S2BFP 1024 bytes con M37721S1BFP 512 bytes Programmable Input Output 5 10 8 bits X 6 ports P4 5 bits X 1 Multifunctional timers 0 4 16 bi
6. tw RASL gt th RAS RA ta E RASH gt RAS output td R W RAS th CAS R W CAS output At write MAo MAg output R W output D RAS output At refreshing ta CAS RAS th RAS CAS CAS output Test conditions 5 10 Output timing voltage 0 8 V 2 0 V Do Dts input 0 8 V 2 5 V 17 96 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics DMAC switching characteristics Vcc 5 V 10 Vss 0 Ta 20 to 85 25 MHz unless otherwise noted Note The limits depend on f X Table 6 lists calculation formulas for the limits Symbol Parameter ROX Unit DMAREQi input setup time 60 ns twbRo input pulse width 80 ns tagi st 5 0 ST1 output delay time 40 15 ta gi pak output delay time 60 ns ta AL e Address low order output delay time Note 15 ns tae pHa Data high order output delay time BYTE L 35 15 2 Data high order floating start delay time BYTE L oj ns Address middle order output delay time Note ns tae pLa Data low order output delay time 35 ns 2 Data low order floating start delay time ol ns Address high order output delay time Note 15 ns taace e
7. 14 2 14 2 1 DRAM control 14 3 14 2 2 Refresh 14 5 14 2 3 Address 0 14 6 14 2 4 RAS and CAS generating 14 6 Em 14 6 14 3 Setting for DRAMYQ onn rana nna nan n n ni nura naa a nam a 14 7 14 4 DRAMC operatiOn eec ones nin ra nx cuu sanewaencenuwennedecunasweweeaedanwacadweanusntvesucwasssbanskuncseswnes 144 Tec MEER 14 10 14 5 Precautions for 14 12 vi 7721 Group User s Manual Table of contents CHAPTER 15 WATCHDOG 16 1 Memory CONNECTION 0 ccccccececessecsseseceeseseussecnsseueususeseusneeeauseuenssseaeasseeaeasseuagessanaessnaeas 16 2 6 1 1 Memory connection 0000400 16 2 16 1 2 How to calculate 0 2 2 0 APPENDIX Appendix 1 Memory assignment of 7721
8. Transfer start 7721 Group User s Manual 13 45 DMA CONTROLLER 13 4 Operation Table 13 4 9 Address directions in 1 bus cycle transfer and examples of transfer results 2 Address direction External data bus width 16 bits External data bus width 16 bits or 8 bits Transfer unit 16 bits Transfer unit 8 bits Transfer source Transfer destination memory Fixed Transfer source Low order Data High order sequence Data arrangement on transfer destination memory transfer result Transfer Low order Data High order Transfer source Data Transfer sequence gt Data arrangement on transfer destination memory transfer result Data Forward Low order Data High order Low order Low order Data Low order Data Backward Transfer start 13 46 Low order Data High order Low order Data 4 High order Low order Data 4 High order 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Precautions for 1 bus cycle transfer 1 The area that overlaps with internal RAM and SFRs must not be assigned to an external memory When the contents in the overlapped area are read the data of internal RAM or SFRs and that of external memory are simultaneously placed on the data bus and they collide with eac
9. When internal trigger is selected Note Writing to each bit except bit 6 of the A D control register must be performed Trigger occur while the A D converter halts before a trigger occurs 5 Operation start Fig 12 5 1 Initial setting example for registers relevant to one shot mode 7721 Group User s Manual 12 15 A D CONVERTER 12 5 One shot mode 12 5 2 One shot mode operation description 1 When an internal trigger is selected The A D converter starts operation when the A D conversion start bit is set to 1 The A D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register i At the same time as step the conversion interrupt request bit is set to 1 The A D conversion start bit is cleared to 0 and the A D converter stops operation 2 When an external trigger is selected The A D converter starts operation when the input level to the pin changes from to L while the A D conversion start bit is 1 A D conversion is completed after 57 cycles of 4 Then the contents of the successive approximation register conversion result are transferred to the A D register i At the same time as step 2 the A D conversion interrupt
10. Edge sense Level sense select bit Note 00 Fixed 0 Edge sense 01 Forward 1 Level sense 1 0 Backward ean 1 1 Do not select DMAACKi validity bit 0 Invalid 1 Valid Transfer destination address direction select bits 00 Fixed 0 1 Forward 1 0 Backward Note When an external source DMAREQi 1 1 Do not select is selected or when the cycle steal transfer mode is selected set this bit b7 b0 DMAO mode register Address 1FCD16 to 0 1 DMA1 mode register H Address 1FDD16 Loli p ofo DMA2 mode register H Address 1FED16 i p mode register Address 1FFD16 Continue to Figure 13 6 4 on next page Transfer direction select bit Used in 1 bus cycle transfer 0 From memory to I O 1 From I O to memory connection select bit Valid in 1 bus cycle transfer 0 Data bus Do D or 015 1 Data bus Ds Dis Transfer source wait bit Valid in DMA transfer 0 Wait 1 No wait Transfer destination wait bit Valid in DMA transfer 0 Wait 1 No wait NL Selection of repeat transfer mode E 623 6100015 68 b7 b0b7 6067 50 Source address register 0 Addresses 1 216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1 216 to 1 016 SAR2 Source address register 3 Addresses 1 216 to 1 016 SAR3
11. Notes 1 Average output current is the average value of a 100 ms interval 2 The sum of loreak for P8 P9 Ao MAc A7 MAz As Ds Ais Dis Aie Do A23 D7 STO ST1 ALE BLE and R W must be 80 mA or less the sum of loupea for P8 P9 As De Ais Dis 1 STO ST1 ALE BLE and R W must be 80 mA or less the sum of for P4 P5 P6 P7 P10 and must be 80 mA or less the sum of for P4 P5 P6 P7 P10 and must be 80 mA or less 7721 Group User s Manual 17 81 APPENDIX Appendix 11 Electrical characteristics Electrical characteristics Vcc 5 V Vss 0 V Ta 20 to 85 C 25 MHz unless otherwise noted Symbol Parameter Test conditions yin We Max Unit High level output _ 7 As Ds A1s D1s A16 DoA23 D7 4 voltage P47 P5o P57 P7o P77 8 8 P9r P9r 10 10 RESETour 9 0 9 10 mA ST1 ALE BLE BHE R W High level output As Ds Ais Dis 2 07 MAg voltage RAS CAS STO ST1 BLE R W 7400 uA X High level output ALE lou 10 mA 3 1 voltage lon 400 uA 4 8 V High level output E lon 10 mA 3 4 volta
12. Symbol Parameter im x Unit tc External clock input cycle time 40 ns twh External clock input high level pulse width 15 ns twi External clock input low level pulse width 15 ns tr External clock input rising time 8 ns External clock input falling time 8 ns tsupin E Port Pi input setup time i 4 10 60 ns th E PiD Port Pi input hold time i 4 10 0 ns Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C 25 MHz unless otherwise noted Symbol Parameter 1 Unit Port Pi data output delay time i 4 10 80 ns ta AL Address low order output delay time Note 15 ns tae pHa Data high order output delay time BYTE 1 35 ns 2 Data high order floating start delay time BYTE L 0 ns la AM E Address middle order output delay time Note 15 ns taAv ALE Address middle order output delay time Note 5 ns ta E DLa Data low order output delay time 35 15 tpxz e pLz Data low order floating start delay time 0 ns Address high order output delay time Note 15 ns taaH atey Address high order output delay time Note 5 ns taate e ALE output delay time 4 ns tw ALe ALE pulse width Note 22 ns tasHe e output delay time Note 20 ns taste BLE output delay time Note 20 ns la R W E R W output delay time Note 20 ns output delay time 0 18 NS th E AL Address low order hold time Note 18 ns
13. 7 1 restored the contents S it becomes its value nd the other cases are no hange Value saved in stack 7721 Group User s Manual 17 51 APPENDIX Appendix 6 Machine instructions Addressing modes Symbol Functions Details DIR DIR b DIR X DIR Y DIR DIR X 0 OP op OP OP n SEB Makes the contents of the specified bit in the memory 1 0418 3 Note 5 SEC Makes the contents of the C flag 1 SEI Makes the contents of the flag 1 SEM Makes the contents of the m flag 1 SEP Set the specified bit of the processor status register s lower byte PSL to 1 STA Stores the contents of the accumulator into the memory Note 1 Stops the oscillation of the oscillator Stores the contents of the index register X into the memory Stores the contents of the index register Y into the memory Transmits the contents of the accumulator A to the direct page register Transmits the contents of accumulator A to the stack pointer Transmits the conten he accumulator A to the index register X Transmits the con he accumulator A to t
14. E 5 5 5 8 5 9 5 9 Precautions for Wait 5 11 CHAPTER 6 INPUT OUTPUT PINS 6 2 Programmable I O ports 6 2 1 Direction register 7 6 Interrupt priority level detection time 7 11 Precautions for interrupts ii 7721 Group User s Manual Table of contents CHAPTER 8 TIMER A E M Seca 9 5 E E E 9 6 9 2 5 Port P5 direction register nennen 9 7 PYV 9 8 A 9 10 9 3 2 Count SOULCO i circicsavesesassseesdscsssccctareiatcueteisnsaranaedsarevavadacarevenenduaveasaccsancudiabanaasenandaaienes 9 11 IP 9 12 P S 9 13 9 14 mer 9 16 HEP 9 17 Precautions for event coutner 9 18 7721 Group User s Manual iii Table of contents 9 5 Pulse period Pulse width measurement 9 19 9 5 1 Setting for pulse period pulse width measurement 9 21 9 5 2 SOUC TUE 10 3 Setting of real time
15. 10 7 10 4 Real time output 10 10 CHAPTER 11 SERIAL I O E E E 11 2 mM 11 3 mE 11 4 11 2 2 UARTI transmit receive control register 0 11 6 T 2 3 VARI transmit receive control register jj MERC 11 7 hrono dE 11 31 npo 11 32 EEE Transfer data formation a a 11 33 11 4 3 Method of 11 34 11 38 11 41 11 44 rovc 11 46 ERATUM 11 47 7721 Group User s Manual Table of contents CHAPTER 12 CONVERTER ae 12 2 12 3 A D 22222 na esa eret saa 12 4 12 2 2 A D sweep pin up 12 6 12 2 3 ACD register i 0 12 7 mo 12 8 12 2 5 Port P7 direction 2 4 4 0040 0 nnn 12 9 Mure 12 10 12 4 Absolute accuracy and differential non li
16. 4 1 Hardware reset 4 2 Software reset qd 4 RESET RESET 4 1 Hardware reset 4 1 Hardware reset When the power source voltage satisfies the microcomputer s recommended operating conditions the microcomputer is reset by supplying L level to the RESET pin This is called a hardware reset Figure 4 1 1 shows an example of hardware reset timing RESET 2ysormore 4 to 5 cycles of a p gt Internal processing sequence after reset Program is executed 4 p td 4 Note When the clock is stably supplied Refer to section 4 1 4 Time supplying L level to RESET pin Fig 4 1 1 Example of hardware reset timing The following explains how the microcomputer operates in periods to above After supplying L level to the RESET pin the microcomputer initializes pins within a period of several ten ns Refer to Table 4 1 1 While the RESET pin is L level and within a period of 4 to 5 cycles of after the RESET pin goes from L to H the microcomputer initializes the central processing unit CPU and SFR area At this time the contents of the internal RAM area become undefined except when Stop or Wait mode is terminated Refer to Figures 4 1 3 to 4 1 9 After the microcomputer performs Internal processing sequence after reset Refer to Figure 4 1 10
17. CPU Central Processing Unit BIU Bus Interface Unit Watchdog timer frequency select bit Bit O at address 6116 Note This signal is generated when the watchdog timer s most significant bit becomes 0 Fig 5 2 1 Clock generating circuit block diagram 7721 Group User s Manual 5 3 CLOCK GENERATING CIRCUIT 5 2 Clocks 5 2 1 Clocks generated in clock generating circuit 1 9 It is the operation clock of BIU It is also the clock source of cev stops by acceptance of Ready request or execution of the STP or WIT instruction It is not stopped by acceptance of bus request 2 It is the operation clock of CPU cru stops by the following Execution of the STP or WIT instruction Acceptance of Ready request L level input to the RDY pin CPU wait request from BIU Acceptance of bus request is included 3 Clock It has the same period as and is output to the external from the pin Clock stops by execution of the STP instruction It is not stopped by acceptance of Ready or bus request or execution of the WIT instruction 4 fe to fs Each of them is the internal peripheral devices operation clock Note Refer to each functional description for details Execution of STP instruction 5 3 Stop mode Execution of WIT instruction 5 4 Wait mode entire n genere 3 3 Ready function Bus
18. 000080 Internal 00047 16 RAM area Not used 000000 gt gt gt gt gt n gt 001FCO 001FFF SFR area W m A17 D1 A18 D2 5 A20 D4 E0000016 21 05 d 22 06 J DRAM area A23 D7 M5M417800CJ FFFFFF16 a Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00102 Fig 16 1 22 Example of M5M417800CJ 2M X 8 bits connection external bus width 8 bits 16 26 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt tw EL 135 min tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max td E CASL 77 5 max tw CASL 92 5 min td RA RAS 5 min 5 min td CA CAS 5 min Wr Row address Column address tOEA 20 max gt tAA 35 max td E CA 60 max tpzx E DLZ 20 min tRAC 70 max 2 ________ Input data acts td AH E 15 min 20 max tsu DL E gt 30 tcLz 5 min toEZ 0 15 A10 M5M417800AJ tASR 0 AC573 lt When writing gt m lt tw EL 135 min tw RASH 60 min pem tw RASL 120 min RAS z min E tw CASL 55 min CAS d E CASL 80 11 lt ta SL 80 115 AC32 tPHL A
19. Fig 14 2 1 Block diagram of DRAMC 14 2 7721 Group User s Manual DRAM CONTROLLER 14 2 Block description 14 2 1 DRAM control register Figure 14 2 2 shows the structure of the DRAM control register 67 66 65 64 63 62 61 b0 DRAM control register Address 6416 C2 b3 b DRAM area select bits No DRAM area F000001e FFFFFF16 0000016 1 D000001e FFFFFF 16 C000001e FFFFFF 6 B00000 e FFFFFF 6 0000016 16 90000016 16 80000016 FFFFFFi6 70000016e FFFFFFi6 60000016e FFFFFFi6 50000016e FFFFFFi6 40000016 FFFFFFi6 30000016 FFFFFFi6 20000016 1 10000016 16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 lt o oF ONO Oi ODE OOS 3 6 to 4 Nothing is assigned The value is 0 at reading DRAM validity bit Note 0 Invalid P104 P107 pins function as programmable input ports Ao pins function as address output pins Refresh timer stops counting 1 Valid 104 107 pins function as CAS RAS MAs and function as MAc MAr Refresh timer starts counting Note Set the refresh timer address 66 6 before setting this bit to 1 Fig 14 2 2 Structure of DRAM control register 7721 Group User s Manual 14 3 DRAM CONTROLLER 14 2 Block description 1 DRAM are
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21. 4 2 2 11 13 2 1 Bus access control circuit 5 4 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 3 Stop mode 5 3 Stop mode Stop mode is used to stop oscillation when there is no need to operate the central processing unit CPU The microcomputer enters Stop mode when the STP instruction is executed Stop mode can be terminated by an interrupt request occurrence or the hardware reset 5 3 1 Stop mode When the STP instruction is executed the oscillator stops oscillating This state is called Stop mode In Stop mode the contents of the internal RAM can be retained intact when Vcc power source voltage is 2 V or more Additionally the microcomputer s power consumption is lowered It is because the CPU and all internal peripheral devices using clocks fz to fs stop the operation Table 5 3 1 lists the microcomputer s state and operation in and after Stop mode Table 5 3 1 Microcomputer s state and operation in and after Stop mode Item State and Operation State in Oscillation Stop mode cpu Stopped Clock 1 12 to 1512 Timers A B Can operate only in event counter mode Serial I O Can operate only when an external clock is selected 5 A D converter Stopped DMA controller 8 DRAM controller Stopped Note 5 gt Watchdog timer Stopped 5 Pins Retains the same state in which the STP instruction was executed Operation By interrupt re
22. i When writing 1 DMA request is generated E nuum huuc DMA transfer starts Fig 13 6 4 Initial setting example for registers relevant to repeat transfer mode 3 7721 Group User s Manual 13 65 DMA CONTROLLER 13 6 Repeat transfer mode 13 6 2 Operation in repeat transfer mode Figure 13 6 5 shows the operation flowchart of the repeat transfer mode and Figure 13 6 6 shows a timing diagram of the repeat transfer mode burst transfer mode For the cycle steal transfer mode refer to the following All transfers except for the last 1 unit transfer Figure 13 8 12 Last 1 unit transfer Figure 13 8 13 Also refer to section 13 2 1 Bus access control circuit for the bus request sampling during transfer request bit lt 0 Only in cycle steal transfer mode 1 unit transfer Refer to section 13 4 Operation Burst Edge Burst Level L Cycle steal Requested DMAi request bit 0 BurstLevel H Cycle steal No request Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREGi pin s input level L Burst Level H burst transfer mode level sense with DMAREGi pin s input level Cycle steal Requested In cycle steal transfer mode with any request of DMA0 3 Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 Fig 13 6 5 Operation flowchart of repeat transfer mode 13 66 7721 Gro
23. 00 Up down register Address 4416 Fix these bits to 0 1 Countup This function is valid when the contents of the up down register is selected as the up 5 Timer A2 two phase pulse signal 0 Two phase pulse signal WO processing select bit Note processing function disabled 1 Two phase pulse signal Timer A3 two phase pulse signal processing function enabled WO processing select bit Note When not using the two phase pulse Timer A4 two phase pulse signal signal processing function set the bit to 0 processing select bit Note value is 0 at reading Note Use the LDM or STA instruction for writing to bits 5 to 7 Fig 8 4 5 Structure of up down register 8 24 7721 Group User s Manual TIMER A 8 4 Event counter mode 8 4 4 Selectable functions The following describes the selectable pulse output and two phase pulse signal processing functions 1 Pulse output function The pulse output function is selected by setting the pulse output function select bit bit 2 at addresses 5816 to to 1 When this function is selected the TAjour pin is forcibly set for the pulse output pin regardless of the corresponding bit of the port P5 direction register The TAjour pin outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs Refer to Figure 8 3 6 When the count start bit address 4016 is 0 count stopped the
24. BEQ Note 3 Branches when ents he Z flag is BMI Note 3 Branches when ents he N flag is BNE Note 3 Branches when ents he 2 flag is BPL Note 3 N 0 Branches when ents he flag is 0 BRA Note 4 PC lt PC offset PGc PG 1 when carry occurs PG c PG 1 when borrow occurs Jumps to the address indicated by the program counter plus the offset value 2 5 S lt S 1 5 S lt S 1 M S e PC S lt S 1 M S lt PSH S lt S 1 M S lt PSt Sc 8 1 1 1 PG lt 0016 Executes software interruption BVC Note 3 V 0 Branches when the contents of the V flag is 0 BVS Note 3 V 1 Branches when the contents of the V flag is 1 CLB Note 5 Mbc 0 Makes the contents of the specified bit in the memory 0 lt 0 Makes the contents of the flag 0 1 0 Makes the contents of the flag 0 0 Makes the contents of the flag 0 Specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction and sets 0 in that bit Makes the contents of the V flag 0 CMP Notes 1 2 17 42 Compares the contents of the accumulator with the con tents of the memory 7721 Group User s Manual
25. The microcomputer executes a program beginning with the address set into the reset vector addresses FFFEis and FFFFie 4 2 7721 Group User s Manual RESET 4 1 Hardware reset 4 1 1 Pin state Table 4 1 1 lists the microcomputer s pin state while RESET pin is at L level Figure 4 1 2 shows the RESETour output retaining timing Table 4 1 1 Pin state while RESET pin is at L level Pin Bus Port name Pin state Ao MAo Az MA 8 15 0 15 Ate Do Azs D7 BLE Outputs H or L level R W E STO ST1 Outputs H level ALE RESETour Outputs L level Outputs HOLD RDY P4s P4 5 10 Floating When RESET pin input level goes from L to in this period eee Le RESET 3 5 cycles of RESETour Fig 4 1 2 RESETour output retaining timing 7721 Group User s Manual 4 3 RESET 4 1 Hardware reset 4 1 2 State of CPU SFR area and internal RAM area Figure 4 1 3 shows the state of the CPU registers immediately after reset Figures 4 1 4 to 4 1 9 show the state of the SFR and internal RAM areas immediately after reset 0 0 immediately after reset 0 Always 0 at reading 1 1 immediately after reset Undefined immediately after reset Register name State immediately after reset 68 67 Accumulator A Accumulato
26. D2 D1 VARTI receive buffer register RxDi UARTi receive register UART BRO count source 1 16 Receive Transfer clock select bits Clock control circuit o Sino 1 fie 9 UART fe4 o 4 116 Transmit control Transfer clock 1512 o Clock _ itcult 7 synchronous Sow Clock synchronous m internal clock selected UARTi transmit register o 1d Clock synchronous Clock synchronous internal clock selected external clock selected UARTi transmit CLKi Q 4 buffer register CTSi RTSi Data bus odd n Values set in UARTi baud rate register BRGi Data bus even Fig 11 2 1 Block diagram of Serial I O 7721 Group User s Manual 11 3 SERIAL I O 11 2 Block description 11 2 1 UARTi transmit receive mode register Figure 11 2 2 shows the structure of transmit receive mode register The serial mode select bits are used to select UARTi s operating mode Bits 4 to 6 are described in section 11 4 2 Transfer data format and bit 7 is done in section 11 4 8 Sleep mode 67 06 b5 b4 63 b2 bi 60 UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 eem Serial I O mode select bits 00 05 Serial l O disabled RW P8 functions as a programmable port Clock synchronous serial I O
27. 4 al Data Address Register DA 24 Arithmetic Logic Data Buffer DBH 8 Data Buffer DBL 8 Instruction Queue Buffer Qo 8 Instruction Queue Buffer Q1 8 Instruction Queue Buffer Q2 8 Incrementer 24 Program Address Register PA 24 Incrementer Decrementer 24 Program Counter PC 16 Program Bank Register PG Data Bank Register DT 8 Input Buffer Register IB 16 Processor Status Register PS 11 Direct Page Register DPR 16 Stack Pointer S 16 Index Register Y 16 Index Register X 16 Accumulator B 16 Accumulator A 16 Unit 16 eH EH ds ya C C 8 uononuisu For the M37721S1BFP the RAM size is 512 bytes nong rm ws 016 FW 438A SSANO SSA 99A 10014648 19999 nox NIX yndyno n ndu uonogjas A0 indino indui ine io ijndinoxoo o indui snes indino sng Blep ejqeu3 1 200 Aowa Note
28. Jo 19JsueJ 1 lt A LEBEL enia euo Ag si pun p 16 991 0 ejejs eu Jajsues pue ui 20 4 Buisseooud 101 uuo e OLS LLS l 5 sng L eey 0q 97 si q sry sq sv AN 0V Wu steal transfer mode 1 f cycle iagram o ing d im 10 Ti 8 13 19 7721 Group User s Manual 13 92 DMA CONTROLLER 13 8 Link array chain transfer mode ejejs Aese ue ui pejdeooe jou sjeuueuo 1 Jo sjsenbe WING 941 si pue snq esn zy eui JO UOI ISUBL UI SI 1 5 sanba eui aym si Aq pesneo jsenbei sng 99 e s pue 1 si euDis sanba snq eui aym s 10 useJjaJ Aq pesneo 15 sng 991 e 2 10 BY JOU s s 1 ureuo eui 6961 Ul 151 Buisseooud 10 Wd erui jo eui si e oqe 99 e snq esn jo uonisuej i Jejsue PUN 1914 4 ejejs Aey SJejeueJed JeJsueJ JO JaJSUeI 015 115 21 IMOVVIAG 1senba sng LQ
29. 21 pin Input mode pin Output mode D F F initialized pin Input mode b7 50 0 Port P9 direction register Address 1516 pin Input mode b7 bo 0 0 1 0 1 DMAO mode register L Address 1FCC 6 Transfer unit 8 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction Fixed Transfer destination address direction Forward b7 50 x 10 0 0 0 0 0 0 DMAO mode register Address 1FCD16 Transfer source Wait Transfer destination Wait Single transfer mode X It may be 0 or 1 Fig 16 2 3 Initial setting example for relevant register 1 7721 Group User s Manual 16 45 APPLICATION 16 2 Examples of using DMA controller 023 016015 b8b7 050 Source address register 0 Addresses 1FC216 to 1 016 latch s address 023 016015 b8b7 050 Destination address register 0 Addresses 1FC616 to 1FC416 Data buffer s start address b23 016015 b8b7 050 Transfer counter register 0 Addresses 1FCAt6 1FC816 L pata buffer size unit byte b7 bO 0 1 1 1 1 0 Timer 2 mode register Address 5816 one shot pulse mode Trigger Rising edge of TA2IN pin s input signal Count source b7 1 0 11 1 1 1 0 Timer mode register Address 5916 50 11111 pulse mode Trigger Rising edge of pin
30. ALE output delay time 4 Hs tw ALe ALE pulse width Note 22 ns taBHE E BHE output delay time Note 20 ns taeLe BLE output delay time Note 20 ns lemw amp _ R W output delay time Note 20 nS h E AL Address low order hold time Note 18 ns thale am Address middle order hold time BYTE L 9 ns Data high order hold time BYTE L Note 18 ns 2 Data high order floating release delay time BYTE L Note 20 ns Address middle order hold time BYTE Note 18 ns Address high order hold time 9 ns tE oo Data low order hold time Note 18 HS lpxE oz Data low order floating release delay time Note 20 ns tne sHe BHE hold time Note 18 ns tnE 8LE BLE hold time Note 18 83 tne rw R W hold time Note 18 ns pulse width Note 55 ns ta data Copy delay time 50 t e ro TC output delay time 20 5 nS TC output pulse width Note 50 ns tsutcm input setup time 60 ns twrcom TC input pulse width 80 Hs Note Figures 13 and 14 show the test circuits 7721 Group User s Manual 17 97 APPENDIX Appendix 11 Electrical characteristics 17 98 At DMA transfer Burst transfer timing External source 1 DMAREQi STO DMAACKi output As Ds A15 D15 output BYTE L As Ds A15 D15 output BYTE A16 Do A23 D7 output ALE o
31. request is generated at the following timings it is not in time to the next bus request sampling Therefore DMAC returns the right to use bus to the CPU Then DMAC regains the right and restarts the DMA transfer Except for the last 1 unit transfer 1 bus cycle transfer is selected without Wait Except for the last 1 unit transfer 1 bus cycle transfer is selected with Wait In addition a time of 0 5 cycle of is less than tsu DRQ Fig 13 4 12 Conditions for performing DMA transfers of the same channel continuously 13 52 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 2 When a DMA transfer of another channel is subsequently performed In the cycle steal transfer mode it takes 1 5 cycles of from the generation of a DMA request until that of a BUS REQUEST DMAC Therefore if a DMA request of another channel is generated during a DMAi transfer in the cycle steal mode either one of the following two cases occurs depending on its timing of request generation The DMAC performs the DMA transfer subsequently without returning the right to use bus After returning the right to use bus to the CPU once the DMAC regains the right and performs the DMA transfer 1 unit transfer Bus request sampling gt DMA transfer is subsequently performed if After returning the right to use bus to request bit of another channel becomes 1 during once DMAC regains the right
32. 1 data is present in the UARTi receive buffer register and next data is transferred to the UARTi receive buffer register in other words when the next data is prepared before reading out the contents of the UARTi receive buffer register When an overrun error occurs the next receive data is written into the UARTi receive buffer register and the UARTi receive interrupt request bit is not changed An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register and the overrun error flag is set to 1 The overrun error flag is cleared to 0 by clearing the serial I O mode select bits to 0002 or clearing the receive enable bit to 0 When an overrun error occurs during reception initialize the overrun error flag and the UARTi receive buffer register before performing reception again When it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side set the UARTi transmit buffer register again before starting transmission again The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below 1 Method of initializing UARTi receive buffer register Clear the receive enable bit to 0 Reception disabled Q Set the receive enable bit to 1 again Reception enabled 2 Method of setting UARTi transmit buffer register again Clear the serial
33. Transmit data which has 1 in bit 7 and the address of the slave microcomputer to be communicated in bits O to 6 from the master microcomputer to all slave microcomputers All slave microcomputers receive data of step At this time a UARTi receive interrupt request occurs For all slave microcomputers check in the interrupt routine whether bits 0 to 6 in the receive data match their own addresses For the slave microcomputer of which address matches bits 0 to 6 in the receive data terminate the sleep mode Do not terminate the sleep mode for the other slave microcomputers By performing steps to the microcomputer which performs transfer is specified Transmit data which has 0 in bit 7 from the master microcomputer Only the microcomputer specified in steps to can receive this data The other microcomputers do not receive this data By repeating step transfer can be performed between two specific microcomputers continuously When communicating with another microcomputer perform steps to in order to specify the new slave microcomputer Data is transferred between the master Master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers Fig 11 4 13 Sleep mode 7721 Group User s Manual 11 47 SERIAL I O 11 4 Clock asynchronous serial I O UART mode MEMORANDUM 11 48 7721 Group User s Manual CHAPTER 12 A D CON
34. 1 Register operation in 1 bus cycle transfer Figure 13 4 6 shows a basic operation of registers for 1 unit transfer in 1 bus cycle transfer For register values to be specified refer to section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode It is because these values vary depending on each continuous transfer mode In 1 bus cycle transfer a read and write of 1 transfer unit data are simultaneously performed during 1 bus cycle When transferring from memory to I O DMAC Transfer source address is specified by SARi SARi Note SARi latch Contents of TCRi are updated by decrementer Transfer Note when value read from TCRi is 0 transfer DAR source of 1 data block is terminated DARI latch Contents of SARi are updated by incrementer decrementer I O is specified by DMAACKi Q TCRi Data is output from memory and is written to I O TCRi latch simultaneously R W H level DMA latch destination When transferring from I O to memory DMAC Transfer source address is specified by DARi Note Contents of TCRi are updated by decrementer Note SARi latch when value read from TCRi is 0 transfer of 1 data Incrementer i i Transfer block is terminated destination Contents of DARi are updated by incrementer DARi latch decrementer I O is specified by DMAACKi Data is output from I O and is writte
35. 2 Event counter mode Timers BO and B1 The timer counts an external signal 3 Pulse period Pulse width measurement mode Timers BO and B1 The timer measures an external signal s pulse period or pulse width In this chapter Timer Bi i 0 to 2 indicates Timers BO to B2 Timer Bj j 0 1 indicates Timers BO and B1 this is used when the timer B s input output pins are used etc Hereafter input output pins are called I O pins 9 2 Block description Figure 9 2 1 shows the block diagram of Timer B Explanation of registers relevant to Timer B is described below Count source select bits Data bus odd Data bus even 512 Low order 8 bits High order 8 bits Timer mode Pulse period Pulse width measurement mode Timer Bi reload register 16 Polarity switching Event counter Timer Bi and edge pulse mode Timer Bi counter 16 generating circuit 4 Count start bit Timer Bj flag Valid in pulse period pulse width measurement mode Counter reset circuit i 0 2 j 0 1 Fig 9 2 1 Block diagram of Timer B 9 2 7721 Group User s Manual TIMER B 9 2 Block description 9 2 1 Counter and reload register timer Bi register Each of timer Bi counter and reload register consists of 16 bits and has the following functions 1 2 Functions in timer mode and event counter mode Countdown in the counter is performed each time the count source is input The reload register i
36. Fig 1 4 1 M37721 block diagram 1 7 7721 Group User s Manual DESCRIPTION 1 4 Block diagram MEMORANDUM 1 8 7721 Group User s Manual CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 2 Bus interface unit 2 3 Access space 2 4 Memory assignment 2 5 Bus access right CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 Central processing unit The CPU Central Processing Unit has the ten registers as shown in Figure 2 1 1 Accumulator A A Accumulator B B Index register X X Index register Y Y Stack pointer S Data bank register DT b16 615 Program counter PC Program bank register PG Direct page register DPR Processor status register PS b10 b8 67 b6 65 64 b3 b2 bi Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level Fig 2 1 1 CPU registers structure 2 2 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 1 Accumulator Acc Accumulators A and B are available 1 Accumulator A A Accumulator A is the main register of the microcomputer The transaction of data such as calculation data transfer and input output are performed mainly through accumulator A It consists of 16 bits and the low order 8 bits can also be used
37. Set the transfer start address of transfer source These bits can be set to 00000016 to FFFFFF i e DIS pm po Destination address register 0 Addresses 1FC6 e to 1FC41e DARO C I Destination address register 1 Addresses 1FD616 to 1FD416 DAR1 Destination address register 2 Addresses 1 16 to 1FE416 DAR2 Destination address register Addresses 1FF616 to 1FF416 DAR3 NEN 623 b16 b15 68 b7 5007 5057 50 Transfer counter register 0 Addresses 1FCAte to 1 816 TCRO Transfer counter register 1 Addresses 1FDA16 to 1FD816 TCR1 Transfer counter register 2 Addresses 1 16 to 1 816 TCR2 Transfer counter register 3 Addresses 1FFAte to 1FF816 TCR3 Set the byte number of transfer data These bits can be set to 00000116 to FFFFFF e Set the transfer start address of destination These bits can be set to 00000016 to FFFFFF e Note 3 When data is transferred from memory to I O in 1 bus cycle transfer it is unnecessary to set DARi When data is transferred form I O to memory in 1 bus cycle transfer it is unnecessary to set SARI Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi Fig 13 6 3 Initial setting example for registers relevant to repeat transfer mode 2 13 64 7721 Group User s Manual DMA CONTROLLER 13 6 Repeat transfer mode
38. e empty flag q UARTi transmit register lt transmit buffer register Stopped because CTSi H Stopped because transmit enable bit 0 999886 CIS 6 3219 38998 br Transmit register empty flag UARTi transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies when the following conditions are satisfied Next transmit conditions are examined when this signal level is Internal clock selected Tenni is an internal signal Accordingly it cannot be read from the external CTS function selected Tc 2 n 1 1 fi BRGi count source frequency f2 116 164 1512 n Value set in BRGi Fig 11 3 5 Example of transmit timing when selecting internal clock selecting CTS function Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register Transmit buffer D empty flag gt UARTi transmit register UARTI transmit buffer register TCLK Stopped because transmit enable bit 0 TENDi NOE Transmit register j empty flag UARTi transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies when the following
39. receive buffer register is read out i e an overrun error occurs The UARTi receive buffer register is initialized by setting the receive enable bit bit 2 at addresses 3516 3016 to 1 after clearing it to 0 Figure 11 2 9 shows the contents of the UARTi receive buffer register when reception is completed High order byte Low order byte addresses 3716 3F16 addresses 3616 3E16 b7 bO 1 b7 b0 rransterdataienatn obits Receive data 9 bits In clock synchronous i serial I O mode In UART mode Transfer data length 8 bits Same value as bit 7 low order byte h 7 bits Same value as bit 6 in low order byte Receive data 7 bits Receive data 8 bits Fig 11 2 9 Contents of UARTi receive buffer register when reception is completed 11 12 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 6 UARTi baud rate register BRGi The UARTi baud rate register BRGi is 8 bit timer exclusively used for UARTi to generate a transfer clock It has a reload register Assuming that the value set in the BRGi is n 0016 to FFie the BRGi divides the count source frequency by n 1 In the clock synchronous serial I O mode the BRGi is valid when an internal clock is selected and the BRGi s output divided by 2 becomes the transfer clock In the UART mode the BRGi is always valid and
40. 1 aa q 1 block Fig 13 9 6 Array chain transfer mode and Link array chain transfer mode Transition of the right to use bus from CPU to DMAC 1 cycle Array state The number of transfer parameters x the number of reads of a transfer parameterx the number of bus cycles for a read 1 cycle Refer to Table 13 9 1 DMA transfer per an entire batch of data e In 2 bus cycle transfer Read cycle Write cycle x the number of transfers 3 amp 1 Add a value which satisfies the read write conditions Refer to Table 13 4 1 2 When the transfer unit is 16 bits the number of transfers the number of transfer bytes 2 When the transfer unit is 8 bits the number of transfers the number of transfer bytes In 1 bus cycle transfer Refer to Table 13 4 5 Last processing of each block cycles Terminate processing 3 cycles Transition of the right to use bus from DMAC to CPU 1 cycle Example Array chain transfer mode external data bus width 16 bits 2 bus cycle transfer transfer unit 16 bits the number of transfer blocks 3 and under the following conditions Transfer source address direction forward without Wait Transfer destination address direction backward without Wait First block transfer source s data start address even transfer destination s data start address even the number of transfer bytes 10 bytes Second block transfer source s da
41. 11 4 Clock asynchronous serial I O UART mode Table 11 4 1 lists the performance overview in the UART mode and Table 11 4 2 lists the functions of pins in this mode Table 11 4 1 Performance overview in UART mode Item Functions Transfer data Start bit 1 bit format Character bit Transfer data 7 bits 8 bits or 9 bits Parity bit bit or 1 bit Odd or even can be selected Stop bit 1 bit or 2 bits Transfer rate When selecting internal clock BRGi s output divided by 16 When selecting external clock Maximum 312 5 kbps 4 types Overrun Framing Parity and Summing Presence of error can be detected only by checking error sum flag Error detection Table 11 4 2 Functions of I O pins in UART mode Pin name TxDi P83 P87 Note 1 Serial data output Method of selection Cannot be used as a programmable I O port even when performing only reception RxDi P82 86 Serial data input Port P8 direction register s corresponding bit 0 be used as a programmable I O port when performing only transmission P81 85 Programmable I O port Internal External clock select 0 BRGi s count source input Internal External clock select bit 1 CTS RTSi P80 P84 CTS input CTS RTS function select bit 0 Note 2 RTS output CTS RTS function select bit 1 Port P8 direction register address 1416 Internal External clock select
42. 14 2 5 Address multiplexer Address data is time shared by the control signal from the address comparator and is output to the MAo pins The time sharing method depends on the external bus width Table 14 2 2 lists the time sharing method for the address at DRAM access When the 8 bit external bus width is selected Ao A19 are time shared are output when the 16 bit external bus width is selected Ai Azo are time shared and are output Table 14 2 2 Time sharing method for address at DRAM access Pin name Ao MAo A1 MA As MAs Ae MAs P10e MAs P107 MAs S 8 bit external Row address Ao Ai Aa As Ais 2 bus width Column address As A12 Ais Ais 9 2 16 bit externallRow address Ais Ai gt Aa As Az Ais Azo bus width Column address A12 Ais A14 Ais Aig 14 6 7721 Group User s Manual DRAM CONTROLLER 14 3 Setting for DRAMC 14 3 Setting for DRAMC Figure 14 3 1 shows an initial setting example for registers relevant to DRAMC Division ratio setting for refresh timer b7 50 Refresh timer Address 6616 EP Can be set to 0016 to FF1e n Refresh timer divides fie by n 1 DRAM area setting and DRAM validity selection DRAM control register Address 64 6 DRAM area select bits b3b2b1 b0
43. 20 min tOEA 20 max tAA 35 max tpzx E DLZ DHZ 20 min lt gt tRAC 70 max gt Input data tCLZ 5 min tsu DL DH E 2 30 ipgz 0 20 AC157 tPHL ll e 1 20 max AC157 tPHL lt When writing gt tw RASH 60 min tw EL 135 min tw RASL 120 min td E CASL 80 115 gt td R W E 20 min e tw CASL 55 min AC32 tPHL RENI AC32 tPHL twcs 0 min gt lt tWCH 15 min 5 min td RA RAS th RAS RA 18 min Column address Row Address gt 60 min lt gt lt td CA CAS 10 min th CAS CA 16 00 23 07 r gt 20 min tDH 15 min lt gt AC157 tPHL th E DLQ DHQ 18 min td BLE BHE E BLE BHE Specifications of M5M44260CJ 7 The others are specification of M37721 Unit ns Fig 16 1 35 Timing chart for example of M5M44260CJ 256K X 16 bits connection external bus width 16 bits 7721 Group User s Manual 16 39 APPLICATION 16 1 Memory connection 16 1 4 Example of I O expansion 1 16 40 Example of port expansion circuit using 66010 Figure 16 1 36 shows an example of a port expansion circuit using the M66010FP Make sure that the frequency of Seria
44. 67 06 b5 04 63 02 bi 0 Count start register Address 4016 Em Timer AO count start bit 0 Stop counting 1 Start counting Timer A1 count start bit Timer A2 count start bit Ce Pierer coursa Timer B2 count start bit One shot start register 67 06 05 b4 b3 62 bi lolol One shot start register Address 4216 Fix these bits to 0 The value is 0 at reading Ea Timer A2 one shot start bit 1 Start outputting one shot pulse valid when internal trigger is EZ Timer one shot start bit selected The value is 0 at reading Timer 4 one shot start bit Nothing is assigned ees 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 16 7721 Group User s Manual APPENDIX Appendix 3 Control registers Up down register 67 66 65 64 63 b2 61 00 folol Up down register Address 4416 Fix these bits to 0 Rw o aw Timer A2 up down bit 0 Countdown o RW 1 Countup Timer A3 up down bit This function is valid when the contents of o nw RW the up down register is selected as the up Timer A4 up down bit down switching factor o RW 5 A2 two phase pulse signal 0 Two phase pulse signal WO processing select bit processing function disabled 1 Two phase pulse signal Timer A3 two phase pulse signal processing function enabled rocessing select bit Note 9
45. 7721 Group User s Manual 11 13 SERIAL I O 11 2 Block description 11 2 7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi 2 types of interrupts which UARTi transmit and UARTi receive interrupts can be used Each interrupt has its corresponding interrupt control register Figure 11 2 12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers For details about interrupts refer to CHAPTER 7 INTERRUPTS 57 56 65 04 53 62 bi 00 UARTO transmit interrupt control register Address 7116 UARTO receive interrupt control register Address 7216 UART1 transmit interrupt control register Address 73 6 UART1 receive interrupt control register Address 7416 Interrupt priority level select bits Level 0 Interrupt disabled RW Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 RW Level 6 Level 7 High level Interrupt request bit 2 No interrupt requested Interrupt requested 704 to 4 7104 Nothing is assigned Fig 11 2 12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers 1 Interrupt priority level select bits bits 0 to 2 These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt When using UARTi transmit receive interrupts select one of the priority levels 1 to 7 When a UARTi tra
46. A pins function as address output pins Refresh timer stops counting 1 Valid P104 P107 pins function as CAS RAS MAs and function as MAo MAr Refresh timer starts counting ES Note Set the refresh timer address 6616 before setting this bit to 1 Refresh timer b7 50 21 Refresh timer Address 6616 7 to 0 These bits can be set to 0116 to FF e Undefined WO Assuming that the set value n this register divides fis by 1 Note Use the LDM or STA instruction for writing to this register Do not set this register to 0016 17 30 7721 Group User s Manual APPENDIX Appendix 3 Control registers DMAC control register L 67 b6 65 64 b3 02 bli 50 ll 1 DMAC conirol register L Address 6816 Bi pibhame Puneions pare Fixed l Ed EN Rotating ELI TC pin validity bit Invalid P103 pin functions as a programmable port CMOS 1 Valid m P103 pin functions as TC pin N channel open drain ae D rese aw ses KACI Notes 1 The state of bits 4 to 7 are not changed when writing 1 to these bits 2 When writing to this register while any of enable bits bits 4 to 7 at address 6916 is 1 set m flag to 1 and use the LDM or STA instruction When DMAi request bit bits 4 to 7 at address 6816 must not be changed set request bit to 1 When writing to
47. CHAPTER 11 SERIAL 1 0 11 1 Overview 11 2 Block description 11 3 Clock synchronous serial I O mode Precautions for clock synchronous serial mode 11 4 Clock asynchronous serial I O UART mode SERIAL I O 11 1 Overview 11 1 Overview Serial I O consists of 2 channels UARTO and UART1 They each have a transfer clock generating timer for the exclusive use of them and can operate independently UARTO and UART1 have the same functions UARTIi i 0 and 1 has the following 2 operating modes 1 Clock synchronous serial I O mode Transmitter and receiver use the same clock as the transfer clock Transfer data has a length of 8 bits 2 Clock asynchronous serial I O UART mode Transfer rate and transfer data format can arbitrarily be set The user can select a transfer data length of 7 bits 8 bits or 9 bits Figure 11 1 1 shows the transfer data formats in each operating mode Ge Clock synchronous serial I O mode Transfer data length of 8 bits UART mode Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig 11 1 1 Transfer data formats in each operating mode 11 2 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 Block description Figure 11 2 1 shows the block diagram of Serial I O Registers relevant to Serial I O are described below Data bus odd Data bus even D7 05
48. CMP CMP CMP B DIR B IMM B ABS CMP CMP CMP B DIR X 5 5 SBC SBC SBC B DIR B IMM B ABS SBC SBC SBC B DIR X 5 5 7721 Group User s Manual 17 57 APPENDIX Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 3 The first word s code of each instruction is 8916 Da Do 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Hexadecimal D7 D4 notaio 9 1 2 3 4 5 6 7 8 9 A B D E F MPY MPY MPY MPY MPY MPY MPY 0000 0 DIR X SR DIR L DIR IMM ABS ABL MPY MPY MPY MPY MPY MPY MPY MPY 0001 1 DIR Y DIR SR Y DIR X L DIR Y ABS Y 5 ABL X DIV DIV DIV DIV DIV DIV DIV 0010 2 XAB DIR X SR DIR L DIR IMM ABS ABL DIV DIV DIV DIV DIV DIV DIV DIV 0011 3 DIR Y DIR SR Y DIR X L DIR Y ABS Y ABS X ABL X RLA 0100 4 IMM 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B LDT 1100 1101 D 1110 E 1111 F 17 58 7721 Group User s Manual APPENDIX Appendix 8 Countermeasure against noise Appendix 8 Countermeasure against noise General countermeasure examples against noise are described below Although the effect of these countermeasure depends on each system refer to the following when an noise related problem occurs 1
49. Column address A16 Do Az3 D7 As Ds A15 D15 Read cycle 1 bus cycle lt b At writing ee E RAS CAS RW npe Write cycle 1 bus cycle c At refresh R W Undefined MAo MAo Undefined mop qe me Tires A16 Do Az3 D7 Floating palo AD Undefined Transition of right to use bus Refresh cycle Transition of right to use bus lt gt lt gt lt gt Fig 14 4 1 Waveform example of DRAM control signals 7721 Group User s Manual 14 9 DRAM CONTROLLER 14 4 DRAMC operation 14 4 2 Refresh request When the DRAM validity bit is set to 1 the refresh timer starts counting down The count source is fie When the contents of the refresh timer reach 00146 a refresh request occurs The refresh timer reloads the contents of address 6616 and continues counting Refresh requests are sampled as bus requests DRAMC by using the bus access controller As soon as a refresh request is acknowledged by sampling the following is performed because DRAM refresh has the highest priority in using the bus However when the CPU or DMAC uses the bus no bus request is sampled until the CPU or DMAC releases the bus Therefore in a period from when a refresh request occurs until DRAM refresh is performed the delay listed in Table 14 4 1 occurs depending on the refresh request generating timing Figures 14 4 2 and 1
50. DMAi mode register L Address 1FCCie Address 1FDCie Address 1FECte Address 1FFCie DMAO mode register L 67 b6 b5 64 63 62 61 BEENBENEER 5 1 DMA3 mode eae Biname of unit transfer bits 16 bits select bit Note 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer 2 Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode Fix this bit to 0 Transfer source address b5b4 EN direction select bits 00 Fixed 01 Forward 10 Backward 1 1 Do not select inati b7b6 rite Oh E hee ate iat Transfer destination address 0 0 Fixed 0 1 Forward oh eee Sad edhe on 10 Backward 1 1 Do not select direction select bits Note When the external data bus has a width of 8 bits and 1 bus cycle transfer is selected set bit to 1 DMAi mode register H DMAO mode register H 67 b6 b5 b4 63 b2 bi PL LL Lolo D buasmece iste h DMAS3 mode register Address 1FCDie Address 1FDD e Address 1FEDt 6 Address 1FFD e PN D os Bit Bit name Functions Funcions Atreset RW Transfer direction select bit From memory to 1 0 RW Used in 1 bus cycle transfer 1 From to memory I O connection select bit Refer to Fig 13 2 7 RW Valid in 1 bus cycle transfer Fix these bits to 0 o aw Transfer source wa
51. Figure 12 2 1 shows the block diagram of the A D converter Registers relevant to the A D converter are described below a AD ladder network Resistor Successive approximation A D sweep pin select register register A D control register A D register 0 A D register 1 A D register 2 A D register 3 A D register 4 A D register 5 Decoder A D register 6 A D register 7 Data bus even ANo AN ANs 6 Selector Fig 12 2 1 Block diagram of A D converter 7721 Group User s Manual Comparator 12 3 A D CONVERTER 12 2 Block description 12 2 1 A D control register Figure 12 2 2 shows the structure of the A D control register The A D operation mode select bit selects the operation mode of the A D converter The other bits are described below 67 06 65 64 63 62 bi A D control register Address 116 Analog input select bits Valid in one shot and repeat ANo selected Undefined modes Note 1 AN1 selected ANe selected ANs selected AN4 selected ANs selected ANe selected AN7 selected Note 2 A D operation m
52. Figures 11 3 5 and 11 3 6 for the change of flag state and the occurrence timing of an interrupt request When using interrupts A UAHTi transmit interrupt request occurs when the transmission starts UARTi transmit interrupt Note This figure shows the bits and registers required for processing Refer to Figures 11 3 5 and 11 3 6 for the change of flag state and the occurrence timing of an interrupt request 11 20 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 3 Transmit operation When the transmit conditions described in section 11 3 2 Method of transmission are satisfied in the case of selecting an internal clock a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed When the transmit conditions are satisfied and the external clock is input to the CLKi pin in the case of selecting an external clock the following operations are automatically performed transmit buffer register s contents are transferred to the UARTi transmit register The transmit buffer empty flag is set to 1 The transmit register empty flag is cleared to 0 8 transfer clocks are generated when an internal clock is selected UARTi transmit interrupt request occurs and the interrupt request bit is set to 1 The transmit operations are described below Data in
53. INdjno jeuueuo N s SUOd pepuedxe si veld k uod pepuedx3 01 pod pepuedx3 veia X X ji X X sia X Y sia via X Y enas Ul si 1 5 jus geq uod pepuedx3 tzoa ez0a Xzzoa X zoa X soa X zoa X X soa X X toa sod pepuedxe 01 indjno s z 1e1siDoJ 6 eq e N 2 JeisiDoJ y ys 0 1ndui s 2 jenas 49181681 45 INdjno s suod pepuedxe geq ejeis peseoja4 suod Fig 16 1 37 Serial transfer timing between M37721 and M66010FP 7721 Group User s Manual 16 42 APPLICATION 16 2 Examples of using DMA controller 16 2 Examples of using DMA controller 16 2 1 Example of Centronics interface configuration The following is an example of Centronics interface configurated by using DMAO Timers 2 and 1 Specifications Octal latch s contents are transferred to the data buffer RAM by using DMAO The trigger is the STB signal Refer to Figure 16 2 1 L level width of the ACK signal is generated by using Timer 2 one shot pulse mode the trigger is the rising edge
54. When not using the two phase pulse 7 Timer A4 two phase pulse signal 2 processing function set the bit WO processing select bit Note The value is 0 at reading Note Use the LDM or STA instruction for writing to bits 5 to 7 7721 Group User s Manual 17 17 APPENDIX Appendix 3 Control registers Timer Ai register b15 b8 Timer AO register Addresses 4716 4616 b7 57 bO A1 register Addresses 4916 4816 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F 16 4 16 15 to 0 These bits have different functions according unaetinea RW to the operating mode Note 1 Notes 1 The access characteristics for the timer A2 register timer A3 register and timer A4 register differ according to Timer A s operating mode 2 Read from or write to this register in a unit of 16 bits Timer Ai mode register 67 b6 65 64 b3 62 bi bO Timer Ai mode register i 0 to 4 Addresses 5616 to 5A 6 ep Operating mode select bits b1 bo 00 Timer mode 0 1 Event counter mode 1 0 One shot pulse mode 1 1 Pulse width modulation PWM mode 17 18 7721 Group User s Manual APPENDIX Appendix 3 Control registers Timer Mode b15 b8 Timer AO register Addresses 4716 4616 b7 bO 57 bO Timer A1 register Addresses 4916 4816 Timer register Addresses 4016 4 16 Timer 4 register Addresses 4F 16 4 16
55. When selecting the two phase pulse signal processing function set the bit corresponding to the TAjour pin to 0 P Setting the count start bit to 1 b7 60 Count start register Address 4016 Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count starts Fig 8 4 3 Initial setting example for registers relevant to event counter mode 2 8 22 7721 Group User s Manual TIMER A 8 4 Event counter mode 8 4 2 Operation in event counter mode When the count start bit is set to 1 the counter starts counting of the count source s valid edges When a counter underflow or overflow occurs the reload register s contents are reloaded and counting continues The timer Aj interrupt request bit is set to 1 at the underflow or overflow in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 8 4 4 shows an example of operation in the event counter mode n Reload register s contents Starts counting Counter contents Hex Set to 1 by software Count start bit et to 1 by software Up down bit EE Timer Aj interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Note The above applies when the up down bit s contents are selected as the up down switc
56. and 6 CPU stops at L level Q The L level which is input to the RDY pin is not accepted however 0 stops at L level L level which is input to the RDY pin is accepted so that E stops at L level for 1 cycle of clock 1 indicated by 38828 and CPU stops at L level Bus not in use Bus in use Ready state is terminated The L level which is input to the RDY pin is not accepted because it is sampled immediately before Wait by software Wait indicated by GY however CPU stops at L level Wait RDY pin input level sampling timing 4 Clock 1 Fig 3 3 1 Timing of acceptance of Ready request and termination of Ready state 7721 Group User s Manual 3 11 CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function 3 4 Hold function When composing the external circuit which accesses the bus without using the central processing unit CPU Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit The microcomputer enters Hold state by input of L level to the HOLD pin and retains this state while the level of the HOLD pin is at L Table 3 4 1 lists the microcomputer s state in Hold state In Hold state the oscillation of the oscillator does not stop Accordingly the internal peripheral devices can operat
57. external memory Note Make sure that d 2 0 is satisfied when generating the external memory read signal OE Fig 16 1 11 Example of making data output timing delayed When using external memory that outputs data for more than 2 2 after rising edge of E signal Because the external memory outputs data for more than tpz e ocziowz after the rising edge of the E signal there is a possibility that the tail of data collides with the head of address In such a case try to carry out the following Cut the tail of data output from the memory by using for example bus buffer Use the Mitsubishi s memory chips that can be connected without a bus buffer Figures 16 1 12 to 16 1 15 show examples of using bus buffers and the timing charts Table 16 1 6 lists the Mitsubishi s memory chips that can be connected without a bus buffer When using one of these memory chips timing parameters tor and listed below are guaranteed Accordingly no bus buffer is necessary for the system where the external memory s read signal OE goes high within tpz e o zinuz tor OF ns after the rising edge of the E signal Table 16 1 6 Mitsubishi s memory chips that can be connected without bus buffers Memory Type tor taisog Maximum Flash memory M5M28F101AP FP J VP RV 85 10 15 ns M5M28F102AFP J VP 85 10 Guaranteed as kit SRAM M5M5256DP FP KP VP RV 45LL 45XL 55LL 55XL
58. request bit changes synchronized with the falling edge of Table 13 3 3 lists the conditions for changing the DMAi request bit For the timing of changing the DMAi request bit refer to Figures 13 3 2 and 13 3 3 Table 13 3 3 Conditions for changing DMAi request bit request bit Burst transfer mode Cycle steal transfer mode Edge sense Level sense Is set to 1 Generation of request Generation of DMAi request Generation of DMAi request Note Refer to Table 13 3 2 L level input to the Refer to Table 13 3 2 DMAREQi pin Is cleared to 0 7 Normal termination e H level input to the Start of 1 unit transfer Change of the TC pin s input oua REGI Change of the TC pin s input level from H to L during Change of the TC pin s input level from H to L during DMA transfer when the TC level from H to L when DMA transfer when the TC pin is valid the TC pin is valid pin is valid write of 0 to the DMAi A write of 0 to the request bit request bit write of 0 to the A write of 0 to the enable bit enable bit Note While the DMAi enable bit is 0 the request bit is not set to 1 even if a DMA request is generated When the DMAi enable bit is cleared to 0 also the DMAi request bit is cleared to 0 However the DMA request generated while the DMAi enable bit 0 is
59. to 1 When this function is selected the TAjour pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 direction register The TAjour pin outputs pulses of which polarity is inverted each time a counter underflow occurs When the count start bit address 4046 is 0 count stopped the TAjour pin outputs L level Figure 8 3 6 shows an example of operation with the pulse output function selected n Reload register s contents Starts counting lt gt t Restarts 1 counting x n 2 o o 2 o Count start bit Pulse output from TAjour Timer Aj interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Fig 8 3 6 Example of operation selecting pulse output function 8 16 7721 Group User s Manual TIMER A 8 3 Timer mode Precautions for timer mode By reading the timer Ai register the counter value can be read out at any timing However if the timer Ai register is read at the reload timing shown in Figure 8 3 7 the value FFFF e is read out If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting the set value is correctly read out et ee Read value 2 1 FFFF n n Reload register s contents Time Fig 8 3 7 Reading timer Ai reg
60. 1 Specifications transfers the stepping motor s phase output data from the phase output data table to the RTPO pulse output data register Refer to Figure 16 2 6 and Table 16 2 1 DMA2 transfers the step time for slow up or slow down from the timer AO set value data table to the timer AO register Refer to Figure 16 2 6 After slow up or slow down is completed a DMA2 interrupt occurs Phase output is performed by RTPO pulse output mode 0 Refer to Figures 16 2 6 and 16 2 7 After slow up or slow down is completed the motor operates with the definite rate M37721 Phase output data table Motor driver N Stepping motor Timer AO set value data table Fig 16 2 6 Example of stepping motor control 16 48 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller Table 16 2 1 Example of phase output data table 2 2 phase 1 2 phase 0 0011 0011 1 1001 0001 2 1100 1001 3 0110 1000 4 0011 1100 5 1001 0100 6 1100 0110 7 0110 0010 Fig 16 2 7 Example of phase output 7721 Group User s Manual 16 49 APPLICATION 16 2 Examples of using DMA controller 2 Initial setting example for relevant register b7 50 jojo 1 0 1 mode register L Address 1FDC 6 Transfer unit 8 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction At regular tu
61. 15 to 0 The measurement result of pulse period or Undefined pulse width is read out Note Read from this register in a unit of 16 bits Fig 9 5 1 Structures of timer Bj mode register and timer Bj register in pulse period pulse width measurement mode 9 20 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 1 Setting for pulse period pulse width measurement mode Figure 9 5 2 shows an initial setting example for registers relevant to the pulse period pulse width measurement mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting pulse period pulse width measurement mode and each function b7 b0 lilo Timer Bj mode register i 0 1 Addresses 5816 5 16 L Selection of pulse period pulse width measurement mode Measurement mode select bits b3 b2 0 0 Pulse period measurement Interval between falling edges measurement pulse Pulse period measurement Interval between rising edges of measurement pulse 0 Pulse width measurement 1 Do not select 01 1 1 Timer Bj overflow flag Note 0 No overflow 1 Overflowed Count source select bits 242 1116 2164 Setting interrupt priority level b7 bo Timer Bj interrupt control register j 0 1 Ep Addresses 7 16 7816 Interrupt priority level se
62. 2 15 NN Tp gt 2 16 m 2 16 2 4 Memory assignmlentl x3 Econ 2 17 2 17 2 18 2 23 CHAPTER 3 m 3 2 nU 3 2 3 5 3 2 W i i sicesiccsecatussauecculesdasesessacnancdaunanveasvaaavenenceceuueusdcuuaaausactaanansessbwadunsetcausceuseccanedunace 3 8 n 3 10 3 11 E E ETE A E 3 12 3 12 3 16 Precautions for Hold function 7721 Group User s Manual Table of contents CHAPTER 4 ick aac a acta a tin sate cae 4 2 HM 4 3 4 4 Meer 4 11 Dou E S re 4 12 E MO EAE 4 13 5 2 NN 5 2 5 1 2 Externally generated clock input 5 2 a 5 3 5 2 1 Clocks generated in clock generating 22 5 4 AM MIN MEI M MEE CDU DE 5 5
63. 716 816 916 16 Port register 16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 Port P9 register 1416 Port P8 direction register 1516 Port P9 direction register 1616 Port P10 register 1716 1816 Port P10 direction register 1916 1A16 Pulse output data register 0 1816 1216 Pulse output data register 1 WO 1016 1 16 control register RW 1F16 0 sweep pin select register 2 2 2 2 Fig 4 1 4 State of SFR and internal RAM areas immediately after reset 1 7721 Group User s Manual 4 5 RESET 4 1 Hardware reset Address Register name 2016 A D register 0 2116 2216 A D register 1 2316 2416 A D register 2 2516 2616 A D register 3 2716 2816 A D register 4 2916 2A16 A D register 5 2 16 2C16 A D register 6 2D16 2E16 A D register 7 2 16 3016 UARTO transmit receive mode register 3116 UARTO baud rate register 3216 3316 3416 UARTO transmit receive control register 0 3516 UARTO transmit receive control register 1 3616 3716 3816 UART1 transmit receive mode register 3916 UART1 baud rate register 16 3816 3C16 UART1 transmit receive control register 0 3D16 UART1 transmit receive control register 1 3E16
64. 8 bit I O Fig 13 2 7 Structure of DMAi mode register H 7721 Group User s Manual 13 15 DMA CONTROLLER 13 2 Block description 13 2 12 control register Figure 13 2 8 shows the structure of the DMAi control register For bits 0 4 refer to section 13 3 2 1 DMA request sources 1 DMAACKi validity bit bit 5 When this bit is set to 1 the corresponding pin of port P9 serves as the DMAACKi pin and outputs L during a DMA transfer For details refer to each timing diagram of section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode DMAO control register Address 1 16 control register Address 1FDE16 control register Address 1 16 DMAS control register Address 1FFE e DMA request source select bits p3b2b1b0 RW Note 0000 Do not select 0001 External source DMAREQI 0010 Software DMA source 0011 Timer AO Timer A1 Timer 2 Timer A3 Timer A4 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UART1 receive UART1 transmit A D conversion 67 06 65 64 63 62 61 00 B44 gt Edge sense Level sense select 0 Edge sense Falling edge bit Used when external source 1 Level sense 4 level and burst transfer mode are selected Note DMAACKi validity bit 0 Invali
65. Figure 12 7 2 shows the conversion operation in the single sweep mode 7721 Group User s Manual A D CONVERTER 12 7 Single sweep mode Trigger occur Convert input voltage from Conversion result ANo pin eae A D register 0 Convert input voltage from Conversion result AN pin a A D register 1 Convert input voltage from Conversion result ERES A D register i A D converter interrupt request occur A D converter halt Fig 12 7 2 Conversion operation in single sweep mode 7721 Group User s Manual 12 23 A D CONVERTER 12 8 Repeat sweep mode 12 8 Repeat sweep mode In the repeat sweep mode the operation for the input voltages from the multiple selected analog input pins is performed repeatedly The A D converter is operated in ascending sequence from the ANo pin In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1 remains set to 1 until it is cleared to 0 by software and the operation is performed repeatedly while the A D conversion start bit is 1 12 8 1 Settings for repeat sweep mode Figure 12 8 1 shows an initial setting example for registers relevant to the repeat sweep mode 12 24 7721 Group User s Manual A D CONVERTER 12 8 Repeat sweep mode A D control register and A D sweep pin select register b7 60 1 1 A D control register address 1216 li A D sweep pin
66. One shot pulse mode Undefined value is read out Pulse width modulation PWM mode Notes 1 Also refer to Precautions for timer mode and Precautions for event counter mode 2 When reading from and writing to the timer Ai register perform it in a unit of 16 bits 8 4 7721 Group User s Manual TIMER A 8 2 Block description 8 2 2 Count start register This register is used to start and stop counting Each bit of this register corresponds to each timer Figure 8 2 2 shows the structure of the count start register 67 06 65 04 63 02 bi b0 Count start register Address 4016 Binane ___ ____ Timer AO count start bit Stop counting Pow Start counting Timer A1 count start bit Timer A2 count start bit Bits 5 to 7 not used for Timer Fig 8 2 2 Structure of count start register 7721 Group User s Manual 8 5 TIMER A 8 2 Block description 8 2 3 Timer Ai mode register Figure 8 2 3 shows the structure of the timer Ai mode register The operating mode select bits are used to select the operating mode of Timer Ai Bits 2 to 7 have different functions according to the operating mode These bits are described in the paragraph of each operating mode 67 06 05 04 63 62 61 00 Timer Ai mode register i 0 to 4 Addresses 5616 to 16 Operating mode select bits bibo 0 0 Timer mode 0 1 Event co
67. UARTi transmit interrupt i 0 1 When external clock is selected UARTi receive interrupt i 0 1 Notes 1 Since the oscillator has stopped oscillating interrupts not listed above cannot be used Also even the interrupts listed above cannot be used when the above conditions are not satisfied The A D converter does not operate also 2 When multiple interrupts listed above are enabled Stop mode is terminated by the interrupt request which occurs first 3 Refer to CHAPTER 7 INTERRUPTS and the description of each internal peripheral device for details about each interrupt Before executing the STP instruction interrupts used to terminate Stop mode must be enabled In addition the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the processor interrupt priority level IPL of the routine where the STP instruction is executed When multiple interrupts in Table 5 3 2 are enabled Stop mode is terminated by the first interrupt request There is a possibility that any of all interrupt requests occurs after the oscillation starts in D and until supply of ceu and starts in The interrupt requests which occur during this period are accepted in order of priority after the watchdog timer s MSB becomes 0 For interrupts not to be accepted set their interrupt priority levels to level O interrupt disabled before executing the STP instruction 7721 Group User s Manual CL
68. b1 b0 00 Timer mode Pulse output function select bit 0 No pulse output TAjour pin functions as a programmable 1 0 port 1 Pulse output TAjour pin functions as a pulse output pin b4 b3 00 No gate function 01 pin functions as prog rammable port 10 Counter counts only while TAjin pin s input signal is at L level 11 Counter counts only while TAjin pin s input signal is at H level Gate function select bits b7 b6 00 12 01 16 10 fea 1 512 Timer AO register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer 2 register Addresses 4816 4 16 Timer register Addresses 4016 4 16 Timer 4 register Addresses 4F 16 4E16 15 to 0 These bits can be set to 000016 to FFFF ie Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 8 3 1 Structures of timer Ai mode register and timer Ai register in timer mode 8 10 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 1 Setting for timer mode Figures 8 3 2 and 8 3 3 show an initial setting example for registers relevant to the timer mode Note that when using interrupts set up to enable the interrupts For details refer to section CHAPTER 7 INTERRUPTS Selecting timer mode
69. ie eee Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 L Write 2900 Set the number of transfer blocks RW These bits be set to 000001167 to FFFFFF e Read After a value is written to this register and until transfer starts the read value indicates the written value the transfer block number After transfer starts the read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register ta Addresses 1FCAte to 1 816 Addresses 1FDAie to 1 836 Addresses 1 16 to 1FE816 Addresses 1 16 to 1FF8 6 an 17 36 7721 Group User s Manual APPENDIX Appendix 3 Control registers Link array chain transfer mode Addresses 1FC216 to 16 Addresses 1 021 to 120016 Addresses 1FE216 to 1FE016 Addresses 1FF216 016 Source address register 0 Source address register 1 Source address register 2 Source address register 3 S Bit Functions At reset 23 to Write Undefined RW Set the start address of transfer parameter memory of block which is first transferred These bits can be set to 00000046 to FFFFFF e Read After a value is written to this register and until transfer starts the read value indicates the written value t
70. n m 1 fi fi Frequency of count source f2 fea or fs 2 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits Fig 8 6 1 Structures of timer Aj mode registers and timer Aj registers in PWM mode 7721 Group User s Manual 8 39 TIMER A 8 6 Pulse width modulation PWM mode 8 6 1 Setting for PWM mode Figures 8 6 2 and 8 6 3 show an initial setting example for registers relevant to the PWM mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting PWM mode and each function b7 50 1 timer aj mode register j 2 to 4 Addresses 5816 to 5A 9 Selection of PWM mode M Trigger select bits b4 b3 0 i Writing 1 to count start bit Internal trigger 10 11 Falling edge of pin s input signal External trigger Rising edge of pin s input signal External trigger 16 8 bit PWM mode select bit 0 Operates as 16 bit pulse width modulator 1 Operates as 8 bit pulse width modulator Count source select bits b7 b6 00 f2 01 ft6 10 fea 11 512 Setting PWM pulse s period and level width When operating as 16 bit pulse width modulator b15 b8 b7 b0 07 Timer 2 register Addresses 4816 4 16 oT Timer M register A
71. s input signal when bit 3 at addresses 5816 to is 0 or at its rising edge when bit is 1 When using an external trigger set the port P5 direction registers bits which correspond to the TAjin pins for the input mode 65 b4 63 b2 bi ojo One shot start register Address 4216 Fix these bits to 0 The value is 0 at reading wo wo Timer A2 one shot start bit 1 Start outputting one shot pulse o wo 5 valid when internal trigger is Timer A3 one shot start bit selected The value is 0 at readin 7 Timer 4 one shot start bit wo Nothing is assigned Fig 8 5 4 Structure of one shot start register 8 34 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 4 Operation in one shot pulse mode When the one shot pulse mode is selected with the operating mode select bits the TAjour pin outputs L level When the count start bit is set to 1 the counter is enabled for counting After that counting starts when trigger is generated When the counter starts counting the TAjout pin outputs level When the counter value becomes 000046 the output from the TAjout pin becomes L level Additionally the reload register s contents are reloaded and the counter stops counting there Simultaneously with the timer Aj interrupt request bit is set to 1 This
72. 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 10 Counts at both falling and rising edges of external signal 11 Do not select Nothing is assigned This bit is invalid in event counter mode its value is undefined at reading These bits are invalid in event counter mode bO Timer BO register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 9 4 1 Structures of timer Bj mode register and timer Bj register in event counter mode 7721 Group User s Manual 9 15 TIMER B 9 4 Event counter mode 9 4 1 Setting for event counter mode Figure 9 4 2 shows an initial setting example for registers relevant to the event counter mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting event counter mode and count polarity b7 50 oli Timer Bj mode register 0 1 Addresses 5B e 5 1 Selection of event counter mode Count polarity select bits b3 b2 0 0 Counts at falling edge of external signal 0 1 Counts at rising edge of external signal 1 0 Count
73. 0 0 0 0 0 0 010 6516 2 6616 Refresh timer WO 6716 6816 DMAC control register L Note 7 RW 212 100 6916 DMAC control register RW WO 6A16 2 6816 2 6 16 DMAO interrupt control register RW Y 0 0 0 0 6D16 interrupt control register RW 0 0 010 6 16 interrupt control register RW 0101010 6F16 DMAG interrupt control register RW 0 0 0 0 7016 A D conversion interrupt control register RW 0 0 00 7116 UARTO transmit interrupt control register RW 0101010 7216 UARTO receive interrupt control register RW 0 0 0 0 7316 UART1 transmit interrupt control register RW 0 0 0 0 7416 1 receive interrupt control register RW 0101010 7516 Timer AO interrupt contro register RW 0 0 01 0 7616 Timer 1 interrupt control register RW 0101010 7716 Timer A2 interrupt control register RW 0101010 7816 Timer interrupt contro register RW 0101010 7916 Timer A4 interrupt control register RW 0101010 7 16 Timer BO interrupt control register RW 0101010 7816 Timer B1 interrupt control register RW 0101010 7C16 Timer B2 interrupt control register RW 0 0 0 0 7D16 INTo interrupt control register RW 7E16 INT interrupt control register RW 7 16 INT2 interrupt control register RW 0 0 0 0 0 0 Notes 5 By writing dummy data to address 6016 the value FFF16 is set to the watchdog timer The dummy data is not
74. 0000 No DRAM area 000 1 Addresses 0000016 16 1 Mbyte 0 0 1 0 Addresses E000001e FFFFFF16 2 Mbytes 0 0 1 1 Addresses D0000016 FFFFFF1e 3 Mbytes 0 1 0 0 Addresses C00000 6 FFFFFF 6 4 Mbytes 0 1 0 1 Addresses B000001e FFFFFFt16 5 Mbytes 0 1 1 0 Addresses A000001e FFFFFFt 6 6 Mbytes 0 1 1 1 Addresses 900000 e FFFFFF16 7 Mbytes 1000 Addresses 800000 1e FFFFFF16 8 Mbytes 100 1 Addresses 70000016 16 9 Mbytes 101 0 Addresses 60000016 16 10 Mbytes 10 1 1 Addresses 50000016 16 11 Mbytes 1100 Addresses 4000001e FFFFFF16 12 Mbytes 110 1 Addresses 3000001e FFFFFF 6 13 Mbytes 1 1 1 0 Addresses 200000 e FFFFFF 6 14 Mbytes 111 1 Addresses 10000016e FFFFFF16 15 Mbytes DRAM is valid Mon P104 P107 pins function as CAS RAS MAs and MAe function as MAo MA when accessing the DRAM area Refresh timer starts counting z During DRAM area access CAS RAS and MAo MA9 are output Each time an underflow of the refresh timer occurs CAS and RAS for refresh are output During refresh STO and ST1 output L level Fig 14 3 1 Initial setting example for registers relevant to DRAMC 7721 Group User s Manual 14 7 DRAM CONTROLLER 14 4 DRAMC operation 14 4 DRAMC operation 14 4 1 Waveform example of DRAM control signals Figure 14 4 1 shows a waveform example of the DRAM control signals When DRAM is acce
75. 006 OE Destination address register 3 Addresses 1FF616 to 1FF416 Port P6 P7 register s address b23 616015 b8b7 b0 006 006 1016 Transfer counter register Addresses 1 1 to 1FF816 L Data number unit byte b7 10 0 1 0 0 0 DMAS control register Address 1 16 DMA request source Timer BO DMAACKS pin Invalid b7 50 olofo DMAS interrupt control register Address 6F 16 Interrupt disabled X It may be 0 or 1 Fig 16 2 12 Initial setting example for relevant register 1 16 54 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller b7 o 0 0 of of of 0 0 Port P6 register Address E16 Output L level Lights go out b7 0 0 P7 register Address F16 E oi L level All digits OFF b7 bO Port P6 direction register Address 1016 02 Timer BO register Addresses 5116 5016 p Digit switch interval b7 bO x 0 0 Timer BO mode register Address 5816 Timer mode Count source b7 bo 0 0 Timer Bo interrupt control register Address 7A 6 Interrupt disabled b7 Count start register Address 4016 Timer BO count started b7 control register L Address 6816 DMAS request bit 0 b7 bo ft control regis
76. 1 0 Interrupt request occurs when pin is at level Level sense 1 1 Interrupt request occurs when pin INTi is at L level Level sense The INT interrupt request occurs by detecting the state of pin INT all the time Therefore when the user does not use the INT interrupt set the interrupt s priority level to level 0 7 18 7721 Group User s Manual INTERRUPTS 7 10 External interrupts INTi interrupt 67 b6 b5 64 63 b2 bi bO INTo to INT2 interrupt control registers Addresses 7D16 to 7F16 Level 0 Interrupt disabled RW Level 1 Level 2 Level 3 RW Level 4 Level 5 Level 6 Interrupt priority level select bits 3200 o008 dOn gagag 3 Interrupt request bit Note A No interrupt requested Interrupt requested Polarity select bit Interrupt request bit is set to 1 at level when level sense is selected this bit is set to 1 at falling edge when edge sense is selected Interrupt request bit is set to 1 at L at level when level sense is selected this bit is set to 1 at rising edge when edge sense is selected Level sense Edge sense Edge sense select bit Level sense 7 6 7 6 Nothing is assigned Undated Note The interrupt request bits of INTo to INT2 interrupts are invalid when the level sense is selected Fig 7 10 1 Structure of INTi i 0 to 2 interrupt control register 67 b6 b5 04
77. 10 2 Block description 10 2 2 Pulse output data registers 0 and 1 Figure 10 2 2 shows the structure of the pulse output data registers 0 and 1 The bit position of the RTPO2 and RTPOs pulse output data bits differs according to the pulse mode Before setting the pulse output data registers 0 and 1 set of the pulse output mode select bit bit 2 at address 6216 The data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output pins every underflow of Timers AO and 1 67 b6 b5 b4 b3 52 bi Pulse output data register 0 Address 1 16 RTPOo pulse output data bit 0 4 level output 1 level output Fe RTPO pulse output data bit RTPO02 pulse output data bit 3 2 EX Valid in pulse mode 0 RTPOs pulse output data bit 3 Valid in pulse mode 0 704 to 4 70041 Nothing is assigned undetnes Note Use the LDM or STA instruction for writing to this register b7 06 b5 b4 b3 b2 bi Pulse output data register 1 Address 1 16 Te 0 1 Nothing is assigned 2 pulse output data bit 0 L level output efined WO Valid in pulse mode 1 1 level output pulse output data bit efined WO Valid in pulse mode 1 4 RTPto pulse output data bit RTPto pulse output data bit output data bit RTP11 pulse output data bit 6 RTP 12 pulse output data bit i WO 7 RTP13 pulse output data bit Note Use t
78. 25 18 0 85 12 0 6 0 1 0 2 0 3 0 4 0 5 0 V 2 N channel lo Vo characteristics 30 0 24 0 25 18 0 85 mA 12 0 6 0 0 1 0 2 0 3 0 4 0 5 0 VoL V 7721 Group User s Manual 17 107 APPENDIX Appendix 12 Standard characteristics 2 Icc f Xw standard characteristics 1 Icc f Xw characteristics on operating and at reset Measurement condition Vcc 5 0 V Ta 25 C f Xin square waveform microprocessor mode 30 20 On operating At reset e Icc mA 10 0 0 5 10 15 20 25 30 f XiN MHz 2 Wait mode Measurement condition Vcc 5 0 V Ta 25 C f XiN square waveform microprocessor mode Icc mA 0 5 10 15 20 25 30 f XiN MHz 17 108 7721 Group User s Manual APPENDIX Appendix 12 Standard characteristics 3 A D converter standard characteristics The lower lines of the graph indicate the absolute precision errors These are expressed as the deviation from the ideal value when the output code changes For example the change in output code from O to 1 should occur at 10 mV but the measured value is 2 mV Accordingly the measured point
79. 3F16 UARTO transmit buffer register UARTO receive buffer register UART1 transmit buffer register UART1 receive buffer register Access characteristics State immediately after reset b7 RO RO RO RO 5 2 2 21 21 2 51 2 2 21 2 2 5 521 9 o Fig 4 1 5 State of SFR and internal RAM areas immediately after reset 2 4 6 7721 Group User s Manual RESET 4 1 Hardware reset Address Register name Access characteristics State immediately after reset b7 50 4016 Count start register RW 0016 4116 2 4216 start register 010 4316 4416 Up down register 4516 4616 RW A716 Timer AO register RW 4816 RW Timer A1 register 4916 RW 4 16 Note 1 Timer A2 register 4B16 3 Note 1 4C16 Note 1 Timer register 4016 Note 1 4E16 Note 1 AF 16 Timer A4 register Note 1 5016 Note 2 51146 Timer BO register Note 2 5216 Note 2 5316 Timer B1 register Note 2 i Timer B2 register i 5616 Timer AO mode register RW 5716 Timer A1 mode register RW 5816 Timer A2 mode register RW 5916 Timer A3 mode register RW 5A16 Timer A4 mode register RW 5 16 Timer BO mode register RW Note 3 5616 Timer B1 mode register RW Notes 5016 Timer B2 mode register RW ioes 5E16 Processor mode register 0 RW 5F16 Proc
80. 6 Bypass capacitor between Vss and Vcc lines 17 60 7721 Group User s Manual APPENDIX Appendix 8 Countermeasure against noise 3 Wiring for analog input pins analog power source pins etc 1 Processing for analog input pins Connect a resistor to the analog signal line which is connected to an analog input pin in series Additionally connect the resistor to the microcomputer as close as possible Connect a capacitor between the analog input pin and the AVss pin as close to the AVss pin as possible Reason A signal which is input to the analog input pin is usually an output signal from a sensor The sensor which detects changes in status is installed far from the microcomputer s printed circuit board Therefore this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer s analog input pin If a capacitor between an analog input pin and the AVss pin is grounded far away from the AVss pin noise on the GND line may enter the microcomputer through the capacitor Note 2 Accej M37721 Thermistor Reference values RI Approximate 100 to 1000 Q Approximate 100 pF to 1000 pF Notes 1 Design an external circuit for the ANi pin so that charge discharge is available within 1 cycle of 2 This resistor and thermistor are used to divide resistance Fig 7 Countermeasure example against noise for analog input pin using thermistor 7721 Group User s Ma
81. Addresses 4716 4616 Timer A1 register Addresses 4916 48 0 Set to 000016 b7 bo EE 0 0 Timer AO interrupt control register Address 7516 Timer 1 interrupt control register Address 7616 Interrupt disabled No interrupt request b7 50 Count start register Address 4016 Timer AO count start bit 1 Start counting Timer A1 count start bit When Timer 0 or A1 underflows the contents of the pulse output data register 0 or 1 are output from the flip flop b7 60 Count start register Address 4016 Timer AO count start bit 0 Stop counting Timer A1 count start bit 54 Note This processing can be neglected if the system is not affected by undefined output Setting Timers AO 1 b7 50 101010101010 Timer AO mode register Address 5616 Timer A1 mode register Address 5716 Count source select bits 67 b6 0 0 f2 01 16 1 0 fe4 1 1 f512 b15 b8 b7 50 b7 50 Timer AO register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 be set to 000016 FFFF16 n b7 Timer AO interrupt control register Address 7516 Timer 1 interrupt control register Address 7616 as Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 S Continue to Figure 10 3 3 Fig 10 3
82. Addresses Ate Bie E16 Fie 1216 1316 1616 Port Pio s pin Data is input from or output to a pin by reading from or writing to the Port 5 pin 0 L level Undefined 1 H level Port pin Undefined Port Pi4 s pin Undefined Port Pis s pin Undefined Port Pie s pin Undefined x Port Pi7 s pin Undefined Note For bits 0 to 2 of the port P4 register nothing is assigned and these bits are fixed to 0 at reading Port Pi direction register 67 b6 b5 04 b3 b2 bi b0 b pb Port Pi direction register i 4 to 10 Addresses C16 D16 1016 1116 1416 1516 1816 E Port Pio direction bit 0 Input mode Rw 1 Port Pi direction bit 1 Output mode RW Port Pi direction bit The port functions as an output port Ce Note For bits 0 to 2 of the port direction register nothing is assigned and these bits are fixed to 0 at reading 17 10 7721 Group User s Manual APPENDIX Appendix 3 Control registers Pulse output data register 0 67 06 b5 04 63 b2 bi 00 Pulse output data register 0 Address 1 16 eme Tee RTP0Oo pulse output data bit 0 L level output 1 level output RTPO pulse output data bit 2 RTPO2 pulse output data bit Valid in pulse mode 0 3 RTPOs pulse output data bit Valid in pulse mode 0 Nothing is assigned
83. Bit 4 of port P10 register Port P10s CAS address 16 6 address 1616 L level output Ports P104 P105 H level output TAS Bits 4 5 of port P10 direction 4 Bit 5 of port P10 register lt 0 Ee register address 18 address 16 6 p DRAM validity bit lt 0 Bit 4 of port P10 register 1 Port P104 CAS bit 7 at address 6416 DRAMG Stopped address 1616 level output Timer AO mode lt 110000002 amp counted Bit 5 of port P10 register lt 1 Port P10s RAS register address 5616 address 16 level output Timer AO register lt 3124 Timer value set addresses 4716 4616 One cycle 64 ms Interrupt priority level set Level 1 or more Interrupt enabled Timer 0 interrupt XXXX00012 control register address 7516 Return to main routine Timer AO count start lt T Timer AO count started bit bit 0 at address 4016 Interrupt enable flag lt 0 Interrupt enabled WIT instruction Wait mode Wait mode completed Note By using 1 bit of RAM judge whether this interrupt is for return from the wait mode or for refresh 7721 Group User s Manual 17 75 APPENDIX Appendix 9 7721 Group Q amp A DRAM How is the program execution time affected when using DRAM When the M37721 uses DRAM the execution time is affected as follows CPU stops and DRAM refresh cycle is inserted 1 bus cycle becomes 3 when accessing
84. S lt S 1 M S e EAR S lt S 1 Regards the 2nd and 3rd bytes of the instruction as 16 bit numerals adds them to the program counter and saves the result into the stack m 0 5 5 5 1 M S A S lt S 1 m 1 M S A 5 5 1 Saves the contents of accumulator A into the stack 17 46 m 0 5 Sc 8 1 M S B Sc 8 1 m 1 M S B 5 5 1 Saves the contents of accumuator into the stack 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Processor status register DIR L DIR Y ABS ABS b ABS X ABS Y ABL ABL X ABS 5 5 STK REL DIRb R ABSb R SR SR Y BLK 9 8 5 op op n s op n op n op n op n PL m 2 B7 3 BD BF 7 4 A3 3142 42 42 42 B7 BD BF A3 9E 7721 Group User s Manual 17 47 APPENDIX Appendix 6 Machine instructions Addressing modes Functions Details R b DIR X DIR Y DIR DIR X 0 n 0p n fop M S lt DPRuH Saves the contents of the direct page register in
85. Transfer source Wait No transfer destination Wait Single transfer mode 623 516015 b8b7 Source address register 2 Addresses 1FE216 to 1FE016 Timer A0 set value data table s start address b23 6166015 0807 50 006 00 46 Destination address register 2 Addresses 1 616 to 1FE416 Timer A0 register s address b23 616615 b8b7 Transfer counter register 2 Addresses 1 16 to 1FE816 Data number of Timer 0 set value data table b7 50 0 0 0 0 1 1 control register Address 1FEE16 DMA request source Timer AO 2 Invalid 67 bo Jo DMA2 interrupt control register Address 6E 6 Interrupt priority level any of 0012 to 1112 X It may be 0 or 1 Fig 16 2 9 Initial setting example for relevant register 2 7721 Group User s Manual 16 51 APPLICATION 16 2 Examples of using DMA controller b7 LE LIT Port P6 register Address E16 ETE RTPOo P6o RTPO3 P6s initial output level b7 bO 4 1 1 Port direction register Address 1016 00 6 6 pin Output mode b7 Pulse output data register 0 Address 1 16 First phase output data b7 50 10 0 0 0 0 Timer AO mode register Address 5616 Count source b7 bo 1
86. U Note Use the LDM or STA instruction for writing to this register Pulse output data register 1 b7 b6 b5 64 63 b2 bi 00 Pulse output data register 1 Address 1 16 mes 0 1 Nothing is assigned RTPO02 pulse output data bit 0 L level output efined WO Valid in pulse mode 1 1 level output EN Valid in pulse mode 1 5 ata Note Use the LDM or STA instruction for writing to this register 7721 Group User s Manual 17 11 APPENDIX Appendix 3 Control registers A D control register 67 06 65 64 63 02 bi 00 A D control register Address 1216 7 Fincions avs Analog input select bits Undefined RW Valid in one shot and repeat ANo selected modes Note 1 AN selected AN2 selected ANs selected Undefined RW AN4 selected ANs selected ANe selected Undefined RW AN7 selected Note 2 A D operation mode select bit 0 0 Oneshot mode 0 1 Repeat mode Single sweep mode Repeat sweep mode oe med trigger RW Trigger select bit External trigger faw conversion start bit 0 Stop A D conversion 1 Start A D conversion A D conversion frequency 0 fe divided by 4 7 select bit 1 fe divided by 2 Notes 1 These bits are invalid in the single sweep and repeat sweep mo
87. When writing 0 to this bit this bit becomes 0 But when writing 1 to this bit this bit does not change Fig 4 1 7 State of SFR and internal RAM areas immediately after reset 4 4 8 7721 Group User s Manual Address 16 1FC116 1FC216 1FC316 1FC416 1FC516 1FC616 1FC716 1FC816 1FC916 16 1 16 1 16 1FCD16 1FCE16 1FCF16 1FD016 1FD116 1FD216 1FD316 1FD416 1FD516 1FD616 1FD716 1FD816 1FD916 1FDA16 1FDB16 1 0 16 1FDDt16 1FDE16 1FDFi6 Register name Source address register 0 Destination address register 0 Transfer counter register 0 DMAO mode register L DMAO mode register DMAO control register Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register control register RESET 4 1 Hardware reset Access characteristics State immediately after reset b7 50 RW RW RW Fig 4 1 8 State of SFR and internal RAM areas immediately after reset 5 7721 Group User s Manual 4 9 RESET 4 1 Hardware reset Address Register name Access characteristics State immediately after reset b7 50 57 50 1FE016 RW 1FE116 Source address register 2 RW 1FE216 RW 1FE316 1FE416 RW 1FE516 Destination address register 2 RW 1FE616 1FE716 1FE816 1FE
88. bits 4 to 7 at address 6916 is 1 use the LDM or STA instruction in m flag 1 When DMAi request bit bits 4 to 7 at address 6816 must not be changed set DMAi request bit to 1 When writing to this register while all of DMAi enable bits bits 4 to 7 at address 6916 are 0 m flag may be 0 or 1 Use the LDM or STA instruction for writing to this register When DMAi request bit bits 4 to 7 at address 6816 must not be changed set DMAi request bit to 1 Fig 13 2 4 Structure of DMAC control register L 13 10 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 3 DMAC control register H Figure 13 2 5 shows the structure of DMAC control register Each of bits 0 3 is a software i 0 to 3 request bit which corresponds to each channel When a software DMA source is selected as a DMA request source each of these bits is valid Refer to 13 3 2 DMA requests Bits 4 7 are described in section 13 3 1 DMA enabling 67 06 65 64 63 b2 bi bO DMAC control register H Address 6916 Software DMAO request bit 1 DMA request Valid when software DMA source The value is 0 at reading Software request bit DMAO enable bit 0 Disabled 1 Enabled DMA1 enable bit EX enable bit DMA3 enable bit Note When any of bits 4 to 7 is set to 1 use the CLB or SEB instruction for writing to this register Fig 13 2 5
89. cycle transfer it is unnecessary to set DAR When data is transferred form I O to memory in 1 bus cycle transfer it is unnecessary to set SAR Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi Fig 13 5 3 Initial setting example for registers relevant to single transfer mode 2 7721 Group User s Manual 13 57 DMA CONTROLLER 13 5 Single transfer mode From preceding Figure 13 5 3 Selection of priority level and TC pin and setting DMAi request bit to 0 b7 50 DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P10s pin functions as a programmable port 1 Valid P10s pin functions as TC pin request bit DMA request bit request bit DMAS request bit 0 No request 3 DMAC control register H Address 6916 Software request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 L DMAO enable bit L pi enable bit Di DMA2 enable bit DMAG enable bit yy When selecting external When selecting internal When selecting internal DMA DMA source DMA source source except software BE
90. except for the last block for processing of each block in the repeat array chain and link array chain transfer modes 1 unit transfer is performed with one DMAi request and the right to use bus is relinquished after 3 cycles of 9 1 AalDe Avs Dis Bus request sampling DMAACKi TC ST1 STO lt gt lt gt Transition of right Transition of right to use bus to use bus The above figure is the example of the last term for processing the first block in Figure 13 8 9 The Bus request caused by DRAM refresh Hold or DMA is sampled while the bus request sampling signal is H and is accepted Fig 13 8 13 Timing diagram of cycle steal transfer mode 4 7721 Group User s Manual 13 95 DMA CONTROLLER 13 8 Link array chain transfer mode Last transfer of last block At the last term for processing the last block in the single array chain and link array chain transfer modes 1 unit transfer and terminate processing are subsequently performed with one DMAi request 1 R W Ao A7 sa2 n 2 sa2 n 2 da2 n 2 t da2 n 2 t As De A1s D1s c 7 APS es uus utn sete Bus request sampling TC DMAACKi 571 STO 1 0 DMAC lt gt 1 unit transfer Terminate processing 8 Transition of Transition of right to use bus right to use bus The above figure is the exampl
91. f2 f16 fe4 f512 fexr BRGi s count source frequency external clock n Value set in BRGi Fig 11 4 6 Example of transmit timing when transfer data length z 8 bits when parity enabled selecting 1 stop bit not selecting CTS function Transfer clock Transmit enable bit Transmit buffer empty flag CTSi TENDi Parity Stop Stopped because CTS H Stopper transmit TxDi Transmit register empty flag UARTI transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies TENDi Next transmit conditions are examined when this signal level is when the following conditions are satisfied Parity enabled 1 stop bit CTS function selected TENDi is an internal signal Accordingly it cannot be read from the external Tc 16 n 1 fi or 16 n 1 fi BRGi s count source frequency f16 164 1512 fExT BRGi s count source frequency external clock n Value set in BRGi Fig 11 4 7 Example of transmit timing when transfer data length 8 bits when parity enabled selecting 1 stop bit selecting CTS function 7721 Group User s Manual 11 39 SERIAL I O 11 4 Clock asynchronous serial I O UART mode Transfer clock Transmit enable bit Transmit buffer empty flag TENDi TxDi Transmit register empty flag UARTI transmit interrupt request bit Cleared to 0 when interru
92. gt lt gt P86 RxD1 lt gt P85 CLK1 lt gt P76 ANe 75 5 P8e RxD1 lt gt 5 P85 CLK1 lt gt S P84 CTSi RTS1 lt gt 8 P83 TxDo lt gt 3 P82 RxDo lt gt 8 P81 CLKo lt gt 8 P8o CTSo RTSo lt gt 5 P77 AN7 ADTRG External data bus width 16 bits BYTE G External data bus width 3 3 7721 Group User s Manual Fig 3 1 1 Pin configurations when external data bus width is 16 bits and 8 bits top view CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 5 Byte low enable signal BLE Byte high enable signal BHE The BLE signal indicates the access to an even address This signal becomes L level when accessing only an even address or when simultaneously accessing both an even and an odd address The signal indicates the access to an odd address This signal becomes L level when accessing only an odd address or when simultaneously accessing both an odd and an even address These signals are used to connect memories I O devices of which data bus width is 8 bits when the external data bus width is 16 bits Table 3 1 2 lists levels of the BLE and BHE signals and access addresses Table 3 1 2 Levels of BLE and BHE signals and access addresses 6 7 8 9 Access address Even and odd addresses Even address Odd address Simultaneous 2 byte access 1 byte access 1 byte access BLE BHE Address latch enable sign
93. lt gt SVO 0Ld 6 lt gt SVu s0Ld 8q ev lt gt 8YN 0 Ld AWAY lt gt 61 1 4014 AWAY A V lt gt 1nocV 1794 lt gt gt 1no V L eGd lt gt Nev L Gd SVIN EV lt gt Nev L eGd eV INE lt gt 1novV L Gd lt gt 1 lt gt NIpVL SSd IWAN lt gt L SSd lt gt 081 964 gt 081 964 SOAYVING 46d lt gt NIG8I Gd lt gt 1 MOVVIAG 96d lt gt 00d 1H 09d MOVVIAG 96d lt gt 00d LH 09d lt gt Od1H 9d lt gt 14 2MOVVIAG 6d lt gt 041 94 2MOVVIAG 6d lt gt 0419 94 LO3UHVIAG 6d lt gt t0d1H t9d LO3HVIAG 6d lt gt 0d 1H 9d LM9VVIAG 26d lt gt 0LdlH 9d LMOVVINQ 26d lt gt 0Ld1u r9d lt gt lt gt I dlH s9d O0xOVVIAG 6d lt gt Ld1u 99d 03OVvVIAQ 06d lt gt Ld1u 99d lt gt 6419 94 LOXL Z8d lt gt 419 94 EIEIEVEIEIEIEIEIEIEIEIEIBIE M37721S2BFP M37721S2BFP 8 bits BYTE Note For the DRAM control signals refer to CHAPTER 14 DRAM CONTROLLER lt gt lt gt lt
94. mode Do not select RW Do not select UART mode Transfer data length 7 bits UART mode Transfer data length 8 bits UART mode Transfer data length 9 bits Do not select 3 Internal External clock select bit Internal clock External clock Stop bit length select bit HE One stop bit Valid in UART mode Note Two stop bits Odd Even parity select bit 0 Odd parity Valid in UART mode when 1 Even parity parity enable bit is 1 Note Parity enable bit X Parity disabled Valid in UART mode Note Parity enabled Sleep select bit Sleep mode terminated Invalid Valid in UART mode Note Sleep mode selected Note Bits 4 to 6 are invalid in the clock TEES serial I O mode They be either 0 or 1 Additionally fix bit 7 to 0 Fig 11 2 2 Structure of UARTi transmit receive mode register 11 4 7721 Group User s Manual SERIAL I O 11 2 Block description 1 Internal External clock select bit bit 3 Clock synchronous serial I O mode By clearing this bit to 0 in order to select an internal clock the clock which is selected with the BRG count source select bits bits 0 and 1 at addresses 3416 3C e becomes the count source of the BRGi described later The BRGi s output divided by 2 becomes the transfer clock Additionally the transfer clock is output from the CLKi pin By setting this bit to 1 in order to select an external clock the cloc
95. or tsu DH E Fig 16 1 3 Timing for reading data from DRAM CAS access time tcac lt RAS access time trac lt The others are specifications of DRAM tweL ta E casL tsu DL DH E tweL ta E RASL tsu DL DH E Column address access time taa lt ta e ca tsu DL DH E OE access time toea lt tw EL tsu DL DH E Table 16 1 3 lists the calculation formula and value for each parameter in Figure 16 1 3 Figure 16 1 4 shows the relationship between tcac trac taa and f Xin 16 6 7721 Group User s Manual APPLICATION 16 1 Memory connection Table 16 1 3 Calculation formula and Value for each parameter in Figure 16 1 3 unit ns e Calculation formula and Value tw EL 4X 10 _ 25 f Xin ta E RASL 30 ta E CASL 1 X 10 4375 ta E CA 1 X 10 tpzx E DLZ 1 10 _ tpzx E DHZ tsu DL E 30 tsu DH E Note When accessing DRAM Wait is always inserted regardless of the contents of the Wait bit source s Wait bit and destination s Wait bit RAS access time TRAC Column address access time tAA CAS access time tCAC E o o Q lt 20 21 22 23 24 25 MHz External clock input frequency Fig 16 1 4 Relations
96. td AH E 15 min tCAC 20 max tsu DL DH E gt 30 tOEz 0 15 10 M5M417800AJ When writing Li o tw EL 135 min q tw RASL 120 min lt gt tw CASL 55 min tw RASH 60 min td E CASL 80 115 td R W E 20 min de min 2 2 twcs 0 min tWCH 10 min gt lt td RA RAS 5 min RAS RA 18 min Row address Column address gt lt 1 d CA CAS 10 th CAS CA 60 16 00 23 07 0 15 015 Address Data tDH 15 min th E DLQ DH Specifications of M5M417800CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 31 Timing chart for example of M5M417800CJ 2M X 8 bits connection external bus width 16 bits 7721 Group User s Manual 16 35 APPLICATION 16 1 Memory connection 9 Example of DRAM connection external bus width 16 bits M5M44400CJ 7 M37721 Make sure that the propagation delay time is within 40 ns Memory map 00008016 Internal 00047 1 RAM area 00000016 BHE Not used A16 D0 001FC016 A17 D1 SFR area 001FFF16 A18 D2 A19 D3 A20 D4 21 05 22 06 23 07 As Ds A9 D9 M5M4400CJ A10 D10 11 011 A12 D12 Ai3 D13 14 014 15 015 XouT Circuit condition DRAM area select bits bits 3 t
97. the number is calculated as 9 1 2 7 5 Note that i 2 shows the integer part when i is divided by 2 10 The number of cycles is the case in the 16 bit 8 bit operation The number of cycles is incremented by 16 for 32 bit 16 bit operation 11 The number of cycles is the case in the 8 bit X 8 bit operation The number of cycles is incremented by 8 for 16 bit X 16 bit operation 12 When setting flag x 0 to handle the data as 16 bit data in the immediate addressing mode the number of bytes increments by 1 13 When flag m is 0 the byte in the table is incremented by 1 17 54 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Symbols in machine instructions table Symbol Description Symbol Description IMP IMM A DIR DIR b DIR X DIR Y DIR DIR X DIR Y L DIR L DIR Y ABS ABS b ABS X ABS Y ABL ABL X ABS L ABS ABS X STK REL DIR b REL 558 Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct bit addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute bit addressing mode Absolute indexed X addressi
98. tnace A Address middle order hold time BYTE L 9 ns Data high order hold time BYTE L Note 18 ns tpzx e vHz Data high order floating release delay time BYTE L Note 20 ns Address middle order hold time BYTE Note 18 ns tnace aH Address high order hold time 9 ns th E DLa Data low order hold time Note 18 ns tpzx e pLz Data low order floating release delay time Note 20 ns hold time Note 18 ns tE amp e BLE hold time Note 18 ns te uw R W hold time Note 18 ns pulse width Note 55 ns tsu A DL Data low order setup time after address stabilization Note 50 15 tsuate ol Data low order setup time after rising of ALE Note 55 ns tsu A DH Data high order setup time after address stabilization Note 50 15 lsuaLe on Data high order setup time after rising of ALE Note 55 ns Note Figure 13 shows the test circuit 7721 Group User s Manual 17 89 APPENDIX Appendix 11 Electrical characteristics Test conditions port Pi Vcc 25V 10 17 90 Microprocessor mode with Wait lt Write gt 1 E Address output Ao A7 Address output 15 BYTE Address Data output As Ds A15 D15 BYTE 47 Data input Do Dt15 BYTE 47 Address Data output A16 Do A23 D7 Data input Do D7 ALE output output BLE output R W output Port Pi output i
99. 0 Framing error flag When the number of detected stop bits does not match the set number of stop bits UARTi receive interrupt request bit is set to 1 Clear the serial I O mode select bits to 0002 Clear the receive enable bit to 0 Read out the low order byte of the UARTi receive buffer register Parity error flag When the sum of 1 s in the parity bit and character bits does not match the set number of 1 s UARTi receive interrupt request bit is set to 1 Clear the serial I O mode select bits to 0002 Clear the receive enable bit to 0 Read out the low order byte of the UARTi receive buffer register Error sum flag When 1 or more errors listed above occur Clear the all error flags which are overrun framing and parity error flags Note The next data is written into the UARTi receive buffer register When an error occurs during reception initialize the error flag and the UARTi receive buffer register and then perform reception again When it is necessary to perform retransmission owing to an error which occurs in the receiver side during transmission set the UARTi transmit buffer register again and then restarts transmission The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below 1 Method of initializing UARTi receive buffer register Clear the rec
100. 03 07 th E DLQ DHQ 18 min td E DLQ DHQ AC573 tPHL AC139 tPHL AC32 tPHL AC32 tPLH Specifications of MBM28F102AFP 10 Specifications of M5M5256DP 70LL The others are specifications of M37721 Unit ns Fig 16 1 19 Timing chart for example of flash memory and SRAM connection maximum model 7721 Group User s Manual 16 23 APPLICATION 16 1 Memory connection 3 Example of DRAM connection external bus width 8 bits M37721 M5M44800CJ 7 Make sure that the propagation delay time is within 80 ns 000000 000080 nterna Not used 001FFF aga Not used gt gt gt gt gt gt gt gt gt N 8 Col CAS W E 16 00 17 01 A18 D2 A19 D3 20 0 F00000 xd DRAM A21 D5 22 06 7 1 M5M44800CJ 23 07 Not used FFFFFF 6 BYTE XOUT Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 20 Example of M5M44800CJ 512K X 8 bits connection external bus width 8 bits 16 24 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E tw EL 135 min OE tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max lt gt lt 59 td E CASL 77 5 max tw CASL 92 5 min td RA RAS 5 min td CA CAS 5 m
101. 12 5 A D CONVERTER 12 2 Block description 12 2 2 A D sweep pin select register Figure 12 2 3 shows the structure of the A D sweep pin select register 67 06 b5 b4 63 b2 bi 60 A D sweep pin select register Address 16 A D sweep pin select bits bib0 1 RW Valid in single sweep and repeat 0 0 ANo AN 2 pins sweep mode Note 1 0 1 ANo to ANs 4 pins 1 r ANo to ANs 6 pins ANo to 8 pins Note 2 Nothing is assigned Notes 1 These bits are invalid in the one shot and repeat modes They may be either 0 or t 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit of the A D sweep pin select register must be performed while the A D converter halts Fig 12 2 3 Structure of A D control register 1 1 A D sweep pin select bits bits 1 and 0 These bits are used to select analog input pins in the single sweep mode or repeat sweep mode In the single sweep mode and repeat sweep mode pins which are not selected as analog input pins function as programmable ports 12 6 7721 Group User s Manual A D CONVERTER 12 2 Block description 12 2 3 A D register i i 0 to 7 Figure 12 2 4 shows the structure of the A D register i When the A D conversion is completed the conversion result contents of the successive approximation register is stored into this register Each A D register i corresponds to an analog input pin
102. 2 Initial setting example for registers relevant to real time output 2 10 8 7721 Group User s Manual REAL TIME OUTPUT 10 3 Setting of real time output Continue to Figure 10 3 2 When pulse mode 0 a When pulse mode 1 is selected is selected TORR Setting real time output port N Setting real time output port E b7 b7 LL Real time output 2 Real time output Geen Waveform output select bits Waveform output select bits b1 b1 bO 1 RTPOc RTPOs 0 1 RTPO RTP10 RTP13 1 0 RTPOs and RTP1o RTP13 RTP1o RTP13 1 1 RTPOo RTPOs and RTP10 RTP13 Pulse mode 0 ________ Pulse mode 1 cu ee Setting count start bit to 1 b7 50 Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Pulse output starts after overflow of Timer AO or A1 Fig 10 3 3 Initial setting example for registers relevant to real time output 3 7721 Group User s Manual 10 9 REAL TIME OUTPUT 10 4 Real time output operation 10 4 Real time output operation When the timer Ai i 0 1 count start bit is set to 1 the counter starts counting of the count source The contents of pulse output data register i are output from t
103. 3 1 Banks The access space is divided in units of 64 Kbytes This unit is called bank The high order 8 bits of address 24 bits indicate a bank which is specified by the program bank register PG or data bank register DT Each bank can be accessed efficiently by using an addressing mode that uses the data bank register DT If the program counter PC overflows at a bank boundary the contents of the program bank register PG is incremented by 1 If a borrow occurs in the program counter PC as a result of subtraction the contents of the program bank register PG is decremented by 1 Normally accordingly the user can program without concern for bank boundaries SFR Special Function Register and internal RAM are assigned in bank 016 For details refer to section 2 4 Memory assignment 2 3 2 Direct page A 256 byte space specified by the direct page register DPR is called direct page A direct page is specified by setting the base address the lowest address of the area to be specified as a direct page into the direct page register DPR By using a direct page addressing mode a direct page can be accessed with less instruction cycles than otherwise Note Refer also to section 2 1 Central processing unit 2 16 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment 2 4 Memory assignment This section describes the internal area s memory assignment For more informa
104. 4 10 tw H dr tc ta AL E lt gt amp th E AL C Adres d AM E th E AM Ades Ta AM E ta E DHQ th E DHQ Co Dam I td ALE E d Th E BHE ta BLE E th E BLE ta R W E th E R W EE ee td E PiQ Test conditions except port Pi Vcc 2 5 V 10 96 Input timing voltage 1 0 V 4 0 V Output timing voltage Vo 0 8 V 2 0 V Output timing voltage 0 8 V 2 0 V Data input Vir 0 8 V 2 5 V 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with no Wait lt Read gt tw H t tc 1 E ta AL E _ _ gt th E AL Address j Td AM E th E AM Address output BYTE Address Data output As Ds A15 D15 BYTE L td AM E td AM ALE 6 lt tpxz E DHZ 2 le gt th ALE AM tsu A DH tsu DH E th E DH 15 tsu ALE DH BYTES t AH E le gt lt gt tral E DLZ 1 4 lpzx E DUZ Address Data output A16 Do Az3 D7 Address ii C tsu A DL tsu DL E gt lt le th E DL atainput 4 seb er Data Do D7 tsu ALE DL t
105. 5 Sc 8 1 5 5 5 1 PCi lt ADu PCue ADu ADL X 1 Saves the contents of the program counter also the con tents of the program bank register for ABL into the stack and jumps to the new address 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Processor status register L DIR L DIR Y ABS ABS b ABS X ABS Y ABL ABL X ABS L ABS ABS x STK R b R ABS b R SR 9 8 5 op op nj nj g op n amp op nj n op n op op n op n op m EC 4 3 CC 7721 Group User s Manual 17 45 APPENDIX Appendix 6 Machine instructions Functions Details Addressing modes R b DIR X D R Y DIR D n op L op n op DA Notes 1 2 ers the contents of the memory into the accummulator 5 5 2 B2 6 42 B5 42 B2 DM ers the immediate vaiue into the memory 74 DT ers the immediate value into the data bank regiater LDX Note 2 ers the contents of the memory into index register X LDY Note 2 er
106. 6 ER __ 6 Bit 0 of waveform output select bits Data bus even __ OPSWRTPto P6s RTP1 _ 12 m P67 RTP1s Bit 1 of waveform output select bits Fig 10 1 2 Configuration of real time output in pulse mode 0 Pulse output data register 0 b7 Timer AO P6o RTPOo 1 0 P6 RTPO Bit 0 of waveform output select bits Pulse output data register 1 b7 60 Timer 1 Data bus even L PexRTPO0 P6s RTPOs Pe4RTP1o QO P6s RTP11 1 0 P6e RTP12 1 6 1 Bit 1 of waveform output select bits lolololole Fig 10 1 3 Configuration of real time output in pulse mode 1 7721 Group User s Manual 10 3 REAL TIME OUTPUT 10 2 Block description 10 2 Block description Relevant registers to real time output are described below 10 2 1 Real time output control register Figure 10 2 1 shows the structure of the real time output control register 67 b6 65 64 63 b2 bi 00 ____ 11 Real time output control register Address 6216 ES Waveform output select bits See the following Table Mx Pulse output mode select bit Pulse mode 0 Pulse mode 1 7 to 3 Nothing is assigned E The value is 0
107. A D register 0 Addresses 2016 A D register 1 Addresses 2216 A D register 2 Addresses 2416 A D register 3 Addresses 2616 A D register 4 Addresses 2816 67 b6 b5 64 63 62 bi 60 A D register 5 Addresses 216 A D register 6 Addresses 2C 16 A D register 7 Addresses 2E16 7 to 0 Reads an A D conversion result Bit Functions At reset Fig 12 2 4 Structure of A D register i 7721 Group User s Manual 12 7 A D CONVERTER 12 2 Block description 12 2 4 A D conversion interrupt control register Figure 12 2 5 shows the structure of the A D conversion interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS 67 06 65 64 63 b2 A D conversion interrupt control register Address 7016 Level 0 Interrupt disabled RW Level 1 Low level Level 6 Level 2 Level 3 RW Level 4 Level 5 RW Level 7 High level 3 Interrupt request bit 0 No interrupt requested RW 1 Interrupt requested 7 to 4 Nothing is assigned Fig 12 2 5 Structure of A D conversion interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select an A D conversion interrupt s priority level When using A D conversion interrupts select one of the priority levels 1 to 7 When an A D conversion interrupt request occurs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is en
108. A4 this is applies when the timer A s input output pins are used etc Hereafter input output pins are called I O pins 7721 Group User s Manual TIMER A 8 2 Block description 8 2 Block description Figure 8 2 1 shows the block diagram of Timer A Explanation of registers relevant to Timer A is described below Count source fo select bits f 16 N f64 o f512 o Timer mode One shot pulse mode PWM mode Timer mode Data bus odd Data bus even Low order 8 bits High order 8 bits Timer Ai reload register 16 T Gate function Polarity Event counter mode TAINO Trigger is NS Timer Ai P interrupt Timer Ai counter 16 request bit Countup Countdown Switching Count start bit Always count down except for event counter mode Countdown Up down bit Pulse output function select bit TAj ourO Fig 8 2 1 Block diagram of Timer A 4 Toggle 7721 Group User s Manual 8 3 TIMER A 8 2 Block description 8 2 1 Counter and reload register timer Ai register Each of timer Ai counter and reload register consists of 16 bits Countdown in the counter is performed each time the count source is input In the event counter mode it can also function as an up counter The reload register is used to store the initial value of the counter When a counter underflow
109. Addresses 7016 to 7F 6 d EP riorty level Level 0 Interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 1 Interrupt requested Polarity select bit 0 Interrupt request bit is set to 1 at level when level sense is selected this bit is set to 1 at falling edge when edge sense is selected Interrupt request bit is set to 1 at L level when level sense is selected this bit is set to 1 at rising edge when edge sense is selected 5 Level sense Edge sense 0 Edge sense select bit 1 Level sense 7 6 Nothing is assigned Undefined Note The interrupt request bits of INTo to INT2 interrupts are invalid when the level sense is selected 17 32 7721 Group User s Manual APPENDIX Appendix 3 Control registers Source address register i b23 Destination address register i b23 Transfer counter register i b23 b16 b16 b16 b15 b15 b15 b8 57 b8 b7 b8 57 50 50 50 Source address register 0 Addresses 1FC216 to 1FC016 Source address register 1 Addresses 1FD216 to 1FD016 eeu Source address register 2 Addresses 1 216 to 1 016 Source address register Addresses 1FF216 to 1FFO16 23 to o These bits have different functions according to the Undefined RW operating mode Note When writing to this register write to all 24 bits Destination a
110. CLK P8 85 clock output Internal External clock select bit 0 Transfer clock input Internal External clock select bit 1 CTS RTSi CTS input CTS RTS select 0 P80 P8 RTS output CTS RTS select bit 1 Port P8 direction register address 1416 Internal External clock select bit bit at addresses 3016 3816 CTS RTS select bit bit 2 at addresses 3416 Note The TxDi pin outputs H level until transmission starts after UARTi s operating mode is selected 11 16 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 1 Transfer clock Synchronizing clock Data transfer is performed synchronously with the transfer clock For the transfer clock the user can select whether to generate the transfer clock internally or to input it from the external The transfer clock is generated by operation of the transmit control circuit Accordingly even when performing only reception set the transmit enable bit to 1 and set dummy data in the UARTIi transmit buffer register in order to make the transmit control circuit active 1 2 Internal generation of transfer clock The count source selected with the BRG count source select bits is divided by the BRGi and the BRGi output is further divided by 2 This is the transfer clock The transfer clock is output from the pin Setting for relevant r
111. DMA request source Channel priority Transfer rate Internal 14 sources and External 1 source Fixed or Rotating Maximum of 12 5 Mbytes sec at f Xin 25 MHz 1 bus cycle transfer Maximum of 6 25 Mbytes sec at f Xin 25 MHz 2 bus cycle transfer 1 bus cycle or 2 bus cycle transfer Data transfer method Transfer unit Address direction of transfer Transfer mode Continuous transfer mode 8 or 16 bits Fixed Forward or Backward Directions of source and destination are independently selectable Burst transfer or Cycle steal transfer mode Single transfer Repeat transfer Array chain transfer or Link array chain transfer mode 13 2 7721 Group User s Manual DMA CONTROLLER 13 1 Overview 13 1 2 Bus use priority levels The bus use priority levels are fixed by hardware as follows DRAMC gt Hold function gt DMAC gt CPU DRAM refresh Because DMAC has the third priority it actually operates as follows When DRAM refresh request or Hold request is generated during DMA transfer After the transfer of one transfer unit 8 bit or 16 bit data which is being performed at that time is complete DMAC relinquishes the bus to a DRAM refresh or a Hold function When DMAC regains the right to use bus after the DRAM refresh ends or the Hold state is removed DMA transfer is restarted at the following address When DMA request is generated during DRAM refresh or in Hold state DMAC
112. DMA request source select bits dis 0 0 0 0 Do not select 0001 External source DMAREQi Transfer method select bit 0 Software DMA source 0 2 bus cycle transfer 0 Timer AO 1 1 bus cycle transfer 1 Timer A1 1 2 1 1 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UART1 receive UART1 transmit A D conversion Timer A2 Timer A3 Timer A4 Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode 2o2o2oao Transfer source address direction select bits Edge sense Level sense select bit Note 00 Fixed 0 Edge sense 01 Forward 1 Level sense 10 Backward 11 not select DMAACKi validity bit 0 Invalid 1 Valid Transfer destination address direction select bits 00 Fixed No 0 1 Forward 1 0 Backward Note When an external source DMAREQi 1 1 Do not select is selected or when the cycle steal transfer mode is selected set this bit to 0 DMAO mode register Address 1FCD16 DMA1 mode register H Address 1FDD16 DMA2 mode register Address 1FED16 DMA3 mode register H Address 1FFD16 Continue to Figure 13 7 5 on next page ransfer direction select bit Used in 1 bus cycle transfer 0 From memory to I O From I O to memory O connection select bit Valid in 1 bus cycle transfer 0 Data
113. DMAREQi pin s input level is L with the enable bit 1 a DMA transfer starts When the DMAREQi pin s input level goes from L to H the right to use bus will be returned to the CPU at completion of 1 unit transfer under execution at that time When the DMAREQi pin s input level goes L again the DMA transfer restarts at the next address Once a DMAi transfer starts any DMA request including that of other channels cannot be accepted even if the DMAREQi pin s input level is H until the transfer is terminated normally or forcibly However the BUS REQUEST signal is sampled basically at every completion of 1 unit transfer Refer to Table 13 2 3 When a DRAM refresh request or Hold request is generated at this time the right to use bus is not returned to the CPU and the request is accepted When the transfer of an entire batch of data is complete the DMAC relinquishes the right to the CPU If the next DMA request is generated the right is once returned to the CPU to sample the DMA request 7721 Group User s Manual DMA CONTROLLER 13 4 Operation DMAREQO DMAO request bit DMAO enable bit request bit ____ E 1 enable bit DRAM refresh request Right to use bus CPU DMA1 DMAO CPU lt gt gt Channel 1 Entire data transfer Channel 0 Entire data transfer This example applies on the following conditions Bot
114. Fig 16 1 29 Timing chart for example of M5M44170CJ 256K X 16 bits connection external bus width 16 bits 16 33 APPLICATION 16 1 Memory connection 8 Example of DRAM connection external bus width 16 bits M37721 M5M417800CJ 7 1 Make sure that the propagation delay time is within 40 ns Make sure that the propagation delay time is within 15 ns Memory map 00047F16 RAM area Not used 00000016 001 016 001FFF16 _SFR area prey Not used 22 06 23 07 ALE M5M417800CJ As Ds A9 D9 A10 D10 A11 D11 A12 D12 Ai3 D13 14 014 15 015 XouT Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00102 Fig 16 1 30 Example of M5M417800CJ 2M X 8 bits connection external bus width z 16 bits 16 34 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt OE 1 tw EL 135 min tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max td E CASL 77 5 max lt tw CASL 92 5 min td RA RAS 5 min gt gt td CA CAS 5 min MAo MAg Row address Column address 20 max 35 max td E CA 60 j i E CA max 70 gt tpzx E DLZ DHZ 20 min 16 00 23 07 15 015 Address Input data tcLz 5 min 4
115. Group User s Manual 9 25 TIMER B 9 5 Pulse period Pulse width measurement mode MEMORANDUM 9 26 7721 Group User s Manual CHAP TT 10 REAL TIME OUTPUT 10 1 Overview 10 2 Block description 10 3 Setting of real time output 10 4 Real time output operation REAL TIME OUTPUT 10 1 Overview 10 1 Overview The real time output has the function of changing the output level of several pins simultaneously at every period of the timer Figure 10 1 1 shows the block diagram of real time output per bit Real time output has two operating modes described below 1 Pulse mode 0 The 8 bit pulse output pins serve for two independent 4 bit outputs Figure 10 1 2 shows the configuration of real time output in the pulse mode 0 2 Pulse mode 1 The 8 bit pulse output pins serve for a 2 bit and a 6 bit outputs Figure 10 1 3 shows the configuration of real time output in the pulse mode 1 Timer Aj underflow signal zd T Pulse output data register j am A Flip flop O P6i RTPOk P6i RTP1k Bit i of port P6 direction register Port P6i latch o ES oO oO Waveform output select bit Fig 10 1 1 Block diagram of real time output per bit 10 2 7721 Group User s Manual REAL TIME OUTPUT 10 1 Overview Pulse output data register 0 __ P6 RTPO1 Port P6i latch a
116. High order Low order Low order Data 2 Data 2 High order High order Low order Low order Data 1 Data 3 High order High order Backward Backward l Low order Low order Data 3 Data 3 High order High order Low order Low order Data 2 Data 2 High order High order Low order Low order Data 1 Data 1 High order High order k Transfer start address 13 36 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Precautions for 2 bus cycle transfer When the 16 bit external data bus width 16 bits and the transfer unit 16 bits under the following conditions 2 bus cycle transfer cannot be performed Refer to Table 13 4 1 Conditions for transfer destination Transfer destination DRAM area Address direction Backward Data s start address Odd address Conditions for transfer source and destination Transfer source DRAM area Address direction Backward Data s start address Odd address Transfer destination DRAM area 7721 Group User s Manual 13 37 DMA CONTROLLER 13 4 Operation 13 4 2 1 bus cycle transfer When the transfer method select bit Refer to Figure 13 2 6 1 1 bus cycle transfer is selected 1 bus cycle transfer is the method used to transfer data between a memory and I O In this method a read and write of 1 tansfer unit data are simultaneously performed during 1 bus cycle The address bus BHE BLE and
117. I O mode select bits to 0002 Serial I O invalid Set the serial I O mode select bits to 0012 again Set the transmit enable bit to 1 Transmission enabled and set the transmit data to the UARTi transmit buffer register 7721 Group User s Manual 11 29 SERIAL I O 11 3 Clock synchronous serial mode Precautions for clock synchronous serial I O mode 1 The transfer clock is generated by operation of the transmit control circuit Accordingly even when performing only reception transmit operation setting for transmission must be performed In this case dummy data is output from the TxDi pin When receiving simultaneously set the receive enable bit and the transmit enable bit to 1 When receiving data write dummy data to the low order byte of the UARTi transmit buffer register for each reception of 1 byte data When selecting an external clock satisfy the following 3 conditions with the input to the CLKi pin level lt When transmitting gt Set the transmit enable bit to 1 Write transmit data to the UARTi transmit buffer register Input L level to the CTSipin when selecting the CTS function lt When receiving gt Set the receive enable bit to 1 Set the transmit enable bit to 1 Write dummy data to the UARTi transmit buffer register 11 30 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode
118. Manual TIMER B 9 5 Pulse period Pulse width measurement mode Precautions for pulse period pulse width measurement mode 1 A timer Bj interrupt request is generated by the following sources Input of measured pulse s valid edge Counter overflow When the overflow generates the interrupt request the timer Bj overflow flag is set to 1 After reset the timer Bj overflow flag is undefined When a value is written to the timer Bj mode register with the count start bit 1 this flag is cleared to O at the next count timing of the count source An undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting In this case no timer Bj interrupt request occurs The counter value at start of counting is undefined Accordingly a timer Bj interrupt request may be generated by an overflow immediately after the counter starts counting If the contents of the measurement mode select bits are changed after the counter starts counting the timer Bj interrupt request bit is set to 1 When the same value which has been set in these bits are written again the timer Bj interrupt request bit is not changed that is the bit retains the state If the input signal to the TBjin pin is affected by noise etc the counter may not perform the exact measurement We recommend to verify by software that the measurement values are within a constant range 7721
119. Nothing is assigned It is impossible to read the bit state The written value becomes invalid Always 0 at reading Always 1 at reading Always undefined at reading 0 immediately after reset Fix this bit to 0 Access characteristics State immediately after reset b7 67 60 RW RW RW RW RW RW RW RW RW mw Le o o o 0 2 0 lt 21 2 21 21 500 RW RW o 2 74 RW RW RW RW RW RW RW RW RW 52 2 2 21 21 21 21 2 91 21 21 1 9 ojo RW RW 7721 Group User s Manual 17 7 APPENDIX Appendix 2 Memory assignment in SFR area 17 8 Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset 1 1 immediately after reset Undefined immediately after reset Address 1FE016 1FE116 1FE216 1FE316
120. Output timing voltage 0 8 V 2 0 V Data input 0 8 V 2 5 V 7721 Group User s Manual E AL h E DHQ 17 93 APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with Wait lt Read gt 91 Address output Ao A7 Address output As A15 BYTE Address Data output As Ds A15 D15 BYTE 47 Data input Ds D15 BYTE 417 Address Data output 16 00 23 07 Data input Do D7 ALE output BHE output BLE output R W output Port Pi input i 4 10 Test conditions port Pi Vcc 25V 10 td AL E lt gt th E AL ta AM E lt gt th E AM C ws O td AM E _ _ gt tpxz E DHZ td AM ALE le 1 tsu A DH tsu ALE DH td AH E gt k gt lpxz E DLZ o eee td AH ALE gt lt th ALE AH tsu A DL tsu DL E tsu ALE DL t gt td ALE E gt lt gt th E DL ae gt IN Input timing voltage 1 0 V 4 0 V Output timing voltage Vo 0 8 V 2 0 V 17 94 7721 G su PiD E t Test conditions except port Pi Vcc s 5V 10 26 Output timing voltage Vor 0 8 V Vou 2 0 V roup User s Manual Data input 0 8 V 2 5 V DRAM control switching characteristics Vcc 5 V 10
121. P53 TA3 13 P52 TASout lt gt 14 P51 TA2in lt gt 15 P50 TA2out lt gt P107 MAs lt gt 17 P106 MAs lt gt 105 5 lt gt 104 5 lt gt P103 TC lt gt P102 INT2 lt gt P10 INT lt gt P100 INTo lt gt P4 lt gt P45 lt gt P45 lt gt 27 P44 lt gt P43 lt gt ee 2 lt 3 8 O SSA SSAV El lt 334A 81 81 99A lt gt 05 405 19 8 5 19 8d lt gt 9 amp lt gt 514 5 19 8 lt gt 9051 84 ddg8cSLcZZ elN Outline 100P6S A Fig 1 2 1 M37721S2BFP pin configuration top view 7721 Group User s Manual DESCRIPTION 1 2 Pin configuration lt gt P87 TxD lt gt 9 lt gt P9 DMAREQO lt gt P92 DMAACK1 lt gt P9 DMAREQ1 lt gt P9 DMAACK2 lt gt P9 5 DMAREQ2 gt P9e DMAACKS lt gt P97 DMAREQ3 Ao MAo AMA gt As MAs As MAs gt Ae MAe gt lt gt lt gt Ao Do lt gt A D lt gt Au D lt gt Ai2 D lt gt Ai3 D lt gt A D lt gt Ai5 D lt gt lt gt Ai7 D lt gt 02 lt gt 19 03 lt gt Aso Da DESCRIPTION 1 3 Pin description 1 3 Pin description Tables 1 3 1 to 1 3 3
122. P66 RTP 12 P6s RTP1 64 10 P6s RTPOs P62 RTP02 _ P6ei RTPO P60 RTPOo gt 56 5466546 446644 00006 0000 P67 RTP13 P66 RTP12 P6s RTP11 P64 RTP10 P6s RTPOs P62 RTPOe P61 RTPO1 P6o RTPOo 000660 6600 0660 P67 RTP13 7 P6e RTP12 P6s RTP1 P64 RTP10 P63 RTPO3 P62 RTPO2_ Er EQ RTP Peo RTPOo 7721 Group User s Manual 17 29 APPENDIX Appendix 3 Control registers DRAM control register 67 b6 65 64 63 b2 bi b0 DER DRAM control register Address 6416 Bit name Functions DRAM area select bits No DRAM area F00000 6 FFFFFF e 1 Mbyte E0000016 FFFFFF 16 2 Mbytes D000001e FFFFFF is 3 Mbytes 00000 4 Mbytes 00000 5 Mbytes 00000 6 Mbytes 90000016 FFFFFFi 7 Mbytes 80000016 16 70000016 FFFFFFis 9 Mbytes 60000016 1 500000 e FFFFFF e 11 Mbytes 4000006 12 Mbytes 30000016 13 Mbytes 200000 e FFFFFF is 14 Mbytes 100000 e FFFFFFis 15 Mbytes bo eee See a eee oe ee eee et Po 4 1 1 6 to 4 Nothing is assigned i The value is 0 at reading EEEE AEAN E E DRAM validity bit Note 0 Invalid P104 P107 pins function as programmable input ports Ao
123. R W indicate the states of memory Figure 13 4 4 shows an example of connecting external memories and I Os 1 bus cycle transfer M37721 Address bus rri 5 5 2 8 2 2 2 Q a c A a T DMAACKi DMAREQi Note The external circuit such as an address latch is disregarded Fig 13 4 4 Example of connecting external memories and I Os in 1 bus cycle transfer 13 38 7721 Group User s Manual DMA CONTROLLER 13 4 Operation In 1 bus cycle transfer the following considerations must be taken in designing the system Achieve the condition that 1 transfer unit data can be accessed in 1 bus cycle Refer to Table 13 4 5 e Specify the transfer address direction and I O connections Refer to Figure 13 2 7 e Compose the read and write signal generating circuit externally These signals are for I Os The M37721 outputs signals to the memory Accordingly make sure to compose the circuit which generates write signals for 1 05 when the M37721 outputs read signals which generates read signals for when the M37721 outputs write signals Figure 13 4 5 shows an example of the circuit generating a write signal and a read signal for I Os M37721 Generating circuit for read and write signals to I Os DMAREQi Fig 13 4 5 Example of circuit generating write signal and read signal for I Os 7721 Group User s Manual 13 39 DMA CONTROLLER 13 4 Operation
124. Read Undefined RW After transfer starts the read value indicates the destination address of data which is next transferred Transfer counter register 0 Addresses 1FCAte to 1FC816 TCRO Transfer counter register 1 Addresses 1FDAte to 1FD816 TCR1 Transfer counter register 2 Addresses 1FEA e to 1 816 TCR2 Transfer counter register 3 Addresses 1FFAie to 1FF816 TCR3 Write 2316 0 Set the number of transfer blocks py These bits can be set to 00000116 to FFFFFF e Read After a value is written to this register and until transfer starts the read value indicates the written value the transfer block number After transfer starts the read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register Fig 13 7 1 Register structures of SARi DARi and TCRi in array chain transfer mode 7721 Group User s Manual 13 69 DMA CONTROLLER 13 7 Array chain transfer mode 13 7 1 Transfer parameter memory in array chain transfer mode The transfer parameters required for each transfer method are described below These parameters must be located in series starting at even addresses Figure 13 7 2 shows a transfer parameter memory map in the array chain transfer mode 1 2 3 13 70 In 2 bus cycle transfer All of the following transfer parameters
125. STO and ST1 is required 3 DRAM refresh is not performed in Stop or Wait mode 14 12 7721 Group User s Manual CHAPTER 15 WATCHDOG TIMER 15 1 Block description 15 2 Operation description 15 3 Precautions for Watchdog timer WATCHDOG TIMER 15 1 Block description Watchdog functions as follows Detects a program runaway Measures a certain time from when oscillation starts owing to terminating Stop mode Refer to section 5 3 Stop mode 15 1 Block description Figure 15 1 1 shows the block diagram of Watchdog timer i Watchdog timer 1 5 Watchdog timer 9 interrupt request Bus request DRAMC 4 A FFF16 Peg is set Bus request Hold gt CPU wait request Bus request DMAC Writing to watchdog timer register address 6016 J gt 2Vcc detection circuit STP instruction Fig 15 1 1 Block diagram of Watchdog timer 15 2 7721 Group User s Manual WATCHDOG TIMER 15 1 Block description 15 1 1 Watchdog timer Watchdog timer is a 12 bit counter where the count source which is selected with the watchdog timer frequency select bit bit O at address 6116 is counted down A value FFF e is automatically set in Watchdog timer in the cases listed below An arbitrary value cannot be set to Watchdog timer When dummy data is written to the watchdog timer register Refer to Figure 15 1 2
126. Steal No request Note When TC pin validity bit is 1 request bit lt 0 Only burst edge Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREQi pin s input level L Burst Level H In burst transfer mode level sense with DMAREQi pin s input level H Cycle steal Requested In cycle steal transfer mode with any request of Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 Fig 13 5 5 Operation flowchart of single transfer mode 7721 Group Users Manual 13 59 DMA CONTROLLER 13 5 Single transfer mode esn 10 uonisuei lt gt BuisseooJd pejdeooe si pue aces s euBis eui eju pejdures s 10 Aq pesneo 1 sng 99 e lt OVW lt 9 IHYA 0 195 SI U9IUM au IHVS 0 195 S YUM eu ON ON premio premio sung sng z 51991 51091 suonipuoo Burwojo eui uo ejdurexe 541 e snq asn 0 anos JeJsueJ sseJppe Jejsue1 sseJppe eoJnos JeJsueJ JejsueJ Snq anyea Jas YOL Jes JeJSueJ jun Jajsues s
127. Structure of DMAC control register H 7721 Group User s Manual 13 11 DMA CONTROLLER 13 2 Block description 13 2 4 Source address register i SARi Source address register i hereafter called SARi is a 24 bit register with a latch SARi indicates the transfer source address of the data to be transferred next The SARi latch has the following functions Maintains the value written to the address of SARi in the single transfer and repeat transfer modes Indicates the start address of the transfer parameter memory of the next block in the array chain transfer and link array chain transfer modes When a value is written into the address of SARi the same value is written into SARi and the SARi latch When writing a value to the address of SARi all 24 bits must be written The contents of SARi can be read by reading the address of SARi however the value of the SARi latch cannot be read Refer to Tables 13 2 4 and 13 2 5 13 2 5 Destination address register i DARi Destination address register i hereafter called DARi is a 24 bit register with a latch DARi indicates the transfer destination address of the data to be transferred next The DARi latch maintains the value written to the address of DARi When a value is written into the address of DARi the same value is written into DARi and the DARi latch When writing a value to the address of DARi all 24 bits must be written The contents of DARi can be read by reading t
128. TAjour pin outputs L level 7721 Group User s Manual 8 25 TIMER A 8 4 Event counter mode 2 Two phase pulse signal processing function The two phase pulse signal processing function is selected by setting the two phase pulse signal processing select bits bits 5 to 7 at address 441 to 1 Refer to Figure 8 4 5 Figure 8 4 6 shows the timer Aj mode registers when the two phase pulse signal processing function is selected For timers with the two phase pulse signal processing function selected the timer counts two kinds of pulses of which phases differ by 90 degrees There are two types of the two phase pulse signal processing normal processing and quadruple processing In Timers A2 and A3 normal processing is performed in timer A4 quadruple processing is performed For some bits of the port P5 direction register correspond to pins used for two phase pulse input set these bits for the input mode 67 66 65 64 b3 62 bi 60 lt P lt o Jo o o timer a3 mode register Address 581 Timer A4 mode register Address 5 1 X It may be either 0 or 1 Fig 8 4 6 Timer Aj mode registers when two phase pulse signal processing function is selected e Normal processing Countup is performed at the rising edges input to the TAkw pin when the phase has the relationship that the pin s input signal level goes from L to while the TAkout 2 and 3 pin s input signal is at H
129. User s Manual 2 21 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment 67 06 65 04 63 62 bi Fix this bit to 0 ENS is assigned KAR value is 1 at reading 2 Wait bit 0 Software Wait is inserted when accessing external area 1 No software Wait is inserted when accessing external area Software reset bit The microcomputer is reset by writing 1 to this bit The value is 0 at reading b5 b4 00 7 cycles of 0 1 4 cycles of o 2 cycles of Do not select Fix this bit to 0 Stack bank select bit Bank 0 6 L Bits 0 to 6 are not used for the memory assignment Interrupt priority detection time select bits Processor mode register 1 Address 5F 16 0 512 bytes addresses 8016 to 27F 1s Notes 1 2 1 1024 bytes addresses 8016 to 47F 16 wating Notes 1 For the M37721S1BFP fix bit 1 to 0 2 For the M37721S2BFP set bit 1 before setting the stack pointer Fig 2 4 4 Structure of processor mode registers 0 1 2 22 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 5 Bus access right 2 5 Bus access right The M37721 s bus is used for DRAMC Hold function and DMAC besides CPU When the bus requests of two or more source are detected at the same timing the highest bus access priority levels get the access right The bus priority levels are fixed by hardware Additionally the bus use state is ou
130. Vss f Xin 25 MHz unless otherwise noted Note The limits depend on f Xin Table 5 lists calculation formulas for the limits APPENDIX Appendix 11 Electrical characteristics 0 V Ta 20 to 85 Read Limits Symbol Parameter Min Max Unit twrast low level pulse width Note 120 ns twicast CAS low level pulse width Note 92 5 ns twrash CAS high level pulse width Note 60 ns taras cas RAS CAS delay time Note 28 ns 5 Row address delay time before RAS Note 5 ns Row address hold time after RAS Note 18 ns taca cas Column address delay time before CAS 5 ns tncas ca Column address hold time after CAS Note 100 ns tapw ras R W delay time before RAS Note 18 Ds tnicas rw R W hold time after CAS __ Note 18 ns ta E CA Column address delay time after E s low level Note 65 ns RAS delay time after E s low level 30 ns tae cast CAS delay time after E s low level Note 77 5 ns tae rash RAS delay time after E s high level 0 20 ns tae cash CAS delay time after E s high level 0 20 ns Note Figure 13 shows the test circuit Write Limits Symbol Parameter Min Max Unit W RASL RAS low level pulse width Note 120 ns twcast CAS low level pulse width Note 55 ns twrash 5 hi
131. Writing 1 to count start register 0 1 pin functions as a pro grammable I O port Falling edge of TAjin pin s input signal pin s input signal 67 b6 00 12 01 16 10 fea 1 512 lt When operating as a 16 bit pulse width modulator gt b8 Timer 2 register Addresses 4816 4 16 Timer register Addresses 4D16 4 1 Timer 4 register Addresses 4F 16 4 16 15 to 0 These bits can be set to 000016 to FFFE e Undefineal WO Assuming that the set value the level width of the PWM pulse output from the TAjour pin is expressed as follows E 1 PWM pulse period at 1 fi Frequency of count source fis 64 or fs12 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits lt When operating as an 8 bit pulse width modulator gt b15 b8 b7 50 57 Timer 2 register Addresses 4816 4 16 Timer register Addresses 4D16 4 16 Timer 4 register Addresses 4F 16 4E16 7 to 0 These bits can be set to 0016 to FF 16 Undefined WO Assuming that the set value m PWM pulse s period output from the TAjour is expressed as follows ime i 15 to 8 These bits can be set to 0016 to Undefined WO Assuming that the set value the level width of the PWM pulse output from the TAjour pin is expressed as follows
132. X It may be 0 or 1 Transmit data is set UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3 16 b7 50 UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3016 b7 bo 04111 Transmit enable bit 1 Transmission enabled lt gt Transmission starts In the case of selecting the CTS function transmission starts when the CTSi pin s input level is L BRG count source select bits RTS select bit CTS function selected RTS function selected CTS function disabled UARTO baud rate register BRGO Address 3116 UART1 baud rate register BRG1 Address 3916 b7 bo HERR Can be set to 0016 to FF16 Necessary only when internal clock is selected UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 50 LH Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Fig 11 3 1 Initial setting example for relevant registers when transmitting 7721 Group User s Manual 11 19 SERIAL I O 11 3 Clock synchronous serial I O mode When not using interrupts When using interrupts A transmit interrupt request occurs when the UART
133. X Dua X Address X Daa BLE N BHE 8 bit data access 4 16 bit data access uc f Access beginning at odd address E ALE N Ao to A7 Address X Address Asto Ats AvelDo to BLE y N BHE N Y 8 bit data access eat 16 bit data access 7 gt Note When accessing 16 bit data 2 times of access are performed the low order 8 bits are accessed first and after that the high order 8 bits are accessed Fig 3 1 3 Examples of operating waveforms of signals input from or output to the external 2 7721 Group User s Manual 3 7 CONNECTION WITH EXTERNAL DEVICES 3 2 Software Wait 3 2 Software Wait Software Wait provides a function to facilitate access to external devices that require long access time To select the software Wait use the wait bit bit 2 at address 5E e Figure 3 2 1 shows the structure of processor mode register 0 address 5E e Figure 3 2 2 shows examples of bus timing when software Wait is used Software Wait is valid only for the eternal area The internal area is always accessed with no Wait 67 06 65 64 63 b2 61 60 RW Fix this bit to 0 Nothing is assigned The value is 1 at reading Wait bit 0 Software Wait is inserted when RW accessing external area 1 No software Wait is inserted when accessing external area Software reset bit The microcomputer is reset by wr
134. Xin Select software Wait is inserted Refer to section 3 2 Software Wait Use Ready function Refer to section 3 3 Ready function Figure 16 1 9 shows an example of using Ready function no software Wait Figure 16 1 10 shows an example of using Ready function software Wait Ready function is valid for the internal areas so that the circuits in Figures 16 1 9 and 16 1 10 use the chip select signal CS2 to specify areas where Ready function is valid In these cases the CS2 signal is externally generated 7721 Group User s Manual APPLICATION 16 1 Memory connection M37721 k1 to 3 Make sure that the sum of propagation delay time is within Data bus 15 ns 3 to 5 Make sure that the sum of Address Address CS1 i ime is withi ae Sus propagation delay time is within circuit circuit CS2 72 ns Address bus Validate Ready function only for areas accessed by CS2 Circuit conditions f XIN lt 15 7 MHz no software Wait Ready request is accepted at A Termination request for Ready state is accepted at 3B Judgement timing of RDY pin s input level QD E L level stopped by Ready function The condition satisfy tsu RDY 61 gt 55 ns is tc gt 63 5 ns This applies when AC32 s propagation delay time is within 8 5 ns Accordingly when f XIN lt 15 7 MHz this circuit example satisfies tsu RDY 1 gt 55 ns tsu RDY 91 AC
135. affect the counting PWM period H level width lt 16 bit pulse width modulator gt RE CE Canone fi s n Timer Aj register s set value H level width 8 lt 8 bit pulse width modulator gt Timer Aj register low order 8 bits m 1 25 1 Period i s Eu value 1 Timer Aj register high order 8 level width s bits set value Count start condition When trigger is generated Note Internal or external trigger can be selected by software Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing At falling edge of PWM pulse pin s function Programmable I O port or trigger input TAjour pin s function PWM pulse output Read from timer Aj register An undefined value is read out Write to timer Aj register While counting is stopped When a value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time Note The trigger is generated with the count start bit 1 8 38 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode 67 b6 65 b4 63 b2 bi 00 Timer Aj mode register 2 to 4 Addresses 5816 to 5A16 AL ates E 00
136. after writing to an internal area or an external area three NOP instructions must be inserted to complete the write operation before the STP instruction is executed Refer to Figure 5 3 2 STA XXXX Write instruction NOP NOP instruction inserted NOP NOP STP STP instruction Fig 5 3 2 NOP instruction insertion example 5 8 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 4 Wait mode 5 4 Wait mode Wait mode is used to stop ceu when there is no need to operate the central processing unit CPU The microcomputer enters Wait mode when the WIT instruction is executed Wait mode can be terminated by an interrupt request occurrence or the hardware reset 5 4 1 Wait mode When the WIT instruction is executed stop The oscillator s oscillation is not stopped This state is called Wait mode In Wait mode the microcomputer s power consumption is lowered though Vcc power source voltage is maintained Table 5 4 1 lists the microcomputer s state and operation in and after Wait mode Table 5 4 1 Microcomputer s state and operation in and after Wait mode Item State and Operation State in Oscillation Operating Wait mode CPU Stopped Clock 1 12 to 1512 Operating D Timer A Timer B Serial I O A D converter DMA controller Stopped DRAM controller Stopped Note Watchdog timer Op
137. an example of determining the channel priority levels 7721 Group User s Manual 13 21 DMA CONTROLLER 13 3 Control Priority level Fixed priority Bus request sampling DMAO request bit request bit request bit DMAS request bit Channel priority level 0 gt 1 gt 2 gt 3 DMA transfer execution channel Priority level Rotating priority Bus request sampling DMAO request bit request bit request bit DMAS request bit Channel priority level 2 1 0 lt 0 lt 6 lt 0 60 lt 1 lt 0 lt 6 6 lt 2 lt 1 lt 0 1 lt 0 lt 6 lt 6 6 lt 0 lt lt 0 2 1 0 0 lt 6 lt 0 lt lt 1 lt 0 lt 6 6 lt 2 lt 1 lt 0 1 lt 0 lt 6 lt 6 6 lt 0 lt lt 0 The above timing diagram applies on the following conditions DRAM refresh request no Hold request All of DMAi enable bits are 1 Fig 13 3 1 Example of determining channel priority levels 13 22 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 4 Processing from DMA request until DMA transfer execution DMA requests are sampled at every falling edge of when requested the request bit is set to 1 Then the channel priority levels and bus use priority levels are determined and BUS REQUEST DMAC goes 1 if any DRAM refresh request or Hold request is not generated Note BUS REQUEST DMAC signal is sampled while the bus reques
138. and each function b7 50 olol Timer Ai mode register i 0 to 4 Addresses 5616 5A16 Selection of timer mode Pulse output function select bit 0 No pulse output 1 Pulses output _ Gate function select bits 04 b3 p No gate function 1 0 Gate function Counter counts only while TAjin pin s input signal is at L level 1 1 Gate function Counter counts only while TAjin pin s input signal is at H level Count source select bits b7 b6 0 0 fe 0 1 fie 1 0 164 1 1 512 27 Note For Timers AO and 1 set bits 0 to 5 to 0 ara division ratio bs Timer AO register Addresses 4716 4616 b7 bo Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4816 4A 6 Timer register Addresses 4016 4616 Timer A4 register Addresses 416 4E16 Can be to 000016 to FFFF e n Note The counter divides the count source frequency by n 1 Continue to Figure 8 3 3 on next page Fig 8 3 2 Initial setting example for registers relevant to timer mode 1 7721 Group User s Manual 8 11 TIMER A 8 3 Timer mode From preceding Figure 8 3 2 Setting interrupt priority level Ny b7 ci Timer Ai interrupt control register i 0 to 4 1 Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of l
139. at reading Note When using the pins as the pulse output pins for real time output set the corresponding bits of the port P6 direction register address 1016 to 1 P67 RTP13 7 P66 RTP 12 P6s RTP11 P64 RTP10 P6s RTPOs P62 RTPO2 P61 RTPO1 P60 RTPOo J P67 RTP13 7 P66 RTP 12 P6s RTP1 P64 RTP10_ P6s RTPOs gt P62 RTP02 P6 RTPO Pey RTPO P67 RTP1s 7 P6e RTP12 P6s RTP1 P64 RTP10 P6s RTPOs P62 RTP02 P61 RTP0 POyRTPOo J P67 RTP13 P66 RTP 12 P6s RTP1 P64 RTP1o P6s RTPOs P62 RTPOz P61 RTPO1 P60 RTPOo When pulse mode 0 is selected P67 RTP13 5 P66 RTP12 P6s RTP1 P64 RTP1o P63 RTPOs P62 RTPO2_ P6 RTPO Aj pon P67 RTP13 7 P6e RTP12 P6s RTP1 64 1 P63 RTPO3 P62 RTPO2 _ P61 RTPO1 P6eo RTPOo ATR P67 RTP13 P66 RTP 12 P6s RTP11 P64 RTP 10 P6es RTPOs P62 RTP02 P67 RTP13 5 P6e RTP12 P6s RTP1 64 1 P63 RTPO3 P62 RTPO2_ 6 Be When pulse mode 1 is selected P61 RTPO1 P60 RTPOo 2 O 20 20 26 66 6666446 6666 05 656444 6006 666666 66066 Port This functions as a programmable I O port RTP This functions as a pulse output pin Fig 10 2 1 Structure of real time output control register 10 4 7721 Group User s Manual REAL TIME OUTPUT
140. bit bit at addresses 3016 3816 CTS RTS select bit bit 2 at addresses 3416 Notes 1 The TxDi pin outputs level while transmission is not performed after selecting UARTi s operating mode 2 The CTS RTSi pin can be used as an input port when performing only reception and not using the RTS function when selecting CTS function 7721 Group User s Manual 11 31 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 1 Transfer rate Frequency of transfer clock The transfer rate is determined by the BRGi addresses 3116 3916 When setting into BRGi BRGi divides the count source frequency by 1 The BRGi s output is further divided by 16 and the resultant clock becomes the transfer clock Accordingly is expressed by the following formula F n Value set BRGi 0016 to DAB 1 F BRGi s count source frequency Hz B Transfer rate bps An internal clock or an external clock can be selected as the BRGi s count source with the internal external clock select bit bit 3 at addresses 3016 3816 When an internal clock is selected the clock selected with the count source select bits bits 0 and 1 at addresses 3416 3Cis becomes the BRGi s count source When an external clock is selected the clock input to the CLKi pin becomes the BRGi s count source Set the same transfer rate for both transmitter and receiver sides Tables 11 4 3 and 11 4 4
141. bits Fig 8 4 1 Structures of timer Aj mode register and timer Aj register in event counter mode 8 20 7721 Group User s Manual TIMER A 8 4 Event counter mode 8 4 1 Setting for event counter mode Figures 8 4 2 and 8 4 3 show an initial setting example for registers relevant to the event counter mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting event counter mode and each function b7 bo x x o o 1 Timer Aj mode register j 2 to 4 Addresses 5816 to 5A 6 Selection of event counter mode Pulse output function select bit 0 No pulse output 1 Pulse output Count polarity select bit 0 Counts at falling edge of external signal 1 Counts at rising edge of external signal Up down switching factor select bit 0 Contents of up down register 1 Input signal to TAjour pin X It may be either 0 or 1 Setting up down register b7 50 TIT T folol Up down register Address 4416 Set the corresponding up down bit when the contents of the up down register are selected as the up down Timer A2 up down bit switching factor Timer A3 up down bit 0 Countdown Timer A4 up down bit 1 Countup Timer A2 two phase pulse signal processing select bit Timer A3 two phase pulse signal processing select bit Timer A4 two phase pulse signal processing select bit Set
142. bits the number of transfers the number of transfer bytes 2 When the transfer unit is 8 bits the number of transfers the number of transfer bytes In 1 bus cycle transfer Refer to Table 13 4 5 Terminate processing cycles Transition of the right to use bus from DMAC to CPU 1 cycle Example External data bus width 16 bits 2 bus cycle transfer transfer unit 16 bits the number of the transfer bytes 10 bytes and under the following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data even without Wait O 0 940 145 3 4 3 1 40 cycles 7721 Group User s Manual 13 101 DMA CONTROLLER 13 9 DMA transfer time 2 Repeat transfer mode In the repeat transfer mode of burst transfer edge sense the method of terminating DMA transfer is only the forced termination by the TC input Therefore the time from the CPU s relinquishing the right to use bus until regaining the right depends on the timing of the TC input TC input Right to use Transition Transition Transfer Transfer lt gt gt Pit e gt 4 8 1 block Fig 13 9 5 Repeat transfer mode burst transfer mode and edge sense selected Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per 1 block e In 2 bus
143. bus Do D or Do D s Data bus De D s Transfer source wait bit Valid in DMA transfer 0 Wait No wait Transfer destination wait bit Valid in DMA transfer 0 Wait 1 No wait Selection of array chain transfer mode 623 b16 b15 8 b7 5007 6067 Source address register 0 Addresses 1FC216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1 216 to 1 016 SAR2 Source address register Addresses 1FF216 to 1 016 SAR3 Set the start address of transfer parameter memory These bits can be set to 00000016 to FFFFFF e 623 b16 b15 b8 es 1916 i UT po Transfer counter register 0 Addresses 1FCA16 to 1 816 TCRO 1 Transfer counter register 1 Addresses 1FDAis to 1 081 TCR1 Transfer counter register 2 Addresses 1 16 to 1 816 TCR2 Transfer counter register Addresses 1FFA16 to 1FF816 TCR3 Set the number of transfer blocks These bits can be set to 00000116 to FFFFFF e Ne Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi Fig 13 7 4 Initial setting example for registers relevant to array chain transfer mode 2 7721 Group User s Manual 13 73 DMA CONTROLLER 13 7 Array chain transf
144. causing the A D converter to start operating Clearing this bit to O causes the A D converter to stop operating In the one shot mode or single sweep mode this bit is cleared to 0 after the operation is completed In the repeat mode or repeat sweep mode the A D converter continues operating until this bit is cleared to 0 by software When external trigger is selected When the 0 pin level goes from to L with this bit 1 a trigger occurs causing the A D converter to start operating The A D converter stops when this bit is cleared to 0 In the one shot mode or single sweep mode this bit remains set to 1 even after the operation is completed In the repeat mode or repeat sweep mode the A D converter continues operating until this bit is cleared to 0 by software 4 A D conversion frequency select bit bit 7 As listed in Table 12 2 1 the conversion time of the A D converter varies depending on the operating clock selected by this bit Since the A D converters comparator consists of capacity coupling amplifiers keep that gt 250 kHz during A D conversion Table 12 2 1 Conversion time per one analog input pin unit ps A D conversion frequency select bit 0 1 f2 4 f2 2 Conversion time f Xin 8 MHz 57 0 28 5 16 MHz 28 5 14 25 f Xin 25 MHz 18 24 9 12 7721 Group User s Manual
145. characteristics Appendix 11 Electrical characteristics The electrical characteristics of the M37721S2BFP are described below For the latest data inquire of addresses described last CONTACT ADDRESSES FOR FURTHER INFORMATION Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Voc Power source voltage 0 3 to 7 V Analog power source voltage 0 3 to 7 V Vi Input voltage RESET CNVss BYTE 0 3 to 12 V Vi Input voltage As Ds Ais D15 A1e Do Azs Dr 4 4 P5o P5 P7o P77 80 87 P90 P97 10 10 RDY HOLD Veer Vo Output voltage As Ds Ais D15 A e Do Aes Dz P43 P 47 5 5 P6o P67 P7o P77 8 8 P9c P9 P100 P107 0 3 to Vec 0 3 V RESETour Xour E STO ST1 ALE BLE BHE R W Pa Power dissipation 25 300 mW Operating temperature 20 to 85 C Tstg Storage temperature 40 to 150 C 0 3 to 0 3 V 17 80 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Recommended operating conditions Vcc 5 V 10 Ta 20 to 85 C unless otherwise noted Symbol Parameter emits Unit Min Typ Max Vcc Power source voltage 4 5 5 0 5 5 V AVcc Analog power source voltage Vcc V Vss Power source voltage 0 V AVss Analog power source voltage 0 V Vin High l
146. conditions are Tenni Next transmit conditions are examined when this signal level is satisfied Tenni is an internal signal Accordingly it cannot be read from the external Internal clock selected CTS function not selected Tc 2 n 1 fi fi BRGi count source frequency 12 116 164 1512 n Value set in BRGi Fig 11 3 6 Example of transmit timing when selecting internal clock not selecting CTS function 11 22 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 4 Method of reception Figures 11 3 7 and 11 3 8 show initial setting examples for relevant registers when receiving Reception is started when all of the following conditions to are satisfied When an external clock is selected satisfy conditions to with the following precondition satisfied lt Precondition gt The CLKi pin s input is at H level Note When an internal clock is selected the above precondition is ignored Reception is enabled receive enable bit 1 Transmission is enabled transmit enable bit 1 Dummy data is present in the UARTi transmit buffer register transmit buffer empty flag 0 By connecting the RTSi pin receiver side and CTSi pin transmitter side the timing of transmission and that of reception can be matched For details refer to section 11 3 5 Receive operation When using interrupts it is necessary to set t
147. destination address direction backward start address of data odd with Wait O 04 0 1 4 25 3 4 1 34 cycles Table 13 9 1 Time required for processing in array state External data Number of transfer Number of reads of Time required for Mode bus width Transfer method parameters a transfer parameter processing in array state Unit cycle Array chain 16 bits 2 bus cycle transfer 3 2 3 2 3 1 19 transfer mode Including internal bus 1 bus cycle transfer 2 2 2x2x3 12 13 8 bits 2 bus cycle transfer 3 4 3 4 3 1 37 1 bus cycle transfer 2 4 2x4x34 1 25 Link array chain 16 bits 2 bus cycle transfer 4 2 4 2 3 1 25 transfer mode Including internal bus 1 cycle transfer 3 2 3 2 3 1 19 8 bits 2 bus cycle transfer 4 4 4 4 1 49 1 bus cycle transfer 3 4 3x4x341 37 13 100 7721 Group User s Manual DMA CONTROLLER 13 9 DMA transfer time 13 9 2 Burst transfer mode 1 Single transfer mode a CPU andi DMAC CPU Transition Transfer _ TerminationTransition Fig 13 9 4 Single transfer mode burst transfer mode selected Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per an entire batch of data In 2 bus cycle transfer Read cycle Write cycle x the number of transfers 1 Add a value which satisfies the read write conditions Refer to Table 13 4 1 3 2 When the transfer unit is 16
148. details refer to CHAPTER 7 INTERRUPTS When external DMA source is selected When internal DMA source is selected m port P9 direction register N b7 50 Port 9 direction register Address 1516 pin DMAREGI pin DMAREQ2 pin DMAREQ3 pin Clear the corresponding bit to 0 N Setting interrupt priority level b7 interrupt control register i 0 to 3 Tit Addresses 6C to 6F1e Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 P Continue to Figure 13 7 4 on next page Fig 13 7 3 Initial setting example for registers relevant to array chain transfer mode 1 13 72 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode From preceding Figure 13 7 3 Selection of transfer mode and each function b7 b0 DMAO mode register L Address 1FCC o po DMAO control register Address 1 mode register L Address 1FDC e EN 1 111 DMAT control register Address 1FDE16 DMA2 mode register L Address 1 16 DMA control register Address 1FEE 6 DMAS3 mode register L Address 1 16 DMAS3 control register Address 1FFE16 Number of unit transfer bits select bit
149. etc When using bus buffers various logical circuits etc be sure to consider the propagation delay time etc 1 Timing for reading data When reading data the external data bus is placed in a floating state and data is read from the external memory This floating state is maintained after the falling edge of the E signal until an interval of tpzxe vLz oHz has passed after the rising edge of the E signal Satisfy 1 when inputting data read from the external memory The following are described below eTiming for reading data from the flash memory SRAM and DRAM Calculation formulas for the external memory s access time which are for tsupuou e to be satisfied The memory output enable signal OE is assumed to be generated from the E signal Timing for reading data from flash memory and SRAM External memory output enable signal Read signal External memory chip select signal 5 tpzx E DLZ DHZ Address output and Data input Aa Ds A15 D15 1 Address A16 Do A23 D7 ta AD tsu A D tor tdis oE External memory data output tsu DUDH Specifications of the M37721 The others are specifications of external memory 1 This applies when the external data bus has a width of 16 bits BYTE L 2 If data is output from the external memory before the falling edge of E there is a possibility that the tail of
150. external DMA source is selected When internal DMA source is selected ne port P9 direction register N b7 50 Port P9 direction register Address 1516 pin DMAREGI pin DMAREQ2 DMAREQS Clear the corresponding bit to 0 Setting interrupt priority level b7 50 interrupt control register i 0 to 3 AL Addresses 6 to 6F 1 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 2 Continue to Figure 13 5 3 on next page Fig 13 5 2 Initial setting example for registers relevant to single transfer mode 1 13 56 7721 Group User s Manual DMA CONTROLLER 13 5 Single transfer mode From preceding Figure 13 5 2 s election of transfer mode and each function bo control register Address 1FCEt6 1 control register Address 1FDE16 control register Address 1FEE 6 DMAS control register Address 1FFE16 DMA request source select bits Do not select Timer BO Timer B1 External source DMAREQI Software DMA source Timer B2 UARTO receive Timer 0 Timer A1 UARTO transmit Timer A2 UART1 receive UART1 transmit Timer A3 Timer A4 conversion b7 b0 DMAO mode register L Address 1 16 bl ft pol LT DMA
151. fi fi Frequency of count source f2 fis fe4 or fs12 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits 67 06 65 04 63 62 61 60 fo 111110 Timer Aj mode register j 2 to 4 Addresses 5816 to 5 16 1111512 i P b1 b0 Operating mode select bits 1 0 One shot pulse mode Rw Fix this bit to 1 in one shot pulse mode Rw i b4 b3 Trigger select bits 00 Writing 1 to one shot start register RW 0 1 TAjin pin functions as a prog i rammable I O port t 1 0 Falling edge of TAjin pin s input signal RW i 11 Rising edge of 5 input signal Fix this bit to 0 in one shot pulse mode Rw i H b7 b6 Count source select bits 00 fe i 01 fie 10 f s ES i 7721 Group User s Manual 17 21 APPENDIX Appendix 3 Control registers Pulse width modulation PWM mode lt When operating as a 16 bit pulse width modulator gt b15 b8 b7 50 57 50 p o M Timer register Addresses 4016 4 16 Timer 4 register Addresses 4F e 4E16 15 to 0 These bits can be set to 000016 to FFFE e Undetined WO Assuming that the set value n the level width of the PWM pulse output from the TAjour pin is expressed as follows E 1 PWM pulse period x 1 fi Frequency of count source fa 116 fea
152. from the timer Bj register perform it in a unit of 16 bits Table 9 2 1 Memory assignment of timer Bi registers Timer Bi register Timer BO register High order byte Address 5116 Low order byte Address 5016 Timer B1 register Address 5316 Address 5216 Timer B2 register Address 5516 Address 5416 Note At reset the contents of the timer Bi register are undefined 7721 Group User s Manual TIMER B 9 2 Block description 9 2 2 Count start register This register is used to start and stop counting Each bit of this register corresponds to each timer Figure 9 2 2 shows the structure of the count start register 67 06 65 64 63 02 bi b0 Count start register Address 4016 Timer AO count start bit 0 Stop counting 1 Start counting 1 Timer A1 count start bit Timer A2 count start bit 7 Timer B2 count start bit L Bits 0 to 4 are not used for Timer B Fig 9 2 2 Structure of count start register 9 4 7721 Group User s Manual TIMER B 9 2 Block description 9 2 3 Timer Bi mode register Figure 9 2 3 shows the structure of the timer Bi mode register The operating mode select bits are used to select the operating mode of Timer Bi Bits 2 3 and bits 5 to 7 have different functions according to the operating mode These bits are described in the paragraph of each operating mode b7 b6 65 64 63 b2 bi 60 Timer Bi mode register i 0 to 2 Addr
153. gt L tw EL 135 min APPLICATION 16 1 Memory connection tw RASL 120 min tw RASH 60 min td E RASL 30 max lt gt td RAS CAS 28 min td E CASL 77 5 max td RA RAS 5 min tw CASL 92 5 min gt BE L gt 5 m MAo MA7 Row address td E CA 60 max 16 00 23 07 As Ds A15 D15 Address je o td AH E 15 min As Ag M5M44170AJ Column address tOEA 20 max tAA 35 max tRAC 70 max gt Input data tpzx E DLZ DHZ 20 min tCLZ 5 min tCAC 20 max tsu DL DH E 2 30 10 2 0 20 lt When writing gt so 4 tw RASH 60 min tw EL 135 min EN td R W E 20 lt tw RASL 120 min lt tw CASL 55 min itd E CASL 80 115 td RA RAS 5 min IAC32 tPHL X 2 twcs 0 min twCcH 15 min C32 tPHL X 2 RAS RA 18 min MAo MAo d CA CAS 10 th CAS CA 60 min 16 00 23 07 As Ds A15 D15 Address Data td BLE BHE E 20 min tDH 15 min BLE BHE lt _ gt th E DLQ DHQ 18 min Specification of M5M44170CJ 7 The others are specifications of M37721 7721 Group User s Manual Unit ns
154. higher priority level is sent to the next comparator Z in Figure 7 5 2 Initial comparison value of X is 0 For interrupt which is not requested the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is When the two priority levels are found the same by comparison the priority level which is sent from the preceding comparator is forwarded to the next comparator Accordingly when the same priority level is set by software the interrupt priority levels are handled as follows DMA3 gt DMA2 gt DMA1 gt DMAO gt A D conversion gt UART1 transmit gt UART1 receive gt UARTO transmit gt UARTO receive gt Timer B2 gt Timer B1 gt Timer BO gt Timer A4 gt Timer A3 gt Timer A2 gt Timer A1 gt Timer 0 gt INT gt INT gt INTo Among the multiple interrupt requests sampled at the same time one request with the highest priority level is detected by the above comparison Then this highest interrupt priority level is compared with the processor interrupt priority level IPL When this interrupt priority level is higher than the processor interrupt priority level IPL and the interrupt disable flag 1 is 0 the interrupt request is accepted A interrupt request which is not accepted here is held until it is accepted or its interrupt request bit is cleared to 0 by software The interrupt priority is detected w
155. inserted when accessing external area 1 No software Wait is inserted when accessing external area B Lr Ellos mes Software reset bit The microcomputer is reset by i writing 1 to this bit The value is 0 at reading eae b5 b4 ESAE E te Mui 00 7 cycles of i 0 1 4 cycles of ME 10 2 cycles of 1 1 Do not select bows ont c Fix this bit to 0 Eee ae EE Ra Stack bank select bit E Bank 0 6 Bank FF e Processor mode register 1 67 b6 65 64 b3 b2 bi 60 Processor mode register 1 Address 5F 16 sme ES Nothing is assigned E Internal RAM area select bit 0 512 bytes addresses 8016 to 27F 6 Notes 1 2 1 1024 bytes addresses 801610 ah 2025225 7 to 2 to2 7102 Nothing i is assigned TES Notes 1 For the M37721S1BFP fix bit 1 to 0 2 For the M37721S2BFP set bit 1 before setting the stack pointer 7721 Group User s Manual 17 27 APPENDIX Appendix 3 Control registers Watchdog timer register b7 50 Watchdog timer register Address 6016 Initializes Watchdog timer Undefined When dummy data is written to this register Watchdog timer s value is initialized to FFF16 Dummy data 0016 to FF 16 Watchdog timer frequency select register 67 66 65 64 63 62 61 60 Watchdog timer frequency select register Address 6116 Watchdog timer frequency select
156. is 1 the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 128 and 127 and cleared to 0 in all other cases The overflow flag is also set to 1 when a result of division exceeds the register length to be stored in a division instruction DIV When the BVC or BVS instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLV or CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode Bit 7 Negative flag N It is set to 1 when a result of arithmetic operation or data transfer is negative Bit 15 of the result is 1 when the data length flag is 0 or bit 7 of the result is 1 when the data length flag is 1 It is cleared to 0 in all other cases When the BPL or BMI instruction is executed this flag determines whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode Bits 10 to 8 Processor interrupt priority level IPL These three bits can determine the processor interrupt priority level to one of levels 0 to 7 The interrupt is enabled when the interrupt priority level of a required interrupt which is set in each interrupt control register is higher tha
157. level Countdown is performed at the falling edges input to the pin when the phase has the relationship that the TAkin pin s input signal level goes from H to L while the TAkour pin s input signal is at H level Refer to Figure 8 4 7 TAkour k 2 3 Counted Counted Counted Counted Counted Counted up up up down down down Fig 8 4 7 Normal processing 8 26 7721 Group User s Manual TIMER A 8 4 Event counter mode Quadruple processing Countup is performed at all rising and falling edges input to the TA4our and TA4in pins when the phase has the relationship that the TA4in pin s input signal level goes from L to H while the TA4our pin s input signal is at H level Countdown is performed at all rising and falling edges input to the TA4our TA4in pins when the phase has the relationship that the TA4in pin s input signal level goes from to L while the TA4ovr pin s input signal is at level Refer to Figure 8 4 8 Table 8 4 3 lists the relationship between the input signals to the TA4our and TA4in pins and count operation when the quadruple processing is selected TA4out Counted up at all edges Counted down at all edges 1 1 1 1 Counted up at all edges 1 1 1 1 i Fig 8 4 8 Quadruple processing Table 8 4 3 Relationship between input signals to TA4our and TA4w pins and count operation when quadruple
158. level and Table 7 3 2 lists the interrupt enabled level corresponding to IPL contents The interrupt disable flag 1 interrupt request bit interrupt priority level select bits and processor interrupt priority level IPL are independent of one another they do not affect one another Interrupt requests are accepted only when the following conditions are satisfied Interrupt disable flag 1 0 Interrupt request bit 1 Interrupt priority level gt Processor interrupt priority level IPL 7721 Group User s Manual 7 7 INTERRUPTS 7 3 Interrupt control Table 7 3 1 Setting of interrupt priority level Interrupt priority level select bits Interrupt priority level Priority b2 b1 50 0 0 0 Level 0 Interrupt disabled 0 0 1 Level 1 Low 0 1 0 Level 2 0 1 1 Level 3 1 0 0 Level 4 1 0 1 Level 5 1 1 0 Level 6 1 1 1 Level 7 High Table 7 3 2 Interrupt enabled level corresponding to IPL contents IPL2 IPL IPLo Enabled interrupt priority level 0 0 0 Enable level 1 and above interrupts 0 0 1 Enable level 2 and above interrupts 0 1 0 Enable level 3 and above interrupts 0 1 1 Enable level 4 and above interrupts 1 0 0 Enable level 5 and above interrupts 1 0 1 Enable level 6 and level 7 interrupts 1 1 0 Enable only level 7 interrupt 1 1 1 Disable all maskable interrupts IPLo Bit 8 in processor status register PS IP
159. link array chain transfer mode consists of an array state and a transfer state 1 Array state In an array state transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi DARi and TCRi and their latches As shown in Figure 13 8 2 a transfer parameter consists of 4 bytes 24 bits of data 8 bits of dummy data One bus cycle always consumes 3 cycles of During an array state the DMAACKi pin outputs H level For the bus request sampling in an array state refer to section 13 2 1 Bus access control circuit 2 Transfer state Data is transferred in a transfer state For the bus request sampling in a transfer state refer to section 13 2 1 Bus access control circuit 7721 Group User s Manual 13 87 DMA CONTROLLER 13 8 Link array chain transfer mode On and after First of each block second SARi Transfer parameter Note Transfer source s transfer start address DARi lt Transfer parameter Note Transfer destination s transfer start address TCRi lt Transfer parameter Byte number of transfer data SARi latch lt Transfer parameter Start address of next transfer parameter memory request bit 0 Only in cycle steal transfer mode 1 unit transfer Burst Edge Refer to section 13 4 Operation Burst Level L Cycle steal Requested Transfer completion of 1 block Burst Edge Burst Level L Cycle steal Requested
160. list the setting examples of transfer rate Table 11 4 3 Setting examples of transfer rate 1 Transtar 24 576 MHz f Xin 25 MHz BRGi s BRGi s set Actual time BRGi s BRGi s set Actual time rate bps count source value bps count source value bps 300 300 00 fea 80 50 6 301 41 600 600 00 fie 162 A216 599 12 1200 1200 00 fie 80 5016 1205 63 2400 2400 00 fie 40 28 2381 86 4800 4800 00 2 162 A216 4792 94 9600 9600 00 2 80 5016 9645 06 14400 14490 57 f2 53 3516 14467 59 19200 19200 00 f2 40 2816 19054 58 31250 f2 24 1816 31250 00 38400 38400 00 f Xin 22 1184 MHz BRGi s BRGi s set Actual time rate bps count source value bps 300 fea 71 4716 300 00 600 fis 143 8F 16 600 00 1200 fis 71 4716 1200 00 2400 fis 35 2316 2400 00 4800 f2 143 8F 16 4800 00 9600 f2 71 4716 9600 00 14400 f2 47 216 14400 00 19200 f2 35 2316 19200 00 28800 f2 23 1716 28800 00 31250 fo 21 1516 31418 18 38400 f2 17 1116 38400 00 57600 fo 11 OBie 57600 00 115200 fo 5 0516 115200 00 230400 f2 2 0216 230400 00 11 32 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 2 Transfer data format The transfer data format can be selected from formats shown in Figure 11 4 1 Bits 4 to 6 at addresses 3016 and 3816 select the transfe
161. min th RAS RA 18 min gt lt Row Address Column address td CA CAS 10 min th CAS CA 60 min 16 00 23 07 08 15 015 Address Data td BLE BHE E 20 min 15 min AC157 tPHL lt gt th E DLQ DHQ 18 min BLE BHE Specifications of M5M418160CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 27 Timing chart for example of M5M418160CJ 1M X 16 bits connection external bus width 16 bits 7721 Group User s Manual 16 31 APPLICATION 16 1 Memory connection 7 Example of DRAM connection external bus width 16 bits M37721 M5M44170CJ 7 1 Make sure that the propagation delay time is within 40 ns 2 Make sure that the propagation delay time is within 15 ns 00008016 Internal 00047 26 RAM area 5 16 0 17 01 A18 D2 A19 D3 A20 D4 21 05 22 06 23 07 1 NOOR WM 4 EN zs Not used 6 ALE 0000016 9 09 DRAM area A10 D10 F7FFFFie M5M44170CJ 11 011 12 0 Not used 14 014 FFFFFF16 15 015 Xour Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 28 Example of M5M44170CJ 256K X 16 bits connection external bus width z 16 bits 16 32 7721 Group User s Manual lt When reading
162. next block SARi Indicates the address of the next transfer source DARi latch Not used DARI Indicates the address of the next transfer destination TCRi latch Indicates the number of remaining transfer blocks TCRi Indicates the number of remaining transfer bytes TC pin validity bit Bit 1 at address 6816 13 68 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode b16 b15 Source address register 0 Addresses 1FC216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1FE216 to 1 016 SAR2 Source address register 3 Addresses 1FF216 to 1FFO16 SAR3 Write Set the start address of transfer parameter memory RWV These bits can be set to 00000016 to FFFFFF e Read After a value is written to this register and until transfer starts the read value indicates the written value the start address of the transfer parameter memory After transfer starts the read value indicates the Source address of data which is next transferred Note When writing to this register write to all 24 bits b16 b15 Destination address register 0 Addresses 1FC616 to 1 416 DARO Destination address register 1 Addresses 1FD6 6 to 1 416 DAR1 Destination address register 2 Addresses 1 16 to 1FE416 DAR2 Destination address register 3 Addresses 1 to 1FF416 DAR3 Need not to be set 23 to 0
163. of change is 10 2 12 mV The upper lines of the graph indicate the input voltage width for which the output code is constant For example the measured input voltage width for which the output code is 15 is 24 mV so that the differential non linear error is 24 20 4 mV 0 2 LSB Measurement conditions Vcc 5 V Vee 5 12 V f Xin 25 MHz 25 C fe divided by 2 30 TT yt 30 20 20 ERROR mV 2 o 1LSBWIDTH mV 20 30 rr b b LE CECEE TELLE eee See eee ee LLL LLLI 32 40 48 56 64 72 80 88 96 104 112 120 128 STEP No 30 TT yt 30 zo 10 3 19 z PHHH 0 1 0 8 20 128 136 14 152 160 168 176 14 192 200 208 216 24 22 240 248 256 STEP 7721 Group User s Manual 17 109 APPENDIX Appendix 12 Standard characteristics MEMORANDUM 17 110 7721 Group User s Manual GLOSSARY GLOSSARY This section briefly explains the terms used in this user s manual The terms defined here apply to this manual only Term Access Meaning Means performing read write or read and write In DRAMC also means performing DRAM refresh Relevant term Access space An accessible memory space of up to 16 Mbytes Access Access characteristics Means whether accessible or not Access Branch Means movin
164. of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials e if these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
165. of the DMAACKO signal Refer to Figure 16 2 2 Timer generates the time from when the ACK signal rises until the BUSY signal falls one shot pulse mode the trigger is the rising edge of the DMAACKO signal Refer to Figure 16 2 2 4 is used for BUSY signal generation When outputting level the next transfer can wait In that case the contents of the preceding transfer are hold in the octal latch When the data buffer is filled in other words DMA transfer is completed a DMA interrupt occurs 7721 Group User s Manual 16 43 APPLICATION 16 2 Examples of using DMA controller M37721 Octal latch AC574 Data bus DMAREQO one shot output TASIN DMAACKO TA2IN P43 2 one shot output Fig 16 2 1 Example of Centronics interface configuration DMAACKO TA20UT T2 Timer A2 s set time T3 Timer A3 s set time Fig 16 2 2 Relationship between ACK and BUSY 16 44 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller 2 Initial setting example for relevant register Port P4 register Address A 6 b7 bO 1 P43 output H level b7 bO 1 Port P5 register Address B16 TA3out output level D F F initialized b7 50 Pi ae fee cle ae Port P4 direction register Address C16 P43 Output mode b7 bO Port P5 direction register Address D16
166. of the successive approximation register with the analog input voltage Vin which is input from the analog input pin ANi By reflecting the comparison result on the successive approximation register Vin is converted into a digital value When a trigger is generated the A D converter performs the following processing Determining bit 7 of the successive approximation register The A D converter compares with Vin At this time the contents of the successive approximation register is 100000002 initial value Bit 7 of the successive approximation register changes according to the comparison result as follows When Veet lt Vin bit 7 1 When gt Vin bit 7 0 Determining bit 6 of the successive approximation register After setting bit 6 of the successive approximation register to 1 the A D converter compares Veet with Vin Bit 6 changes according to the comparison result as follows When Veet lt Vin bit 6 1 When Vret gt Vin bit 6 40 Determining bits 5 to 0 of the successive approximation register Operations in are performed for bits 5 to 0 When bit 0 is determined the contents conversion result of the successive approximation register is transferred to the A D register i The comparison voltage Vre is generated according to the latest contents of the successive approximation register Table 12 3 1 lists the relationship between the successive approximation reg
167. port P10 Port P10 is an 8 bit I O port with the same function as P107 P4 These pins can be programmed as pin for TC and output pins for DRAM controller P10c P10z2 also function as input pins for INTo INT2 1 6 7721 Group User s Manual 1 4 Block diagram DESCRIPTION Figure 1 4 1 shows the M37721 block diagram 1 4 Block diagram yd uod Sd uod 2 uod Hod uod Old eyeq sseippy indingandu indingandu indingandu indinog indu indingandu MINIMI MIL ML MEN 8 91 6 td 8 8 8 Ld 8 8d 8 LE __ 1 __7 tit PEL 5 22 44 45 91 8 6 1 91 08 91 OWL 91 6 1 91 191 91 eva 91 291 jeu 91 nig eue T 030 eoepelul 219 sng 91 IYL vz0L WOH 91 Data Bus Even Data Bus Odd Address Bus Jeu 91 91
168. register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer BO mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register Real time output control register DRAM control register Refresh timer DMAC control register L DMAC control register H DMAO interrupt control register interrupt control register interrupt control register DMAS interrupt control register A D conversion interrupt control register UARTO transmit interrupt control register UARTO receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer AO interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer 4 interrupt control register Timer BO interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INTo interrupt control register INT interrupt control register INT2 interrupt control register 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment Address 001FCO016 001FC116 Sour
169. register Write to timer Aj register When a value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time Note The trigger is generated with the count start bit 1 7721 Group User s Manual 8 29 TIMER A 8 5 One shot pulse mode 67 06 65 64 b3 b2 i Timer Aj mode register 2 to 4 Addresses 5816 to 5A 6 b1 b0 1 0 One shot pulse mode b4 b3 00 Writing 1 to one shot start register 0 1 pin functions as a prog rammable I O port Falling edge of TAjin s input signal 1 1 1 Rising edge of 5 input signal b7 b6 00 fe 01 fie 10 fea 1111512 Timer 2 register Addresses 4816 4 1 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4Fi6 4E 6 15 to 0 These bits can be set to 000116 to FFFF e Undefined WO Assuming that the set value n the H level width of the one shot pulse output from the TAjour pin is expressed as follows n fi fi Frequency of count source fis 164 or 1512 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits Fig 8 5 1 Structures of timer Aj mode regis
170. registers 7721 Group User s Manual 7 5 INTERRUPTS 7 3 Interrupt control Fig 7 6 67 b6 b5 b4 63 62 bi DMAO to DMA3 conversion UARTO and 1 transmit UARTO and 1 receive timers 0 to A4 timers BO to B2 interrupt control registers Addresses 6C 6 to 7 16 iori b2 b1 60 4 neni Level 0 Interrupt disabled Level 1 Level 6 Level 7 3 Interrupt request bit 0 No interrupt requested 1 Interrupt requested Nothing is assigned Level 2 Level 3 RW Level 4 Level 5 67 b6 b5 b4 b3 b2 bi T2 interrupt control registers Addresses 7016 to 7F 6 Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit Note 0 No interrupt requested 1 Interrupt requested Polarity select bit 0 Interrupt request bit is set to 1 i 34223200008 300 0078 5 at level when level sense is selected this bit is set to 1 at falling edge when edge sense is selected Interrupt request bit is set to 1 at L level when level sense is selected this bit is set to 1 at rising edge when edge sense is selected Level sense Edge sense PE Edge sense select bit Level sense Nothing is assigned Note The interrupt request bits of INTo to INT2 interrupts are invalid when the level sense is selected 7 3 2 S
171. request bit is set to 1 The conversion stops The A D conversion start bit remains set to 1 after the operation is completed Accordingly the operation of the A D converter can be performed again from step when the level of the pin changes from H to L When the level of the ADtre pin changes from to L during operation the operation at that point is cancelled and is restarted from step Figure 12 5 2 shows the conversion operation in the one shot mode Trigger occur Conversion result Convert input voltage from R A D register i ANi pin A D conversion interrupt request occurs A D converter halt Fig 12 5 2 Conversion operation in one shot mode 12 16 7721 Group User s Manual A D CONVERTER 12 6 Repeat mode 12 6 Repeat mode In the repeat mode the operation for the input voltage from the one selected analog input pin is performed repeatedly In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E e remains set to 1 until it is cleared to 0 by software and the operation is performed repeatedly while the A D conversion start bit is 1 12 6 1 Settings for repeat mode Figure 12 6 1 shows an initial setting example for registers relevant to the repeat mode 7721 Group User s Manual 12 17 A D CONVERTER 12 6 Repeat mode A D control register b7 bo J
172. select the CTS function pins P80 and P84 function as CTS input pins and the input signal of L level to these pins becomes one of the transmission conditions By setting this bit to 1 in order to select the RTS function pins P80 and P84 become RTS output pins When the receive enable bit bit 2 at addresses 3516 6 is 0 reception disabled the RTS output pin outputs H level In the clock synchronous serial I O mode the output level of the RTS pin becomes L when reception conditions are satisfied and it becomes H when reception starts Note that when an internal clock is selected bit 3 at addresses 3016 3816 O the RTS output is undefined Accordingly do not select the RTS function In the clock asynchronous serial I O mode the output level of the RTS pin becomes L when the receive enable bit is set to 1 It becomes H when reception starts and it becomes L when reception is completed 2 Transmit register empty flag bit 3 This flag is cleared to 0 when the UARTi transmit buffer register s contents are transferred to the UARTi transmit register When transmission is completed and the UARTi transmit register becomes empty this flag is set to 1 11 6 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 3 UARTi transmit receive control register 1 Figure 11 2 4 shows the structure of UARTi transmit receive control register 1 For b
173. separately The data length flag m determines whether the register is used as a 16 bit register or as an 8 bit register When an 8 bit register is selected only the low order 8 bits of accumulator A are used and the contents of the high order 8 bits is unchanged 2 Accumulator Accumulator B is a 16 bit register with the same function as accumulator A Accumulator B can be used instead of accumulator A The use of accumulator B however except for some instructions requires more instruction bytes and execution cycles than that of accumulator A Accumulator B is also controlled by the data length flag m just as in accumulator A 2 1 2 Index register X X Index register X consists of 16 bits and the low order 8 bits can also be used separately The index register length flag x determines whether the register is used as a 16 bit register or as an 8 bit register When an 8 bit register is selected only the low order 8 bits of index register X are used and the contents of the high order 8 bits is unchanged In an addressing mode in which index register X is used as an index register the address obtained by adding the contents of this register to the operand s contents is accessed In the MVP or MVN instruction a block transfer instruction the contents of index register X indicate the low order 16 bits of the source address The third byte of the instruction is the high order 8 bits of the source address Note Refer to 7700
174. shifted by 1 bit to the right Steps and are repeated at each rising edge of the transfer clock When set of data has been prepared in other words when the shift has been performed several times according to the selected data format the UARTi receive register s contents are transferred to the UARTi receive buffer register Simultaneously with step the receive complete flag is set to 1 Additionally a UARTi receive interrupt request occurs and its interrupt request bit is set to 1 The receive complete flag is cleared to 0 when the low order byte of the UARTi receive buffer register is read out The RTSi pin s output level becomes L simultaneously with step amp when selecting the RTS function Figure 11 4 12 shows an example of receive timing when the transfer data length 8 bits Transmitter side Receiver side Fig 11 4 11 Connection example 11 44 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode BRGi count source Receive enable bit RxDi Stop bit Transfer clock _ At falling edge of start bit transfer clock UARTi receive register gt UARTI receive buffer register Receive is generated and reception started AU ue complete flag Wn RTSi UARTi receive interrupt request bit The above timing diagram applies when the Cleared to 0 when interrupt request is accepted following conditions are satisfied or
175. the UARTi transmit register is transmitted from the TxDi pin synchronously with the falling edge of the transfer clock This data is transmitted bit by bit sequentially beginning with the least significant bit When 1 byte data has been transmitted the transmit register empty flag is set to 1 This indicates the completion of transmission Figure 11 3 4 shows the transmit operation When an internal clock is selected when the transmit conditions for the next data are satisfied at completion of the transmission the transfer clock is generated continuously Accordingly when performing transmission continuously set the next transmit data to the UARTi transmit buffer register during transmission when the transmit register empty 0 When the transmit conditions for the next data are not satisfied the transfer clock stops at H level Figures 11 3 5 and 11 3 6 show examples of transmit timing b7 bO transmit buffer register Transmit data V MSB LSB Transfer clock transmit register D7 Ds Dz D1 Do E 66 os e os oo wd C T To s 55 ps gt 0 196300008 gt De Annnhnnn mmmm Fig 11 3 4 Transmit operation 7721 Group User s Manual 11 21 SERIAL I O 11 3 Clock synchronous serial I O mode Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register Transmit buffer
176. the method used to transfer data between memories Since this method has a read and a write cycle it consumes a minimum of 2 bus cycles for 1 unit transfer Figure 13 4 1 shows an example of connecting external memories in 2 bus cycle transfer M37721 Address bus 92JnO0S JOJSUBI sseuyppe 92JnO0S J9JSUEJ ua 3 JeJsue ssesppe 19JSUE ITI E 29 o lt n 20 Note The external circuit such as an address latch is disregarded Fig 13 4 1 Example of connecting external memories in 2 bus cycle transfer 13 30 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 1 Register operation in 2 bus cycle transfer Figure 13 4 2 shows a basic operation of registers for 1 unit transfer in 2 bus cycle transfer For register values to be specified refer to section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode It is because that these values vary according to continuous transfer modes In 2 bus cycle transfer the data read at a read cycle is maintained temporarily in the DMA latch and the contents of this latch are written to a memory at a write cycle 1 Read cycle DMAC Transfer source address is specified by SARi Note Contents of TCRi are updated by decrementer Transfer Note when value read from TCR is 0 transfer sour
177. to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time 7721 Group User s Manual 8 19 TIMER A 8 4 Event counter mode 67 06 65 64 63 b2 bi 00 Timer Aj mode register 2 to 4 Addresses 5816 to 5 16 a ee ew Operating mode select bits 0 1 Evanteountor mode Pulse output function select bit 0 No pulse output TAjour pin functions as a programmable port 1 Pulse output TAjour Da functions as a pulse output pin Count polarity select bit A Counts at falling edge of external signal Counts at rising edge of external signal Up down switching factor select Contents of up down register bit Input signal to TAjour pin 5 Fix this bit to 0 in event counter mode These bits are invalid event counter mode EE o jew Timer A2 register Addresses 4 16 4 1 Timer register Addresses 4D16 4 1 Timer A4 register Addresses 4F16 4E16 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 during countdown or by FFFF 6 n 1 during countup When reading the register indicates the counter value Note Read from or write to this register in a unit of 16
178. transfer source s transfer start address transfer data s byte number next transfer parameter memory s start address from I O to memory transfer destination s transfer start address transfer data s byte number next transfer parameter memory s start address SARi latch 0 and TCRi 0 Falling edge of TC pin s input from H to L when the TC pin validity bit 1 Write 0 to the DMAi enable bit At normal termination SARi latch Indicates the transfer parameter memory s start address of the next block SARi Indicates the address of the next transfer source DARi latch Not used DARI Indicates the address of the next transfer destination TCRi latch Not used TCRi Indicates the number of remaining bytes being transferred TC pin validity bit Bit 1 at address 6816 Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers 13 80 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode b16 b15 Source address register 0 Addresses 1FC216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1FE216 to 1FE016 SAR2 Source address register 3 Addresses 1FF216 to 1FF016 SAR3 Set the start address of transfer parameter memory s Mid of block which is first transferred These bits can be set to 00000016 to FFFF
179. tsu A DH tpzx E DLZ 1 X 10 tpzx E DHZ f Xin en tsu DL E 30 tsu DH E Wait No Wait N S o o o 5 m oS E E 2 o S tv e 10 11 12 138 14 15 16 17 18 19 20 21 External clock input frequency f XIN Fig 16 1 2 Relationship between tsu a bLon and f Xin 7721 Group User s Manual 16 5 APPLICATION 16 1 Memory connection Timing for reading data from DRAM DRAM output enable signal Read signal OE td tw EL H E RASL Address output MAo MA7 Row addres td E CASL Column address Td E CA 16 00 23 07 Address output and Data I O Atos Mou 51 Address DRAM data output 21 This applies when the external data bus has a width of 16 bits BYTE L 2 If one of DRAM s specifications is greater than tpzx E DLZ DHZ tpzx E DLZ DHZ tOEZ 2 tsu DL DH E there is a possibility that the tail of data collides with the head of address gt Refer to section 3 Precautions on ___ Specifications of the M37721 memory connection Note tpzx E DLZ DHZ tpzx E DLZ or tpzx E DHZ tsu DL DH E tsu DL E
180. upper 8 bits Direct page register s lower 8 bits Processor status register Processor status register s upper 8 bits Processor status register s lower 8 bits Processor status register s b th bit Contents of memory at address indicated by stack pointer b th memory location Value of 24 bit address s upper 8 bit Value of 24 bit address s middle 8 bit A1s As Value of 24 bit address s lower 8 bit A7 Ao Operation code Number of cycle Number of byte Number of transfer byte or rotation Number of registers pushed or pulled 17 55 APPENDIX Appendix 7 Hexadecimal instruction code table Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 1 0010 0011 Hexadecimal notation ORA SEB ORA A SR ABS b A ABS ORA ORA ORA CLB ORA A DIR A SR Y A ABS Y ABS b 5 JSR AND AND BBS AND ABL A SR ABS b R A ABS AND AND AND BBC AND A DIR A SR Y A ABS Y ABS b R A ABS X EOR EOR JMP EOR Note 1 A SR A IMM ABS A ABS EOR EOR EOR JMP EOR A DIR A SR Y A ABS Y ABL A ABS X ADC ADC JMP ADC PER A SR A IMM ABS A ABS ADC ADC ADC JMP ADC A DIR A SR Y A ABS Y 5 5 BRA STA STY STA Note 2 REL A SR ABS A ABS STA STA STA LDM STA A DIR A SR Y j j A ABS Y ABS A ABS X LDX LDA LDA LDY LDA IMM A SR D
181. value n the counter divides the count source frequency by n 1 during countdown or by FFFF e n 1 during countup When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits 67 b6 65 64 63 b2 Timer Aj mode register j 2 to 4 Addresses 5816 to een n 0 1 Event counter mode EET Pulse output function select bit 0 No pulse output TAjour pin functions as a programmable I O port 1 Pulse output TAjout functions as a pulse output pin 82 Count polarity select bit ME Counts at falling edge of external signal Counts at rising edge of external signal eene eee Up down switching factor select E Contents of up down register bit Input signal to TAjour pin Po 4 5 Fix this bit to 0 in event counter mode SSSR SS a NS See These bits are invalid in event counter mode 17 20 7721 Group User s Manual APPENDIX Appendix 3 Control registers One shot pulse mode b15 b8 b7 bO b7 Timer register Addresses 4016 4 16 Timer 4 register Addresses 4Fi6 4 16 15 to 0 These bits can be set 000116 to Undefined WO Assuming that the set value the level width of the one shot pulse output from the TAjour pin is expressed as follows
182. which is accessed frequently because the internal RAM can be accessed with no Wait Accordingly it is expected that the capacity will lack to be used as the stack area As for the M37721 DRAM area can be set as the stack area because cheap DRAM can be connected Use bank 0 which is assigned to the internal RAM area as the stack area when DRAM is not connected or the internal RAM is sufficient to be used as the stack area 17 72 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A DRAM WIT instruction Are there methods to refresh DRAM in the wait mode 7721 Group User s Manual 17 73 APPENDIX Appendix 9 7721 Group Q amp A In the wait mode DRAM refresh function does not operate but the watchdog timer timer A and timer B operate Accordingly DRAM can be refreshed by using these timers and ports 1 Method using watchdog timer Interval of watchdog timer interrupt Return from the wait mode by the watchdog f Xin fa selected selected timer interrupt Control ports P104 P10s by 25 MHz 2 621 ms 41 943 ms software and perform the CAS before RAS 16 MHz refresh 4 096 ms 65 536 ms Example 1 A case in 1024 refresh cycles every 16 4 ms f Xw 16 MHz watchdog timer count source fs2 DRAM refresh is performed 256 times This refresh is performed by every watchdog timer interrupt See flow chart Flow chart Main routine Watchdog timer interrupt routine Watchdog timer freque
183. 1 416 1FE516 1FE616 1FE716 1FE816 1FE916 1FEA16 1FEB16 16 1FED16 1 16 1 16 1FF016 1FF116 1FF216 1FF316 1FF416 1FF516 1FF616 1FF716 1FF816 1FF916 1 16 1 16 1FFCi6 16 1FFE16 1FFF16 0 1 RS Register name Source address register 2 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 Destination address register 3 Transfer counter register 3 DMAS mode register L DMAS3 mode register DMAS control register Always 0 at reading Always 1 at reading Always undefined at reading Access characteristics 0 immediately after reset Fix this bit to 0 State immediately after reset b7 RW RW RW RW RW RW RW RW RW 30 00 50 RW RW RW RW RW RW RW RW RW RW RW RW SISIEN ES RW RW ojojo ojojo 7721 Group User s Manual APPENDIX Appendix 3 Control registers Appendix 3 Control registers The control registers allocated in the SFR area are shown on the following pages Below is the structure diagram for all registers 1 67 66 65 04
184. 1 fie 10 fea 11 f512 UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 Receive enable bit CTS RTS select bit RIT 1 Reception enabled 0 CTS function selected 1 RTS function selected 2 Reception starts when the start bit is detected Fig 11 4 9 Initial setting example for relevant registers when receiving 11 42 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode When not using interrupts When using interrupts A UARTI receive interrupt request occurs when reception is completed Checking completion of reception UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3016 UARTI receive interrupt b7 Receive complete flag 0 Reception not completed C 1 Reception completed E Checking error UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Framing error flag Parity error flag Error sum flag 0 No error 1 Error detected Reading of receive data UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F16 3E16 b15 b8 b7 50 Read out receive data Checking error UARTO transmit receive control register 1 Address 351
185. 1 and 2 The timer Aj interrupt request bit is set to 1 each time the PWM pulse level goes from to L The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Each time PWM pulse has been output for one period the reload register s contents are reloaded and the counter continues counting The following explains operations of the pulse width modulator 1 16 bit pulse width modulator When the 16 8 bit PWM mode select bit is set to 0 the counter operates as a 16 bit pulse width modulator Figures 8 6 4 and 8 6 5 show operation examples of the 16 bit pulse width modulator 2 8 bit pulse width modulator When the 16 8 bit PWM mode select bit is set to 1 the counter is divided into 8 bit halves Then the high order 8 bits operate as an 8 bit pulse width modulator and the low order 8 bits operate as an 8 bit prescaler Figures 8 6 6 and 8 6 7 show operation examples of the 8 bit pulse width modulator Notes 1 If a value 0000 is set into the timer Aj register when the counter operates as a 16 bit pulse width modulator the pulse width modulator does not operate and the output from the TAjour pin remains L level The timer Aj interrupt request does not occur Similarly if a value 0016 is set into the high order 8 bits of the timer Aj register when the counter operates as an 8 bit pulse width modulat
186. 1 mode register L Address 1FDC 6 DMA2 mode register L Address 1 16 mode register L Address 1FFCte Number of unit transfer bits select bit 0 16 bits 1 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode Edge sense Level sense select bit Note 0 Edge sense 1 Level sense DMAACKi validity bit 0 Invalid 1 Valid Transfer source address direction select bits 00 Fixed 0 1 Forward 10 Backward 1 1 not select Transfer destination address direction select bits 00 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select Note When an external source DMAREQi is selected or when the cycle steal transfer mode is selected set this bit to 0 b0 DMAO mode register Address 1FCD16 DMA1 mode register Address 1FDD e DMA2 mode register Address 1FED 6 DMAS mode register Address 1FFD e Continue to Figure 13 5 4 on next page Transfer direction select bit Used in 1 bus cycle transfer 0 From memory to I O 1 From I O to memory 1 0 connection select bit Valid in 1 bus cycle transfer 0 Data bus Do D or Do D s 1 Data bus De Dis Transfer source wait bit Valid in DMA transfer 0 Wait 1 No wait Transfer d
187. 10N JOS S en e MoU YIM 1e uo spuedep 5906 NMd 9ui YOIYM eui 01 9 00 fumes eui 0 195 S Meqe ue ueuM O 8 S 19 S16 1 10 219 49 914 JUNOD Jo AouenbeJ 2 158 fy 0 195 8 9 20 0 49181601 01195 s 912000 49181591 fy 0 195 s 92070 uid 1nofy asind Bununoo Suelsou 50016 Q 5 o 3 5 I 25 jeubis indui s uid 21 05 1 L7 eg x 1 x 07 1 L eg w x 17 1 t gg 1 x 17 1 8 6 Pulse width modulation PWM mode bit pulse width modulator when counter value is updated during 7721 Group User s Manual Fig 8 6 7 Operation example of 8 pulse output 8 46 TIMER A 8 6 Pulse width modulation PWM mode Precautions for PWM mode 1 If the count start bit is cleared to 0 while outputting PWM pulses the counter stops counting When the TAjour pin was outputting H level at that time the output level becomes L and the timer Aj interrupt request bit is set to 1 When the TAjour pin was outputting L level the output level does not c
188. 12 4 Absolute accuracy and differential non linearity error 12 4 2 Differential non linearity error The differential non linearity error indicates the difference between the 1 LSB step width the ideal analog input voltage width while the same output code is expected to output of an A D converter with ideal characteristics and the actual measured step width the actual analog input voltage width while the same output code is output For example when 5 12 V the 1 LSB width of an A D converter with ideal characteristics is 20 mV however when the differential non linearity error is 1 LSB the actual measured 1 LSB width is 0 to 40 mV Output code A D conversion result 1 LSB width with ideal A D conversion characteristics Differential non linearity error 20 40 60 80 100 120 140 160 180 Analog input voltage mV Fig 12 4 2 Differential non linearity error 7721 Group User s Manual 12 13 A D CONVERTER 12 5 One shot mode 12 5 One shot mode In the one shot mode the operation for the input voltage from the one selected analog input pin is performed once and the A D conversion interrupt request occurs when the operation is completed 12 5 1 Settings for one shot mode Figure 12 5 1 shows an initial setting example for registers relevant to the one shot mode When using an interrupt it is necessary to set the relevant registers to enable the interrupt Refer to CHAPTER 7 INTERRUPTS for more d
189. 15 to 0 These bits can be to 000016 to Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits b7 b6 65 b4 63 62 bi 00 Timer AO mode register Address 5616 o o ojo ojo Timer 1 mode register Address 5716 i Bit Bit name Functions po e KM Fix these bits to 0 esl Count source select bits 67 06 65 b4 b3 b2 bi bO o Timer Aj mode register 2 to 4 Addresses 5816 to 5 16 6 0 Timer mode Pulse output function select bit No pulse output TAjour pin functions as a programmable 1 0 port Pulse output TAjour pin functions as a pulse output pin b4 b3 00 No gate function 01 TAji pin functions as a prog rammable 1 port 10 Counter counts only while pin s input signal is at L level 1 Counter counts only while TAjin Gate function select bits pin s input signal is at H level b7 b6 00 f2 01 fie 10 fea 11 512 7721 Group User s Manual 17 19 APPENDIX Appendix 3 Control registers Event counter mode 015 08 67 50 67 50 Timer register Addresses 4016 4C16 Timer 4 register Addresses 4Fi6 4E16 15 to 0 These bits can be set to 000016 to FFFF 6 Undefined RW Assuming that the set
190. 16 56 7721 Group User s Manual APPLICATION 16 3 Comparison of sample program execution rate 64 65 INI 66 69 69 A SOUR X SOUR X 00000011 8 A DEST X SOUR 2 X B 00001100B DEST 1 X 16 DEST 1 X A 001100008 DEST 2 X DEST 2 X LOOP1 A DEST Y 11000000 DEST 3 X 8 DEST 3 X DEST 2 Y TALIC i 16 SOUR DEST Work area Direct page area Access this area by using the following modes Direct addressing mode Direct Indexed X addressing mode Absolute Indexed Y addressing mode Fig 16 3 1 Sample program list 7721 Group Users Manual 16 57 APPLICATION 16 3 Comparison of sample program execution rate 16 3 2 Comparison between software Wait f Xw 20 MHz and software Wait Ready f Xin 25 MHz Figure 16 3 3 shows the execution time ratio when sample programs in Figure 16 3 1 are executed on the two conditions in Table 16 3 2 Figure 16 3 2 shows the memory assignment at execution rate comparison The execution time ratio depends on the program or the usage conditions Table 16 3 2 Comparison conditions Item Condition Condition Processor mode Microprocessor mode Microprocessor mode 20 MHz 25 MHz External data bus width 16 bits 16 bits Software Wait Inserted Inserted Ready Invalid Valid only for external EPROM area Program area External EPROM External E
191. 25 MHz 1 0 fea 125 kHz 250 kHz 390 625 kHz 1 1 512 15625 2 31250 Hz 48 8281 kHz 8 6 3 Trigger When a trigger is generated the TAjour pin starts outputting PWM pulses An internal or an external trigger can be selected as that trigger An internal trigger is selected when the trigger select bits bits 4 and at addresses 58 e to 5A16 are 002 or 012 an external trigger is selected when the bits are 102 or 112 A trigger generated during outputting of PWM pulses is invalid and it does not affect the pulse output operation 1 2 8 42 When selecting internal trigger A trigger is generated when 1 is written to the count start bit address 4016 When selecting external trigger A trigger is generated at the falling edge of the TAjw pin s input signal when bit 3 at addresses 5816 to 5 is 0 or at its rising edge when bit 3 is 1 However the trigger input is accepted only when the count start bit is 1 When using an external trigger set the port P5 direction registers bits which correspond to the TAjin pins for the input mode 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode 8 6 4 Operation in PWM mode When the PWM mode is selected with the operating mode select bits the TAjour pin outputs L level When trigger is generated the counter pulse width modulator starts counting and the TAjour pin outputs a PWM pulse Notes
192. 3 3 6 DMA transfer restart after termination 1 2 13 28 Restarting the same DMA transfer as the previous one from the beginning At normal and forced termination the latches of SARi DARi and TCRi maintain their values written before the transfer start Refer to Figure 13 3 4 a Therefore DMA transfer must be restarted according to the following procedures In single or repeat transfer mode Set the DMAi enable bit to 1 It is not necessary to re set the values of SARi DARi and TCRi by software Refer to Figure 13 3 4 b In array chain or link array chain transfer mode Re set the values of SARi and TCRi Set the DMAi enable bit to 1 Restarting transfer of data subsequent to one which has been transferred just before forced termination When reading values at the addresses of SARi DARi and TCRi after forced termination the values of these registers counters can be read These read values are the transfer source address the transfer destination address which were to be transferred subsequently and the number of remaining bytes When writing these read values to the addresses of SARi DARi and TCRi respectively the same values are also written to their latches When setting the DMAi enable bit to 1 under this condition transfer of data subsequent to one which has been transferred just before forced termination is restarted Refer to Figure 13 3 4 c In single transfe
193. 30 max td E CASL 77 5 tw CASL 92 5 min Lac RARAS 5 min td CA CAS 5 min Row addres Column address toEA 20 max gt tAA 35 max tozx E DLZ 20 mi td E ca 60 max gt pzx gt ASD Address Input data teLz 5 min gt tcac 20 max tsu DL E 2 30 lt gt toEZ 0 20 lt When writing gt tw EL 135 min E tw RASH 60 min tw RASL 120 min tw CASL 55 min td E CASL 80 115 id R W E 20 min AC32 tPHL gt AC32 tPHL twcs 0 tWCH 15 min gt lt td RA RAS 5 min th RAS RA 18 min Row address Column address td CA CAS 10 min th CAS CA 60 min A16 Do 23 07 Address Data lt gt tDH 15 min lt gt th E DLQ 18 min Specifications of M5M44400CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 25 Timing chart for example of M5M44400CJ 1M 4 bits connection external bus width 8 bits 7721 Group User s Manual 16 29 APPLICATION 16 1 Memory connection 6 Example of DRAM connection external bus width 16 bits M37721 M5M418160CJ 7 1 Make sure that the propagation delay time is within 20 ns Make sure that the pro
194. 32 tPHL Fig 16 1 9 Example of using Ready function no software Wait 7721 Group User s Manual 16 13 APPLICATION 16 1 Memory connection M37721 1 to 53 Make sure that the sum of propagation delay time is within 25 00 015 Data bus ns Address Address CS1 latch decode circuit circuit CS2 Address bus Validate Ready function only for areas accessed by 74 2 Circuit conditions f XIN lt 25 MHz software Wait Ready request is accepted at Termination request for Ready state is accepted at B Judgement timing of RDY pin s input level ZZ 17 level stopped by software Wait GD E 1 level stopped by Ready function 04 AC74 AC32 s th o1 RDY propagation delay time tsu RDY 61 Fig 16 1 10 Example of using Ready function software Wait 16 14 7721 Group User s Manual APPLICATION 16 1 Memory connection When data is output from external memory before falling edge of E signal Because the external memory outputs data before the falling edge of the E signal there is a possibility that the tail of address collides with the head of data In such a case generate the external memory read signal OE by using E Refer to Figure 16 1 11 External memory output enable signal Read signal Address output External memory data output el Specifications of
195. 4 4 3 show refresh delay time examples when CPU is operating and during DMA transfer For a bus request refer to 13 2 1 Bus access control circuit When the refresh request is accepted the right to use the bus is passed to DRAM refresh 1 cycle of Both of the output levels of ST1 and STO are L The bus status is indicated as 0 0 amp The RAS and the CAS signals are output and the DRAM data is refreshed refresh cycle 3 cycles of 9 The right to use the bus is passed to the CPU DRAM or Hold 1 cycle of 4 The outputs of ST1 and STO change Note In Stop or Wait mode DRAM refresh is not performed because no refresh request occurs Table 14 4 1 Delay time from when refresh request occurs until DRAM refresh is performed Source ar using bus Hort time SIDES g Minimum Maximum no Wait Maximum with Wait CPU 1 5 4 5 6 5 Transfer a unit of 1 transfer 8 5 12 5 DMAC Transfer a unit of 1 transfer Complete cycle 1 5 11 5 15 5 Array state 6 5 6 5 Hold 1 5 1 5 1 5 Note The above is applied when Ready is not used The delay time includes the time for passing the right to use buses to DRAM refresh 1 cycle 14 10 7721 Group User s Manual DRAM CONTROLLER 14 4 DRAMC operation Refresh request Bus request DRAMC Bus request sampling ST1 STO 11 CPU 00 Refresh Delay time Min 1 5 cycles of Refresh cycle Delay time Max
196. 416 b7 s priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 M xi UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 b7 no Eos Set dummy data here UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Transmit enable bit 1 Transmission enabled Receive enable bit 1 Reception enabled Note Set the receive enable bit and the transmit enable bit to 1 simultaneously Reception starts Fig 11 3 8 Initial setting example for relevant registers when receiving 2 7721 Group User s Manual 11 25 SERIAL I O 11 3 Clock synchronous serial mode When not using interrupts When using interrupts A UARTI receive interrupt request occurs when reception is completed Checking completion of reception UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 50 Receive complete flag 0 Reception not completed V 1 Reception completed X UARTi receive interrupt Reading of receive data UARTO receive buffer register Address 3616 UART1 receive buffer register Address 3E16 60 C Receive data is read out from here Che
197. 5 Port peripheral circuits 2 6 6 7721 Group User s Manual OUTPUT PINS 6 3 Examples of handling unused pins 6 3 Examples of handling unused pins When unusing an I O pin some handling is necessary for the pin Examples of handling unused pins are described below The following are just examples The user shall modify them according to the user s actual application and test them Table 6 3 1 Examples of handling unused pins Pin name Handling example to P47 P5 to P10 Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor or set these pins to the output mode and leave them open Notes 1 and 2 BLE ALE STO ST1 Leave them open Xout Note 3 HOLD RDY Connect these pins to Vcc via a resistor pull up Note 2 CNVss Connect this pin to Vcc or Vss Connect this pin to Vcc AVss VREF Connect these pins to Vss Notes 1 When leaving these pins open after they are set to the output mode note the following these pins function as input ports from reset until they are switched to the output mode by software Therefore voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports After reset immediately set these ports to the output mode Software reliability can be enhanced by setting the contents of the above ports direction registers periodically This is becau
198. 6 UART1 transmit receive control register 1 Address 3D16 b7 Pes i Overrun error flag 0 No overrun error 1 Overrun error detected Note This figure shows the bits and registers required for processing Refer Figure 11 4 12 for the change of flag state and the occurrence timing of an interrupt request Processing after reading out receive data Fig 11 4 10 Processing after receive completion 7721 Group User s Manual 11 43 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 6 Receive operation When the receive enable bit is set to 1 the UARTi enters the receive enable state After this reception starts when ST is detected and a transfer clock is generated In the case of selecting the RTS function when the reception is enabled the RTSi pin s output level becomes L to inform the transmitter side that reception is enabled When reception is started the RTSi pin s output level becomes Accordingly by connecting the RTS pin to the CTSi pin of the transmitter side the timing of transmission and that of reception can be matched Figure 11 4 11 shows an connection example The receive operation is described below The input signal of the RxDi is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock s rising edge The contents of the UARTi receive register are
199. 6 5 cycles of Refresh cycle 1 gt i i 1 5 1 1 5 1 Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus The following are internal signals Refresh request request DRAMC Bus request sampling Refresh request becomes 0 at an underflow of the refresh timer Fig 14 4 2 Refresh delay time example when CPU is operating Refresh request Bus request DRAMC Bus request sampling ST1 STO 10 DMAC 00 Refresh Delay time Max 12 5 cycles of Refresh cycle 46 5 gt 6 5 2 Transition of right to use bus The following are internal signals Refresh request request DRAMC request sampling Refresh request becomes 0 at an underflow of the refresh timer Fig 14 4 3 Refresh delay time example during DMA transfer 7721 Group User s Manual 14 11 DRAM CONTROLLER 14 5 Precautions for DRAMC 14 5 Precautions for DRAMC 1 Set the refresh timer address 66 to any of 0116 FFic 2 When a DRAM refresh request occurs during Hold state a refresh cycle is activated regardless of the bus state It is because a bus request is always sampled during Hold state Therefore in order to use the DRAMC together with the Hold function an external circuit which is controlled depending on the states of
200. 8 Link array chain transfer mode From preceding Figure 13 8 3 Selection of transfer mode and each function bo DMAO control register Address 1FCE16 control register Address 1FDE16 control register Address 1FEE 6 DMAS control register Address 1 16 b7 50 DMAO mode register L Address 1 0 DMA1 mode register L Address 1FDCie DMA2 mode register L Address 1 16 DMA3 mode register L Address 1FFCt6 Number of unit transfer bits select bit 0 16 bits 1 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer DMA request source select bits Do not select External source DMAREQi Software DMA source Timer AO Timer A1 Timer A2 Timer A3 Timer A4 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UARTI receive UART1 transmit conversion Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode 5 4 070 0 0 Edge sense Level sense select bit Note 0 Edge sense 1 Level sense DMAACKi validity bit 0 Invalid 1 Valid Transfer source address direction select bits 00 Fixed 0 1 Forward 10 Backward 1 Do not select Transfer destination address direction select bits 00 Fixed 0 1 Forward 10 Backward 1 Do not select Note When extern
201. 9 These bits are valid for the internal and external areas In the DRAM area however 1 bus cycle consumes 3 cycles of regardless of the states of these bits Refer to CHAPTER 14 DRAM CONTROLLER The wait bit bit 2 at address 5E e is invalid in DMA transfer However Ready function is still valid in DMA transfer DMAO mode register Address 1FCDte 67 66 b5 04 63 02 bi LT LL lolol mese racer faites pepe DMA3 mode eo Address 1FFD e Bitname Funcions reset RW ca direction select bit 0 From memory to ENT M Used in 1 bus cycle transfer Note 1 4 From I O to memory connection select bit Refer to below Valid in 1 bus cycle transfer Fix these bits to 0 4 Transfer source wait bit Note 2 0 Wait 1 No Wait Continuous transfer mode select b7b6 bits 0 0 Single transfer 0 1 Repeat transfer 10 Array chain transfer 1 1 Link array chain transfer Notes 1 Set bit 0 to 0 in 2 bus cycle transfer 2 Bits 4 and 5 are valid to the external and internal areas However DRAM area is always handled with Wait regardless of the contents of these bits The wait bit bit 2 at address 5 is invalid in DMA transfer Setting for I O connection select bit Transfer method External data bus width connection Setting for I O connection select bit 1 bus cycle transfer Do Dz 16 bits Do D15 16 bit 1 0 X 1 or 8 bit I O X 2 Do D7 8 bit I O Ds D15
202. 9 f512 RW bit 1 2 7 to 1 Nothing is assigned 17 28 7721 Group User s Manual APPENDIX Appendix 3 Control registers Real time output control register 67 06 65 64 b3 b2 bi 60 Real time output control register Address 6216 7 to 3 Nothing is assigned The value is 0 at reading See the following Table EN Waveform output select bits LE Note When using the pins as the pulse output pins for real time output set the corresponding bits of the port P6 direction register address 1016 to 1 P67 RTP13 7 P66 RTP 12 P6s RTP1 P64 RTP10_ P6s RTPOs gt P62 RTP02 P61 RTP0 Pey RTPO When pulse mode 0 is selected P67 RTP1s 7 P66 RTP 12 P6s RTP1 P64 RTP1o P6s RTPOs P62 RTPO2 P61 RTPO1 P60o RTPOo P67 RTP13 P66 RTP 12 P6s RTP1 64 10 P63 RTPOs P62 RTPO2 P61 RTPO1 P6o RTPOo P67 RTP13 7 P66 RTP 12 P6s RTP1 Pe4 RTP1o P6es RTPOs P62 RTPOz P6i1 RTPO1 Pulse output mode select bit 2 Pulse mode 0 Pulse mode 1 RTP gt RTP P67 RTP13 7 P6e RTP12 P6s RTP11 P64 RTP 10 P6s RTPOs P62 RTPO2_ P6 RTPO Port When pulse mode 1 is selected 66 5606664 6666 5660 Port This functions as a programmable I O port RTP This functions as a pulse output pin P67 RTP13
203. 916 Transfer counter register 2 1FEA16 1 16 1 16 DMA2 mode register L 1FED16 DMA2 mode register H 1FEE16 control register 1FEF16 1FF016 1FF116 Source address register 3 1FF216 1FF316 1FF416 1FF516 Destination address register 3 1FF616 1FF716 1FF816 1FF916 Transfer counter register 3 1FFA16 1FFB16 1FFC16 mode register L 1FFD16 mode register 1FFE16 DMAS control register 1FFF16 92 2 2 2 52 2 2 52 2 21 25 9 2 2 2 21 2 2 21 2 2 21 9 RAM area addresses 8016 to 27F 16 hardware reset Except the case where Stop or Wait mode is terminated Undefined software reset Retains the state immediately before reset At termination of Stop or Wait mode Hardware reset is used to terminate Retains the state immediately before the STP or WIT instruction is executed For the M37721S2BFP the internal RAM area can be assigned to addresses 8016 to 47F16 by setting the internal RAM area select bit bit 1 at address 5F16 Refer to section 2 4 Memory assignment Fig 4 1 9 State of SFR and internal RAM areas immediately after reset 6 4 10 7721 Group User s Manual RESET 4 1 Hardware reset 4 1 3 Internal processing sequence after reset Figure 4 1 10 shows the internal proces
204. A IMM ABS A ABS LDA LDA D LDX LDA LDY LDA A DIR A SR Y DIR Y A ABS Y ABS X A ABS X CLP CMP DEC CMP CPY CMP IMM A SR DIR A IMM ABS A ABS CMP CMP DEC CMP JMP CMP A DIR A SR Y DIR X AL DIR 5 L ABS A ABS X SEP SBC INC BC SBC SBC IMM A SR DIR DIR A IMM ABS A ABS SBC SBC INC BC SBC JSR SBC A DIR A SR Y A DIR X DIR X A ABS Y 5 5 Notes 1 4216 specifies the contents of the INSTRUCTION CODE TABLE 2 About the second word s codes refer to the INSTRUCTION CODE TABLE 2 2 8916 specifies the contents of the INSTRUCTION CODE TABLE 3 About the second word s codes refer to the INSTRUCTION CODE TABLE 2 17 56 7721 Group User s Manual APPENDIX Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 2 The first word s code of each instruction is 4216 0000 0001 0101 0110 1010 1011 Hexadecimal notation ORA ORA ORA B DIR B IMM B ABS ORA ORA ORA B DIR X 5 5 AND AND B DIR B IMM B ABS AND AND AND BDIRX B ABS Y B ABS X EOR EOR B IMM B ABS EOR EOR 5 5 ADC ADC B IMM B ABS ADC ADC 5 5 STA B ABS STA STA B ABS Y 5 LDA LDA B IMM B ABS LDA LDA B DIR X 5 5
205. ADVANCED AND EVER ADVANCINGMITSUBISHI ELECTRIC MITSUBISHI 16 BIT SINGLE CHIP MICROCOMPUTER 7700 FAMILY 7700 SERIES MITSUBISHI ELECTRIC keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials information contained in these materials including product data diagrams and charts represent information on products at the time
206. AL input low level pulse width 80 ns Timer A input External trigger input in pulse width modulation mode Limits Symbol Parameter Min Max Unit tw TAH TAjin input high level pulse width 80 ns tw TAL input low level pulse width 80 ns Timer A input Up down input in event counter mode Limits Symbol Parameter Win oo tc UP TAjour input cycle time 2000 ns tw UPH TAjout input high level pulse width 1000 ns tw UPL TAjout input low level pulse width 1000 ns tsuuP ry TAjout input setup time 400 ns input hold time 400 ns Timer A input Two phase pulse input in event counter mode Limits Symbol Parameter Min Max nit te TA TAjin input cycle time 800 ns tsu TAjin TAjout TAjin input setup time 200 ns tsutajour tain TAjour input setup time 200 ns 7721 Group User s Manual 17 83 APPENDIX Appendix 11 Electrical characteristics Internal peripheral devices Count input in event counter mode Gating input in timer mode External trigger input in one shot pulse mode External trigger input in pulse width modulation mode input Up down input and count input in event counter mode TAjour input Up down input TAjour input Up down input input When counted at falling edge th Tin UP tsu UP Tin gt TAjin input When counted at rising edge Two phase pulse input in event counter mod
207. AREQ3 pin Clear the corresponding bit to 0 Continue to Figure 13 6 3 on next page Fig 13 6 2 Initial setting example for registers relevant to repeat transfer mode 1 7721 Group User s Manual 13 63 DMA CONTROLLER 13 6 Repeat transfer mode From preceding Figure 13 6 2 gt Selection of transfer mode and each function E b7 DMAO mode register L Address 1FCC s DMAO control register Address 1FCE 6 DMA1 mode register L Address 1FDC16 DMA1 control register Address 1FDE 6 mode register L Address 1FEC16 control register Address 1 16 DMA mode register L Address 1FFC16 DMAS control register Address 1FFE16 Number of unit transfer bits select bit 0 16 bits 1 8 bits Do not select External source DMAREQi Transfer method select bit Software DMA source 0 2 bus cycle transfer Timer AO 1 1 bus cycle transfer Timer 1 Timer A2 Transfer mode select bit Timer 0 Burst transfer mode Timer A4 1 Cycle steal transfer mode DMA request source select bits Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UART1 receive UART1 transmit conversion 4444ucg000 Transfer source address direction select bits
208. ARI DARI and TCRi Except for the first transfer of the block the values read from SARI DAR and TCRi are used Fig 13 4 2 Basic operation of registers for 1 unit transfer in 2 bus cycle transfer 7721 Group User s Manual 13 31 DMA CONTROLLER 13 4 Operation 2 Bus operation in 2 bus cycle transfer The time required for 1 unit transfer in 2 bus cycle transfer is given by the following formula Transfer time per 1 unit transfer Read cycle Write cycle Since any area can be specified as a transfer source or a transfer destination a read cycle varies with the conditions of a transfer source and a write cycle with that of a transfer destination Table 13 4 1 lists the time required for a read or write cycle per 1 unit transfer in 2 bus cycle transfer and Figure 13 4 3 shows the bus cycle operation waveforms in 2 bus cycle transfer Table 13 4 1 Time required for a read or write cycle per 1 unit transfer in 2 bus cycle transfer External Transfer Address directions Data s start Read Write cycle Unit cycle bus width unit address Formula No Wait With Wait DRAM area 16 bits 16 bits Fixed Forward Even 1 i 2 a 3 d including Odd 2 2i 4 c 6 f internal Backward Even 2 2i 4 6 f bus Odd 2 i 3 b 4 e 4 Note 8 bits Fixed Forward Even Odd 2 3 Backward 8 bits 16 bits Fixed Forward Even Odd 2 2i 4 6 f Backward 8 bits Fixed Forwar
209. According to the information of each block stored in memory area Note several blocks of data are transferred All of the transfer parameters must be located in series Table 13 7 1 lists the specifications of the array chain transfer mode and Figure 13 7 1 shows the register structures of SARi DARi and TCRi in this mode Note Each of the following information is called transfer parameter transfer start addresses of transfer source and destination and transfer data s byte number Table 13 7 1 Specifications of array chain transfer mode Item Transfer parameter memory Performance specifications Required In 2 bus cycle transfer 12 bytes per one block transfer source s transfer start address transfer destination s transfer start address transfer data s byte number n 1 bus cycle transfer 8 bytes per one block from memory to I O transfer source s transfer start address transfer data s byte number from I O to memory transfer destination s transfer start address transfer data s byte number Condition of normal termination TCRi latch 2 0 and TCRi 2 0 Conditions of forced termination Falling edge of the input from to L when the TC pin validity bit 1 Write 0 to the DMAi enable bit Interrupt request generation timing At normal termination Functions of registers SARi latch Indicates the transfer parameter memory s start address of the
210. All except the following After completion of 1 unit transfer Link At the end of each block Bi During transfer in burst transfer mode Note 1 except the last block After the last 1 unit transfer of 1 block the subsequent 3 cycles of 0 and a read of the first 2 bytes in the array state of the next block are performed sequentially During transfer in cycle steal transfer mode After the last 1 unit transfer of 1 block and the subsequent 3 cycles of are performed sequentially At the end of the last block 1 unit transfer and terminate processing 3 cycles of are performed sequentially At an array state After a read of 2 bytes of a transfer parameter CPU When an instruction is After completion of 1 bus cycle fetched into queue buffer At a read from or a write into After completion of 1 bus cycle or after completion of memory the second bus cycle if a 16 bit data is accessed in a unit of 8 bits Note 2 While CPU does not use bus Every 1 cycle of Notes 1 S Single transfer mode R Repeat transfer mode Array Array chain transfer mode Link Link array chain transfer mode 2 This applies when the data bus width is 8 bits or when memory is accessed starting at an odd address If a DRAM refresh request or a Hold request is generated during a data transfer in the burst transfer mode the request is accepted at the above mentioned bus request sampling Another DMA request including that of other channels cannot be acc
211. C32 tPHL twcs 0 min gt lt twCH 10 min gt th RAS RA 18 m it td R W E 20 min td RA RAS 5 min lt 9 Row address Column address lt gt lt td CA CAS 10 min th CAS CA 60 min Ai6 Do r gt tDH 15 min lt gt th E DLQ 18 Specifications of M5M417800CJ 7 The others are specifications of M37721 Fig 16 1 23 Timing chart for example of M5M417800CJ 2M X 8 bits connection external bus width z 8 bits 7721 Group User s Manual 16 27 APPLICATION 16 1 Memory connection 5 Example of DRAM connection external bus width 8 bits M37721 M5M44400CJ 7 Make sure that the propagation delay time is within 80 ns BR gt 00008016 Internal 00047 16 RAM area 00000016 oN A A A A 5 A16e Do 17 01 A18 D2 A19 D3 A20 D4 M5M44400CJ A21 D5 22 06 23 07 XOUT Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 24 Example of M5M44400CJ 1M X 4 bits connection external bus width 8 bits 16 28 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E _ OE tw EL 135 min tw RASL 120 min tw RASH 60 min 1d RAS CAS 28 min td E RASL
212. CR2 Transfer counter register Addresses 1FFA e to 1 816 TCR3 Set the dummy data These bits can be set 00000116 to FFFFFF e m Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi Fig 13 8 4 Initial setting example for registers relevant to link array chain transfer mode 2 7721 Group User s Manual 13 85 DMA CONTROLLER 13 8 Link array chain transfer mode From preceding Figure 13 8 4 Selection of priority level and TC pin and setting DMAi request bit to 0 b7 bO 0 0 0 0 control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P10s pin functions as a programmable 1 O port 1 Valid EN P105 pin functions as TC pin request bit request bit DMA2 request bit request bit 0 No request DMAC control register Address 6916 Software DMAi request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit enable bit Di enable bit enable bit S a When selecting external When selecting internal When selecting internal DMA DMA sou
213. Control registers Timer Bi register b15 b8 b7 50 b7 50 Timer BO register Addresses 5116 5016 i Timer B2 register Addresses 5516 5416 15 to 0 These bits have different functions according Undefined RW to the operating mode Note 1 Notes 1 The access characteristics for the timer BO register and timer B1 register differ according to Timer B s operating mode 2 Read from or write to this register in a unit of 16 bits Timer Bi mode register b7 06 b5 64 b3 b2 bi 60 BEEN Timer Bi mode register i 0 to 2 Addresses 5 to 5016 w mmm eme 1 Operating mode select bits Timer mod Event counter mode 1 Pulse period Pulse width SUP measurement mode Do not select ww ing i i 3 Undefined lille i i i i Undefined RO Note sme Note Bit 5 is invalid in the timer and event counter modes its value is undefined at reading 7721 Group User s Manual 17 23 APPENDIX Appendix 3 Control registers Timer mode b15 b8 b7 50 07 bO Timer BO register Addresses 5116 5016 L Timer 1 register Addresses 531s 52w Timer B2 register Addresses 5516 5416 15 to 0 These bits be set 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register in
214. D trigger input Limits Symbol Parameter Min Max Ut tean ADrrc input cycle time trigger enabled minimum 1000 ns tw ADL input low level pulse width 125 ns Serial I O Limits Symbol Parameter Wim Tras CLKi input cycle time 200 ns tw CkH CLKi input high level pulse width 100 ns CLKi input low level pulse width 100 ns ta c a TxDi output delay time 80 ns thic a TxDi hold time 0 ns tsu D c RxDi input setup time 20 ns th c D RxDi input hold time 90 ns External interrupt INTi input Limits Symbol Parameter Mia rax tw INH INTi input high level pulse width 250 ns twin INTi input low level pulse width 250 ns 7721 Group User s Manual 17 85 APPENDIX Appendix 11 Electrical characteristics Internal peripheral devices TBjin input ADrno input CLKi input TxDi output 0 RxDi input input Test conditions Vcc 25V 10 timing voltage 1 0 V 4 0 V Output timing voltage 0 8 V 2 0 V 17 86 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Ready and Hold Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xw 25 MHz unless otherwise noted Limits Symbol Parameter Min Max unit tsuRDy 1 RDY input setup time 55 ns lsuroto o I HOLD input setup time 55 ns _
215. DIX Appendix 9 7721 Group Q amp A Watchdog timer When detecting the software runaway by the watchdog timer if the same value as the contents of the reset vector address is set to the watchdog timer interrupt vector address not performing software reset how does it result in When branching to the reset branch address within the watchdog timer interrupt routine how does it result in The CPU registers and the SFR are not initialized in the above mentioned way Accordingly the user must initialize all of them by software Note that the processor interrupt priority level IPL retains 7 of the watchdog timer interrupt priority level and is not initialized Consequently all interrupt requests cannot be accepted When rewriting the IPL by software save once the 16 bit immediate value to the stack area and then restore that 16 bit immediate value to all bits of the processor status register PS When a software runaway occurs we recommend to use software reset in order to initialize the microcomputer 17 78 7721 Group User s Manual APPENDIX Appendix 10 Differences between 7721 Group and 7720 Group Appendix 10 Differences between 7721 Group and 7720 Group Table 2 Differences between M37721S2BFP and M37720S1AFP Item M37721S2BFP M37720S1AFP Internal RAM size 1024 bytes Note 512 bytes External clock input frequency 25 MHz maximum 16 MHz maximum Instruction execution time minimum 160 ns 250 n
216. DMAi request bit Transfer completion of all blocks SARi latch 0 2 0 Burst Level H Cycle steal No request Y Completion TC L output Note request bit interrupt request bit lt 1 enable bit 0 0 Note When TC pin validity bit is 1 Burst Level H Cycle steal No request request bit 0 Only in burst transfer mode edge sense Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREQi pin s input level L Burst Level H In burst transfer mode level sense with DMAREQi pin s input level H Cycle steal Requested In cycle steal transfer mode with any request of DMA0 3 Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 SARi latch indicates the start address of the transfer parameter memory of the next block Note The above figure applies when 2 bus cycle transfer is performed When data is transferred from memory to I O in 1 bus cycle transfer there is DARic Transfer parameter When data is transferred from I O to memory in 1 bus cycle transfer there is SARi Transfer parameter Fig 13 8 6 Operation flowchart of link array chain transfer mode 13 88 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode peideooe si pue 41 s 1senbai snq eui aym pejdures si pjoH 10 useJjeJ Aq pesneo jsanb
217. DRAM 1 Refresh method of the M37721 s DRAMC is the dispersion refresh and 5 cycles of necessary for one refresh The rate occupied by the DRAM refresh cycle during the program execution time is described below Rate occupied by DRAM refresh cycle during program execution time Rate occupied by DRAM refresh cycle f Xw 25 MHz 16 MHz Refresh interval 15 625 us Case of 512 refresh cycles every 8 ms 125 us Case of 512 refresh cycles every 64 ms 2 The comparison results of two sample programs execution times are listed below one is for the case where SRAM is used and the other is for the case where DRAM is used Use conditions Execution program Sample program B See 2 2 16 MHz External data bus width 16 bits Refresh interval 13 us Memory used as work area Software wait valid area Execution time Speed comparison SRAM Nothing 3 4 ms 1 00 SRAM ROM and RAM 5 0 ms 1 47 DRAM bank FF e Nothing 3 9 ms 1 15 DRAM bank FF e ROM 5 2 ms 1 53 17 76 7721 Group User s Manual APPENDIX Appendix 9 7721 GroupQ amp A DRAM Sample program B SEP X CLM DATA 16 INDEX 8 LDY 69 LDX 69 ASL SOUR X SEM DATA 8 ROL SOUR 2 X ROL B CLM DATA 16 ROR A DEX DEX DEX BNE LOOP1 STA A DEST Y SEM DATA 8 STA B DEST 2 Y CLM DATA 16 DEY DEY DEY BNE SOUR DEST Work areas 7721 Group User s Manual 17 77 APPEN
218. ER B Timer B1 6 FFE2 6 Timer B2 FFE1 6 FFEO0 e UARTO receive FFDF e FFDEis Maskable internal interrupts 11 SERIAL UARTO transmit FFDDie FFDCte UART1 receive FFDBie FFDAi6 UART1 transmit FFD9 e FFD816 A D conversion FFD7 6 FFDe _ internal interrupt 12 A D CONVERTER DMAO 2205 2204 Maskable internal interrupts 13 CONTROLLER DMA1 FFD3 e FFD2 e DMA2 FFD1 6 FFDO e DMAS3 FFCF e FFCEte Note The DBC interrupt is used exclusively for debugger control eMaskable interrupt An interrupt of which request s acceptance can be disabled by software Non maskable interrupt including Zero division BRK instruction Watchdog timer interrupts An interrupt which is certain to be accepted when its request occurs These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag 1 7721 Group User s Manual INTERRUPTS 7 3 Interrupt control 7 3 Interrupt control The maskable interrupts are controlled by the following Interrupt request bit Interrupt priority level select bits Processor interrupt priority level IPL Assigned to the processor status register PS Interrupt disable flag 1 Assigned to the interrupt control register of each interrupt Figure 7 3 1 shows the memory assignment of the interrupt control registers and Figure 7 3 2 shows their structures Address Fig 7 3 1 Memory assignment of interrupt control
219. FF e Read After a value is written to this register and until transfer starts the read value indicates the written value the start address of the transfer parameter memory of block which is first transferred After transfer starts the read value indicates the Source address of data which is next transferred Note When writing to this register write to all 24 bits b16 015 Destination address register 1 Addresses 1FD616 to 1 416 DAR1 Destination address register 2 Addresses 1 16 to 1FE416 DAR2 Destination address register 3 Addresses 1FF616 to 1FF416 DAR3 Need not to be set 23 to 0 Read Undefined RW After transfer starts the read value indicates the Destination address register 0 Addresses 1FC616 to 1 416 DARO destination address of data which is next transferred b16 b15 Transfer counter register 0 Addresses 1FCAte to 1 816 TCRO Transfer counter register 1 Addresses 1FDAte to 1FD816 TCR1 Transfer counter register 2 Addresses 1 16 to 1 816 TCR2 Transfer counter register 3 Addresses 1FFAte to 1FF816 TCR3 Write Set the dummy data RW These bits can be set to 00000116 to Read After a value is written to this register and until transfer starts the read value indicates the written value dummy data After transfer starts the read value indicates the remaining byte number of the block which is be
220. Family Software Manual for addressing modes 2 1 3 Index register Y Y Index register Y is a 16 bit register with the same function as index register X Just as in index register X the index register length flag x determines whether this register is used as a 16 bit register or as an 8 bit register In the MVP or MVN instruction a block transfer instruction the contents of index register Y indicate the low order 16 bits of the destination address The second byte of the instruction is the high order 8 bits of the destination address 7721 Group User s Manual 2 3 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 4 Stack pointer S The stack pointer S is a 16 bit register It is used for a subroutine call or an interrupt It is also used when addressing modes using the stack are executed The contents of S indicate an address stack area for storing registers during subroutine calls and interrupts Stack area is selected by the stack bank select bit described later bit 7 at address 5 The stack area is specified to bank 0 when the stack bank select bit is 0 and the stack area is specified to bank FF ewhen it is 1 When an interrupt request is accepted the microcomputer stores the contents of the program bank register PG at the address indicated by the contents of S and decrements the contents of S by 1 Then the contents of the program counter PC and the processor status register PS are
221. From preceding Figure 13 6 3 of priority level and TC pin and setting DMAi request bit to 0 b7 DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P105 pin functions as a programmable I O port 1 Valid mJ P105 pin functions as TC pin DMAO request bit request bit request bit DMAS request bit 0 No request 22 Note When the burst transfer mode edge sense is selected set bit 1 to 1 DMAC control register H Address 6916 Software request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit enable bit Di DMA2 enable bit enable bit Ns When selecting external When selecting internal When selecting internal DMA DMA source DMA source Source except software ERFEEREERRERERERRERERERRRERRERRRERRERRRRERRRRERRERERERERRARERRERRERRERERRERRERERERRRRRERRERERRERRERERRERRERRERRERRERERR When selecting software DMA request N Interrupt request of each peripheral DMAC control register H Address 6916 function occurs nputting DMA request signal to DMAREQi pin Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit Software DMA request bit
222. Functions Indicates the storage address for the instruction which is next taken into the instruction queue buffer Program address register Instruction queue buffer Data address register Data buffer Temporarily stores the instruction which has been taken in Indicates the address for the data which is next read from or written to Temporarily stores the data which is read from the memorysl O device by the BIU or which is written to the memory l O device by the CPU 7721 Group User s Manual 2 11 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit The CPU and the bus send or receive data via BIU because each operates based on different clocks Note The BIU allows the CPU to operate at high speed without waiting for access to the memory I O devices that require a long access time The BIU s functions are described bellow Note The CPU operates based on cPU The period of CPU is normally the same as that of 9 The internal 1 2 3 4 bus operates based on the E signal The period of the E signal is twice that of at a minimum Reading out instruction Instruction prefetch When the CPU does not require to read or write data that is when the bus is not in use the BIU reads instructions from the memory and stores them in the instruction queue buffer This is called instruction prefetch The CPU reads instructions from the instruction queue buffer and executes them so that the CPU ca
223. Group User s Manual CHAPTER 18 DMA CONTROLLER 13 1 Overview 13 2 Block description Precautions for DMAC 13 3 Control 13 4 Operation Precautions for 2 bus cycle transfer Precautions for 1 bus cycle transfer Precautions for burst transfer mode Precautions for cycle steal transfer mode 13 5 Single transfer mode 13 6 Repeat transfer mode 13 7 Array chain transfer mode Precautions for array chain transfer mode 13 8 Link array chain transfer mode Precautions for link array chain transfer mode 13 9 DMA transfer time DMA CONTROLLER 13 1 Overview 13 1 Overview The DMA controller hereafter called DMAC transfers data using the bus and bypassing the CPU DMAC of the M37721 provides four independent channels of which have the same function each In this chapter the source and destination of each DMA transfer are represented as follows e Memory A device which needs its own address to be specified Examples Internal RAM and SFRs external memory and memory mapped l Os e 1 0 A device which does not need its own address to be specified Example External I O devices 13 1 1 Performance overview Table 13 1 1 lists the performance overview Table 13 1 1 DMAC performance overview Item Performance specifications 4 channels 16 Mbytes between arbitrary spaces Maximum of 16 Mbytes Number of channels Transfer space Number of transfer bytes
224. Hz 9 22 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 3 Operation in pulse period pulse width measurement mode When the count start bit is set to 1 the counter starts counting of the count source The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected Refer to section 1 Pulse period Pulse width measurement The counter value is cleared to 000016 after the transfer in and the counter continues counting The timer Bj interrupt request bit is set to 1 when the counter value is cleared to 000016 Note The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software The timer repeats operations to above Note No timer Bj interrupt request occurs when the first valid edge is input after the counter starts counting 1 Pulse period Pulse width measurement The measurement mode select bits bits 2 and at addresses 5B e and 5C e specify whether the pulse period of an external signal is measured or its pulse width is done Table 9 5 3 lists the relationship between the measurement mode select bits and the pulse period pulse width measurements Make sure that the measurement pulse interval from the falling edge to the rising edge and vice versa are two cycles of the count source
225. L Bit 9 in processor status register PS IPL2 Bit 10 in processor status register PS 7721 Group User s Manual INTERRUPTS 7 4 Interrupt priority level 7 4 Interrupt priority level When the interrupt disable flag 1 0 interrupts enabled and more than one interrupt request is detected at the same sampling timing which means a timing to check whether an interrupt request exists or not they are accepted in order of priority levels In other words the interrupt request with the highest priority level is accepted first Among a total of 23 interrupt sources the user can set the desired priority levels for 20 interrupt sources except software interrupts zero division and BRK instruction interrupts and the watchdog timer interrupt Use the interrupt priority level select bits to set their priority levels Priority levels of reset which is handled as the interrupt request with the highest priority and the watchdog timer interrupt are set by hardware Figure 7 4 1 shows the interrupt priority set by hardware Note that software interrupts are not affected by the interrupt priority levels Whenever the instruction is executed a program certainly branches to the interrupt routine gt LT 550545255256 gt 20 interrupt sources except software interrupts Priority levels determined by hardware and watchdog timer interrupt The user can set the desired priority levels inside of the dotted line Priority level High Fi
226. L level to HOLD pin while bus is used when data access is completed with continuous 2 bus cycle State when inputting L level to HOLD pin External data bus Data length External data bus width 8 Used 16 16 Access beginning at odd address Clock 1 Note 2 Address Address 1 a XC 9 External address bus Floating BLE BHE HOLD Bus request Hold Note 3 Bus request sampling Note 3 Hold state cH Bus in use Businuse Transfer of right Transfer of right to use bus to use bus When a Hold request is accepted not a new address but the address which was output immediately before is output again Notes 1 The above diagram shows the case of 2 access in low speed running 2 Clock 1 has the same polarity and the same frequency as 6 Timing of signals to be input from or output to the external is ordained on the basis of clock 3 Bus request Hold and bus request sampling are internal signals Fig 3 4 3 Timing of acceptance of Hold request and termination of Hold state 3 7721 Group User s Manual 3 15 CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function Precautions for Hold function When a DRAM refresh request occurs in Hold state DRAM refresh is performed immediately because the bus use priority level of DRAM refresh is higher than that of Hold function 3 16 7721 Group User s Manual
227. L tPLH tPHz tPLz Data output B from external memory AC245 Unit ns Fig 16 1 13 Timing chart for circuit example using bus buffers 1 7721 Group User s Manual 16 17 APPLICATION 16 1 Memory connection M37721 Address bus LE OE 245 08 15 015 Data bus odd DIR OC AC245 A16 Do A23 D7 A B Data bus even DIR OC These circuits make the occurrence of the L 1 write signal s rising edge earlier by 1 2 61 so that the write hold time is extended Circuit condition Software Wait 1 Make sure that the propagation delay time is within 20 ns 2 Make sure that the output disable time is within 20 ns Fig 16 1 14 Example for using bus buffers 2 connecting with memory requiring long data hold time for writing 16 18 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt tw EL 135 min E OC AC245 tpzx E DLZ DHZ 20 min As Ds A15 D15 A16 Do A23 D7 AC32 tPHL AC32 tPLH RD Data output A from tPZH tPZL tPHz tPLz external memory AC245 lt When writing gt A Cu T EG UN GL P tw EL 135 min AC04 tPLH AC74 tPLH AC32 X 2 tPLH WO WE As Ds A15 D15 A16 Do A23 D7 tPHz tPLz Data output B from external memory AC245 Write hold time Unit ns Fig 16 1 15
228. M time select bits 4 cycles of This bit is 1 at reading i 2 Wait bit 0 Software Wait is inserted when accessing external area i 1 No software Wait is inserted i when accessing external area Software reset bit The microcomputer is reset by writing 1 to this bit The value of this bit is 0 at reading 100 2 cycles of Do not select Fix this bit to 0 7 Stack bank select bit 0 Bank O16 1 Bank FF e Bits 0 to 2 and bits 4 to 7 are not used for software reset Fig 4 2 1 Structure of processor mode register 0 7721 Group User s Manual 4 13 RESET 4 2 Software reset When the software reset bit is set to 1 the RESETour pin s output level becomes L In a period of 4 5 cycles of clock 6 after the software reset bit is set to 1 the RESETour pin s output level is L Figure 4 2 2 shows the RESETour output timing at software reset ye Set software reset bit to 1 RESETout Fig 4 2 2 RESETour output timing 4 14 7721 Group User s Manual CHAPTER 5 CLOCK GENERATING CIRCUIT 5 1 Oscillation circuit examples 5 2 Clocks 5 3 Stop mode Precautions for Stop mode 5 4 Wait mode Precautions for Wait mode CLOCK GENERATING CIRCUIT 5 1 Oscillation circuit examples 5 1 Oscillation circuit examples To the oscillation circuit a ceramic resonator or a quartz crystal oscillator
229. M controller refer to CHAPTER 14 DRAM CONTROLLER 3 1 1 Descriptions of signals Figure 3 1 1 shows the pin configurations when the external data bus width is 16 bits and 8 bits 1 External buses As Des A s Dis 16 0 23 07 The external area is specified by the address Ac Azs output The As Azs pins of the external address bus and the Do Dis pins of the external data bus are assigned to the same pins When the BYTE pin level described later is L external data bus width is 16 bits the As Ds Ais Dis and Ase Do Aezs D pins perform address output and data input output with time sharing When the BYTE pin level is external data bus width is 8 bits the A e Do Aes D pins perform address output and data input output with time sharing and the 5 pins output the address 2 External data bus width switching signal BYTE pin level This signal is used to select the external data bus width from 8 bits and 16 bits The width is 16 bits when the level is L and 8 bits when the level is H Fix this signal to either H or L level This signal is valid only for the external area When accessing the internal area the data bus width is always 16 bits 3 Enable signal E This signal becomes L level while reading or writing data from and to the data bus Refer to Table 3 1 1 4 Read Write signal R W This signal indicates the state of the data bus This
230. Note 70LL 70XL M5M5278DP J 12 6 ns M5M5278DP FP J 15 15L 7 ns M5M5278DP FP J 20 20L 8 ns Note tor or listed above is guaranteed when these memory chips are connected with the M37721 When the user wants specifications of these memory chips add a comment 15 ns microcomputer and kit 7721 Group User s Manual 16 15 APPLICATION 16 1 Memory connection M37721 Address bus LE AC245 4 As Ds A15 D15 A B Data bus odd DIR OC AC245 2 A Data bus even O F A16 Do A23 D7 3 2 Circuit condition Software Wait 321 Make sure that the propagation delay time is within 20 ns 2 3 Make sure that the sum of output disable time in 2 and propagation delay time 3453 is within 20 ns x4 Make sure that the propagation delay time is within 15 ns Fig 16 1 12 Example of using bus buffers 1 16 16 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt 135 min tpzx E DLZ DHZ 20 min As Ds Ai5 D15 A16 Do A23 D7 AC32 tPHL AC32 tPLH OC AC245 RD 245 245 Data output A from tPZH tPZL tPHz tPLz external memory AC245 lt When writing gt twEL 135 min td E DLQ DHQ 35 max As Ds A15 D15 Ase Do Aes D7 roc ru SAUA AC32 tPHL gt AC32 teLH OC AC245 WO WE AC245 AC245 tPH
231. O transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 16 Transmit data is set L 15 to 9 Nothing is assigned Note Use the LDM or STA instruction for writing to this register UARTI transmit receive control register 0 b7 b6 b5 b4 63 62 bi UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C 6 p BRG count source select bits b1 b0 00 fe 01 16 i 164 1512 Wo CTS RTS select bit CTS function selected RTS function selected M Transmit register empty flag 0 Data present in transmit register During transmission 1 No data present in transmit register Transmission completed I E Nothing is assigned 17 14 7721 Group User s Manual APPENDIX Appendix 3 Control registers UARTI transmit receive control register 1 67 b6 b5 64 b3 62 bi transmit receive control register 1 Address 3516 transmit receive control register 1 Address 3016 Functions At reset reset RW EX enable bit eu E Transmission disabled Transmission enabled Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Receive enable bit i Reception disabled Reception enabled Receive complete flag 0 No data pre
232. OCK GENERATING CIRCUIT 5 3 Stop mode Stop mode Interrupt request used to terminate Stop mode Interrupt request bit 4 gt 16 ii Value of Watchdog timer CPU Operating Stopped Stopped Operating Internal peripheral devices Operating Stopped Operating Operating ZEN LN STP instruction lnterrupt request used to 6 Watchdog timer s MSB 0 is executed terminate Stop mode However watchdog timer interrupt occurs request does not occur Oscillation starts When Supply of cpu starts an external clock is input lnterrupt request which has been used from the Xin pin clock to terminate Stop mode is accepted input starts e Watchdog timer starts counting Fig 5 3 1 Stop mode terminating sequence by interrupt request occurrence 2 Termination by hardware reset Supply L level to the RESET pin by using the external circuit until the oscillation of the oscillator is stabilized The CPU and the SFR area are initialized in the same way as system reset However the internal RAM area retains the same contents as that before executing the STP instruction The terminating sequence is the same as the internal processing sequence which is performed after reset Refer to CHAPTER 4 RESET for details about reset 7721 Group User s Manual 5 7 CLOCK GENERATING CIRCUIT 5 3 Stop mode Precautions for Stop mode When executing the STP instruction
233. PC P RPE R PRPC EEE EEEE EEE EEEE EEE EE When selecting software DMA request Interrupt request of signal to DMAREQi pin each peripheral Inputting DMA request 5 DMAC control register H Address 6916 function occurs Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit Software DMAG request bit bs Requested When writing 1 DMA request is generated DMA transfer starts Fig 13 5 4 Initial setting example for registers relevant to single transfer mode 3 13 58 7721 Group User s Manual DMA CONTROLLER 13 5 Single transfer mode 13 5 2 Operation in single transfer mode Figure 13 5 5 shows the operation flowchart of the single transfer mode and Figure 13 5 6 shows a timing diagram of the single transfer mode burst transfer mode For the cycle steal transfer mode refer to the following All transfers except for the last 1 unit transfer Figure 13 8 12 Last 1 unit transfer Figure 13 8 14 Also refer to section 13 2 1 Bus access control circuit for the bus request sampling during transfer request bit lt 0 Only in cycle steal transfer mode 1 unit transfer Refer to section 13 4 Operation Transfer completion of 1 block Burst Edge Burst Level L Cycle steal Requested DMAi request bit TC L output Note interrupt request bit lt 1 enable bit lt 0 0 Burst Level H Cycle
234. PROM Work area Internal or External SRAM Internal or External SRAM M37721 memory map SFR area Internal SRAM External SRAM Area where software 4 Wait is valid Program area External EPROM Specify either area as work area Condition Ready valid area Insert Wait which is equivalent to 2 cycles of at access Software Wait included Fig 16 3 2 Memory assignment at execution rate comparison 16 58 7721 Group User s Manual APPLICATION 16 3 Comparison of sample program execution rate Figure 16 3 3 shows that there is almost no difference between conditions and 2 about the execution time The bus buffers become unnecessary when using the specified memory Refer to Table 16 1 6 Considering this the case where software Wait is inserted with f Xin 20 MHz condition is superior in the cost performance Sample A excution time ratio Sample B excution time ratio Work area Internal RAM Work area External RA Work area Internal RAM Work area External RAM Condition L Condition Fig 16 3 3 Execution time ratio 7721 Group User s Manual 16 59 APPLICATION 16 3 Comparison of sample program execution rate MEMORANDUM 16 60 7721 Group User s Manual Appendix 1 Appendix 2 Appendix 3 Appendix 4 Appendix 5 Appendix 6 Appendix 7 Appendix 8 Appendix 9 App
235. RDY input hold time 0 ns thi Hoto HOLD input hold time 0 ns Switching characteristics Vcc 5 V 10 96 Vss 0 V Ta 20 to 85 C f Xw 25 MHz unless otherwise noted Limits Symbol Parameter Win Max Unit tagi st STO output delay time 40 ns Note Figure 13 shows the test circuit 7721 Group User s Manual 17 87 APPENDIX Appendix 11 Electrical characteristics Ready function With no Wait 1 E output RDY input tsu RDY 61 th o1 RDY With Wait 1 E output RDY input tsu RDY 61 th o1 RDY AE Test conditions Vcc 2 5V 10 Input timing voltage 1 0 V 4 0 V Output timing voltage 0 8 V 2 0 V Hold function tsu HOLD 1 th o1 HOLD HOLD input ta o1 STi ta o1 STi e gt STi output Test conditions Vcc 25V 10 96 Input timing voltage 1 0 V Viu 4 0 V Output timing voltage 0 8 V 2 0 V 17 88 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with no Wait Note The limits depend on f Xin Table 4 lists calculation formulas for the limits Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted
236. Real time output control register Address 6216 Pulse mode 0 bO Timer AO register Addresses 4716 4616 L First step time b7 50 Count start register Address 4016 Timer AO count start b7 bO DMAC control register L Address 68 6 DMA1 request bit t to 0 DMA2 request bit b7 bO DMAC control register H Address 6916 1 enabled enabled X It may be 0 or 1 Fig 16 2 10 Initial setting example for relevant register 3 16 52 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller 16 2 3 Example of dynamic lighting for LED The following is an example of dynamic lighting for LED by using DMA3 and Timer BO 1 Specifications The eight 7 segment LEDs are lighted up port P6 outputs the segment data port P7 outputs the digit data Refer to Figure 16 2 11 The display data and the segment data are transferred from the data buffer to the port P6 and P7 registers by Digit switch interval is generated by Timer BO 16 bytes of RAM are used as the data buffer 1 digit display data consists of 2 bytes the digit data is placed in the high order byte the segment data is placed in the low order byte Refer to Table 16 2 2 When the digit data and segment data are 0 the LED is lighted up ON when they are 1 the light goes o
237. Setting pulse output mode N b7 50 0 0 Real time output control register Address 6216 7 pins functions as the programmable I O port Pulse output mode select bit 0 Pulse mode 0 V 1 Pulse mode 1 di When pulse mode 0 is selected PEPPER eee When pulse mode 1 is selected Setting output data oe output data UN b7 bo b7 b0 Pulse output data register 0 x x Pulse output data register 0 Address 116 Address 1 6 RTPOo RTPOo 0 L level ____ RTPO0 1 H level gt 0 L level 1 H level X It may be either 0 or 1 bO Pulse output data register 1 Pulse output data register 1 Address 1 16 Address 1C16 RTPO2 RTPOs 25 RTP11 RTP1o 17 L level 0 L level level RTP12 level RTP 11 1 RTP12 RTP1s X It may be either 0 or 1 Continue to Figure 10 3 2 Fig 10 3 1 Initial setting example for registers relevant to real time output 1 7721 Group User s Manual 10 7 REAL TIME OUTPUT 10 3 Setting of real time output From preceding Figure 10 3 1 Processing of avoiding undefined output before starting pulse output Note b7 60 0 timer at mode register Address Select of count source f2 b15 b8 b7 bO 67 bO Timer AO register
238. Short wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer The shorter the total wiring length mm unit the less possibility of noise insertion into the microcomputer 1 Wiring for RESET pin Make the length of wiring connected to the RESET pin as short as possible In particular connect a capacitor between the RESET pin and the Vss pin with the shortest possible wiring within 20 mm Reason If noise is input to the RESET pin the microcomputer restarts operation before the internal state of the microcomputer is completely initialized This may cause a program runaway Noise M37721 M37721 Reset Reset _ circuit circuit Vss Not acceptable Acceptable Fig 3 Wiring for RESET pin 2 Wiring for clock input output pins Make the length of wiring connected to the clock input output pins as short as possible Make the length of wiring between the grounding lead of the capacitor which is connected to the oscillator and the Vss pin of the microcomputer as short as possible within 20 mm Separate the Vss pattern for oscillation from all other Vss patterns Refer to Figure 11 Reason The microcomputer s operation synchronizes with a clock generated by the oscillation circuit If noise enters clock I O pins clock waveforms may be deformed This may cause a malfunction or a program runaway M37721 M37721 Also if the noise causes a pote
239. T CPU 2 4 Memory assignment M37721S2BFP M37721S1BFP SFR area Note 1 SFR area Note 1 00000016 00007 16 00008016 512 bytes Case of Internal RAM Internal RAM area area select bit 0 512 bytes Note 2 00027 16 _ Internal RAM Interrupt vector table area OOFFDOt6 DMA2 OOFFD216 DMA1 OOFFD416 _ DMAO OOFFD6 6 A D conversion Case of Internal RAM 512 bytes area select bit 1 00047Fi6 OOFFD816 J janr transmit 001 016 OOFFDAte UART1 receive SFR area SFR area OOFFDCi6 UARTO transmit 001FFF 6 OOFFDE16 UARTO receive OOFFEOt16 Timer B2 OOFFE216 Timer B1 OOFFE616 Timer A4 OOFFE816 Timer A3 OOFFEAt6 Timer A2 OOFFECi6 Timer 1 OOFFEE16 Timer OOFFFO16 INTs OOFFF216 INT OOFFF416 TNTo OOFFF616 OOFFF816 Watchdog timer DBC Note 3 OOFFFAie BRK instruction 00 divide OOFFFE16 RESET qT Ij qT qT ijr Ij Ij qT Ij qT I qT Ij I I Ij FFFFFF e The internal memory is not assigned SFR area Refer to Figure 2 4 2 and Figure 2 4 3 Notes 1 Addresses 216 to 916 are the external memory area 2 For the M37721S1BFP fix the internal RAM area select bit to 0 3 DBC is an interrupt only for debugging do not use this interrupt Fig 2 4 1 Memory assignment 7721 Group User s Manual 2 19 CEN
240. TRAL PROCESSING UNIT CPU 2 4 Memory assignment Address 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000 16 00000 16 00000C16 00000D16 00000 16 00000 16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001 16 00001 16 00001016 00001 16 00001F 16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002 16 00002 16 00002016 00002 16 00002 16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C16 00003D16 00003E16 00003F 16 Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register Pulse output data register 0 Pulse output data register 1 A D control register A D sweep pin select register A D register 0 A D register 1 A D register 2 A D register 3 A D register 4 A D register 5 A D register 6 A D register 7 UARTO transmit
241. Timer B input Pulse period measurement mode Symbol Calculation formula Unit 8 x 10 ns f Xin tw TBH 4 X 10 ns f Xin tw TBL 4 X 10 ns Timer input Pulse width measurement mode Symbol Calculation formula Unit lere 8 X 10 ns tw TBH 4 X 10 ns f Xin tw TBL 4 X 10 ns f Xin 7721 Group User s Manual 17 103 APPENDIX Appendix 11 Electrical characteristics Table 4 Calculation formulas for bus timing depending on f X Vcc 5 V 10 Vss 0 V Ta 20 to 85 C Symbol Calculation formula Unit ta AL E 1 X 10 la AM E 25 ns ta AH E f Xin ta AM ALE 9 ta AH ALE XS 35 ns tw ALe 1 X 10 _ 18 Xin 1 X 10 ta BHE E 20 ns pos f Xin h E AL 109 E 22 ns th E DLa 1 X 10 th E DHa Xin 22 ns tpzx E DLZ 9 tpzx E DHZ E 20 ns th E BLE 1 X 10 th E BHE 22 ns h E R Ww T Wait bit 1 2 X 10 25 f Xin Wait bit 0 4 10 Mgr ES lee Tsu A DL bit 1 9 tsu A DH 1 Xe 70 ns Wait bit 0 5 X 10 _ aie f Xin tsu ace pL Wait bit 1 3 10 _ 65 tsu ALE DH Xin ns Wait bit 4 5 10 _ 65 17 104 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Table 5 Calculation formulas
242. Timer BO register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 Timer B2 register Addresses 5516 5416 15 to 0 These bits can be set to 0000 e to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 9 3 1 Structures of timer Bi mode register and timer Bi register in timer mode 7721 Group User s Manual 9 9 TIMER B 9 3 Timer mode 9 3 1 Setting for timer mode Figure 9 3 2 shows an initial setting example for registers relevant to the timer mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting timer mode and count source b7 50 Timer Bi mode register i 0 to 2 Jx olo Addresses 5816 to 5016 Selection of timer mode Count source select bits b7 b6 00 f2 01 16 10 fea 11 f512 X It may be either 0 or 1 Setting division ratio b15 bo Timer BO register Addresses 5116 5016 Timer B2 register Addresses 5516 5416 EN Can be set to 000016 to FFFF e n Note The counter divides the count source by n 1 Setting interrupt priority level Timer Bi interrupt control register i 2 O to 2 Addresses 7 16 to 7 16 Interrupt priority level select bit
243. Timing chart for circuit example using bus buffers 2 7721 Group User s Manual 16 19 APPLICATION 16 1 Memory connection 16 1 3 Example of memory connection Examples of the flash memory SRAM and DRAM connection and the timing charts are described as follows 1 Example of flash memory connection minimum model M5M28F101AFP 10 Make sure that the propagation delay Address bus 15 time is within 25 ns Data bus Do D7 Memory map 000016 SFR area 008016 Internal RAM area 048016 External ROM area M5M28F101AFP ACOA TREO SFR area 200016 Circuit condition Software Wait External ROM area M5M28F 101 AFP Fig 16 1 16 Example of flash memory connection minimum model 16 20 7721 Group User s Manual lt When reading gt APPLICATION 16 1 Memory connection tw EL 135 min lt gt N A16 Do A23 D7 External ROM data output ta AH E 15 min lt 9 lt tpzx E DLZ 20 min ta R W E 20 min lt th E R W 18 max AC04 tPLH ACO4 tPHL 15 max Guaranteed as kit tsu DL E gt 30 Specifications of M5M28F101AFP 10 The others are specifications of M37721 Fig 16 1 17 Timing chart for flash memory connection example minimum model 7721 Group User s Manual 16 21 APPLICATION 16 1 Memory connection 2 Example of fl
244. Transfer counter register 3 Addresses 1FFA16 to 1FF816 TCR3 Bit Functions At reset 23 to 0 Write RW Note When writing to this register write to all 24 bits Set the byte number of transfer data These bits can be set to 00000116 to FFFFFF e Read The read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register Fig 13 6 1 Register structures of SARi DARi and TCRi in repeat transfer mode 13 62 7721 Group User s Manual DMA CONTROLLER 13 6 Repeat transfer mode 13 6 1 Setting of repeat transfer mode Figures 13 6 2 through 13 6 4 show an initial setting example for registers relevant to the repeat transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function In this mode only the forced termination can terminate the DMA transfer Refer to section 13 3 5 2 Forced termination Therefore in the burst transfer mode edge sense selected be sure to validate the TC pin When external DMA source is selected When internal DMA source is selected port P9 direction register b7 50 Port 9 direction register Address 1516 pin DMAREGI pin DMAREQ2 pin DM
245. VERTER 12 1 Overview 12 2 Block description 12 3 A D conversion method 12 4 Absolute accuracy and differential non linearity error 12 5 One shot mode 12 6 Repeat mode 12 7 Single sweep mode 12 8 Repeat sweep mode 12 9 Precautions for A D converter A D CONVERTER 12 1 Overview 12 1 Overview Table 12 1 1 lists the performance specifications of the A D converter Table 12 1 1 Performance specifications of A D converter Item Performance specifications A D conversion method Successive approximation conversion method Resolution 8 bits Absolute accuracy 3 LSB Analog input pin 8 pins ANo to Note Conversion rate per analog input pin 57 cycles converter s operation clock The A D converter has the 4 operation modes listed below One shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin Repeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin Single sweep mode This mode is used to perform the operation for voltages input from multiple selected analog input pins one at a time Repeat sweep mode This mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins 12 2 7721 Group User s Manual A D CONVERTER 12 2 Block description 12 2 Block description
246. When the most significant bit of Watchdog timer becomes 0 When the STP instruction is executed Refer to section 5 3 Stop mode t reset b7 50 Watchdog timer register Address 6016 Initializes Watchdog timer Undefined When dummy data is written to this register Watchdog timer s value is initialized to FFF16 Dummy data 0016 to FF 6 Fig 15 1 2 Structure of watchdog timer register 15 1 2 Watchdog timer frequency select register This is used to select a Watchdog timer s count source Figure 15 1 3 shows the structure of the watchdog timer frequency select register b7 06 65 64 63 62 61 60 Watchdog timer frequency select register Address 6116 Bit name Functions At reset Watchdog timer frequency select bit 0 512 Nothing is assigned Fig 15 1 3 Structure of watchdog timer frequency select register 7721 Group User s Manual 15 3 WATCHDOG TIMER 15 2 Operation description 15 2 Operation description 15 2 1 Basic operation Watchdog timer starts counting down from FFF e When the Watchdog timer s most significant bit becomes 0 counted 2048 times a watchdog timer interrupt request occurs Refer to Table 15 2 1 When the interrupt request occurs at above 02 a value FFF e is set to Watchdog timer The watchdog timer interrupt is a non maskable interrupt When the watchdog timer interrupt request is accepted the processor inte
247. a select bits bits 0 to 3 These 4 bits specify a DRAM area of 15 Mbytes maximum in a unit of 1 Mbyte Figure 14 2 3 shows setting examples of DRAM areas 1 Mbyte 4 Mbytes 8 Mbytes 15 Mbytes 00000016 00000016 00000016 00000016 10000016 80000016 Maximum C0000016 F00000 6 FFFFFFi Minimum FFFFFF16 FFFFFF16 FFFFFF 6 DRAM area 00012 DRAM area select bits Bits 3 0 Fig 14 2 3 Setting examples of DRAM areas 2 DRAM validity bit bit 7 When this bit is set to 1 pin functions for DRAM control become valid and the refresh timer starts counting Table 14 2 1 lists the pin functions for DRAM control Table 14 2 1 Pin functions for DRAM control Pins DRAM Operation Ao MAo P106 MAs P104 CAS 570 5 1 validity bit A7 MAz P107 MAs P10s RAS As De Ars Dis R W E BLE BHE Accessing MAc MA MAs MAs CAS RAS Do Azs Dr STO ST1 DRAM area As Ds Ats D1s R W E BLE BHE 1 DRAM refresh MAs CAS RAS 00 0 STO ST1 As Ds A1s Di5 0 0 is R W E BLE output Other than Ao A7z MAs CAS RAS A16 Do A23 D7 STO ST1 the above As Ds A15 D15 R W E BLE BHE 7 P10e P107 104 105 Aie Do Azs D7 STO ST1 0 As Ds Ats Dis R W E BLE BHE 14 4 7721 Group User s Manual DRAM CONTROLLER 14 2 Block description 14 2 2 Refresh timer The refresh timer is an 8 bit timer wit
248. a sng 1 sng esn 10 uonisuei ojejs Aeuy SJejeureJed JejsueJ JO JeJsueJ JojeureJed jojsueJj JO 1 JSUVI L 11 8 8 21 e1nBi4 OLS 16 IOVVIAG Buidures jsanbe sng Zq eey 0d 9 lV si qysiv eq ev 4 0 Fig 13 8 7 Timing diagram of link array chain transfer mode burst transfer mode 1 13 89 7721 Group User s Manual 13 8 Link array chain transfer mode DMA CONTROLLER esn jo uonisuej gt i e a e i gt lt i 1 5 1eJsueJ s ayeys oyeys Aey 1 wt Jo JejsueJ gt JejsueJ pun 015 LLS oL 1senboJ sng WH AA LALLA CLA 78761 Fig 13 8 8 Timing diagram of link array chain transfer mode burst transfer mode 2 7721 Group User s Manual 13 90 DMA CONTROLLER 13 8 Link array chain transfer mode Figure 13 8 9 shows the conditions necessary for timings shown in Figures 13 8 7 13 8 8 and 13 8 10 through 13 8 14 External data bus width Transfer unit Transfer method Transfer mode Transfer source address direction Transfer destination address directi
249. abled only when its priority level is higher than the IPL However this applies when the interrupt disable flag 1 0 To disable A D conversion interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when an A D conversion interrupt request occurs This bit is automatically cleared to 0 when the A D conversion interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 12 8 7721 Group User s Manual A D CONVERTER 12 2 Block description 12 2 5 Port P7 direction register Input pins of the A D converter are multiplexed with port P7 When using these pins as A D converter s input pins set the corresponding bits of the port P7 direction register to 0 to set these port pins for the input mode Figure 12 2 6 shows the relationship between the port P7 direction register and converter s input pins 67 66 b5 64 63 b2 bli Port P7 direction register Address 1116 o menn 0 Input mode ES 1 Output mode When using these pins as 5 ANs pin Fig 12 2 6 Relationship between port 7 direction register and A D converter s input pins 7721 Group User s Manual 12 9 A D CONVERTER 12 3 A D conversion method 12 3 A D conversion method The A D converter compares the comparison voltage Vre which is internally generated according to the contents
250. across banks 0 and 1 when the DPR is FF01 e or more Fig 2 1 4 Setting example of direct page area 2 6 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 9 Processor status register PS The processor status register is an 11 bit register Figure 2 1 5 shows the structure of the processor status register 615 614 613 612 611 610 69 68 67 b6 65 64 63 62 61 z e register PS Note Bits 11 15 is always 0 at reading Fig 2 1 5 Processor status register structure 1 Bit 0 Carry flag C It retains a carry or a borrow generated in the arithmetic and logic unit ALU during an arithmetic operation This flag is also affected by shift and rotate instructions When the BCC or BCS instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEC or SEP instruction to set this flag to 1 and use the CLC or CLP instruction to clear it to 0 2 Bit 1 Zero flag 2 It is set to 1 when a result of an arithmetic operation or data transfer is 0 and cleared to 0 when otherwise When the BNE or instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode additi
251. address collides with the head of data Refer to section 3 Precautions on memory connection 3 If one of the external memory s specifications is greater than tpzx E pLz DHz there is a possibility that the tail of data collides with the head of address Refer to section 3 Precautions on memory connection Note tsu A DL DH tsu A DL OF tsu A DH tpzx E DLZ DHZ tpzx E DLZ tpzx E DHZ tsu DL DH E tsu DL E tsu DH E Fig 16 1 1 Timing for reading data from flash memory and SRAM 16 4 7721 Group User s Manual APPLICATION 16 1 Memory connection Address access time taan lt tswa o on address latch delay OE access time taog lt tsu DL DH E Chip select access time tas address decode time address latch delay time Address latch delay time Delay time required when latching address Unnecessary in minimum model Address decode time Time required for validating chip select signal after decoding address Table 16 1 2 lists the calculation formulas and values for each parameter in Figure 16 1 1 Figure 16 1 2 shows the relationship between and f Xin Table 16 1 2 Calculation formulas and Values for each parameter in Figure 16 1 1 unit ns Calculation formulas and Values No Wait Wait twEL 2 X 10 4 X 10 f Xin VER f Xin E tsu a DL 3 X 10 5 X 10 70 70
252. address of data block at the transfer destination DARI Indicates the address of the next transfer destination TCRi latch Indicates the number of transfer bytes TCRi Indicates the number of remaining transfer bytes Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers pin validity bit Bit 1 at address 6816 13 54 7721 Group User s Manual DMA CONTROLLER 13 5 Single transfer mode Source address register 0 Addresses 1 216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 1FD016 Source address register 2 Addresses 1FE216 to 1 016 SAR2 Source address register 3 Addresses 1FF216 to 1FFO16 SAR3 23 to 0 Write Set the transfer start address of the source ndetined RW These bits can be set to 00000016 to Read The read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits Destination address register 0 Addresses 1FC6 6 to 1FC416 DARO Destination address register 1 Addresses 1FD6 6 to 1FD416 DAR1 Destination address register 2 Addresses 1FE616 to 1FE416 DAR2 Destination address register Addresses 1FF616 to 1FF416 DAR3 Write Set the transfer start address of the destination undenhedi RW These bits can be set to 00000016
253. al APPENDIX Appendix 6 Machine instructions Addressing modes Processor status register L DIR LibIR v ABS ABS b ABS x ABS Y ABL ABL x ABS JL ABS ABS X STK RE R b R 5 SR 6 5 lop n n fop op n n amp op jop n fop n op m OC 9 4 7721 Group User s Manual 17 53 APPENDIX Appendix 6 Machine instructions The number of cycles shown in the table is described in the case of the fastest mode for each instruction The number of cycles shown in the table is calculated for DPRL 0 The number of cycles in the addressing mode concerning the DPR when DPR 0 must be incremented by 1 The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer or according to whether the memory read write address is odd or even It also differs when the external region memory is accessed by Notes 1 The operation code at the upper row is used for accumulator A and the operation at the lower row is used for accumulator B 2 When setting flag m 0 to handle the data as 16 bit data in the immediate add
254. al ALE This signal is used to latch the address from the multiplexed signal which consists of the address and data This multiplexed signal is input to or output from the As Ds Ais D1s and A e Do Azs D7 pins When the ALE signal is H latch the address and simultaneously output the addresses When this signal is L retain the latched address Ready function related signal RDY This is the signal to use Ready function Refer to section 3 3 Ready function Hold function related signal HOLD This is the signal to use Hold function Refer to section 3 4 Hold function Status signals STO ST1 These signals indicate the bus use status Table 3 1 3 lists the bus use status indicated by the STO and ST1 signals 10 Clock This signal has the same period as Table 3 1 3 Bus use status indicated by STO and ST1 signals ST1 STO Bus use status L L DRAM refresh L H Hold H L DMA H H CPU 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 3 1 2 Operation of bus interface unit BIU Figures 3 1 2 and 3 1 3 show the examples of operating waveforms of the signals input from or output to the external when accessing external devices The following explains these waveforms being compared with the basic operating waveform Refer to section 2 2 3 Operation of bus interface unit BIU 1 When fetching instructions in
255. al 17 105 APPENDIX Appendix 11 Electrical characteristics Table 6 Calculation formulas for DMA transfer bus timing depending on Vcc 5 V 10 Vss 0 V Ta 20 to 85 C Symbol Calculation formula Unit td AL E 1 X 10 1 25 ns td AH E tw ALE 1 X 10 1 1 45 td BLE E 1 X 10 ta BHE E 20 ns ta R w e f Xin th E AL 9 WX nua ns Th E DLQ 9 th E DHa E 22 ns tpzx E DLz 1 X 10 lpzx E DHZ Ld 20 ns th E BLE 1 X 10 th E BHE 22 ns n E R W f Xin tun Transfer source Transfer 2 X 10 _ 25 destination wait bit 2 1 Transfer source Transfer 4X 10 _ 25 destination wait bit 0 ie 2 10 995 S Ao MAo A7 MA7 As Da8 A15 D15 16 00 23 07 Fig 13 Test circuit for each Fig 14 Test circuit for TC output delay time and TC output pulse width 17 106 7721 Group User s Manual APPENDIX Appendix 12 Standard characteristics Appendix 12 Standard characteristics Standard characteristics described below are just examples of the M37721S2BFP s characteristics and are not guaranteed For each parameter s limits refer to section Appendix 11 Electrical characteristics 1 Programmable I O port CMOS output standard characteristics 1 P channel characteristics 30 0 24 0
256. al source DMAREQi is selected or when the cycle steal transfer mode is selected set this bit to 0 DMAO mode register Address 1FCD16 DMA1 mode register Address 1FDD16 DMA2 mode register Address 1FEDie DMA3 mode register Address 1FFD16 Continue to Figure 13 8 5 on next page Transfer direction select bit Used in 1 bus cycle transfer 0 From memory to 1 From I O to memory l O connection select bit Valid in 1 bus cycle transfer 0 Data bus Do D or 015 1 Data bus De D s Transfer source wait bit Valid in DMA transfer 0 Wait 1 No wait Transfer destination wait bit Valid in DMA transfer 0 Wait 1 No wait Selection of link array chain transfer mode S 7 523 b16 b15 68 7 5057 50 Source address register 0 Addresses 1 216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 12006 SAR1 Source address register 2 Addresses 1 216 to 1 016 SAR2 Source address register Addresses 1FF216 to 1 016 SAR3 Set the start address of transfer parameter memory of block which is first transferred These bits can be set to 00000016 to FFFFFF e 623 516 615 08 ee eae bo Transfer counter register 0 Addresses 1FCA16 to 1FC816 TCRO L Transfer counter register 1 Addresses 1FDA e to 1 081 TCR1 Transfer counter register 2 Addresses 1FEA e to 1 816 T
257. and this term on condition that DMAi request bit of restarts DMA transfer if DMAi request another channel becomes 1 at the timing bit of another channel becomes 1 satisfying tsu DRQ 61 during this term When DMA request is generated at the following timing it is not in time to the next bus request sampling Therefore DMAC returns the right to use bus to the CPU Then the DMAC regains the right and restarts DMA transfer Except for the last 1 unit transfer is selected without Wait In addition a time of 0 5 cycle of is less than tsupno 61 Fig 13 4 13 Conditions for performing DMA transfers of another channel subsequently 7721 Group User s Manual 13 53 DMA CONTROLLER 13 5 Single transfer mode 13 5 Single transfer mode This mode is used to transfer a block of data once Table 13 5 1 lists the specifications of the single transfer mode and Figure 13 5 1 shows the register structures of SARi DARi and TCRi in this mode Table 13 5 1 Specifications of single transfer mode Performance specifications Not required TCRi 0 Falling edge of the TC pin s input from to L when the pin validity bit 1 Write 0 to the DMAi enable bit At normal termination SARi latch Indicates the transfer start address of data block at the transfer source SARi Indicates the address of the next transfer source DARi latch Indicates the transfer start
258. are required for each block of data that is a transfer parameter memory consumes 12 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits In 1 bus cycle transfer from memory to I O All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 8 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits In 1 bus cycle transfer from I O to memory All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 8 bytes for each block Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits 7721 Group User s Manual 1 2 bus cycle transfer 4 bytes Transfer source s transfer start address 1 4 bytes 4 bytes The above applies when 4 block transfer is performed 2 1 bus cycle transfer Transfer source s transfer start address 1 Transfer data s byte number 1 Transfer source s transfer start address 2 Transfer data s byte number 2 Transfer source s transfer start address 3 Transfer data s byte number 3 Tra
259. ash memory and SRAM connection maximum model M37721 Address bus 16 As Ds A15 D15 573 T S E CE 14 14 15 M5M28F102AFP M5M5256DP 70LL M5M5256DP 70LL 10 A16 Do A18 D2 DQ i DQs DQ i DQs 015 OE W OE Memory map 000016 SER area 008016 Internal RAM area Circuit condition Software Wait 048016 External ROM area M5M28F102AFP 1 2 Make sure that the sum of propagation delay time is within 30 ns External ROM area 453 4 Make sure that the sum of propagation delay time is within 20 ns M5M28F102AFP 5 Make sure that the propagation delay time is within 5 ns External RAM area M5M5256DP X 2 Fig 16 1 18 Example of flash memory and SRAM connection maximum model 16 22 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt 135 min E ta AL E 15 min lt _____ gt A1 A7 08 15 015 16 00 18 02 Dp 9 tpzx E DLZ DHZ 20 min r AC32 tPLH AC32 tPHL lt tDF tdis OE 15 max External memory Guaranteed as kit data output tsu DL DH E gt 30 tsu A DL DH 130 max ta AD AC573 tPHL tPLH lt When writing gt tw EL 135 min ta AL E 15 min A1 A7 As Ds A15 D15 16 00 18 02
260. ation effective Sep 1997 1997 MITSUBISHI ELECTRIC CORPORATION Specifications subject to change without notice
261. b3 62 bi 10 1 register Address 2 i Dn pe UU Select bit es flag Td mpg This bit is invalid mode ____ RW x1 4 Blank Set to 0 or 1 according to the usage 0 Set to 0 at writing 1 Set to 1 at writing x Invalid depending on the mode or state It may be 0 or 1 SS Nothing is assigned 0 0 immediately after reset 1 1 immediately after reset Undefined Undefined immediately after reset 3 RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid Accordingly the written value may be 0 or 1 WO The written value becomes valid It is impossible to read the bit state The value is undefined at reading However when 0 is at reading is indicated the Function or Note column the bit is always 0 at reading See k4 above It is impossible to read the bit state The value is undefined at reading However when 0 is at reading is indicated the Function or Note column the bit is always 0 at reading See 4 above The written value becomes invalid Accordingly the written value may be 0 or 1 7721 Group User s Manual 17 9 APPENDIX Appendix 3 Control registers Port Pi register b7 06 65 04 63 02 bi b0 Port Pi register i 4 to 10
262. b3 b2 bi 0 Port P10 direction register Address 1816 1 E Input mode Output mode When using a pin as an input pin INT for an external interrupt clear the rm 7 corresponding bit to 0 ______ ewe eae Bits 3 to 7 are not used for external interrupts Fig 7 10 2 Relationship between port P10 direction register and input pins of external interrupt 7721 Group User s Manual 7 19 INTERRUPTS 7 10 External interrupts INTi interrupt 7 10 1 Functions of INTi interrupt request bit 1 2 Functions when edge sense is selected The interrupt request bit has the same functions as that of an internal interrupt That is when an interrupt request occurs the interrupt request bit is set to 1 and retains this state until the interrupt request is accepted When this bit is cleared to 0 by software the interrupt request is cancelled when this bit is set to 1 by software the interrupt request can be generated Functions when level sense is selected The INTi interrupt request bit is ignored Interrupt requests continuously occur while the level of the INTi pin is the valid level when the pin s level changes from the valid level to the invalid level before the INTi interrupt request is accepted this interrupt request is not retained Refer to Figure 7 10 4 Valid level This means the level select
263. bank register PG S is the initial address that the stack pointer S indicates at accepting an interrupt request The S s contents become 5 5 after storing the above registers Fig 2 1 2 Stored registers of the stack area 2 4 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 5 Program counter PC The program counter is a 16 bit counter that indicates the low order 16 bits of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored The contents of the high order program counter become FF e and the low order program counter PCL becomes at reset The contents of the program counter becomes the contents of the reset s vector address addresses FFFE e immediately after reset Figure 2 1 3 shows the program counter and the program bank register Fig 2 1 3 Program counter and program bank register 2 1 6 Program bank register PG The access space is divided in units of 64 Kbytes This unit is called bank Refer to section 2 3 Access space The program bank register is an 8 bit register This register indicates the high order 8 bits bank of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored These 8 bits ar
264. can be connected or the clock which is externally generated can be input Oscillation circuit examples are shown below 5 1 1 Connection example using resonator oscillator Figure 5 1 1 shows an example when connecting a ceramic resonator quartz crystal oscillator between pins Xin and The circuit constants such as Rf Rd Cin and Cour shown in Figure 5 1 1 depend on the resonator oscillator These values shall be set to the values recommended by the resonator oscillator manufacturer 5 1 2 Externally generated clock input example M37721 Figure 5 1 2 shows an input example of the clock which is externally generated The external clock must be input from the pin and the Xour pin must be left open Fig 5 1 1 Connection example using resonator oscillator M37721 Externally generated clock Vss Fig 5 1 2 Externally generated clock input example 5 2 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 2 Clocks 5 2 Clocks Figure 5 2 1 shows the clock generating circuit block diagram XIN Q internal peripheral devices Interrupt request Q eS gt 1512 Operation clock for 0 Watchdog timer 1512 frequency select bit STP instruction 4 f 32 Watchdog WIT instruction d 6 Ready request n CPU wait request from BIU Bus request DRAMC Hold V _
265. ce of 1 data block is terminated latch Contents of SARi are updated by incrementer decrementer Data is read from memory and maintained DMA Q TOR ach TCRi latch SARi latch Transfer DMA latch destination 2 Write cycle DMAC Transfer destination address is specified by DARi Note ARi SARi latch Contents of DARI are updated by incrementer ncrementer Transfer Co DMA latch are write t DARI source ontents atch are written to memory DARi latch TCRi latch Transfer DMA latch 4 destination When the transfer unit is 16 bits When an even address is accessed with 16 bit external data bus width data can be read or written at 1 bus cycle Accordingly the incrementer decrementer and the decrementer increment or decrement by 2 and sequences through are performed once When an odd address is accessed with 16 bit external data bus width or when 8 bits is used as external data bus width data is read or written at 2 bus cycles and sequences through or through are repeated twice The incrementer decrementer and the decrementer increment or decrement by 1 every time sequences through or through are performed once Note In the single transfer mode and repeat transfer mode only at the first transfer of the block the values read from SARi latch DARi latch and TCRi latch are used The results obtained by increment or decrement are written to S
266. ce address register 0 001FC216 001FC316 001FC416 001FC516 Destination address register 0 001FC616 001FC716 001FC816 001FC916 Transfer counter register 0 001FCA16 001FCB16 001FCC16 DMAO mode register L 001FCD16 DMAO mode register 001FCE16 DMAO control register 001FCF16 001 0016 001FD116 Source address register 1 001FD216 001FD316 001FD416 001FD516 Destination address register 1 001FD616 001FD716 001FD816 001FD916 Transfer counter register 1 001FDA16 001FDB16 001FDC16 DMA1 mode register L 001FDDie DMA1 mode register H 001FDE16 DMA1 control register 001FDF16 001 016 001 116 Source address register 2 001FE216 001FE316 001FE416 001FE516 Destination address register 2 001FE616 001FE716 001FE816 001 916 Transfer counter register 2 001 16 001 16 001 16 DMA2 mode register L 001FED16 DMA2 mode register H 001 16 control register 001FEF16 001FF016 001FF116 Source address register 3 001FF216 001FF316 001FF416 001FF516 Destination address register 3 001FF616 001FF716 001FF816 001FF916 Transfer counter register 3 001 16 001 16 001 16 DMA3 mode register L 001FFD16 DMA3 mode register H 001 16 DMAG control register 001 16 Fig 2 4 3 SFR area s memory 2 7721 Group
267. cessed eALE This is used to obtain only the address from address and data multiplex signals HOLD Hold input Input The microcomputer is in Hold state while L level is input to the HOLD pin RDY Ready input Input The microcomputer is in Ready state while L level is input to the RDY pin Clock output Output This is the output pin 7721 Group User s Manual 1 5 DESCRIPTION 1 3 Pin description Table 1 3 3 Pin description 3 Pin Name Input Output Functions P4s P47 port P4 Port P4 is 5 bit CMOS I O port This port has an I O direction register and each pin can be programmed for input or output P5o P5 port P5 Port P5 is an 8 bit I O port with the same function as P4 These pins can be programmed as pins for Timers 2 4 and I O pins for Timers BO B1 P6o P67 port P6 Port is an 8 bit I O port with the same function as P4 These pins can be programmed as output pins for the real time output P7o P77 port P7 Port P7 is an 8 bit I O port with the same function as P4 These pins can be programmed as input pins for A D converter P80 P87 port P8 Port P8 is an 8 bit I O port with the same function as P4 These pins be programmed as pins for Serial I O 9 9 gt port P9 Port 9 is 8 bit I O port with the same function as P4 These pins be programmed as pins for DMA controller P10c
268. ch are also decremented by 1 13 2 9 DMA latch The DMA latch is a 16 bit latch In 2 bus cycle transfer mode the DMA latch maintains the value read from the transfer source memory with a read cycle until this value is written into the transfer destination memory In 1 bus cycle transfer mode the DMA latch is used to copy data For copy refer to section 13 4 2 1 bus cycle transfer 7721 Group User s Manual 13 13 DMA CONTROLLER 13 2 Block description 13 2 10 DMAi mode register L Figure 13 2 6 shows the structure of DMAi mode register L For bit 0 refer to section 13 1 3 2 Transfer unit For bit 1 refer to section 13 4 1 2 bus cycle transfer and section 13 4 2 1 bus cycle transfer for bit 2 refer to section 13 4 3 Burst transfer mode and section 13 4 4 Cycle steal transfer mode 1 Transfer source address direction select bits bits 4 and 5 and Transfer destination address direction select bits bits 6 and 7 Address direction means an order of accessing memory in DMA transfer and is defined as follows Fixed direction an address does not move Forward direction an address moves upward from the specified start address Backward direction an address moves downward from the specified start address For details refer to section 13 4 1 3 Address directions in 2 bus cycle transfer and section 13 4 2 3 Address directions in 1 bus cycle transfer DMAO mode register L Ad
269. cking error UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Overrun error flag b7 50 0 No overrun error a 1 Overrun error detected Note This figure shows the bits and registers required for processing Refer to Figure 11 3 12 for the change of flag state and the occurrence timing of an interrupt request Processing after reading out receive data Fig 11 3 9 Processing after receive completion 11 26 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial mode 11 3 5 Receive operation In the case of selecting an internal clock when the receive conditions described in section 11 3 4 Method of reception are satisfied a transfer clock is generated and the reception is started after 1 cycle of the transfer clock has passed In the case of selecting an external clock when the receive conditions are satisfied the UARTi enters the receive enable state and reception is started by input of an external clock to the CLKi pin In the case of selecting an external clock and the RTS function when the UARTi enters the receive enable state the RTSi pin s output level becomes L to inform the transmitter side that reception is enabled When reception is started the RTSi pin s output level becomes Accordingly by connecting the RTS pin to the CTSi pin of the transmitter side the timin
270. cle steal transfer mode not changed Note DMAi enable bit 0 output Outputs L when the TC pin is valid Channel priority levels Rotating when the rotating priority is selected Note In the cycle steal transfer mode the DMAi request bit is cleared to 0 when a DMA request is accepted This bit is does not change at normal termination At normal termination the CPU regains the right to use bus after the terminate processing 3 cycles of via the transition of the right to use bus 1 cycle of 0 Figure 13 3 3 shows a timing example at normal termination 7721 Group User s Manual 13 25 DMA CONTROLLER 13 3 Control Transition of right to use bus Terminate processing E RW Address Address Data enable bit request bit When Burst transfer mode edge sense selected When Burst transfer mode level sense selected Q9 When Cycle steal transfer mode selected BUS REQUEST DMAC Bus request sampling DMAACKi TC ST1 STO interrupt request bit The above timing diagram applies on the following conditions DMAACKi valid TC valid e External source DMAREQi Fig 13 3 3 Timing example at normal termination 13 26 7721 Group User s Manual DMA CONTROLLER 13 3 Control 2 Forced termination The methods of terminating DMAC other than normal termination are as follows Drives the TC pin s input level fro
271. cle transfer and Table 13 4 7 lists the outputs of the address bus the data bus and the bus control signals in 1 bus cycle transfer 7721 Group User s Manual 13 41 DMA CONTROLLER 13 4 Operation Internal clock A D A Address D Data I 4 Transfer term per 1 unit transfer Fig 13 4 7 Bus cycle operation waveforms in 1 bus cycle transfer 13 42 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Table 13 4 6 Data flows on data bus in 1 bus cycle transfer External data Transfer Read Write address bus width connection unit of memory Data flow M37721 Data bus Data bus Ds D15 Do Dz Even address il6bits and 16 bits and Data Dus Dp Ds D15 Odd address M37721 Data bus Ds D15 Even address Data bus Data bus 16 bits Do Dz 8 bits Data bus Ds D15 Data bus Do D7 Odd address Note Data is copied from data bus Do D7 to Ds D15 or from data bus Ds D15 to Do D7 in the M37721 s DMAC Note the data copy delay time ta data M37721 Data bus Ds D15 Data bus Do D7 Even address Note Data is copied from data bus Do D7 to Ds D15 or from data bus Ds D15 to 07 in the M37721 s DMAC Note the data copy delay time ta data Data bus 16 bits Da Dis 9 bits M37721 Data bus Ds D15 Data bus Do D Odd address ad M37721 Even address Data bus 8 bits Do Dz 8 bits and Data bus Do D7 Odd address N
272. cleared by software Parity disabled 1 stop bit RTS function selected Fig 11 4 12 Example of receive timing when transfer data length 8 bits when parity disabled selecting 1 stop bit selecting RTS function 7721 Group User s Manual 11 45 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 7 Processing on detecting error In the UART mode 3 types of errors can be detected Each error can be detected when the data in the UARTi receive register is transferred to the UARTi receive buffer register and the corresponding error flag is set to 1 When any error occurs the error sum flag is set to 1 Accordingly presence of errors can be judged by using the error sum flag Table 11 4 6 lists conditions for setting each error flag to 1 and method for clearing it to 0 Table 11 4 6 Conditions set to 1 and method cleared to 0 for each error flag Error flag Overrun error flag Conditions for being set to 1 When the next data is prepared in the receive register with the receive complete flag 1 i e data is present in the UARTi receive buffer register In other words when the next data is prepared before the contents of the UARTi receive buffer register are read out Note UARTi receive interrupt request bit is not changed Method for being cleared to 0 Clear the serial I O mode select bits to 0002 Clear the receive enable bit to
273. control 13 16 13 2 13 interrupt control E E ET 13 17 Precautions iegien Ptel MEE 7721 Group User s Manual V Table of contents 13 3 13 19 13 314 DMA enabling 13 19 13 9 2 eon eeu ud 13 20 hannel prioritv 2 0 2 6 13 21 13 23 S 13 25 13 3 6 DMA transfer restart after 13 28 A A AA A E 13 30 ET 13 30 13 37 M E 13 38 Precautions for 1 bus cycle 1 0 13 47 ansfer 0 0 00144144111 lt 13 48 Precautions for burst transfer 0 0 14 2 Block descriptlon oco i cune eR cu a Yarn nn xk mama aux oC ERG
274. cordingly the internal peripheral devices can operate Ready function is valid for the internal and external areas Table 3 3 1 Microcomputer s state in Ready state Oscillation Operating cru 9 Stopped at L Pins Ao to Az As Ds to A1s D15 A16 Do to Azs Dz E R W Retain the state when Ready request was accepted BHE BLE STO ST1 ALE Pins P4s to P47 P5 to P10 Note Pin Outputs clock Watchdog timer Operating Note This applies when this functions as a programmable I O port 3 10 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 3 Ready function 3 3 1 Operation description The input level of the RDY pin is judged at the falling edge of clock When L level is detected at this point the microcomputer enters Ready state This is called Acceptance of Ready request In Ready state the input level of the RDY is judged at every falling edge of clock When level is detected at this point the microcomputer terminates Ready state at the next rising edge of clock Figure 3 3 1 shows timing of acceptance of Ready request and termination of Ready state Refer also to section 16 1 Memory connection for usage of Ready function lt No Wait gt RDY pin input level sampling timing J D The L level which is input to the RDY pin is accepted so that E stops at H level for 1 cycle of clock 1 indicated by 559
275. cycle transfer Read cycle Write cycle x the number of transfers 1 Add a value which satisfies the read write conditions Refer to Table 13 4 1 3 2 When the transfer unit is 16 bits the number of transfers the number of transfer bytes 2 When the transfer unit is 8 bits the number of transfers the number of transfer bytes In 1 bus cycle transfer Refer to Table 13 4 5 Terminate processing cycles DMA transfer of the block at the TC input above 9 The number of transfers is assumed to be up to the DMA transfer of 1 unit transfer which was in progress at the TC input Transition of the right to use bus from DMAC to CPU 1 cycle Example External data bus width 16 bits 2 bus cycle transfer transfer unit 216 bits the number of the transfer bytes 10 bytes and under the following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data even without Wait is input when the m th byte m even of the n th block is in transfer n 1 O 1 n 1 5 3 4 3 2 1 38n m 2 36 cycles 13 102 7721 Group Users Manual DMA CONTROLLER 13 9 DMA transfer time 3 Array chain transfer mode and Link array chain transfer mode Transition Array state Transfer Array state Transfer Termination Transition T 4 m 4
276. d For details refer to section 13 4 3 Burst transfer mode Cycle steal transfer mode For each DMA request 1 transfer unit of data is transferred Hereafter transferring 1 transfer unit data which is 8 bit or 16 bit data in the M37721 is called 1 unit transfer When 1 unit transfer is complete and another DMA request including that of other channels is not generated the DMAC relinquishes the right to use bus to the CPU In the cycle steal transfer mode all of the DMA request sources are available For details refer to section 13 4 4 Cycle steal transfer mode Figure 13 1 1 shows the outline of the DMA transfer modes E Burst transfer mode Edge sense request is accepted Rightiousebus CPU Transfer of entire batch of data E Burst transfer mode External source DMAREQi level sense DMAREGi input Righttousebus CPU ____ __________690 __ _ Cycle steal transfer mode DMAO request is accepted DMAO request is accepted request is accepted Rightto usebus CPU DMA0 DMA0 CPU One transfer unit One transfer unit transfer unit Fig 13 1 1 Outline of DMA transfer modes 13 4 7721 Group User s Manual DMA CONTROLLER 13 1 Overview 4 Continuous transfer mode E Single transfer mode 1 block of data is transferred once For details refer to section 13 5 Single transfer mode Repeat tran
277. d Even Odd 14i 2 a 3 d Backward Address directions Refer to section 13 4 1 3 Address directions in 2 bus cycle transfer i A term of E L in 1 bus cycle i 1 at No Wait and i 2 at With Wait or DRAM area When Ready function is used Refer to section 3 3 Ready function the number of cycles extended by Ready must be added Indicates the corresponding waveform in Figure 13 4 3 Note When a transfer destination applies to this condition 2 bus cycle transfer cannot be performed When a transfer source applies to this condition and a transfer destination is in the DRAM area 2 bus cycle transfer cannot also be performed 13 32 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Internal clock A D A Address D Data I Read or write term per 1 unit transfer Fig 13 4 3 Bus cycle operation waveforms in 2 bus cycle transfer 7721 Group User s Manual 13 33 DMA CONTROLLER 13 4 Operation 3 Address directions in 2 bus cycle transfer In 2 bus cycle transfer the address direction of a transfer source and that of a transfer destination each can be selected independently Refer to Figure 13 2 6 Addresses move in the specified direction by the transfer unit Tables 13 4 2 through 13 4 4 list address directions in 2 bus cycle transfer and examples of transfer result Tables 13 4 2 Ad
278. d The pin functions as a programmable port Valid The pin functions as DMAACKi Nothing is assigned Undefined Note When a certain source other than an external source is selected by bits 0 to 3 or when the cycle steal transfer mode is selected set bit 4 to 0 Level sense can be selected only when both of the external source and the burst transfer mode are selected Fig 13 2 8 Structure of DMAi control register 13 16 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 13 DMAi interrupt control register Figure 13 2 9 shows the structure of the DMAi interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS 67 b6 65 b4 b3 b2 61 00 interrupt control register i 0 to 3 Addresses 6 16 to GF 6 b2 b1 60 2 Level 0 Interrupt disabled RW Level 1 Low leve Level 6 Level 2 Level 3 RW Level 4 Level 5 RW Level 7 High leve Interrupt request bit 0 No interrupt requested RW 1 Interrupt requested 7 to 4 Nothing is assigned Undefined Fig 13 2 9 Structure of DMAi interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a DMAi interrupt s priority level When using DMAi interrupts select one of the priority levels 1 to 7 When a DMAi interrupt request occurs its priority level is compared with the processor interrupt priorit
279. d these bits are fixed to 0 at reading Port Pis direction bit Rw Fig 6 2 2 Structure of port Pi i 4 to 10 direction register 7721 Group User s Manual 6 3 INPUT OUTPUT PINS 6 2 Programmable ports 6 2 2 Port register Data is input from or output to the external by writing reading data to from a port register A port register consists of a port latch which holds the output data and a circuit which reads the pin state Each bit of the port register corresponds one for one to each pin of the microcomputer Figure 6 2 3 shows the structure of the port Pi i 4 to 10 register When outputting data from programmable I O port set to output mode By writing data to the corresponding bit of the port register the data is written into the port latch The data is output from the pin according to the contents of the port latch By reading the port register of a port set to the output mode the contents of the port latch is read out instead of the pin state Accordingly the output data is correctly read without being affected by an external load etc Refer to Figures 6 2 4 and 6 2 5 When inputting data from programmable I O port set to input mode pin which is set to the input mode enters the floating state By reading the corresponding bit of the port register the data which is input from the pin can be read out By writing data to the port register of a programmable I O port
280. d timer Ai register in the timer mode Table 8 3 1 Specifications of timer mode Item Count source Specifications fo fie fea Or 512 Count operation Countdown When counter underflow occurs reload registers contents are reloaded and counting continues Division ratio 1 n1 n Timer Ai register s set value Count start condition When the count start bit is set to 1 Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing When a counter underflow occurs TAjin pin s function Programmable port or gate input TAjour pin s function Programmable port or pulse output Read from timer Ai register Counter value can be read out Write to timer Ai register While counting is stopped When a value is written to the timer Ai register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Ai register it is written only to the reload register Transferred to the counter at the next reload timing 7721 Group User s Manual 8 9 TIMER A 8 3 Timer mode 67 06 b5 64 63 62 bi 00 Timer AO mode register Address 5616 Timer A1 mode register Address 5716 Count source select bits b7 b6 00 f2 01 16 10 64 111512 67 66 65 64 b3 b2 61 00 lo Timer Aj mode register 2 to 4 Addresses 5816 to 5A 6
281. d use the CLP instruction to clear it to 0 This flag is cleared to 0 at reset Note When transferring data between registers which are different in bit length the data is transferred with the length of the destination register but except for the TXA TYA TXB TYB and TXS instructions Refer to 7700 Family Software Manual for details 7721 Group User s Manual 2 7 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 6 7 8 9 Bit 5 Data length flag m It determines whether to use a data as a 16 bit unit or as an 8 bit unit A data is treated as a 16 bit unit when this flag is 0 and as an 8 bit unit when it is 1 Use the SEM or SEP instruction to set this flag to 1 and use the CLM or CLP instruction to clear it to 0 This flag is cleared to 0 at reset Note When transferring data between registers which are different in bit length the data is transferred with the length of the destination register but except for the TXA TYA TXB TYB and TXS instructions Refer to 7700 Family Software Manual for details Bit 6 Overflow flag V It is used when adding or subtracting with a word regarded as signed binary When the data length flag is 0 the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 32768 32767 and cleared to 0 in all other cases When the data length flag m
282. ddress register 0 Addresses 1FC616 to 1FC4 6 Destination address register 1 Addresses 1FD6 6e to 1FD4 6 Destination address register 2 Addresses 1FE616e to 1 416 Destination address register Addresses 1FF6 6 to 1FF416 23 to 0 These bits have different functions according to the Undetinedl RW operating mode Note When writing to this register write to all 24 bits Addresses 1FCAte 1FC816 Addresses 1FDAte to 1FD816 Addresses 1 16 to 1 816 Addresses 1 16 to 1FF8 6 Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 p ODER 23 to o These bits have different functions according to the Undefined RW operating mode Note When writing to this register write to all 24 bits Do not write 00000016 to this register 7721 Group User s Manual 17 33 APPENDIX Appendix 3 Control registers Single transfer mode b23 b16 b15 b8 b7 bO Addresses 1 216 to 1FC016 Addresses 1 0216 to 1FDO16 Addresses 1FE216 to 1FE016 Addresses 1FF216 to 1 16 Source address register 0 Source address register 1 Source address register 2 Source address register 3 et a Undefined RW Set the transfer start address of the source These bits can be set to 00000016 to FFFFFF 16 Read The read value indicates the source address of data which is next transferred Note When writing to this r
283. ddresses 40 4C Timer A4 register Addresses 4 16 4E16 Can be set to 000016 to FFFE16 n When operating as 8 bit pulse width modulator b15 b8 5 bo Timer A2 register Addresses 4816 4A16 LLL Timer A register Addresses 4Dss 4C Timer A4 register Addresses 4F 16 4 16 _ be set to 0016 to FF16 Can be set to 0016 to FE16 n Note When operating as 8 bit pulse width modulator 1 28 1 fi n m 1 fi fi Frequency of count source Note When operating as 16 bit pulse width modulator Period DLL H level width Period H level width fi Frequency of count source However if n 000016 the pulse width modulator does not operate and the TAjour pin outputs L level At this time no timer Aj interrupt request occurs However if n 00 6 the pulse width modulator does not operate and the TAjour pin outputs L level At this time no timer Aj interrupt request occurs Continue to Figure 8 6 3 Fig 8 6 2 Initial setting example for registers relevant to PWM mode 1 8 40 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode From preceding Figure 8 6 2 Setting interrupt priority level b b7 50 Timer Aj interrupt control register 2 to 4 LH Addresses 7716 to 79 6 Interrupt priority level select bits When using interrupts set these bits to one
284. de They may be either O or 1 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts A D sweep pin select register 67 06 65 b4 b3 b2 bi 60 A D sweep pin select register Address 1F 16 w mem Rem eem A D sweep pin select bits Valid single sweep and repeat ANo AN 2 pins ni Sweep modes Note 1 ANo to ANs 4 pins ANo to ANs 6 pins ANo to 8 pins Note 2 Nothing is assigned Notes 1 These bits are invalid in the one shot and repeat modes They may be either 0 41 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit of the A D sweep pin select register must be performed while the A D converter halts Rise Geen A erecta A D register i b7 60 A D register i i 0 to 7 Addresses 2016 2216 2416 2616 2816 2A16 2C16 2E16 7 to 0 Reads an A D conversion result RO 17 12 7721 Group User s Manual APPENDIX Appendix 3 Control registers UARTI transmit receive mode register b7 b6 b5 b4 b3 02 bi 60 UARTO transmit receive mode register Address 3016 transmit receive mode register Address 3816 b2 b1 60 0 00 Serial I O disabled P8 functions as a programmable port Clock synchronou
285. der to improve data Parity bit reliability The level of this signal changes according to selection of odd even parity in such a way that the sum of 175 in this bit and character bits is always odd or even number SP H level signal equivalent to 1 or 2 character bits which is added immediately after Stop bit the character bits or parity bit when parity is enabled It indicates finish of data transmission 7721 Group User s Manual 11 33 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 3 Method of transmission Figure 11 4 3 shows an initial setting example for relevant registers when transmitting The difference due to selection of transfer data length 7 bits 8 bits or 9 bits is only that data length When selecting a 7 or 8 bit data length set the transmit data into the low order byte of the UARTi transmit buffer register When selecting a 9 bit data length set the transmit data into the low order byte and bit 0 of the high order byte Transmission is started when all of the following conditions to G are satisfied Transmit is enabled transmit enable bit 1 Transmit data is present in the UARTIi transmit buffer register transmit buffer empty flag 07 G The CTSi input is at L level when the CTS function selected Note When the CTS function is not selected condition is ignored By connecting the pin receiver side and pin transmitter
286. dicates the counter value Note Read from or write to this register in a unit of 16 bits 67 06 05 04 b3 b2 bli b1 b0 00 Timer mode b7 b6 00 fe 01 fie mercedem 10 164 11 fs12 17 24 7721 Group User s Manual APPENDIX Appendix 3 Control registers Event counter mode 015 68 50 Timer BO register Addresses 5116 5016 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits 67 b6 65 64 63 b2 x x Timer Bj mode register j 0 1 Addresses 5816 5 16 m esl erating mode select bits RW Td Event counter mode Ew p Ls m i i b3 b2 RW 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 10 Counts at both falling and rising edges of external signal RW 11 not select Nothing is assigned 425830523325 5232 This bit is invalid in event counter mode its value is undefined at Undefined reading MEL These bits are invalid in event counter mode r 7721 Group User s Manual 17 25 APPENDIX Appendix 3 Control registers Pulse period pulse width measurement
287. dress 1FCCie 67 b6 b5 04 63 02 bi DMA3 mode L Address 1FFCie Buie NK of unit transfer bits 9 16 bits select bit Note 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer 2 Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode Fix this bit to 0 direction select bits 0 0 Fixed 0 1 Forward 10 Backward 1 1 Do not select T f inati b7b6 ransfer destination address 0 0 Fixed 0 1 Forward 10 Backward 1 1 Do not select direction select bits EJ Transfer source address b5b4 Note When the external data bus has width of 8 bits and 1 bus cycle transfer is selected set bit to 1 Fig 13 2 6 Structure of DMAi mode register L 13 14 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 11 DMAi mode register H Figure 13 2 7 shows the structure of DMAi mode register H Bits 0 and 1 are used in 1 bus cycle transfer For details refer to section 13 4 2 1 bus cycle transfer Bits 6 and 7 are the bits for selecting the continuous transfer mode For details refer to section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode 1 Transfer source wait bit and Transfer destination wait bit bits 4 and 5 When each of these bits is set to 1 1 bus cycle in a DMA transfer consumes cycles of and when cleared to 0 2 cycles of
288. dress directions in 2 bus cycle transfer and examples of transfer result 1 External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 bits Data arrangement on transfer source memory Data arrangement on transfer source memory Data arrangement on transfer destination memory transfer result Data arrangement on transfer destination memory transfer result Transfer sequence Transfer sequence Transfer destination Transfer source Fixed Fixed Low Data High order Low order Data High order Data Fixed Forward Low Data High order Low order Low order Data High order Data Fixed Transfer start address 13 34 Backward Low order Data High order 7721 Group User s Manual High order Low order Data Low order Data High order Low order Data High order Data DMA CONTROLLER 13 4 Operation Tables 13 4 3 Address directions in 2 bus cycle transfer and examples of transfer result 2 External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 bits Data arrangement Data arrangement on Data arrangement Data arrangement on Transfer on transfer source transfer destination on transfer source ee transfer destination Source esunaton m
289. dt hold time Note 18 ns these BLE hold time Note 18 ns R W hold time Note 18 ns E pulse width Note 135 ns tsu a DL Data low order setup time after address stabilization Note 130 NS tsuace ol Data low order setup time after rising of ALE Note 135 ns tsua pH high order setup time after address stabilization Note 130 NS tsuate oH Data high order setup time after rising of ALE Note 135 ns Note Figure 13 shows the test circuit 17 92 7721 Group User s Manual Microprocessor mode with Wait lt Write gt 1 Address output Ao A7 Address output As A15 BYTE H Address Data output As Ds A15 D15 BYTE 47 Data input Do Dt15 BYTE 47 Address Data output A16 Do A23 D7 Data input Do D7 ALE output BHE output BLE output R W output Port Pi output i 4 10 Test conditions port Pi Vcc 2 5 10 96 Input timing voltage 1 0 V 4 0 V Output timing voltage 0 8 V 2 0 V tw L tw H APPENDIX Appendix 11 Electrical characteristics td AL E lt gt 959 th d AM E gt ly th E AM td AM E gt ta E DHQ td BLE E td R W E Address gt Data Address Data gt th E BLE th E R W See ee 6 Test conditions except port Pi Vcc 5V 10 96
290. ductor product distributor for further details on these materials or the products contained therein REVISION DESCRIPTION LIST 7721 Group User s Manual DESCRIPTION LIST 7721 REVISION DESCRIPTION LIST 7721 Group User s Manual User s Manual E No date First Edition 970926 1 1 Preface This manual describes the hardware of the Mitsubishi CMOS 16 bit microcomputers 7721 Group After reading this manual the user will be able to understand the functions so that their capabilities can fully be utilized BEFORE USING THIS MANUAL 1 Constitution This user s manual consists of the following chapters Refer to the chapters relevant to the products Chapter 1 DESCRIPTION through Chapter 16 APPLICATION Functions which are common to the M37721S1BFP and the M37721S2BFP are explained using the M37721S2BFP as an example Differences between the M37721S1BFP and the M37721S2BFP are described as notes Appendix Practical information for using the 7721 Group is described 2 Remark Product expansion Refer to the latest catalog and data book or contact the appropriate office as listed in CONTACT ADDRESSES FOR FURTHER INFORMATION on the last page Electrical characteristics Refer to the latest data book Software Refer to 7700 Family Software Manual Development support tools Refer to the latest data book of the development support tools 3 Signal levels in Figure As a rule si
291. e te TA input tsu TAjin TAjour tsu TAjin TAjour tsu TAjour TAj TAjout input cae tsu TAjour TAjin Test conditions Vcc 25V 10 Input timing voltage 1 0 V 4 0 V 17 84 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Timer B input Count input in event counter mode Limits Symbol Parameter Min Max Unit input cycle time one edge count 80 ns tw TBH TBji input high level pulse width one edge count 40 ns tw TBL TBji input low level pulse width one edge count 40 ns TBji input cycle time both edges count 160 ns tw TBH TBjin input high level pulse width both edges count 80 ns tw TBL TBjin input low level pulse width both edges count 80 ns Timer B input Pulse period measurement mode Limits Symbol Parameter Win Maa TBjin input cycle time Note 320 ns tw TBH input high level pulse width Note 160 ns tw TBL input low level pulse width Note 160 ns Timer B input Pulse width measurement mode Limits Symbol Parameter Min Max Unit TBjin input cycle time Note 320 ns tween TBjin input high level pulse width Note 160 ns tw TBL input low level pulse width Note 160 ns A
292. e However Watchdog timer stops operating Table 3 4 1 Microcomputer s state in Hold state Item State Oscillation Operating Operating Stopped at L E Stopped at H Pins Ao Az As Ds to Ais Dis Aie Do to A23 D7 R W Floating BHE BLE Pins ALE ST1 Output L level Pin STO Outputs H level Pin i Outputs clock Pins 4 to P47 P5 to P10 Note Retain the state when Hold request was accepted Watchdog timer Stopped Note This applies when this functions as a programmable I O port 3 4 1 Operation description Judgment of the HOLD pin input level is performed at every falling edge of When L level is detected at judgment of the input level bus request Hold becomes 1 when H level is detected bus request Hold becomes 0 Bus request Hold is sampled within a period when the bus request sampling signal is 1 and bus request is accepted when there is no bus request DRAMC This is called Acceptance of Hold request For bus request refer to section 13 2 1 Bus access control circuit When Hold request is accepted cru stops at L level at the next rising edge of and the STO pin s level becomes the ST1 pin s level becomes L When 1 cycle of has passed after the levels of the STO and ST1 pins are changed the R W BHE BLE pins and the external bus enter the floating state In Hold state wh
293. e address bus and writes data in the data buffer into the specified address The CPU advances to the next processing without waiting for completion of BIU s write operation However if the BIU uses the bus for instruction prefetch when the CPU requires to write data the BIU keeps the CPU waiting Bus control To perform the above operations 1 to 3 the BIU inputs and outputs the control signals and controls the address bus and the data bus The cycle in which the BIU controls the bus and accesses the memory l O device is called the bus cycle Refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES about the bus cycle at accessing the external devices 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 3 Operation of bus interface unit BIU Figure 2 2 3 shows the basic operating waveforms of the bus interface unit BIU About signals which are input output externally when accessing external devices refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 1 When fetching instructions into the instruction queue buffer When the instruction which is next fetched is located at an even address the fetches 2 bytes at a time with the timing of waveform a However when accessing an external device which is connected with the 8 bit external data bus width BYTE H only 1 byte of the instruction is fetched Q When the instruction which is next fetched is located at an odd address
294. e 13 4 8 shows a transfer example in the burst transfer mode edge sense When once a DMA request is accepted in this mode an entire batch of data is transferred the right to use bus is not returned to the CPU until the transfer is complete During a burst transfer any DMA request including that of other channels cannot be accepted However the BUS REQUEST signal is sampled basically at every completion of 1 unit transfer Refer to Table 13 2 3 When a DRAM refresh request or Hold request is generated at this time the right to use bus is not returned to the CPU and the request is accepted When the transfer of an entire batch of data is complete the DMAC relinquishes the right to use bus to the CPU When the next DMA request is generated the right is once returned to the CPU to sample the DMA request Burst transfer mode level sense When the transfer mode select bit 0 and the edge sense level sense select bit 1 this mode is selected Refer to Figures 13 2 6 and 13 2 8 In this mode only the external source is used as a DMA request source Set the DMA request source select bits to 00012 Refer to Figure 13 2 8 Figure 13 4 9 shows a transfer example in the burst transfer mode level sense When the pin s input level L the request bit is cleared to 0 when this pin s input level L the DMAi request bit is set to 1 Therefore when the
295. e called bank When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others the contents of the program bank register is automatically incremented by 1 When a borrow occurs after subtracting the contents of the program counter the contents of the program bank register is automatically decremented by 1 Accordingly there is no need to consider bank boundaries in programming usually This register is cleared 0016 at reset 2 1 7 Data bank register DT The data bank register is an 8 bit register In the following addressing modes using the data bank register the contents of this register is used as the high order 8 bits bank of a 24 bit address to be accessed Use the LDT instruction to set a value to this register This register is cleared to 00 at reset e Addressing modes using data bank register Direct indirect Direct indexed X indirect Direct indirect indexed Y Absolute Absolute bit Absolute indexed X Absolute indexed Y Absolute bit relative Stack pointer relative indirect indexed Y 7721 Group User s Manual 2 5 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 8 Direct page register DPR The direct page register is a 16 bit register The contents of this register indicate the direct page area which is allocated in bank 0 or in the space across banks 016 and 1 The f
296. e next data are satisfied in step G the start bit is generated following the stop bit and the next data is transmitted When performing transmission continuously set the next transmit data in the UARTi transmit buffer register during transmission when the transmit register empty flag 0 When the transmit conditions for the next data are not satisfied the TxDi pin outputs level and the transfer clock stops Figures 11 4 6 and 11 4 7 show examples of transmit timing when the transfer data length 8 bits and Figure 11 4 8 shows an example of transmit timing when the transfer data length 9 bits 11 38 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode Transfer clock Transmit enable bit 5 Data is set in UARTi transmit buffer register Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register TENDi Start bit Parity bit Stop bit TxDi Transmit register empty flag UARTI transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies when the following conditions are satisfied Parity enabled 1 stop bit CTS function not selected TENDi Next transmit conditions are examined when this signal level is H Tenni is an internal signal Accordingly it cannot be read from the external Tc 16 n 1 fi or 16 n 1 fExT fi BRGi s count source frequency
297. e of the last term for processing the second block in Figure 13 8 9 The Bus request caused by DRAM refresh Hold or DMA is sampled while the bus request sampling signal is H and is accepted Fig 13 8 14 Timing diagram of cycle steal transfer mode 5 13 96 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode Precautions for link array chain transfer mode If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed the link array chain transfer mode can be used external data bus width 16 bits or the internal memory is used transfer start address on the address direction fixed side is an even address 7721 Group User s Manual 13 97 DMA CONTROLLER 13 9 DMA transfer time 13 9 DMA transfer time Calculation of time from the relinquishing the right to use bus until its regaining the right under the following conditions is described with reference to cycles of 0 DMAi request is generated while the CPU holds the right to use bus The above right is returned to the CPU after completion of DMA transfer for one DMA request For the time per 1 unit transfer refer to section 13 4 1 2 Bus operation in 2 bus cycle transfer and section 13 4 2 2 Bus operation in 1 bus cycle transfer Also for the time from DMA request generation until the star
298. e oqpiv sig sry eq ev 3 01 8 21 lt steal transfer mode 2 f cycle iagram o ing d im 11 Ti 8 13 19 13 93 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 1 unit transfer 1 unit transfer is performed with a DMAi request on the following conditions Single transfer mode except for the last 1 unit transfer Repeat transfer mode except for the last 1 unit transfer of block Array chain transfer mode except for the first and last 1 unit transfers of each block Link array chain transfer mode except for the first and last 1 unit transfers of each block 1 teaver X Mania X PG Bara Baa aay A16 Do A23 D7 Bus request sampling DMAACKi TC 1 0 DMAC 1 1 CPU i 1 unit transfer 4 Transition of right Transition of right to use bus to use bus The above figure is the example of the second 1 unit transfer for processing the first block in Figure 13 8 9 The Bus request caused by DRAM refresh Hold or DMA is sampled while the Bus request sampling signal is H and is accepted Fig 13 8 12 Timing diagram of cycle steal transfer mode 3 13 94 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode Last transfer of each block At the last term
299. ected When Cycle steal transfer mode selected BUS REQUEST DMAC Bus request sampling DMAACKi TC ST1 STO DMAi interrupt request bit The above timing diagram applies on the following conditions Single transfer mode or Repeat transfer mode 2 bus cycle transfer No Wait e DMAACKi valid TC valid External source DMAREQi After request occurs L is input to the DMAREQi pin the right to use bus is relinquished to DMAC at the shortest time Fig 13 3 2 Example of timing from determination of DMA request until DMA transfer execution 13 24 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 5 Termination of DMA transfer As the methods of terminating DMA transfer normal and forced termination are used 1 Normal termination All of the DMAi transfers terminate and DMAC stops This method is used in the single transfer array chain transfer and link array chain transfer modes In the repeat transfer mode however normal termination cannot be applied to terminating transfer then forced termination must be used Refer to 2 Forced termination of this section Table 13 3 4 lists the states of DMAC at normal termination Table 13 3 4 States of DMAC at normal termination Item interrupt request bit State 1 request bit In the burst transfer mode edge sense 0 In the burst transfer mode level sense not changed In the cy
300. ed by the polarity select bit bit 4 at addresses 7D e to 7F 6 Invalid level This means the reversed level of valid level Data bus Level sense Edge sense i 0 Select bit INTi pin Edge detection 0 circuit Interrupt request bit Interrupt request 1 Fig 7 10 3 INTi Interrupt request When the INTi pin s level changes to the invalid level before an interrupt request is accepted the interrupt Interrupt request is accepted request is not retained Return to main routine Valid X INTi pin level Invalid gt Main routine Main routine First interrupt routine Second interrupt Third interrupt routine routine Fig 7 10 4 Occurrence of INTi interrupt request when level sense is selected 7 20 7721 Group User s Manual INTERRUPTS 7 10 External interrupts INTi interrupt 7 10 2 Switching of INTi interrupt request occurrence factor When the INTi interrupt request occurrence factor is switched in one of the following ways the interrupt request bit may be set to 1 Switching the level sense to the edge sense Switching polarity Therefore after this switching make sure to clear the interrupt request bit to 0 Figure 7 10 5 shows example of the switching procedure for the INTi interrupt request occurrence factor 1 Switching level sense to edge sense 2 Switching polarity Set the interrupt priority level to level 0 Set the interrupt priority le
301. egister 6F16 interrupt control register 7016 conversion interrupt control register 7116 UARTO transmit interrupt control register 7216 UARTO receive interrupt control register 7316 UARTI transmit interrupt control register 7416 UARTI receive interrupt control register 7516 Timer AO interrupt control register 7616 imer A1 interrupt control register 7716 imer A2 interrupt control register 7816 imer interrupt control register 7916 4 interrupt control register 7 16 BO interrupt control register 7B16 imer B1 interrupt control register NNN NPV VP VP VP 7 16 imer B2 interrupt control register 7D16 1 interrupt control register RW 7 16 INT interrupt control register RW 7F16 INT2 interrupt control register RW Notes 5 By writing dummy data to address 6016 the value FFF16 is to the watchdog timer The dummy data is not retained anywhere 6 The value FFF 16 is set to the watchdog timer Refer to CHAPTER 15 WATCHDOG TIMER T It is possible to read the bit state at reading
302. egister write to all 24 bits b23 616 b15 b8 57 bO Destination address register 0 Destination address register 1 Destination address register 2 Addresses 1 16 to 1FE416 Destination address register Addresses 1F F616 to 1FF416 23 to Write SE Undefined RW Set the transfer start address of the destination These bits can be set to 00000016 to FFFFFF 6 Read The read value indicates the destination address of data which is next transferred Note When writing to this register write to all 24 bits Addresses 1FC61e to 1 416 Addresses 1 061 to 1FD416 prae b23 b16 515 b8 b7 bO Addresses 1FCA16 to 1FC816 Addresses 1FDA16 to 1FD816 Addresses 1FEA16 to 1 816 Addresses 1 16 to 1FF8 6 Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 23 to 0 Write Undefined RW Set the byte number of the transfer data These bits can be set to 00000116 to FFFFFF e Read The read value indicates remaining byte number of the transfer data Note When writing to this register write to all 24 bits Do not set this register to 00000016 m Es 17 34 7721 Group User s Manual APPENDIX Appendix 3 Control registers Repeat transfer mode b23 b16 615 08 b7 50 Addresses 1 216 to 1 016 Addresses 1 0216 to 1 016 Addresses 1FE216 to 1FE016 Addres
303. egisters Select an internal clock bit at addresses 3016 3816 O Select the BRGi s count source bits 0 and 1 at addresses 3416 3Cie Set division value 1 00 to to the BRGi addresses 3116 3916 fi Transfer clock s frequency 2 1 fi Frequency of BRGi s count source fe fie 15 2 Enable transmission bit 0 at addresses 3516 3D16 1 Set data to the UARTi transmit buffer register addresses 3216 3A e Pin s state transfer clock is output from the CLKi pin Serial data is output from the TxDi pin Dummy data is output when performing only reception Input of transfer clock from the external A clock input from the CLKi pin is the transfer clock Setting for relevant registers Select an external clock bit 3 at addresses 3016 3816 1 Enable transmission bit 0 at addresses 3516 3D16 1 Set data to the UARTi transmit buffer register addresses 3216 3A Pin s state transfer clock is input from the CLKi pin Serial data is output from the TxDi pin Dummy data is output when performing only reception 7721 Group User s Manual 11 17 SERIAL I O 11 3 Clock synchronous serial mode 11 3 2 Method of transmission Figure 11 3 1 shows an initial setting example for relevant registers when transmitting Transmission is started when all of the following conditions to G are satisfied Wh
304. eive enable bit to 0 reception disabled Q Set the receive enable bit to 1 again reception enabled 2 Method of setting UARTi transmit buffer register again Clear the serial I O mode select bits to 0002 serial I O invalid Set the serial I O mode select bits again Set the transmit enable bit to 1 transmission enabled and set the transmit data to the UARTi transmit buffer register 11 46 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 8 Sleep mode This mode is used to transfer data between the specified microcomputers which are connected by using UARTI The sleep mode is selected by setting the sleep select bit bit 7 at addresses 3016 3816 to 1 when receiving In the sleep mode receive operation is performed when the MSB De when the transfer data is 9 bits length D7 when it is 8 bits length De when it is 7 bits length of the receive data is 1 Receive operation is not performed when the MSB is 0 The UARTi receive register s contents are not transferred to the UARTi receive buffer register Additionally the receive complete flag and error flags do not change and a UARTi receive interrupt request does not occur The following shows an usage example of the sleep mode when the transfer data is 8 bits length Set the same transfer data format for the master and slave microcomputers Select the sleep mode for the slave microcomputers
305. emory memory transfer result memory memory transfer result Forward Fixed Low order Low order x Data 1 High order Low order Data 2 High order Low order Data 3 High order Forward Forward Low order Low order sk Data 1 Data 1 High order High order Low order Low order Data 2 Data 2 High order High order Low order Low order Data 3 Data 3 High order High order Forward Backward Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Note The position relationship between low order byte and high order byte is not reversed Transfer start address 7721 Group Users Manual 13 35 DMA CONTROLLER 13 4 Operation Tables 13 4 4 Address directions in 2 bus cycle transfer and examples of transfer result 3 External data bus width 16 bits or 8 bits Adaress direction Transfer unit 16 bits Transfer unit 8 bits Data arrangement Data arrangement on Data arrangement Data arrangement on Transfer ee on transfer source transfer destination on transfer source transfer destination Source esunanon memory seguence memory transfer result memory q memory transfer result Backward Fixed Law order Low order Data Data 3 m 1 3 Low order Data 2 High order Low order Data 1 High order Back F 21 ackward orward Low order Low order Data 3 Data 1 71 High order
306. en an external clock is selected satisfy conditions to with the following precondition satisfied lt Precondition gt The CLKi pin s input is at H level Note When an internal clock is selected the above precondition is ignored Transmission is enabled transmit enable bit 1 Transmit data is present the UARTi transmit buffer register transmit buffer empty 0 The CTS pin s input is at L level when the CTS function selected Note When the CTS function is not selected condition is ignored By connecting the RTSi pin receiver side and CTSi pin transmitter side the timing of transmission and that of reception can be matched For details refer to section 11 3 5 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 3 2 shows writing data after start of transmission and Figure 11 3 3 shows detection of transmit completion 11 18 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 57 50 Clock synchronous serial I O mode Internal External clock select bit 0 Internal clock 1 External clock NC
307. en the HOLD pin s input level becomes H the STO and ST1 pins levels are changed at the next rising edge of When 1 cycle of has passed after the levels of the STO 571 pins changed the microcomputer terminates Hold state Figures 3 4 1 to 3 4 3 show timing of acceptance of Hold request and termination of Hold state Note has the same polarity and the same frequency as clock However stops by acceptance of Ready request or executing the STP or WIT instruction Accordingly judgment of the input level of the HOLD pin is not performed during Ready state 3 12 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function lt When inputting L level to HOLD pin while bus is unused gt State when inputting L level to HOLD pin External data bus Data length External data bus width 8 8 16 Unused External address bus Floating A B External data bus JA Addressa O adress External address bus Floating ese Xr Bus request Hold Note 2 Bus request sampling Note 2 Hold state Bus not in use EIN Transfer of right to use bus Transfer of right to use bus Bus in use This is the period in which the bus is not used so that not a new address but the address which was output immediately before is output again Notes 1 Clock has the same polarity and the same frequency as 9 Timing of signals to be input f
308. ence for b without executing the main rou tine not even one instruction It is because that sampling is completed while executing the RTI instruction Interrupt request b Sampling pulse 1 RTI instruction Interrupt routine a gt sequence for interrupt b If the next interrupt request b occurs immediately after sampling pulse is generated the microcomputer executes one instruction of the main routine before executing the INTACK sequence for b It is because that the interrupt request is sampled by the next sampling pulse Interrupt request b Sampling pulse ral RTI instruction One instruction executed Interrupt routine a gt lt Main routine INTACK sequence for interrupt b 17 68 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A Interrupt Suppose that there is a routine which should not accept one certain interrupt request The other interrupt request are acceptable Although when the interrupt priority level select bits for the above interrupt are set to 0002 in other words when this interrupt is set to be disabled this interrupt request is actually accepted immediately after change of the priority level Why did this occur and what should do about it Interrupt request is LDM 00H XXXIC Writes 0002 to interrupt priority level select bits accepted in this gt Clears interr
309. endix 10 APPENDIX Memory assignment of 7721 Group Memory assignment in SFR area Control registers Package outline Examples of handling unused pins Machine instructions Hexadecimal instruction code table Countermeasure against noise 7721 GroupQ amp A Differences between 7721 Group and 7720 Group Appendix 11 Electrical characteristics Appendix 12 Standard characteristics APPENDIX Appendix 1 Memory assignment of 7721 Group Appendix 1 Memory assignment of 7721 Group Microprocessor mode M37721S2BFP M37721S1BFP SFR area SFR area SFR area 00000016 00007 00008016 3 2 00000216 512 bytes Sa e ofina RAMarea Internal RAM area E 512 bytes Note 2 ire onda 00027Ft6 Internal RAM area Case of internal RAM area 512 bytes f select bit 1 00047F 6 2 External area External area 001 016 Notes 1 Interrupt vector table is assigned to addresses to FFFFi6 SFR area SFR area Make sure to set a ROM to this area 001FFF 6 2 For the M37721S1BFP fix the internal RAM area select bit to 0 Y OOFFFF 6 01000016 External area Bank 116 Note 1 Note 1 01 16 A 000016 Bank FF16 Y FFFFFF e Fig 1 Memory assignment microprocessor mode 17 2 7721 Group User s Manual APPENDIX Appendix 2 Memory assignment in SFR area Appendix 2 Memory assignm
310. ength flag x operation or is applied when flag m or x 0 operation or is applied when flag m or x Em The setup of flags m and x and the selection of the external data bus width do not affect each other 7721 Group User s Manual 3 5 CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices Fig 3 1 2 Examples of operating waveforms of signals input from or output to the external 1 3 6 External data bus width 16 bits BYTE L lt 16 bit data access gt a Access beginning at even address ALE Aoto A7 As Ds to A15 D15 A16 Do to A23 D7 Das Data even BLE BHE N b Access beginning at odd address ALE Ao to As Dsto Ars Dis __ X Are Doto __XAdaress X Address XDataloven 8 bit data access C Access to even address E ALE Aoto Ar As Ds to A15 D15 Address Data even A16 Do to A23 D7 BLE d Access to odd address Bo ALE Aoto Ar Data odd BLE N BHE N As Ds to A15 D15 A16 Do to A23 D7 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices External data bus width 8 bits BYTE H lt 8 16 bit data access gt e Access beginning at even address E ALE N N Moto Ar As to Ais Az D X Address
311. ent in SFR area Access characteristics RW It is possible to read the bit state at reading The written value becomes invalid The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid RO WO It is possible to read the bit state at reading The written value becomes valid State immediately after reset 0 0 meaa y Ri reset 0 Always 0 at reading 1 1 immediately after reset tr 2 Undefined immediately after LL Always 1 at reading reset Always undefined at reading XN 0 immediately after reset Fix this bit to 0 Address Register name Access characteristics State immediately after reset b7 50 b7 50 016 116 216 316 416 E 516 616 716 816 916 16 Port P4 register 2 01010 16 Port P5 register 2 Port P4 direction register 0 0 0 0 0 0 0 0 D16 Port P5 direction register 0016 E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 0016 1116 Port P7 direction register 0016 1216 Port P8 register 1316 Port P9 register 2 1416 Port P8 direction register 0016 1516 Port P9 direction register 0016 1616 Port P10 register 1716 2 1816 Port P10 direction register 0016 1916 1 16 Pulse output data register 0 1 16 2 1 16 Pulse outpu
312. epted until the DMA transfer which is in progress normally terminates or is forced into termination If a DRAM refresh request a Hold request or another DMA request including that of other channels is generated during a data transfer in the cycle steal transfer mode the bus request with the highest priority is accepted at the above mentioned bus request sampling If only several DMA requests are generated the request of the channel whose priority is highest is accepted If any bus request is not generated at the above mentioned bus sampling the right to use bus is relinquished to the CPU Note that no DMA request is accepted in array states 13 8 7721 Group User s Manual DMA CONTROLLER 13 2 Block description E DRAM refresh This is the term in which the bus is not used so that sampingis performed every 1 cycle of Sampling is performed after completion of Refresh request a refresh cycle G Sampling is performed after completion of BUS REQUEST DRAMC 1 bus cycle Bus request sampling ST1 STO Refresh gt Dy Refresh efres Bus used by efres Transition of right Transition of right CPU Transition of right Transition of right to use bus to use bus to use bus to use bus This is the term in which the bus is not used so that sampling is performed every 1 cycle of HOLD Q This is at Hold state so that sampling is performed every 1 cycle of Sampling is performed after completi
313. er 1 bus transfer timing DMAACKi output Aa8 D8 A15 D15 output BYTE L Do Dt5 input A16 Do A23 D7 output Do D7 output tw ALE td ALE E ALE output I lt gt th E BHE lt gt td BHE E 5 th E BHE BHE output Xl TKX ta BLE E 9 th E BLE lt gt td BLE E th E BLE gt l R W E le th E R W gt td R W E th E R W Test conditions Vcc 5V 10 96 Output timing voltage 0 8 V 2 0 V Do D15 input 0 8 V 2 5 V 17 100 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics At DMA transfer Transfer complete timing 91 oF Ne NS AENA AS TS E TC ta o1 STi 01 571 STO td 1 DAK DMAACKi th E AL gt td AL E Le th E DHQ GY Data MK Address XA BYTE 1 aA Data oes Address _ Data th E AM gt ta AM E BYTE Address Address Address le th E DLQ gt la AH E ALE output gt th E BHE gt th E BLE td BLE E gt th E R W td R W E R W output NEU III NEN Test conditions 2 5V 10 96 Output timing voltage 0 8 V 2 0 V Do Dt5 input 0 8 V 2 5 V 7721 Group User s Manual 17 101 APPENDIX Appendix 11 Electrical cha
314. er mode From preceding Figure 13 7 4 Selection of priority level and TC pin and setting DMAi request bit to 0 N b7 bO o o o o DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P105 pin functions as a programmable 1 port 1 Valid p 10 pin functions as TC pin DMAO request bit request bit request bit DMAS request bit 0 No request DMAC control register H Address 6916 Software DMAi request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit enable bit Di enable bit ERES DMAG enable bit When selecting external When selecting internal When selecting internal DMA DMA source DMA source source except software bat Rt Rl ee EE EE EE EE EE EE E E E E EE EEN When selecting software DMA request Inputting DMA request Interrupt request of each peripheral signato DMARESI pin DMAC control register H Address 6916 function occurs Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit 1i R Software DMA3 request bit Requested When writing 1 DMA request is generated EEEE LELLI DMA transfer starts Fig 13 7 5 Initial setting
315. er s Manual APPLICATION 16 1 Memory connection Table 16 1 4 Calculation formulas and Values for each parameter in Figure 16 1 5 unit ns Calculation formulas and Values No Wait Wait twEL 2 X 10 4 X 10 f Xin iE d E DLQ 35 ta E DHa th E DLa 1 X 10 th E DHa 22 Wait No Wait o 13 14 15 16 17 18 19 20 21 22 23 24 25 External clock input frequency f XIN MHz Fig 16 1 6 Relationship between tsup f Xin 7721 Group User s Manual 16 9 APPLICATION 16 1 Memory connection Timing for writing data to DRAM td E CASL DRAM write signal W A td E DLO DHQ Address output and Data I O AUD Address A16 Do A23 D7 gt gt This applies when the external data bus has a width of 16 bits BYTE L h E DLQ DHQ ___ Specifications of the M37721 The others are specifications of DRAM Fig 16 1 7 Timing for writing data to DRAM Data hold time ton lt tae cast th E DLa DHa Table 16 1 5 lists the calculation formula and value for each parameter in Figure 16 1 7 Figure 16 1 8 shows the relationship between tox and f Xin 16 10 7721 Group User s Manual APPLICATION 16 1 Mem
316. erating Pins Retains the same state in which the WIT instruction was executed Operation after By interrupt request occurrence Supply of cPU and 6 starts just after the termination By hardware reset Operates in the same way as hardware reset Wait mode Note The refresh timer operates but DRAM refresh is not performed because the bus request DRAMC does not occur Refer to section Appendix 9 7721 Group Q amp A 7721 Group User s Manual 5 9 CLOCK GENERATING CIRCUIT 5 4 Wait mode 1 2 5 10 Termination by interrupt request occurrence When an interrupt request occurs supply of and starts Q The interrupt request which occurred in is accepted The following interrupts are used to terminate Wait mode When a watchdog timer interrupt request occurs Wait mode is also terminated interrupt i 0 to 2 Timer Ai interrupt i O to 4 Timer Bi interrupt i O to 2 UARTiI transmit interrupt i 0 1 UARTi receive interrupt i 0 1 A D converter interrupt Note Refer to CHAPTER 7 INTERRUPTS and each functional description about interrupts Before executing the WIT instruction interrupts used to terminate Wait mode must be enabled In addition the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the processor interrupt priority level IPL of the routine where the WIT instruction is executed When multiple
317. eriod Pulse width measurement mode In this mode the timer measures an external signal s pulse period or pulse width Refer to Table 9 5 1 Timers BO and 1 be used in this mode Figure 9 5 1 shows the structures of the timer Bj mode register and timer Bj register in the pulse period pulse width measurement mode Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBjm pin Pulse width measurement The timer measures the pulse width L level and H level widths of the external signal that is input to the TBjin pin Table 9 5 1 Specifications of pulse period pulse width measurement mode Item Specifications Count source Count operation f2 f16 164 or f512 Countup Counter value is transferred to the reload register at valid edge of measurement pulse and counting continues after clearing the counter value to 000016 When the count start bit is set to 1 When the count start bit is cleared to 0 When valid edge of measurement pulse is input Note 1 When a counter overflow occurs Timer Bj overflow flag is set to 1 simultaneously Measurement pulse input Count start condition Count stop condition Interrupt request occurrence timing TBjIN function Read from timer Bj register The value obtained by reading timer Bj register is the reload register s contents Measurement resul
318. errupt processing starts from the cycle just after the completion of the instruction which was executed at accepting the interrupt request Figure 7 7 1 shows the sequence from acceptance of interrupt request to execution of interrupt routine After execution of an instruction at accepting the interrupt request is completed an INTACK Interrupt Acknowledge sequence is executed and a branch is made to the start address of the interrupt routine allocated in addresses 016 to FFFF e The INTACK sequence is automatically performed in the following order The contents of the program bank register PG just before performing the INTACK sequence are pushed onto stack The contents of the program counter PC just before performing the INTACK sequence are pushed onto stack The contents of the processor status register PS just before performing the sequence is pushed onto stack The interrupt disable flag 1 is set to 1 The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level IPL The contents of the program bank register PG are cleared to 0016 and the contents of the interrupt vector address are set into the program counter PC Performing the INTACK sequence requires at least 13 cycles of internal clock Figure 7 7 2 shows the INTACK sequence timing After the INTACK sequence is completed the instruction execution starts from the start address of t
319. escriptions 12 14 7721 Group User s Manual A D CONVERTER 12 5 One shot mode 4 A D control register b7 50 olo A D control register address 1216 Analog input select bits b2 b1 bo 0 0 0 ANo selected AN selected AN2 selected ANs selected AN4 selected ANs selected ANe selected AN7 selected One shot mode Trigger select bit 0 Internal trigger 1 External trigger A D conversion start bit 0 Stop A D conversion A D conversion frequency AD select bit 0 divided by 4 L 1 f2 divided by 2 priority level b7 b0 A D conversion interrupt control register address 7016 Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt Set to a level 0 when disabling this interrupt ePort P7 direction register b7 bo Port P7 direction register address 1116 A D conversion start bit to 1 b7 1 T register address 16 9 A D conversion start bit ANo bits corresponding AN3 to analog input pins to 0 AN4 Set bit 7 to 0 when ANs selecting external trigger AN7 When external trigger is selected v Input falling edge to
320. esses 5Bie to 5016 m ae 77 Operating mode select bits Timer mode Event counter mode Pulse period Pulse width measurement mode Do not select Rw Undefined Undefined Note RW Note Bit 5 is invalid in the timer and event counter modes its value is undefined at reading Fig 9 2 3 Structure of timer Bi mode register 7721 Group User s Manual 9 5 TIMER B 9 2 Block description 9 2 4 Timer Bi interrupt control register Figure 9 2 4 shows the structure of the timer Bi interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS 67 06 b5 64 b3 62 bi b0 Timer Bi interrupt control register i 0 to 2 Addresses 7 16 to 7 16 ae Stamens Level 0 Interrupt disabled RW Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 Level 6 Level 7 High level 3 Interrupt request bit 0 No interrupt requested RW 1 Interrupt requested Nothing is assigned Fig 9 2 4 Structure of timer Bi interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a timer Bi interrupt s priority level When using timer Bi interrupts select one of the priority levels 1 to 7 When a timer Bi interrupt request occurs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when i
321. essor mode register 1 2 52 55 9 49 59 2 209 209 50 2 45 5 ND 50 Notes 1 The access characteristics at addresses 4 16 to 4216 vary according to Timer A s operating mode Refer to CHAPTER 8 TIMER A 2 The access characteristics at addresses 5016 to 5316 vary according to Timer B s operating mode Refer to CHAPTER 9 TIMER B 3 The access characteristics for bit 5 at addresses 5 16 and 5C16 vary according to Timer B s operating mode Bit 5 at address 5016 is invalid Refer to CHAPTER 9 TIMER B Bit 1 at address 5F16 becomes 0 immediately after reset For the M37721S1BFP fix this bit to 0 Fig 4 1 6 State of SFR and internal RAM areas immediately after reset 3 7721 Group User s Manual 4 7 RESET 4 1 Hardware reset Address Register name Access characteristics State immediately after reset b7 bO b7 50 6016 Watchdog timer register Note 5 6 6116 Watchdog timer frequency select register 6216 Real time output control register 6316 6416 DRAM control register 6516 6616 Refresh timer 6716 6816 DMAC control register L Note 7 6916 DMAC control register H RW 6A16 6816 6 16 interrupt control register 6D16 interrupt control register 6E16 interrupt control r
322. estination wait bit Valid in DMA transfer 0 Wait 1 No wait Selection of single transfer mode 623 b16 b15 08 b7 5057 b0b7 bo Source address register 0 Addresses 1FC2 e to 1FC0 e SARO Source address register 1 Addresses 1FD216 to 1FDO16 SAR1 Source address register 2 Addresses 1 216 to 1 016 SAR2 Source address register Addresses 1 216 to 12016 SAR3 Set the transfer start address of transfer source These bits can be set to 00000016 to FFFFFF ie 558 0160015 08 Destination address register 0 Addresses 1FC616 to 1 416 DARO Destination address register 1 Addresses 1FD616 to 1FD416 DAR1 Destination address register 2 Addresses 1 16 to 1FE416 DAR2 Destination address register Addresses 1FF616 to 1FF416 DAR3 Set the transfer start address of destination These bits can be set to 00000016 to FFFFFF ie b23 b16 b15 b8 b7 5057 6067 50 Transfer counter register 0 Addresses 1 1 to 1 816 TCRO 1 Transfer counter register 1 Addresses 1FDA16 to 1FD816 TCR1 Transfer counter register 2 Addresses 1FEA e to 1 816 TCR2 Transfer counter register 3 Addresses 1FFA16 to 1 816 TCR3 Set the byte number of transfer data These bits can be set to 00000116 to FFFFFF 16 Note 3 When data is transferred from memory to 1 in 1 bus
323. evel input voltage 4 4 5 5 7 77 P80 P87 9 9 10 10 RDY 9 8 Vcc Vcc V HOLD BYTE CNVss RESET Xin Vner Vin High level input voltage As Ds A s D s A16 Do Az3 D7 0 5 Vcc Vcc V Low level input voltage P4s P47 5 5 P6o P67 7 77 P8o P87 P9o P9 P10o P107 RDY 0 0 2 V HOLD BYTE CNVSS RESET Xm VREF Vu Low level input voltage As Ds Ais Dis A1e Do Az3 D7 0 0 16 V loH peak High level peak output current As Ds A15 D15 Aie Do Az3 D7 P4s P47 P5o P57 P60 P67 7 7 P80 P87 10 mA 90 9 P100 P107 RESETour STO ST1 ALE BLE BHE R W avg High level average output As Ds A15 Dis current Aie Do Az23 D7 P43s P47 5 5 P6o P6 P7o P77 P80 P87 5 mA 90 97 P10o P107 RESETour STO ST1 ALE BLE BHE R W peak Low level peak output current As Ds A15 Dis A e Do Aes Dz PAs P47 P5o P57 P6o P6 P7o P77 P80 P87 10 mA 90 9 100 107 RESETour STO ST1 ALE BLE BHE R W avg Low level average Ao MAc A7 MAz7 As Ds Ais D15 output current Aie Do Az23 D7 P43s P47 5 5 P60 P67 P7o P77 P80 P87 5 mA P9o P9 P100 P107 RESETour STO ST1 ALE BLE BHE R W f Xin External clock input frequency 25 MHz
324. evels 1 to 7 When disabling interrupts set these bits to level 0 x Setting port P5 direction register b7 50 Port P5 direction register Address D16 21 pin TASIN pin 41 pin When gate function is selected set the bit corresponding to the TAjin pin to 0 Setting count start bit to 1 b b7 50 Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count starts Fig 8 3 3 Initial setting example for registers relevant to timer mode 2 8 12 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 2 Count source In the timer mode the count source select bits bits 6 and 7 at addresses 5616 5 select the count source Table 8 3 2 lists the count source frequency Table 8 3 2 Count source frequency Count source Count source frequency select bits source b7 b6 8 MHz f Xin 16 MHz f Xin 25 MHz 0 0 f2 4 MHz 8 MHz 12 5 MHz 0 1 fie 500 kHz 1 MHz 1 5625 MHz 1 0 fea 125 kHz 250 kHz 390 625 kHz 1 1 1512 15625 Hz 31250 Hz 48 8281 kHz 7721 Group User s Manual 8 13 TIMER A 8 3 Timer mode 8 3 3 Operation in timer mode When the count start bit is set to 1 the counter starts counting of the count source When a counter underflow occurs the re
325. example for registers relevant to array chain transfer mode 3 13 74 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode 13 7 3 Operation in array chain transfer mode Figure 13 7 6 shows the operation flowchart of the array chain transfer mode and Figures 13 7 7 and 13 7 8 show timing diagrams of the array chain transfer mode burst transfer mode For the cycle steal transfer mode refer to the following Transfer of transfer parameters in an array state Figures 13 8 10 and 13 8 11 All transfers except in an array state and except the last 1 unit transfer of each block Figure 13 8 12 Last 1 unit transfer of each block except the last block Figure 13 8 13 Last 1 unit transfer of the last block Figure 13 8 14 The processing performed in the array chain transfer mode consists of an array state and a transfer state 1 Array state In an array state transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi DARi and TCRi and their latches As shown in Figure 13 7 2 a transfer parameter consists of 4 bytes 24 bits of data 8 bits of dummy data One bus cycle always consumes cycles of During an array state the DMAACKi pin outputs H level For the bus request sampling in an array state refer to section 13 2 1 Bus access control circuit 2 Transfer state Data is transferred in a transfer state For the bus request sam
326. f an entire batch of data is applied It is also valid while the CPU has the right to use bus 7721 Group User s Manual 13 19 DMA CONTROLLER 13 3 Control 13 3 2 DMA requests 1 DMA request sources DMA request sources are specified by the DMA request source select bits and the edge sense level sense select bit Refer to Figure 13 2 8 Table 13 3 2 lists the conditions for generating a DMA request Table 13 3 2 Conditions for generating DMA request Condition for generating DMA request DMA request sources External source Level sense L level input to the DMAREQi pin only in the burst transfer mode DMAREQi Edge sense Change of the DMAREQi input pin s level from to L A write of 1 to the software request bit each of bits 0 3 at address 6916 refer to Figure 13 2 5 When the interrupt request bit of each peripheral is set to 1 by the activity of peripherals If 1 is written to any of these interrupt request bits by software the DMAi request bit does not change Also whatever value within 0 7 an interrupt priority level takes this does not affect DMA requests Software DMAi request Timers 0 4 Timers 0 2 UARTO UART1 A D converter 2 Change of DMAi request bit A read of the DMAi request bits each of bits 4 7 at address 6816 indicates whether the corresponding channel 0 3 is generating its DMA request or not
327. for DRAM control bus timing depending of f Xin Vcc 5 V 10 Vss 0 V Ta 20 to 85 Read Symbol Calculation formula Unit Symbol Calculation formula Unit tw RASL 4 X 10 5 4 10 40 ns a ns f Xin f Xin ia tw CASL 3 X 10 ta R W RAS 1 X 10 27 5 ns ns f Xin Be tw t RASH 2 X 10 _ 20 ns h CAS R W 1 X 10 2155 H f Xin ta RAs cas 1 X 10 1 X 10 12 ns UY 4 25 ns f Xin 5 1 10 ta E CAsL 1 X 10 Bee ns 37 5 ns f Xin m f Xin th RAS RA 1 X 10 m nis Write Symbol Calculation formula Unit Symbol Calculation formula Unit tw RASL 4 X 10 la CA CAS 1 X 10 pe 0 ns EU Xin D S lw CASL 2 x 10 3 10 25 ns ns i w tarw tw RASH 2 109 _ 20 d R W RAS 1 109 _ 55 H f Xin latRAS CAS 2 X 10 th CAS R W 1 X 10 gt 20 ns SER LADO ns f Xin ta RA RAS 1 10 ta E CAsL 2 X 10 EMO ups ns 35 0 ns xw 3500 th RAS RA 1 X 10 E Hs f Xin x The value within is for the minimum value Refresh Symbol Calculation formula Unit Symbol Calculation formula Unit tw RASL 4 X 10 la CAS RAS 1x10 40 ns 22 ns f Xin f Xin lw CASL 2 x 10 lh RAS CAS 1 X 10 25 ns 2 29 ns f Xin f XiN 7721 Group User s Manu
328. fresh request or a Hold request is generated during DMA transfer or if TC input is driven from H to L to force DMA transfer into termination DMAC relinquishes the bus after completion of 8 bit data transfer which is being performed at that time 16 bit transfer A minimum unit of DMA transfer is 16 bits that is a 16 bit data is transferred for one DMA request in the cycle steal transfer mode In the burst transfer mode if a DRAM refresh request or a Hold request is generated during DMA transfer or if TC input is driven from H to L to force DMA transfer into termination DMAC relinquishes the bus after completion of 16 bit data transfer which is being performed at that time 7721 Group User s Manual 13 3 DMA CONTROLLER 13 1 Overview 3 Transfer modes Burst transfer mode When once a DMA request is accepted in this mode an entire batch of data is transferred Neither is the right to use bus returned to the CPU nor the DMA request of the channel with the higher priority is accepted until the transfer is complete However if an external source DMAREQi is selected as a DMA request source with the level sense selected DMA transfer is performed when the DMAREQi pin s input level is L and the right to use bus is returned to the CPU when the pin s input level is Even in this case any DMA request of the other channels is not accepted until the entire batch of data has been transferre
329. g See 4 above It is impossible to read the bit state The value is undefined at reading However when 0 at reading is indicated in the Function or Note column the bit is always 0 at reading See 4 above The written value becomes invalid Accordingly the written value may be 0 or 1 Table of contents Table of contents CHAPTER 1 DESCRIPTION Tu POT 1 2 1 2 Pin connvaiesiuacnseduesccndccdshessusaceuasasoscastecunsauvacddoussannauteesavsnetees 1 3 1 4 DENEN cn eater 1 7 CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing cccccccscceseccececescececcscscssssnsneseneneeeneeeeeeeseeeeneususesueceeacacscasssseseees 2 2 HR 2 3 M 2 3 Hv 2 3 uw 2 4 2 1 5 Program counter Fe ona edd nada an ee de a Pena eee d rau 2 5 2 1 6 Program bank register 2 5 eco 2 5 2 1 8 Direct page register 2 6 Pe nr er 2 7 2 2 ENIIICISEUIMI LA MERECE 2 9 2 9 On nterface unit BILL mmm 2 11 M 2 13
330. g 7 4 1 Interrupt priority level set by hardware 7721 Group User s Manual 7 9 INTERRUPTS 7 5 Interrupt priority level detection circuit 7 5 Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt with the highest priority level when more than one interrupt request occurs at the same sampling timing Figure 7 5 1 shows the interrupt priority level detection circuit Interrupt priority level Level 0 initial value CERE Interrupt priority level A D conversion Timer A4 UART1 transmit Timer A3 lt UART1 receive Timer A2 UARTO transmit Timer 1 UARTO receive Timer AO Timer B2 Timer B1 Em AB RN i Timer BO F lt SEE Interrupt with the highest priority leve NM Processor interrupt priority level lt Interrupt disable flag 1 Watchdog timer interrupt FD Accepting of interrupt request Reset Fig 7 5 1 Interrupt priority level detection circuit 7 10 7721 Group User s Manual INTERRUPTS 7 5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority detection circuit using Figure 7 5 2 The interrupt priority level of a requested interrupt Y in Figure 7 5 2 is compared with the resultant priority level which is sent from the preceding comparator X in Figure 7 5 2 the interrupt with the
331. g of bus request sampling 7721 Group User s Manual 13 9 DMA CONTROLLER 13 2 Block description 13 2 2 DMAC control register L Figure 13 2 4 shows the structure of DMAC control register L Bit 0 is described in section 13 3 3 Channel priority levels and bits 4 7 are also in section 13 3 2 DMA requests 1 TC pin validity bit Bit 1 When this bit is set to 1 port P10s functions as the TC pin The TC pin is of an N channel open drain type and provides the following functions Terminal count signal output When the transfer of an entire batch of data is normally terminated the pin outputs L for 1 cycle of Refer to section 13 3 5 1 Normal termination Forced termination signal input When the TC pin s input level goes from H to L during DMA transfer this DMA transfer is forced into termination Refer to section 13 3 5 2 Forced termination 67 06 b5 64 63 62 bi 00 DMAC control register L Address 6816 EX Priority select bit Sieh TC validity bit 0 Invalid RW P10s pin functions as a programmable I O port CMOS 1 Valid m P103 pin functions as TC pin N channel open drain Nothing is assigned 0 No request Rw 1 Requested Note 1 rw s ____ Notes 1 The state of bits 4 to 7 is not changed when writing 1 to these bits 2 When writing to this register while any of enable bits
332. g of transmission and that of reception can be matched When an internal clock is selected do not use the RTS function It is because the RTS output becomes undefined Figure 11 3 10 shows a connection example The receive operations are described below The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the rising edge of the transfer clock The contents of the UARTi receive register are shifted by 1 bit to the right Steps and are repeated at each rising edge of the transfer clock When 1 byte data is prepared in the UARTi receive register the contents of this register are transferred to the UARTi receive buffer register Simultaneously with step the receive complete flag is set to 1 and UARTi receive interrupt request occurs and its interrupt request bit is set to 1 The receive complete flag is cleared to 0 when the low order byte of the UARTi receive buffer register is read out The RTSi pin outputs H level until the receive conditions are next satisfied when selecting the RTS function Figure 11 3 11 shows the receive operation and Figure 11 3 12 shows an example of receive timing when selecting an external clock Transmitter side Receiver side Fig 11 3 10 Connection example 7721 Group User s Manual 11 27 SERIAL I O 11 3 Clock synchronous serial I O mode UARTI receive regis
333. g the program s execution point 2 address to another location Bus control signal A generic name for ALE E R W BLE BHE RDY HOLD HLDA BYTE STO and ST1 signals Countdown Means decreasing by 1 and counting Countup Count source A signal that is counted by timers A and B the UARTi baud rate register BRGi and the watchdog timer That is f2 f16 fe4 1512 selected by the count source select bits and others Countup Means increasing by 1 and counting Countdown External area An accessible area for external devices connected It is up to 16 Mbyte external area Internal area External bus A generic name for the external address bus and the external data bus External device Devices connected externally to the microcomputer A generic name for a memory an I O device and a peripheral IC Internal area An accessible internal area A generic name for areas of the internal RAM and the SFR External area Interrupt routine A routine that is automatically executed when an interrupt request is accepted Set the start address of this routine into the interrupt vector table Overflow A state where the countup resultant is greater than the counter resolution Underflow Countup Read modify write instruction An instruction that reads the memory contents modifies them and writes back to the same address Relevant instructions are the ASL ASR CLB DEC INC LSR ROL ROR SEB instruction
334. gains the right to use bus after the DRAM refresh ends or the Hold state is removed When DMA request is generated while CPU uses bus Upon end of the bus cycle DMAC gains the right to use bus if any DRAM refresh request or Hold request is not generated at that time If a DRAM refresh request or a Hold request is generated when the bus cycle ends DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed For details refer to section 13 2 1 Bus access control circuit and bus request sampling signals in timing diagrams 13 1 3 Modes DMAC has the following transfer methods and modes Because these methods and modes are independent each other any combination between them is selectable 1 2 Data transfer method B 2 bus cycle transfer This is a method used to transfer data between memories A DMA transfer consumes 2 cycles a read and a write cycle of data For details refer to section 13 4 1 2 bus cycle transfer 1 bus cycle transfer This is a method used to transfer data between a memory and an I O A read and write of data is carried out at the same time in 1 bus cycle so that high speed transfer can be accomplished For details refer to section 13 4 2 1 bus cycle transfer Transfer unit B 8 bit transfer A minimum unit of DMA transfer is 8 bits that is an 8 bit data is transferred for one DMA request in the cycle steal transfer mode In the burst transfer mode if a DRAM re
335. ge lon 400 uA 4 8 V VoL Low level output AyMAoc Az MA As Ds A15 D1s voltage 23 07 4 4 P5o P57 etos dA 2 y P7o P77 P80 P87 P90 P97 P10c P107 i STO ST1 ALE BLE R W Low level output AyMAoc Az MA As Ds A15 D1s voltage 0 07 MAs MAs RAS CAS STO ST1 lo 2 mA 0 45 V BLE BHE R W Vo Low level output ALE lo 10 mA 19 V voltage lo 2 mA 0 43 Vo Low level output lo 10 mA 1 6 voltage lo 2 mA 0 4 Vr Vr Hysteresis HOLD RDY 2 4 INToINT2 CTS CTS CLK 0 4 1 V DMAREQO DMAREQ3 Vr Vr Hysteresis RESET 0 2 0 5 V Vr Vr Hysteresis 0 1 0 3 V High level input As Ds A1s Dis A1e Do Azs D7 P4s P47 P5o P57 current P60 P67 P7o P77 P80 P87 9 P10c P107 RDY HOLD BYTE CNVss ES Xin RESET Low level input As Ds A15 D15 16 P4s P47 50 57 current P60 P67 7 77 P8 amp v P8 9 P100 P107 Vi 0 V 5 RDY HOLD BYTE CNVss Xin RESET Vram hold voltage When clock is stopped 2 V Icc Power source current f Xw 25 MHz Square 27 54 mA waveform Ta 25 C when clock 1 is stopped Ta 85 C when clock 20 uA is stopped A D CONVERTER CHARACTERISTICS Vcc 5 V Vss 0 V 20 to 85 C 25 MHz unless other
336. gh level pulse width Note 60 ns taras cas RAS CAS delay time Note 60 ns tara Ras Row address delay time before RAS Note 5 ns t mas Row address hold time after RAS Note 18 ns taca cas Column address delay time before CAS Note 10 ns tncas ca Column address hold time afrer CAS Note 60 ns 5 R W delay time before RAS Note 18 ns thicas rw R W hold time after CAS Note 18 ns tae rast RAS delay time after E s low level 30 NS tae cast CAS delay time after E s low level Note 80 115 ns RAS delay time after E s high level 0 20 15 CAS delay time after E s high level 0 20 ns Note Figure 13 shows the test circuit Refresh state Symbol Parameter RE Unit tw RASL RAS low level pulse width Note 120 ns twcast 65 low level pulse width Note 55 ns taicas ras CAS RAS delay time Note 17 5 ns thiras cas CAS hold time after RAS 17 5 ns Note Figure 13 shows the test circuit 7721 Group User s Manual 17 95 APPENDIX Appendix 11 Electrical characteristics At DRAM control Nea Nc c e e e td RAS CAS tw RASL ta E RASH gt th RAS RA RAS output ld E CASH th CAS R W ta R W RAS tw CASL WI CAS output ta E CA lo Ta CA CAS At read MAo MAs output R W output X td RAS CAS
337. gister 8 18 While counting is stopped When a value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time 7721 Group User s Manual TIMER A 8 4 Event counter mode Table 8 4 2 Specifications of event counter mode when using two phase pulse signal processing function Item Count source Specifications External signal two phase pulse input to the TAjw or TAjour Count operation Countup or countdown be switched by external signal two phase pulse When a counter overflow or underflow occurs reload register s contents are reloaded and counting continues Division ratio For countdown 1 n 1 Timer Aj register s set value e For countup 1 n 1 Count start condition When the count start bit is set to 1 Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing When a counter overflow or underflow occurs TAjour pin function Two phase pulse input Read from timer Aj register Counter value can be read out Write to timer Aj register While counting is stopped When a value is written to the timer Aj register it is written
338. gister BRG1 Address 3916 b7 bo be set 0016 16 CN UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 50 HH Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 9 UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3816 16 b15 b8 07 Pas Set transmit data here UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bo Transmit enable bit 1 Transmission enabled Y Transmission starts In the case of selecting the CTS function transmission starts when the CTSi pin s input level is L Fig 11 4 3 Initial setting example for relevant registers when transmitting 11 35 SERIAL I O 11 4 Clock asynchronous serial I O UART mode When not using interrupts When using interrupts A UARTI transmit interrupt request occurs when the UARTi transmit buffer register becomes empty Checking state of UARTi transmit buffer register UARTO transmit receive control register 1 Address 3516 transmit receive control register 1 Address 3016 UARTi transmit interrupt b7 50 Transmit buffer empty flag 0 Data
339. gister RW 0016 3116 UARTO baud rate register WO 2 3216 UARTO transmit buffer register WO 5 3316 WO d 3416 UARTO transmit receive control register 0 RO RW 3516 UARTO transmit receive control register 1 RO RW RO RW 3616 RO UARTO receive buffer register 3716 i RO 3816 UART1 transmit receive mode register RW 3916 UART1 baud rate register WO 6 UART1 transmit buffer register 3816 WO 3C16 UART1 transmit receive control register 0 RO RW 3D16 UART1 transmit receive control register 1 RO RWIRORW 3E16 UART1 receive buffer register RO 3F16 RO 17 4 7721 Group User s Manual APPENDIX Appendix 2 Memory assignment in SFR area Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset 0 Always 0 at reading 1 1 immediately after reset 1 di 2 Undefined immediately after Always at reading reset Always undefined at reading 0 immediately after reset Fix this bit to 0
340. gnal levels in each operation example and timing diagram are as follows Signal levels The upper line indicates 1 and the lower line indicates 0 Input output levels of pin The upper line indicates H and the lower line indicates L For the exception the level is shown on the left side of a signal 4 Register structure Below is the structure diagram for all registers 1 67 06 05 64 63 b2 bi lite XXX register Address XX 6 2 eR ni Gp T e 3 Fix this bit to 0 _____ 9 4 This bit is invalid in mode RW 34 4 Blank Set to 0 or 1 according to the usage 0 Set to 0 at writing 1 Set to 1 at writing x Invalid depending on the mode or state It may be 0 or 1 Nothing is assigned 2 0 0 immediately after reset 1 1 immediately after reset Undefined Undefined immediately after reset 3 RW Itis possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid Accordingly the written value may be 0 or 1 WO The written value becomes valid It is impossible to read the bit state The value is undefined at reading However when 0 at reading is indicated in the Function or Note column the bit is always 0 at readin
341. gram runaway occurs values of the data bank register DT direct page register DPR etc may be changed When 1 is written to the software reset bit by the addressing mode using DT DPR etc set values to DT and DPR again Fig 15 2 1 Example of program runaway detection by Watchdog timer 7721 Group User s Manual 15 5 WATCHDOG TIMER 15 2 Operation description 15 2 2 Stop period Watchdog timer stops operation in the following period Hold state Refer to section 3 4 Hold function During DMAC operation Refer to CHAPTER 13 DMA CONTROLLER During DRAM refresh Refer to CHAPTER 14 DRAM CONTROLLER Stop mode When states to are terminated Watchdog timer restarts counting from the state before it stops operation For Watchdog timer s operation when state is terminated refer to section 15 2 3 Operation in Stop mode 15 2 3 Operation in Stop mode In Stop mode Watchdog timer stops operation Immediately after Stop mode is terminated Watchdog timer operates as follows Refer to section 5 3 Stop mode 1 When Stop mode is terminated by hardware reset Supply of and ceu starts immediately after Stop mode is terminated and the microcomputer performs operation after reset Refer to CHAPTER 4 RESET The watchdog timer frequency select bit becomes 0 and Watchdog timer starts counting of fs from 2 When Stop mode is terminated by interrup
342. h a reload register and is used to generate refresh requests for DRAM data Assuming that the set value of the refresh timer n the refresh timer counts fis 1 times Figure 14 2 4 shows the structure of the refresh timer and the following formula gives the value to be written to the refresh timer f Xin m us X 16 1 n a set value of the refresh timer n 016 m a refresh interval Examples of an average of 15 625 us for 512 refresh cycles at 8 ms intervals an average of 125 us for 512 refresh cycles at 64 ms intervals Refresh timer Address 6616 7 to 0 These bits can be set to 0116 to Undefined WO Assuming that the set value n this register divides by 1 Note Use the LDM or STA instruction for writing to this register Do not set this register to 0016 Fig 14 2 4 Structure of refresh timer 7721 Group User s Manual 14 5 DRAM CONTROLLER 14 2 Block description 14 2 3 Address comparator The address comparator examines whether the address to be accessed is within the DRAM area When this address is within DRAM area control signals are sent to the RAS and CAS generating circuit and the address multiplexer 14 2 4 RAS and CAS generating circuit The RAS signal a timing signal to latch a row address and the CAS signal a timing signal to latch a column address are generated by a control signal from the address comparator
343. h of DMAO and request sources are external sources Channel priority level Fixed Channel 0 gt Channel 1 Fig 13 4 8 Transfer example in the burst transfer mode edge sense DMAREQO DMAO request bit DMAO enable bit DMAREQ1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU OWA C es ouo U gt lt gt Channel 1 Entire data transfer Channel 0 Entire data transfer This example applies on the following conditions Channel priority level Fixed Channel 0 gt Channel 1 Fig 13 4 9 Transfer example in the burst transfer mode level sense 7721 Group User s Manual 13 49 DMA CONTROLLER 13 4 Operation Precautions for burst transfer mode 1 In the burst transfer mode edge sense the request bit is cleared to 0 when the transfer of an entire batch of data is complete or the transfer is forced into termination Therefore another DMA request of the same channel i is invalid if generated during DMAi transfer Transition of right to use bus 1 unit transfer Termination processing from DMAC to CPU request bit is set to 0 Fig 13 4 10 Timing when clearing DMAi request bit to 0 in burst transfer mode 2 Because interrupt priority levels are determined while the CPU fetches an operation code interrupt requests are not accepted during a DMA transfer In the burst transfer mode edge sense therefore in
344. h other 2 For the system that transfers data with 16 bit external data bus width from an external memory to an 8 bit I O the external memory must be composed to be read in a unit of 8 bits If the external memory cannot be read in a unit of 8 bits the data read from the external memory at data copy collides with the copied data on the data bus 3 Under the following conditions 1 bus cycle transfer cannot be performed Refer to Table 13 4 5 External data bus width 16 bits Transfer unit 16 bits Address direction of memory Fixed Forward Data s start address of memory Odd External data bus width 16 bits Transfer unit 16 bits Address direction of memory Backward Data s start address of memory Even External data bus width 16 bits Transfer unit 16 bits Target memory of DMA transfer DRAM area Address direction of memory Backward Data s start address of memory Odd External data bus width 8 bits Transfer unit 16 bits 7721 Group User s Manual 13 47 DMA CONTROLLER 13 4 Operation 13 4 3 Burst transfer mode The burst transfer mode can operate in either edge sense or level sense mode 1 2 13 48 Burst transfer mode edge sense When the transfer mode select bit 0 and the edge sense level sense select bit 0 this mode is selected Refer to Figures 13 2 6 and 13 2 8 In this mode all of the DMA request sources are available Figur
345. hange and a timer Aj interrupt request does not occur 2 When the timer s operating mode is set by one of the following procedures the timer Aj interrupt request bit is set to 1 When the PWM mode is selected after reset When the operating mode is switched from the timer mode to the PWM mode When the operating mode is switched from the event counter mode to the PWM mode Accordingly when using the timer Aj interrupt interrupt request bit be sure to clear the timer Aj interrupt request bit to 0 after the above setting 7721 Group User s Manual 8 47 TIMER A 8 6 Pulse width modulation PWM mode MEMORANDUM 8 48 7721 Group User s Manual CHAPTER TIMER B 9 1 Overview 9 2 Block description 9 3 Timer mode Precautions for timer mode 9 4 Event counter mode Precautions for event counter mode 9 5 Pulse period Pulse width measurement mode Precautions for pulse period pulse width measurement PWM mode TIMER B 9 1 Overview 9 2 Block description 9 1 Overview Timer B consists of three counters Timers BO to B2 each equipped with a 16 bit reload function Timers BO to B2 operate independently of one another Timer B has three operating modes listed below Timers BO and B1 have selective three operating modes listed below Timer B2 operates only in the timer mode 1 Timer mode Timers BO to B2 The timer counts an internally generated count source
346. hdog timer s count may gain Refer to Figure 15 3 1 Note 152 or fsi2 which is selected by the watchdog timer frequency select bit f32 or f512 Bus request Count source which is actually 4 counted by Watchdog timer In case the bus request is changed in a period which is shorter than 1 cycle of fs2 or 1512 Fig 15 3 1 Count source for Watchdog timer 7721 Group User s Manual 15 7 WATCHDOG TIMER 15 3 Precautions for Watchdog timer MEMORANDUM 15 8 7721 Group User s Manual CHAPTER 16 APPLICATION 16 1 Memory connection 16 2 Examples of using DMA controller 16 3 Comparison of sample program execution rate APPLICATION 16 1 Memory connection This chapter describes application Application shown here is just examples The user shall modify them according to the actual application and test them 16 1 Memory connection This section shows examples for memory and I O connection Refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES for details about the functions and operations of used pins when connecting a memory or I O Refer to section Appendix 11 Electrical characteristics for timing requirements of the microcomputer 16 1 1 Memory connection model For the M37721 the level of the external data bus width select signal makes it possible to select the memory connection model from the fo
347. he LDM or STA instruction for writing to this register Fig 10 2 2 Structure of pulse output data registers 0 and 1 7721 Group User s Manual 10 5 REAL TIME OUTPUT 10 2 Block description 10 2 3 Port P6 direction register The pulse output pins are shared with port P6 When using these pins as pulse output pins of real time output set the corresponding bits of the port P6 direction register to 1 to set these ports for the output mode Figure 10 2 3 shows the relationship between the port P6 direction register and the pulse output pins 67 06 65 64 b3 62 bi Port direction register Address 1016 0 Input mode Rw 1 Output mode 6 When using these pins as pulse REPO pin output pins set the corresponding Le mmm ____ Note When setting these bits to 0 the corresponding pins serve as input port floated regardless of the state of the waveform output select bits bits 0 and 1 at address 6216 Fig 10 2 3 Relationship between port P6 direction register and pulse output pins After reset the state of the port P6 pins are floated since these pins are in the input mode The output levels of the pulse output pins are undefined until Timer AO or A1 underflows first after the data for the timer is written Because the pulse output data registers 0 and 1 are undefined after reset When these conditions should be avoided follow the procedure Processing of avoiding undef
348. he address of DARi however the value of the DARi latch cannot be read Refer to Tables 13 2 4 and 13 2 5 13 2 6 Transfer counter register i TCRi Transfer counter register i hereafter called TCRi is a 24 bit register with a latch TCRi indicates the number of remaining bytes of the block under transfer The TCRi latch has the following functions Maintains the value written to the address of TCRi in the single transfer and repeat transfer modes Indicates the number of remaining blocks in the array chain transfer mode When a value is written into the address of TCRi the same value is written into TCRi and the TCRi latch When writing a value to the address of TCRi all 24 bits must be written The contents of TCRi can be read by reading the address of TCRi however the value of the TCRi latch cannot be read Refer to Tables 13 2 4 and 13 2 5 Table 13 2 4 Addresses of SARi DARi and TCRi Channel Source address register i Destination address Transfer counter register i SARI register i DARI TCRi 0 1FC2 e 1FCO 6 1FC616 1F C416 1FCA e 1FC8 6 1 1FD2 1e 1FDO e 1FD6 e 1FD4 e 1FDA e 1FD8 e 2 1FE2 e 1FE0 6 1FE61s 1F E416 2 2816 3 1 21 1 16 1FF616 1F F416 1FFAtc 1F F816 13 12 7721 Group User s Manual DMA CONTROLLER 13 2 Block description Table 13 2 5 Functions of SARi DARi and TCRi Mode Single transfer mode Repeat transfer mode Array chain tra
349. he index register Y Transmits the con he accumulator B to the direct page register Transmits the contents of the accumulator B to the stack pointer Transmits the contents of the accumulator B to the index register Transmits the contents of the accumulator B to the index register Transmits the contents of the direct page register to the accumulator A Transmits the contents of the direct page register to the accumulator B Transmits the contents of the stack pointer to the accumulator A Transmi s the contents of the stack pointer to the accu mulator B Transmits the contents of the stack pointer to the index register X Transmits the contents of the index register X to the ac cumulator A Transmits the contents of the index register X to the ac cumulator B Transmits the contents of the index register X to the stack pointer Transmits the contents of the index register X to the index register Y Transmits the contents of the index register Y to the ac cumulator A Transmits the contents of the index register Y to the ac cumulator B Transmits the contents of the index register Y to the index register X Stops the internal clock Exchanges the contents of the accumulator A and the con tents of the accumulator B 17 52 7721 Group User s Manu
350. he interrupt routine Interrupt request is accepted Interrupt request Time allis nud sequence Instructions in interrupt routine IBEETTUDEFGSpORSe time Interrupt priority level detection time Time from the occurrence of an interrupt request until the instruction execution which is in progress at that time is completed Time from when execution of an instruction next to begins Note until the instruction execution which is in progress at completion of interrupt priority level detection Note At this time detection of interrupt priority level begins Time required to execute the INTACK sequence 13 cycles of at minimum Fig 7 7 1 Sequence from acceptance of interrupt request until execution of interrupt routine 7721 Group User s Manual 7 13 INTERRUPTS 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine When stack pointer S s contents are even and no Wait Internal clock N oX oX o o gt Interrupt disable flag 1 INTACK sequence CPU standard clock Not used High order 8 bits of CPU internal address bus S Contents of stack pointer S Middle order 8 bits of CPU internal addre
351. he pulse output pins at every underflow of Timer Ai The timer is reloaded with the contents of the reload register and continues counting The timer Ai interrupt request bit is set to 1 when the counter underflows in The interrupt request bit retains 1 until the interrupt request is accepted or it is cleared by software Write the next output data into the pulse output data register i during the timer Ai interrupt routine or after the recognition of the timer Ai interrupt request occurrence Figure 10 4 1 shows an example of real time output operation Starts counting Starts pulse outputting Hex Counter contents 000016 x1 m 22 Undefined 0011 0110 11002 10012 00112 522272 2 Gee RTPOs output Undefined 2 RTPO2 output Undefined 2 RTP0O1 output Undefined 2 RTPOo output Undefined 2 Timer AO interrupt request bit 1 Written by software 2 To avoid undefined output for these terms follow the procedure Processing of avoiding undefined output before starting pulse output in Figures 10 3 1 and 10 3 2 k3 Cleared to 0 when interrupt request is accepted or cleared by software The above figure shows an example of he following conditions Pulse mode 0 selected RTPOo RTPOs selected Timer AO register set value n 000316 Fig 10 4 1 Example of real time output operation 10 10 7721 Group User s Manual
352. he relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 3 9 shows processing after receive completion 7721 Group User s Manual 11 23 SERIAL I O 11 3 Clock synchronous serial I O mode dd UARTO transmit receive mode register Address 30 6 D UART1 transmit receive mode register Address 3816 b7 60 of oft LT Clock synchronous serial I O mode Internal External clock select bit 0 Internal clock 1 External clock C X It may be 0 or 1 E g UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C 6 b7 50 BRG count source select bits b1 b0 00 fe 01 fie 10 fea 11 12 CTS RTS select bit 0 CTS function selected 1 RTS function selected UARTO baud rate register BRGO Address 31 6 UART1 baud rate register BRG1 Address 3916 b7 50 inse Can be set to 0016 to FF16 Necessary only when an internal clock is selected Continued to Figure 11 3 8 on next page Fig 11 3 7 Initial setting example for relevant registers when receiving 1 11 24 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode From preceding Figure 11 3 7 Port P8 direction register Address 1416 RxD1 pin ie UARTO receive interrupt control register Address 7216 UART1 receive interrupt control register Address 7
353. he start address of the transfer parameter memory of block which is first transferred After transfer starts the read value indicates the Source address of data which is next transferred Note When writing to this register write to all 24 bits Addresses 1FC61e to 1FC4 6 Addresses 1FD616e to 1FD4 6 Addresses 1 16 to 1 416 Addresses 1FF616 to 1FF4 16 Destination address register 0 Destination address register 1 Destination address register 2 Destination address register 3 23 to 0 Need not to set Undefined RW Read After transfer starts the read value indicates the destination address of data which is next transferred Addresses 1FCA16 1 816 Addresses 1FDAie to 1FD8 6 Addresses 1 16 to 1FE8 6 Addresses 1 16 to 1FF8 6 Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 Write Set the dummy data These bits can be set to 00000116 to FFFFFF e Read After a value is written to this register and until transfer starts the read value indicates the written value dummy data After transfer starts the read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register 7721 Group User s Manual 17 37 APPENDIX Appendix 3 Control registers
354. hen selecting the gate function set the port P5 direction registers bits which correspond to the TAjin pin for the input mode Additionally make sure that the TAjin pin s input signal has a pulse width equal to or more than two cycles of the count source Table 8 3 3 Count valid levels Gale Tunetion select bits Count valid level Duration while counter counts b4 b3 1 0 While pin s input signal is at L level 1 1 While TAjw pin s input signal is at level Note The counter does not count while the 5 input signal is not at the count valid level n Reload register s contents Starts counting x i 7 2 o 2 c 5 Count start bit Count valid TAjin pin s level input signal Invalid level Timer Aj interrupt request bit The counter counts when the count start bit 1 and the TAjin pin s input signal is at the count valid level The counter stops counting while the TAjin pin s input signal is not at the count valid level and the counter value is retained Cleared to 0 when interrupt request is accepted or cleared by software Fig 8 3 5 Example of operation selecting gate function 7721 Group User s Manual 8 15 TIMER A 8 3 Timer mode 2 Pulse output function The pulse output function is selected by setting the pulse output function select bit bit 2 at addresses 5816 to
355. hen the CPU fetches an op code which is called the CPU s op code fetch cycle However when an op code fetch cycle starts during detection of an interrupt priority a new interrupt priority detection does not start Refer to Figure 7 6 1 Since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection even if they change the interrupt priority detection is performed for the previous state before the change occurred The interrupt priority level is detected when the CPU fetches an op code Therefore in the following execution or states after the execution or state is terminated no interrupt request is accepted until the CPU fetches the op code of the next instruction Execution of an instruction which requires many cycles such as the MVN or MVP instruction During DRAM refreshment During Hold state During DMA transfer Interrupt source Y Comparator X Priority level sent from the preceding Priority level comparator Highest priority at this point comparison Y Priority level of interrupt source Y 2 Highest priority at this point Z When X gt Y thenZ X When X lt YthenZ Y Fig 7 5 2 Interrupt priority level detection model 7721 Group User s Manual 7 11 INTERRUPTS 7 6 Interrupt priority level detection time 7 6 Interrupt priority level detection time When the interrupt priority level detection time has passed after sa
356. hing factor i e up down switching factor select bit 0 Fig 8 4 4 Example of operation in event counter mode without pulse output and two phase pulse signal processing functions 7721 Group Users Manual 8 23 TIMER A 8 4 Event counter mode 8 4 3 Switching between countup and countdown The up down register address 44 or the input signal from the TAjour pin is used to switch countup from and to countdown This switching is performed by the up down bit when the up down switching factor select bit bit 4 at addresses 58 to is 0 and by the input signal from the TAjour pin when the up down switching factor select bit is 1 When the switching between countup and countdown is set while counting is in progress this switching is actually performed when the count source s next valid edge is input 1 Switching by up down bit Countdown is performed when the up down bit is 0 and countup is performed when the up down bit is 1 Figure 8 4 5 shows the structure of the up down register 2 Switching by TAjour pin s input signal Countdown is performed when the TAjour pin s input signal is at L level and countup is performed when the TAjour pin s input signal is at level When using the TAjour pin s input signal to switch countup from and to countdown set the port P5 direction register s bit which corresponds to the TAjour pin for the input mode 67 b6 65 04 b3 b2 bi 00
357. hip between tcac trac taa and f Xin 7721 Group User s Manual APPLICATION 16 1 Memory connection 2 Timing for writing data When writing data the output data is stabilized when an interval of has passed after the falling edge of the E signal This data is continuously output until when an interval of has passed after the rising edge of the E signal Data to be written to an external memory must satisfy the data set up time for DRAM the data hold time of the external memory The following are described below Timing for writing data to flash memory SRAM and DRAM Calculation formulas which are for tsup and tox to be satisfied Timing for writing data to flash memory and SRAM External memory write signal External memory chip select signals S td E DL DHQ h E DLQ DHQ Address output and Data input 15 15 Address A16 Do A23 D7 Specifications of the M37721 The others are specifications of external memory This applies when the external data bus has a width of 16 bits BYTE L Fig 16 1 5 Timing for writing data to flash memory and SRAM Data setup time lt tw Table 16 1 4 lists the calculation formulas and values for each parameter in Figure 16 1 5 Figure 16 1 6 shows the relationship between and f Xin 16 8 7721 Group Us
358. i transmit buffer register becomes empty Checking state of transmit buffer register UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3016 b7 60 Transmit buffer empty 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing of next transmit data is possible S UARTi transmit interrupt Writing of next transmit data UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 b7 50 Loo rg 2 transmit data here P Fig 11 3 2 Writing data after start of transmission When not using interrupts Checking start of transmission UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 50 0 No interrupt requested 1 Interrupt requested c Transmission has started Interrupt request bit US Checking completion of transmission UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 b7 00 Transmit register empty flag 0 During transmitting C 1 Transmitting completed A C Processing at completion of transmission Fig 11 3 3 Detection of transmit completion Note This figure shows the bits and registers required for processing Refer to
359. in Row addres Column address 20 35 max td E CA 60 gt gt tpzx E DLZ 20 min gt tRAC 70 max 5 Input data tCLz 5 min lt I 20 max tsu DL E gt 30 tOEZ 0 20 lt When writing gt tw EL 135 min tw RASH 60 min tw RASL 120 min tw CASL 55 min gt td E CASL 80 115 ta R W E 20 min AC32 tPHL AC32 tPHL twCs 0 min tWCH 15 min gt lt td RA RAS 5 min th RAS RA 18 min gt MAo MAg Row address Column address td CA CAS 10 th CAS CA 60 min A16 Do 23 07 Data gt gt th E DLQ 18 min tDH 15 min Specifications of M5M44800CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 21 Timing chart for example of M5M44800CJ 512K X 8 bits connection external bus width z 8 bits 7721 Group Users Manual 16 25 APPLICATION 16 1 Memory connection 4 Example of DRAM connection external bus width 8 bits M37721 M5M417800CJ 7 1 Make sure that the propagation delay time is within 80 ns 2 Make sure that the propagation delay time is within 15 ns gt gt gt gt gt gt
360. ined output before starting pulse output in Figures 10 3 1 and 10 3 2 When reading the port P6 register address E e the output values of the real time output pins can be read out 10 2 4 Timers AO and A1 The data written into the pulse output registers O and 1 is output from the pulse output pins every underflow of Timer AO or A1 Refer to section 8 3 Timer mode for the setting of Timers AO and A1 10 6 7721 Group User s Manual REAL TIME OUTPUT 10 3 Setting of real time output 10 3 Setting of real time output Figures 10 3 1 to 10 3 3 show an initial setting example for registers relevant to the real time output Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Processing of avoiding undefined output before starting pulse output Note b7 bo Port P6 register Address E16 Note This processing can be neglected if the system is not affected by RTPOo Settoinitial output level undefined output of real time output 2 0 L level 1 H level RTP1o RTP1 RTP12 J gt Setting port P6 direction register N b7 bo Port P6 direction register Address 1016 RTPOo Set the bits corresponding to the RTPO0 selected pulse output pins to 1 L RTP0s RTP1o RTP12 1
361. ing transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register Fig 13 8 1 Register structures of SARi DARi and TCRi in link array chain transfer mode 7721 Group User s Manual 13 81 DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 1 Transfer parameter memory in link array chain transfer mode The transfer parameters required for each transfer method are described below These parameters can be located in separate memory locations in a unit of one block s parameters However these parameters must be located starting even address Figure 13 8 2 shows a transfer parameter memory map in the link array chain transfer mode 1 2 3 Note 13 82 In 2 bus cycle transfer All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 16 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits Start address of next transfer parameter memory 24 bits Note Dummy data 8 bits In 1 bus cycle transfer from memory to I O All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 12 bytes for each block Transfer so
362. instructions Addressing modes Processor status register L DIR L oIR v ABS ABS b ABS X ABS Y ABL ABL x ABS JL ABS ABS X STK RE R b R ABS bR SR 6 5 lop n n op n op n op op op n fop op n opn fop n m 0B Value saved in stack 7721 Group User s Manual 17 49 APPENDIX Appendix 6 Machine instructions Addressing modes Functions Details DIR DIR b DIR X DIR Y DIR DIR X 0 OP n s op P OP n op Restores the contents of the stack on the index register Y PSH Saves the registers among accumulator index register direct Note 6 page register data bank register program bank register or processor status register specified by the bit pattern of the second byte of the instruction into the stack PUL Restores the contents of the stack to the registers among Note 7 accumulator index register direct page register data bank register or processor status register specified by the bit pattern of the second byte of the instruction RLA Rotates the contents of the accumulator A n bits to the Note 13 it rotate left lef
363. interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 8 5 5 shows an example of operation in the one shot pulse mode When trigger is generated after above the counter and TAjour pin perform the same operations beginning from again Furthermore if a trigger is generated during counting the counter performs countdown once after this new trigger is generated and it continues counting with the reload register s contents reloaded If generating a trigger during counting make sure that a certain time which is equivalent to one cycle of the timer s count source or more has passed between the previously generated trigger and a new trigger The one shot pulse output from the TAjout pin can be disabled by clearing the timer Aj mode register s bit 2 to 0 Accordingly Timer Aj can be also used as an internal one shot timer that does not perform the pulse output In this case the TAjour pin functions as a programmable I O port 7721 Group User s Manual 8 35 TIMER A 8 5 One shot pulse mode n Reload register s contents Stops n d Starts counting counting Starts counting Stops counting 4 9 Reloaded Counter contents Hex Set to 1 by software Count start bit Trigger during counting TAji pin input signal 1 fi X n1 One shot pulse output fro
364. interrupts listed above are enabled Wait mode is terminated by the interrupt request which occurs first Termination by hardware reset The CPU and the SFR area are initialized in the same way as system reset However the internal RAM area retains the same contents as that before executing the WIT instruction The terminating sequence is the same as the internal processing sequence which is performed after reset Refer to CHAPTER 4 RESET for details about reset 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 4 Wait mode Precautions for Wait mode When executing the WIT instruction after writing to an internal area or an external area three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed Refer to Figure 5 4 1 STA A Write instruction NOP NOP instruction inserted NOP NOP WIT WIT instruction Fig 5 4 1 NOP instruction insertion example 7721 Group User s Manual 5 11 CLOCK GENERATING CIRCUIT 5 4 Wait mode MEMORANDUM 5 12 7721 Group User s Manual CHAPTER 6 INPUT OUTPUT PINS 6 1 Overview 6 2 Programmable I O ports 6 3 Examples of handling unused pins INPUT OUTPUT PINS 6 1 Overview 6 2 Programmable I O ports 6 1 Overview Input output pins hereafter called I O pins have functions as programmable I O ports internal peripheral devices s I O pins external buse
365. ister 7721 Group User s Manual 8 17 TIMER A 8 4 Event counter mode 8 4 Event counter mode In this mode the timer counts an external signal Refer to Tables 8 4 1 and 8 4 2 Timers A2 to A4 can be used in this mode Figure 8 4 1 shows the structures of the timer Aj mode register and timer Aj register in the event counter mode Table 8 4 1 Specifications of event counter mode when not using two phase pulse signal processing function Item Count source Specifications External signal input to the TAjin pin The count source s valid edge can be selected from the falling edge and the rising edge by software Count operation Countup or countdown can be switched by external signal or software When a counter overflow or underflow occurs reload register s contents are reloaded and counting continues Division ratio For countdown 1 n 1 n Timer Aj register s set value e For countup 1 FFFFie n 1 Count start condition When the count start bit is set to 1 Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing When a counter overflow or underflow occurs pin s function Count source input TAjour pin s function Programmable port pulse output or countup countdown switch signal input Read from timer Aj register Counter value can be read out Write to timer Aj re
366. ister s contents and Vre Table 12 3 2 lists changes of the successive approximation register and during the A D conversion Figure 12 3 1 shows the ideal A D conversion characteristics Table 12 3 1 Relationship between successive approximation register s contents and Vret Successive approximation register s contents n Vret V 0 0 2 X 0 5 1 255 Vrer Reference voltage 12 10 7721 Group User s Manual A D CONVERTER 12 3 A D conversion method Table 12 3 2 Change in successive approximation register and Vre during A D conversion Se Successive approximation register Change of Vref A D converter halt VREF 1st comparison 7512 v 2nd comparison 0 0 0 VREF _ VREF y i 4 512 1st comparison resul V n A VREF 1 4 _ VREF 7 n7 0 4 t g VREF ne 0 8 V V V M VREF 3rd comparison nzne 10 0 0 0 REE SVREF 8 512 Y 2nd comparison result 8th comparison ps v Conversion complete A D conversion result Ideal A D conversion characteristics 9 gt VREF VREF VREF 256 X253 256 254 256 255 VREF Analog input voltage Fig 12 3 1 Ideal A D conversion characteristics 7721 Group User s Manual 12 11 A D CONVERTER 12 4 Absolute accuracy and differential non linear
367. istinguish power on reset from hardware reset for terminating the stop or wait mode The contents of the internal RAM is undefined after power on reset On the other hand the contents of the internal RAM are retained when performing hardware reset in the stop or wait mode with Vcc 22V Accordingly write a certain data to the internal RAM before executing STP or WIT instruction and judge by checking the contents of the internal RAM after hardware reset 7721 Group User s Manual 17 67 APPENDIX Appendix 9 7721 Group Q amp A Interrupt If an interrupt request b occurs while executing an interrupt routine a is it true that the main routine is not executed at all from when the execution of the interrupt routine a is completed until the execution of the INTACK sequence for the next interrupt b starts Sequence of execution RTI instruction Interrupt routine a lt Main routine gt lt INTACK sequence for interrupt b Conditions is cleared to 0 by executing the RTI instruction linterrupt priority level of interrupt b is higher than IPL of main routine Interrupt priority detection time is 2 cycles of Sampling for interrupt requests is performed by sampling pulses generated synchronously with the CPU s op code fetch cycles 1 If the next interrupt request b occurs before sampling pulse for the RTI instruction is gener ated the microcomputer executes the INTACK sequ
368. it request BUS REQUEST DRAMC fie Refresh timer request Hold request Array state DRAM refresh Channel 0 DMAREQO Software Timer AO Timer 1 Bus access control circuit 9 0 BUS REQUEST DMAC Request source selection Channel priority level determination Channel 1 Channel 2 Channel 3 Fig 13 2 2 DMAC block diagram 2 DMAACKO DMAACK1 DMAACK2 DMAACK3 Acknowledge signal generation 13 6 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 1 Bus access control circuit In the M37721 the bus is used by DRAMC Hold function DMAC and CPU When each request of DRAM refresh Hold and DMA is generated each of DRAMC Hold function and DMAC issues its bus request to the bus access control circuit in DMAC Refer to Figure 13 2 2 Table 13 2 1 lists the bus request generating sources Table 13 2 1 Bus request generating sources Bus request BUS REQUEST Bus request generating source DRAM refresh request DRAMC Generated by an underflow of the refresh timer BUS REQUEST Hold request Hold Generated by L level input to the HOLD pin BUS REQUEST DMAC DMA request Generated by a DMA request source The bus access control circuit relinquishes the right to use bus to the function with
369. it bit Note 2 0 Wait 0 1 No Wait Continuous transfer mode select 0706 bits 0 0 Single transfer 0 1 Repeat transfer 1 0 Array chain transfer RW 11 Link array chain transfer Notes 1 Set bit 0 to 0 in 2 bus cycle transfer 2 Bits 4 and 5 are valid to the external and internal areas However DRAM area is always handled with Wait regardless of the contents of these bits The wait bit bit 2 at address 5 is invalid in DMA transfer 17 38 7721 Group User s Manual APPENDIX Appendix 3 Control registers DMAi control register DMAO control register control register DMA2 control register Address 1 16 DMAS control register Address 1FFE 6 RW DMA request source select bits b3b2b1b0 Note 0000 Do not select External source DMAREQi Software DMA source Timer AO Timer A1 Timer A2 Timer A3 Timer A4 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UART1 receive UART1 transmit A D conversion Address 1FCE16 67 b6 b5 b4 b3 62 bi 00 Address 1FDE16 40000 0082 0 0 0 0 00 0 Edge sense Level sense select 0 Edge sense Falling edge bit Used when external source 1 Level sense L level and burst transfer mode are selected Note DMAACKi validity bit 0 Invalid The pin functions as a program
370. iting 1 to this bit The value is 0 at reading b5 b4 00 7 cycles of 01 4 cycles of 10 2 cycles of o 1 Do not select Interrupt priority detection time select bits Fix this bit to 0 7 Stack bank select bit x Bank 016 Bank FF e O Bits 0 1 and 3 to 6 are not used for accessing external area Fig 3 2 1 Structure of processor mode register 0 3 8 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 2 Software Wait lt No Wait gt 1 bus cycle Clock 1 E ALE Note As Ds A15 D15 A16 Do A23 D7 areas are always accessed with this waveform 1 bus cycle Clock E ALE Note As Ds A15 D15 Ate Do Azs D Note When the external data bus is 8 bits wide BYTE H As Ds to A15 D15 operate with the same bus timing as Ao to A7 Fig 3 2 2 Examples of bus timing when software Wait is used BYTE z L 7721 Group User s Manual 3 9 CONNECTION WITH EXTERNAL DEVICES 3 3 Ready function 3 3 Ready function Ready function provides the function to facilitate access to external devices that require long access time The microcomputer enters Ready state by input of L level to the RDY pin and retains this state while the level of the RDY pin is at L Table 3 3 1 lists the microcomputer s state in Ready state In Ready state the oscillator s oscillation does not stop Ac
371. its 4 7 refer to section 11 3 6 Processing on detecting overrun error and 11 4 7 Processing on detecting error 67 b6 b5 64 63 62 61 2 UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3016 Bit Bit name Functions At reset Transmit enable bit 0 Transmission disabled 1 Transmission enabled Transmit buffer empty flag 0 Data present in transmit buffer 1 register 1 No data present in transmit buffer register 2 Receive enable bit 0 Reception disabled 1 Reception enabled 3 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register 4 Overrun error flag Note 1 0 No overrun error 1 Overrun error detected 5 Framing error flag Notes 1 2 0 No framing error Valid in UART mode 1 Framing error detected Parity error flag Notes 1 2 0 No parity error Valid in UART mode 1 Parity error detected 7 Error sum flag Notes 1 2 0 No error Valid in UART mode 1 Error detected Notes 1 Bit 4 is cleared to 0 when the receive enable bit is cleared to 0 or when the serial mode select bits bits 2 to 0 at addresses 3016 3816 are cleared to 0002 Bits 5 and 6 are cleared to 0 when one of the following is performed Clearing the receive enable bit to 0 Reading the low order byte of the UARTi receive buffer register addresses 3616 3E16
372. ity error 12 4 Absolute accuracy and differential non linearity error The A D converter s accuracy is described below Refer to section Appendix 12 3 A D converter standard characteristics also 12 4 1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A D conversion result and the output code of an A D converter with ideal characteristics The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A D converter with ideal characteristics For example when Vrer 5 12 V 1 LSB width is 20 mV and 0 mV 20 mV 40 mV 60 mV 80 mV are selected as the analog input voltages The absolute accuracy 3 LSB indicates that when the analog input voltage is 100 mV the output code expected from an ideal A D conversion characteristics is O0516 however the actual A D conversion result is between 00216 to 00816 The absolute accuracy includes the zero error and the full scale error The absolute accuracy is degraded when Vner is lowered Any of the output codes for analog input voltages from Vrerto AVcc is FF e Output code A D conversion result Ideal A D conversion characteristics 40 60 80 100 120 140 160 180 200 220 Analog input voltage mV Fig 12 4 1 Absolute accuracy of A D converter 12 12 7721 Group User s Manual A D CONVERTER
373. ixed Channel 0 gt Channel 1 Fig 13 4 11 Transfer example in cycle steal transfer mode 7721 Group User s Manual 13 51 DMA CONTROLLER 13 4 Operation Precautions for cycle steal transfer mode 1 When DMA transfers of the same channel are continuously performed In the cycle steal transfer mode the DMAi request bit is cleared to 0 in every 1 unit transfer Also it takes 1 5 cycles of from the generation of a DMA request until that of a BUS REQUEST DMAC Therefore if another DMA request of the same channel i is generated during a DMAi transfer in the cycle steal transfer mode any one of the following three cases occurs depending on the timing of request generation The DMA request becomes invalid The DMA transfer continues without returning the right to use bus After returning the right to use bus to the CPU the DMAC regains the right and restarts the DMA transfer 1 unit transfer Bus request sampling d DMAi request bit is cleared to 0 during this term request is invalid DMA transfers After returning the right to use bus even when request continuously performed if to CPU DMAC regains the right and bit becomes 1 DMAi request bit becomes 1 restarts DMA transfer if request during this term on condition bit becomes 1 during this term that DMAi request bit becomes 1 at the timing satisfying tsu DRQ When a
374. j mode register and the timer Bj register in the event counter mode Table 9 4 1 Specifications of event counter mode Item Count source Specifications External signal input to the TBji pin The count source s valid edge can be selected from the falling edge the rising edge and both of the falling and rising edges by software Count operation Countdown When a counter underflow occurs reload register s contents are reloaded and counting continues Division ratio 1 n Timer Bj register s set value n 1 Count start condition When the count start bit is set to 1 Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing When a counter underflow occurs pin s function Count source input Read from timer Bj register Counter value can be read out Write to timer Bj register 9 14 While counting is stopped When a value is written to the timer Bj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Bj register it is written only to the reload register Transferred to the counter at the next reload time 7721 Group User s Manual TIMER B 9 4 Event counter mode 67 b6 65 64 63 b2 61 b0 Timer Bj mode register 0 1 Addresses 5816 5 16 0 T Event counter mode b3 b2
375. k input to the CLKi pin becomes the transfer clock UART mode By clearing this bit to 0 in order to select an internal clock the clock which is selected with the BRG count source select bits bits 0 and 1 at addresses 3416 3C e becomes the count source of the BRGi described later Then the pin functions as a programmable I O port By setting this bit to 1 in order to select an external clock the clock input to the CLKi pin becomes the count source of BRGi Always in the UART mode the BRGi s output divided by 16 becomes the transfer clock 7721 Group User s Manual 11 5 SERIAL I O 11 2 Block description 11 2 2 UARTi transmit receive control register 0 Figure 11 2 3 shows the structure of UARTi transmit receive control register 0 For bits 0 and 1 refer to section 11 2 1 1 Internal External clock select bit bit 3 b7 66 b5 64 b3 62 bi 00 UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address SC BRG count source select bits ae CTS RTS select bit 5 CTS function selected RTS function selected Transmit register empty flag 0 Data present in transmit register During transmission 1 No data present in transmit register Transmission completed Nothing is assigned Fig 11 2 3 Structure of UARTi transmit receive control register 0 1 CTS RTS select bit bit 2 By clearing this bit to 0 in order to
376. l I O transfer clock must be 1 923 MHz or less About Serial I O control in this expansion example is described below In this example 8 bit data transmission reception is performed 3 times by using UARTO so that 24 bit port expansion is realized Setting of UARTO is described below Clock synchronous serial I O mode Transmission Reception enable state Internal clock is selected Transfer clock frequency is 1 66 MHz LSB first The control procedure is described below Output L level from port P4s Expanded I O ports of the M66010FP enter a floating state by this signal Q Output level from port P4s Output L level from port P44 Transmit Receive 24 bit data by using UARTO Output level from port P44 Figure 16 1 37 shows the serial transfer timing between the M37721 and the M66010FP 7721 Group User s Manual APPLICATION 16 1 Memory connection M37721 M66010FP P45 RTSo A0 A7 As Ds A15 D15 Expanded input ports A16 Do A23 D7 ALE Circuit conditions UARTO used in clock synchronous serial I O mode Internal clock selected b Frequency of transfer clock S 1 5625 VESTE 2 8 1 2 Fig 16 1 36 Example of port expansion circuit using M66010FP 7721 Group User s Manual 16 41 APPLICATION 16 1 Memory connection JO s uid 54401 099 94 5 122720
377. l level changes Install an oscillator and its wiring pattern away from signal lines where potential levels change frequently Do not cross these signal lines over the clock related or noise sensitive signal lines Reason Signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge In particular if the lines cross over a clock related signal line clock waveforms may be deformed which causes a microcomputer malfunction Or a program runaway Oscillator protection using Vss pattern Print a Vss pattern on the bottom soldering side of a double sided printed circuit board under the oscillator mount position Connect the Vss pattern to the Vss pin of the microcomputer with the shortest possible wiring separating it from other Vss patterns 7721 Group User s Manual 37721 Do not cross 1 O pin for signal with frequently changing potential levels Fig 10 Wiring for signal lines where potential levels frequently change An example of Vss pattern on the underside of an oscillator M37721 Mounted pattern example of oscillator unit Separate Vss lines for oscillation and supply Fig 11 Vss pattern underneath mounted oscillator 17 63 APPENDIX Appendix 8 Countermeasure against noise 5 Setup for I O ports Setup I O ports by hardware and software as follows lt Hardware protection gt Connect a resistor of 100 Q or more to an I O por
378. le sweep mode In the single sweep mode the operation for the input voltage from multiple selected analog input pins is performed one at a time The A D converter is operated in ascending sequence from the ANo pin The A D conversion interrupt request occurs when the operation for all selected input pins are completed 12 7 1 Settings for single sweep mode Figure 12 7 1 shows an initial setting example for registers relevant to the single sweep mode When using an interrupt it is necessary to set the relevant registers to enable the interrupt Refer to CHAPTER 7 INTERRUPTS for more information 12 20 7721 Group User s Manual A D CONVERTER 12 7 Single sweep mode A D control register and A D sweep pin select register b7 b7 60 0 11 0 A D control register address 1E 6 NENNNN A D sweep pin select register address 1F 6 Single sweep mode AD pin select bits i 0 0 ANo AN 2 pins Trigger select bit 0 1 ANo ANs 4 pins 0 Internal trigger 1 0 6 pins 1 External trigger 1 1 ANo AN 8 pins A D conversion start bit 0 Stop A D conversion conversion frequency AD select bit 0 f2 divided by 4 1 f2 divided by 2 lnterrupt priority level b7 bO THEME A D conversion interrupt control register address 7016 Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt Set to a level 0
379. lect bits When using interrupts set these bits to one of levels 1107 When disabling interrupts set these bits to level 0 t Setting port P5 direction register b7 bo Port P5 direction register Address D16 TBOm pin 1 Clear the corresponding bit to 0 7 Setting count start bit to 1 b7 50 Count start register Address 4016 Count starts Timer BO count start bit Timer B1 count start bit Note The timer Bj overflow flag is a read only bit This bit is undefined after reset When a value is written to the timer Bj mode register with the count start bit 1 this bit is cleared to 0 at the next count timing of the count source Fig 9 5 2 Initial setting example for registers relevant to pulse period pulse width measurement mode 7721 Group User s Manual 9 21 TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 2 Count source In the pulse period pulse width measurement mode the count source select bits bits 6 and 7 at addresses 5B e and 5C e select the count source Table 9 5 2 lists the count source frequency Table 9 5 2 Count source frequency Count source Count Count source frequency select bits source b7 b6 f Xin 8 MHz 16 MHz 25 MHz 0 0 4 MHz 8 MHz 12 5 MHz 0 1 fie 500 kHz 1 MHz 1 5625 MHz 1 0 fea 125 kHz 250 kHz 390 625 kHz 1 1 512 15625 Hz 31250 Hz 48 8281 k
380. lected The operation for the input voltage from the ANo pin starts when the A D conversion start bit is set to 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register 0 For all of the selected analog input pins the A D conversion is performed The conversion result is transferred to the A D register i each time each pin is converted For all of the selected analog input pins the A D conversion is performed again The operation is performed repeatedly until the A D conversion start bit is cleared to 0 by software When an external trigger is selected The A D converter starts operation for the input voltage from the ANo pin when the input level to the ADtre pin changes from to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register 0 For all of the selected analog input pins the conversion is performed The conversion result is transferred to the A D register i each time each pin is converted For all of the selected analog input pins the A D conversion is performed again The operation is performed repeatedly until
381. lid data address BHE L H H BLE Even AA a bis Data bus B Dis address 8 15 Transfer source address Transfer destination address Do D7 and TrnsfersouceV na X Transfer destination Odd address 9 Do Aes D ree Lor A DUE gt When the memory is the internal memory SFR data is output When the memory is the external memory it enters a floating state 13 44 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 3 Address directions in 1 bus cycle transfer In 1 bus cycle transfer the transfer source and destination address directions of memory are selectable Refer to Figure 13 2 6 Addresses move in the specified direction by the transfer unit Tables 13 4 8 and 13 4 9 list address directions in 1 bus cycle transfer and examples of transfer results Table 13 4 8 Address directions in 1 bus cycle transfer and examples of transfer results 1 External data bus width 16 bits External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 bits Transfer Transfer Data arrangement Transfer destination source destination on transfer source Transfer memory sequence Data arrangement T Transfer Transfer destination sequence O memory on Fixed Forward Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Backward
382. list the pin description Table 1 3 1 Pin description 1 Pin Name Input Output Functions Vcc Vss Power supply Supply 5 V 10 to Vcc pin and 0 V to Vss pin CNVss CNVss Input Connect to Vss or Vcc pin RESET Reset input Input The microcomputer is reset when supplying L level to this pin RESETour Reset output Output When input to RESET pin is L this pin outputs L Output from this pin returns H after the release of reset When writing 1 to the software reset bit this pin outputs L Clock input Input These are I O pins of the internal clock generating circuit Connect a ceramic resonator or quartz crystal Clock output Output oscillator between pins Xin and Xour using external clock the clock source should be input to Xin and Xour pin should be left open E Enable output Output Data instruction code read or data write is performed when output from this pin is L level BYTE Exernal data bus width Input Input level to this pin determines whether the external selection input data bus has a 16 bit width or an 8 bit width The width is 16 bits when the level is L and 8 bits when the level is STO Status signal output Output The bus use state is output in 2 bit code ST1 571 570 Bus use state 0 0 DRAM refresh 0 1 Hold 1 0 DMA 1 1 CPU AVcc Analog supply input The power supply
383. load registers contents are reloaded and counting continues The timer Ai interrupt request bit is set to 1 at the underflow The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 8 3 4 shows an example of operation in the timer mode n Reload register s contents Starts counting Stops counting 1 fi X n 1 i 1 1 Counter contents Hex Set to 1 by software Cleared to 0 by software to 1 by software 4 Count start bit i Timer Ai interrupt request bit fi frequency of count source fe fie fos fora Cleared to 0 when interrupt request is accepted or cleared by software Fig 8 3 4 Example of operation in timer mode without pulse output and gate functions 8 14 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 4 Selectable functions The following describes the selectable gate function for Timers A2 to A4 and pulse output function 1 Gate function The gate function is selected by setting the gate function select bits bits 4 and 3 at addresses 5816 to 5A16 to 102 or 112 The gate function makes it possible to start or stop counting depending on the TAjin pin s input signal Table 8 3 3 lists the count valid levels Figure 8 3 5 shows an example of operation with the gate function selected W
384. lse Note The above applies when an external trigger falling edge of TAjin pin s input signal is selected Fig 8 5 6 Output delay in one shot pulse output 3 When the timer s operating mode is set by one of the following procedures the timer Aj interrupt request bit is set to 1 e When the one shot pulse mode is selected after reset e When the operating mode is switched from the timer mode to the one shot pulse mode e When the operating mode is switched from the event counter mode to the one shot pulse mode Accordingly when using the timer Aj interrupt interrupt request bit be sure to clear the timer Aj interrupt request bit to 0 after the above setting 4 Don not set 0000 e to the timer Aj register 7721 Group User s Manual 8 37 TIMER A 8 6 Pulse width modulation PWM mode 8 6 Pulse width modulation PWM mode In this mode the timer continuously outputs pulses which have an arbitrary width Refer to Table 8 6 1 Timers A2 to A4 can be used in this mode Figure 8 6 1 shows the structures of the timer Aj mode registers and timer Aj registers in the PWM mode Table 8 6 1 Specifications of PWM mode Item Specifications Count source fo fie fea Or fs12 Count operation Countdown operating as 8 bit or 16 bit pulse width modulator Reload register s contents are reloaded at rising edge of PWM pulse and counting continues A trigger generated during counting does not
385. ltiple interrupts are processed Figure 7 9 1 shows the processing for multiple interrupts An interrupt request which has not been accepted because its priority level is lower is held When the RTI instruction is executed the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled into the IPL Therefore if the following relationship is satisfied when interrupt priority level detection is performed next the held interrupt request is accepted Held interrupt request s priority level gt Processor interrupt priority level IPL 7 16 7721 Group User s Manual Interrupt request generated INTERRUPTS 7 9 Multiple interrupts Nesting gt Reset Interrupt 1 Interrupt priority level 3 Interrupt 2 Interrupt priority level 5 Interrupt 3 Interrupt priority level 2 r Main routine Multiple interrupts This request cannot be accepted because its priority level is lower than the interrupt 1 s one lt The instruction in the main routine is not executed Interrupt 3 Interrupt disable flag IPL Processor interrupt priority level 2 They are automatically set L They must be set by software Fig 7 9 1 Processing for multiple interrupts 7721 Group User s Manual 7 17 INTERRUPTS 7 10 External interrupts INTi interrupt 7 10 External interrupts INTi interrupt An external inter
386. m to 41 during a DMA transfer when the TC pin is valid Writes 0 to the DMAi enable bit Table 13 3 5 lists the states of DMAC at forced termination Table 13 3 5 States of DMAC at forced termination Item State interrupt request bit Not changed request bit 0 DMAi enable bit 0 output Not changed Channel priority levels Not changed When the TC is used for forced termination select TC pin valid bit 1 at address 68 1 Forced termination by the TC input is valid in the following cases During a DMA transfer in the burst transfer mode edge sense During the term from the DMA transfer start until the transfer completion of an entire batch of data in the burst transfer mode with the level sense selected It is also valid while the CPU has the right to use bus During a DMA transfer in the cycle steal transfer mode Forced termination by the TC input is invalid while the CPU has the right to use bus pin s input is determined at the falling edge of and DMAC will relinquish the right to use bus to the CPU upon completion of the 1 unit transfer under execution at that time At the forced termination by the DMAi enable bit 0 is written to this bit at the rising edge of E of a write cycle to the DMAi enable bit Accordingly DMAi is disabled after this write 7721 Group User s Manual 13 27 DMA CONTROLLER 13 3 Control 1
387. m TAjout pin Timer Aj interrupt request bit fi Frequency of count source f2 f16 fea or f512 Cleared to 0 when interrupt request is accepted or cleared by software When the count start bit 0 counting stopped the TAjour pin outputs L level When a trigger is generated during counting the counter counts the count source n 1 times after a new trigger is generated Note The above applies when an external trigger rising of TAjin pin s input signal is selected Fig 8 5 5 Example of operation in one shot pulse mode selecting external trigger 8 36 7721 Group User s Manual TIMER A 8 5 One shot pulse mode Precautions for one shot pulse mode 1 If the count start bit is cleared to 0 during counting the counter becomes as follows counter stops counting and the reload register s contents are reloaded into the counter The TAjour pin s output level becomes L The timer Aj interrupt request bit is set to 1 2 A one shot pulse is output synchronously with an internally generated count source Accordingly when selecting an external trigger there will be a delay equivalent to one cycle of the count source at maximum from when a trigger is input to the pin until a one shot pulse is output Trigger input TAjin pin s input signal Y NN Count source i Y i output from TAjour pin Starts outputting of one shot pulse One shot pu
388. mable port 1 Valid The pin functions as DMAACKi Metis tL Nothing is assigned Undefined Note When a certain source other than an external source is selected by bits 0 to 3 or when the cycle steal transfer mode is selected set bit 4 to 0 Level sense can be selected only when both of the external source and the burst transfer mode are selected 1 2 3 4 5 7 6 7721 Group User s Manual 17 39 APPENDIX Appendix 4 Package outline Appendix 4 Package outline 1 65 Plastic 1 OOpin 14 2 body EIAJ Package Code JEDEC Code Weight g Lead Material QFP100 P 1420 065 158 Alloy42_ Scale 2 1 c 013 015 02 138 140 142 E 198 220 202 L 05 04 06 08 Li L M 05 e p Los 1w Lau 05 Li 15 M 15 26 17 40 7721 Group User s Manual APPENDIX Appendix 5 Examples of handling unused pins Appendix 5 Examples of handling unused pins Examples of handling unused pins are described below These descriptions are just examples The user shall modify them according to the actual application and test them Table 1 Examples of handling unused pins Pins Handling example P4s to P47 P5 to P10 Connect these pins to the Vcc or Vss pin via resistors after these pins are set to the input mode
389. maintained and when the enable bit is set to 1 the request bit is also set to 1 except for the burst transfer mode level sense 13 20 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 3 Channel priority levels When the DMA enable bits of several channels are 1 and their DMA request bits are set to 1 the request of the channel with the highest priority is accepted first The fixed or rotating channel priority can be selected by the priority select bit bit 0 at address 6816 The priority levels themselves cannot be specified arbitrary The channel priority levels are determined after the DMA requests are determined 1 2 Fixed priority The fixed priority is selected when the priority select bit bit 0 at address 6816 0 In the fixed priority the channel priority levels are as follows channel 0 gt channel 1 gt channel 2 gt channel 3 Rotating priority The rotating priority is selected when the priority select bit 1 After reset the priority levels are the same descending order as in the fixed priority channel 0 gt channel 1 gt channel 2 gt channel 3 Then after every normal termination of a DMA transfer the priority levels rotate in such a way that the lowest priority is given to the channel having been performed When transfer is forced into termination the channel priority levels does not rotate Figure 13 3 1 shows
390. mer Bi mode register and timer Bi register in the timer mode Table 9 3 1 Specifications of timer mode Item Count source Specifications fo fie fea Or fs12 Count operation Countdown When a counter underflow occurs reload register s contents are reloaded and counting continues Division ratio 1 n 1 n Timer Bi register s set value Count start condition When the count start bit is set to 1 Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing When a counter underflow occurs pin s function Programmable port Read from timer Bi register Counter value can be read out Write to timer Bi register While counting is stopped When a value is written to the timer Bi register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Bi register it is written only to the reload register Transferred to the counter at the next reload time 7721 Group User s Manual TIMER B 9 3 Timer mode 67 b6 65 64 63 b2 bi bO _ Timer Bi mode register i 0 to 2 Addresses 5816 to 5016 ee RN o Pw sm Nothing is assigned b1 50 00 Timer mode This bit is invalid in timer mode its value is undefined at reading Undefined Count source select bits EE
391. mode b15 b8 b7 b7 50 Timer 1 register Addresses 5316 5216 15 to 0 The measurement result of pulse period or Undefined pulse width is read out Note Read from this register in a unit of 16 bits 67 06 65 64 b3 62 bi Timer Bj mode register 0 1 Addresses 5816 5C16 Bit faw b1 50 Operating mode select bits 1 0 Pulse period Pulse width measurement mode 1 Measurement mode select bits Pulse period measurement Interval between falling edges of measurement pulse Pulse period measurement Interval between rising edges of measurement pulse Pulse width measurement Interval from a falling edge to a rising edge and from a rising edge to a falling edge of measurement pulse Do not select be Sainte amare ae 4 Nothing is assigned Undefined 5 Timer Bj overflow flag No overflow Undefined Note Overflowed Count source select bits Note The timer Bj overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit 1 17 26 7721 Group User s Manual APPENDIX Appendix 3 Control registers Processor mode register 0 b7 06 b5 04 b3 b2 bli TORTNE 5 Processor mode register 0 Address 5 16 Fix this bit to 0 is assigned value is 1 at reading 2 Wait bit 0 Software Wait is
392. mode with no request of DMA0 3 SARi latch indicates the start address of the transfer parameter memory of the next block TCRi latch indicates the number of remaining transfer blocks Note The above figure applies when 2 bus cycle transfer is performed When data is transferred from memory to I O in 1 bus cycle transfer there is no DARi lt Transfer parameter When data is transferred from I O to memory in 1 bus cycle transfer there is SARI Transfer parameter Fig 13 7 6 Operation flowchart of array chain transfer mode 13 76 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode 00 4 puooes 1 0014 15414 u zes u zes zes w es w es pes siajowesed 1 S xoo g SJejeure ed 2 5 20 1514 lt OVW lt 9 5 00 1511 Jo SSeJppe BIS ON ON pJeM04 sung o9 oKo snq z 51891 51991 peideooe si pue SI jeubis Burdures sng pejdures si 10 useJjeJ pesneo 1senbei sng eu1 e snq esn 0 1 198 HOL dy Zep pes Jejsuei
393. mpling starts an interrupt request is accepted The interrupt priority level detection time can be selected by software Figure 7 6 1 shows the interrupt priority level detection time Usually select 2 cycles of 0 as the interrupt priority level detection time 1 Interrupt priority detection time select bits 67 66 b5 64 b3 62 61 LBLLLLLI Processor mode register 0 Address 5E16 Lt L Processor mode bits Wait bit Software reset bit 00 7 cycles of e shown below 4 cycles of b shown below Must be fixed to 0 Clock 1 output select bit 2 Interrupt priority level detection time Op code fetch cycle Sampling pulse a 7 cycles Interrupt priority level detection time 0 4 cycles c 2 cycles EE epp Toe WP De L 3l Note Oe ____ Note The pulse resides when 2 cycles of is selected Fig 7 6 1 Interrupt priority level detection time 7 12 7721 Group User s Manual INTERRUPTS 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine The sequence from the acceptance of interrupt request until the execution of the interrupt routine is described below When an interrupt request is accepted the interrupt request bit of the accepted interrupt is cleared to 0 And then the int
394. n 7721 Group User s Manual 11 41 SERIAL I O 11 4 Clock asynchronous serial I O UART mode UARTO transmit receive mode register Address 3016 AAA EEE aa ea UART1 transmit receive mode register Address 3816 UARTO baud rate register BRGO Address 3116 UART1 baud rate register BRG1 Address 3916 b7 Can be set to 0016 to FF 16 b2b1b0 100 UART mode 7 bits 101 UART mode 8 bits 110 UART mode 9 bits Internal External clock select bit 0 Internal clock 1 External clock Stop bit length select bit 0 1 stop bit Port P8 direction register Address 1416 1 2 stop bits 57 50 Odd Even parity select bit 0 Odd parity 1 Even parity RxDo pin RxD1 pin Parity enable bit 0 Parity disabled 1 Parity enabled Sleep select bit 0 Sleep mode terminated Invalid 1 Sleep mode selected UARTO receive interrupt control register Address 7216 UART1 receive interrupt control register Address 7416 b7 50 imma 127 Note Set the transfer data format in the same way as set on the transmitter side Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 UARTO transmit receive control register 0 Address 3416 N UART1 transmit receive control register 0 Address 3Ct6 b7 50 BRG count source select bits b1b0 00 fe 0
395. n IPL When an interrupt request is accepted IPL is stored in the stack area and IPL is replaced by the interrupt priority level of the accepted interrupt request There are no instruction to directly set or clear the bits of IPL IPL can be changed by storing the new IPL into the stack area and updating the processor status register with the PUL or PLP instruction The contents of IPL is cleared to 000 gt at reset 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 Bus interface unit A bus interface unit BIU is built in between the central processing unit CPU and memory l O devices BIU s function and operation are described below When externally connecting devices refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 2 2 1 Overview Transfer operation between the CPU and memory l O devices is always performed via the BIU The reads an instruction from the memory before the CPU executes it When the CPU reads data from the 1 device the CPU first specifies the address from which data is read to the BIU The BIU reads data from the specified address and passes it to the CPU When the CPU writes data to the memoryel O device the CPU first specifies the address to which data is written to the BIU and write data The BIU writes the data to the specified address To perform the above operations to the inputs and outputs the control sig
396. n operate at high speed without waiting for access to the memory which requires a long access time When the instruction queue buffer becomes empty or contains only 1 byte of an instruction the BIU performs instruction prefetch The instruction queue buffer can store instructions up to 3 bytes The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed and the BIU reads a new instruction from the destination address When instructions in the instruction queue buffer are insufficient for the CPU s needs the BIU extends the pulse duration of clock CPU in order to keep the CPU waiting until the BIU fetches the required number of instructions or more Reading data from device The CPU specifies the storage address of data to be read to the BIU s data address register and requires data The CPU waits until data is ready in the BIU The BIU outputs the address received from the CPU onto the address bus reads contents at the specified address and takes it into the data buffer The CPU continues processing using data in the data buffer However if the BIU uses the bus for instruction prefetch when the CPU requires to read data the BIU keeps the CPU waiting Writing data to memory l O device The CPU specifies the address of data to be written to the BIU s data address register Then the CPU writes data into the data buffer The BIU outputs the address received from the CPU onto th
397. n to memory simultaneously R W L level TCRi latch Transfer DMAACKi DMA latch source When the transfer unit is 16 bits the incrementer decrementer and the decrementer increment or decrement by 2 Note In the single transfer mode and repeat transfer mode only at the first transfer of the block the values read from SARi latch DARi latch and TCRi latch are used The results obtained by increment or decrement are written to SARI DARI and TCRi Except for the first transfer of the block the values read from SARi and TCRi are used Fig 13 4 6 Basic operation of registers for 1 unit transfer in 1 bus cycle transfer 13 40 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 2 Bus operation in 1 bus cycle transfer The time required for 1 unit transfer in 1 bus cycle transfer is given by the following formulas Transfer from memory to I O Transfer time per 1 unit transfer Read cycle of memory Transfer from I O to memory Transfer time per 1 unit transfer Write cycle of memory In 1 bus cycle transfer 1 transfer unit data is accessed in 1 bus cycle so that limitations are imposed on the transfer conditions to be applied Table 13 4 5 lists the conditions of 1 bus cycle transfer and the transfer time per 1 unit transfer and Figure 13 4 7 shows the bus cycle operation waveforms in 1 bus cycle transfer Table 13 4 5 Conditions of 1 bus cycle transfer and Transfer time per 1 uni
398. nals and control the bus Figure 2 2 1 shows the bus and bus interface unit BIU 7721 Group User s Manual 2 9 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 1noqe SH UOISJOGAUOO eu491X3 LY 01 OY 849 1 1 y JO SAOIAAG TVNH3IX3 HLIM NOILO3NNOO 6 YSLdVHO 0 1994 2 Jeujoue euo JO juepuedepui snq pue eujejul SNG 24L L SIJON 1 0 oy sng eujelu Zq 01 snq 9 0180 snq eujo u hau d 1 15 uonoun J eroeds HJS nig yun eoepelul sng BuisseooJud LoZZEW Fig 2 2 1 Bus and bus interface unit BIU 7721 Group User s Manual 2 10 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 2 Functions of bus interface unit BIU The bus interface unit BIU consists of four registers shown in Figure 2 2 2 Table 2 2 1 lists the functions of each register 50 Program address register b7 50 L Instruction queue buffer 02 50 Data address register Data buffer Fig 2 2 2 Register structure of bus interface unit BIU Table 2 2 1 Functions of each register Name
399. ncy lt 4 Watchdog timer count Bit 4 of port P10 register Port P104 CAS select bit bit 0 at address 61 source fs selected address 16 6 L level output Bits 4 5 of port P10 register 4 Bit 5 of port P10 register lt O Port P105 RAS address 16 6 address 1616 L level output Ports P104 P10s H level output Bits 4 5 of port P10 directions 1 Bit 4 of port P10 register lt 1 Port P104 CAS register address 18 6 address 16 6 level output DRAM validity bit o DRAMC stopped Bit 5 of port P10 register lt 1 Port P10s RAS bit 7 at address 6416 WIT instruction Wait mode Y Wait mode completed Return to main routine Note By using 1 bit of RAM judge whether this interrupt is for return from the wait mode or for refresh address 16 6 level output 17 74 7721 Group User s Manual APPENDIX Appendix 9 7721 GroupQ amp A DRAM WIT instruction 2 Method using timer A or timer B Return from the wait mode by a timer A or timer B interrupt every definite time Control ports P104 P10s by software and perform the CAS before RAS refresh Example 2 A case in 512 refresh cycles every 64 ms f Xin 25 MHz timer AO used DRAM refresh is performed 512 times by timer AO interrupts This interrupt occurs every 64 ms See flow chart Q Flow chart Timer AO interrupt routine Bits 4 5 of port P10 register 1
400. nearity error 12 12 EE PDT TRE 12 12 12 4 2 Differential non dean OOM A E E 12 13 12 14 12 14 12 5 2 One shot mode operation description eeeeee nnn 12 16 12 17 12 6 1 Settings for repeat modebl eeeee nnnm 12 17 G 12 19 12 20 dunt asennad Geta 12 20 12 7 2 Single sweep mode operation 3 1 2 Bus use priorit Su e 13 3 E 0 A 13 3 iat ths thi HE 13 6 13 2 1 Bus access control circuit 13 7 13 2 2 DMAC control register LJ 13 10 13 2 3 DMAC control register 22 2 13 11 13 2 4 Source address register i SARI 13 12 13 2 5 Destination address register i 0 40400 13 12 13 2 6 Transfer counter register i 44 13 12 Rm 13 13 32226 Decrement 13 13 I ODA RET 13 13 13 2 10 mode register 1 13 14 13 2 11 mode register 13 15 13 2 12
401. ng byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register 7721 Group User s Manual 17 35 APPENDIX Appendix 3 Control registers Array chain transfer mode b23 b16 b15 b8 b7 bO Addresses 1FC216 to 1FC016 Addresses 1 0216 to 1FDO16 Addresses 1FE216 to 1FE016 Addresses 1 216 to 1 16 Source address register 0 Source address register 1 Source address register 2 Source address register 3 OL L Write 9100 Set the start address of transfer parameter memory ELA These bits can be set to 00000016 to FFFFFF e Read After a value is written to this register and until transfer starts the read value indicates the written value the start address of the transfer parameter memory After tranfer starts the read value indicates the Source address of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 b15 b8 b7 Addresses 1 to 1 416 Addresses 1 061 to 1FD416 Addresses 1FE616 to 1FE416 Addresses 1FF616 to 1FF416 Destination address register 0 Destination address register 1 Destination address register 2 Destination address register 3 23 to 0 Need not to set Undefined RW Read After transfer starts the read value indicates the destination address of data which is next transferred b23 b16 b15 b8 b7 bO
402. ng mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR 7721 Group User s Manual Exclusive OR Negation Movement to the arrow direction Accumulator Accumulator s upper 8 bits Accumulator s lower 8 bits Accumulator A Accumulator A s upper 8 bits Accumulator A s lower 8 bits Accumulator B Accumulator B s upper 8 bits Accumulator B s lower 8 bits Index register X Index register X s upper 8 bits Index register X s lower 8 bits Index register Y Index register Y s upper 8 bits Index register Y s lower 8 bits Stack pointer Program counter Program counter s upper 8 bits Program counter s lower 8 bits Program bank register Data bank register Direct page register Direct page register s
403. nit ns Fig 16 1 33 Timing chart for example of M5M44400CJ 1M X 4 bits connection external bus width 16 bits 7721 Group User s Manual 16 37 APPLICATION 16 1 Memory connection 10 Example of DRAM connection external bus width 16 bits M37721 M5M44260CJ 7 Make sure that the propagation delay time is within 20 ns Make sure that the propagation delay time is within 7 5 ns Memory map 000000 000080 nterna wx RAV Not used 16 00 001FCO mae 001 FFF A18 D2 A19 D3 A20 D4 A21 D5 22 06 Not used 23 07 As Ds 10 D10 A11 D11 F0000016 DRAM area A12 D12 A13 D13 7 M5M44260CJ 14 014 15 015 Not used FFFFFF16 25 MHz Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 34 Example of M5M44260CJ 256K X 16 bits connection external bus width 16 bits 16 38 7721 Group User s Manual lt When reading gt APPLICATION 16 1 Memory connection tw EL 135 min tw RASL 120 min tw RASH 30 max td E RASL 60 min td RAS CAS td E CASL td RA RAS 77 5 5 28 tw CASL 92 5 td CA CAS 5 min 5 Column address Row addres td E CA 60 A16 D0 A23 D7 Address As Ds A15 D15 td BLE BHE E
404. nq esn 1 pun JUM gt 4 d 10 uonisueJ 015 LLS 21 IMOVVING Buiduues sng 40 82 00 9 20 le transfer mode burst transfer mode ing fs iagram o 6 Timing d 5 13 19 7721 Group User s Manual 13 60 DMA CONTROLLER 13 6 Repeat transfer mode 13 6 Repeat transfer mode This mode is used to transfer one block of data repeatedly Table 13 6 1 lists the specifications of the repeat transfer mode and Figure 13 6 1 shows the register structures of SARi DARi and TCRi in this mode Table 13 6 1 Specifications of repeat transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Performance specifications Not required No normal termination Falling edge of the TC pin s input from H to L when the TC pin validity bit 1 e Write 0 to the enable bit No request is generated SARi latch Indicates the transfer start address of data block at the transfer source SARi Indicates the address of the next transfer source DARi latch Indicates the transfer start address of data block at the transfer destination DARi Indicates the address of the next transfer destination TCRi latch Indicates the number of transfer bytes TCRi Indicates the number of remaining bytes being tran
405. nsfer Link array chain Register mode transfer mode SARi SARi Indicates the transfer source address of the data to be transferred next SARi latch Maintains the transfer start address of the Indicates the start address of the transfer source parameter memory of the next block DARi DARi Indicates the transfer destination address of the data next to be transferred DARi latch Maintains the transfer start address of the Not used Not used destination TCRi TCRi Indicates the number of remaining bytes of the block under transfer TCRi latch Maintains the byte number of the transfer Indicates the number Not used Note data of remaining blocks Note Any value other than 0 000001 6 must be written before DAM transfer 13 2 7 Incrementer Decrementer The incrementer decrementer is a 24 bit register After every 1 unit transfer that increments adds or decrements subtract the contents of SARi and DARi Table 13 2 6 lists the increment decrement values Table 13 2 6 Increment Decrement values Address directions Transfer unit Forward Backward 8 bits 1 1 16 bits 2 2 13 2 8 Decrementer The decrementer is a 24 bit register After every 1 unit transfer that decrements the contents of TCRi by 1 when the transfer unit is 8 bits and by 2 when 16 bits In the array chain transfer mode every time a transfer parameter is read the contents of the TCRi lat
406. nsfer source s transfer start address 4 Transfer data s byte number 4 The above applies on the following conditions When data is transferred from memory to I O DMA CONTROLLER 13 7 Array chain transfer mode Transfer L Even address source s transfer M start address H Transfer L Even address destination s transfer M start address H Dummy data L Even address Transfer data s M byte number B JO SJejeueJed Dummy data L Even address source s transfer M Transfer start address H Transfer data s byte number 104 5 Jesu When transferring from I O to memory replace all the above mentioned Transfer source s transfer start address with Transfer destination s transfer start address 4 block transfer Fig 13 7 2 Transfer parameter memory map in array chain transfer mode 7721 Group User s Manual 13 71 DMA CONTROLLER 13 7 Array chain transfer mode 13 7 2 Setting of array chain transfer mode Figures 13 7 3 through 13 7 5 show an initial setting example for registers relevant to the array chain transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function When a DMAi interrupt is used the setting for enabling the interrupt is also required For
407. nsmit receive interrupt request occurs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag 1 0 To disable transmit receive interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 The UARTi transmit interrupt request bit is set to 1 when data is transferred from the UARTi transmit buffer register to the UARTi transmit register The UARTi receive interrupt request bit is set to 1 when data is transferred from the UARTi receive register to the UARTi receive buffer register However when an overrun error occurs it does not change Each interrupt request bit is automatically cleared to 0 when its corresponding interrupt request is accepted This bit can be set to 1 or 0 by software 11 14 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 8 Port P8 direction register pins of UARTi are multiplexed with port P8 When using pins P82 and 86 as serial data input pins RxDi set the corresponding bits of the port P8 direction register to 0 to set these pins for the input mode When using pins P80 P8 8 to P8s and P87 as I O pins CTS RTSi TxDi of UARTI these pins are forcibly set as I O pins of UARTi regardless of the port P8 direction register s contents Figu
408. ntents of the stack pointer S are even the contents of the program counter PC and the processor status register PS are simultaneously pushed in a unit of 16 bits When the contents of the stack pointer S are odd each of these registers is pushed in a unit of 8 bits Figure 7 7 3 shows the push operation for registers In the INTACK sequence only the contents of the program bank register PG program counter PC and processor status register PS are pushed onto the stack area The other necessary registers must be pushed by software at the start of the interrupt routine By using the PSH instruction all CPU registers except the stack pointer S can be pushed 1 When contents of stack pointer S are even I ven Address S 5 odd S 2 even Low order byte of program counter PCL High order byte of program counter m bank register PG S 1 odd S even Pushed in 3 times 2 When contents of stack pointer S are odd Address S 5 even S 4 odd S 3 even Low order byte of processor status register PSL 4 High order byte of processor status register PS S 2 odd Low order byte of program counter Pushed in a unit of 8 bits S 1 even S odd High order byte of program counter Se bank register PG Pushed in 5 times S is an initial address that the stack pointer S indicates when an inte
409. nter decrementer and the decrementer are loaded in each register Values are used by reading them from registers at the second and the following 1 unit transfers Latch Transfer source destination address is specified Previously written values Contents are updated by incrementer decrementer and decrementer Addresses which were to be transferred subsequently or the number of remaining bytes Q Updated contents are written c When reading values at addresses of SARi DARi and TCRi after forced termination and rewriting them Latch Written by software Previously written values Register Addresses which were to be Addresses which were to be transferred subsequently or the transferred subsequently or the number of remaining bytes number of remaining bytes Read by software Fig 13 3 4 States of SARi DARi TCRi after forced termination 7721 Group User s Manual 13 29 DMA CONTROLLER 13 4 Operation 13 4 Operation Operation of 1 unit transfer varies according to the data transfer method 2 bus cycle or 1 bus cycle transfer In addition how many units of transfer data are transferred for a DMA request varies according to the transfer mode burst transfer or cycle steal transfer mode These data transfer methods and modes are described below 13 4 1 2 bus cycle transfer When the transfer method select bit Refer to Figure 13 2 6 0 2 bus cycle transfer is selected 2 bus cycle transfer is
410. ntial difference between the Vss level of the microcomputer and the Vss level XIN d of an oscillator the correct clock XOUT will not be input in the Vss Vss microcomputer Not acceptable Acceptable Fig 4 Wiring for clock input output pins 7721 Group User s Manual 17 59 APPENDIX Appendix 8 Countermeasure against noise 3 Wiring for CNVss pin Connect CNVss pin to the Vss pin with the shortest possible wiring Reason The processor mode of the microcomputer is influenced by a potential at the CNVss pin when the CNVss pin and the Vcc or Vss 37721 Noise 37721 are connected If the noise causes a potential difference between the CNVss pin CNVss and the Vss or Vcc pin the processor mode may become Vss unstable This may cause a microcomputer malfunction or a Not Acceptable Acceptable When connecting the CNVssand Vcc pins connect them inthe shortest possible distance also Fig 5 Wiring for CNVss pin 2 Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0 1 uF bypass capacitor as follows Connect a bypass capacitor between the Vss and Vcc pins at equal lengths The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible Use thicker wiring for the Vss and Vcc lines than that for the other signal lines Bypass capacitor Wiring pattern Wiring pattern Vss Vcc M37721 Fig
411. nual 17 61 APPENDIX Appendix 8 Countermeasure against noise 2 Processing for analog power source pins etc Use independent power sources for the Vcc AVcc and Vrer pins Insert capacitors between the AVcc and AVss pins and between the and AVss pins Reasons Prevents the A D converter from noise on the Vcc line M37721 Reference values C1 2 0 47 uF C2 gt 0 47 uF Note Connect capacitors using the thickest shortest wiring possible sensor etc Fig 8 Processing for analog power source pins etc 17 62 7721 Group User s Manual APPENDIX Appendix 8 Countermeasure against noise 4 Oscillator protection The oscillator which generates the basic clock for the microcomputer operations must be protected from the affect of other signals 1 Distance oscillator from signal lines with large current flows Install the microcomputer especially the oscillator as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance 2 3 Reason The microcomputer is used in systems which contain signal lines for controlling motors LEDs thermal heads etc Noise occurs due to mutual inductance when a large current flows through the signal lines M37721 Mutual inductance Large current Fig 9 Wiring for signal lines where large current flows Distance oscillator from signal lines with frequent potentia
412. o 0 1 A D control register address 1E16 5129 Analog input select bits b2 b1 b0 0 0 0 ANo selected AN selected AN2 selected ANs selected AN4 selected AN5 selected selected AN7 selected Repeat mode Trigger select bit 0 Internal trigger 1 External triggeer A D conversion start bit 0 Stop A D conversion A D conversion frequency select bit 0 fe divided by 4 1 fe divided by 2 Port P7 direction register b7 50 Port P7 direction register address 1116 ANo AN AN2 Set the bits corresponding AN3 to analog input pins to 0 AN4 Set bit 7 to 0 when ANs selecting external trigger AN6 AN7 d D G Set A D conversion start bit to 1 b7 b0 1 A D control register address 1E16 A D conversion start bit E hen external trigger is selected When internal trigger is selected Input falling edge to ADrne pin A Trigger occur Operation start Note Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts before a trigger occurs Fig 12 6 1 Initial setting example for registers relevant to repeat mode 12 18 7721 Group User s Manual A D CONVERTER 12 6 Repeat mode 12 6 2 Repeat mode operation description 1 When an internal trigger is selected The A D converter starts operation when the conversion start bi
413. o 0 at address 6416 00102 Fig 16 1 32 Example of M5M44400CJ 1M X 4 bits connection external bus width 16 bits 16 36 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt 135 min tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max lt gt td E CASL 77 5 max tw CASL 92 5 min Lac RARAS 5 min td CA CAS 5 min MAo MA9 Row address Column address tOEA 20 max tAA 35 max tRAC 70 max gt td E CA 60 max 16 00 23 07 lt When writing gt tw EL 135 min lt tw RASH 60 min gt tpzx E DLZ DHZ 20 min gt tcLz 5 min 0 9 20 max tsu DL DH E gt 30 toEZ 0 20 tw RASL 120 min tw CASL 55 min itd E CASL 80 115 id R W E 20 min IAC32 tPHL X 2 C32 tPHL X 2 twcs 0 min i min gt e 10 min td RA RAS 5 min RAS RA 18 min Row address Column address gt lt d CA CAS 10 min th CAS CA 60 min A16 D0 A23 D7 As Ds A15 D15 Address Data gt td BLE BHE E 20 min tDH 15 min lt gt th E DLQ DHQ 18 min BLE BHE Specifications of 5 44400 7 The others are specifications of M37721 U
414. o Vcc pin Fig 2 Examples of handling unused pins 7721 Group User s Manual 17 41 APPENDIX Appendix 6 Machine instructions Appendix 6 Machine instructions Functions Details Addressing modes R b DIR X D R Y n op n ADC Notes 1 2 Acc C lt Acc M C Adds the carry the accumulator and the memory contents The result is entered into the accumulator When the flag is 0 binary additions is done and when the D flag is 1 decimal addition is done 75 5 2 42 75 AND Notes 1 2 Acce AccaM Obtains the logical product of the contents of the accumu lator and the contents of the memory The result is en tered into the accumulator 35 42 35 ASL Note 1 Shifts the accumulator or the memory contents one bit to the left O is entered into bit 0 of the accumulator or the memory The contents of bit 15 bit 7 when the m flag is 1 of the accumulator or memory before shift is entered into the C flag 16 BBC Notes 3 5 Tests the specified bit of the memory Branches when all the contents of the specified bit is 0 BBS Notes 3 5 Tests the specified bit of the memory Branches when all the contents of the specified bit is 1 BCC Note 3 Branches when the contents of the flag is 0 BCS Note 3 Branches when ents he C flag is 1
415. ode 8 4 Event counter mode Precautions for event counter mode 8 5 One shot pulse mode Precautions for one shot pulse mode 8 6 Pulse width modulation PWM mode Precautions for pulse width modulation PWM mode TIMER A 8 1 Overview 8 1 Overview Timer A consists of five counters Timers AO to A4 each equipped with a 16 bit reload function Timers AO to A4 operate independently of one another Timer A has four operating modes listed below Timers AO and 1 operate in the timer mode only Timers A2 to A4 have selective four operating modes listed below 1 2 3 4 Timer mode Timers 0 to 4 The timer counts an internally generated count source For Timers 2 to 4 the following functions can be used in this mode Gate function Pulse output function Event counter mode Timers A2 to A4 The timer counts an external signal The following functions can be used in this mode Pulse output function Two phase pulse signal processing function One shot pulse mode Timers A2 to A4 The timer outputs a pulse which has an arbitrary width once Pulse width modulation PWM mode Timers A2 to A4 Timer outputs pulses which have an arbitrary width in succession The counter functions as one of the following pulse width modulators 16 bit pulse width modulator 8 bit pulse width modulator In this chapter Timer Ai i 0 to 4 indicates Timers AO to A4 Timer Aj j 2 to 4 indicates Timers A2 to
416. ode select bits 0 0 One shot mode 0 1 Repeat mode 10 Single sweep mode 1 1 Repeat sweep mode Trigger select bit 0 Internal trigger 1 External trigger A D conversion start bit Stop conversion Start A D conversion A D conversion frequency 0 fe divided by 4 AD select bit 1 fe divided by 2 Notes 1 These bits are ignored in the single sweep and repeat sweep mode They may be either 0 or 1 2 When an external trigger is selected the AN7 pin cannot be used as an analog input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts Fig 12 2 2 Structure of A D control register 1 Analog input select bits bits 2 to 0 These bits are used to select an analog input pin in the one shot mode and repeat mode Pins which are not selected as analog input pins function as programmable ports These bits must be set again when the user switches the A D operation mode to the one shot mode or repeat mode after A D conversion is performed in the single sweep mode or repeat sweep mode 12 4 7721 Group User s Manual A D CONVERTER 12 2 Block description 2 Trigger select bit bit 5 This bit is used to select the source of trigger occurrence Refer to section 3 A D conversion start bit 3 A D conversion start bit bit 6 When internal trigger is selected Setting this bit to 1 generates a trigger
417. of levels 1 to 7 When disabling interrupts set these bits to level 0 2 When external trigger is selected When internal trigger is selected Setting port P5 direction register Setting count start bit to 1 b7 Port P5 direction register 57 bo Address Die Count start register Address 4016 TA2IN pin Timer A2 count start bit TASIN pin TA4IN Timer A3 count start bit Timer A4 count start bit Clear the corresponding bit to 0 Setting count start bit to 1 b7 60 Count start register Address 4016 Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Trigger input to TAjiN pin wT Trigger generated Count Fig 8 6 3 Initial setting example for registers relevant to PWM mode 2 7721 Group User s Manual 8 41 TIMER A 8 6 Pulse width modulation PWM mode 8 6 2 Count source In the PWM mode the count source select bits bits 6 and 7 at addresses 58 to 5 select the count source Table 8 6 2 lists the count source frequency Table 8 6 2 Count source frequency Count source Count Count source frequency select bits source b7 b6 f Xin 8 MHz f Xin 16 MHz f Xin 25 MHz 0 0 f2 4 MHz 8 MHz 12 5 MHz 0 1 fie 500 kHz 1 MHz 1 56
418. ollowing addressing modes use the direct page register The contents of the direct page register indicate the base address the lowest address of the direct page area The space which extends to 256 bytes above that address is specified as a direct page The direct page register can contain a value from 000016 to FFFF e When it contains a value equal to or more than FF01 e the direct page area spans the space across banks 0 e and 116 When the contents of low order 8 bits of the direct page register is 0016 the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not 0016 Accordingly the access efficiency can be enhanced in this case This register is cleared to 0000 e at reset Figure 2 1 4 shows a setting example of the direct page area e Addressing modes using direct page register Direct Direct bit Direct indexed X Direct indexed Y Direct indirect Direct indexed X indirect Direct indirect indexed Y Direct indirect long Direct indirect long indexed Y Direct bit relative Direct page area when DPR 000016 Direct page area when DPR Bank 016 0123 e Note 1 FFFF16 1000016 1000 1 Bank 116 Direct page area when DPR FF 1016 Note 2 6 Notes 1 The number of cycles required to generate an address is 1 cycle smaller when the low order 8 bits of the DPR are 0046 2 The direct page area spans the space
419. on Transfer source Wait Transfer destination Wait sal sa2 dal da2 1 1 Transfer block s number Right to use bus First block s transfer parameter Second block s transfer parameter tp2 12 16 bits 16 bits 2 bus cycle transfer Burst Figure 13 8 7 and Figure 13 8 8 Cycle steal Figure 13 8 10 through Figure 13 8 14 Forward Forward No No Transfer parameter even Start address of first block s transfer parameter memory 2 CPU 2 DMAC CPU Memory dal First block transfer 1 1 1 Second block transfer da2 Fig 13 8 9 Conditions necessary for timings shown in Figures 13 8 7 13 8 8 and 13 8 10 through 13 8 14 7721 Group User s Manual 13 91 DMA CONTROLLER 13 8 Link array chain transfer mode eyeis Aene ue ui pajdoooe jou Jeujo y 5 5 941 pejdeooe si pue sng esn 1u8u ay 3y ul SI jeuBrs sng eui si yg Aq pesneo jsenbaJ sng eu e pejdeooe si pue SI jeuDis jsanbas sng y pejdures si 10 useJjeJ WHC Aq pesneo jsenbas sng eu e 4 6 9 I enDiJ Ul 2 151 BU Bursseooud 10 eiui jo ejduexe y si au sng esn 011ufu uonisuej 4 5 gt i ejejs Aey i i
420. on the ADC instruction 3 Bit 2 Interrupt disable flag 1 It disables all maskable interrupts interrupts other than watchdog timer the BRK instruction and zero division Interrupts are disabled when this flag is 1 When an interrupt request is accepted this flag is automatically set to 1 to avoid multiple interrupts Use the SEI or SEP instruction to set this flag to 1 and use the CLI CLP instruction to clear it to 0 This flag is set to 1 at reset 4 Bit 3 Decimal mode flag D It determines whether addition and subtraction are performed in binary or decimal Binary arithmetic is performed when this flag is 0 When it is 1 decimal arithmetic is performed with 8 bits treated as two digits decimal the data length flag m 1 or 16 bits treated as four digits decimal the data length flag 0 Decimal adjust is automatically performed Decimal operation is possible only with the ADC and SBC instructions Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 This flag is cleared to 0 at reset 5 Bit 4 Index register length flag x It determines whether each of index register X and index register Y is used as a 16 bit register or an 8 bit register That register is used as a 16 bit register when this flag is 0 and as an 8 bit register when it is 1 Use the SEP instruction to set this flag to 1 an
421. on of BUS REQUEST Hold 1bus cycle Bus request sampling ST1 STO re gt used by ag Hold state Transition of right Transition of right CPU Transition of right Transition of right to use bus to use bus to use bus to use bus E DMA transfer This is the term in which the bus is not used so that sampling is performed every 1 cycle of 6 DMAREQi 0 Sampling is performed after completion of 1 unit transfer f Sampling is performed after completion of request bit 1 bus cycle BUS REQUEST DMAC Bus request sampling ST1 STO uva 5 oo MA transfer Bus used DMA transfer gt gt gt Transition of right Transition of right by CPU Transition of right Transition of right to use bus to use bus to use bus to use bus The above applies on the following conditions Cycle steal transfer mode DMA request source external request DMAREQi 1 bus cycle transfer No Wait This is the term in which the bus is not used so that sampling is performed every 1 cycle of o Sampling is performed after completion of Bus request sampling 1 bus cycle 16 bit data is accessed in a unit of 8 bits so that sampling is performed after ST1 STO 1 1 completion of the second bus cycle OOO Oe oe eer Bus used by CPU 1 gt it When access When 16 bit data is accessed is complete in a unit of 8 bits 1 bus cycle Fig 13 2 3 Timin
422. or the same is performed 2 When the counter operates as an 8 bit pulse width modulator after a trigger is generated the TAjour pin outputs L level which has the same width as level width of the PWM pulse which was set After that the PWM pulse output starts from the TAjour pin 7721 Group User s Manual 8 43 TIMER A 8 6 Pulse width modulation PWM mode 1 fix 216 1 Count source pin s input signal i ME Trigger is not generated by this signal Y 4 1 f x n PWM pulse output from TAjour Timer Aj interrupt request bit fi Frequency of count source 2 64 or 1512 Cleared to 0 when interrupt request is accepted or cleared by software Note The above applies when reload register 000316 and an external trigger rising edge of TAjin pin s input signal is selected Fig 8 6 4 Operation example of 16 bit pulse width modulator n Reload register s contents 1 1 X 216 1 1 fi X 216 1 1 1 x 2 16 1 gt 1 fi X 4 200016 p Counter contents Hex Stops Restarts counting counting pin s input signal PWM pulse output from Y 7 7771 TAjour pin m NEM FFFEte is set to timer Aj 0000 e is set to timer Aj 2000 e is set to timer Aj register registe
423. or 1512 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits lt When operating as an 8 bit pulse width modulator gt b15 b8 b7 50 57 50 D Timer register Addresses 4D16 4 16 Timer A4 register Addresses 4F16 4E16 7 to 0 These bits can be set to 0016 to Undefined WO i Assuming that the set value m PWM pulse s period output from the TAjour is expressed as follows mae i 15 to 8 These bits can be set to 0016 to FE16 Undefined WO Assuming that the set value n the H level width of the PWM pulse output from the TAjour pin is expressed as follows n m 1 fi fi Frequency of count source 116 fea or 1512 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits 67 06 65 64 63 62 bi 00 Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 M 1 b4 b3 AGED 00 Writing 1 to count start register 01 TAjin pin functions as a pro grammable port SPREE 10 Falling edge of pin s input signal 11 Rising edge of pin s input signal A iUm Sn Wallen Zw FE eA ARR og RA cae b7 b6 00 f2 01 16 lt 10 f64 11 f512 17 22 7721 Group User s Manual APPENDIX Appendix 3
424. or leave these pins open after they are set to the output mode Notes 1 2 BLE ALE STO 571 Leave this pin open Xout Note 3 Leave this pin open HOLD RDY Connect these pins to the Vcc pin via resistors These pins are pulled high Note 2 CNVss Connect this pin to the Vcc pin or Vss pin AVcc Connect this pin to the Vcc pin AVss _Vrer Connect these pins to the Vss pin Notes 1 When leaving these pins open after they are set to the output mode note the following these pins function as input ports from reset until they are switched to the output mode by software Therefore voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports Accordingly set these ports to the output mode immediately after reset Software reliability can be enhanced when the contents of the above ports direction registers are set periodically This is because these contents may be changed by noise a program runaway which occurs to noise etc 2 For unused pins use the shortest possible wiring within 20 mm from the microcomputer s pins 3 This applies when a clock externally generated is input to the Xm pin When setting ports to input mode When setting ports to output mode P4s P47 P5 P10 P43 P47 P5 P10 1 eft open STO STi BLE Left open Left open BHE ALE 777 Vss CNVss can be connected t
425. or more Additionally use software to identify whether the measurement result indicates the H level or the L level width Table 9 5 3 Relationship between measurement mode select bits and pulse period pulse width measurements 63 02 Pulse period Pulse width measurement Measurement interval Valid edges 0 0 Pulse period measurement From falling edge to falling edge Falling edges 0 1 From rising edge to rising edge Rising edges 1 0 width measurement From falling edge to rising edge and vice versa Falling and rising edges 2 Timer Bj overflow flag A timer Bj interrupt request occurs when a measurement pulse s valid edge is input or a counter overflow occurs The timer Bj overflow flag is used to identify the cause of the interrupt request that is whether it is an overflow occurrence or a valid edge input The timer Bj overflow flag is set to 1 by an overflow Accordingly the cause of the interrupt request occurrence is identified by checking the timer Bj overflow flag in the interrupt routine When a value is written to the timer Bj mode register with the count start bit 1 the timer Bj overflow flag is cleared to 0 at the next count timing of the count source The timer Bj overflow flag is a read only bit Use the timer Bi interrupt request bit to detect the overflow timing Do not use the timer Bi overflow flag for this detection Figure 9 5 3 shows the operation during p
426. or overflow occurs the reload register s contents are reloaded into the counter A value is set to the counter and reload register by writing the value to the timer Ai register Table 8 2 1 lists the memory assignment of the timer register The value written into the timer Ai register while counting is not in progress is set to the counter and reload register The value written into the timer Ai register while counting is in progress is set only to the reload register In this case the reload register s updated contents are transferred to the counter at the next reload time The value obtained when reading out the timer Ai register varies according to the operating mode Table 8 2 2 lists reading from and writing to the timer Ai register Table 8 2 1 Memory assignment of timer Ai register Timer Ai register Timer AO register Timer A1 register Timer A2 register High order byte Low order byte Address 4716 Address 4616 Address 491 Address 48 Address 48 Address 4 Timer register Address 401 Address 4C e Timer A4 register Address 4F e Address 4E16 Note At reset the contents of the timer Ai register are undefined Table 8 2 2 Reading from and writing to timer Ai register Operating mode Read Write Timer mode Counter value is read out While counting Event counter mod Note 1 Written only to reload register lt While not counting gt Written to both of the counter and reload register
427. ormed Reading the low order byte of the UARTi receive buffer register out Clearing the receive enable bit bit 2 to 0 Clearing the serial mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 4 transmit register and UARTi transmit buffer register Figure 11 2 5 shows the block diagram for the transmitter Figure 11 2 6 shows the structure of UARTi transmit buffer register Data bus odd Data bus even D7 iDei Ds Da i Ds i De Di Do BUTS RUE SP Stop bit PAR Parity bit 8 bit UART 9 bit UART Parity SDU Clock sync enabled UART 2S seis oepa SoS HHHHAHJ O TxDi Parity Clock sync 7 bit UART bi disabled 8 bit UART UARTI transmit register Clock sync UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3B1e 16 Transmit data is set 15 to 9 Nothing is assigned Note Use the LDM or STA instruction for writing to this register Fig 11 2 6 Structure of UARTi transmit buffer register 7721 Group User s Manual 11 9 SERIAL I O 11 2 Block description Transmit data is set into the UARTi transmit buffer register Set the transmit data into the low order byte of this register when the microcomputer operates in the clock synchronous serial I O mode o
428. ory connection Table 16 1 5 Calculation formula and value for each parameter in Figure 16 1 7 unit ns Calculation formula and Value twEL 4 X 10 f Xin ER tie AA 80 to 115 ta E DLa 35 ta E DHa th E DLa 1 X 10 th E DHa f Xin age Note When accessing DRAM Wait is always inserted regardless of the contents of the Wait bit source s Wait bit and destination s Wait bit 8 E 5 c a 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MHz External clock input frequency f XIN Fig 16 1 8 Relationship between tox and f Xin 7721 Group User s Manual 16 11 APPLICATION 16 1 Memory connection 3 16 12 Precautions on memory connection As described in to below if specifications of the external memory do not match those of the M37721 some considerations must be incorporated into circuit design When using an external memory that requires a long access time When data is output from an external memory before falling edge of the E signal When using an external memory that outputs data for more than tpz E p ziouz after rising edge of the E signal When using external memory that requires long access time If the M37721 s cannot be satisfied because the external memory requires a long access time try to carry out the following Lower f
429. ote When the memory is the internal memory or SFR the above case for external data bus width 16 bits applies 7721 Group User s Manual 13 43 DMA CONTROLLER 13 4 Operation Table 13 4 7 Outputs of address bus data bus and bus control signals in 1 bus cycle transfer Output of address bus data bus and bus control signals Transfer Read Write Transferred from memory to Transferred from I O to memory ata bus address of width connection unit memory E R W L Transf Odd address inati EET SD ES Data bus Even Transfer source V Even address i 16 bits Do D7 16 bits address a ced Toan a and ane BHE 08 015 Odd address L L BLE L L As Ds A15 D15 Invalid data ur add Invalid data Transfer source V Even address Transfer destination 9 jl address BHE BLE L 16 bits Data bus Do D7 Aa Ds A15 D15 us due mi e data Transfer source _ gt Odd A16 Do A23 D7 address Odd address dat Cae address BHE H H BLE Transfer source Transfer destination N _________ pert CE cow E A16 Do A23 D7 2 a data H address BHE BLE Data bus L L 16 bits Ds D15 8bis uel As De Ats Dis assess Odd Aie Do Aes Dz source Invalid data Tranter destination X Inva
430. out Clearing the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 Bit 7 is cleared to 0 when all of bits 4 to 6 become 0 2 Bits 5 to 7 are invalid in the clock synchronous serial I O mode Fig 11 2 4 Structure of UARTi transmit receive control register 1 7721 Group User s Manual 11 7 SERIAL I O 11 2 Block description 1 2 3 4 Transmit enable bit bit 0 By setting this bit to 1 UARTi enters the transmission enable state By clearing this bit to 0 during transmission UARTi enters the transmission disable state after the transmission which is in progress at that time is completed Transmit buffer empty flag bit 1 This flag is set to 1 when data set in the UARTi transmit buffer register is transferred from the UARTi transmit buffer register to the UARTi transmit register This flag is cleared to 0 when data is set in the UARTi transmit buffer register Receive enable bit bit 2 By setting this bit to 1 UARTi enters the reception enable state By clearing this bit to 0 during reception UARTi quits the reception immediately and enters the reception disable state Receive complete flag bit 3 This flag is set to 1 when data is ready in the UARTi receive register and that is transferred to the UARTIi receive buffer register i e when reception is completed This flag is cleared to 0 when one of the following is perf
431. p mode refer to section 5 3 Stop mode For details about clocks refer to CHAPTER 5 CLOCK GENERATING CIRCUIT Powered on here x 4 5V Fig 4 1 11 Power on reset conditions 1 M51957AL Vcc Delay capacity GND The delay time is about 11 ms when 0 033 taz 0 34 X us Ca pF Fig 4 1 12 Example of power on reset circuit 4 12 7721 Group User s Manual RESET 4 2 Software reset 4 2 Software reset When the power source voltage satisfies the microcomputer s recommended operating conditions the microcomputer is reset by writing 1 to the software reset bit bit at address 5E16 This is called Software reset In this case the microcomputer initializes pins CPU and SFR area just as in the case of a hardware reset However the microcomputer retains the contents of the internal RAM area Refer to Table 4 1 1 and Figures 4 1 3 to 4 1 9 Figure 4 2 1 shows the structure of the processor mode register 0 address 5 After completing initialization the microcomputer performs internal processing sequence after reset Refer to Figure 4 1 10 After that it executes a program beginning from the address set into the reset vector addresses FFFE e and FFFFie 67 06 b5 04 63 62 bi bO 7773 Fix this bit to 0 EXEJ Nothing is assigned 1 Interrupt priority detection 7 cycles of DE
432. pagation delay time is within 7 5 ns Memory map 000000 000080 00047F 001FCO 001FFF E R W A16 Do 17 01 A18 D2 A19 D3 A20 D4 A21 D5 22 06 A10 D10 11 011 A12 D12 A13 D13 A14 D14 15 015 Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00102 Fig 16 1 26 Example of M5M418160CJ 1M X 16 bits connection external bus width 16 bits 16 30 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt tw EL 135 min tw RASL 120 min 60 min gt td RAS CAS 28 td E RASL 30 max td E CASL 77 5 max tw CASL 92 5 min td RA RAS 5 min td CA CAS 5 Row address Column address tOEA 20 35 max tRAC 70 max td E CA 60 max tpzx E DLZ DHZ 20 min 16 00 23 07 A8 D8 A15 D15 tCLZ 5 min AC157 tPHL Sao et tsu DL DH E gt BLE BHE E 20 min 20 gt 10 2 0 15 AC157 tPHL lt When writing gt E tw EL 135 min tw RASL 120 min lt gt tw CASL 55 tw RASH 60 min gt td E CASL 80 115 td R W E 20 min AC32 tPHL AC32 tPHL twcs 0 min tWCH 10 min gt lt td RA RAS 5
433. phase pulse signal processing function 8 28 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 One shot pulse mode In this mode the timer outputs a pulse which has an arbitrary width once Refer to Table 8 5 1 Timers A2 to 4 can be used in this mode When a trigger occurs the timer outputs level from the TAjour pin for an arbitrary time Figure 8 5 1 shows the structures of the timer Aj mode register and timer Aj register in the one shot pulse mode Table 8 5 1 Specifications of one shot pulse mode Item Count source Count operation Specifications f2 f16 164 or 1512 Countdown When the counter value becomes 000016 reload register s con tents are reloaded and counting stops a trigger occurs during counting reload register s contents reloaded and counting continues Output pulse width H put p H ra S n Timer Aj registers set value Count start condition When a trigger occurs Note Internal or external trigger can be selected by software When the counter value becomes 000016 When the count start bit is cleared to 0 When counting stops Programmable port or trigger input One shot pulse output An undefined value is read out While counting is stopped Count stop condition Interrupt request occurrence timing pin s function TAjour pin s function Read from timer Aj
434. pin for the A D converter Connect AVss AVcc to Vcc pin Connect AVss to Vss pin VREF Reference voltage input Input This is a reference voltage input pin for the A D converter 7721 Group User s Manual DESCRIPTION 1 3 Pin description Table 1 3 2 Pin description 2 Pin Name Input Output Functions Address low order Output Low order 8 bits of the address are output A7 MAz DRAM address When the DRAM is accessed the row and column addresses are output with the time sharing As Ds Address middle order I O External data bus width 8 bits When the BYTE 5 015 data high order pin is H level Middle order 8 bits As A s of the address are output External data bus width 16 bits When the BYTE pin is L level Data Ds D15 input output and output of the middle order 8 bits As A s of the address are performed with the time sharing A e Do Address high order I O Data Do D7 input output and output of the high order data low order 8 bits Aise Azs of the address are performed with the time sharing R W Memory control signal Output eR w BHE output The Read Write signal indicates the data bus state BLE The state is read while this signal is H level and ALE write while this signal is L level eBHE L level is output when an odd numbered address is accessed eBLE L level is output when an even numbered address is ac
435. pling in a transfer state refer to section 13 2 1 Bus access control circuit 7721 Group User s Manual 13 75 DMA CONTROLLER 13 7 Array chain transfer mode On and after First of 1 block second lt Transfer parameter Note Transfer source s transfer start address DARi lt Transfer parameter Note Transfer destination s transfer start address TCRi lt Transfer parameter Byte number of transfer data TCRi latch TCRi latch 1 request bit lt 0 Only in cycle steal transfer mode 1 unit transfer Burst Edge Refer to section 13 4 Operation Burst Level L Cycle steal Requested Transfer completion of 1 block Burst Edge Burst Level L Cycle steal Requested request bit 2 Transfer completion of all blocks latch 0 0 Burst Level H Cycle steal No request Y Completion output Note request bit 2 interrupt request bit lt 1 enable bit lt 0 0 Note When TC pin validity bit is 1 Burst Level H Cycle steal No request request bit lt 0 Only in burst transfer mode edge sense Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREQi pin L Burst Level H In burst transfer mode level sense with DMAREQi pin H Cycle steal Requested In cycle steal transfer mode with any request of DMA0 3 Cycle steal No request In cycle steal transfer
436. present in transmit buffer register 1 No data present in transmit buffer register C Writing of next transmit data is possible Note This figure shows the bits and registers required for processing Refer to Figures 11 4 6 to 11 4 8 for the change of flag state and the occurrence timing of an interrupt request f Writing of next transmit data UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3816 3A16 b15 b8 b7 50 Set transmit data here Fig 11 4 4 Writing data after start of transmission 11 36 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode When not using interrupts Checking start of transmission UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 50 Interrupt request bit 0 No interrupt requested 1 Interrupt requested Transmission has started Checking completion of transmission UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 50 Transmit register empty flag 0 During transmission V 1 Transmission completed Processing at completion of transmission Fig 11 4 5 Detection of transmit completion 7721 Group User s Manual When using interrupts UARTI transmit interrupt request occ
437. processing is selected m Input signal to 400 pin Input signal to TA4IN pin Up count H level Rising edge L level Falling edge Rising edge L level Falling edge H level Down count H level Falling edge L level Rising edge Rising edge H level Falling edge L level 7721 Group User s Manual 8 27 TIMER A 8 4 Event counter mode Precautions for event counter mode 1 While counting is in progress by reading the timer Aj register the counter value can be read out at any timing However if the timer Aj register is read at the reload timing shown in Figure 8 4 9 the value FFFF e at an underflow 00004 at an overflow is read out If reading is performed in the period from when a value is set into the timer Aj register with the counter stopped until the counter starts counting the set value is correctly read out 1 For countdown 2 For countup Reload Reload Ce LENS Read val Read val Me 2 1 rr n 1 ee FFFD FFFE FFFF 0000 Time Time n Reload register s contents n Reload register s contents Fig 8 4 9 Reading timer Aj register 2 The TAjour pin is used for all functions listed below Accordingly only one of these functions can be selected for each timer Switching between countup and countdown by TAjour pin s input signal Pulse output function Two
438. provided in Q amp A format In Q amp A as a rule one question and its answer are summarized within one page The upper box on each page is a question and a box below the question is its answer If a question or an answer extends to two or more pages there is a page number at the lower right corner At the upper right corner of each page the main function related to the contents of description in that page is listed 7721 Group User s Manual 17 65 APPENDIX Appendix 9 7721 Group Q amp A SFR Is there any SFR to which a certain instruction cannot be used for writing 1 Use the LDM or STA instruction to write to the registers or the bits listed below Do not use read modify write instructions i e CLB SEB ASL ASR DEC INC LSR ROL and ROR Pulse output data register 0 1 addresses 1A e 1 UARTO 1 baud rate register addresses 3116 39 6 UARTO 1 transmit buffer register addresses 3316 3216 3Bis Timer A2 A4 two phase pulse signal processing select bit bits 5 7 at address 44 6 Timer 2 4 register addresses 4A e 4F e one shot pulse mode or pulse width modulation mode Refresh timer address 66 6 Use the SEB or CLB instruction to write to the following register DMAC control register H address 6916 when any of bits 4 to 7 1 17 66 7721 Group User s Manual APPENDIX Appendix 9 7721 GroupQ amp A Reset STP instruction WIT instruction Is it possible to d
439. pt request is accepted or cleared by software The above timing diagram applies when hs the following conditions are satisfied TENDi Next transmit conditions are examined when this signal level is Parity disabled TENDi is an internal signal Accordingly it cannot be read from the external 2 stop bits CTS function disabled Tc 16 n 1 fi or 16 n 1 fexr fi BRGi count source frequency f2 116 164 1512 BRGi count source frequency external clock n Value set in BRGi Fig 11 4 8 Example of transmit timing when transfer data length 9 bits when parity disabled selecting 2 stop bits not selecting CTS function 11 40 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 5 Method of reception Figure 11 4 9 shows an initial setting example for relevant registers when receiving Reception is started when all of the following conditions and are satisfied Reception is enabled receive enable bit 1 The start bit is detected By connecting the RTSi pin receiver side and pin transmitter side the timing of transmission and that of reception can be matched For details refer to section 11 4 6 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 4 10 shows processing after receive completio
440. pts set these bits to level 0 Continue to Figure 8 5 3 Fig 8 5 2 Initial setting example for registers relevant to one shot pulse mode 1 7721 Group User s Manual 8 31 TIMER A 8 5 One shot pulse mode From preceding Figure 8 5 2 When external trigger is selected When internal trigger is selected Setting port P5 direction register Setting count start bit to 1 b7 50 b7 Port P5 directi eo register Count start register Address 4016 TA2IN pin Timer A2 count start bit pin Timer A3 count start bit 4 pin Timer A4 count start bit Set the corresponding bit to 0 iem count start bit to 1 N Setting one shot start bit to 1 b7 50 Count start register Address 4016 PA start register Address Timer A2 count start bit Timer A2 one shot start bit Timer A3 count start bit Timer A3 one shot start bit Timer A4 count start bit Timer A4 one shot start bit b7 50 Trigger input to pin Trigger generated Count starts Fig 8 5 3 Initial setting example for registers relevant to one shot pulse mode 2 8 32 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 2 Count source In the one shot pulse mode the count source select bits bits 6 and 7 at addresses 5816 to 5A e select the count source Table 8 5 2 lists the count source frequency Table 8 5 2 Count source frequenc
441. quest Supply of ceu and starts after a certain time measured by after terminating occurrence Watchdog timer has passed Stop mode By hardware reset Operates in the same way as hardware reset Note DRAM refresh is not performed because the refresh timer also stops 7721 Group User s Manual 5 5 CLOCK GENERATING CIRCUIT 5 3 Stop mode 1 Termination by interrupt request occurrence When terminating Stop mode by interrupt request occurrence instructions are executed after a certain time measured by the watchdog timer has passed When an interrupt request occurs the oscillator starts oscillating Simultaneously supply of clock fsi2 starts The watchdog timer starts counting owing to the oscillation start The watchdog timer counts fee regardless of the watchdog timer frequency select bit s bit 0 at address 6116 contents When the watchdog timer s becomes 0 supply of ceu and 6 starts At the same time the watchdog timer s count source returns to fs or fs12 that is selected by the watchdog timer frequency select bit The interrupt request which occurred in is accepted Table 5 3 2 lists the interrupts used to terminate Stop mode Table 5 3 2 Interrupts used to terminate Stop mode INTi interrupt i 0 to 2 Interrupt Conditions for using each function to generate interrupt request Timer Ai interrupt i 2 2 to 4 In event counter mode Timer Bi interrupt i 2 O 1
442. r register fi Frequency of count source fe fie fea or fs12 When an arbitrary value is set to the timer Aj register after setting 000016 to it the timing at which the PWM pulse goes H depends on the timing at which the new value is set Note The above applies when an external trigger rising edge of TAjin pin s input signal is selected Fig 8 6 5 Operation example of 16 bit pulse width modulator when counter value is updated during pulse output 8 44 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode 1 X m 1 X 28 1 i e i TAjin pin s input signal 8 bit prescaler s underflow signal PWM pulse output from TAjout pin Timer Aj interrupt request bit fi Frequency of count source fos tie fea oF Cleared to 0 when interrupt request is accepted or cleared by software The 8 bit prescaler counts the count source Q The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note The above applies when the reload register s high order 8 bits 0216 and low order 8 bits m 0216 and an external trigger falling edge of pin input signal is selected Fig 8 6 6 Operation example of 8 bit pulse width modulator 7721 Group User s Manual 8 45 TIMER A pejoejes si 1ndui s uid jo 16661 ue uaym Saljdde y 9
443. r B B Index register X X Index register Y Y Stack pointer S Data bank register DT Program bank register PG 0016 b15 68 b7 Program counter Contents at address FFFF16 Contents at address FFFE16 b15 b8 b7 Direct page register DPR 0016 0016 b15 68 b7 50 Processor status register PS 0 olo 0 910 012 2 0 0 011 2 IPL N Vm x D I Fig 4 1 3 State of CPU registers immediately after reset 4 4 7721 Group User s Manual RESET 4 1 Hardware reset e SFR area 016 to 7F16 1 016 to 1FFF16 Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset Always 0 at reading 1 1 immediately after reset Always 1 at readin 2 Underfined immediately after 9 reset Always undefined at reading 0 immediately after reset Fix this bit to 0 Address Register name Access characteristics State immediately after reset b7 50 57 60 016 116 216 316 416 516 616
444. r data format Refer to Figure 11 2 2 Set the same transfer data format for both transmitter and receiver sides Figure 11 4 2 shows an example of transfer data format Table 11 4 5 lists each bit in transmit data Transfer data length of 7 bits 1ST 7DATA 1SP 1ST 7DATA 25 1ST 7DATA 1PAR 1SP 1ST 7DATA 1PAR 2SP Transfer data length of 8 bits 1ST 8DATA 15 1ST 8DATA 25 1ST 8DATA 1PAR 1SP 1ST 8DATA 1PAR 2SP Transfer data length of 9 bits 1ST 9DATA 15 1ST 9DATA 2SP ST Start bit 1ST 9DATA 1PAR 1SP DATA Character bit Transfer data 1ST 9DATA 1 PAR 2SP PAR Parity bit SP Stop bit Fig 11 4 1 Transfer data format For the case where 18T 8DATA 1PAR 1SP Time Transmit Receive data gt Next transmit receive data 8 bits When continuously i i transferring ___ 58 ____ Fig 11 4 2 Example of transfer data format Table 11 4 5 Each bit in transmit data Name Functions ST L signal equivalent to 1 character bit which is added immediately before the Start bit character bits It indicates start of data transmission DATA Transmit data which is set in the UARTi transmit buffer register Character bit PAR A signal that is added immediately after the character bits in or
445. r mode The remaining data can be transferred by the following procedure Read the values at addresses of SARI and TCRi Then rewrite these values into these addresses Q Set the DMAi enable bit to 1 In repeat transfer array chain transfer and link array chain transfer modes The remaining data of the block that was interrupted by forced termination can be transferred by the following procedure Switch over the current mode to the single transfer mode Read the values at addresses of SARI DARi and TCRi Then rewrite these values into these addresses Set the enable bit to 1 Refer to Figure 13 3 4 c In order to transfer the next block switch over the current mode to the previous mode after the above mentioned transfer is normally terminated Then re set the values of SARi DARi and TCRi In the array chain or the link array chain transfer mode information such as the next transfer parameters etc cannot be read from each latch 7721 Group User s Manual DMA CONTROLLER 13 3 Control a State at forced termination Latch Previously written values Register Addresses which were to be transferred subsequently or the number of remaining bytes b When setting DMAi enable bit to 1 without rewriting values at addresses of SARi DARi and TCRi A value read from each latch is used by hardware only at the first 1 unit transfer The contents updated by the increme
446. r when a 7 bit or 8 bit length of transfer data is selected in the UART mode When a 9 bit length of transfer data is selected in the UART mode set the transmit data into the UARTi transmit buffer register as follows Bit 8 of the transmit data into bit 0 of high order byte of this register Bits 7 to 0 of the transmit data into the low order byte of this register The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register when the transmission conditions are satisfied and then it is output from the TxDi pin synchronously with the transfer clock The UARTi transmit buffer register becomes empty when the data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register Accordingly the user can set the next transmit data When quitting the transmission which is in progress and setting the UARTi transmit buffer register again follow the procedure described bellow Clear the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 Serial I O disabled Set the serial I O mode select bits again Set the transmit enable bit bit 0 at addresses 3516 30 6 to 1 transmission enabled and set transmit data the UARTi transmit buffer register 11 10 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 5 UARTi receive register and UARTi receive buffer register Figure 11 2 7 shows the block diag
447. racteristics When DMA transfer is forcedly completed by TC input input timing 17 102 1 m TC input STO DMAACKi output As Ds A15 D15 output BYTE L As Ds A15 D15 output BYTE A16 Do A23 D7 output ALE output R W output Destination address Source Destination address address Edi TAE DES X ye CX com uem th E AM lt lt Source address td AM E Destination address td AH E gt lt Source Dg address X tw ALE le td ALE E gt lt th ALE AM Destination address stination address th ALE AH Address ta R W E th E R W Test conditions Vcc 5V 10 Output timing voltage 0 8 V 2 0 V Do Dt5 input TC input Vit 0 0 8 V 2 5 8 V 2 5 V 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Table 3 Calculation formulas for internal peripheral devices input output timing depending on f Xw Vcc 5 V 10 Vss 0 V Ta 20 to 85 C Timer A input Gating input in timer mode Symbol Calculation formula Unit tc TA 8 10 ns f Xin tw TAH 4 X 10 ns f Xin tw TAL 4 X 10 ns Timer input External trigger input in one shot pulse mode Calculation formula Symbol to TA 4 10 Unit ns
448. ram for the receiver Figure 11 2 8 shows the structure of UARTi receive buffer register Data bus odd Data bus even UARTI receive D7 De buffer register SP Stop bit 8 bit UART PAR Parity bit park 9 bit UART 658 9 bit UART Clock sync Socr ro Parit disabled 7 bit UART 7 bit UART 8 bit UART Clock sync UARTi receive register UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F16 3E16 8 to 0 Receive data is read out from here unaenea RO 15 to 9 Nothing is assigned The value is 0 at reading Fig 11 2 8 Structure of UARTi receive buffer register 7721 Group User s Manual 11 11 SERIAL I O 11 2 Block description The receive register is used to convert serial data which is input to the RxDi pin into parallel data This register takes in the signal input to the RxDi pin in a unit of 1 bit synchronously with the transfer clock The UARTi receive buffer register is used to read out receive data When reception is completed the receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register Note that the contents of the UARTi receive buffer register is updated when the next data is ready in the UARTi receive register before the data which has been transferred to the
449. ransfer destination address direction backward start address of data even without Wait O 0 0 2 14 3 4 3 1 12 cycles 7721 Group User s Manual 13 99 DMA CONTROLLER 13 9 DMA transfer time 3 Transfer of array state In the following cases the processing in an array state and the first 1 unit transfer are performed sequentially Refer to Figures 13 8 10 and 13 8 11 Array chain transfer mode the first transfer of each block Link array chain transfer mode the first transfer of each block Right to use bus GN DMAC cu Transition Array state Transfer Transition Fig 13 9 3 Transfer of array state Transition of the right to use bus from CPU to DMAC 1 cycle Array state The number of transfer parameters x the number of reads of a transfer parameter x the number of bus cycles for a read 1 cycle Refer to Table 13 9 1 DMA transfer per 1 unit transfer In 2 bus cycle transfer Read cycle Write cycle Add a value which satisfies the read write conditions Refer to Table 13 4 1 e n 1 bus cycle transfer Refer to Table 13 4 5 Transition of the right to use bus from DMAC to CPU 1 cycle Example Link array chain transfer mode external data bus width 16 bits 2 bus cycle transfer transfer unit 216 bits and under the following conditions Transfer source address direction forward start address of data even with Wait Transfer
450. rce DMA source Source except software When selecting software DMA request Interrupt request of each peripheral DMAC control register H Address 6916 function occurs Inputting DMA request 60 signal to DMAREQi pin Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit Software request bit When writing 1 DMA request is generated 90 DMA transfer starts Fig 13 8 5 Initial setting example for registers relevant to link array chain transfer mode 3 13 86 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 3 Operation in link array chain transfer mode Figure 13 8 6 shows the operation flowchart of the link array chain transfer mode and Figures 13 8 7 and 13 8 8 show timing diagrams of the link array chain transfer mode burst transfer mode In addition Figure 13 8 9 shows the conditions necessary for timings shown in Figures 13 8 7 13 8 8 and 13 8 10 through 13 8 14 For the cycle steal transfer mode refer to the following Transfer of transfer parameters in an array state Figures 13 8 10 and 13 8 11 All transfers except for that in an array state and except for the last 1 unit transfer of each block Figure 13 8 12 Last 1 unit transfer of each block except for the last block Figure 13 8 13 Last 1 unit transfer of the last block Figure 13 8 14 The processing performed in the
451. rd start address of data even without Wait OC O9 1 3 4 1 9 cycles 13 98 7721 Group User s Manual DMA CONTROLLER 13 9 DMA transfer time 2 Last transfer of each block In the following cases 1 unit transfer and the processing for 3 cycles are performed sequentially Refer to Figures 13 8 13 and 13 8 14 Single transfer mode the last 1 unit transfer Repeat transfer mode the last 1 unit transfer of a block Array chain transfer mode the last 1 unit transfer of each block including the last block Link array chain transfer mode the last 1 unit transfer of each block including the last block Ore DMAC Transition Transfer Terminationy ansition bd p a c 1 1 Fig 13 9 2 Last transfer of each block Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per 1 unit transfer e In 2 bus cycle cycle Write cycle Add a value which satisfies the read write conditions Refer to Table 13 4 1 n 1 bus cycle transfer Refer to Table 13 4 5 Terminate processing or the last processing of each block cycles Transition of the right to use bus from DMAC to CPU 1 cycle Example 2 bus cycle transfer transfer unit 16 bits external data bus width 16 bits and under the following conditions Transfer source address direction forward start address of data even with Wait T
452. re 11 2 13 shows the relationship between the port direction register and UARTi s I O pins For details refer to the description of each operating mode 67 66 b5 64 63 b2 bi Port P8 direction register Address 1416 1 Output mode 1 When using pins P82 and P8e as 5 RESETR s imo Fig 11 2 13 Relationship between port P8 direction register and UARTi s I O pins 7721 Group User s Manual 11 15 SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 Clock synchronous serial mode Table 11 3 1 lists the performance overview in the clock synchronous serial I O mode and Table 11 3 2 lists the functions of I O pins in this mode Table 11 3 1 Performance overview in clock synchronous serial I O mode Item Functions Transfer data format Transfer data has a length of 8 bits LSB first BRGi s output divided by 2 Maximum 5 Mbps CTS function or RTS function can be selected by software Transfer rate When selecting internal clock When selecting external clock Transmit Receive control Table 11 3 2 Functions of I O pins in clock synchronous serial I O mode Pin name Method of selection TxDi P83 P87 Serial data output Note Dummy data is output when performing only reception RxDi P82 86 Serial data input Port P8 direction register s corresponding bit 0 be used as I O port when performing only transmission
453. receive mode register UARTO baud rate register BRGO UARTO transmit buffer register UARTO transmit receive control register 0 UARTO transmit receive control register 1 UARTO receive buffer register UART1 transmit receive mode register UART1 baud rate register BRG1 UART1 transmit buffer register UART1 transmit receive control register 0 UART1 transmit receive control register 1 UART1 receive buffer register Fig 2 4 2 SFR area s memory map 1 2 20 Address 00004016 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C16 00004D16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005 16 00005016 00005E16 00005 16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C16 00006D16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007 16 00007016 00007 16 00007 16 Count start register One shot start register Up down register Timer AO register Timer A1 register Timer A2 register Timer A3 register Timer 4 register Timer BO register Timer B1 register Timer B2 register Timer AO mode
454. required for the change depends on the contents of the interrupt priority detection time select bits bits 4 and 5 at address Table 7 11 1 lists the correspondence between the number of instructions inserted in Figure 7 11 1 and the interrupt priority detection time select bits LDM B 0XH 00XXH Write instruction for the interrupt priority level select bits NOP Inserted NOP instruction Note NOP 2 LDM B 0XH 00XXH Write instruction for the interrupt priority level select bits Note Except the write instruction for address XX16 any instruction which has the same cycles as the NOP instruction can also be inserted For the number of inserted NOP instructions refer to Table 7 11 1 XX any of 6C to 7F Fig 7 11 1 Program example to reserve time required for change of interrupt priority level Table 7 11 1 Correspondence between number of instructions to be inserted in Figure 7 11 1 and interrupt priority detection time select bits Interrupt priority detection time select bits Note Interrupt priority level Number of inserted b5 b4 detection time NOP instructions 0 0 7 cycles of 4 or more 0 1 4 cycles of 2 or more 1 0 2 cycles of 1 or more 1 1 Do not select Note We recommend b5 1 64 0 7 22 7721 Group User s Manual CHAPTER TIMER A 8 1 Overview 8 2 Block description 8 3 Timer mode Precautions for timer m
455. ressing mode the number of bytes increments by 1 3 The number of cycles increments by 2 when branching 4 The operation code on the upper row is used for branching in the range of 128 to 127 and the operation code on the lower row is used for branching in the range of 32768 to 32767 5 When handling 16 bit data with flag m 0 the byte in the table is incremented by 1 6 Type of register A B X Y DPR DT PG PS Number of cycles 2 2 2 2 2 1 1 2 The number of cycles corresponding to the register to be pushed are added The number of cycles when no pushing is done is 12 i1 indicates the number of registers among A B X Y DPR and PS to be saved while i2 indicates the number of registers among DT and PG to be saved 7 Type of register A B X Y DT PS Number of cycles 3 3 3 3 4 3 3 The number of cycles corresponding to the register to be pulled are added The number of cycles when no pulling is done is 14 i1 indicates the number of registers among A B X Y DT and PS to be restored while iz 1 when DPR is to be restored 8 The number of cycles is the case when the number of bytes to be transferred is even When the number of bytes to be transferred is odd the number is calculated as 7 2 7 4 Note that i 2 shows the integer part when i is divided by 2 9 The number of cycles is the case when the number of bytes to be transferred is even When the number of bytes to be transferred is odd
456. retained anywhere 6 The value FFF 16 is set to the watchdog timer Refer to CHAPTER 15 WATCHDOG TIMER 7 t is possible to read the bit state at reading When writing 0 to this bit this bit becomes 0 But when writing 1 to this bit this bit does not change 17 6 7721 Group User s Manual Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid wo The written value becomes valid It is impossible to read the bit state State immediately after reset 0 0 immediately after reset 0 1 1 immediately after reset Undefined immediately after reset Address 16 1FC116 1FC216 1FC316 1FC416 1FC516 1FC616 1FC716 1FC816 1FC916 16 16 16 1FCD16 1FCE16 1FCF16 1FD016 1FD116 1FD216 1FD316 1FD416 1FD516 1FD616 1FD716 1FD816 1FD916 1FDA16 1FDB16 1FDCi6 1FDD16 1FDE16 1FDF16 Register name Source address register 0 Destination address register 0 Transfer counter register 0 DMAO mode register L DMAO mode register DMAO control register Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register APPENDIX Appendix 2 Memory assignment in SFR area
457. rning O12 Forward At reverse turning 102 Backward Transfer destination address direction Fixed b7 50 1 1 DMA1 mode register H Address 1FDD 6 Transfer source Wait No transfer destination Wait Repeat transfer mode b23 b16b15 b8b7 50 Source address register 1 Addresses 1FD216 to 1FD016 Phase output data table s start address 023 016015 0807 Destination address register 1 Addresses 1FD616 to 1FD416 Pulse output data register 075 address b23 b16b15 b8b7 50 Transfer counter register 1 Addresses 1FDAte to 1FD816 L Phase output data table s data number b7 0 0 0 0 1 1 DMAt control register Address 1FDE e DMA request source Timer AO DMAACK 1 Invalid b7 50 0 interrupt control register Address 6016 Interrupt disabled X It may be O or 1 Fig 16 2 8 Initial setting example for relevant register 1 16 50 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller b7 bO 010 0 1 0 0 2 mode register L Address 1FEC16 Transfer unit 16 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction At slow up 012 Forward At slow down 102 Backward Transfer destination address direction Fixed b7 bO 0 0 1 0 0 x 0 DMA2 mode register H Address 1FED16
458. rom or output to the external is ordained on the basis of clock 2 Bus request Hold and bus request sampling are internal signals Fig 3 4 1 Timing of acceptance of Hold request and termination of Hold state 1 7721 Group User s Manual 3 13 CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function lt When inputting L level to HOLD pin while bus is used when data access is completed with 1 bus cycle gt State when inputting L level to HOLD pin External data bus Data length External data bus width 8 16 16 Access beginning at even address External address bus External data bus External address bus BLE BHE HOLD Bus request Hold Note 3 Bus request sampling Note 3 Hold state STO L Businuse Transfer of Transfer of right to use bus right to use bus When a Hold request is accepted not a new address but the address which was output immediately before is output again Notes 1 The above diagram shows the case of no Wait 2 Clock has the same polarity and the same frequency as Timing of signals to be input from or output to the external is ordained on the basis of clock 3 Bus request Hold and bus request sampling are internal signals Fig 3 4 2 Timing of acceptance of Hold request and termination of Hold state 2 3 14 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function When inputting
459. rrupt priority level IPL is set to 1112 Table 15 2 1 Occurrence interval of watchdog timer interrupt request Watchdog timer frequency select bit 0 1 f Xin 25 MHz Count source Occurrence interval 1512 41 94 ms 2 62 ms 15 4 7721 Group User s Manual WATCHDOG TIMER 15 2 Operation description Write dummy data to the watchdog timer register address 6016 before the most significant bit of Watchdog timer becomes 0 When Watchdog timer is used to detect a program runaway a watchdog timer interrupt request occurs if writing to address 6016 is not performed owing to a program runaway and the most significant bit of Watchdog timer becomes 0 This means that a program runaway has occurred In order to reset the microcomputer when a program runaway is detected write 1 to the software reset bit bit 3 at address 5E e in the watchdog timer interrupt routine Main routine Watchdog timer register a 8 bit dummy data Watchdog timer initialized Address 6016 Value of watchdog timer FFF16 Note 1 Watchdog timer interrupt request occur program runaway detected Watchdog timer interrupt routine Software reset bit 1 Note 2 Address 5 16 b3 Reset microcomputer Notes 1 Initialize Watchdog timer before the most significant bit of Watchdog timer becomes 0 Write dummy data to address 6016 before a watchdog timer interrupt request occurs 2 When a pro
460. rrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 9 4 3 shows an example of operation in the event counter mode n Reload register s contents Starts counting Stops counting 1 1 1 1 2 E 2 c i 5 Cleared to 0 i Set to 1 by software software Set to 1 by software Count start bit Timer Bj interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Fig 9 4 3 Example of operation in event counter mode 7721 Group User s Manual 9 17 TIMER B 9 4 Event counter mode Precautions for event counter mode While counting is in progress by reading the timer Bj register the counter value can be read out at any timing However if the timer Bj register is read at the reload timing shown in Figure 9 4 4 the value FFFF16 is read out If reading is performed in the period from when a value is set into the timer Bj register with the counter stopped until the counter starts counting the set value is correctly read out Reload up ye Read value 2 fern Time n Reload register s contents Fig 9 4 4 Reading timer Bj register 9 18 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 Pulse p
461. rrupt request is accepted The S s contents become S 5 after all of the above registers are pushed Fig 7 7 3 Push operation for registers 7721 Group User s Manual 7 15 INTERRUPTS 7 8 Return from interrupt routine 7 9 Multiple interrupts 7 8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine the contents of the program bank register PG program counter PC and processor status register PS which were pushed onto the stack area just before the INTACK sequence are automatically pulled After this the control returns to the original routine And then the suspended processing which was in progress before the acceptance of the interrupt request is resumed Before the RTI instruction is executed pull registers which were pushed by software in the interrupt routine using the PUL instruction etc 7 9 Multiple interrupts Just after a branch is made to an interrupt routine the following occur Interrupt disable flag 1 1 Interrupts are disabled Interrupt request bit of accepted interrupt 0 Processor interrupt priority level IPL Interrupt priority level of accepted interrupt Accordingly as long as the IPL remains unchanged an interrupt request whose priority level is higher than that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag 1 to 0 in an interrupt routine In this way mu
462. rupt request occurs by an input signal to the INTi i 0 to 2 pin The occurrence factor of the interrupt request can be selected by the level sense edge sense select bit and the polarity select bit bits 5 and 4 at addresses 7D e to 7F e shown in Figure 7 10 1 Table 7 10 1 lists the occurrence factor of INT interrupt request When using P10 INTo to P102 INT2 pins as input pins of external interrupts set the corresponding bits at address 18 port P10 direction register to 0 Refer to Figure 7 10 2 The signals input to the pin require or L level width of 250 ns or more independent of f Xin Additionally even when using the pins P10o INTo to P102 INT2 as the input pins of external interrupts the user can obtain the pin s state by reading bits O to 2 at address 16 e port P10 register Note When selecting an input signal s falling or L level as the occurrence factor of an interrupt request make sure that the input signal is held L for 250 ns or more When selecting an input signal s rising or level as that make sure that the input signal is held for 250 ns or more Table 7 10 1 Occurrence factor of INT interrupt request b5 b4 INTi interrupt request occurrence factor 0 0 Interrupt request occurs at the falling edge of a signal input to pin INT Edge sense 0 1 Interrupt request occurs at the rising edge of a signal input to pin INT Edge sense
463. s Signal required for access A generic name for bus control address bus and data bus signals Bus control to external device signal Stop mode A state where the oscillation circuit halts and the program execution Wait mode is stopped By executing the STP instruction the microcomputer enters the stop mode UART Clock asynchronous serial I O When used to designate the name Clock of a functional block this term also means the serial I O which synchronous be switched to the cock synchronous serial I O serial I O Underflow state where the countdown resultant is greater than the counter Overflow resolution Countdown Wait mode state where the oscillation circuit is operating however the Stop mode program execution is stopped By executing the WIT instruction the microcomputer enters the wait mode N 7721 Group User s Manual MITSUBISHI SEMICONDUCTORS USER S MANUAL 7721 Group Sep First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1997 MITSUBISHI ELECTRIC CORPORATION User s Manual 7721 Group RA MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE MITSUBISHI DENKI BLDG MARUNOUCHI TOKYO 100 TELEX J24532 CABLE MELCO TOKYO New public
464. s Bit configuration of real time output channel 4 bits X 2 channels or 6 bits X 1channel and 2 bits X channel 4 bits X 2 channels Port latch state after using real time output Real time output Retains the value before using real time output Undefined Limitation for instruction used when writing to interrupt control register Nothing LDM STA instructions can be used Exists LDM STA instructions cannot be used Timing when overrun error flag becomes 0 Serial I O One of the following When setting the receive enable bit to 0 When setting the serial I O mode select bits to 0002 One of the following When setting the receive enable bit to 0 When setting the serial I O mode select bits to 0002 When reading the receive buffer register mode Conditions for outputting L of RTS signal in clock synchronous serial I O When all of the following are satisfied Receive enable bit 1 Reception is stopped data is present in the transmit buffer register When all of the following are satisfied Receive enable bit 1 Reception is stopped DMA shortest transfer rate At 1 bus cycle transfer 12 5 Mbytes sec Note 512 bytes can be selected by software For the M37721S1BFP its 7721 Group User s Manual 8 Mbytes sec internal RAM size is 512 bytes 17 79 APPENDIX Appendix 11 Electrical
465. s When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Setting count start bit to 1 b7 50 Count start register Address 4016 Timer BO count start bit Timer B1 count start bit Timer B2 count start bit Count Starts Fig 9 3 2 Initial setting example for registers relevant to timer mode 9 10 7721 Group User s Manual TIMER B 9 3 Timer mode 9 3 2 Count source In the timer mode the count source select bits bits 6 and 7 at addresses 5816 to 5016 select the count source Table 9 3 2 lists the count source frequency Table 9 3 2 Count source frequency Count source Count Count source frequency select bits source b7 b6 f Xin 8 MHz f Xin 16 MHz f Xin 25 MHz 0 0 f2 4 MHz 8 MHz 12 5 MHz 0 1 fie 500 kHz 1 MHz 1 5625 MHz 1 0 fea 125 kHz 250 kHz 390 625 kHz 1 1 512 15625 Hz 31250 Hz 48 8281 kHz 7721 Group User s Manual TIMER B 9 3 Timer mode 9 3 3 Operation in timer mode When the count start bit is set to 1 the counter starts counting of the count source When a counter underflow occurs the reload registers contents are reloaded and counting continues The timer Bi interrupt request bit is set to 1 at the underflow The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bi
466. s etc For the basic functions of each I O pin refer to section 1 3 Pin description For the I O functions of the internal peripheral devices refer to relevant sections of each internal peripheral device For the external address bus external data bus bus control signals etc refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES This chapter describes the programmable I O ports and examples of handling unused pins 6 2 Programmable I O ports The programmable I O ports have direction registers and port registers in the SFR area Figure 6 2 1 shows the memory map of direction registers and port registers Addresses Fig 6 2 1 Memory of direction registers and port registers 6 2 7721 Group User s Manual INPUT OUTPUT PINS 6 2 Programmable ports 6 2 1 Direction register This register determines the I O direction of programmable ports Each bit of this register corresponds one for one to each pin of the microcomputer Figure 6 2 2 shows the structure of port Pi i 4 to 10 direction register 67 b6 05 64 63 b2 bi 00 Port Pi direction register i 4 to 10 Addresses C16 D16 1016 1116 1416 1516 1816 RES Port Pio direction bit 0 Input mode Rw Port Pi direction bit 1 Output mode Port Pie direction bit The port functions as an output port s Note For bits 0 to 2 of the port P4 direction register nothing is assigned an
467. s used to store the initial value of the counter When a counter underflow occurs the reload register s contents are reloaded into the counter A value is set to the counter and reload register by writing the value to the timer Bi register Table 9 2 1 lists the memory assignment of the timer Bi register The value written into the timer Bi register when the counting is not in progress is set to the counter and reload register The value written into the timer Bi register when the counting is in progress is set only to the reload register In this case the reload register s updated contents are transferred to the counter when the next underflow occurs The counter value is read out by reading out the timer Bi register Note When reading from or writing to the timer Bi register perform it in a unit of 16 bits For more information about the value obtained by reading the timer Bi register refer to Precautions for timer mode and Precautions for event counter mode Functions in pulse period pulse width measurement mode Countup in the counter is performed each time the count source is input The reload register is used to retain the pulse period or pulse width measurement result When a valid edge is input to the TBjin pin the counter value is transferred to the reload register In this mode the value obtained by reading the timer Bj register is the reload register s contents so that the measurement result is obtained Note When reading
468. s at both of falling and rising edges of external signal 1 1 Do not select X It may be 0 or 1 Setting division ratio b15 b8 b7 50 Timer BO register Addresses 5116 5016 Timer register Addresses 531 524 M Can be set to 000016 to FFFF e n Note The counter divides the count source by n 1 Setting interrupt priority level b7 bO Timer Bj interrupt control register j 0 1 Addresses 7 16 7B16 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Setting port P5 direction register b7 50 Port P5 direction register Address Die TBOw pin Clear the corresponding bit to 0 pin Setting count start bit to 1 b7 60 Count start register Address 4016 Count starts Timer BO count start bit Timer B1 count start bit Fig 9 4 2 Initial setting example for registers relevant to event counter mode 9 16 7721 Group User s Manual TIMER B 9 4 Event counter mode 9 4 2 Operation in event counter mode When the count start bit is set to 1 the counter starts counting of the count source s valid edges When a counter underflow occurs the reload register s contents are reloaded and counting continues The timer Bj interrupt request bit is set to 1 at the underflow The inte
469. s for DMAC Do not access the registers relevant to DMAC by using DMA transfers the address of the accessing register collides with that of the accessed one on the DMAC internal bus 13 18 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 Control The conditions for performing DMA transfer of DMAi i 0 3 are as follows Neither a DRAM refresh request nor a Hold request is generated request of the channel with a higher priority than that of DMAi is not generated or the request is disabled though it has been generated e is enabled enable bit 1 DMAi request is generated request bit 1 The control method for each channel is described below 13 3 1 DMA enabling Each of DMA channels 0 3 has a DMAi enable bit bits 4 7 at address 6916 Table 13 3 1 lists the conditions for changing each DMAi enable bit Table 13 3 1 Conditions for changing DMAi enable bit DMAi enable bit Conditions for bit change Is set to 1 A write of 1 to the DMAi enable bit Is cleared to 0 A write of 0 to the DMAi enable bit Transfer of an entire batch of data is complete normal termination change of TC input level from to 41 during a DMA transfer of DMAi Note Forced termination when TC pin is valid Note In the burst transfer mode level sense however the term from the DMA transfer start until the transfer completion o
470. s for bit 5 at addresses 5816 and 5 16 vary according to Timer B s operating mode Bit 5 at address 5016 is invalid Refer to CHAPTER 9 TIMER B 4 Bit 1 at address 5F16 becomes 0 immediately after reset For the M37721S1BFP fix this bit to 0 7721 Group User s Manual 17 5 APPENDIX Appendix 2 Memory assignment in SFR area Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset 0 Always 0 at reading 1 1 immediately after reset 1 di 2 Undefined immediately after Always k abreaging reset Always undefined at reading 0 immediately after reset Fix this bit to 0 Address Register name Access characteristics State immediately after reset b 6016 Watchdog timer register Note 5 Note 6 6116 Watchdog timer frequency select register RW 0 6216 Real time output control register RW 6316 2 6416 DRAM control register RW RW
471. s input signal Count source 50 Timer A2 register Addresses 4816 4A16 ________ signal s L level time T2 in Figure 16 2 2 015 58 07 A Timer A3 register Addresses 4016 4616 2 Period from falling edge of ACK signal until falling edge of BUSY signal T3 in Figure 16 2 2 Fig 16 2 4 Initial setting example for relevant register 2 16 46 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller b7 bo 1 0 0 0 0 1 DMAO control register Address 1 16 DMA request source External source DMAREQO Edge sense selected DMAACKO pin Valid b7 bo _ 0 DMAO interrupt control register Address 6 16 Interrupt priority level any of 0012 to 1112 b7 50 1 1 Count start register Address 4016 Timer A2 count start Timer A3 count start b7 bO Jof DMAC control register L Address 6816 DMAO request flag is set to 0 b7 bO DMAC control register H Address 6916 DMAO enabled b7 bO Jo Por P4 register Address P43 output L level Fig 16 2 5 Initial setting example for relevant register 3 7721 Group User s Manual 16 47 APPLICATION 16 2 Examples of using DMA controller 16 2 2 Example of stepping motor control The following is an example where the slow up or slow down control for the stepping motor is performed by using DMA1 DMA2 and RTPO
472. s latch for latching n bits of Ais to Azs are required 7721 Group User s Manual APPLICATION 16 1 Memory connection Table 16 1 1 Memory connection model External data Maximum 64 Kbytes Maximum 16 Mbytes bus width M37721 BYTE 8 bit width ATAR A16 Do A23 D7 BYTE H ALE 16 00 23 07 Memory connection model Minimum model Memory connection model M37721 M37721 BYTE 7 As Ds A15 D15 As Ds A15 D15 16 bit width Aie Do Azs Dz BYTE L BLE Memory connection model Medium model Memory connection model Maximum model Notes 1 Refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES for details about the functions and operations of used pins when connecting a memory Refer to section Appendix 11 Electrical characteristics for timing requirements 2 Because the address bus can be expanded up to 24 bits when connecting a memory strengthen the M37721 s Vss and Vcc lines on the system Refer to section Appendix 8 Countermeasure against noise 7721 Group User s Manual 16 3 APPLICATION 16 1 Memory connection 16 1 2 How to calculate timing Timings at which data is read or written when connecting a memory and precautions when connecting a memory are described below For timing requirements of the memory and detailed account except limits described below also refer to the memory s Data book
473. s serial I O ad T Do not select Do not select UART mode Transfer data length 7 bits UART mode Serial I O mode select bits Transfer data length 8 bits UART mode Transfer data length 9 bits Do not select Internal External clock select bit Internal clock External clock Stop bit length select bit d One stop bit Valid in UART mode Note Two stop bits Odd Even parity select bit 0 Odd parity RW Valid in UART mode when 1 Even parity parity enable bit is 1 Note Parity enable bit 0 Parity disabled RW Valid in UART mode Note 1 Parity enabled Sleep select bit 0 Sleep mode terminated Invalid RW Valid in UART mode Note 1 Sleep mode selected Note Bits 4 to 6 are invalid in the clock synchronous serial I O mode They may be either O or 1 Additionally fix bit 7 to 0 UARTIi baud rate register b7 50 UARTO baud rate register Address 3116 UART1 baud rate register Address 3916 Bit iem 7 to 0 Can be set 0016 to FF e Undefined WO Assuming that the set value n BRGi divides the count source frequency by n 1 Note Writing to this register must be performed while the transmission reception halts Use the LDM or STA instruction for writing to this register 7721 Group User s Manual 17 13 APPENDIX Appendix 3 Control registers UARTI transmit buffer register b15 b8 b7 b0 b7 b0 O 1 UART
474. s set to 1 at this time 2 There are two methods one uses external interrupt s level sense and the other uses the timer s event counter mode Method using external interrupt s level sense As for hardware input a logical sum of multiple interrupt signals e g a b and c to the pin and input each signal to each corresponding port As for software check the ports input levels in the INT interrupt routine in order to detect which signal a b or was input M37721 Method using timer s event counter mode As for hardware input interrupt signals to the pins or pins As for software set the timer s operating mode to the event counter mode Then set a value 000016 into the timer register and select the valid edge The timer s interrupt request occurs when an interrupt signal selected valid edge is input 7721 Group User s Manual 17 71 APPENDIX Appendix 9 7721 Group Q amp A Stack DRAM What are there the stack bank select bit bit 7 at address 5E e for It is supposed that DRAM is used as the stack area When connecting DRAM the stack pointer addressing mode or stack operation instruction etc can be used It is because all of 64 Kbytes can be used as the stack area when bank which is assigned to DRAM is set as the stack area The internal RAM also functions as the temporary area or the register file
475. s the contents of the memory into index register Y LSR Note 1 Shifts the contents of the accumulator or the contents of he memory one bit to the right The bit 0 of the accumu lator or the memory is entered into the C flag 0 is en ered into bit 15 bit 7 when the m flag is 1 MPY Notes 2 11 Multiplies the contents of accumulator A and the contents of the memory he higher order of the result of operation are entered into accumulator B and the lower order into accumulator A MVN Note 8 Mn i Mm i Transmits the data block The transmission is done from he lower order address of the block MVP Note 9 Transmits the data block Transmission is done form the higher order address of the data block NOP 1 Advances the program counter but pertorms nothing else ORA Notes 1 2 Acce AccVM Logical sum per bit of the contents of the accumulator and the contents of the memory is obtained The result is en tered into the accumulator 5 2 S lt S 1 M S IMM S lt S 1 The 3rd and the 2nd bytes of the instruction are saved into the stack in this order M S lt M DPR IMM 1 S lt S 1 M S lt M DPR IMM S lt S 1 Specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction and saves the contents into the stack EAR lt PC IMMa2 IMM1 M S lt EARuH
476. se these contents may be changed by noise a program runaway which occurs owing to noise etc 2 For unused pins use the shortest possible wiring within 20 mm from the microcomputer s pins 3 This applies when a clock externally generated is input to the Xin pin When setting ports to input mode When setting ports to output mode P43 P47 P5 P10 4 4 P5 P10 STO STO STi ST1 BLE BLE Left open BHE Left open ALE ALE 1 1 Xour Xour Left open Voc HOLD HOLD RDY RDY AVcc AVcc CNVss CNVss AVss AVss VREF VREF 77 Vss CNVss can be connected to Vcc too Fig 6 3 1 Examples of handling unused pins 7721 Group User s Manual 6 7 INPUT OUTPUT PINS 6 3 Examples of handling unused pins MEMORANDUM 6 8 7721 Group User s Manual CHAPTER 7 INTERRUPTS 7 1 Overview 7 2 Interrupt sources 7 3 Interrupt control 7 4 Interrupt priority level 7 5 Interrupt priority level detection circuit 7 6 Interrupt priority level detection time 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine 7 8 Return from interrupt routine 7 9 Multiple interrupts 7 10 External interrupts interrupt 7 11 Precautions for interrupts INTERRUPTS 7 1 Overview 7 1 Overview The M37721 provides 23 interrupt sources to generate interrupt requests Figure 7 1 1 shows the interrupt proces
477. select register address 116 A D sweep pin select bits b1 b0 0 0 ANo AN 2 pins Trigger select bit 0 1 ANo ANs 4 pins 0 Internal trigger 1 0 ANo ANs 6 pins 1 External trigger 1 1 ANo AN7 8 pins A D conversion start bit 0 Stop A D conversion Repeat sweep mode A D conversion frequency AD select bit 0 f2 divided by 4 1 divided by 2 d G Port P7 direction register b7 50 Port P7 direction register address 1116 ANo AN AN2 Set the bits corresponding AN3 to analog input pins to 0 AN4 Set bit 7 to 0 when ANs selecting external trigger AN7 gt A D conversion start bit to 1 57 50 aaa ee Ace a A D control register address 1E 6 A D conversion start bit When external trigger is selected When internal trigger is selected Input falling edge to ADrne pin A Trigger occur Operation start Note Writing to each bit except bit 6 of the A D control register and each bit of the A D sweep pin select register must be performed while the A D converter halts before a trigger occurs Fig 12 8 1 Initial setting example for registers relevant to repeat sweep mode 7721 Group User s Manual 12 25 A D CONVERTER 12 8 Repeat sweep mode 12 8 2 Repeat sweep mode operation description 1 2 When an internal trigger is se
478. sent in receive buffer register 1 Data present in receive buffer register 4 Overrun error flag Note 1 0 No overrun error 1 Overrun error detected 5 Framing error flag Notes 1 2 0 No framing error Valid in UART mode 1 Framing error detected Parity error flag Notes 1 2 0 No parity error Valid in UART mode 1 Parity error detected 7 Error sum flag Notes 1 2 0 No error Valid in UART mode 1 Error detected Notes 1 Bit 4 is cleared to 0 when the receive enable bit is cleared to 0 or when the serial mode select bits bits 2 to 0 at addresses 3016 3816 are cleared to 0002 Bits 5 and 6 are cleared to 0 when one of the following is performed Clearing the receive enable bit to 0 Reading the low order byte of the UARTi receive buffer register addresses 3616 3E16 out Clearing the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 Bit 7 is cleared to 0 when all of bits 4 to 6 become 0 2 Bits 5 to 7 are invalid in the clock synchronous serial I O mode UARTI receive buffer register b15 b8 b7 b0 07 UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F 16 3E16 Receive data is read out from here Undetnes RO d 15 to 9 Nothing is assigned The value is 0 at reading 7721 Group User s Manual 17 15 APPENDIX Appendix 3 Control registers Count start register
479. ses 1FF21e to 1FF016 Source address register 0 Source address register 1 Source address register 2 Source address register 3 Write Undefined RW Set the transfer start address of the source These bits can be set to 00000016 to FFFFFF1e Read The read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 015 b8 57 bO E cox 1 Destination address register 0 Destination address register 1 Destination address register 2 Destination address register 3 Addresses 1FC6 6 to 1FC416 Addresses 1FD61e to 1FD4 6 Addresses 1FE6 6e to 1FE416 Addresses 1 16 to 1FF4416 prp 23 to Write T Undefined RW Set the transfer start address of the destination These bits can be set to 00000016 to FFFFFFie Read The read value indicates the destination address of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 515 b8 b7 bO Addresses 1FCA16 to 1FC816 Addresses 1FDAte to 1FD8 6 Addresses 1 16 to 1FE816 Addresses 1 16 to 1FF816 Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 pump 23 to o Write Undefined RW Set the byte number of the transfer data These bits can be set to 00000116 to FFFFFF1e Read The read value indicates the remaini
480. set to the input mode the data is written only into the port latch and is not output to the external Note The pin remains floating Note When executing a read modify write instruction CLB SEB INC DEC ASL ASR LSR ROL ROR to the port register of a programmable I O port set to the input mode the instruction is executed to the data which is input from the pin and the result is written into the port register b7 06 65 04 63 b2 bi 60 Port Pi register i 410 10 Addresses Ate Bie E16 Fie 1216 1316 1616 Bit name Functions EN Port Pio s pin Data is input from or output to a pin by reading from or writing to the 1 PortPirs pin corresponding bit 1 H level na Port Pis s pin Undefi Port Pi2 s pin 0 L level Port Pie s pin Undefi Port Pi7 s pin Note For bits 0 to 2 of the port P4 register nothing is assigned and these bits are fixed to 0 at reading Fig 6 2 3 Structure of port Pi i 4 to 10 register 6 4 7721 Group User s Manual INPUT OUTPUT PINS 6 2 Programmable ports Figures 6 2 4 and 6 2 5 show the port peripheral circuits Inside dotted line not included Ports P4 to Pd Inside dotted line included Data bus Ports P47 5 2 n P53 TA3in P5s TA4in P5e TBOw P57 TB1n P82 RxDo P8e RxD1 P9 DMAREQO P93 DMAREQ1 P9s DMAREQ2 P97 DMAREQ3 P100 INTo P10 INT P102 INT2 There is no hysteresis for P82 RxDo and P8e RxD1
481. sfer mode 1 block of data is transferred repeatedly For details refer to section 13 6 Repeat transfer mode Array chain transfer mode Several blocks of data are transferred The transfer parameters transfer source and destination addresses the number of transfer bytes of each block must be located on the memory in series For details refer to section 13 7 Array chain transfer mode B Link array chain transfer mode Several blocks of data are transferred Transfer parameters for each block can be located on the memory in separate in a unit of 1 block s parameters For details refer to section 13 8 Link array chain transfer mode 7721 Group User s Manual 13 5 DMA CONTROLLER 13 2 Block description 13 2 Block description Figures 13 2 1 and 13 2 2 show the DMAC block diagrams and relevant registers are described below Address bus Incrementer Decrementer Source address register 0 SARO Destination address register 0 DARO 2 Destination address register 1 DAR1 Source address register 2 SAR2 Transfer counter register 2 TCR2 PX Source address register SAR3 Destination address register 3 DAR3 Transfer counter register 3 TCR3 _____ 7 Data bus Even Data bus Odd Microcomputer s internal bus _1 DMAC s internal bus ALZA 52 Fig 13 2 1 DMAC block diagram 1 BIU CPU wa
482. sferred TC pin validity bit Bit 1 at address 6816 Interrupt request generation timing Functions of registers 7721 Group User s Manual 13 61 DMA CONTROLLER 13 6 Repeat transfer mode b16 b15 b16 b15 b16 b15 Source address register 0 Addresses 1 216 to 1 016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1FE216 to 1FE016 SAR2 Source address register Addresses 1FF216e to 1FF0 e SAR3 Set the transfer start address of the source These bits be set to 00000016 to FFFFFF ie DARO DAR1 which is next transferred Note When writing to this register write to all 24 bits Destination address register 0 Addresses 1FC6 e to 1FC4 6 Destination address register 1 Addresses 1 616 to 1FD4 6 Destination address register 2 Addresses 1 16 to 1FE416 Destination address register Addresses 1FF616 to 1FF416 Read The read value indicates the source address of data DAR2 DAR3 23 to o Write Set the transfer start address of the destination These bits can be set to 00000016 to FFFFFF ie Read The read value indicates the destination address of data which is next transferred Transfer counter register 0 Addresses 1FCAte to 1 816 TCRO Transfer counter register 1 Addresses 1FDAte to 1FD8 6e TCR1 Transfer counter register 2 Addresses 1 to 1FE816 TCR2
483. sfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed the array chain transfer mode can be used external data bus width 16 bits or the internal memory is used The transfer start address on the address direction fixed side is an even address 7721 Group User s Manual 13 79 DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 Link array chain transfer mode This mode is used to transfer several blocks of data According to the information of each block stored in memory area Note several blocks of data are transferred Transfer parameters can be located in separate memory locations in a unit of one block s parameters Table 13 8 1 lists the specifications of the link array chain transfer mode and Figure 13 8 1 shows the register structures of SARi DARi and TCRi in this mode Note Each of the following information is called transfer parameter transfer start addresses of transfer source and destination and transfer data s byte number Table 13 8 1 Specifications of link array chain transfer mode Item Performance specifications Transfer parameter memory Required n 2 bus cycle transfer 16 bytes per one block transfer source s transfer start address transfer destination s transfer start address transfer data s byte number next transfer parameter memory s start address n 1 bus cycle transfer 12 bytes per one block from memory to I O
484. side the timing of transmission and that of reception can be matched For details refer to section 11 4 6 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 4 4 shows writing data after start of transmission and Figure 11 4 5 shows detection of transmit completion 11 34 7721 Group User s Manual N UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 UART mode 7 bits UART mode 8 bits UART mode 9 bits Internal External clock select bit 0 Internal clock 1 External clock Stop bit length select bit 0 1 stop bit 1 2 stop bits Odd Even parity select bit 0 Odd parity 1 Even parity Parity enable bit 0 Parity disabled 1 Parity enabled Sleep select bit 0 Sleep mode terminated Invalid 1 Sleep mode selected J fi UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 b7 bO BRG count source select bits b1 b0 0 0 12 0 1 fie 1 0 fea 1 1 512 CTS RTS select bit 0 CTS function selected ___ 1 RTS function selected CTS function disabled X 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode UARTO baud rate register BRGO Address 3116 UART1 baud rate re
485. signal becomes L level while writing data to the data bus Table 3 1 1 lists the state of the data bus indicated with the E and R W signals Table 3 1 1 State of data bus indicated with E and R W signals E R W State of data bus H H Not used L L H Read data L Write data 3 2 7721 Group User s Manual 3 1 Signals required for accessing external devices CONNECTION WITH EXTERNAL DEVICES gt RESETout RESET gt RESETout lt CNVss BYTE bus control signal bus control signal r3 B r3 5 z 5 2 External address bus external data bus External address bus external data bus gt 6 62 lt gt ttd lt gt Std 92 gt lt gt lt gt 0101 0014 lt gt HINI Old lt gt NI 20Ld lt gt O1 0ld lt gt SVO 0Ld 5 lt gt SVH S0Ld lt gt 8VIN 30Ld lt gt eVWN 0Ld 91 lt gt 1 L 0Sd lt gt L Gd lt gt LNOEW L 2Gd t lt gt 26 8 2 lt gt sq sty lt gt 8 81 lt gt lt gt lt gt 9 gt lt gt siq siy lt gt lt gt gv lt gt 0LNI 00 Ld ry lt gt gi g eiv lt gt LNI OLd ely lt gt 1NI 20Ld ziy lt gt ny 0
486. sing sequence When an interrupt request is accepted a branch is made to the start address of the interrupt routine set the interrupt vector table addresses to FFFF e Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table Fig 7 1 1 Interrupt processing sequence 7 2 7721 Group User s Manual INTERRUPTS 7 1 Overview When an interrupt request is accepted the following registers contents just before acceptance of an interrupt request are automatically pushed onto the stack area gt in that order Program bank register PG Program counter PC PC Processor status register PS 5 Figure 7 1 2 shows the state of the stack area just before entering the interrupt routine Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted By executing the RTI instruction the register contents pushed onto the stack area are pulled in that order Then the suspended processing 15 resumed from where it left off Stack area Address S 5 S 4 Processor status register s low order byte PSL S 3 Processor status register s high order byte PSH S 2 Program counter s low order byte PCL S 1 Program counter s high order byte PCH S Program bank regi
487. sing sequence after reset External bus width 16 bits BYTE L Ao A7 15 015 Next op code operand 00 23 07 Next op code E e External bus width 8 bits BYTE H Ao A7 ADL 15 AD A16 Do A23 D7 E Fig 4 1 10 Internal processing sequence after reset 7721 Group User s Manual 4 11 RESET 4 1 Hardware reset 4 1 4 Time supplying L level to RESET pin Time supplying L level to the RESET pin varies according to the state of the clock oscillation circuit When the oscillator is stably oscillating or a stable clock is input from the pin supply L level for 2 us or more When the oscillator is not stably oscillating including the case at power on reset or in Stop mode supply L level until the oscillation is stabilized The time required for stabilizing oscillation varies according to the oscillator For details contact the oscillator manufacturer Figure 4 1 11 shows the power on reset conditions Figure 4 1 12 shows an example of a power on reset circuit For details about Sto
488. ss bus XX16 Low order 8 bits of vector address Low order 8 bits of CPU internal address bus AD Contents of vector address High order address CPU internal data bus for odd address AD Contents of vector address Low order address CPU internal data bus for even address Fig 7 7 2 INTACK sequence timing at minimum 7 7 1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted the processor interrupt priority level IPL is replaced with the interrupt priority level of the accepted interrupt This results in easy control of the processing for multiple interrupts Refer to section 7 9 Multiple interrupts At reset or when a watchdog timer interrupt or a software interrupt is accepted a value listed in Table 7 7 1 is set into the IPL Table 7 7 1 Change in IPL at acceptance of interrupt request Interrupts Change in IPL Level 0 0002 is set Level 7 1112 is set Not changed Not changed Accepted interrupt priority level is set Reset Watchdog timer Zero division BRK instruction Other interrupts 7 14 7721 Group User s Manual INTERRUPTS 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine 7 7 2 Push operation for registers The push operation for registers performed in the INTACK sequence depends on whether the contents of the stack pointer S at acceptance of an interrupt request are even or odd When the co
489. ssed the bus cycle is always with wait the low level width of E is equivalent to 2 cycles of It is not affected by the wait bit the wait bit of the transfer source and the wait bit of the transfer destination 1 2 3 14 8 Read Cycle M In the read cycle the CAS signal falls with a delay of 0 5 cycle of after the RAS signal has changed from H to L The address bus signal changes from row address to column address within a period from a fall of RAS until a fall of CAS Pins A e Do Aos Dz As Ds Ais D1s5 output addresses and input data in the same way as in reading external devices other than DRAM Write Cycle m In the write cycle the CAS signal falls with a delay of 1 cycle of after the RAS signal has changed from H to L The address bus signal changes row address to column address within a period from a fall of RAS until a fall of CAS Pins A e Do Azs Dz and As De A s D ss output addresses and data in the same way as in writing external devices other than DRAM Refresh Cycle In the refresh cycle the RAS signal falls with a delay of 0 5 cycle of after the CAS signal has changed from H to L R W is undefined One refresh request requires 5 cycle of including the time for passing the right to use buses 7721 Group User s Manual DRAM CONTROLLER 14 4 DRAMC operation a At reading CO e R W
490. ster PG S isaninitial address that the stack pointer S indicates when an interrupt request is accepted The S s contents become S 5 after all of the above registers are pushed Fig 7 1 2 State of stack area just before entering interrupt routine 7721 Group User s Manual 7 3 INTERRUPTS 7 2 Interrupt sources 7 2 Interrupt sources Table 7 2 1 lists the interrupt sources and the interrupt vector addresses When programming set the start address of each interrupt routine at the vector addresses listed in this table Table 7 2 1 Interrupt sources and interrupt vector addresses Interrupt source Interrupt vector addresses Remarks Reference High order Low order address address Reset FFF Fis Non maskable 4 RESET Zero division FFFDi6 FFFCis Non maskable software interrupt 7700 Family Software BRK instruction FFFBie 6 Non maskable software interrupt Manual DBC Note FFFQ16 8 00 not use Watchdog timer FFF7 6 FFF616 Non maskable interrupt 15 WATCHDOG TIMER INTo FFF5 e 4 Maskable external interrupts 7 10 External interrupts INT FFF3 e FFF2 e INTI interrupt INT2 FFF 116 FFFOt6 Timer AO FFEF ie FFEE s Maskable internal interrupts B TIMER A Timer A1 FFED e FFECte Timer A2 FFEB e FFEAie Timer A3 916 FFE816 Timer A4 FFE7 6 FFE616 Timer BO 6 FFE4i6 Maskable internal interrupts 9 TIM
491. stination s transfer start address 3 parameter Transfer data s byte number 3 start address Next transfer parameter memory s start address 4 Dummy data Transfer parameter address 2 The above figure applies when 4 block transfer is performed 2 1 bus cycle transfer 4 bytes Transfer source s transfer start address 1 Even address Transfer data s byte number 1 transfer start Next transfer parameter memory s start address 2 address Even address i Transfer data s Transfer source s transfer start address 3 Transfer parameter byt b address 3 number Transfer data s byte number 3 Next transfer parameter memory s start address 4 Even address X90Jq 10 gt Transfer data s byte number 2 Next transfer parameter memory s start address 3 gt Transfer source s transfer start address 4 Transfer parameter Transfer data s byte number 4 address 4 last block 00000016 The above applies on the following conditions When data is transferred from memory to I O When transferring from I O to memory replace all the above mentioned Transfer source s transfer start address with Transfer destination s transfer start address 4 block transfer Fig 13 8 2 Transfer parameter memory map in link array chain transfer mode 7721 Group User s Manual 13 83 DMA CONTROLLER 13 8 Link arra
492. stored The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting of the interrupt request Refer to Figure 2 1 2 When completing the process in the interrupt routine and returning to the original routine the contents of registers stored in the stack area are restored into the original registers in the reverse sequence PS PCPG by executing the RTI instruction The contents of S is returned to the state before accepting an interrupt request The same operation is performed during a subroutine call however the contents of PS is not automatically stored The contents of PG may not be stored This depends on the addressing mode The user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls Additionally initialize S at the beginning of the program because its contents are undefined at reset The stack area changes when subroutines are nested or when multiple interrupt requests are accepted Therefore make sure of the subroutine s nesting depth not to destroy the necessary data Note Refer to 7700 Family Software Manual for addressing modes Stack area e 5 5 5 4 Processor status register s low order byte PSL S 3 Processor status register s high order byte PSH Program counter s low order byte PCL Program counter s high order byte PCH Program
493. struction LDM instruction LDA instruction CPU operation executed executed executed BIU operation Instruction prefetched Interrupt priority level select bits set A Change of interrupt priority levels completed 7721 Group User s Manual 17 69 APPENDIX Appendix 9 7721 Group Q amp A Interrupt To prevent this problem after change of the interrupt priority level is completed use software to execute the routine that should not accept a certain interrupt request The following shows a sample program Sample program After an instruction which writes 0002 to the interrupt priority level select bits fill the instruction queue buffer with the NOP instruction to make the next instruction not to be executed before the writing is completed LDM 00H XXXIC Sets the interrupt priority level select bits to 0002 NOP NOP NOP LDA A DATA Instruction at the beginning of the routine that should not accept a certain interrupt request 17 70 7721 Group User s Manual APPENDIX Appendix 9 7721 GroupQ amp A Interrupt 1 Which timing of clock is the external interrupts input signals to the INT pin detected 2 How can four or more external interrupt input pins INTi be used 1 In both the edge sense and level sense external interrupt requests occur when the input signal to the INT pin changes its level This is independent of clock In the edge sense the interrupt request bit i
494. t bis bo ROL Links the accumulator or the memory to C flag and rotates Note 1 result to the left by 1 bit ROR Links the accumulator or the memory to C flag and rotates Note 1 result to the right by 1 bit S lt S 1 Returns from the interruption routine PSLeM S 5 5 1 5 5 5 5 1 5 5 5 1 5 SeS 1 5 5 5 1 Returns the subroutine The contents of the program 68 PCieM S bank register are also restored 5 5 1 5 5 5 1 5 5 85 1 Returns from the subroutine The contents of the program 60 5 bank register are not restored 5 5 1 5 SBC Acc Subtracts the contents of the memory the borrow from Notes 1 2 the contents of the accumulator 17 50 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Processor status register L DIR L DIR Y ABS ABS aBs x aBs Y ABL ABL x ABS JL ABS ABS X STK REL oimbR aBsbR sR SR Y BLK 5 lop n op n amp Jop n op n op n fop n Jop n op n
495. t Note 2 Invalid Write to timer Bj register Timer Bj overflow flag The bit used to identify the source of an interrupt request occurrence Notes 1 No interrupt request occurs when the first valid edge is input after the counter starts counting 2 The value read out from the timer Bj register is undefined after the counter starts counting until the second valid edge is input 7721 Group User s Manual 9 19 TIMER B 9 5 Pulse period Pulse width measurement mode 67 66 65 64 b3 62 bi i EGO Timer Bj mode register 0 1 Addresses 5 16 5 16 ee 6160 Operating mode select bits 10 Pulse period Pulse width measurement mode Measurement mode select bits Pulse period measurement Interval between falling edges of measurement pulse Pulse period measurement Interval between rising edges of measurement pulse Pulse width measurement Interval from a falling edge to a rising edge and from a rising edge to a falling edge of measurement pulse Do not select Nothing is assigned b7 b6 00 fe 01 fie 10 fea 1111512 Count source select bits 5 Timer Bj overflow flag 1 No overflow Undefined Note Overflowed Note The timer Bj overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit 1 b8 b7 bO Timer B1 register Addresses 5316 5216
496. t data register 1 1016 i 1E16 control register 0 01001019177 1 16 sweep pin select register ae 1 7721 Group User s Manual 17 3 APPENDIX Appendix 2 Memory assignment in SFR area Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after a reset 0 0 immediately after reset 1 1 immediately after reset Undefined immediately after Always 0 at reading Always 1 at reading 0 1 2 NN 0 immediately after reset Fix this bit to 0 reset Always undefined at reading Address Register name Access characteristics State immediately after reset b7 50 67 2016 A D register 0 RO 2 2116 2 2216 A D register 1 RO 2316 2416 A D register 2 RO 2 2516 2 2616 A D register 3 RO 2 2716 2816 A D register 4 RO 2916 2 2A16 A D register 5 RO 2 2816 2C16 A D register 6 RO 2016 2 2E16 A D register 7 RO 2 2F16 2 3016 UARTO transmit receive mode re
497. t in series Software protection Read the data of an input port several times to confirm that input levels are equal Since the output data may reverse because of noise rewrite data to the output port s Pi register periodically Rewrite data to port Pi direction registers periodically Fig 12 Setup for I O ports 6 Reinforcement of the power source line For the Vss and Vcc lines use thicker wiring than that of other signal lines When using a multilayer printed circuit board the Vss and Vcc patterns must each be one of the middle layers The following is necessary for double sided printed circuit boards one side the microcomputer is installed at the center and the Vss line is looped or meshed around it The vacant area is filled with the Vss line the opposite side the Vcc line is wired the same as the Vss line power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer s power source lines with the shortest possible wiring Reasons With external devices connected to the microcomputer the levels of many of the signal lines total external address buses 24 bits may change simultaneously causing noise on the power source line 17 64 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A Appendix 9 7721 Group amp A Information which may be helpful in fully utilizing the 7721 Group is
498. t is cleared to 0 by software Figure 9 3 3 shows an example of operation in the timer mode n Reload register s contents Starts counting Restarts counting 1 1 1 1 1 1 Counter contents Hex Set to 1 by software Cleared to 0 by software Set to 1 by software Count start bit Timer Bi interrupt request bit fi frequency of count source fe fie fea fs12 Cleared to 0 when interrupt request is accepted or cleared by software Fig 9 3 3 Example of operation in timer mode 9 12 7721 Group User s Manual TIMER B 9 3 Timer mode Precautions for timer mode While counting is in progress by reading the timer Bi register the counter value can be read out at any timing However if the timer Bi register is read at the reload timing shown in Figure 9 3 4 the value FFFF16 is read out If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting the set value is correctly read out Reload Counter value Hex es f Reload register s contents Time Fig 9 3 4 Reading timer Bi register 7721 Group User s Manual 9 13 TIMER B 9 4 Event counter mode 9 4 Event counter mode In this mode the timer counts an external signal Refer to Table 9 4 1 Figure 9 4 1 shows the structures of the timer B
499. t is set to 1 The first A D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register i The A D converter repeats operation until the A D conversion start bit is cleared to 0 by software The conversion result is transferred to the A D register i each time the conversion is completed 2 When an external trigger is selected A D converter starts operation when the input level to the ADrtra pin changes from to L while the A D conversion start bit is 1 The first A D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register i The A D converter repeats operation until the A D conversion start bit is cleared to 0 by software The conversion result is transferred to the A D register i each time the conversion is completed When the level of the ADtre pin changes from to L during operation the operation at that point is cancelled and is restarted from step Figure 12 6 2 shows the conversion operation in the repeat mode Trigger occur Conversion result Convert input voltage from A D register i ANi pin Fig 12 6 2 Conversion operation in repeat mode 7721 Group User s Manual 12 19 A D CONVERTER 12 7 Single sweep mode 12 7 Sing
500. t of the DMA transfer refer to section 13 3 4 Processing from DMA request until DMA transfer execution and for that from issuing instructions for forced termination until returning the right to use bus to the CPU refer to section 13 3 5 2 Forced termination 13 9 1 Cycle steal transfer mode 1 1 unit transfer In the following cases 1 unit transfer is performed at one DMAi transfer Refer to Figure 13 8 12 Single transfer mode except for the last 1 unit transfer Repeat transfer mode except for the last 1 unit transfer of a block Array chain transfer mode except for the first and last 1 unit transfers of each block Link array chain transfer mode except for the first and last 1 unit transfers of each block Right to use Transition Transfer Transition 4 5 Fig 13 9 1 1 unit transfer Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per 1 transfer unit In 2 bus cycle transfer Read cycle Write cycle Add a value which satisfies the read write conditions Refer to Table 13 4 1 In 1 bus cycle transfer Refer to Table 13 4 5 Transition of the right to use bus from DMAC to CPU 1 cycle Example 2 bus cycle transfer transfer unit 16 bits external data bus width 16 bits and under the following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backwa
501. t request occurrence Immediately after Stop mode is terminated Watchdog timer starts counting of fs from FFF e regardless of the contents of watchdog timer frequency select bit bit O at address 6116 Supply of and starts when Watchdog timer s most significant bit becomes 0 At this time a watchdog timer interrupt request does not occur When supply of starts the microcomputer executes the routine of the interrupt which is used to terminate Stop mode Watchdog timer restarts counting of the count source fs or fs12 which was counted immediately before executing the STP instruction from FFFie 15 6 7721 Group User s Manual WATCHDOG TIMER 15 3 Precautions for Watchdog timer 15 3 Precautions for Watchdog timer 1 When dummy data is written to address 6016 with the 16 bit data length writing to address 6116 is simultaneously performed Accordingly when the user does not want to change a value of the watchdog timer frequency select bit bit 0 at address 6116 write the previous value to the bit simultaneously with writing to address 6016 2 When the STP instruction is executed Watchdog timer stops Refer to section 5 3 Stop mode 3 Watchdog timer stops during DRAM refresh hold state and DMAC operation For Watchdog timer s structure refer to Figure 15 1 1 Accordingly when a bus request is changed in the period which is shorter than 1 cycle of the count source Note Watc
502. t sampling signal is 1 and is accepted DMA request acceptance Figure 13 3 2 shows an example of timing from the determination of a DMA request until the DMA transfer execution Refer to section 13 9 DMA transfer time for the time from DMA request generation until the CPU s regaining the right to use bus via DMA transfer Note In the following cases BUS REQUEST DMAC does not go 1 However the DMAi request bit remains set to 1 Accordingly after completion of each state the channel priority levels and bus use priority levels are determined and BUS REQUEST DMAC goes 1 if any DRAM refresh request or Hold request is not generated When a DMA request is generated during a burst transfer or in an array state However if a DRAM refresh request or Hold request is generated during this term its BUS REQUEST goes 1 When a DMA request is not accepted with a DRAM refresh request or Hold request generated 7721 Group User s Manual 13 23 DMA CONTROLLER 13 3 Control Transition of right When request is to use nies sampled at this point 1 unit transfer f E a Read cycle 1 Write cycle Channel priority level determination and bus i ag Brad gt use priority level determination 1 5 cycles of E RW Address Address Data enable bit DMAREQi When Burst transfer mode edge sense selected request bit When Burst transfer mode level sense sel
503. t transfer External Transfer Address directions Data s start Read Write cycle Unit cycle bus width unit address Formula No Wait With Wait DRAM area 16 bits 16 bits Fixed Forward Even 2 3 including Odd internal Backward Even bus Odd 2 3 b 4 d 8 bits Fixed Forward Even Odd 2 3 Backward 8 bits 16 bits Fixed Forward Even Odd Backward 8 bits Fixed Forward Even Odd 14i 2 a 3 c Backward Address directions Refer to section 13 4 2 3 Address directions in 1 bus cycle transfer There is no address direction on the side i A term of E L in 1 bus cycle i 1 at No Wait and i 2 at With Wait or DRAM area When Ready function is used Refer to section 3 3 Ready function the number of cycles extended by Ready must be added Indicates the corresponding waveform in Figure 13 4 7 1 bus cycle transfer cannot be performed When the external data bus width 16 bits and the transfer unit 8 bits are selected the data bus which the memory uses and the data bus to which I O is connected may be different In such a case data is copied from the data bus of a transfer source to that of a transfer destination by using the DMA latch For the combination that data copy may occur data copy delay time taata must be taken into consideration Table 13 4 6 lists the data flows on the data bus in 1 bus cy
504. ta Even address Internal data bus Ds tO D15 Data Odd address Invalid data Fig 2 2 3 Basic operating waveforms of bus interface unit BIU 2 14 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 3 Access space 2 3 Access space Figure 2 3 1 shows the M37721 s access space By combination of the program counter PC which is 16 bits of structure and the program bank register PG 16 Mbyte space from addresses 0 to FFFFFF e can be accessed For details about access of an external area refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES The memory and I O devices are assigned in the same access space Accordingly it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from I O devices 00000016 00007F 6 00008016 Internal RAM area 00047F 6 Bank 016 OOFFFFte 01000016 Bank 116 02000016 000046 A Bank 16 i Indicates the memory assignment FF000016 of the internal areas Bank FF16 FFFFFF e Indicates that nothing is assigned Note Memory assignment of internal RAM area varies according to the type of microcomputer This figure shows the case of the M37721S2BFP Refer to Figure 2 4 1 for the M37721S1BFP SFR Special Function Register Fig 2 3 1 M37721 s access space 7721 Group User s Manual 2 15 CENTRAL PROCESSING UNIT CPU 2 3 Access space 2
505. ta start address even transfer destination s data start address odd the number of transfer bytes 212 bytes Third block transfer source s data start address odd transfer destination s data start address odd the number of transfer bytes 214 bytes 1 19 5 2 4 3 19 6 2 3 3 19 7 4 3 3 1 177 cycles 7721 Group User s Manual 13 103 DMA CONTROLLER 13 9 DMA transfer time MEMORANDUM 13 104 7721 Group User s Manual CHAPTER 14 DRAM CONTROLLER 14 1 Overview 14 2 Block description 14 3 Setting for DRAMC 14 4 DRAMC operation 14 5 Precautions for DRAMC DRAM CONTROLLER 14 1 Overview 14 2 Block description 14 1 Overview Table 14 1 1 lists the performance specifications of DRAM controller hereafter called DRAMC Table 14 1 1 Performance specifications of DRAMC Item Performance specifications DRAM area 0 to 15 Mbytes programmable in a unit of 1 Mbyte Refreshing method CAS before RAS dispersive refreshing Refresh timer 8 bits Multiplexed address pins 10 14 2 Block description Figure 14 2 1 shows the block diagram of DRAMC Registers relevant to DRAMC are described below Refresh request Bus Access controller RAS and CAS Refresh timer 1 1 generating circuit DRAM Address comparator control register A20 A23 Address Address multiplexer
506. ted analog input pins the conversion is performed The conversion result is transferred to the A D register i each time each pin is converted When step is completed the A D conversion interrupt request bit is set to 1 The A D conversion start bit is cleared to 0 and the A D converter stops operation When an external trigger is selected The A D converter starts operation for the input voltage from the ANo pin when the input level to the ADtre pin changes from to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register 0 For all of the selected analog input pins the conversion is performed The conversion result is transferred to the A D register i each time each pin is converted When step is completed the A D conversion interrupt request bit is set to 1 The A D conversion stops The A D conversion start bit remains set to 1 after the operation is completed Accordingly the operation of the A D converter can be performed again from step when the level of the ADrre pin changes from H to L When the level of the ADtra pin changes from to L during operation the operation at that point is cancelled and is restarted from step
507. ter De Ds or oe ve os e e Be v b7 receive buffer register Receive data Fig 11 3 11 Receive operation Receive enable bit Transmit enable bit y Dummy data is set to UARTi transmit buffer register Transmit buffer d empty flag i UARTi transmit register UARTi transmit buffer register RTSi Received data taken in UARTi receive register UARTI receive buffer register receive buffer register is read out Receive complete flag lis 947 UARTI receive interrupt request bit zt Cleared to 0 when interrupt request is accepted or cleared by software When the CLKi pin s input level is H satisfy the following conditions Transmit enable bit gt 1 Receive enable bit 1 fext Frequency of external clock Writing of dummy data to UARTi transmit buffer register The above timing diagram applies when the following setting conditions are satisfied External clock selected RTS function selected Fig 11 3 12 Example of receive timing when selecting external clock 11 28 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial mode 11 3 6 Processing on detecting overrun error In the clock synchronous serial I O mode an overrun error can be detected An overrun error occurs when the next data is prepared in the UARTi receive register with the receive complete flag
508. ter H Address 6916 DMAS enabled may be O or 1 Fig 16 2 13 Initial setting example for relevant register 2 7721 Group User s Manual 16 55 APPLICATION 16 3 Comparison of sample program execution rate 16 3 Comparison of sample program execution rate Sample program execution rates are compared in this paragraph The execution time ratio depends on the program or the usage conditions 16 3 1 Differences depending on data bus width and software Wait Internal areas are always accessed with data bus of which width is 16 bits and no software Wait In the external areas the external data bus width and software Wait are selectable Table 16 3 1 lists the sample program Refer to Figure 16 3 1 execution time ratio depending on these selection and usable memory areas Table 16 3 1 Sample program execution time ratio external data bus width and software Wait Memory area External data bus S Sample program execution time ratio oftware Wait RAM ROM width unit bit Sample A Sample B None 1 00 1 00 2 Inserted 1 17 1 10 Internal External None 1 19 1 08 8 Inserted 1 67 1 46 None 1 00 1 00 Inserted 1 25 1 17 External Internal None 1 19 1 13 8 Inserted 1 78 1 65 Calculated value 0 92 0 90 Calculated value The value is calculated from the shortest execution cycle number of each instruction described in 7700 Family Software Manual
509. ter and timer Aj register in one shot pulse mode 8 30 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 1 Setting for one shot pulse mode Figures 8 5 2 and 8 5 3 show an initial setting example for registers relevant to the one shot pulse mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting one shot pulse mode and each function b7 50 Jo fatto Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 Selection of one shot pulse mode Trigger select bits b4 b3 j Writing 1 to one shot start bit Internal trigger 10 Falling edge of TAjin pin s input signal External trigger 11 Rising edge of input signal External trigger Count source select bits b7 b6 00 f2 01 16 10 fea 11 f512 Setting level width of one shot pulse b15 b8 b7 bO 57 60 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F ie 4 16 EN Can be set 000116 to FFFF e n Note H level width 1 fi Frequency of count source Setting interrupt priority level b7 b0 _ A Timer Aj interrupt control register j 2 to 4 PETE CLL Addresses 7716 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interru
510. terrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the transfer is forced into termination 13 50 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 13 4 4 Cycle steal transfer mode When the transfer mode select bit 1 and the edge sense level sense select bit 0 this mode is selected Refer to Figures 13 2 6 and 13 2 8 In this mode all of the DMA request sources are available Figure 13 4 11 shows a transfer example in the cycle steal transfer mode 1 transfer unit data is transferred for each DMA request The BUS REQUEST signal is sampled basically at every completion of 1 unit transfer Refer to Table 13 2 3 When a DRAM refresh request or Hold request is generated at this time the right to use bus is not returned to the CPU and the request is accepted When several DMA requests are generated the request of the channel which has the highest priority among them is accepted and DMA transfer is performed without returning the right to use bus to the CPU When any request is not generated the CPU gains the right DMAREQO DMAO request bit DMAO enable bit DMAREQ1 DMA1 request bit 1 enable bit DRAM refresh request Right to use bus CPU 1 CPU 1 1 PRAM TDMA ceu This example applies on the following conditions Both of DMAO and DMA1 request sources are external sources Channel priority level F
511. the conversion start bit is cleared to 0 by software When the level of the ADtre pin changes from to L during operation the operation at that point is cancelled and is restarted from step Figure 12 8 2 shows the conversion operation in the repeat sweep mode 12 26 7721 Group User s Manual A D CONVERTER 12 8 Repeat sweep mode Trigger occur Conversion result Convert input voltage from ANo pin gt A D register 0 N Conversion result Convert input voltage from AN pin A D register 1 Conversion result Convert input voltage from ANi pin ap A D register i Fig 12 8 2 Conversion operation in repeat sweep mode 7721 Group User s Manual 12 27 A D CONVERTER 12 9 Precautions for A D converter 12 9 Precautions for A D converter 1 Writing to the following must be performed before a trigger occurs while the A D converter halts Each bit except bit 6 of the A D control register Each bit of the A D sweep pin select register When an external trigger is selected the ANz ADrne pin is disconnected from the comparator Therefore this pin cannot be used as an analog input pin When the AN pin is selected as an analog input pin while an external trigger is selected the A D converter operates however an undefined value is stored into the A D register 7 3 Refer to Appendix 8 Countermeasure against noise when using the A D converter 12 28 7721
512. the BIU fetches only 1 byte with the timing of waveform a The contents at the even address are not taken into the instruction queue buffer 2 When reading or writing data to and from the device When accessing a 16 bit data which begins at an even address waveform a is applied The 16 bits of data are accessed at a time When accessing a 16 bit data which begins at an odd address waveform b is applied The 16 bits of data are accessed separately in 2 operations 8 bits at a time Invalid data is not fetched into the data buffer When accessing 8 bit data at an even address waveform is applied The data at the odd address is not fetched into the data buffer When accessing 8 bit data at an odd address waveform a is applied The data at the even address is not fetched into the data buffer For instructions that are affected by the data length flag m and the index register length flag x operation or is applied when flag m or x 0 operation or is applied when flag m or x 4 7721 Group User s Manual 2 13 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit Internal address bus Ao tO A23 X Address X Internal data bus Do tO D7 Data Even address Internal data bus Ds 10 D15 Data Odd address eS Internal address bus Ao tO A23 Address Odd address Address Even address Internal data bus Do to D7 Invalid data Da
513. the BRGi s output divided by 16 becomes the transfer clock The data which is written to the UARTi baud rate register BRGi is written to both the timer and the reload register whether transmission reception is in progress or not Accordingly writing to these register must be performed while transmission reception is stopped Figure 11 2 10 shows the structure of the UARTi baud rate register BRGi Figure 11 2 11 shows the block diagram of transfer clock generating section UARTO baud rate register Address 3116 UART1 baud rate register Address 3916 7 to 0 Can be set to 0016 to FF e Undefined WO Assuming that the set value n BRGi divides the count source frequency by n 1 Note Writing to this register must be performed while the transmission reception halts Use the LDM or STA instruction for writing to this register Fig 11 2 10 Structure of UARTi baud rate register BRGi Clock synchronous serial I O mode fi BRGi 1 2 9 enemi control orout Transfer clock for transmit operation Receive control circuit gt Transfer clock for receive operation lt UART mode gt TT fext 1 16 Transfer clock for transmit operation 1 16 Transfer clock for receive operation fi Clock selected by BRG count source select bits f2 f16 164 or 1512 fext Clock input to CLKi pin external clock Fig 11 2 11 Block diagram of transfer clock generating section
514. the corresponding bit to 1 when the two phase pulse signal processing function is selected for timers A2 to A4 0 Two phase pulse signal processing function disabled 1 Two phase pulse signal processing function enabled Setting division ratio b15 50 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F 16 4E16 mz Can be set to 0000 e to FFFF e n The counter divides the count source frequency by n 1 when counting down or by FFFF e n 1 when counting up Continue to Figure 8 4 3 on next page Fig 8 4 2 Initial setting example for registers relevant to event counter mode 1 7721 Group User s Manual 8 21 TIMER A 8 4 Event counter mode From preceding Figure 8 4 2 etting interrupt priority level dt N Timer Aj interrupt control register 2 to 4 Addresses 7716 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 S Setting port P5 direction register b7 50 Port P5 direction register Address D16 2 4 TA4IN pin Clear the bit corresponding to the TAjin pin to 0 When selecting the TAjour pin s input signal as the up down switching factor set the bit corresponding to the TAjour pin to 0
515. the highest priority among functions which issue bus requests when the BUS REQUEST signal is sampled This is the bus request acceptance If any bus request is not generated at bus request sampling the CPU gains the right to use bus The bus use priority levels are fixed by hardware and the bus status is reported by status signal outputs STO and ST1 Table 13 2 2 lists the relationship between the bus use priority level bus status and status signals Table 13 2 2 Relationship between bus use priority level bus status and status signals priority level ST1 STO 1 Highest DRAM refresh 2 Hold 3 DMAC 4 Lowest CPU Including the term while the CPU does not use the bus for example the term when the CPU is calculating and does not use the bus 7721 Group User s Manual 13 7 DMA CONTROLLER 13 2 Block description The BUS REQUEST signal is sampled at a break in bus use Table 13 2 3 and Figure 13 2 3 shows the timings of bus request sampling Also bus request sampling signals are shown in them Table 13 2 3 Bus request sampling timing Bus user Bus request sampling timing DRAM refresh After completion of a DRAM refresh cycle Hold Every 1 cycle of S R All except the following After completion of 1 unit transfer Note 1 At the end of each block After 1 unit transfer and terminate processing 3 cycles of 0 etc are performed sequentially Array
516. the index register X by 1 DEY Ye Y 1 Decrements the contents of the index register Y by 1 DIV Notes 2 10 A quotient B A M B remainder he numeral that places the contents of accumlator B to the higher order and the contents of accumulator A to the lower order is divided by the contents of the memory The quotient is entered into accumula or A and the remainder into accumulator B EOR Notes 1 2 Accc Acc M Logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory The result is placed into the accumulator INC Note 1 1 or lt 1 Increments the contents of the accumulator or memory by f Xc X 1 Increments the contents of the index register X by 1 lt 1 Increments the contents of the index register Y by 1 ABS PCL ADL ABL PCL ADL PG c ADc ABS PCi lt ADu 1 L ABS PCi lt ADu 0 1 PG c ADu 2 ABS X PCi lt ADu ADL X PCue ADu ADL X 1 Places a new address into the program counter and jumps to that new address 17 44 ABS 5 5 5 1 5 Sc 8 1 PCL ADL ABL 5 Sc 8 1 5 Sc 8 1 M S e PC Sc 8 1 PCL ADL PG c ADc ABS X
517. this register while all of enable bits bits 4 to 7 at address 6916 0 m flag may be 0 or 1 Use the LDM or STA instruction for writing to this register When DMAi request bit bits 4 to 7 at address 6816 must not be changed set DMAi request bit to 1 DMAC control register H 67 b6 65 64 b3 02 bli 50 DMAC control register Address 6916 Software DMAO request bit 1 DMA request Valid when software DMA source The value is 0 at reading Software DMA3 request bit DMAO enable bit 0 Disabled 1 Enabled DMA enable bit E DMA2 enable bit enable bit Note When any of bits 4 to 7 is set to 1 use the CLB or SEB instruction for writing to this register 7721 Group User s Manual 17 31 APPENDIX Appendix 3 Control registers Interrupt control register 07 b6 65 63 b2 bi 50 DMAO to DMA3 conversion UARTO and 1 transmit UARTO and 1 receive timers 0 to A4 timers BO to B2 interrupt control registers Addresses 6 16 to 7 16 E Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Level 2 b oin ami Level 3 Level 4 Level 5 Level 6 Level 7 MEC 3 Interrupt request bit 0 No interrupt requested 1 Interrupt requested 1 1 2 Nothing is assigned ES 67 06 b5 04 b3 b2 bi 00 INTo to INT2 interrupt control registers
518. tion about the external area refer also to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES Figure 2 4 1 shows the memory assignment 2 4 1 Memory assignment in internal area SFR Special Function Register and internal RAM are assigned in the internal area 1 2 SFR area The registers for setting internal peripheral devices are assigned at addresses 0 to 7F e and 1FCO e to 1FFF e This area is called SFR Figures 2 4 2 and 2 4 3 show the SFR area s memory assignment For each register in the SFR area refer to each functional description in this manual For the state of the SFR area immediately after reset refer to section 4 1 2 State of CPU SFR area and internal RAM area Internal RAM area The M37721S2BFP Note 1 assigns the 1024 byte static RAM at addresses 8016 to 47F e 512 bytes of that can be selected either it is used as the internal RAM or it is used as the external area Note 2 The internal RAM area is used as a stack area Note 3 as well as an area to store data Accordingly note that set the nesting depth of a subroutine and multiple interrupts level not to destroy the necessary data Notes 1 The M37721S1BFP assigns the 512 byte static RAM at addresses 8016 to 27F ie 2 The internal RAM area becomes 512 bytes after reset because the internal RAM area select bit is 0 3 Either bank 016 or bank FF e can be selected as the stack area by the stack bank select bit bit 7 at address 5E Figure 2 4 4 sho
519. to Read The read value indicates the destination address of data which is next transferred Note When writing to this register write to all 24 bits 016 b15 Transfer counter register 0 Addresses 1FCAte to 1FC816 TCRO Transfer counter register 1 Addresses 1FDA16 to 1FD816 1 Transfer counter register 2 Addresses 1 16 to 1FE816 TCR2 Transfer counter register Addresses 1 16 to 1FF816 TCR3 2 Write Set the byte number of the transfer data RW These bits can be set to 00000116 to Read The read value indicates remaining byte number of the transfer data Note When writing to this register write to all 24 bits Do not set this register to 00000016 Fig 13 5 1 Register structures of SARi DARi and TCRi in single transfer mode 7721 Group User s Manual 13 55 DMA CONTROLLER 13 5 Single transfer mode 13 5 1 Setting of single transfer mode Figures 13 5 2 through 13 5 4 show an initial setting example for registers relevant to the single transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function When a DMAi interrupt is used the setting for enabling the interrupt is also required For details refer to CHAPTER 7 INTERRUPTS When
520. to instruction queue buffer 2 When the instruction which is next fetched is located at an even address When the external data bus width is 16 bits the BIU fetches 2 bytes of the instruction at a time with waveform a When the external data bus width is 8 bits the BIU fetches only 1 byte of the instruction with the first half of waveform e When the instruction which is next fetched is located at an odd address When the external data bus width is 16 bits the BIU fetches only 1 byte of the instruction with waveform d When the external data bus width is 8 bits the BIU fetches only 1 byte of the instruction with the first half of waveform f When a branch to an odd address is caused by a branch instruction etc with the 16 bit external data bus width the BIU first fetches 1 byte of the instruction with waveform d and after that fetches instructions in a unit of 2 bytes with waveform a When reading or writing data from and to memories or I O devices When accessing 16 bit data which begins at an even address waveform or e is applied When accessing 16 bit data which begins at an odd address waveform b or f is applied When accessing 8 bit data at an even address waveform c or the first half of e is applied When accessing 8 bit data at an odd address waveform d or the first half of f is applied For instructions that are affected by the data length flag m and the index register l
521. to the S lt S 1 stack M S DPRi S lt S 1 M S PG Saves the contents of the program bank register into the S lt S 1 stack 5 5 Saves the contents of the program status register into the S lt S 1 stack M S lt PSt S lt S 1 M S DT Saves the contents of the data bank register into the stack S lt S 1 x 0 Saves the contents of the index register X into the stack 5 S lt S 1 M S X S lt S 1 x 1 M S X 5 5 1 x 0 Saves the contents of the index register Y into the stack 5 S lt S 1 M S e Y S lt S 1 x 1 M S e Y Sc 1 m 0 Restores the contents of the stack on the accumulator A 5 5 1 5 SeS 1 5 1 5 5 1 5 m 0 Restores the contents of the stack on the accumulator B 5 5 1 BL lt M S 5 5 1 5 1 5 5 1 B eM S 5 5 1 ores the contents of the stack on the direct reg DPRL M S 5 5 1 5 Sc S41 Restores the contents of the stack on the processor status PSLeM S register S lt S 1 PSH M S Sc S41 ores the contents of the stack on the data bank reg DT lt M S x 0 ores the contents of the stack on the index register X 5 5 1 5 5 5 1 5 x 1 5 5 1 5 17 48 7721 Group User s Manual APPENDIX Appendix 6 Machine
522. tput from the status signal output pins STO and ST1 Table 2 5 1 lists the bus use priority levels and the status signals depending on the bus use state Table 2 5 1 Bus use priority levels and status signals depending on bus use state Status signal Bus use priority levels Bus use state STI STO 1 Highest DRAM refresh 0 0 2 Hold 0 1 3 DMAC 1 0 4 Lowest CPU Including the term that CPU does not use the bus 1 1 during calculation etc For details refer to section 13 2 1 Bus access control circuit and chapter for each peripheral devices 7721 Group User s Manual 2 23 CENTRAL PROCESSING UNIT CPU 2 5 Bus access right MEMORANDUM 2 24 7721 Group User s Manual CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 3 2 Software Wait 3 3 Ready function 3 4 Hold function Precautions for Hold function CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 3 1 Signals required for accessing external devices The functions and operations of the signals which are required for accessing the external devices are described below When connecting an external device that requires long access time refer to sections 3 2 Software Wait 3 3 Ready function and 3 4 Hold function as well as this section When the external DRAM is controlled by using DRA
523. tructures of interrupt control register 7721 Group User s Manual INTERRUPTS 7 3 Interrupt control 7 3 1 Interrupt disable flag I All maskable interrupts can be disabled by this flag When this flag is set to 1 all maskable interrupts are disabled when this flag is cleared to 0 those interrupts are enabled Because this flag is set to 1 at reset clear this flag to O when enabling interrupts 7 3 2 Interrupt request bit When an interrupt request occurs this bit is set to 1 This bit remains set to 1 until the interrupt request is accepted it is cleared to O when the interrupt request is accepted This bit can also be set to O or 1 by software The interrupt request bit i 0 to 2 is ignored when the interrupt is used with level sense 7 3 3 Interrupt priority level select bits and processor interrupt priority level IPL The interrupt priority level select bits are used to determine the priority level of each interrupt When an interrupt request occurs its interrupt priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when the comparison result meets the following condition Accordingly an interrupt can be disabled by setting its interrupt priority level to 0 Each interrupt priority level gt Processor interrupt priority level IPL Table 7 3 1 lists the setting of interrupt priority
524. ts 5 0 2 16 bits 3 Serial UARTO UART1 UART or clock synchronous serial I O 2 A D converter 8 bit successive approximation method 1 8 channels Watchdog timer 12 bits X 1 DMA controller 4 channels Maximum transfer rate 12 5 Mbytes sec at f Xin 25 MHz 1 bus cycle transfer Maximum transfer rate 6 25 Mbytes sec at 25 MHz 2 bus cycle transfer DRAM controller CAS before RAS refreshing method Real time output 4 bits X 2 channels or 6 bits X 1 channel 2 bits X 1 channel Interrupts 3 external 20 internal priority levels O to 7 can be set for each interrupt with software Clock generating circuit Built in externally connected to a ceramic resonator or a quartz crystal oscillator Supply voltage 5 V 10 Power dissipation 135 mW at 25 MHz typ Port Input Output Input Output withstand voltage 5V characteristics Output current 5 mA Memory expansion Maximum 16 Mbytes Operating temperature range 20 to 85 C Device structure CMOS high performance silicon gate process Package 1 2 100 pin plastic molded QFP 7721 Group User s Manual 1 2 Pin configuration Figure 1 2 1 shows the M37721S2BFP pin configuration P67 RTP13 lt gt P60 RTPOo lt gt 8 P57 TB1 5 P5s TA4 9 lt gt 10 Nc 11 P54 TA4out gt 12
525. ts priority level is higher than the IPL However this applies when the interrupt disable bit 1 0 To disable timer Bi interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when a timer Bi interrupt request occurs This bit is automatically cleared to 0 when the timer Bi interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 9 6 7721 Group User s Manual TIMER B 9 2 Block description 9 2 5 Port P5 direction register Input pins of Timer Bj are multiplexed with port P5 When using these pins as Timer Bj s input pins set the corresponding bits of the port P5 direction register to 0 to set these port pins for the input mode Figure 9 2 5 shows the relationship between port P5 direction register and the Timer Bj s input pins 67 06 65 64 63 b2 bi 00 pin 0 Input mode 9 Rw i When using these pins as ESI TA3our pin Timer Bj s input pins set the TA3N pin corresponding bits to 0 Tao TA4In TBON pin Bits 010 5 are not used for Timer B Fig 9 2 5 Relationship between port P5 direction register and Timer Bj s input pins 7721 Group User s Manual 9 7 TIMER B 9 3 Timer mode 9 3 Timer mode In this mode the timer counts an internally generated count source Refer to Table 9 3 1 Figure 9 3 1 shows the structures of the ti
526. ulse period measurement Figure 9 5 4 shows the operation during pulse width measurement 7721 Group User s Manual 9 23 TIMER B 9 5 Pulse period Pulse width measurement mode Count source Measurement pulse Transferred Reload register Counter undefined value Transfer timing Timing at which counter is cleared to 000016 Count start bit Timer Bj interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer Bj overflow flag Counter is initialized by completion of measurement Counter overflow Note The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse Fig 9 5 3 Operation during pulse period measurement Count source Transferred TransferredY undefined Transferred measured Transferred Mvalue j measured value Wf measured vA value value Reload register Counter Transfer timing Timing at which counter is cleared to 000016 Count start bit Timer Bj interrupt request bit Cleared to 0 when interrupt request is accepted or f Timer Bj overflow flag by Software Counter is initialized by completion of measurement Counter overflow Fig 9 5 4 Operation during pulse width measurement 9 24 7721 Group User s
527. unter mode 1 0 One shot pulse mode 1 1 Pulse width modulation PWM mode Fig 8 2 3 Structure of timer Ai mode register 8 6 7721 Group User s Manual TIMER A 8 2 Block description 8 2 4 Timer Ai interrupt control register Figure 8 2 4 shows the structure of the timer Ai interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS 67 06 05 64 63 02 61 Timer Ai interrupt control register i 0 to 4 Addresses 7516 to 7916 riority level Level 0 Interrupt disabled RW Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 RW Level 6 Level 7 High level Interrupt request bit e No interrupt requested Interrupt requested 7 to 4 Nothing is assigned Fig 8 2 4 Structure of timer Ai interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a timer Ai interrupt s priority level When using timer Ai interrupts select one of the priority levels 1 to 7 When a timer Ai interrupt request occurs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag 1 0 To disable timer Ai interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1
528. up User s Manual DMA CONTROLLER 13 6 Repeat transfer mode JO 19JsueJ IHVS 01195 SI YOIUM 99 Jes u peideooe si pue 5 euis 5 jsenbas eui si pjoH 10 Aq pesneo sng e OVWG lt snq esn oj 9 anjea 195 HOL IHYA 01195 S U9IUM 99 ON uoneunsep Jejsuei ON NOS J9JSUEJ 4 1ejsue uonoeuip eoinos Jejsuei Jaysuedy epo o snq z JeJSUeJ SIIq 91 JoJSUeJ 91 suonipuoo eui uo 5141 e esn o1 Jo uopsuea e 154 jo 1 1 nt 1 UN IMOVVING Buiduues 1senbai sng 1Q zv o qo Cams X 38988 oue X renes _ MH f repeat transfer mode burst transfer mode iagram o d iming Fig 13 6 6 T 13 67 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode 13 7 Array chain transfer mode This mode is used to transfer several blocks of data
529. upt request bit to 0 interval LDA A DATA Instruction at the beginning of the routine which should not accept one certain interrupt request As for the change of the interrupt priority level when the following are met the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled The next instruction in the above example it is the LDA instruction is already stored into a instruc tion queue buffer for the BIU Conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed When writing to a memory or an I O the CPU passes the address and data to the BIU Then the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address Detection of interrupt priority level is performed at the beginning of each instruc tion In the above case the CPU executes the next instruction before the BIU completes the change of the interrupt priority level Therefore when the interrupt priority level is detected synchronously with the execution of the next instruction the interrupt priority level before the change is detected and its interrupt request is accepted Interrupt request generated Sequence of execution gt Interrupt request accepted Interrupt priority detection time lt gt lt gt lt gt Previous in
530. ur models listed in Table 16 1 1 1 2 3 4 16 2 Minimum model This is a connection model of which external data bus width is 8 bits and access space is expanded up to 64 Kbytes It is unnecessary to connect the address latch externally so this model gives priority to cost and is most suitable when connecting the memory of which data bus width is 8 bits Medium model A This is a connection model of which external data bus width is 8 bits and access space is expanded up to 16 Mbytes In this model the high order 8 bits of the external address bus A16 to A23 are multiplexed with the external data bus Therefore an n bit n lt 8 address latch is required for latching n bits of the address Ais to Azs Medium model B This is a connection model of which external data bus width is 16 bits and access space is expanded up to 64 Kbytes This model gives priority to rate performance In this model the middle order 8 bits of the external address bus As to Ais are multiplexed with the external data bus Therefore an 8 bit address latch is required for latching to Ais Maximum model This is a connection model of which external data bus width is 16 bits and access space is expanded up to 16 Mbytes In this model the high and middle order 16 bits of the external address bus As to A23 are multiplexed with the external data bus Therefore an 8 bit address latch for latching As to Ais and an n bit lt 8 addres
531. urce s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits Start address of next transfer parameter memory 24 bits Note Dummy data 8 bits In 1 bus cycle transfer from I O to memory All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 12 bytes for each block Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits Start address of next transfer parameter memory 24 bits Note Dummy data 8 bits For the last block of data write 00000016 as the start address of the next transfer parameter memory 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 1 2 bus cycle transfer 4 bytes 7 Transfer source s transfer start address 1 Transfer source s L Even address Transfer desta vance sat address 1 transfer start M address Transfer L Even address destination s transfer Transfer source s transfer start address 4 Transfer parameter start address Transfer destination s transfer start address 4 address 4 last block Dummy data Transfer data s byte number 4 L Even address 00000016 Transfer data s byte number Dummy data H yoolq JO Next transfer Even address Transfer de
532. urs when transmission starts UARTi transmit interrupt Note This figure shows the bits and registers required for processing Refer to Figures 11 4 6 to 11 4 8 for the change of flag state and the occurrence timing of an interrupt request 11 37 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 4 Transmit operation When the receive conditions described in section 11 4 3 Method of transmission are satisfied a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed The transmit buffer register s contents are transferred to the UARTi transmit register The transmit buffer empty flag is set to 1 The transmit register empty flag is cleared to 0 UARTIi transmit interrupt request occurs and the interrupt request bit is set to 1 The transmit operations are described below Data in the UARTIi transmit register is transmitted from the TxDi pin Q This data is transmitted bit by bit sequentially in order of LSB DATA MSB 5PAR SP according to the transfer data format The transmit register empty flag is set to 1 at the center of the stop bit or the second stop bit when selecting 2 stop bits indicating completion of transmission Additionally whether the transmit conditions for the next data are satisfied or not is examined When the transmit conditions for th
533. ut OFF Assuming that the segment pattern is generated by another processing M37721 7 segment LED X 8 Data buffer driver LED HR f LED driver Fig 16 2 11 Example of dynamic lighting for LED Table 16 2 2 Data buffer Data buffer Digit data Segment pattern 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Notes 1 This applies in the following ewhen the digit data is 0 the light goes out ewhen the digit data is 1 the LED is lighted up 2 Assuming that the segment pattern is generated by another processing Segment pattern of the contents to be displayed in each digit 7721 Group User s Manual 16 53 APPLICATION 16 2 Examples of using DMA controller b7 50 1 0 1 0 0 mode register L Address 1FFC16 Transfer unit 16 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction Forward Transfer destination address direction Fixed b7 60 mode register Address 1FFD16 No transfer source Wait No transfer destination Wait Repeat transfer mode b23 b16b15 b8b7 00 Source address register Addresses 1FF216 to 1 16 L Data buffer s start address b23 016015 0807 50 00
534. utput BHE output BLE output R W output td o1 STi la AL E le th E AL d AM E gt td E DHQ E EK LE AM d E DLQ t gt lt lt lt tha 1 ta AH E lt Adis dress tw ALE lt td ALE E ta BHE E 31 1 td BLE E ta R W E 4 E Test conditions Vcc 2 5V 10 26 Output timing voltage 0 8 V 2 0 V Do Dt5 input 0 8 V 2 5 V DMAREQi input Vit 0 8 V 2 5 V 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics At DMA transfer Cycle steal transfer timing External source DMAREQi 1 E tsu DRQ 61 DMAREGI td o1 STi STO ta o1 STi 9 1 DMAACKi td AL E th E AL As Ds A15 D15 output IC rrr Ad Nes cis Dol BYTE 4 dress td AM E gt lt th E AM As Ds A15 D15 output td AH E le output oss Qare tw ALE le td ALE E ALE output td BHE E th E BHE td BLE E th E BLE ta R W E R W output Test conditions Vcc 2 5 V 10 96 Output timing voltage 0 8 V 2 0 V Do Dt5 input 0 8 V 2 5 V DMAREQi input 0 8 V 2 5 V 7721 Group User s Manual 17 99 APPENDIX Appendix 11 Electrical characteristics At DMA transf
535. vel to level 0 or set the interrupt disable flag I to 1 or set the interrupt disable flag I to 1 INTi interrupt is disabled INTi interrupt is disabled Clear the level sense edge sense select bit to 0 Set the polarity select bit Edge sense is selected Clear the interrupt request bit to 0 Set the interrupt priority level to one of levels 1 7 or clear the interrupt disable flag I to 0 Clear the interrupt request bit to 0 or clear the interrupt disable flag I to 0 INTi interrupt request is acceptable Note The above settings must be done separately Multiple settings must not be done at the same time in other words they must not be done only by 1 instruction Fig 7 10 5 Example of switching procedure for INTi interrupt request occurrence factor 7721 Group User s Manual 7 21 INTERRUPTS 7 11 Precautions for interrupts 7 11 Precautions for interrupts When changing the interrupt priority level select bits bits 0 to 2 at addresses 6Cis to 7F e 2 to 7 cycles of are required until the interrupt priority level is changed Therefore when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time which consists of a few instructions it is necessary to reserve the time required for the change by software Figure 7 11 1 shows a program example to reserve the time required for the change Note that the time
536. w ALE 6 99 ta ALE E ALE output J 9 th E BHE BHE output th E BLE Ta R W E y th E R W R W output gt EY Ta eee MEE ee tsu PiD E Jl e tavE Pia Port Pi input i 4 10 Test conditions port Pi Vcc 25V 10 Vcc 2 5 10 Input timing voltage 1 0 V 4 0 V Output timing voltage 0 8 V 2 0 Output timing voltage 0 8 V 2 0 V Data input 0 8 V 2 5 V Test conditions except port Pi 7721 Group User s Manual 17 91 APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with Wait Note The limits depend on f Xin Table 4 lists calculation formulas for the limits Timing requirements Vcc 5 V 10 Vss 0 V 20 to 85 C 25 MHz unless otherwise noted Symbol Parameter WS Unit te External clock input cycle time 40 ns twit External clock input high level pulse width 15 ns twit External clock input low level pulse width 15 ns tr External clock input rising time 8 ns External clock input falling time 8 ns lsurip Port Pi input setup time i 4 10 60 ns th E PiD Port Pi input hold time i 4 10 0 ns Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted
537. when a timer Ai interrupt request occurs This bit is automatically cleared to 0 when the timer Ai interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 7721 Group User s Manual 8 7 TIMER A 8 2 Block description 8 2 5 Port P5 direction register The I O pins of Timers A2 to 4 are multiplexed with port P5 When using these pins as Timer Aj s input pins set the corresponding bits of the port P5 direction register to 0 to set these port pins for the input mode When used as Timer 5 output pins these pins are forcibly set to the output pins of Timer Aj regardless of the direction registers s contents Figure 8 2 5 shows the relationship between the port P5 direction register and the Timer Aj s I O pins 67 06 b5 04 b3 b2 bi Port P5 direction register Address D16 0 Input mode RW 1 Output mode 1 TA2 pin When using these pins as Timer Aj 2 TASour pin s input pins set the corresponding bits to 0 3 4 TA4our Ce mem Bits 6 and 7 are not used for Timer Fig 8 2 5 Relationship between port P5 direction register and Timer Aj s I O pins 8 8 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 Timer mode In this mode the timer counts an internally generated count source Refer to Table 8 3 1 Figure 8 3 1 shows the structures of the timer Ai mode register an
538. when disabling this interrupt P7 direction register gt b7 60 Port P7 direction register address 1116 ANo AN2 Set the bits corresponding AN3 to analog input pins to 0 AN4 Set bit 7 to 0 when ANs selecting external trigger AN7 Set A D conversion start bit 1 57 50 1 A D control register address 1 16 A D conversion start bit P When external trigger is selected dum falling edge to A V ADrne When internal trigger is selected A Trigger occur Operation start Note Writing to each bit except bit 6 of the A D control register and each bit of the A D sweep pin select register must be performed while the A D converter halts before a trigger occurs Fig 12 7 1 Initial setting example for registers relevant to single sweep mode 7721 Group User s Manual 12 21 A D CONVERTER 12 7 Single sweep mode 12 7 2 Single sweep mode operation description 1 2 12 22 When an internal trigger is selected The operation for the input voltage from the ANo pin starts when the A D conversion start bit is set to 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register 0 For all of the selec
539. wise noted Symbol Parameter Test conditions Min To Max Unit Resolution Vrer Voc 8 Bits Absolute accuracy Vrer Vcc 3 LSB Rapper Ladder resistance Vrer Voc 2 10 tcov time 9 12 us VREF Reference voltage 2 Vcc V Via Analog input voltage 0 Vrer V 17 82 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Internal peripheral devices timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Note The limits depend on f Xin Table 3 lists calculation formulas for the limits Timer A input Count input in event counter mode Limits Symbol Parameter Min Max Unt tota TAjin input cycle time 80 ns TAjin input high level pulse width 40 ns tw TAL input low level pulse width 40 ns Timer A input Gating input in timer mode Limits Symbol Parameter Min Max Unit teta TAjin input cycle time Note ns tw TAH TAjw input high level pulse width Note 160 ns TAj input low level pulse width Note 160 ns Timer A input External trigger input in one shot pulse mode Limits Symbol Parameter Min Mant tera TAjin input cycle time Note 160 ns tw TAH TAjin input high level pulse width 80 ns tw T
540. ws the structure of the processor mode registers 0 1 7721 Group User s Manual 2 17 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment 2 4 2 External area Table 2 4 1 lists the external area When connecting the external device follow the procedure described bellow Connect the ROM to addresses FFCE e to FFFFie because they are interrupt vector table Stack area can be assigned to bank or bank FF e Select the stack area by the stack bank select bit bit 7 at address 5 Refer to Figure 2 4 4 When using the DRAM controller DRAM area can be selected from address FFFFFF e toward the low order address in a unit of 1 Mbytes Refer to CHAPTER 14 DRAM CONTROLLER In the case connecting an external device to the area where overlaps the internal area when reading out the overlapping area the central processing unit CPU take in data of the internal area and do not take in data of the external area When writing to the overlapping area data is written to the internal area The signal is output to the external at the same timing when data is written to the internal area Table 2 4 1 External area TASE Pp tT 0 Ohiso 0 216 916 216 916 External area 48016 1 28016 1F BF ie 20001e FFFFFF 6 20001e FFFFFF ie Type name Internal RAM area select bit Internal RAM area select bit bit 1 at address 5F e 2 18 7721 Group User s Manual CENTRAL PROCESSING UNI
541. y Count source Count Count source frequency select bits source b7 b6 f Xin 8 MHz f Xin 16 MHz f Xin 25 MHz 0 0 fe 4 MHz 8 MHz 12 5 MHz 0 1 fie 500 kHz 1 MHz 1 5625 MHz 1 0 fea 125 kHz 250 kHz 390 625 kHz 1 1 512 15625 Hz 31250 Hz 48 8281 kHz 7721 Group User s Manual 8 33 TIMER A 8 5 One shot pulse mode 8 5 3 Trigger The counter is enabled for counting when the count start bit address 4016 is set to 1 The counter starts counting when a trigger is generated after counting has been enabled An internal or external trigger can be selected as that trigger An internal trigger is selected when the trigger select bits bits 4 and at addresses 5816 to 5A16 are 002 or O12 an external trigger is selected when the bits are 102 or 112 If a trigger is generated during counting the reload register s contents are reloaded and the counter continues counting If generating a trigger during counting make sure that a certain time which is equivalent to one cycle of the timer s count source or more has passed between the previously generated trigger and a new trigger 1 When selecting internal trigger A trigger is generated when writing 1 to the one shot start bit bits 2 to 4 at address 4216 Figure 8 5 4 shows the structure of the one shot start register 2 When selecting external trigger A trigger is generated at the falling edge of the TAjin pin
542. y chain transfer mode 13 8 2 Setting of link array chain transfer mode Figures 13 8 3 through 13 8 5 show an initial setting example for registers relevant to the link array chain transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function When a DMAi interrupt is used the setting for enabling the interrupt is also required For details refer to CHAPTER 7 INTERRUPTS When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 0 Port P9 direction register Address 1516 DMAREQO pin DMAREQ DMAREGQ3 pin Clear the corresponding bit to 0 r PEPE ELI Setting interrupt priority level b7 bO DMAi interrupt control register i 0 to 3 LL Addresses 6C1s to Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Continue to Figure 13 8 4 on next page Fig 13 8 3 Initial setting example for registers relevant to link array chain transfer mode 1 13 84 7721 Group User s Manual DMA CONTROLLER 13
543. y level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag 1 0 To disable DMAi interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when a DMAi interrupt request occurs after the DMA transfer is complete This bit is automatically cleared to 0 when the DMAi interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 7721 Group Users Manual 13 17 DMA CONTROLLER 13 2 Block description 13 2 14 Port P9 direction register pins of DMAi are multiplexed with port P9 When using these pins as the DMAREQi input pins set the corresponding bits of the port P9 direction register to 0 to set these port pins for the input mode When using these pins as the DMAACKi output pins these pins are forcibly set to the DMAACKi output pins regardless of the direction register s contents Figure 13 2 10 shows the relationship between the port P9 direction register and DMAi s I O pins 67 06 65 b4 b3 b2 bi Port P9 direction register Address 15 6 omom Sen 1 Output mode o aw 6 7 25 224 When using pins P91 9 P95 and corresponding bits to 0 Rw Fig 13 2 10 Relationship between port P9 direction register and 5 I O pins Precaution

MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700

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