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TC1782 Data Sheet

1. Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 40 AN24 l D ADC1 Analog Input Channel 24 39 AN25 l D ADC1 Analog Input Channel 25 38 AN26 l D ADC1 Analog Input Channel 26 37 AN27 l D ADC1 Analog Input Channel 27 35 AN28 l D ADC1 FADC Analog Input Channel 28 34 AN29 l D ADC1 FADC Analog Input Channel 29 33 AN30 l D ADC1 FADC Analog Input Channel 30 32 AN31 l D ADC1 FADC Analog Input Channel 31 31 AN32 l D FADC Analog Input P Channel 0 30 AN33 l D FADC Analog Input N Channel 0 29 AN34 l D FADC Analog Input P Channel 1 28 AN35 l D FADC Analog Input N Channel 1 54 Vopm ADC Analog Part Power Supply 3 3V 5V 53 Vaaw ADC Analog Part Ground 52 VaREFO ADCO and ADCI Reference Voltage 51 VAGNDO ADC Reference Ground 24 Vopme FADC Analog Part Power Supply 3 3V 23 VoparF FADC Analog Part Logic Power Supply 1 3V 25 VssmF FADC Analog Part Ground Vssar FADC Analog Part Ground 26 Vearer FADC Reference Voltage 27 VEAGND FADC Reference Ground a Von Digital Core Power Supply 1 3V 21 68 84 91 99 123 153 170 2 Data Sheet 38 V 1 4 1 2014 05 Cinfineon e PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pi
2. Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 71 P1 14 OO A1 Port 1 General Purpose I O Line 14 IN18 PU LTCA2 Input 18 ADOEMUX2 JO1 ADCO External Multiplexer Control Output 2 ADOEMUX2 O2 ADCO External Multiplexer Control Output 2 OUT18 O3 LTCA2 Output 18 117 JP1 15 OO A2 Port 1 General Purpose I O Line 15 BRKIN l PU Break Input Reserved O1 Reserved O2 Reserved 03 BRKOUT O Break Output controlled by OCDS module Port 2 74 P2 0 lOO A2 Port 2 General Purpose I O Line 0 IN32 PU GPTAO Input 32 OUT32 01 GPTAO Output 32 TCLKO O2 MLIO Transmitter Clock Output 0 OUT28 O3 LTCA2 Output 28 75 P2 1 lOO A2 Port 2 General Purpose I O Line 1 IN33 PU GPTAO Input 33 TREADVOA I MLIO Transmitter Ready Input A OUT33 01 GPTAO Output 33 SLSO03 O2 SSCO Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 76 P2 2 lOO A2 Port 2 General Purpose I O Line 2 IN34 PU GPTAO Input 34 OUT34 01 GPTAO Output 34 TVALIDO O2 MLIO Transmitter Valid Output OUT29 O3 LTCA2 Output 29 Data Sheet 26 V 14 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d
3. OUT9 01 GPTAO Output 9 OUT65 02 GPTAO Output 65 OUT9 03 LTCA2 Output 9 151 P0 10 OO A2 Port 0 General Purpose I O Line 10 IN10 PU GPTAO Input 10 OUT10 01 GPTAO Output 10 TXDAO 02 E Rav Channel A transmit Data Output OUT10 O3 LTCA2 Output 10 Data Sheet 21 V 1 4 1 2014 05 Cinfineon e PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 152 P0 11 OO A2 Port0 General Purpose I O Line 11 IN11 PU GPTAO Input 11 OUT11 01 GPTAO Output 11 TXDBO 02 E Ray Channel B transmit Data Output OUT11 O3 LTCA2 Output 11 168 JPO 12 OO A2 Port 0 General Purpose I O Line 12 IN12 PU GPTAO Input 12 OUT12 O1 GPTAO Output 12 TXENA O2 SCH Channel A transmit Data Output enable OUT12 O3 LTCA2 Output 12 169 P0 13 OO A2 Port 0 General Purpose I O Line 13 IN13 PU GPTAO Input 13 OUT13 01 GPTAO Output 13 TXENB O2 EP Channel B transmit Data Output enable OUT13 O3 LTCA2 Output 13 175 JPO 14 OO A1 Port 0 General Purpose I O Line 14 IN14 PU GPTAO Input 14 REQ4 l External Request Input 4 OUT14 01 GPTAO Output 14 FCLPOC O2 MSCO Clock Output Positive C OUT14 O3 LTCA2 Output 14 176 JPO 15 OO A1 Port 0 General Purpose I O Line
4. full operation life time 24000 h is not exceeded Operating Conditions are met for pad supply levels Vppp or Vppm temperature If a pin current is out of the Operating Conditions but within the overload parameters then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed Operation is still possible in most cases but with relaxed parameters Note An overload condition on one or more pins does not require a reset Table 15 Overload Parameters Parameter Symbol Values Unit Note Min Typ Max Test Con dition Input current on any digital pin Zi 5 l 5 mA during overload condition except LVDS pins Input current on LVDS pins Zi yps 3 3 mA Absolute sum of all input Inc 20 20 mA circuit currents for one port group during overload condition Input current on analog pins Jinana 3 3 mA Absolute sum of all analog Insas 15 15 mA input currents for analog inputs of a single ADC during overload condition Absolute sum of all input Lins 100 100 mA circuit currents during overload condition 1 The port groups are defined in Table 19 Note FADC input pins count as analog pin as they are overlayed with an ADC pins Data Sheet 48 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersGeneral Parameters Table 16 PN Junction Charac
5. ns RCLK high time ta SR l 05x ns 120 RCLK low time toy SR l 05x l ns t20 RCLK rise time to SR l 4 ns RCLK fall time tog SR l 4 ns RDATA RVALID setup ts SR 42 ns time before RCLK falling edge RDATA RVALID hold time te CC 2 2 ns after RCLK falling edge RREADY output delay f CC JO 16 ns time 1 The following formula is valid t21 t22 t20 2 Min and Max values for this parameter can be derived from the typ value by considering the other receiver timing parameters 3 The RCLK max input rise fall times are best case parameters for fSYS 90 MHz For reduction of EMI slower input signal rise fall times can be used for longer RCLK clock periods Table 39 MLI Transmitter Parameter Symbol Values Unit Note Min Typ Max Test Condition TCLK clock period fg CC 2x1 ns fre TCLK high time ta CC 0 45x 0 5x 10 55x ns tio tio tio TCLK low time tp CC 0 45x 0 5x 0 55x ins tio tio tio TCLK rise time ty3CC 0 3x jns tio Data Sheet 107 V 1 4 1 2014 05 Cinfineon TC1782 Table 39 MLI Transmitter cont d Electrical ParametersAC Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition TCLK fall time Dutt Mi 0 3x ns Le TDATA TVALID output tis CC l 3 44 ns delay time TREADY setup time fg SR 18 ii ns before TCLK rising edge TREADY hold time after rt SR 2
6. MHz Charge consumption per conversion Qconv CC 70 8510 100 pc charge needs to be provided via VARE FO Data Sheet 75 V 1 4 1 2014 05 Cinfineon TC1782 Table 27 ADC Parameters cont d Electrical ParametersDC Parameters Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Input leakage at analog inputs 1674 CC 100 500 nA Vis Voom V V 0 97 x Voom V overlayed No 100 600 nA V2 0 97 x Voom V Vis Voom V overlayed Yes 500 100 nA V 0 03 x Voom V V20V overlayed No 600 100 nA V 0 03 x Voom V V20V overlayed Yes 100 200 nA Vi 0 03 x Voom V V lt 0 97 x Voom V overlayed No 100 300 nA V lt 0 97 x Voom V V gt 0 03 x Voom V overlayed Yes Input leakage current at Varef0 Ioz CC HA VaneroS Voom V Input leakage current at VagndO Toza CC HA VacnpoS Voom V ON resistance of the transmission gates in the analog voltage path Ran CC 900 1500 Ohm ON resistance for the ADC test pull down for AIN7 Rau CC 180 550 900 Ohm Data Sheet 76 V 1 4 1 2014 05 infineon TC1782 Electrical ParametersDC Parameters Table 27 ADC Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test
7. TC1782 Table 18 Operating Conditions Parameters cont d Electrical ParametersGeneral Parameters Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Core Supplv Voltage Van SR 1 235 1 3 1 365 2 SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 256F133HR SAK TC1782N 256F133HL for duration limitation see Voltage Operating Timing Profiles 1 3 1 439 V SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL for duration limitation see Voltage Operating Timing Profiles Flash supply voltage 3 3V Vopria SR 2 97 3 3 3 639 V for duration limitation see Voltage Operating Timing Profiles ADC analog supply voltage Voom SR 2 97 3 3 5 53 Data Sheet 54 V 1 4 1 2014 05 Cinfineon TC1782 Table 18 Electrical ParametersGeneral Parameters Operating Conditions Parameters cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Oscillator core supplv voltage Voposc SR 1 235 1 3 1 365 V SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 256F133HR SAK TC1782N 256F133HL for duration limitation see Voltage Ope
8. Unit Note Test Condition DNL error EF ont CC LSB Vin mode differential Gain 1 or 2 Gain 4 or 8 and Vopar VopurS 5 Vppar V pomr TYP LSB Vin mode single ended Gain 1 or 2 Gain 4 or 8 and Vopar VoourS 5 Vppar V pomel TYP LSB Vin mode differential Gain 4 or 8 and Vopar Vopur 5 Vana V pomel Typ LSB Vin mode single ended Gain 4 or 8and Vopar Vopur 5 Vppar V pomel Typ Data Sheet 81 V 1 4 1 2014 05 Cinfineon TC1782 Table 29 FADC Parameters cont d Electrical ParametersDC Parameters Parameter Svmbol Values Min Tvp Max Unit Note Test Condition GRADient error EF rap CC 5 Vin mode differential Gains 4 5 Vin mode single ended Gains 4 Vin mode differential Gain 8 Vin mode single ended Gain 8 INL error EF n CC LSB Vin mode differential LSB Vin mode single ended Offset error EF ofr CC 90 mV Vin mode differential Calibrationz No 90 mV Vin mode single ended Calibrationz No 20 mV Vin mode differential Calibration Ye s 9 20 mV Vin mode single ended Calibration Ye s 9 Error of commen mode voltage Vearer 2 EF rer CC 60 mV Channel amplifier cutoff fregue
9. Io lt 2 MA N MOS Fall time pad type A1 tear CC 150 ns C 7 20 pF pin Out driver weak 50 ns C 50 pF pin out driver medium 140 ns C z 150 pF pin out driver medium 550 ns C z 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet 60 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 21 Standard Pads Class A1 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Rise time pad type A1 tra CC 150 ns C 20 pF pin out driver weak 50 ns Cu 50 pF pin out driver medium 140 ns C 7 150 pF pin out driver medium 550 ns C 7 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Input high voltage class Vint 06x min V V A1 pads SR Voop DDP 0 3 3 6 Input low voltage class A1 Vi 44 SR l 0 3 0 36x V pads Mons Data Sheet 61 V 1 4 1 2014 05 Cinfineon TC1782 Table 21 Electrical ParametersDC Parameters Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Output voltage high class A1 pads Vous CC Vopr 0 4 Io 1 4 mA pin ou
10. Tvp Max Unit Note Test Condition LMB frequencv fims CC 133 MH N SAK TC1782N 256F133HR SAK TC1782N 256F133HL 180 MHz SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL 160 MH N SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Data Sheet 52 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersGeneral Parameters Table 18 Operating Conditions Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition PCP Frequency fece SR 133 MHz SAK TC1782N 256F133HR SAK TC1782N 256F133HL 180 MHz SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL 160 MHz SAK TC1782F 320F 160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Inactive device pin ID SR 1 1 mA All power supply current voltages Vppx O Short circuit current of s SR 5 5 mA digital outputs Absolute sum of short Z spp 100 mA circuit currents of the CC device Absolute sum of short X sc pe 20 mA circuit currents per pin CC group Ambient Temperature T SR 40 125 C Junction temperature T SR l 40 150 C Data Sheet 53 V 1 4 1 2014 05 Cinfineon
11. 145 P0 0 OO A1 Port 0 General Purpose I O Line 0 INO PU GPTAO Input 0 INO l LTCA2 Input 0 HWCFGO l Hardware Configuration Input 0 OUTO 01 GPTAO Output 0 OUT56 O2 GPTAO Output 56 OUTO O3 LTCA2 Output 0 146 P0 1 OO A1 Port 0 General Purpose I O Line 1 IN1 PU GPTAO Input 1 IN l LTCA2 Input 1 SDI1 l MSCO Serial Data Input 1 HWCFG1 l Hardware Configuration Input 1 OUT1 01 GPTAO Output 1 OUT57 O2 GPTAO Output 57 OUT1 O3 LTCA2 Output 1 147 P02 OO A1 Port 0 General Purpose I O Line 2 IN2 PU GPTAO Input 2 IN2 l LTCA2 Input 2 HWCFG2 l Hardware Configuration Input 2 OUT2 01 GPTAO Output 2 OUT58 O2 GPTAO Output 58 OUT2 O3 LTCA2 Output 2 Data Sheet 19 V 14 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 148 P0 3 1 00 A1 Port 0 General Purpose I O Line 3 IN3 PU GPTAO Input 3 IN3 l LTCA2 Input 3 HWCFG3 l Hardware Configuration Input 3 OUT3 01 GPTAO Output 3 OUT59 O2 GPTAO Output 59 OUT3 O3 LTCA2 Output 3 166 P0 4 lOO A1 Port 0 General Purpose I O Line 4 INA PU GPTAO Input 4 IN4 l LTCA2 Input 4 HWCFG4 l Hardware Configuration Input 4 OUT4 01 GPTAO Output 4 OUT60 O2 GPTAO Out
12. ASCO Receiver Input A Async amp Sync Mode RXDOA 01 ASCO Output Sync Mode RXDOA O2 ASCO Output Sync Mode OUT84 03 GPTAO Output 84 135 P3 1 OO A1 Port 3 General Purpose I O Line 1 TXDO o1 JPU asco Output TXDO 02 ASCO Output OUT85 O3 GPTAO Output 85 129 P32 OO JA14 Port 3 General Purpose I O Line 2 SCLKO PU sscoclock Input Slave Mode SCLKO O1 SSCO Clock Output Master Mode SCLKO O2 SSCO Clock Output Master Mode OUT86 03 GPTAO Output 86 130 P3 3 OO JA14 Port 3 General Purpose I O Line 3 MRSTO l PU SSCO Master Receive Input Master Mode MRSTO 01 SSCO Slave Transmit Output Slave Mode MRSTO O2 SSCO Slave Transmit Output Slave Mode OUT87 O3 GPTAO Output 87 Data Sheet 29 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 132 P3 4 lOO A2 Port 3 General Purpose I O Line 4 MTSRO l PU sscoSlave Receive Input Slave Mode MTSRO 01 SSCO Master Transmit Output Master Mode MTSRO O2 SSCO Master Transmit Output Master Mode OUT88 03 GPTAO Output 88 126 P3 5 OO A1 Port 3 General Purpose I O Line 5 SLSO00 o1 PU ssco Slave Select Output 0 SLSO10 O2 SSC1 Slave Select Output 0 SLSOANDOO 03 SSCO AND SSC1
13. Note Min Typ Max TeSt Con dition Storage temperature Tst SR 65 150 Voltage at 1 3 V power supply Vbo SR 2 0 pins with respect to Vss Voltage at 3 3 V power supply Vopp 4 33 pins with respect to Vss SR Voltage at 5 V power supply Vopy SR 7 0 pins with respect to Vss Voltage on any Class A input Vn SR 0 6 Vppp 0 7 Whatever pin and dedicated input pins or max 4 33 is lower with respect to Vss Voltage on any Class D Vain 0 6 7 0 analog input pin with respect Varero to Vacnoo SR Voltage on any shared Class Var 0 6 7 0 D analog input pin with SR respect to Vsgar if the FADC is switched through to the pin Input current on anv pin Tin 10 10 mA during overload condition Absolute maximum sum ofall Ziq 25 25 mA input circuit currents for one port group during overload condition Absolute maximum sum of all Ziw Mi 1200 mA input circuit currents during overload condition 1 The port groups are defined in Table 19 Data Sheet 47 V 1 4 1 2014 05 Cinfineon es Electrical ParametersGeneral Parameters 5 1 4 Pin Reliabilitv in Overload When receiving signals from higher voltage devices low voltage devices experience overload currents and voltages that go bevond their own IO power supplies specification Table 15 defines overload conditions that will not cause anv negative reliabilitv impact if all the following conditions are met
14. Page Products http www infineon com products 5 4 3 Flash Memory Parameters The data retention time of the TC1782 s Flash memory depends on the number of times the Flash memory has been erased and programmed Data Sheet 115 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersPackage and Reliabilitv Table 45 FLASH32 Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition Data Flash Erase Time fern CC 3 s per Sector Program Flash Erase terp CC l 5 S Time per 256 KByte Sector Program time data flash fppRp CC x 5 3 ms without per page reprogramming 15 9 ms with two reprogramming cycles Program time program tprp CC 5 3 ms without flash per page reprogramming 10 6 ms with one reprogramming cycle Data Flash Endurance Ng CC 60000 cycle Min data 4 S retention time 5 years Erase suspend delay Io ErSusp 15 ms Wait time after margin FL Margin 10 HS change Del CC Program Flash Retention tac CC 20 year Max 1000 Time Physical Sector S erase program cycles Program Flash Retention fker CC 20 year Max 100 Time Logical Sector s erase program cycles UCB Retention Time ien CC 20 year Max 4 S erase program cycles per UCB Wake Up time twy CC 270 HS Data Sheet 116 V 1 4 1 2014 05 Cinfineon TC1782 Elec
15. Pin Symbol Ctrl Type Function 77 P2 3 OO A2 Port 2 General Purpose I O Line 3 IN35 PU GPTAO Input 35 OUT35 01 GPTAO Output 35 TDATAO O2 MLIO Transmitter Data Output OUT30 O3 LTCA2 Output 30 78 P2 4 lOO A2 Port 2 General Purpose I O Line 4 IN36 PU GPTAO Input 36 RCLKOA l MLI Receiver Clock Input A OUT36 01 GPTAO Output 36 OUT36 O2 GPTAO Output 36 OUT31 O3 LTCA2 Output 31 79 P2 5 lOO A2 Port 2 General Purpose I O Line 5 IN37 PU GPTAO Input 37 OUT37 O1 GPTAO Output 37 RREADYOA 02 MLIO Receiver Ready Output A OUT110 O3 LTCA2 Output 110 80 P2 6 lOO A2 Port2 General Purpose I O Line 6 IN38 PU GPTAO Input 38 RVALIDOA l MLI Receiver Valid Input A OUT38 01 GPTAO Output 38 OUT38 O2 GPTAO Output 38 OUT111 O3 LTCA2 Output 111 81 P2 7 lOO A2 Port 2 General Purpose I O Line 7 IN39 PU GPTAO Input 39 RDATAOA l MLI Receiver Data Input A OUT39 01 GPTAO Output 39 OUT39 O2 GPTAO Output 39 Reserved O3 Data Sheet 27 V 14 1 2014 05 Cinfineon e PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 164 P2 8 lOO A2 Port 2 General Purpose I O Line 8 SLSO04 o1 PU ssco Slave Select Output 4 SLSO14 O2 SSC1 Slave Select Output 4 ENOO O3 MSCO Enable Output
16. Table 34 PLL SysCIk Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Accumulated Jitter DpCC 7 7 ns PLL base frequency puBase 90 200 320 MHZ CC VCO input frequencv Joer CC 8 16 MHz VCO frequency range fuco CC 400 720 MHz PLL lock in time t CC 14 200 HS N gt 32 14 400 HS N lt 32 Phase Locked Loop Operation When PLL operation is enabled and configured the PLL clock fyco and with it the LMB Bus clock fi mg is constantly adjusted to the selected frequency The PLL is constantly adjusting its output frequency to correspond to the input frequency from crystal or clock source resulting in an accumulated jitter that is limited This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle This is especially important for bus cycles using wait states and for the operation of timers serial interfaces etc For all slower operations and longer periods e g pulse train generation or measurement lower baudrates etc the deviation caused by the PLL jitter is negligible Two formulas are defined for the absolute approximate maximum value of jitter Dn in ns dependent on the K2 factor the LMB clock frequency fimg in MHz and the number m of consecutive fi ye clock periods for K2 s 100 and m lt fi 4g MHz 2 i 740 g L 0 01 x K2 x m 1 l 6 E RS 5 x f us MH
17. wc Qnfineon Never stop thinking 32 Bit Microcontroller TC1782 32 Bit Single Chip Microcontroller Data Sheet V 1 4 1 2014 05 Microcontrollers Edition 2014 05 Published bv Infineon Technologies AG 81726 Munich Germanv 2014 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that devic
18. 0 160 P2 9 lOO A2 Port2 General Purpose I O Line 9 SLSO05 o1 JPU ssco Slave Select Output 5 SLSO15 O2 SSC1 Slave Select Output 5 ENO1 O3 MSCO Enable Output 1 161 P2 10 OO A1 Port 2 General Purpose I O Line 10 MRST1A PU Issc1 Master Receive Input A IN10 l LTCA2 Input 10 MRST1A O1 SSC1 Slave Transmit Output OUTO 02 LTCA2 Output 0 Reserved O3 162 P2 11 OO A1 Port 2 General Purpose I O Line 11 SCLK1A PU Issc1 Clock Input A IN11 l LTCA2 Input 11 SCLK1A 01 SSC1 Clock Output A OUT 02 LTCA2 Output 1 FCLPOB O3 MSCO Clock Output Positive B 163 P2 12 OO A1 Port 2 General Purpose I O Line 12 MTSR1A PU SC1 Slave Receive Input A IN12 l LTCA2 Input 12 MTSR1A 01 SSC1 Master Transmit Output A OUT2 O2 LTCA2 Output 2 SOPOB O3 MSCO Serial Data Output Positive B Data Sheet 28 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 165 P2 13 00 A1 Port 2 General Purpose I O Line 13 SLSI11 PU ssc1 Slave Select Input 1 SDIO l MSCO Serial Data Input 0 IN13 l LTCA2 Input 13 OUT3 01 LTCA2 Output 3 Reserved O2 Reserved O3 Port 3 136 P3 0 OO JA14 Port 3 General Purpose I O Line 0 RXDOA PU
19. F000 0464 BA SCU_CHIPID 9400 9410 F000 0640 BA SCU_MANID 0000 1820 F000 0644 BA SCU_RTID 0000 0000 F000 0648 BA Table 8 SAK TC1782N 256F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 F000 0464 BA SCU_CHIPID 1400 9410 F000 0640 BA SCU_MANID 0000 1820 FOOO 0644 BA SCU_RTID 0000 0000 F000 0648 BA Table 9 SAK TC1782F 320F160HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 FOOO 0464 BA SCU_CHIPID A500 93104 F000 0640 BA SCU MANID 0000 1820 FOOO 0644 BA SCU RTID 0000 0000 F000 0648 BA Data Sheet 43 V 1 4 1 2014 05 Cinfineon TC1782 Identification Registers Table 10 SAK TC1782F 320F160HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 F000 0464 BA SCU_CHIPID 2500 9310 F000 0640 BA SCU_MANID 0000 1820 F000 0644 BA SCU_RTID 0000 0000 F000 06484 BA Table 11 SAK TC1782N 320F160HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 F000 0464 BA SCU_CHIPID A500 94104 F000 0640 BA SCU_MANID 0000 1820 FOOO 0644 BA SCU_RTID 0000 0000 F000 0648 BA Table 12 SAK TC1782N 320F160HL Identification Registers Short Name
20. Memory Parameters 5 115 5 4 4 OualityDeclarations 5 117 6 Histoly ETT 6 119 Data Sheet l 2 V 1 4 1 2014 05 Cinfineon TENE Data Sheet 3 V 1 4 1 2014 05 Cinfineon TENE Data Sheet 4 V 1 4 1 2014 05 Cinfineon PS 1 Summarv of Features Summary of Features The SAK TC1782F 320F180HR SAK TC1782F 320F180HL has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 180 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 180 MHz operation at full temperature range Multiple on chip memories 2 5 Mbyte Program Flash Memory PFLASH with ECC 128 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 128 Kbyte Data Memory LDRAM Instruction Cache up to 16 Kbyte ICACHE configurable 40 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure
21. OUT 30 OUT35 IN35 P 2 3 d 77 OUT 31 OUT 36 RCLK OAI TVALIDO A OUT 29 OUT34 I N34 P2 2 76 OUT38 O UTI 11 RVAL IDOA OUT 52 OUT 28 INS2 IN2 8IRXDCAN2 P4 0 c 86 OUTS 3 0 UT29 IN5 3l N29 TXDCAN2 P4 1 487 EXT CLK 1 0 UTS 4 0 UT30 N 54 1N30 P4 2 EH 88 Data Sheet 17 V 1 4 1 2014 05 infineon e PinningTC1782 Pin Configuration ga a EE a 55 sa S 5 DIER e G El care B5 soge 8858 g FI ad Sore FERRE e E 585 888 ask 5555 88 25 BLO SZzga99900 oooo Ex Bx BISS ze mp pare s5 ee Ergo EE 5555 22 zz ESCH Torte EE Poooo f ER 988 928203333 58828588 88 88 EECH Aare98222 o9O00OL x DER ggau SE QROQQ u EIER 55 S55ereRE Bee EXEREE cess 329953388 5zzzzopg seiseg S ZE EE SizriBBE SESLER zzz2 azZZZ39955 222z2000 202200 LEFT anssazzzz 222225882 080038 meno Bree ege eet Ee sass diil de se S3352555B9882529555 Sana FEER ER DESEE Ed oo m sew PERE SegsBus fix Sbss SLSCO20 JOUT 40 OUT 8IIN 40 IN26 P5 0 SLSCO21 OUT 41 OUT 9IIN 41 IN27 P5 1 SLSCO 22 OUT42 OUT 10 IN 42 IN28 P5 2 SLSCO 23 0UT4310UT11 1N43 P53 SLSCO24 OUT 44 IOUT 12 SLSI2A IN 44 IN29 P5 4 MRST2A OUT45 OUT 13 IN 45 IN30 P55 gt P36 SLS001 SLSO 11 SLSO01 8SLSO 11 MTSR2 A OUT 46 0UT 44 IN 46 IN31 P56 l 7 P35 SLSO00 SLSO 10 SLSO 00 8SLSO 10 SCLK2 OUT47 0UT 18 IN47 P5 7 Eve 2 P34 0UT88 MTSR l 7 P37 SLSI01 OUT 89 SLS002 SLSO 12 P3 3 OUT87 IMRSTO P3 2 0UT 86 ISCLKO P38 SLS006 OUT 9
22. Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 F000 0464 BA SCU_CHIPID 2500 9410 F000 0640 BA SCU_MANID 0000 1820 FOOO 0644 BA SCU_RTID 0000 0000 F000 06484 BA Data Sheet 44 V 1 4 1 2014 05 Cinfineon es Electrical ParametersGeneral Parameters 5 Electrical Parameters This specification provides all electrical parameters of the TC1782 5 1 General Parameters 5 1 1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1782 and partly its requirements on the system To aid interpreting the parameters easily when evaluating them for a design they are marked with an two letter abbreviation in column Symbol CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1782 and must be regarded for a system design e SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1782 designed in Data Sheet 45 V 1 4 1 2014 05 Cinfineon 5 1 2 TC1782 Electrical ParametersGeneral Parameters Pad Driver and Pad Classes Summarv This section gives an overview on the different pad driver classes and its basic characteristics More details mainlv DC parameters are defined in the Section 5 2 1 Table 13 Pad Driver and Pad Classes Overview Class Power Type Sub Class Speed Load Leakage Termination Su
23. Vop1 3 and Varer power supplies and the oscillator have reached stable operation within the normal operating conditions 2 At normal power down the PORST signal should be activated within the normal operating range and then the power supplies may be switched off Care must be taken that all Flash write or delete sequences have been completed 3 At power fail the PORST signal must be activated at latest when any 3 3 V or 1 3 V power supply voltage falls 1296 below the nominal level If under these conditions the PORST is activated during a Flash write only the memory row that was the target of the write at the moment of the power loss will contain unreliable content In order to ensure clean power down behavior the PORST signal should be activated as close as possible to the normal operating voltage range 4 In case of a power loss at any power supply all power supplies must be powered down conforming at the same time to the rules number 2 and 4 5 Although not necessary it is additionally recommended that all power supplies are powered up down together in a controlled way as tight to each other as possible 6 Additionally regarding the ADC reference voltage Varer Varer Must power up at the same time or later then Vppy and Varer must power down either earlier or at latest to satisfy the condition Varer lt Voom 0 5 V This is required in order to prevent discharge of Varep filter capacitance through the ESD diodes thr
24. an asymmetry of rising and falling edges of f 42 tra2l lt 1 ns 4 Limits of 966ns and 1046 1ns correspond to 30 70 Vppp FlexRay standard input thresholds For input thresholds of this product a correction of 0 5 ns and 0 1 ns has to be applied Data Sheet 112 V1 4 1 2014 05 infineon es Electrical ParametersAC Parameters 5 Valid for output slopes of the bus driver of dRxSlope x 5ns 20 Vppp to 80 Mos according to the FlexRay Electrical Physical Layer Specification V2 1B For A2 pads the rise and fall times of the incoming signal have to satisfy the following inequality 1 6ns lt frag fraz lt 1 3ns BSS Last CRC Byte FES Byte Start Sequence Frame End Sequence tsample TXD BSS Last CRC Byte FES Byte Start Sequence Frame End Sequence ERAY_TIMING Figure 25 ERAY Timing Data Sheet 113 V 1 4 1 2014 05 infineon TC1782 Electrical ParametersPackage and Reliabilitv 54 Package and Reliabilitv 5 4 1 Package Parameters Table 43 Thermal Characteristics of the Package Device Package Rojcr Roycs Roylead Unit Note TC1782 PG LQFP 176 8 1 0 3 30 9 K W with soldered 10 PG LQFP exposed pad 2 176 20 TC1782 PG LQFP 176 18 1 12 6 30 9 K W with not soldered 10 PG LQFP exposed pad 176 20 1 The top and bottom thermal resistances between the case and the ambient R rcar Rtcag are to be co
25. and specified by crystral suppliers 2 If the XTAL1 pin is driven by a crystal reaching a minimum amplitude peak to peak of 0 4 Vpposca is necessary 3 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Note It is strongly recommended to measure the oscillation allowance negative resistance in the final target system layout to determine the optimal parameters for the oscillator operation Please refer to the limits specified by the crystal or ceramic resonator supplier Data Sheet 85 V 1 4 1 2014 05 Cinfineon TC1782 5 2 5 Temperature Sensor Table 31 DTS Parameters Electrical ParametersDC Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition Measurement time t CC l 100 HS Temperature sensor Tsp SR l 40 150 C range Sensor Accuracy Trsa CC 6 6 C calibrated Start up time after resets fresr SR 20 HS inactive The following formula calculates the temperature measured by the DTS in C from the RESULT bit field of the DTSSTAT register Data Sheet Tj 2 03 86 DTSSTATRESULT 596 1 V 1 4 1 2014 05 Cinfineon ses Electrical ParametersDC Parameters 5 2 6 Power Supply Current The total power supply current defined below consists of leakage and switching componen
26. fapc time without post calibration The power up calibration of the ADC requires a maximum number of 4352 fpc cycles Analog Input Circuitry AIN On Canror i Cansw Cansw Reference Voltage Input Circuitry Her On C I AREFTOT C AREFSW Carta Analog InpRefDiag Figure 7 ADCx Input Circuits Data Sheet 78 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters loz1 500nA 4 200nA L 100nA Single ADC Input Vin Vppm gt 100nA1 500nA loz1 600nA 4 300nA L 100nA 100nA1 600nA 396 97 100 Overlayed ADC FADC Input Vin Vppm gt 396 97 100 Figure 8 Data Sheet ADCx Analog Inputs Leakage 79 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters 5 2 3 Fast Analog to Digital Converter FADC Table 29 FADC Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition Input current at VFAREF Jeaper 120 HA CC Input leakage current at roz 500 500 nA Vearer lt Vopme VFAREF CC V Veaner 0 V Input leakage current at Joss 500 500 nA VFAGND CC Data Sheet 80 V 1 4 1 2014 05 Cinfineon Table 29 TC1782 FADC Parameters cont d Electrical ParametersDC Parameters Parameter Svmbol Values Min Tvp Max
27. for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality One FlexRay module with 2 channels E Ray Data Sheet 7 V 1 4 1 2014 05 Cinfineon PS Summarv of Features One General Purpose Timer Arrav Module GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management e 32 analog input lines for ADC 2 independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fkap clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 86 digital general purpose I O lines GPIO 4 input lines Digital I O ports with 3 3 V capabilitv On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1782ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 8 V 1 4 1 2014 05 Cinfineon PS Summarv of Features The SAK TC1782N 320F160HR SAK TC1782N 320F160HL has the fo
28. from last SCLK ts CC 7 x ns latching edge MRST delay from SCLK fg CC JO 16 5 ns shift edge SLSI to valid data on tg CC l 16 5 ns MRST 1 SCLK signal rise fall times are the same as the rise fall times of the pad TSSCmin TSYS 1 fSYS SCLK signal high and low times can be minimum 1xTSSC Fractional divider switched off SSC internal baud rate generation used For CON PH 1 slave select must not be removed before the following shifting edge This mean that what ever is configured shifting latching first SLSI must not be de actived before the last trailing edge from the pair of shifting latching edges Data Sheet 110 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersAC Parameters SCLK 2 MTSR 1 This timing is based on the following setup CON PH CON PO 0 2 The transition at SLSOn is based on the following setup SSOTC TRAIL 0 and the first SCLK high pulse is in the first one of a transmission SSC TmgMM Figure23 SSC Master Mode Timing La sa j First latchil Last latchii SCLK s SCLK edge Ni a ss bs gt ts 1 This timing is based on the following setup CON PH CON PO 0 SSC_TmgSM Figure 24 Data Sheet SSC Slave Mode Timing 111 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 8 4 ERAY Interface Timing The timings
29. increase If the reference voltage is reduced by the factor k k 1 TUE DNL INL Gain and Offset errors increase also by the factor 1 k If the analog reference voltage is gt Vbpm then the ADC converter errors increase For 10 bit conversions the error value must be multiplied with a factor 0 25 For 8 bit conversions the error value must be multiplied with a factor 0 0625 For a conversion time of 1 us a rms value of 85pA result for 4 ecco The leakage current definition is a continuos function as shown in figure ADCx Analoge Input Leakage The numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function Data Sheet 77 V 1 4 1 2014 05 Cinfineon ses Electrical ParametersDC Parameters 12 13 14 15 Measured without noise For 10 bit conversion the TUE is 2LSB for 8 bit conversion the TUE is 1LSB A running conversion may become inexact in case of violating the normal conditions voltage overshoot If the reference voltage Varerg increase or the Vppy decrease so that Varer Voom 0 05V to Vppy 0 07V then the accuracy of the ADC decrease by 4LSB12 Table 28 Conversion Time Operating Conditions apply Parameter Symbol Values Unit Note Conversion te CC 2x Tapc 44 STC n x Tang us n 7 8 10 12 for time with n bit conversion post calibration Tape 1 fepi Conversion 2x Tanc 2 STC n x Tape Tanai 1
30. of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with C 25 pF The ERAY interface is only available for the SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782F 320F133HR SAK TC1782F 320F 133HL Table 42 ERAY Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Time span from last BSS Iren CC 997 75 1002 2 ns to FES without the 5 influence of quartz tolerancies d10Bit TX TxD data valid from 1647162 1 5 ns Asvmmetrical fsample flip flop xd reg CC delav of rising TxDA TxDB and falling edge dTxAsym 9 TxDA TxDB Time span between last re SR 966 1046 1 ns BSS and FES without influence of quartz tolerancies d10Bit RX 99 RxD capture by fsample 164 165 i x 3 0 ns Asymmetrical RxDA RxDB sampling CC delav of rising flip flop dRxAsym and falling edge RxDA RxDB TxD data delay from dTxdly 10 0 ns Px PDR PDy sampling flip flop CC 000 15 0 ns Px PDR PDy 001 RxD capture delay by dRxdly 10 00 ns sampling flip flop CC 1 This includes the PLL ERAY accumulated jitter 2 Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers Quarz tolerance and PLL ERAY accumulated jitter are not included 3 E Rav TxD output drivers have
31. protocol state 2 The Host has to find a suitable sampling point by analyzing the sync telegram response 0 9 Voor 1 Vis MC DAPO Figure 18 Test Clock Timing DAPO Data Sheet 104 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters AJANA DAPO he ti DAP1 MC DAP1 RX Figure 19 DAP Timing Host to Device MC DAP1 TX Figure 20 DAP Timing Device to Host Data Sheet 105 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 8 Peripheral Timings Note Peripheral timing parameters are not subject to production test Thev are verified bv design characterization 5 3 8 1 Micro Link Interface MLI Timing MLI Transmitter Timing ta ta 0 TCLKx TDATAx TVALIDx TREADVx MLI Receiver Timing bs b 0 RCLKx RDATAx RVALIDx RREADYx MLI_Tmg_2 vsd Figure 21 MLI Interface Timing Note The generation of RREADY x is in the input clock domain of the receiver The reception of TREADYx is asynchronous to TCLKx Data Sheet 106 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersAC Parameters The MLI parameters are vaild for C 50 pF and for strong driver medium edge Table 38 MLI Receiver Parameter Symbol Values Unit Note Min Typ Max Test Condition RCLK clock period to SR 1 fp
32. shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality Data Sheet 9 V 1 4 1 2014 05 Cinfineon PS Summarv of Features One General Purpose Timer Arrav Module GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management e 32 analog input lines for ADC 2 independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fkap clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 86 digital general purpose I O lines GPIO 4 input lines Digital I O ports with 3 3 V capabilitv On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1782ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or t
33. type A1 tears CC 150 ns C 20 pF pin out driver weak 28 ns C 50 pF edge slow pin out driver strong 16 ns C 7 50 pF edge soft pin out driver strong 50 ns C z 50 pF pin out driver medium 140 ns C z 150 pF pin out driver medium 550 ns C z 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet 63 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 22 Standard Pads Class A1 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Rise time pad type A1 fon CC 150 ns C 7 20 pF pin out driver weak 28 ns Ce 50 pF edge slow pin out driver strong 16 ns C 50pF edge soft pin out driver strong 50 ns C 7 50 pF pin out driver medium 140 ns C z 150 pF pin out driver medium 550 ns C z 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Input high voltage Class Vina 0 6x min V V A1 pads SR Vppp DDP 0 3 3 6 Input low voltage Class Vra 0 3 0 36x IV A1 pads SR Vope Ratio Vil Vih A1 pads Via s 0 6 Vinat CC Data Sheet 64
34. 0 TXD1 O TCLKO OUT95 P5 15 Vos od E Vo Voor gt ESRO Ves E PORST RDATAQB OUT 89 P 5 8 2 ESR RVALIDO B OUT 90 P 5 9 P 1 1 IN17 0UT 17 OUT 73 RREADVOB OUT91 P5 10 RCLKOB OUT92 P5 11 TDATAO SLSO 07 OUT93 P 5 12 TVALIDOB SLSO 16 P5 13 TREADWB OUT94 P5 14 van E TC1782 TESTMODE P1 15 BRKINIBRKOUT gt PI 0 IN16 OUT 16 OUT 72 BRKINIBRKOUT AN30 AN29 99 AN28 98 AN7 97 AN27 96 AN26 95 JE P1 9 IN25 IN49 IMRSTI B OUT 25 OUT 49 AN25 94 2 P 1 8 IN24 IN48 MT SRI B OUT 24 OUT 48 AN24 88 P1 2 IN18 OUT 18 OUT 74 AN23 92 AN22 9t ANZI 89 P4 3 1N31 IN55 OUT 31 OUT 55 EXTCLKO wen q Du SESRZZBZS2 3 385 HigiiHi s s EE 829 322383305502 bor wuwwsbzsQQFa Sse 3333085553 amp z SAK TC1782N 320F180HR RE 323 SAK TC1782N 320F180HL am e ef SAK_TC1782N 320F160HR 2 825 SAK TC1782N 320F160HL 2 SAK TC1782N 320F133HR SAK TC1782N 320F133HL Figure 6 SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL SAK TC1782N 256F133HR SAK TC1782N 256F133HL Pinning Data Sheet 18 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package Pin Symbol Ctrl Type Function Port 0
35. 0HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL 3709 mA power pattern realistic SAK TC1782N 256F133HR SAK TC1782N 256F133HL Vpp 1 326 V 398 mA power pattern realistic SAK TC1782F320F180HR SAK TC1782F320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL Vop 1 326 V 386 mA power pattern realistic SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Vpp 1 326 V Ipp current at PORST Low I DD_PORS 7 300 mA CC 291 mA Vop 1 326 V 314 mA Vop 1 43 V Analog core supply current Ippar CC 23 mA Data Sheet 88 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 32 Power Supplv Parameters cont d Parameter Svmbol Values Unit Note Test Condition Min Typ Max Oscillator core Ipposc_ 4 mA supply current CC ppp current at ppp por 2 5 mA PORST Low sr CC ppp current no Ippp CC e lppe p mA including flash read current pad activity orst LVDS off 12 EE lppe p mA including flash programming ORST current 9 27 Es lppe p mA including flash erase current ORST 8 207 Flash memory Jppri3 E 56 mA flash read current 5 current cc 21 mA flash programming current 9 56 mA flash erase current 9 Oscillator Ipposca i 15 mA power sup
36. 0HL to SAK TC1782F 320F180HR SAK TC1782F 320F180HL change SAK TC1782 256F133HR SAK TC1782 256F133HL to SAK TC1782F 256F133HR SAK TC1782F 256F133HL add information for the following products SAK TC1782N 320F180HR Data Sheet 120 V 1 4 1 2014 05 Cinfineon es Historv SAK TC1782N 320F180HL SAK TC1182N 320F180HR SAK TC1182N 320F180HL SAK TC1782N 256F133HR SAK TC1782N 256F133HL SAK TC1182N 256F133HR SAK TC1182N 156F133HL The following changes where done between Version 1 0 and 1 1 of this document add section Pin Reliability in Overload remove sentence Exposure to conditions within the maximum ratings will not affect device reliability To replace this sentence section Pin Reliability in Overload was added increase values for absolute maximum parameters Ju and Sum y remove capacitance conditions for LVDS pad parameters as loads are defined by interface MSC timings remove term typical from load of Peripheral Timings e add definition of driver strength settings for ERAY Interface Timing change footnote 4 wording for ERAY timing back to TC1797 wording increase flash parameters fppp and fppp values rework the 3 3 V current part of the Power Supply Parameters for better description and usage Parameters Ippp rp Jon se and ppp ap are removed and replaced in the following way ppp pp is replaced by Ippp with the condition including flash programming curr
37. 15 IN15 PU GPTAO Input 15 REQ5 l External Request Input 5 OUT15 01 GPTAO Output 15 SOPOC O2 MSCO Serial Data Output Positive C OUT15 O3 LTCA2 Output 15 Port 1 Data Sheet 22 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 116 P1 0 O00 A2 Port 1 General Purpose I O Line 0 IN16 PU GPTAO Input 16 BRKIN l Break Input OUT16 01 GPTAO Output 16 OUT72 O2 GPTAO Output 72 OUT16 O3 LTCA2 Output 16 BRKOUT Oo Break Output controlled by OCDS module 119 P1 1 lOO A1 Port 1 General Purpose I O Line 1 IN17 PU GPTAO Input 17 OUT17 01 GPTAO Output 17 OUT73 O2 GPTAO Output 73 OUT17 O3 LTCA2 Output 17 93 P1 2 00 A1 Port 1 General Purpose I O Line 2 IN18 PU GPTAO Input 18 OUT18 01 GPTAO Output 18 OUT74 O2 GPTAO Output 74 OUT18 O3 LTCA2 Output 18 98 P1 3 1 00 A1 Port 1 General Purpose I O Line 3 IN19 PU GPTAO Input 19 IN19 l LTCA2 Input 19 OUT19 01 GPTAO Output 19 OUT75 O2 GPTAO Output 75 OUT19 O3 LTCA2 Output 19 107 P1 4 OO A1 Port 1 General Purpose I O Line 4 IN20 PU GPTAO Input 20 IN20 l LTCA2 Input 20 EMGSTOP l Emergency Stop Input OUT20 01 GPTAO Output 20 OUT76 02 GPTAO Ou
38. 18 MHz Remove parameter xinrr covered by RAwz Replace parameter hrer by Oconv Changed typical value of Ran from 700 to 900 Ohm Add parameter ts Add footnote to max value of TUE Add parameter feapc Add parameter fc Add formula for DTS temperature calculation Adapt current values to reduced limits of BA step Add clarification to parameter June Remove parameter R74 not required Add clarification to parameter tp description Add clarification to parameter fpos description Add min value to parameters t Changed typical value of fp Base eray from 200 to 250 MHz Add MSC 145 behavior for CMOS LVDS usage Add R44 for non soldered exposed pad Add table 33 Change DTS accuracy to 6 C of the complete temperature range Remove limitations of the DFLASH and PFLASH operating in extended Range operating conditions Change package version von PG LQFP 176 6 to PG LQFP 176 12 The following changes where done between Version 0 8 and 1 0 of this document Change package version von PG LQFP 176 12 to PG LQFP 176 10 Data Sheet 119 V 1 4 1 2014 05 Cinfineon es Historv improve description in table 2 for analog channels add class A1 to type list of table 2 add clarification that table 7 defines the conditions for all other parameters add note the spike filter is only available for the PORST pin add Vil to Vih ratio for A1 pad remove irritating Note Test Conditions adapt maximum power dissipation va
39. 2 O3 SSC2 Clock Output Master Mode Data Sheet 34 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 13 P5 8 OO A2 Port 5 General Purpose I O Line 8 RDATAOB JI PU MLIO Receiver Data Input B Reserved O1 TXDA1 02 E Ray Channel A transmit Data Output OUT89 O3 LTCA2 Output 89 14 P5 9 lOO A2 Port 5 General Purpose I O Line 9 RVALIDOB JI PU MLIO Receiver Data Valid Input B Reserved O1 TXDB1 02 E Ray Channel B transmit Data Output OUT90 O3 LTCA2 Output 90 15 P5 10 OO A2 Port 5 General Purpose I O Line 10 RREADYOB 01 JPU MLIO Receiver Ready Input B TXENA O2 prey Channel A transmit Data Output enable OUT91 03 LTCA2 Output 91 16 P5 11 OO A2 Port 5 General Purpose I O Line 11 RCLKOB PU MLIO Receiver Clock Input B Reserved O1 TXENB O2 ER Channel B transmit Data Output enable OUT92 O3 LTCA2 Output 92 17 P5 12 OO JA14 Port 5 General Purpose I O Line 12 TDATAQ 01 JPU MLlo Transmitter Data Output SLSO07 02 SSCO Slave Select Output 7 OUT93 O3 LTCA2 Output 93 18 P5 13 OO JA14 Port 5 General Purpose I O Line 13 TVALIDOB Loi PU MLIO Transmitter Valid Input B SLSO16 O2 SSC1 Slave Select Output 6 Reser
40. 3 and V ssosc iS limited to a peak to peak voltage of Vpp 100 mV for noise frequencies below 300 KHz and Vpp 40 mV for noise frequencies above 300 KHz These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes Data Sheet 101 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface The JTAG module is fullv compliant with IEEE1149 1 2000 Note These parameters are not subject to production test but verified bv design and or characterization Table 36 JTAG Interface Timing Parameters Operating Conditions applv Parameter Svmbol Values Unit Note Min Tvp Max Test Condition TCK clock period ti SR 25 ns TCK high time t SR 10 ns l TCK low time tz SR 10 ns TCK clock rise time t SR 4 ns TCK clock fall time ts SR 4 ns TDI TMS setup tg SR 6 ns to TCK rising edge TDI TMS hold t SR 6 ns after TCK rising edge TDO valid after TCK falling tg CC 13 ns C 50 pF edge propagation delay tg CC 3 E ns C 20pF TDO hold after TCK falling ti CC 2 ns edge TDO high imped to valid t9 CC 14 ns C 50 pF from TCK falling edg
41. 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asvnchronous Svnchronous Serial Channels ASC with baud rate generator paritv framing and overrun error detection Three High Speed Svnchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality One FlexRay module with 2 channels E Ray Data Sheet 1 V 1 4 1 2014 05 Cinfineon PS Summarv of Features One General Purpose Timer Arrav Module GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management e 32 analog input lines for ADC 2 independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cy
42. AM 16 KB BROM OCDS Li Debug Interface JTAG I MLIO oz MemCheck Z7 System Peripheral Bus SPB 16 KB PRAM Interrupt ASCO System ASC1 FPI Bus Interface Interrupts 5V 3 3V supported as well Ext ADC Supply i 32KBCMEM a 32KB CMEM E Rav E mm SCU 2 Channels 2 g amp 5 2 amp 3 3V Ext FADC Supply Ext Multi MSCU Request S N LVDS ssc2 BlockDiagram Unit 128 MO U SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782F 320F160HR SAK TC1782F 320F160HL Figure 1 SAK TC1782 320F180HR SAK TC1782 320F180HL SAK TC1782 320F160HR SAK TC1782 320F160HL Block Diagram Data Sheet 13 V 1 4 1 2014 05 Cinfineon TC1782 System Overview of the TC1782Block Diagrams Figure 2 shows the block diagram of the SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL PMI 24 KB SPRAM 16 KB ICACHE Configurable FPU TriCore CPU 124 KB LDRAM 4KB DCACHE Configurable 128 KB DFlash 8 KB OVRAM 16 KB BROM Local Memory Bus 2 5 MB PFlash LMB Abbreviations ICACHE Instruction Cache DCACHE Data Cache SPRAM Scratch Pad RAM OVRAM Overlav RAM BROM Boot ROM PFlash Program Flash DFlash Data Flash PRAM Parameter RAM in PCP PCODE Code RAM in PCP 16 KB
43. Condition Resistance of the Rarer l 500 1000 Ohm reference voltage input CC path Sample time ts CC 2 257 Tapci Calibration time after bit tea CC 4352 cycle ADC_GLOBCFG SUCAL s is set Total Unadjusted TUE CC 4 419 LSB ADC Error9912 resolution 12 bit Analog reference ground Vacnpo Vssm Varero V SR 0 05 1 Analog input voltage Vain SR VacNpo Varero V Analog reference voltage Varero l Vacnpo Voomt V SR 1 0 0519 15 Analog reference voltage Varero Vpp2 Voomt V range 982 VAGNDO 0 05 SR 1 oon ao 1 1 The sampling capacity of the conversion C network is pre charged to Vanrro 2 before the sampling moment Because of the parasitic elements the voltage measured at AINx can deviate from Varery 2 Applies to AINx when used as auxiliary reference input This represents an equivalent switched capacitance This capacitance is not switched to the reference voltage at once Instead smaller capacitances are successively switched to the reference voltage The sum of DNL INL GAIN OFF errors does not exceed the related TUE total unadjusted error If a reduced analog reference voltage between 1V and Vppw 2 is used then there are additional decrease in the ADC speed and accuracy If the analog reference voltage range is below Vpp but still in the defined range of Vppm 2 and Vppy is used then the ADC converter errors
44. DC Abbreviations ICACHE Instruction Cache DCACHE Data Cache SPRAM Scratch Pad RAM LDRAM Local Data RAM OVRAM Overlay RAM BROM Boot ROM PFlash Program Flash DFlash Data Flash PRAM Parameter RAM in PCP PCODE Code RAM in PCP OCDS 11 Debug Interface JTAG DA max 4 3 3V Ext FADC Supply BlockDiagram SAK TC1782N 256F133HR SAK TC1782N 256F133HR Figure 3 Data Sheet SAK TC1782N 256F133HR SAK TC1782N 256F133HL Block Diagram 15 V 1 4 1 2014 05 Cinfineon Se Pinning 3 Pinning Figure 4 is showing the TC1782 Logic Svmbol PORST Alternate Functions General Control S LB Port 0 GPTA SCU E RAYD ee MSCO ESRI 16 GPTA SSCI EE KZ Port 1 ADCO OCDS TEST 14 GPTA SSO0 1 SEN TCK DAPO EN Pot2 MIO MSO JTAG Contro TDI BRKIN 2 Pot 3 SEU MM TDO DAP2 4 i BRKOUT KZ Port 4 GPTA SCU CAN bii 116 pen GPTA MLIO E RAY Analog Inputs AN 35 0 4 SSC2 Voom K Port 6 GPTA MSCO Vssm Voowr SK UC 1 80 P 320 FI80HR Vssur SAK TC1782 F 320 F180HL Analog Power Vppar SAK TC1782 F 320 F160HR Supply SAK TC1782 F 320F 160HL Varero SAK TC1782 F 320 F133HR and NK SAK TC1782 F 320 F133HL VEAREF Ve enb XTAL1 XTAL2 Vopris Voposc Oscillator Digital Circuitry Vop Voposca Power Supply Mac Vssosc Vss TC1782 LQFP 176 Figure 4 TC1782 Logic Svmbol Data Sheet 16 V 1 4 1 2014 05 infineon e PinningTC1782 Pin Configuration 3 1 TC1782 Pin Configurat
45. FP 176 10 Data Sheet 11 V 1 4 1 2014 05 Cinfineon Se Svstem Overview of the TC1782 2 Svstem Overview of the TC1782 The TC1782 combines three powerful technologies within one silicon die achieving new levels of power speed and economv for embedded applications Reduced Instruction Set Computing RISC processor architecture Digital Signal Processing DSP operations and addressing modes On chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real world signals The RISC load store architecture provides high computational bandwidth with low system cost On chip memory and peripherals are designed to support even the most demanding high bandwidth real time embedded control systems tasks Additional high level features of the TC1782 include Efficient memory organization instruction and data scratch memories caches Serial communication interfaces flexible synchronous and asynchronous modes Peripheral Control Processor standalone data operations and interrupt servicing DMA Controller DMA operations and interrupt servicing General purpose timers High performance on chip buses On chip debugging and emulation facilities Flexible interconnections to external components Flexible power management The TC1782 is a high performance microcontroller with TriCore CPU program and data memories buses bus ar
46. General Purpose I O Line 1 IN29 PU GPTAO Input 29 IN53 GPTAO Input 53 OUT29 O1 GPTAO Output 29 OUT53 O2 GPTAO Output 53 TXDCAN2 O3 CAN Node 2 Transmitter Output 88 P4 2 lOO A2 Port 4 General Purpose I O Line 2 IN30 PU GPTAO Input 30 IN54 l GPTAO Input 54 OUT30 O1 GPTAO Output 30 OUT54 O2 GPTAO Output 54 EXTCLK1 O3 External Clock 1 Output 90 P4 3 lOO A2 Port 4 General Purpose I O Line 3 IN31 PU GPTAO Input 31 IN55 l GPTAQ Input 55 OUT31 01 GPTAO Output 31 OUT55 O2 GPTAO Output 55 EXTCLKO O3 External Clock 0 Output Data Sheet 32 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function Port 5 1 P5 0 OO A1 Port 5 General Purpose I O Line 0 IN40 PU GPTAO Input 40 IN26 l LTCA2 Input 26 OUT40 01 GPTAO Output 40 OUT8 O2 LTCA2 Output 8 SLSO20 O3 SSC2 Slave Select Output 0 2 P5 1 OO A1 Port 5 General Purpose I O Line 1 IN41 PU GPTAO Input 41 IN27 l LTCA2 Input 27 OUT41 O1 GPTAO Output 41 OUT9 O2 LTCA2 Output 9 SLSO21 O3 SSC2 Slave Select Output 1 3 P5 2 l OO JA14 Port 5 General Purpose I O Line 2 IN42 PU GPTAO Input 42 IN28 l LTCA2 Input 28 OUT42 O1 GPTAO Output 42 OUT10 O2 LTCA2 Output 10 SL
47. ORST power power t down fail Power Up 5 vsd Figure 14 5V 3 3V 1 3 V Power Up Down Sequence for 5 Operating Range The following list of rules applies to the power up down sequence All ground pins Vss must be externally connected to one single star point in the system Regarding the DC current component all ground pins are internally directly connected At any moment in time to avoid increased latch up risk each power supply must be higher then any lower power supply 0 5 V or Vpps gt Vpp33 0 5 V Vops gt Vpp43 0 5 V Vpp33 gt Vpp13 0 5 V see Figure 14 The latch up risk is minimized if the I O currents are limited to 20 mA for one pin group AND 100 mA for the completed device I Os AND additionally before power up after power down 1 mA for one pin in inactive mode 0 V on all power supplies During power up and power down the voltage difference between the power supply pins of the same voltage 3 3 V 1 3 V and 5 V with different names for example Mopp Vppria that are internally connected via diodes must be lower than 100 mV On the other hand all power supply pins with the same name for example all Vppp are internally directly connected It is recommended that the power pins of the same voltage are driven by a single power supply Data Sheet 94 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 1 The PORST signal may be deactivated after all Vops Vpp33
48. PRAM 32KB CMEM Interrupt NY System o ASCO 4 2 4 E ASC1 jar oe amp 3 a T 8 E 5 A Ext Request MSCO LVDS System Peripheral Bus SPB ssc2 K k OCDS 11 Debug Local Data RAM Interface JTAG a K B V max a FADC 3 3V Ext FADC Supply BlockDiagram SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Figure 2 SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Block Diagram Data Sheet 14 V 1 4 1 2014 05 infineon TC1782 System Overview of the TC1782Block Diagrams Figure 3 shows the block diagram of the SAK TC1782N 256F133HR SAK TC1782N 256F133HL PMI TriCore 24 KB SPRAM CPU 16 KB ICACHE Configurable DMI 124 KB LDRAM 4KB DCACHE Configurable LMB 2 MB PFlash 64 KB DFlash 8 KB OVRAM 16 KB BROM DMA 16 channels ws U SMF 16 KB PRAM PCP2 Core 32KB CMEM FPl Bus Interface 2 a E g ae SBCU E RAV Svstem Peripheral Bus feru System Peripheral Bus Interrupt System D STM SCU Ports ssco MSCO vps Unit 3 Nodes ssci ER ssc2 i kK FA
49. SI 01x V CC Vo Input Leakage Current Ion CC l 1000 1000 n Ratio between low and Mu Mu 0 6 high input threshold CC Input high voltage class Mu SR 10 6x min V V pins Monn DDP 0 3 3 6 Input low voltage Class Mu SR 0 3 0 36x IV pads Mons Data Sheet 72 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 26 LVDS_Pads Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Output impedance pad Ro CC 40 140 Ohm class F LVDS mode Fall time pad type LVDS it CC 2 ns termination 100 OQ x 1 96 Rise time pad type LVDS tp CC 2 ns termination 100 O x 1 96 Pad set up time ser up gt 13 us termination s CC 1000 1 Output Differential Voltage Vo CC 150 400 mV termination 1000 1 Output voltage high pad Vg CC 1525 mV termination class F LVDS mode 100041 Output voltage low pad Vo CC 875 mV termination class F LVDS mode 100041 Output Offset Voltage Vos CC 1075 1325 mV termination 100 O x 1 96 Data Sheet 73 V 1 4 1 2014 05 Cinfineon TC1782 5 2 2 Analog to Digital Converters ADCx Electrical ParametersDC Parameters ADC parameter are valid fo
50. SO22 O3 SSC2 Slave Select Output 2 4 P5 3 O00 A1 Port 5 General Purpose I O Line 3 IN43 PU GPTAO Input 43 OUT43 O1 GPTAO Output 43 OUT11 O2 LTCA2 Output 11 SLSO23 O3 SSC2 Slave Select Output 3 Data Sheet 33 V 14 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 5 P5 4 O00 A1 Port 5 General Purpose I O Line 4 IN44 PU GPTAO Input 44 IN29 l LTCA2 Input 29 SLSI2A l SSC2 Slave Select Input A OUT44 01 GPTAO Output 44 OUT12 O2 LTCA2 Output 12 SLSO24 O3 SSC2 Slave Select Output 4 6 P5 5 OO A1 Port 5 General Purpose I O Line 5 IN45 PU GPTAO Input 45 IN30 l LTCA2 Input 30 MRST2A l SSC2 Master Receive Input Master Mode OUT45 01 GPTAO Output 45 OUT13 O2 LTCA2 Output 13 MRST2 O3 SSC2 Master Transmit Input Slave Mode 7 P5 6 OO A1 Port 5 General Purpose I O Line 6 IN46 PU GPTAO Input 46 IN31 l LTCA2 Input 31 MTSR2A l SSC2 Slave Receive Input Slave Mode OUT46 01 GPTAO Output 46 OUT14 O2 LTCA2 Output 14 MTSR2 03 SSC2 Master Transmit Output Master Mode 8 P5 7 OO A1 Port 5 General Purpose I O Line 7 IN47 PU GPTAO Input 47 SCLK2A l SSC2 Clock Input Slave Mode OUT47 O1 GPTAO Output 47 OUT15 O2 LTCA2 Output 15 SCLK
51. ST rise time por SR 50 ms TESTMODE TRST tpos SR 0 ns setup time to PORST rising edge 1 2 2 The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts The given time includes the time of the internal reset extension for a configured value of SCU RSTCNTCON RELSA 0x05BE The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts The given time includes the internal reset extension time for the System and Application Reset which is visible through ESRO This parameter includes the delay of the analog spike filter in the PORST pad Data Sheet 97 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters Voor 129 Vppppa Sp ie VDDP Vopppa VDD POA POA gt PORT f 7 N f 2 o kon kon TRST TESTMODE ESRO HWCFG Pads Pad state undefined Tri state or pull device active reset_beh2 As programmed Figure 15 Power Pad and Reset Timing Data Sheet 98 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 4 Phase Locked Loop PLL
52. Slave Select Output 0 127 P3 6 OO A1 Port 3 General Purpose I O Line 6 SLSOO1 oi PU ssco Slave Select Output 1 SLSO11 O2 SSC1 Slave Select Output 1 SLSOANDO1 03 SSCO AND SSC1 Slave Select Output 1 131 P3 7 lOO A2 Port 3 General Purpose I O Line 7 SLSIO1 l PU ssco Slave Select Input 1 SLSO02 01 SSCO Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTAO Output 89 128 P3 8 lOO A2 Port 3 General Purpose I O Line 8 SLSO06 o1 JPU ssco Slave Select Output 6 TXD1 O2 ASC1 Transmit Output OUT90 O3 GPTAO Output 90 138 P3 9 00 A1 Port3 General Purpose I O Line 9 RXD1A PU ASC1 Receiver Input A RXD1A 01 ASC1 Receiver Output A Synchronous Mode RXD1A O2 ASC1 Receiver Output A Synchronous Mode OUT91 O3 GPTAO Output 91 Data Sheet 30 V 1 4 1 2014 05 Cinfineon e PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 137 P3 10 00 A1 Port 3 General Purpose I O Line 10 REQO l PU External Request Input 0 Reserved 01 Reserved O2 OUT92 O3 GPTAO Output 92 144 P3 11 OO A1 Port 3 General Purpose I O Line 11 REQ1 PU External Request Input 1 Reserved O1 Reserved O2 OUT93 O3 GPTAO Output 93 143 P3 12 OO A1 Port3 Gene
53. V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 22 Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Output voltage high class A1 pads Vous CC Vopr 0 4 Io 1 4 mA pin out driver medium Vopr 0 4 Igy2 1 4 mA pin out driver strong 2 4 Jo 2 MA pin out driver medium 2 4 Jo 2 mA pin out driver strong Vopr 0 4 Igy2 400 uA pin out driver weak 2 4 Igy2 500 uA pin out driver weak Output voltage low class A1 pads VoLat CC 0 4 Ig 2 mA pin out driver medium 0 4 Ig 2 mA pin out driver strong 0 4 Ig S 500 uA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Data Sheet 65 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 23 Standard Pads Class A2 Parameter Svmbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for A2 HYSA2 0 1x V pads CC Vopp Input Leakage current loza2 6000 6000 nA VS Vopp 2 Class A2 CC 1 V Me Vppp 2 1V V20V Me Vopp V 3000 3000 nA V gt Vppp 2 1 V V lt
54. Vppp 2 1V Ratio Vil Vih A2 pads Vino 10 6 V ikaz CC On Resistance of the Rpsoww 450 600 Ohm Lous 0 5 mA class A2 pad weak driver CC P MOS 210 340 Ohm ZoL lt 0 5 mA N MOS On Resistance of the RpsowM 155 Ohm lous 2 mA class A2 pad medium CC P_MOS driver gt 110 Ohm 1 lt 2 mA N MOS On Resistance of the Roson2 28 Ohm lous 2 mA class A2 pad strong driver CC P_MOS 22 Ohm 7g 2 mA N MOS Data Sheet 66 V 1 4 1 2014 05 Cinfineon TC1782 Table 23 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Fall time pad tvpe A2 tra CC 150 ns C 20 pF pin out driver weak ns C 50 pF edge medium pin out driver strong 10 ns C 50 pF edge medium minus pin out driver strong 3 7 ns C 50 pF edge sharp pin out driver strong ns C 50 pF edge sharp minus pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 50 pF pin out driver medium 7 5 ns C 7 100 pF edge sharp pin out driver strong 140 ns C 150 pF pin out driver medium Data Sheet 67 V 1 4 1 2014 05 Cinfineon Table 23 TC1782 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parame
55. am Flash Memory PFLASH with ECC 128 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 128 Kbyte Data Memory LDRAM Instruction Cache up to 16 Kbyte ICACHE configurable 40 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Three High Speed Synchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality Data Sheet 5 V 1 4 1 2014 05 Cinfineon PS Summarv of Features One General Purpose Timer Arrav M
56. bitration an interrupt controller a peripheral control processor and a DMA controller and several on chip peripherals The TC1782 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price performance real time responsiveness computational power data bandwidth and power consumption are key design elements The TC1782 offers several versatile on chip peripheral units such as serial controllers timer units and Analog to Digital converters Within the TC1782 all these peripheral units are connected to the TriCore CPU system via the Flexible Peripheral Interconnect FPI Bus and the Local Memory Bus LMB Several I O lines on the TC1782 ports are reserved for these peripheral units to communicate with the external world Data Sheet 12 V 1 4 1 2014 05 Cinfineon PS System Overview of the TC1782Block Diagrams 2 1 Block Diagrams Figure 1 shows the block diagram of the SAK TC1782 320F180HR SAK TC1782 320F180HL SAK TC1782 320F160HR SAK TC1782 320F160HL Abbreviations ICACHE Instruction Cache FPU DMI DCACHE Data Cache SPRAM Scratch Pad RAM PMI c LDRAM Local Data RAM TriCore OVRAM Overlay RAM 24 KB SPRAM 124 KB LDRAM N y S CPU KB DCACHE COM S UM Configurable Configurable DFlash Data Flash PRAM Parameter RAM in PCP PCODE Code RAM in PCP Local Memory Bus LMB 2 5MB PFlash Bridge 128 KB DFlash 8 KB OVR
57. c Ves R TXDA1 RDAT AOB OUT 89 P5 8 Sf ESRI TXDBI RVALIDO B OUT 90 P5 9 S f P1 IN 17 OUT 17 OUT73 TESTMODE 2 P1 15 BRKIN BRKOUT FP 1 ONN 16 OUT 16 0UT 72 BRKIN BRKOUT 2 ICKDAPO TXENB RCLKOB OUT g2 P5 11 S TDATAQ SLSO07 0UT93 P5 12 TVALIDOB SLSO16 P5 13 SJ RXDA1 TREADYOB OUT 94 P5 14 CJ L e AER Y E TDODAPZBRKINIBRKOUT Vees TMSDAP1 Vsse TDUBRKINIBRKOUT Vooar c TC1782 l 2 P1 7 IN23 0UT 23 0UT79 Voe c P1 6 IN22 0UT22 0U178 Vss sd P1 5 IN21JOUT21 0UT77 Vraner 2 P1 4 IN20 EMGSTOROUT20 OUT 76 Wee Vpoosca AN35 Vooosc AN34 E Vssosc AN33 ES xt a ANIZ gt XTAL AN31 E Vss AN30 L2 Vor AN29 voo AN28 l 2 P1 3 IN19 0UT 19 0UT75 ANT P1 11 IN27 IIN51 SCLK 1B OUT 27 OUT 51 gt P1 10 IN26 INS0 OUT 26 JOUT 50 SLSO 17 P1 9 IN25 IN49 IMRSTI B OUT 25 0UT 49 ANS E P1 8 IN24 JINAB MT SRI B OUT 24 OUT 48 AN24 P12 IN18 OUT 18 OUT74 ANZ3 Eau AN22 cd Sr ANZI cd ES P4 3 IN31 IN55 0UT 31 OUT 55 EXT CLKO voor SAK TC 1782 320F 180HR SAK TC 1782 320F 180HL SAK TC 1782 320F 160HR SAK TC 1782 320F 160HL SAK TC 1782 320F 133HR SAK TC 1782 320F 133HL Figure 5 SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782F 320F160HR SAK TC1782F 320F160HL Pinning ADOEMUX2 OU T1 8 IN18P 1 14 471 ADOEM UX 1 OU T17 IN17 P1 13 Zf 72 ADOEMUXO OU T16 N16P 1 12 73 TCLKO OUT 28 OUT32 N32 P20 2 74 SLSO 13 SL S003 OUT 33 TREADYOA IN33 P2 1 75 TDATAO
58. cles of fkap clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 86 digital general purpose I O lines GPIO 4 input lines Digital I O ports with 3 3 V capabilitv On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1782ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 2 V 1 4 1 2014 05 Cinfineon PS Summarv of Features The SAK TC1782N 320F180HR SAK TC1782N 320F180HL has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 180 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 180 MHz operation at full temperature range Multiple on chip memories 2 5 Mbyte Program Flash Memory PFLASH with ECC 128 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 128 Kbyte Data Memory LDRAM Instruction Cache up to 16 Kbyte ICACHE configurable 40 Kbyte Code Scratchpad Memory SPRAM Da
59. coupling Kovan 0 000 Toys 0 mA Ia factor for analog inputs CC 1 2 mA analog negative pad 5 0 V Overload coupling Kovap 0 000 Toys 3 MA factor for analog inputs CC 01 Iov 0 mA analog positive pad 5 0 V CPU Frequency Jepu SR 133 MHz SAK TC1782N 256F 133HR SAK TC1782N 256F 133HL 180 MHz SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL 160 MHz SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Data Sheet 50 V 1 4 1 2014 05 Cinfineon Table 18 TC1782 Electrical ParametersGeneral Parameters Operating Conditions Parameters cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition FPI bus frequencv ep SR 90 MHz SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782F 256F133HR SAK TC1782F 256F133HL SAK TC1782N 256F133HR SAK TC1782N 256F133HL 80 MHz SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Data Sheet 51 V 1 4 1 2014 05 Cinfineon Table 18 Operating Conditions Parameters cont d TC1782 Electrical ParametersGeneral Parameters Parameter Svmbol Values Min
60. driver The driver drives low during power on reset 1 Only available for SAK TC1782F 320F180HR SAK TC1782F 320F 180HL and SAK TC1782F 320F160HR 2 For the emulation device ED this pin is bonded to VDDSB ED Stand By RAM supply In the production devide device this pin is bonded to a VDD pad Legend for Table 2 Column Cirl Input for GPIO port lines with IOCR bit field selection PCx OXXXg O Output O0 Output with IOCR bit field selection PCx 1X00 O1 Output with IOCR bit field selection PCx 1X01 ALT1 O2 Output with IOCR bit field selection PCx 1X10 ALT2 O3 Output with IOCR bit field selection PCx 1X11 ALT3 Column Type A1 Pad class A1 LVTTL A1 Pad class A1 LVTTL A2 Pad class A2 LVTTL Data Sheet 40 V 1 4 1 2014 05 Cinfineon PS PinningTC1782 Pin Configuration F Pad class F LVDS CMOS D Pad class D ADC Pad class LVTTL PU with pull up device connected during reset PORST 0 PD with pull down device connected during reset PORST 0 TR tri state during reset PORST 0 Data Sheet 41 V 1 4 1 2014 05 TC1782 Cinfineon 4 Identification Registers The Identification Registers uniquely identify the whole device Identification Registers Table 3 SAK TC1782F 320F180HR Identification Registers Short Nam
61. e TDO valid to high imped ti CC 13 5 ns C 50pF from TCK falling edge 1 The falling edge on TCK is used to generate the TDO timing 2 The setup time for TDO is given implicitly by the TCK cycle time Data Sheet 102 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 0 9 Vpop 0 1 V f DDP MC JTAG TCK Figure 16 Test Clock Timing TCK ts L TMS Galat te TDO MC JTAG Figure17 JTAGTiming Data Sheet 103 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 7 DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface Note These parameters are not subject to production test but verified bv design and or characterization Table 37 DAP Parameters Parameter Svmbol Values Unit Note Min Tvp Max Test Condition DAPO clock period trek SR 12 5 ns DAPO high time ta SR 4 ns DAPO low time ta SR 4 ns DAPO clock rise time t4 SR 2 ns DAPO clock fall time fis SR m 2 ns DAP1 setup to DAPO De SR 6 0 ns rising edge DAP1 hold after DAPO Lu SR 6 0 ns rising edge DAPI valid per DAPO fg CC 8 ii ns C 20 pF clock period f 80 MHz 10 ns C 7 50 pF f 40 MHz 1 See the DAP chapter for clock rate restrictions in the Active IDLE
62. e Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 FOOO 0464 BA SCU_CHIPID 8500 9310 F000 0640 BA SCU_MANID 0000 1820 FOOO 0644 BA SCU_RTID 0000 0000 F000 0648 BA Table 4 SAK TC1782F 320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 FOOO 0464 BA SCU_CHIPID 0500 9310 F000 0640 BA SCU_MANID 0000 1820 F000 0644 BA SCU_RTID 0000 0000 FOOO 0648 BA Table 5 SAK TC1782N 320F180HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 F000 0464 BA SCU_CHIPID 8500 9410 F000 0640 BA SCU_MANID 0000 1820 F000 0644 BA SCU_RTID 0000 0000 FOOO 0648 BA Table 6 SAK TC1782N 320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 BA CBS_JTAGID 1018 E083 F000 0464 BA SCU_CHIPID 0500 9410 F000 0640 BA Data Sheet 42 V 1 4 1 2014 05 Cinfineon TC1782 Identification Registers Table 6 SAK TC1782N 320F180HL Identification Registers cont d Short Name Value Address Stepping SCU MANID 0000 1820 F000 0644 BA SCU RTID 0000 0000 F000 0648 BA Table 7 SAK TC1782N 256F133HR Identification Registers Short Name Value Address Stepping CBS JDPID 0000 6350 F000 0408 BA CBS JTAGID 1018 E083
63. e or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Cinfineon Never stop thinking 32 Bit Microcontroller TC1782 32 Bit Single Chip Microcontroller Data Sheet V 1 4 1 2014 05 Microcontrollers Cinfineon P Table of Contents Table of Contents 1 1 1 Summary of Features 1 1 2 System Overview of the TC1782 2 12 2 1 Block Diagrams saries vied BER sk eme beled KE 2 13 3 ai Ill HEEN 3 16 3 1 TC1782 Pin Configuration 3 17 4 Identification Registers 4 42 5 Electrical Parameters 5 45 5 1 General Parameters sisse eese sua gu be deg d 5 45 5 1 1 Parameter Interpretation 5 45 5 1 2 Pad Driver and Pad Classes Summary 5 46 5 1 3 Absolute Maximum Ratings 5 47 5 1 4 Pin Reliability in Overload 5 48 5 1 5 OperatingConditions 5 50 5 2 DC Parameters EE EEN e Re EE ees 5 59 5 2 1 InputOutputPins 5 59 5 2 2 Analo
64. ed the term typical change description of parameter toa for the ADC correct typo for class D pads in tables 14 and 15 adapt Absolute Maximun Rating add footnote to Flash parameter con add note at the end of Pin Reliability in Overload section clearify pad supply levels in Pin Reliability in Overload section add footnote for D Flash currents in power section The following changes where done between Version 1 2 and 1 3 of this document add product option SAK TC1782F 320F160HL SAK TC1782F 320F160HR SAK TC1782N 320F 160HL and SAK TC1782N 320F 160HR update block diagrams to cover new option add identification registers for new product option rework first sentence for chapter 5 3 reduce min value for f for both PLLs add for MLI and SSC parameter valid strong driver medium edge only add footnote 5 for SSC parameters update FADC parameter EF pn e change MLI parameter min value rename section Extented Range Operating Conditions to Voltage Operating timing Profiles and remove limitions on GPIOs split Rpsonm for class F pads into two conditions The following changes where done between Version 1 3 and 1 3 1 of this document correct typos in table 1 SAK TC1782N 320N160HR SAK TC1782F 320F160HR SAK TC1782N 320N160HL gt SAK TC1782F 320F 160HL reduce current for I ypg from 24mA to 12mA only 2 pairs are available The following changes where done between Version 1 3 1 and 1 4 of this docu
65. ency that is monitored is foscper which is derived for fosc 8 OSC Ioscase OSCVAL 41 The divider value SCU OSCCON OSCVAL has to be selected in a way that fosceer S 2 5 MHz Note foscrer has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2 5 MHz The monitored frequency is too low if it is below 1 25 MHz and too high if it is above 7 5 MHz This leads to the following two conditions Too low fose lt 1 25 MHz x SCU OSCCON OSCVAL H Too high fosc gt 7 5 MHz x SCU OSCCON OSCVAL 1 Note The accuracy is 3096 for these boundaries Data Sheet 100 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersAC Parameters 5 3 5 ERAY Phase Locked Loop ERAY PULL Table 35 PLL ERAV Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition Accumulated jitter at Dpp CC 0 8 0 8 ns SYSCLK pin Accumulated_Jitter Dp CC 0 5 ke 0 5 ns PLL Base Frequency of foripase_ 50 250 360 MHz the ERAY PLL ERAv CC VCO input frequency of kek CC 20 40 MHz the ERAY PLL VCO frequency range of fyco era 450 gt 500 MHZ the ERAY PLL y CC PLL lock in time t CC 5 6 200 HS Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF with the maximum driver and sharp edge Note The maximum peak to peak noise on the pad supplv voltage measured between Vbposc
66. ent Ippriae is replaced by Ippp With the condition including flash erase verify current Jee sp is replaced by Ippp With the condition including flash read current parameter Jo an Was renamed to ppr 3 The rework of the 3 3 V current part of the Power Supply Parameters was done for simplification and clarification Former given values could still be used if liked the new definition results in the same resulting values or slightly better values The flash module is supplied via ppris and ppp For the different flash operating modes in worst case different allocations for the two domains resulting The application typical case flash read has max Ippp of 12 mA and max Ippri3 Of 56 mA resulting is a sum of 68 mA The case flash programming has max ppp of 27 mA and max ppg 3 of 21 mA resulting is a sum of 48 mA The case flash erase verify has max Ippp of 20 mA and max Ippri3 of 56 mA resulting is a sum of 76 mA So for the old parameter Ippp with 15 mA the new version reads as ppp 12 Ippp porsT 14 5 mA for the same application relevant case The following changes where done between Version 1 1 and 1 2 of this document Data Sheet 121 V 1 4 1 2014 05 Cinfineon es Historv removed products SAK TC1182N 320F180HR SAK TC1182N 320F180HL SAK TC1182N 256F133HR and SAK TC1182N 256F 133HL improve parameters ppr 3 change for parameter Ng note from Max data retention to Min remov
67. eptibility IVismi 500 V of the LVDS pins ESD susceptibility Vopy 500 V Conforming to according to JESD22 C101 C Charged Device Model CDM Moisture MSL 3 Conforming to Jedec Sensitivity Level J STD 020C for 240 C Data Sheet 117 V 1 4 1 2014 05 infineon lie Electrical ParametersPackage and Reliabilitv zi This lifetime refers only to the time when the device is powered on M For worst case temperature profile equivalent to 1200 hours at 7 125 150 C 3600 hours at T 110 125 C 7200 hours at T 100 110 C 11000 hours at T 25 100 C 1000 hours at 7 40 25 C Data Sheet 118 V 1 4 1 2014 05 Cinfineon es 6 Historv Historv The following changes where done between Version 0 7 and 0 8 of this document Change product name from SAK TC1782 320F180HL to SAK TC1782 320F180HR Change product name from SAK TC1782 256F133HL to SAK TC1782 256F133HR Change DFLASH size from 64Kbyte to 128Kbyte in chapter 1 Add ADC module abbreviation to table 1 Analog Input Port Function description Change SCU RTID and SCU CHIPID values to match the step Extend Vpposc3 to 7 5 o Add parameter HYSA 1 Add parameter HYSA2 Add parameter Vi e Vine Add parameter Rpsoyr Changed typical value of Cainsy from 7 to 9 pF Changed typical value of Cainror from 25 to 20 pF Remove 3 3 V values from ADC section Add parameter fanc Changed max value of fapc from 20 to
68. eration This current includes the E Ray module power consumption including the PCP operation component The Ipp decreases typically by 68mA if the f p decreases by 5OMHz at constant 7 The pp decreases typically by 30mA if the fp decreases by 50MHz at constant 7 For operations including the D Flash the required currents are always lower than the currents for non D Flash 6 Relevant for the power supply dimensioning not for thermal considerations Data Sheet 90 V 1 4 1 2014 05 Cinfineon ses Electrical ParametersDC Parameters 7 In case of erase of Program Flash PF internal flash arrav loading effects mav generate transient current spikes of up to 15 mA for maximum 5 ms per flash module 5 2 6 1 Calculating the 1 3 V Current Consumption The current consumption of the 1 3 V rail compose out of two parts Static current consumption Dynamic current consumption The static current consumption is related to the device temperature T and the dynamic current consumption depends of the configured clocking frequencies and the software application executed These two parts needs to be added in order to get the rail current consumption 2 I MAT 0 02696 x T Mer 20897 S xe di 3 mA 0 02203 x T ig d 68 c Jxe JEC Function 2 defines the typical static current consumption and Function 3 defines the maximum static current consumption Both functions are valid for Vpp 1 326 V For the dynam
69. files Data Sheet 56 V 1 4 1 2014 05 Cinfineon es Electrical ParametersGeneral Parameters Table 18 Operating Conditions Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition FADC ADC analog Vopme 2 97 3 3 3 63 V for duration supply voltage SR limitation see Voltage Operating Timing Profiles Analog ground voltage Vesar 0 1 0 0 1 V for Vopme SR 1 Applicable for digital outputs 2 Voltage overshoot to 1 7V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h 3 Voltage overshoot to 6 5V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h 4 Voltage overshoot to 4 0V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h 5 This parameter is valid under the assumption the PORST signal is constantly at low level during the power up power down of Vppp Voltage Operating Timing Profiles 1 3V lt Vpp Vpposc Vppar lt 1 3V 5 limited to Operation Lifetime top see Table 46 1 3V 5 lt Vpp Voposc Vopar lt 1 3V 7 5 overvoltage condition limited to 10000 hour duration cumulative in lifetime due to the reliability reductio
70. fineon TC1782 Electrical ParametersDC Parameters 5 2 DC Parameters 5 2 1 Input Output Pins Table 20 Standard_Pads Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Pin capacitance digital Co CC l 10 pF T4 25 C inputs outputs f 1 MHz Pull down current ppl 150 HA IV20 6x Vopp V cc 10 uA V gt 0 36 x Vopp V Pull Up current Heuul 10 HA V 0 6 xX Vbpp V cc a 2 100 uA V lt 0 36 x Vopp V Spike filter always blocked isk CC 10 ns only PORST pin pulse duration Spike filter pass through tsr2 CC 100 ns only PORST pin pulse duration Table 21 Standard Pads Class A1 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for A1 HYSAI 0 1x V pads CC Vppp Input Leakage Current Toza 500 500 nA V20V Class A1 CC VS Vppp V Ratio Vil Vih A1 pads Via 10 6 Vinat CC On Resistance of the Rpsoww 450 600 Ohm Lous 0 5 mA class A1 pad weak driver CC P_MOS 210 340 Ohm ZoL lt 0 5 mA N MOS Data Sheet 59 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 21 Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition On Resistance of the class A1 pad medium driver Rosonm CC 155 Ohm Iop lt 2 mA P_MOS 110 Ohm
71. g to Digital Converters ADCX 5 74 5 2 3 Fast Analog to Digital Converter EADC 5 80 5 24 Oscillator PINS NEEN EE ENEE RE mn 5 85 5 2 5 Temperature Sensor 4424044 alak eke da ee 5 86 5 2 6 Power Supply Current 5 87 5 2 6 1 Calculating the 1 3 V Current Consumption 5 91 5 3 AC Parameters ei eccesso eee Kat gn RE S Pos RR LIRE 5 92 5 3 1 Testing Waveforms 5 92 5 3 2 Power Sequencing c slg kg x Pee ee eee eee 5 93 5 3 3 Power PadandResetlimingg 5 96 5 3 4 Phaselockedloop PLL 5 99 5 3 5 ERAY Phase Locked Loop ERAY PLL 5 101 5 3 6 JTA interffaceTiming 5 102 5 3 7 DAPinterfaceTiming 5 104 5 3 8 PeripheralTimings 5 106 5 3 8 1 Micro Link Interface MLI Timing 5 106 5 3 8 2 Micro Second Channel MSC Interface Timing 5 108 5 3 8 3 SSC Master Slave Mode Timing 5 110 5 3 8 4 ERAY Interface Timing 5 112 5 4 Package and Reliability 5 114 5 4 1 Package Parameters 20 06 00 sls cee eee eee eee 5 114 5 4 2 Package Outline 5 115 Data Sheet l 1 V 1 4 1 2014 05 Cinfineon e 5 4 3 Flash
72. gated by LVDS or by CMOS strong driver and non soft edge When using slow and asymmetrical edges like in case of open drain upstream connection the application must take care that the bit is long enough the baud rate is low enough so that under worst case conditions the three sampling points in the middle of the bit are not violated 0 9 V FCLP cd 0 1 Vopp SOP EN G i 0 9 Vopp 0 1 Viis MSC_Tmg_1 vsd Figure 22 MSC Interface Timing Note The data at SOP should be sampled with the falling edge of FCLP in the target device Data Sheet 109 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersAC Parameters 5 3 8 9 SSC Master Slave Mode Timing The SSC parameters are vaild for C 50 pF and for strong driver medium edge Table 41 SSC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition SCLK clock period 79 fg CC 2x1 ns fre MTSR SLSOx delay form f CC JO 8 ns SCLK rising edge MRST setup to SCLK f SR 16 5 ns falling edge MRST hold from SCLK s SR 0 ns falling edge SCLK input clock t4 SR 4x1 ns period frei SCLK input clock duty tss sa 145 55 cycle SR MTSR setup to SCLK fgg CC 1 fep ns latching edge MTSR hold from SCLK CC 11 fepi ns latching edge 5 SLSI setup to first SCLK tsgCC 1 feg x ns latching edge 5 SLSI hold
73. ic current consumption using the application pattern and yg 2 fep the function 4 applies 4 mA Ipvm dieel x fopy MHz and this finally results in 5 Ipp lo IpyM Data Sheet 91 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 AC Parameters All AC parameters are defined with maximum driver strength unless otherwise noted 5 3 1 Testing Waveforms Vopp 90 rise_fall Figure 10 Rise Fall Time Parameters Vopp Vope 2 Test Points gt Vppe 2 Vss mc04881 a vsd Figure 11 Testing Waveform Output Delay Vioagt 0 1 V Voy 0 1 V Wee Timing memi Reference Vi gag 0 1 V ro s Points m th Vg 0 1V MCT04880 new Figure 12 Testing Waveform Output High Impedance Data Sheet 92 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters 5 3 2 Power Sequencing Va 5 5V a BV bo Km 4 5V kal 3 63V 3 3V 2 97V 1 43V 4 1 3V 7 1 17V t VpppA PORST DA power power t down fail Power Up 10 vsd Figure 13 5 V 3 3 V 1 3 V Power Up Down Sequence for 10 Operating Range Data Sheet 93 V 1 4 1 2014 05 Cinfineon Se Electrical ParametersAC Parameters V a 5 5V DN T li EE 4 5V v l 3 47V X VAREF 3 3V x 2 97V 5 129N 1 365V 1 3V 4 1 235V UN 1 gt t Vopp4 P
74. independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fkap clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 86 digital general purpose I O lines GPIO 4 input lines Digital I O ports with 3 3 V capabilitv On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1782ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 4 V 1 4 1 2014 05 Cinfineon PS Summarv of Features The SAK TC1782N 256F133HR SAK TC1782N 256F133HL has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 133 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 133 MHz operation at full temperature range Multiple on chip memories 2 Mbyte Progr
75. ion This chapter shows the pin configuration of the TC1782 package PG LQFP 176 10 PG LQFP 176 20 88 Eg 8 8 988 eg 2 2 o 2 2 SER a x 2858 g a SSES a See a tebe 8 Es EEEE p ES 835555 88 ER putoo a 22528922 ee5330000 Er EK 588 2 Zzz2888 o az3annce SE SE EEOG u arp sass BOsBEBSELE 8 SE Een 5553835 98525555 22 zz 55 EE ES 33 Soke E 229255555 kE gt 29900 66 egen ges 5 22203888 5828388388 eege ES 58 f SE ZE SE eggs 5 Se Sbeacsssseec EL SEER 55 555522 EXER gest g eesdd33 Oo SE5 EzEZeE ERE CERN 82833999 2Sk izzzeen sPSSPP esi SEPDSSRS re i iiz Eb SS a zz zz2229 20o00 o oo G a ezz 222222288 888893 FER SeS see 09 feste 23885 3373 33333333588 353535 se SES E SSES EE EE E EE im MANN immer Df nn Se SS errr ES se 8858 Ws xus Svane SLSCO 20 OUT 40 OUT 8 IN 40 IN 26 P5 0 A SLSCO 21 OUT 41 OUT YIN 41 IN 27 P5 1 SLSCO22 OUT 42 JOUT 10 IN 42 IN 28 P5 2 54 SLSCO 23 OUT 43 OUT 11 IN 43 P5 3 54 SLSCO24 OUT 44 OUT 12 SLSI2AIN 44 IN 29 A CJ MRST2A OUT45 OUT 13 IN 451IN 30 P5 5 Sf P3 6 SLS001 SLSO11 SLSO 01 amp SLSO 11 MTSR2A OUT46 OUT 14 JIN 461IN 31 PS 6 S P3 5 SLSO00 SLSO10 SLSO 00 amp SLSO 10 SCLK2 OUT 47 OUT 15 IN 47 7 54 l Vss 8 P34 OUT 88 MTSRO P37I SLSI01 OUT 89 SLSO02 SLSO12 P3 3 OUT 87 MRSTO P3 2 OUT 86 SCLKO P3 8 SLSOO6 OUT90 TXD1 RXDBI TCLKQIOUT 98 P5 15 Voor bo eil SH Vo c S
76. is permissible provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h A running conversion may become inexact in case of violating the nomal operating conditions voltage overshoots 2 The calibration procedure should run after each power up when all power supply voltages and the reference voltage have stabilized FADC Analog Input Stage FADC Reference Voltage Input Circuitry eo FADC InpRefDiag Figure 9 FADC Input Circuits Data Sheet 84 V 1 4 1 2014 05 Cinfineon TC1782 5 2 4 Oscillator Pins Table 30 OSC XTAL Parameters Electrical ParametersDC Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition Input current at XTAL1 Tix CC l 25 25 HA Vin lt Voposcs Vin20 V Input frequency fosc SR 4 40 MHz Direct Input Mode selected 8 25 MHZ External Crystal Mode selected Oscillator start up time foses Mi 10 ms CC Input high voltage at Vinx SR O 7x Vooos V XTAL1 Vopos c3 c3 0 5 Input low voltage at Vix SR 0 5 03x V XTAL1 Vppos G3 Input Hysteresis for HYSAX 200 mV XTAL4 pad 9 CC 1 toscs is defined from the moment when Vppose3 3 13V until the oscillations reach an amplitude at XTAL1 of 0 3 Vpposca The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended
77. llowing features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 160 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 160 MHz operation at full temperature range Multiple on chip memories 2 5 Mbyte Program Flash Memory PFLASH with ECC 128 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 128 Kbyte Data Memory LDRAM Instruction Cache up to 16 Kbyte ICACHE configurable 40 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Three High Speed Synchronous Serial Channels SSC with programmable data length and
78. lues add conditions for MLI MSC SSC parameters changed definition for t13 and t14 of the MLI timing changed definition for t45 of the MSC timing add parameters dTxdly and dRxdiv to ERAY parameters correct ERAY parameters t60 and t63 values correct footnotes for ERAY parameters split flash parameters tPRD and tPRP in two conditions add conditions to LVDS pad parameters Changed VAREFx to VAREFO and VAGNDx to VAGNDO remove Pin Reliability in Overload section add parameters IIN and Sum IN to absolute ratings adjust thresholds in figure 28 ERAY add parameter HYSX to PSC XTAL added RDSON values for all driver settings weak medium and strong removed footnote 2 of table 6 change conditions for RDSON weak parameters change load for timing of SSC MSC and MLI from C 25 pF to C 50 pF typical e add type to legend of table 2 add SAK TC1782 320F180HL and SAK TC1782 256F133HL changed timing checkpoints in figure 23 add section 5 2 6 1 add to parameters tkp and ter condition C 50 pF add new footnote 7 to ADC parameter table add min and max value for Qconv and adapt typ value add load conditions for ter and ter add conditions to PLL parameter t change DAP parameter t g from SR to CC classification remove footnote 2 for the FADC increase current for ppp por from 2 to 2 5mA add footnote 3 to table 9 change SAK TC1782 320F180HR SAK TC1782 320F18
79. mbined with the thermal resistances between the junction and the case given above Rrjet Rrjeg in order to calculate the total thermal resistance between the junction and the ambient R54 The thermal resistances between the case and the ambient Rrcat Rtcag depend on the external system PCB case characteristics and are under user responsibility The junction temperature can be calculated using the following equation T Ta Krou x Pp where the Rui is the total thermal resistance between the junction and the ambient This total junction ambient resistance R ya can be obtained from the upper four partial thermal resistances Thermal resistances as measured by the cold plate method MIL SPEC 883 Method 1012 1 2 It is recommended by Infineon Technologies AG to connect the exposed pad Data Sheet 114 V 1 4 1 2014 05 Cinfineon PS Electrical ParametersPackage and Reliabilitv 5 4 2 Package Outline EN i na ta d i y T Twv i I L 1 2 Al TI i Fr ee 2 l RO Wt K Ax ma lee da 80 H 8 i Exposed UHT HEES ER E ISS ll RES x DIPAD E S fk E E E s E a I a i MM MIM EEE EEE DELI LEELEEE LELI TT 05 Juan EIS Get eg 43 x 754775 Al Figure 26 Package Outlines PG LQFP 176 10 PG LQFP 176 20 Table 44 Exposed pad Dimensions Ex 7 8 mm Ey 7 8 mm You can find all of our packages sorts of packing and others in our Infineon Internet
80. ment remove the following product options SAK TC1782F 256F133HR SAK TC1782F 256F 133HL e change t from 100ns to 200ns in table 42 change 749 from 100ns to 200ns in table 42 e extend Kovan conditon from Joys 0 mA Joy2 1 mA to Igy lt 0 mA Ioy2 2 mA change parameter EF o from 90mV to 120 for condition Calibration No The following changes where done between Version 1 4 and 1 4 1 of this document change parameter EF opp from 120mV to 90 for condition Calibration No Data Sheet 122 V 1 4 1 2014 05
81. n Symbol Ctrl Type Function 11 Vppp Port Power Supply 3 3V 20 69 83 89 100 124 139 154 171 12 Ves Digital Ground 22 70 82 85 92 101 125 140 155 172 105 Vpposc Main Oscillator and PLL Power Supply 1 3V 106 Voposc3 Main Oscillator Power Supply 3 3V 104 Vesosc Main Oscillator and PLL Ground 141 Vppri3 Power Supply for Flash 3 3V 102 XTAL1 Main Oscillator Input 103 XTAL2 O Main Oscillator Output 111 JTDI l A2 JTAG Serial Data Input BRKIN PU OCDS Break Input Line BRKOUT O OCDS Break Output Line 112 TMS l A2 JTAG State Machine Control Input DAP1 o PD Device Access Port Line 1 Data Sheet 39 V 1 4 1 2014 05 Cinfineon PS PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 113 JTDO lO A2 JTAG Serial Data Output DAP2 vo PU Device Access Port Line 2 BRKIN l OCDS Break Input Line BRKOUT O OCDS Break Output Line 114 TRST l II JTAG Reset Input PD 115 TCK l AV JTAG Clock Input DAPO l PD Device Access Port Line 0 118 TESTMODE jl II Test Mode Select Input PU 120 ESR1 UO A2 External System Request Reset Input 1 PD 121 PORST l 1 Power On Reset Input PD 122 JESRO UO A2 External System Request Reset Input 0 Default configuration during and after reset is open drain
82. n of the chip caused by the overvoltage stress 1 3V 7 5 lt Vpp Vpposc Vppar lt 1 3V 10 overvoltage condition limited to 1000 hour duration cumulative in lifetime due to the reliability reduction of the chip caused by the overvoltage stress 3 3V lt Vppp Vpposcs Voorts Vopme lt 3 3V 5 limited to Operation Lifetime top see Table 46 Vppp Voposca Vppris Vpomes 3 3 V 10 3 3V 5 lt Vppp Vpposca Vppria Vopme lt 3 3V 1096 overvoltage condition limited to 1000 hour duration cumulative in lifetime due to the reliability reduction of the chip caused by the overvoltage stress SV lt Vopm 5V 10 limited to Operation Lifetime top see Table 46 Data Sheet 57 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersGeneral Parameters Table 19 Pin Groups for Overload Short Circuit Current Sum Parameter Group Pins 1 P5 7 2 P5 15 2 P5 9 8 3 P5 11 10 4 P5 14 12 5 P1 14 12 P2 0 6 P2 4 1 7 P2 7 5 8 P4 2 0 9 P4 3 10 P1 2 P1 8 11 P1 10 9 12 P1 3 P1 11 13 P1 7 4 14 P1 1 0 P1 15 15 P3 8 5 P3 3 2 16 P3 1 0 P3 4 P3 10 9 P3 15 14 17 PO 1 0 P3 13 11 18 PO 3 2 PO 9 8 19 PO 11 10 20 P6 3 0 21 P2 13 8 22 PO 5 4 PO 13 12 23 PO 7 6 PO 15 14 P5 1 0 Data Sheet 58 V 1 4 1 2014 05 Cin
83. n Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 95 P1 9 OO A1 Port 1 General Purpose I O Line 9 IN25 PU GPTAO Input 25 IN49 l GPTAO Input 49 MRST1B l SSC1 Master Receive Input B Master Mode OUT25 01 GPTAO Output 25 OUT49 O2 GPTAO Output 49 MRST1B O3 SSC1 Slave Transmit Output B Slave Mode 96 P1 10 OO A1 Port 1 General Purpose I O Line 10 IN26 PU GPTAO Input 26 IN50 l GPTAQ Input 50 OUT26 01 GPTAO Output 26 OUT50 O2 GPTAO Output 50 SLSO17 O3 SSC1 Slave Select Output 7 97 P1 11 OO A1 Port 1 General Purpose I O Line 11 IN27 PU GPTAO Input 27 IN51 l GPTAO Input 51 SCLK1B l SSC1 Clock Input B OUT27 O1 GPTAO Output 27 OUT51 O2 GPTAO Output 51 SCLK1B O3 SSC1 Clock Output B 73 P1 12 OO A1 Port 1 General Purpose I O Line 12 IN16 PU ILTCA2 Input 16 ADOEMUXO JO1 ADCO External Multiplexer Control Output 0 ADOEMUXO O2 ADCO External Multiplexer Control Output 0 OUT16 O3 LTCA2 Output 16 72 P1 13 OO A1 Port 1 General Purpose I O Line 13 IN17 PU LTCA2 Input 17 ADOEMUX1 JO1 ADCO External Multiplexer Control Output 1 ADOEMUX1 O2 ADCO External Multiplexer Control Output 1 OUT17 O3 LTCA2 Output 17 Data Sheet 25 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration
84. ncy corr CC MHz Data Sheet 82 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 29 FADC Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition Converter clock ADE 1 90 MHz frapc fep SC SAK TC1782F 320F180HR S AK TC1782F 320F180HL S AK TC1782N 320F180HR S AK TC1782N 320F180HL S AK TC1782N 256F133HR S AK TC1782N 256F133HL 1 m 80 MHZ franc pi SAK TC1782F 320F160HR S AK TC1782F 320F160HL S AK TC1782N 320F160HR S AK TC1782N 320F160HL Conversion time i CC 21 1 For 10 bit franc conversion Input resistance of the Reain 100 200 kOh analog voltage path Rn CC m Rp Settling time of a channel ftse CC 5 HS amplifier after changing ENN or ENP Analog input voltage Vane VEAGND Voomr V range SR Analog reference ground Veacnn Vssar Vssar V SR 0 05 0 05 Analog reference voltage Vearer 3 0 3 63 IV SR 6 Data Sheet 83 V 1 4 1 2014 05 infineon ses Electrical ParametersDC Parameters This value applies in power down mode N No missing codes Calibration should be preformed at each power up In case of a continous operation it should be performed minimium once per week S gt The offser error voltage drifts over the whole temperature range maximum 3LSB 9 Voltage overshoot to AV
85. nd Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 159 P6 3 O00 A1 Port 6 General Purpose I O Line 3 IN25 ig LTCA2 Input 25 SOPOA 01 MSCO Serial Data Output Positive A OUT83 O2 GPTAO Output 83 OUT7 O3 LTCA2 Output 7 Analog Input Port 67 ANO l D ADCO Analog Input Channel 0 66 AN1 l D ADCO Analog Input Channel 1 65 AN2 l D ADCO Analog Input Channel 2 64 AN3 l D ADCO Analog Input Channel 3 63 AN4 l D ADCO Analog Input Channel 4 62 AN5 l D ADCO Analog Input Channel 5 61 ANG l D ADCO Analog Input Channel 6 36 AN7 l D ADCO Analog Input Channel 7 60 AN8 l D ADCO Analog Input Channel 8 59 AN9 l D ADCO Analog Input Channel 9 58 AN10 l D ADCO Analog Input Channel 10 57 AN11 l D ADCO Analog Input Channel 11 56 AN12 l D ADCO Analog Input Channel 12 55 AN13 l D ADCO Analog Input Channel 13 50 AN14 l D ADCO Analog Input Channel 14 49 AN15 l D ADCO Analog Input Channel 15 48 AN16 l D ADC1 Analog Input Channel 16 47 AN17 l D ADC1 Analog Input Channel 17 46 AN18 l D ADC1 Analog Input Channel 18 45 AN19 l D ADC1 Analog Input Channel 19 44 AN20 l D ADC1 Analog Input Channel 20 43 AN21 l D ADC1 Analog Input Channel 21 42 AN22 l D ADC1 Analog Input Channel 22 41 AN23 l D ADC1 Analog Input Channel 23 Data Sheet 37 V 1 4 1 2014 05 Cinfineon SE PinningTC1782 Pin Configuration
86. nput Leakage Current lozr CC 6000 6000 nA VS Vppp 2 Class F 1 V Me Vppp 2 1V V20V Me Vopp V 3000 3000 nA VP Vopp 2 1 V V lt Vppp 2 1V Ratio Vil Vih F pads Mur 0 6 Vine CC On Resistance of the RpsonM 170 Ohm Lous 2 mA class F pad medium CC P_MOS driver 175 Ohm Ioy lt 2 mA P MOS Vppp2t5 Vp DP 145 Ohm g 2 mA N MOS Data Sheet 71 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 24 Standard Pads Class F cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition Fall time pad type F fer CC Mi 60 ns C 7 50 pF CMOS mode Rise time pad type F tap CC 60 ns C 50 pF CMOS mode Input high voltage pad VHE SR 0 6x min V V class F CMOS mode Monn DDP 0 3 3 6 Input low voltage Class F Vic SR 0 3 0 36 x IV pads CMOS mode Vopp Output high voltage class Vonr Mopp V Top 1 4 mA F pads CMOS mode CC 0 4 2 4 V Toz 2 MA Output low voltage class Vopr CC 0 4 V Io s2mA F pads CMOS mode 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 25 Standard Pads Class Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis Class HY
87. ns TCLK rising edge 1 The following formula is valid t11 t12 t10 2 The min max TCLK low high times t11 t12 include the PLL jitter of fSYS Fractional divider settings must be regarded additionally to t11 t12 3 For high speed MLI interface strong driver sharp or medium edge selection class A2 pad is recommended for TCLK 5 3 8 2 Micro Second Channel MSC Interface Timing The MSC parameters are vaild for C 50 pF Table 40 MSC Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition FCLP clock period ta CC 2x Tusc ns SOP ENx outputs delay from FCLP rising edge tas CC ns ENx with strong driver and sharp minus edge 2 10 ns ENx with strong driver and medium minus edge 21 ns ENx with strong driver and soft edge Data Sheet 108 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersAC Parameters Table 40 MSC Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition SDI bit time Le CC 8x ns Tusc SDI rise time Lg SR l 200 ins SDI fall time Le SR l 200 ns 1 FCLP signal rise fall times are only defined by the pad rise fall times 2 FCLP signal high and low can be minimum 1xTysc 3 A 5 TMSC TSYS 1 fSYS SOP FCLP either propa
88. odule GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management e 32 analog input lines for ADC 2 independent kernels ADCO and ADC1 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fkap clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 86 digital general purpose I O lines GPIO 4 input lines Digital I O ports with 3 3 V capabilitv On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Bus Dedicated Emulation Device chip available TC1782ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 6 V 1 4 1 2014 05 Cinfineon PS Summarv of Features The SAK TC1782F 320F160HR SAK TC1782F 320F160HL has the following features High performance 32 bit super scalar TriCore V1 3 1 CPU with 4 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit FPU 160 MHz operation at full temperature range 32 bi
89. ough the Vbpm power supply In case of discharging the reference capacitance through the ESD diodes the current must be lower than 5 mA Data Sheet 95 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersAC Parameters 5 3 3 Power Pad and Reset Timing Table 33 Reset Timings Parameters Parameter Svmbol Values Unit Note Min Typ Max Test Condition Application Reset Boot tg CC 150 810 HS SAK TC1782N Time 256F133HR SAK TC1782N 256F133HL 150 665 HS SAK TC1782F320F1 80HR SAK TC1782F320F1 80HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL 150 740 HS SAK TC1782F 320F160HR SAK TC1782F 320F160HL S AK TC1782N 320F160HR SAK TC1782N 320F160HL Power on Reset Boot tgp CC 2 5 ms Time HWCFG pins hold time fun SR 16 i ns from ESRO rising edge Ion HWCFG pins setup time to tes CC 0 Ge ns ESRO rising edge Ports inactive after ESRO tjj CC m 8 frp NS reset active Ports inactive after pp CC 150 ns PORST reset active Data Sheet 96 V 1 4 1 2014 05 infineon TC1782 Electrical ParametersAC Parameters Table 33 Reset Timings Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition Minimum PORST active tpg CC 10 ms time after power supplies are stable at operating levels TESTMODE TRST hold fpon SR 100 ns time from PORST rising edge POR
90. ply CC current 3 3V FADC analog Jppme 15 mA supply current CC 3 3V Current Jupe 12 mA for all LVDS pads in total Consumption of CC LVDS Pad Pairs ADC SV power Ippy CC 2 mA supply current Data Sheet 89 V 1 4 1 2014 05 Cinfineon Table 32 TC1782 Power Supply Parameters cont d Electrical ParametersDC Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition Maximum power dissipation PDCC 1143 mW power pattern max SAK TC1782N 256F 133HR SAK TC1782N 256F 133HL 1231 mW power pattern max SAK TC1782F320F180HR SAK TC1782F320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F 180HL 1231 mW power pattern max SAK TC1782F 320F160HR SAK TC1782F 320F 160HL SAK TC1782N 320F 160HR SAK TC1782N 320F 160HL 957 mW power pattern realistic SAK TC1782N 256F133HR SAK TC1782N 256F133HL V5571 326 V 994 mW power pattern realistic SAK TC1782F320F180HR SAK TC1782F320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL Vpp 1 326 V 979 mW power patternz realistic SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL Vpp 1 326 V 1 Infineon Power Loop CPU and PCP running all peripherals active The power consumption of each customer application will most probably be lower than this value but must be evaluated seperately op
91. pply Grade 150 C 1 A 3 3 V LVTTL Ai 6 MHz 100 pF 500 nA No I O e g GPIO LVTTL At 25 50pF 14A Series outputs e g serial MHz termination I Os recommended A2 40 50 pF 3 pA Series e g serial MHz termination l Os recommended F 3 3 V LVDS 50 Parallel MHz termination 100 Q 10 CMOS 6 MHz 50 pF De 5V ADC I 3 3 V LVTTL input only 1 These values show typical application configurations for the pad Complete and detailed pad parameters are available in the individual pad parameter table on the following pages 2 In applications where the LVDS pins are not used disabled these pins must be either left unconnected or properly terminated with the differential parallel termination of 100 10 Data Sheet 46 V 1 4 1 2014 05 Cinfineon TC1782 5 1 3 Electrical ParametersGeneral Parameters Absolute Maximum Ratings Stresses above the values listed under Absolute Maximum Ratings mav cause permanent damage to the device This is a stress rating only and functional operation of the device at these or anv other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions may affect device reliability Table 14 Absolute Maximum Rating Parameters Parameter Symbol Values Unit
92. put 60 OUT4 O3 LTCA2 Output 4 167 P0 5 OO A1 Port 0 General Purpose I O Line 5 IN5 PU GPTAOInput5 IN5 l LTCA2 Input 5 HWCFG5 l Hardware Configuration Input 5 OUT5 01 GPTAO Output 5 OUT61 O2 GPTAO Output 61 OUT5 03 LTCA2 Output 5 173 P0 6 lOO A1 Port 0 General Purpose I O Line 6 ING PU GPTAO Input 6 ING l LTCA2 Input 6 HWCFG6 l Hardware Configuration Input 6 REQ2 l External Request Input 2 OUT6 01 GPTAO Output 6 OUT62 O2 GPTAO Output 62 OUT6 O3 LTCA2 Output 6 Data Sheet 20 V 14 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 174 P0 7 OO A1 Port 0 General Purpose I O Line 7 IN7 PU GPTAO Input 7 IN7 LTCA2 Input 7 HWCFG7 l Hardware Configuration Input 7 REQ3 l External Request Input 3 OUT7 01 GPTAO Output 7 OUT63 02 GPTAO Output 63 OUT7 O3 LTCA2 Output 7 149 P0 8 O00 A1 Port 0 General Purpose I O Line 8 IN8 PU GPTAO Input 8 IN8 l LTCA2 Input 8 RXDAO I E Ray Channel A Receive Data Input 0 OUT8 01 GPTAO Output 8 OUT64 02 GPTAO Output 64 OUT8 03 LTCA2 Output 8 150 P0 9 OO A1 Port 0 General Purpose I O Line 9 INQ PU GPTAO Input 9 INQ l LTCA2 Input 9 RXDBO E Ray Channel B Receive Data Input 0
93. r Vop ppar 1 17 V to 1 43 V Vppy 4 5 V to 5 5 V Table 27 ADC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Switched capacitance at Cainsw 9 20 pF the analog voltage inputs CC Total capacitance of an Caintot 20 30 pF analog input CC Switched capacitance at Capersw 15 30 pF the positive reference CC voltage input 3 Total capacitance of the O Caperto 20 40 pF voltage reference inputs Des Differential Non Linearity EApy 3 3 LSB JADC Error CC resolution 12 bit 9 9 Gain Error 99 EAgan 95 l 3 5 LSB ADC CC resolution 12 bit 9 9 Integral Non EA y 3 3 LSB JADC Linearity CC resolution 12 bit 9 9 Offset Error 997 EAorr 4 4 LSB ADC CC resolution 12 bit 9 9 Data Sheet 74 V 1 4 1 2014 05 Cinfineon TC1782 Table 27 ADC Parameters cont d Electrical ParametersDC Parameters Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Converter clock fanc SC 90 MHz Saoc Sep SAK TC1782F 320F180HR S AK TC1782F 320F180HL S AK TC1782N 320F180HR S AK TC1782N 320F180HL S AK TC1782N 256F133HR S AK TC1782N 256F 133HL 80 MHz Saoc frp SAK TC1782F 320F160HR S AK TC1782F 320F160HL S AK TC1782N 320F160HR S AK TC1782N 320F160HL Internal ADC clock apc CC 18
94. ral Purpose I O Line 12 RXDCANO JI PU CAN Node 0 Receiver Input RXDOB l ASCO Receiver Input B RXDOB 01 ASCO Receiver Output B Synchronous Mode RXDOB O2 ASCO Receiver Output B Synchronous Mode OUT94 O3 GPTAO Output 94 142 P3 13 OO A2 Port 3 General Purpose I O Line 13 TXDCANO 01 PU CAN Node 0 Transmitter Output TXDO O2 ASCO Transmit Output OUT95 03 GPTAO Output 95 134 P3 14 OO A1 Port3 General Purpose I O Line 14 RXDCAN1 JI PU CAN Node 1 Receiver Input RXD1B l ASC1 Receiver Input B SDI2 l MSCO Serial Data Input 2 RXD1B O1 ASC1 Receiver Output B Synchronous Mode RXD1B O2 ASC1 Receiver Output B Synchronous Mode OUT96 O3 GPTAO Output 96 Data Sheet 31 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 133 P3 15 lOO A2 Port 3 General Purpose I O Line 15 TXDCAN1 01 IPU CAN Node 1 Transmitter Output TXD1 O2 ASC1 Transmit Output OUT97 O3 GPTAO Output 97 Port 4 86 P4 0 OO A1 Port 4 General Purpose I O Line 0 IN28 PU GPTAO Input 28 IN52 l GPTAQ Input 52 RXDCAN2 l CAN Node 2 Receiver Input OUT28 01 GPTAO Output 28 OUT52 O2 GPTAO Output 52 Reserved O3 87 P4 1 OO A1 Port 4
95. rating Timing Profiles 1 3 1 439 V SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL for duration limitation see Voltage Operating Timing Profiles Oscillator 3 3V supply voltage Voposc3 SR 2 97 3 3 3 639 V for duration limitation see Voltage Operating Timing Profiles Digital supply voltage for IO pads Vopp SR 2 97 3 3 3 63 9 for duration limitation see Voltage Operating Timing Profiles Data Sheet 55 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersGeneral Parameters Table 18 Operating Conditions Parameters cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition VDDP voltage to ensure defined pad states VopPPA CC 0 65 Digital ground voltage Vss SR 0 lt Analog ground voltage for Voom Vssm SR 0 1 0 1 Analog core supply Vopar SR 1 235 1 365 V SAK TC1782F 320F180HR SAK TC1782F 320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL SAK TC1782N 256F133HR SAK TC1782N 256F133HL for duration limitation see Voltage Operating Timing Profiles 1 3 1 439 V SAK TC1782F 320F160HR SAK TC1782F 320F160HL SAK TC1782N 320F160HR SAK TC1782N 320F160HL for duration limitation see Voltage Operating Timing Pro
96. t Application relevant values are typically lower than those given in the following two tables and depend on the customer s system operating conditions e g thermal connection or used application configurations The operating conditions for the parameters in the following table are Vpp 1 365 V Vppp73 47 V Vopw 5 1 V fimp 180 160 MHz 133 MHz T 150 C The realisic power pattern defines the following conditions e T 150 C ra foop fopu 180 160 MHz 133 MHz Le 90 MHz 80 MHz 66 5 MHz Vop Voposc Vopar 1 326 V 5 Vopp Vpposcs Vopris Vopwr 3 366 V Voom 5 1 V The max power pattern defines the following conditions e T 150 C fue fece fopy 180 160 MHz 133 MHz f p 90 MHz 80 MHz 66 5 MHz Voo Voposc Vppar 1 365 V 1 43 V 1 365 V one Vpposcs Voorus Vopmr 3 47 V 3 63 V 3 47 V Voom 5 5 V Data Sheet 87 V 1 4 1 2014 05 Cinfineon Table 32 TC1782 Power Supplv Parameters Electrical ParametersDC Parameters Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Core active mode supplv current ho CE 486 mA power pattern max SAK TC1782N 256F133HR SAK TC1782N 256F133HL 5509 mA power pattern max SAK TC1782F320F180HR SAK TC1782F320F180HL SAK TC1782N 320F180HR SAK TC1782N 320F180HL 5509 mA power pattern max SAK TC1782F 320F160HR SAK TC1782F 320F16
97. t driver medium 2 4 Top 2 mA pin out driver medium Vopp 0 4 Toy 400 uA pin out driver weak 2 4 Toy 500 uA pin out driver weak Output voltage low class A1 pads Vorat CC 0 4 Ig 2 mA pin out driver medium 0 4 Jon S 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 22 Standard Pads Class A1 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis forA1 HYSA 0 1x V pads CC Monn Input Leakage Current loza l 1000 1000 nA Class A1 CC On Resistance of the Rpsonw 450 600 Ohm lous 0 5 mA class A1 pad weak CC P_MOS driver 210 340 Ohm Jos 0 5 mA N MOS Data Sheet 62 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 22 Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition On Resistance of the class A1 pad medium driver Rosonm CC 155 Ohm Iop lt 2 mA P_MOS 110 Ohm Io lt 2 MA N_MOS On Resistance of the class A1 pad strong driver Roson1 CC 100 Ohm Lag 2 mA P MOS 80 Ohm Ig 2 mA N MOS Fall time pad
98. t driver medium 65000 ns C 20000 pF pin out driver weak Input high voltage class A2 pads ViHaz SR 0 6 x Mons min V DDP 0 3 3 6 Input low voltage Class A2 pads Vaz SR 0 3 0 36 x Vopp Output voltage high class A2 pads VoHaz CC Vopp 0 4 Top 1 4 mA pin out driver medium Vopp 0 4 Tone 1 4 mA pin out driver strong 2 4 Io 2 MA pin out driver medium 2 4 Io 2 MA pin out driver strong Vope 0 4 Toyz 400 pA pin out driver weak 2 4 Toz 500 pA pin out driver weak Data Sheet 70 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 23 Standard Pads Class A2 cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Output voltage low class A2 pads VoLa2 CC 0 4 Io s 2 mA pin out driver medium 0 4 Jo 2 mA pin out driver strong 0 4 Ig 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 24 Standard Pads Class F Parameter Svmbol Values Unit Note Min Typ Max Test Condition Input Hysteresis F HYSF 0 05x V cc Vopp I
99. t Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 160 MHz operation at full temperature range Multiple on chip memories 2 5 Mbyte Program Flash Memory PFLASH with ECC 128 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 128 Kbyte Data Memory LDRAM Instruction Cache up to 16 Kbyte ICACHE configurable 40 Kbyte Code Scratchpad Memory SPRAM Data Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Three High Speed Synchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects
100. ta Cache up to 4 Kbyte DCACHE configurable 8 Kbyte Overlay Memory OVRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Local Memory Buses between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge LFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Three High Speed Synchronous Serial Channels SSC with programmable data length and shift direction One serial Micro Second Bus interface MSC for serial port expansion to external power devices One High Speed Micro Link interface MLI for serial inter processor communication One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality Data Sheet 3 V 1 4 1 2014 05 Cinfineon PS Summarv of Features One General Purpose Timer Arrav Module GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management e 32 analog input lines for ADC 2
101. ter Symbol Values Min Typ Max Unit Note Test Condition 550 ns Cu 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet V 1 4 1 2014 05 Cinfineon TC1782 Table 23 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition Rise time pad tvpe A2 trag CC 150 ns C 20 pF pin out driver weak 7 0 ns C 50 pF edge medium pin out driver strong 10 ns C 50 pF edge medium minus pin out driver strong 3 7 ns C 50 pF edge sharp pin out driver strong ns C 50 pF edge sharp minus pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 50 pF pin out driver medium 7 5 ns C 7 100 pF edge sharp pin out driver strong 140 ns C 150 pF pin out driver medium Data Sheet 69 V 1 4 1 2014 05 Cinfineon TC1782 Electrical ParametersDC Parameters Table 23 Standard Pads Class A2 cont d Parameter Svmbol Values Min Tvp Max Unit Note Test Condition 550 ns C z 150 pF pin out driver weak 18000 ns C 20000 pF pin ou
102. terisitics for positive Overload Pad Tvpe ln 3 mA liy 5 mA A1 A1 F Uy Vppp 0 6 V Un Vopr 0 7 V A2 Un Vopr 0 5 V Un Vopr 0 6 V LVDS Un Vppp 0 7 V D Un Voom 0 6 V Table 17 PN Junction Characterisitics for negative Overload Pad Type ln 3 MA ln 5 mA A1 A1 F_ Un Vss 0 6 V Un Vss 0 7 V A2 Un Vss 0 5 V Un Vss 0 6 V LVDS Un Vss 0 7 V D Un Vssm 0 6 V Note A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life time Data Sheet 49 V 1 4 1 2014 05 Cinfineon es Electrical ParametersGeneral Parameters 5 1 5 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliabilitv of the TC1782 Digital supplv voltages applied to the TC1782 must be static regulated voltages which allow a typical voltage swing of 5 All parameters specified in the following tables refer to these operating conditions Table 18 unless otherwise noticed in the Note Test Condition column The Voltage Operating Timing Profiles did not increase area of validity of the parameters defined in table 8 and later Table 18 Operating Conditions Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max Overload
103. tput 76 OUT20 O3 LTCA2 Output 20 Data Sheet 23 V 1 4 1 2014 05 Cinfineon SE PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 108 P1 5 00 A1 Port 1 General Purpose I O Line 35 IN21 PU GPTAO Input 21 IN21 l LTCA2 Input 21 OUT21 01 GPTAO Output 21 OUT77 O2 GPTAO Output 77 OUT21 O3 LTCA2 Output 21 109 P1 6 OO A1 Port 1 General Purpose I O Line 6 IN22 PU GPTAO Input 22 IN22 l LTCA2 Input 22 OUT22 O1 GPTAO Output 22 OUT78 O2 GPTAO Output 78 OUT22 O3 LTCA2 Output 22 110 P1 7 lOO A1 Port 1 General Purpose I O Line 7 IN23 PU GPTAO Input 23 IN23 l LTCA2 Input 23 OUT23 01 GPTAO Output 23 OUT79 O2 GPTAO Output 79 OUT23 O3 LTCA2 Output 23 94 P1 8 OO A1 Port 1 General Purpose I O Line 8 IN24 PU GPTAO Input 24 IN48 l GPTAQ Input 48 MTSR1B l SSC1 Slave Receive Input B Slave Mode OUT24 O1 GPTAO Output 24 OUT48 O2 GPTAO Output 48 MTSR1B O3 SSC1 Master Transmit Output B Master Mode Data Sheet 24 V 1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pi
104. trical ParametersPackage and Reliabilitv Table 45 FLASH32 Parameters cont d Parameter Svmbol Values Unit Note Min Typ Max Test Condition DFlash wait state WSpr 50 ns x l configuration CC fesi PFlash wait state WSpr 26 ns x configuration CC fesi 1 Incase of wordline oriented defects see robust EEPROM emulation in the User s Manual this erase time can increase by up to 100 2 3 2 oe 5 ms 5 ms Storage and inactive time included In case the Program Verify feature detects weak bits these bits will be programmed up to twice more Each reprogramming takes additiona In case the Program Verify feature detects weak bits these bits will be programmed once more The reprogramming takes additiona Only valid when a robust EEPROM emulation algorithm is used For more details see the User s Manual At average weighted junction temperature 7 100 C or the retention time at average weighted temperature of T 110 C is minimum 10 years or the retention time at average weighted temperature of 7 150 C is minimum 0 7 years 5 4 4 Quality Declarations Table 46 Quality Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max Operation top 24000 hours l 2 Lifetime ESD susceptibility Vi 2000 V Conforming to according to JESD22 A114 B Human Body Model HBM ESD susc
105. ved 03 Data Sheet 35 V1 4 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions and Functions PG LQFP 176 10 PG LQFP 176 20 Package cont d Pin Symbol Ctrl Type Function 19 P5 14 00 A1 Port 5 General Purpose I O Line 14 TREADVOB li PU MLIO Transmitter Ready Input B RXDA1 I E Ray Channel A Receive Data Input 1 Reserved O1 Reserved O2 OUT94 O3 LTCA2 Output 94 9 P5 15 OO JA14 Port 5 General Purpose I O Line 15 RXDB1 PU E Rav Channel B Receive Data Input 1 TCLKO O1 MLIO Transmitter Clock Output Reserved O2 OUT95 O3 LTCA2 Output 95 Port 6 156 P6 0 OO A1 Port 6 General Purpose I O Line 0 IN14 F LTCA2 Input 14 FCLNO O1 CS MSCO Clock Output Negative OUT80 02 GPTAO Output 80 OUT4 O3 LTCA2 Output 4 157 P6 1 lOO A1 Port 6 General Purpose I O Line 1 IN15 F LTCA2 Input 15 FCLPOA 01 ES MSCO Clock Output Positive A OUT81 O2 GPTAO Output 81 OUT5 O3 LTCA2 Output 5 158 P6 2 O00 A1 Port 6 General Purpose I O Line 2 IN24 F LTCA2 Input 24 SONO O1 S MSCO Serial Data Output Negative OUT82 O2 GPTAO Output 82 OUT6 O3 LTCA2 Output 6 Data Sheet 36 V 14 1 2014 05 Cinfineon TC1782 PinningTC1782 Pin Configuration Table 2 Pin Definitions a
106. wo wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL Data Sheet 10 V 1 4 1 2014 05 Cinfineon PS Summarv of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product This ordering code identifies The derivative itself i e its function set the temperature range and the supply voltage The package and the type of delivery For the available ordering codes for the TC1782 please refer to the Product Catalog Microcontrollers which summarizes all available microcontroller variants This document describes the derivatives of the device The Table 1 enumerates these derivatives and summarizes the differences Table 1 TC1782 Derivative Synopsis Derivative Ambient Temperature Range Package SAK TC1782F 320F180HR T 40 C to 125 C PG LQFP 176 20 SAK TC1782F 320F 180HL Ta 40 C to 125 C PG LQFP 176 10 SAK TC1782N 320F180HR T 40 C to 125 C PG LQFP 176 20 SAK TC1782N 320F180HL Ta 40 C to 125 C PG LQFP 176 10 SAK TC1782N 256F133HR T 40 C to 125 C PG LQFP 176 20 SAK TC1782N 256F 133HL Ta 40 C to 125 C PG LQFP 176 10 SAK TC1782F 320F160HR T 40 C to 125 C PG LQFP 176 20 SAK TC1782F 320F160HL T4 40 C to 125 C PG LQFP 176 10 SAK TC1782N 320F160HR T 40 C to 125 C PG LQFP 176 20 SAK TC1782N 320F 160HL TA 40 C to 125 C PG LQ
107. z ETT MENT JE A ka 7 else Dm ns ee nee S K2 x fi mp MHz With rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2 factor of the PLL Beyond this value of m the maximum Data Sheet 99 V 1 4 1 2014 05 Cinfineon es Electrical ParametersAC Parameters accumulated jitter remains at a constant value Further a lower LMB Bus clock frequency fi mg results in a higher absolute maximum jitter value Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF with the maximum driver and sharp edge Note The maximum peak to peak noise on the pad supplv voltage measured between Vpposcs and V ssosc S limited to a peak to peak voltage of Vpp 100 mV for noise frequencies below 300 KHz and Vpp 40 mV for noise frequencies above 300 KHz The maximum peak to peak noise on the pad supply voltage measured between Vpposc and V ssosc is limited to a peak to peak voltage of V pp 100 mV for noise frequencies below 300 KHz and Vpp 40 mV for noise frequencies above 300 KHz These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes Oscillator Watchdog OSC WDT The expected input frequency is selected via the bit field SCU OSCCON OSCVAL The OSC WDT checks for too low frequencies and for too high frequencies The frequ

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