XEM6310 User`s Manual
Contents
1. s Opal Kelly XEMO6310 User s Manual A compact 75mm x 50mm integration board featur ing the Xilinx Spartan 6 FPGA SuperSpeed USB 3 0 on board DDR2 memory and two 16 MiB Flash memories The XEM6310 is a compact USB 3 0 SuperSpeed FPGA integration module featuring the Xilinx Spar tan 6 FPGA 1 Gib 64 Mx16 bit DDR2 SDRAM two 128 Mib SPI Flash devices high efficiency switch ing power supplies and two high density 0 8 mm expansion connectors The USB 3 0 SuperSpeed interface provides fast configuration downloads and PC FPGA communication as well as easy access with our popular FrontPanel application and SDK A low jitter 100 MHz crystal oscillator is attached to the FPGA Software documentation samples and related materials are Copyright 2014 2015 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision Hi2. 796 25 546 feo ais tsino 25284 28 088 2835 26 666 18 067 8 059 JP1 Length Pin Connection FPGA Pin mm 2 penn T a zw L23P 2 51 413 L43P 2 40 650 1 2VDD T14 L43N_2 49 296 L74P_1 48 345 18 805 14 616 44 403 41 096 10 730 14 240 14 500 28 674 28 161 mE 25918 26 538 26 347 NO VCCOO 26 087 C10 D11 C12 D15 3 220 2 838 2 432 6 492 L4P 0 LAN O L5P 0 VCCOO L62P 0 33 397 L62N VREF 0 L5N O 3 118 0 906 LN GcLKi2 0 20 714 Iso 21102 sono 20868 Loro 24 806 Leno 24536 tese o 267755 6 112 8 080 N N N NININ N OD m a OA O BIBKIBIBIR PO O MIWIWIN N N IN 2 gt gt gt gt oio gt A O BIN O DIBIN O 0 O NJ JO O DIBINJ O O DIBIN O O DI BIN O gt gt gt PIOQ P O O O O A mE A gt lt EN HEN dol NIO oo NI W o Oo AB N Oo O co O o www opalkelly com XEM6310 User s Manual 25
3. allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by the XEM6310 by allowing the user to connect independent supplies to the FPGA VCCO pins on two of the FPGA banks By default ferrite beads have been installed that attach each VCCO bank to the 3 3VDD supply If you intend to supply power to a particular I O bank you MUST remove the appropriate ferrite beads Power can then be supplied through the expansion connectors The table below lists details for user supplied I O bank voltages I O Bank Ferrite Bead lo JP1 36 56 JP2 35 55 Considerations for Differential Signals The XEM6310 PCB layout and routing has been designed with several applications in mind including applications requiring the use of differential LVDS pairs Please refer to the Xilinx Spartan 6 datasheet for details on using differential I O standards with the Spartan 6 FPGA Note LVDS output on the Spartan 6 is restricted to banks 0 and 2 LVDS input is available on all banks For more information please refer to the Spartan 6 FPGA SelectlO Resources User Guide from Xilinx www opalkelly com XEM6310 User s Manual FPGA I O Bank Voltages In order to use differential I O standards with the Spartan 6 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Spartan 6 datasheet Please see the sec tion above entitled Setting I O Voltages
4. clock rate of the SDRAM is 333 MHz With the 2 speed grade of the Spartan 6 the maximum clock rate is 312 5 MHz for a supported peak memory bandwidth of 10 Gb s The DDR2 SDRAM is a Micron MT47H64M16HR 3 G or compatible FPGA Flash 16 MiB Serial Flash Memory A 128 Mib serial flash device Numonyx N25Q128A11B1240E or equivalent provides on board non volatile storage for the FPGA This device is attached directly to the FPGA for use in your design oystem Flash 16 MiB Serial Flash Memory A 128 Mib serial flash device Numonyx N25Q128A11B1240E or equivalent provides on board non volatile storage accessible to the USB microcontroller This device is used to store device firmware and configuration settings as well as other user assets such as FPGA configuration files or calibration data Erase read and write functions are available at all times with or without a configured FPGA through the use of FrontPanel API methods LEDs Eight LEDs and are available for general use as indicators www opalkelly com TA XEM6310 User s Manual Expansion Connectors Two high density 80 pin expansion connectors are available on the bottom side of the XEM6310 PCB These expansion connectors provide user access to several power rails on the XEM6310 the JTAG interface on the FPGA and 124 non shared I O pins on the FPGA including several GCLK inputs The connectors on the XEM6310 are Samtec part number BSE 040 01 F D A The table below li
5. est 250mw konn J T_ ste T_T Example XEM6310 LX150 FPGA Power Consumption XPower Estimator version 12 3 was used to compute the following power estimates for the Vc CINT supply These are simply estimates your design requirements may vary considerably The numbers below indicate approximately 70 to 80 utilization CT mem 2230 mW E Available 2400 mW Supply Heat Dissipation MPORTANT Due to the limited area available on the small form factor of the XEM6310 and the density of logic provided heat dissipation may be a concern This depends entirely on the end application and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM6310 Of primary focus should be the FPGA U5 and SDRAM U7 Although the switching supplies are high efficiency they are very compact and consume a small amount of PCB area for the current they can provide If you plan to put the XEM6310 in an enclosure be sure to consider heat dissipation in your design 10 www opalkelly com XEM6310 User s Manual Host Interface There are 41 signals that connect the on board USB microcontroller to the FPGA These signals comprise the host interface on the FPGA and are used for configuration downloads After con figuration these signals are used to allow FrontPanel communication with the FPGA If the FrontPanel okHost module is instantiated in your design you must map the interfa
6. for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is approxi mately 50 Q Differential Pair Lengths In many cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application Due to space con straints some pairs are better matched than others Reference Voltage Pins VREF The Xilinx Spartan 6 supports externally applied input voltage thresholds for some input signal standards The XEM6310 supports these VREF applications for banks 0 and 1 For Bank O the four VREF pins are routed to expansion connector JP1 on pins 48 51 62 and 65 Note that all four must be connected to the same voltage for proper application of input thresh olds Please see the Xilinx Spartan 6 documentation for more details For Bank 1 the four VREF pins are connected to a single pin on expansion connector JP2 pin 10 BRK6110 Breakout Board Pins The BRK6110 is a simple two layer breakout board which can be used to evaluate or transition to the XEM6310 It provides standard 2 mm thru hole connections to the 0 8 mm high density connectors on the XEM6310 and a DC power connector 2 1mm 5 5mm
7. A20 94 825 DGND MN DGND kt C2 BE N 4 102 4 092 3 VBAT 5 JTAG TCK 7 JTAG TMS 9 JTAG TDI a fuz 13 DGND 15 G16 17 f87 19 H9 21 He 23 26 FIT 27 IT 29 KI7 31 jke 133 M6 35 vecot 137 v2 39 v22 Ka eee 43 T22 as P 47 P22 49 M21 51 M22 53 L20 155 vecot 57 i2 59 H21 O 61 H22 63 F21 los F22 67 D21 69 D2 71 B21 73 B2 77 320 79 yee N 24 JP2 Length Pin Connection FPGA Pin mm 2 soo AE o savo mo RFUSE DGND G19 L33P 1 61 093 F20 61 369 H20 52 874 526 D19 48 369 D20 48 196 F18 40 724 F19 41 050 M16 30 348 L15 29 853 bob LA0P GCLKM 1 K20 LAOP GCLK11 1 29 273 K19 LAON GCLK10 1 29 267 NO U20 22 557 U22 22 965 R20 26 121 R22 25 746 N20 26 691 N22 26 043 M20 24 052 pen LA2N GCLKG 1 I I L19 LA2N GCLK6 1 24 190 K21 23 920 K22 23 603 G20 27 676 G22 27 153 E20 31 177 E22 31 491 C20 33 951 C22 33 893 A20 34 325 DGND bewo N N 4 www opalkelly com FPGA Pin XEM6310 Quick Reference JP1 Length Pin Connection FPGA Pin mm AS oea COO OoOo s wo 7 faso 5 avo f miso o Hs eso T s ow a9 pe Jono 21074 as e jao 1789 13 856 ss pomo 18 153 59 20 086 20 183 25035 24
8. T Reset filters Connector all Power all Ground all WO Power all VO all I O Bank all JTAG all Clock all FPGA Clockin all CONNECTOR PIN FPGA PIN DESCRIPTION LENGTH MM BRK6110 Connector FPGA Pin Description Length mm BRK6110 JP2 JP2 JP2 JP2 JP2 JP2 Vbatt DGND 3 3VDD VBATT 3 3VDD JTAG TCK 3 3VDD JP1A 1 JP1A 2 JP1A 4 JP3 6 JP1A 6 N DA uU RR W N Q JP2 JTAG_TMS JP3 4 Filters You can hide or show the additional information associated with each signal by clicking on the icon at the top left Toggle Filters Use these filters to limit the visible pin listing to particular subsets of signals you are interested in Search You can search the pin list using the search entry at the top right Click on the magnifying glass drop down to adjust the function of the search to one of e Highlight Highlights search results only e Hide Matching Hides rows where search matches are found e Show Only Matching Shows only rows where a search match is found Export PDF CSV Constraints Files The export button near the search entry allows you to export the pin list in several formats PDFs can be viewed or printed CSV can be loaded into a spreadsheet application or manipulated with scripts Constraints files can be used as inputs to Xilinx and Altera synthesis and mapping tools 18 www opalkelly com XEM6310 User s Manual The constraints files include additional mapping i
9. T 4 7 k 5 NoLoad DGND a BTI MS412FE FL26E NoLoad DGND Non Volatile Encryption Key Storage eFUSE Non volatile storage of the encryption key is also possible by programming the Spartan 6 eFUSE via JTAG Please see the Xilinx Spartan 6 FPGA Configuration User Guide UG380 for more details To program the eFUSE you must first install the components listed in the table below You must also provide an external resistor RFuse between JP2 12 and GND The value of this resistor is specified in the Xilinx Spartan 6 Datasheet DS162 between 1129 O and 1151 O RefDes Manufacturer Manufacturer P N C149 0 1 uF SM 0402 Decoupling 0 Q SM 0402 Connects FPGA Vrs to 3 3v 0 Q SM 0402 Connects FPGA Rruse to JP2 12 Expansion Connectors JP1 Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins JP1 is an 80 pin high density connector providing access to FPGA Banks 0 1 and 2 Several pins 42 44 59 61 64 66 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network www opalkelly com 15 XEM6310 User s M
10. anual 16 JP2 Pin mappings for JP1 are listed at the end of this document in the Quick Reference section For each pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs Note that JP1 pins 8 10 12 are attached to FPGA Bank 2 which is powered as a 1 8v bank This may not be changed JP2 is an 80 pin high density connector providing access to FPGA Bank 1 except for pin JP2 11 which is on Bank 2 Several pins 38 40 54 58 59 61 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock net work Pin JP2 10 is connected to the VREF pins of Bank 1 Pin mappings for JP2 are listed at the end of this document in the Quick Reference section For each pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs Note that JP2 pin 11 is attached to FPGA Bank 2 which is powered as a 1 8v bank This may not be changed Setting I O Voltages The Spartan 6 FPGA
11. ce pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file Please see the sample projects includ ed with your FrontPanel installation for examples Reset Profile RESET Pin AB8 of the FPGA is an active high RESET signal from the host interface This signal is as serted when configuration download begins and is deasserted during the execution of the Reset Profile For more information on the timing of this deassertion event see the FrontPanel User s Manual System Flash The Flash memory attached to the USB microcontroller stores device firmware and settings as well as user data that is accessible via the FrontPanel API The API includes three methods for accessing this memory FlashEraseSector FlashWrite and FlashRead Please refer to the FrontPanel User s Manual and the FrontPanel API Reference for information about applying these methods Layout The Numonyx N25Q128A11B1240E is a 16 MiB Flash memory arranged into 256 64 kiB sectors Each sector contains 256 256 byte pages Sectors 0 15 are reserved for device firmware and settings and are not accessible to user software The remaining 15 MiB may be erased written and read using the FrontPanel API at any time even without a valid FPGA configuration Full 64 kiB sectors must be erased at a time However contents may be read or written on any page address boundary Loadin
12. center positive for pro viding VDC to the XEM6310 Please visit the Pins reference for the XEM6310 for pin mapping details Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins Toolbar The toolbar at the top of a Pins product page has a number of features Explore a bit you won t break it www opalkelly com 17 XEM6310 User s Manual vam Click for column selection and filters yo Export PDF CSV or constraints file Drop down for search behaviors A B XEM6310 Click for symbol legend Pin Lists As the primary reference for Opal Kelly integration module expansion connectors Pin Lists con tain a comprehensive table of the FPGA to Connector data including connector pin FPGA pin signal description routed length when applicable breakout board pin mapping FPGA I O bank and other properties By default not all data columns are visible Click on the Toggle Filters icon at the top left to se lect which columns to show Depending on the specific module several additional columns may be shown The data in these columns is always exported when you export the pin list to CSV E XEM6310 CHOOSE PRODUC
13. e core datasheet Al though MIG can save a tremendous amount of development time understanding all this informa tion is critical to building a working DDR2 memory interface The XEM6310 provides 1 2v as Vccint According to the memory controller block documenta tion the Spartan 6 2 speed grade can operate memory to 312 5 MHz with this internal voltage MIG Settings The following are the settings used to generate the MIG core for our RAMTester sample using Xilinx Core Generator These settings were used with ISE 12 2 and MIG 2 3 Note that settings may be slightly different for different versions of ISE or MIG www opalkelly com 13 XEM6310 User s Manual JTAG Frequency 312 5 MHz Memory Type Component Memory Part MT47H64M16XX 3 1Gb x16 Data Width 16 Enable DQS Enable CHECKED High temp self refresh DISABLED Output drive strength Reducedstrength RT T nominal 50 ohms default DCI for DQ DQS CHECKED DCI for address control CHECKED ZIO pin Y2 RZQ pin K7 Calibrated Input Selection Yes Class for address control Class Il Debug signals Your option System clock Differential The JTAG connections on the FPGA are wired directly to the expansion connector JP2 on the XEM6310 to facilitate FPGA configuration and ChipScope usage using a Xilinx JTAG cable The BRK6110 has these signals connected to a 2 mm header compatible with the Xilinx JTAG cable Key Memory Storage LX150 only 14 The Spartan 6 FPGA supports desig
14. efault Enable the specific module features you would like to appear in the exported con straints file When a feature is enabled Output filename xem6310 ucf Pins will export the constraints appropri Export features ate to that feature such as pin locations When a feature is disabled Pins will skip that portion The User Lead In and User Lead Out sections allow you to add custom pay loads your own constraints that will be added to the exported constraints file Additional timing constraints or com ments can be added here www opalkelly com M Lead In M4 FrontPanel 4 FrontPanel Timing _ System Clock _ Reset _ User Lead In Add payload M LEDs _ FPGA Flash M DDR2 User Lead Out Add payload 19 XEM6310 User s Manual Migrating Hardware from the XEM6010 to the XEM6310 The XEM6310 was designed to be as compatible as possible with our XEM6010 in order to facili tate customer design migration with minimal changes The physical dimentions and connector footprints are identical The differences between these two products are highlighted below FPGA Boot Configuration The XEM6010 has a small flash memory attached to the FPGA that could be used for FPGA boot configuration The XEM6310 has a larger flash memory attached to the USB microcontroller that allows the microcontroller to boot from one of multiple boot imags stored The XEM6310 also has a separate flash memory attached to the FPGA that may not be used for b
15. egulator for use as a www opalkelly com XEM6310 User s Manual DDR2 termination voltage Each of the three switching regulators can provide up to 2A of cur rent DC Power Connector The DC power connector on the XEM6310 is part number PJ 102AH from CUI Inc It is a stan dard canon style 2 1mm 5 5mm jack The outer ring is connected to DGND The center pin is connected to VDC SuperSpeed USB 3 0 Interface The XEM6310 uses a Cypress CYUSB3014 BZXI FX3 USB microcontroller to make the XEM a USB 3 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peripheral on millions of PCs More importantly FPGA downloads to the XEM happen quickly virtual instruments under FrontPanel update quickly and data transfers are blazingly fast On board Peripherals The XEM6310 is designed to compactly support a large number of applications with a small num ber of on board peripherals These peripherals are listed below Low Jitter Crystal Oscillator A fixed frequency 100 MHz low jitter oscillator is included on board and outputs LVDS to the FPGA The Spartan 6 FPGA can produce a wide range of clock frequencies using the on chip DCM and PLL capabilities 128 MByte Word Wide DDR2 Synchronous DRAM The XEM also includes a 128 MiByte DDR2 SDRAM with a full 16 bit word wide interface to the FPGA This SDRAM is attached exclusively to the FPGA and does not share any pins with the expansion connector The maximum
16. esigned as a full featured integration system the XEM6310 provides access to over 110 I O pins on its 484 pin Spartan 6 device and has a 128 MiByte DDR2 SDRAM available to the FPGA Two SPI Flash devices provide a total of 32 MiB of non volatile memory one attached to the USB microcontroller and one attached to the FPGA Available with LX45 and LX150 FPGA densities the XEM6310 is designed for me dium to large sized FPGA designs with a wide variety of external interface requirements PCB Footprint A mechanical drawing of the XEM6310 is shown at the end of this manual The PCB is 75mm x 50mm with four mounting holes M2 metric screws spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM6310 The two connectors USB and DC power overhang the PCB by approximately 1mm in order to accommodate mount ing within an enclosure The XEM6310 has two high density 80 pin connectors on the bottom side which provide access to many FPGA pins power and JTAG BRK6110 Breakout Board A simple breakout board the BRK6110 is provided as an optional accessory to the XEM6310 This breakout board provides DC power JTAG connector and easy access to the high density connectors on the XEM6310 by routing them to lower density 2mm spaced thru holes The breakout board also provides a convenient reference for building boards that will mate to the XEM6310 www opalkelly com 5 XEM6310 User s Manual Opal Kell
17. g a Power On FPGA Configuration The user area in System Flash may be used to store a Xilinx bitfile to configure the FPGA at power on Power on configuration takes approximately 6 10 seconds from when power is ap plied A full Reset Profile may also be performed after configuration The API is used to erase and program the power on bitfile and the Flashloader sample is pro vided to perform these steps from a simple command line utility Source code to the Flashloader sample is included with the FrontPanel SDK Called with a single argument the filename for a valid Xilinx bitfile the Flashloader sample will erase the first sectors in the System Flash user area then write the bitfile It will also setup the Boot Reset Profile to point to this area on power on No Power On Configuration Called with no arguments the Flashloader sample will clear the existing Boot Reset Profile This has the effect of preventing an FPGA configuration from being loaded at power on This func tionality may also be accomplished from the API by setting an empty okTFPGAResetProfile using the API SetFPGABootResetProfile See the FrontPanel API Reference for details www opalkelly com 11 XEM6310 User s Manual FPGA Flash The SPI Flash attached to the FPGA is a Numonyx N25Q128A11B1240E or equivalent It pro vides non volatile storage for use by the FPGA It may not be used for FPGA configuration stor age The System Flash is used to store FPGA boot confi
18. gurations The Flash FPGA pin mappings are shown in the table below Flash Pin FPGAPin Dao o WS paz W D 3 HOLD LEDs There are eight LEDs on the XEM6310 in addition to the power LED Each is wired directly to the FPGA according to the pin mapping tables at the end of this document The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA on Bank 2 with a bank I O voltage of 1 8v To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be at logic 1 DDR2 SDRAM The Micron DDR2 SDRAM is connected exclusively to the 1 8 v I O on Bank 3 of the FPGA The tables below list these connections 12 www opalkelly com XEM6310 User s Manual po m De e pe a De e D14 Clock Configuration Source Synchronous The DDR2 clocking is designed to be source synchronous from the FPGA This means that the FPGA sends the clock signal directly to the SDRAM along with control and data signals allowing very good synchronization between clock and data Memory Controller Blocks Spartan 6 has integrated memory control blocks to communicate with the external DDR2 mem ory on the XEM6310 This is instantiated using the Xilinx Core Generator memory interface generator or MIG to create a suitable memory controller for your design You should read and become familiar with the DDR2 SDRAM datasheet as well as MIG and th
19. is supply must be delivered through the VDC pins on the two device s two expansion connec tors or the DC power connector The expansion bus has several power supply pins described below VDC is provided by an external device to the XEM6310 It must be a clean filtered sup ply within the range of 4 5 volts and 5 5 volts 3 3v is the output of a 2 Amp switching regulator on the XEM6310 1 8v is the output of a 2 Amp switching regulator on the XEM6310 1 2v is the output of a 2 Amp switching regulator on the XEM6310 VCCOO is the bank 0 I O voltage to the FPGA Factory default is 3 3v VCCO1 is the bank 1 I O voltage to the FPGA Factory default is 3 3v Power Budget The table below can help you determine your power budget for each supply rail on the XEM6310 All values are highly dependent on the application speed usage and so on Entries we have made are based on typical values presented in component datasheets or approximations based on Xilinx power estimator results Shaded boxes represent unconnected rails to a particular component Empty boxes represent data that the user must provide based on power estimates The user may also need to adjust parameters we have already estimated such as FPGA Vcco values where appropriate www opalkelly com 9 XEM6310 User s Manual moms DD Ken iso mw Dogg 600mw omw kon LE FPGA Veo DD Jesomw FPGA Voces DOR es 250mW FPGA Vcco2 USB
20. ks e 13 MILEES Ss EEE 19 T c 14 Key Memory Storage LX150 only 14 Volatile Encryption Key Storage VBATT 14 Non Volatile Encryption Key Storage eFUSE 15 Expansion Connectors sas AG NG NG Ri 15 i rE 15 lc PUPPI 16 Setting VO Vallages 4 do ace arridet e ak dv e ei 16 Considerations for Differential SignalS 16 BRK6110 Breakout Boa essre 17 Si AA cee pee eee AA dees Eus 17 ON 22e 224299 p satse d ii K dik bas qus dde E 17 XEM6310 User s Manual acr M HQ 18 Dede de CPP rm 18 Export PDF CSV Constraints Files 18 AASA AA ITE TTE 19 Migrating Hardware from the XEM6010 to the XEM6310 20 FPGA Boot Configuration 20 Clock PLL Clock Oscillator 20 Expansion Connector Differences 20 PCB Version FISTONY kw uou dc koe ends HA aa la ao AKBAR KANG 21 704 203 p TORE COPIE 21 XEM6310 Mechanical Drawing 22 BRK6110 Mechanical Drawing 23 XEM6310 Quick Reference 24 XEM6310 Quick Reference 25 4 www opalkelly com XEM6310 User s Manual Introducing the XEM6310 The XEM6310 is a compact FPGA board featuring the Xilinx Spartan 6 FPGA and SuperSpeed USB 3 0 connectivity via a USB 3 0 Micro B receptacle D
21. n security using AES decryption logic and provides two methods for encryption key memory storage The first is a volatile memory storage supported by an external battery backup supply voltage VBATT The second is a one time programmable eFUSE The XEM6310 design supports both types of key storage with user modification re quired For quantity purchases of 50 or more units please contact Opal Kelly salesQopalkelly com to discuss factory installation of these components Volatile Encryption Key Storage VBATT A small lithium rechargeable battery and three support components can be installed to provide VBATT to the FPGA when the XEM is unpowered This will preserve the contents of the FPGA s volatile key storage so long as VBATT remains over the threshold specified in the Spartan 6 docu mentation Please see the Xilinx Spartan 6 FPGA Configuration User Guide UG380 for more details Alternatively VBATT may be provided through JP2 3 In this case BT1 should not be installed The applicable schematic section and components required to support this functionality are shown below RefDes Manufacturer Manufacturer P N Seiko Instruments MS412FE FL26E 3V 1mAh lithium battery BAS40 04 TP Schottky Diode SOT23 C150 0 1 uF SM 0402 Decoupling R43 R44 4 7 KO 596 SM 0402 0 Q SM 0402 Connects Vaart to JP2 3 www opalkelly com XEM6310 User s Manual P VDC D10 R43 BAS40 04 TP 4 7 k NoLoad 5 NoLoad R44 VBAT
22. nformation for other peripherals on the module such as memory clock oscillators and LEDs Peripherals A Pins Peripheral is a project definition where you can enter your top level HDL design nets to have Pins generate a complete constraint file for you When you create a Peripheral you will select a target integration module The Peripheral is paired to this module so that the design parameters match the features and expansion capabili ties of the module L38P 0 25 099 0 JP2B 63 SDATA pix sdata IOSTANDARD LVCMOS33 L37P GCLK13 O 20 996 0 JP2B 64 IVCMOS33 L38N VREF O 22 706 0 JP2B 65 kn nce a oe VCMOS33 L37N GCLK12 0 20 055 0 JP2B 66 VCMOS33 L51P_0 25 362 0 JP2B 67 pix reset x VCMOS33 L50P 0 21 102 0 JP2B 68 per ni nme VCMOS33 L51N_0 23 293 0 JP2B 69 RESET pix reset IOSTANDARD LVCMOS33 L50N 0 19 964 0 JP2B 70 PIX6 pix data 6 IOSTANDARD LVCMOS33 opecifying Net Names The Pin List view for a Peripheral includes three additional editable columns e Design Net The name of the signal as it appears in your top level HDL e Constraints Text that is inserted into the constraints file for that signal e Comment Additional comment text that is added to the constraints file These additional data are merged with the default Pin List constraints file prior to export The re sult is a constraints file complete with net names that can be used with your FPGA development flow Export Features Constraint file template D
23. oot configuration Clock PLL Clock Oscillator The XEM6010 has a Cypress CY22393 multi output PLL that provided clock signals to the FPGA and expansion connectors The XEM6310 has a fixed output 100 MHz clock oscillator that provides this clock signal to the FPGA The FPGA has on board DCMs and PLLs which may be used to produce a wide range of clock frequencies The expansion connector signals that were routed to the CY22393 on the XEM6010 are routed to the FPGA on the XEM6310 Expansion Connector Differences There are some minor differences between the XEM6010 and XEM6310 expansion connector pinouts The location and type of connector is unchanged e JP30n the XEM6010 is the same connector and location as JP1 on the XEM6310 This connector reference designator has changed e The XEM6310 has two connections on the expansion bus to support the VBATT function ality of the LX150 Spartan 6 FPGA to store encryption keys This functionality is not available in the L X45 e The XEM6010 provided the USB microcontroller FX2 1 C signals to the expansion con nector The XEM6310 routes these two signals to the FPGA If this support is required an 1 C controller will need to be implemented in FPGA fabric The following table summarizes the expansion connector differences XEM6010 XEM6310 JP2 3 is a no connect JP2 3 is FPGA VBATT JP2 12 is a no connect JP2 12 is FPGA RFUSE 20 www opalkelly com XEM6310 User s Manual PCB Version Hist
24. ory 20120517 First production PCB www opalkelly com 21 XEM6310 User s Manual XEM6310 Mechanical Drawing D 2 50 If All dimensions in mm 22 www opalkelly com XEM6310 User s Manual BRK6110 Mechanical Drawing All dimensions in mm E ng Opal Kelly 0 3 004 B OOO Cy ND O 00 CT TN O Oo O DOM mO OND de 06000 M lt COO N 00 OO CO N N N AN DAO 20 XO WOR N OO www opalkelly com 23 XEM6310 User s Manual XEM6310 Quick Reference JP2 Length Pin Connection FPGA Pin mm i n JTAG_TCK JIAGTMS W JTAG TDI U12 L22N 2 pop G16 an H9 H18 F16 E n7 a7 K16 Me N ACCO S V21 L52P 1 L20 wooo N L22 L45N 1 1 859 H21 5 953 H22 5 745 F21 8 198 F22 7 818 D21 2 225 D22 2 358 B21 1 387 B22 0 928 A457 77 20 J22 e Ca 8 25953 leo mrs fo 92225 e 2 a0 3 3VDD NEN menn EN RFUSE HEN DGND menn Gis 61 093 F20 61 369 H20 52 874 52611 Di9 48 369 D20 48 196 FB 40 724 Fig 41 080 MI 30 348 LIS 29 853 DOND ee K20 29273 KID 29 267 u20 22 557 U22 22 965 R20 26 121 R22 25 746 N20 26 691 N22 26 043 M20 24 082 DGND penn Kon 24 190 Kat 23 920 K22 23 603 G20 27676 G22 27 183 E20 31 177 E22 1491 C20 33 951 C22 93 893
25. story Date Description Contents Introducing the XEM6310 5 PCB POO iuo mma v som d aj l v pf da Re m ai 5 BRK6110 Breakout Board 5 Functional Block Diagram 6244600844 iii 6 Ha qe 6 Power Supply Li 6 DC Power Connector e T SuperSpeed USB 3 0 Interface T On board Peripherals nananana aana cece eee eee T Low Jitter Crystal OscillatOr 7 128 MByte Word Wide DDR2 Synchronous DRAM 7 FPGA Flash 16 MiB Serial Flash Memory T System Flash 16 MiB Serial Flash Memory T CEDO py ra n APA na 7 Expansion Connectors e esesoo 8 FrontPanel Support esouseroo 8 Programmers Interface 8 Applying the XEM6310 ooo 9 Powering the XEM6310 5 ated AA e od ea 9 Power B dgel kao kam kon s dit oak laa de ak e a eww a 9 Example XEM6310 L X150 FPGA Power Consumption 10 Supply Heat Dissipation IMPORTANT 10 ROSI INITIO NA bon ET ETT TET TOT TT TU TT 11 Reset Profile RESET e e 11 CE UPA PUT PCT 11 Wy co 11 Loading a Power On FPGA Configuration 11 gata MP 12 BID NA T 12 DDR2 SDRAM pipi dla i r quor d eue PADI 0455642 12 Clock Configuration Source Synchronous 13 Memory Controller Bloc
26. sts the appropriate Samtec mating connectors along with the total mated height Samtec Part Number Mated Height BTE 040 01 F D A 5 00mm 0 197 BTE O40 02 F D A 8 00mm 0 315 BTE 040 03 F D A 11 00mm 0 433 BTE 040 04 F D A 16 10mm 0 634 BTE 040 05 F D A 19 10mm 0 752 FrontPanel Support The XEM6310 is fully supported by Opal Kelly s FrontPanel Application FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigu rable I O board and adds tremendous value to the XEM6310 as an experimentation or prototyp ing system Programmer s Interface In addition to complete support within FrontPanel the XEM6310 is also fully supported by the FrontPanel SDK a powerful C class library available to Windows Mac OS X and Linux pro grammers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for CZ Java and Python making the API available under those languages as well Sample wrappers unsupported are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel 8 www opalkelly com XEM6310 User s Manual Applying the XEM6310 Powering the XEM6310 The XEM6310 requires that this supply be clean filtered and within the range of 4 5v to 5 5v Th
27. y reserves the right to change the form factor and possibly pinout of the BRK6110 Therefore unlike the XEM6310 it is not intended or recommended for production integration Full schematics and Gerber artwork files for the BRK6110 are provided free of charge If your application depends on the existing form factor you may reproduce this board from these docu ments A mechanical drawing of the BRK6110 is also shown at the end of this document Functional Block Diagram System Flash FPGA Flash DDR2 SDRAM 16 MiB 16 MiB 128 MiB FPGA Host Interface Ups Spartan 6 FPGA XC6SLX45 2FGG484 USB 3 0 te Or XC6SLX150 2FGG484 8 LEDs 100 MHz ivos Clock le I O 63 I O Samtec Expansion Connector Samtec Expansion Connector The XEM6310 is offered in two variants These two variants are identical except for the FPGA provided The table below lists some of the differences between the two devices Please consult the Xilinx documentation for a more thorough comparison Features xEMestpixas n XEMOSIXISD Clock Management Ties 4 Se o Power Supply The XEM6310 is designed to be operated from a 5 volt power source supplied through the DC power jack on the device or the expansion connectors on the bottom of the device This provides power for the three high efficiency switching regulators on board to provide 3 3v 1 8v and 1 2v 0 9v is derived from the 3 3 volt supply using a small low dropout LDO r
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