EDP-AM-DIO54 Digital IO Module User Manual Version v4.0, 29/03
Contents
1. from the load Software drivers are provided for each CM to talk directly to the Digital IO Outputs both by DC and also by direct MCU port control Electrocomponents plc Page 152. output pins 1 5 5 Mapping Of CPU Peripheral Pins To The Digital Module The mapping of the various CPU modules to the backplane is different for each CPU Module This means the digital IO Module appears slightly differently for each CM that is fitted An example of the mapping is shown below for two CPU modules The provided software allows for easy reading and writing of values to the Digital IO Module The software is different for each Command Module XC167 Pin Allocation STRO Pin Allocation EDP AM DIO54 Allocation Vcc to BB Vcc 3V3 or 5V Vcc 3V3 or 5V supplied by CM supplied by CM P3 5 P5 7 IRQ GPIO18 I2C GENO INT P3 2 P5 6 IRQ GPIO16 CNTRLI2C INT 9 P6 2 CC210 P6 0 EDP DO9 8 P6 1 CC110 P4 7 EDP_DO8 56 P2 15 CC1510 P4 6 EDP_DO7 55 P2 14 CC1410 P4 5 EDP_DO6 54 P2 13 CC1310 P4 4 EDP_DO5 53 P2 12 CC1210 P4 3 EDP_DO4 52 P2 11 CC1110 P4 2 EDP_DO3 51 P2 10 CC1010 P4 0 EDP_DO2 13 P6 6 CC6IO P6 4 EDP_DO13 12 P6 5 CC5IO P6 3 EDP_DO12 11 P6 3 CC410 P6 2 EDP_DO11 10 P6 3 CC310 P6 1 EDP_DO10 50 P2 9 CC910 P4 1 EDP_DO1 P2 8 CC810 P4 0 EDP_DOO P3 7 P7 4 EDP_DI11 Digital GND Digital GND Digital GND Vcc 5V from reg 5V from baseboard 5V from baseboard regulator regulator Vcc 3V3 from reg 3V3 from baseboard 3V3 from baseboard regulator regulator 12V Power GND 12V Power GND 12V Power GND 12V Power GND 12V Power GND 12V Power GND 12V 2A 12V 2A 12V 2A 12V 2A 12V 2A 12V 2A Electrocomponents plc Page 9 EDP AM
3. DIO54 Manual XC167 Pin Allocation Vcc to BB STR9 Pin Allocation Vcc 3V3 or 5V supplied by CM 24 P9 3 CC1910 P4 0 21 P9 0 CC1610 22 P9 1 CC1710 23 P9 2CC1810 131 P1H 4 CC2410 132 P1H 5 CC2510 133 P1H 6 CC2610 134 P1H 7 CC2710 15 P7 4 CC2810 16 P7 5 CC2910 17 P7 6 CC3010 P7 7 CC3110 CS8900A INT 124 P1L 7 CC2210 127 P1H 0 CC2310 Digital GND Vcc 5V from reg Digital GND 5V from baseboard regulator 3V3 from baseboard regulator 12V Power GND 12V Power GND 12V 2A 12V 2A Vcc 3V3 from reg 12V Power GND 12V Power GND 12V 2A 12V 2A XC167 Pin Allocation Vcc 5V from reg Vcc 3V3 or 5V supplied by CPU Vcc 3V3 from reg STR9 Pin Allocation Vcc 5V from reg Vcc 3V3 from reg 26 SCL2 P2 0 25 SDA2 24 SCL1 23 SDA1 Digital GND P2 1 P2 2 P2 3 Digital GND Vcc 3V3 or 5V supplied by CPU EDP AM DIO54 Allocation Vcc 3V3 or 5V supplied by CM NC EDP_DO18 EDP_DO17 EDP_DO16 EDP_DO15 EDP_DO14 EDP_DI9 EDP_DI8 EDP_DI7 EDP_DI6 EDP_DI5 EDP_DI4 EDP_DI3 EDP_DI2 EDP_DI10 EDP_DI1 EDP_DIO Digital GND 5V from baseboard regulator 3V3 from baseboard regulator 12V Power GND 12V Power GND 12V 2A 12V 2A EDP AM DIO54 Allocation Vcc 5V from reg Vcc 3V3 or 5V supplied by CPU Vcc 3V3 from reg EDPCON2 79 EDPCON2 77 EDPCON2 7 EDPCON2 5 Digital GND Note The shaded signals are not available with certain CPU modules These inputs and outputs are recommended to be co
4. Digital I O Module can also read in external input signals via an input buffer The real world signals are referred to as DI y where y 0 to 15 Signals DI 0 to DI 11 have an input protection stage and hex Schmitt trigger inverting buffer input whilst signals DI 12 to DI 15 have a different input protection arrangement There are no buffers or inversion of these signals The input signals after the protection stage can be routed via jumper links to either the serial input latches or to the STR9 MCU I O pins Jumpers J400 and J401 provide routing for 12 inputs DI 0 to DI 11 whilst input DI 12 to DI 15 have no routing capability and are fed directly into one of the PCA9555 serial latch device The signals which are passed into the latches are referred to as IN_PO x and IN_P1 x where x 0 to 7 whilst the signals which pass directly into the MCU pins are referred to as EDP_DI z where z 0 to 11 Electrocomponents plc Page 8 EDP AM DIO54 Manual RS There is no problems at all when the devices are configured as serial latch input device although it s worth noting that the same logic level when presented to DI 0 to DI 11 will read differently when presented to DI 12 to DI 15 This is because the DI 0 to DI 11 inputs have the Schmitt inverter in series with them When the link options are organised for direct input digital reading it s worth noting that there may be a share conflict with other modules that may require these I O pins as
5. EDP AM DIO54 Digital IO Module User Manual Version v4 0 29 03 2010 This document contains information on the DIO54 digital IO module for the RS EDP system EDP AM DIO54 Manual Contents 1 Digital IO Module 3 1 1 DAA 3 1 2 Using Multiple Digital IO Modules eee erre 3 1 3 Software Drivers For Digital Module 3 1 4 Digital IO Module Connectors occccccnoccnncccoccnnnccnnconncononcnnnononnnnonnnas 5 1 4 1 OA Me 5 1 4 2 DC GPIO Outputs 25MmA RR cici ecce 5 1 4 3 I2C GPIO Inputs unprotected oocccccccocccncccnoconccononccnnonanccnncnnos 6 1 4 4 Protected Digital Inpute cici cici cccicicciiiiiiciiiiiiiiiiiiin 6 1 4 5 Location Of Module Jumpers And Connectors 7 1 5 Detailed Notes On Configuring The DIO54 Module For Use 8 1 5 1 DIO54 Compatibility EE 8 1 52 Controlling The DIO54 Digital I O Module 8 1 5 3 Digital Outputs iii 8 1 5 4 Digtal NPU EE EE EEE 8 1 5 5 Mapping Of CPU Peripheral Pins To The Digital Module 9 1 6 Setting The Jumpers And Solder Bridges 10 1 7 Digital IO Module Jumper Settings rrrrrnnnrrrrrrnnnrrnrrnnnrrnrrnnnnnenn 12 Electrocomponents plc Page 2 EDP AM DIO54 Manual RS 1 Digital 10 Module The digital module provides a means to apply digital signals to the CM and drive world devices from it There are 12 input channels with overvoltage protection and optional pull ups plus another 16 TT
6. L inputs accessible only via I2C 16 outputs are present each with a current drive capability of 500mA plus another 16 25mA logic outputs The first 12 inputs and 16 outputs are derived from the CM where possible although the protected input stages and high current output stages can be connected to the 12C IO expander also The input 12C ports can generate an interrupt request This is disabled by default as it could result in a high CPU interrupt loading An RGB colour LED may be fitted for experimental purposes 1 1 Digital Outputs The 500mA outputs are simple low side drives and are in the OFF state at power up They are designed to drive relays and solenoids and in fact can sink up to 1A but the user may need to attach a mini heatsink to the driver IC if high duty ratios are expected It is up to the user to program the digital output pins of the CPU to a logic 1 to turn the outputs on There is a net inversion through the drivers so that a logic 1 at the CPU output pin will result in a low i e current sink enabled at the output connector The user is provided with a software suite of drivers to allow the pins of the IO module to be controlled both by I2C and also via direct port manipulation of the MCU s lO pins All of the CMs provided by Hitex provide software support for the Digital IO Module Depending on the CPU module being used not all of the 12 inputs and 16 outputs can be controlled independently This is d
7. O54 Digital 1 0 Module Outputs to RS EDP Backplane X202 Digital Output Connector jp a o gt 0 gt 9 gt gt _ gt T 9 e gt mr 9 mr 9 mn 9 x gt EVG16_GPIO64 8606 lt p 7 RSR gt FDo 12 z or CE bou 2508 RD L ee O pot pe enge gt RE SESH gt Do 15 EVG15 GPIO63 d gt Do 16 oe onge BO frr B308 1 gt DO 18 X500 GND Terminal CNTRL Ge X500 B309 flac ceno PAVE Np Darlington outputs controlled by either 12C or direct M are MCU logic level outputs controlled only by direct M Mapping Aid summary of Digital Output jumpers and lO configuration As you can see from the diagram above the Digital IO Module can be fed with output data either directly from the back plane signals EVGO to EVG19 or via I2C packets from the I2C buses The user can select which of these two he wishes to use via the link options shown in the diamonds above The diagram shows the same I2C bus interface which can be selected to be the same as the input module i e CNTRL I2C or I2C GENO Note also the large X500 ground terminal which can be used to terminate large high current switching loads As the backplane connections are only rated for up to 2A for higher current loads the user should connect the high side load to the IO pin and use the X500 ground terminal for the return current
8. Sr ge juel 6 O 2288 US 7ahcrapw RA405 404 SOMUR 4 UMN OG OF G r a Fora BOPA 83 6 2 54 TSM DO 00 Sp LPT HE NS LS 2 01 28 53 6 2 54 TSM WSL PS 2 0L 2S w Hn DCH 00 Ww SEET gt U502 Gi JULN2003AD O C3000 8304 JE ULN2003AD 8302 8303 B301 O E U503 B308 B305 JE o U603 ULN2003AD SP ULN2003AD 7 3 U604 gize 9OU 031 X200 2 70 S AMP X201 52 50 S AMP WSL S Z 0L 2S OWS S 2 2 1 2S Se p GIR 2 Top View Bottom View Electrocomponents plc Page 7 EDP AM DIO54 Manual RS 1 5 Detailed Notes On Configuring The DIO54 Module For Use 1 5 1 DIO54 Compatibility The DIO54 module has been designed as a universal module which can accept any processor modules designed for the EDP system As such it is important to note that there are a few limitations which the user needs to be aware of You must check that the DIO54 is correctly configured for your CPU before fitting it to the EDP baseboard 1 5 2 Controlling The DIO54 Digital I O Module This module can be controlled by the CPU in several ways On board the module are two independent serial I O latch devices Each of these devices has an input mode and an output mode function The PCB has been designed such that one device is dedicated to output mode and the other device is dedicated for input mode The chip used is the NXP PCA9555 device The PCA9555 device can be controlled via the 12C0 channel
9. ctor 400 OQ DI O 1400 lt Dia 400 lt amp 01 200 lt ni 200 lt Dis 400 lt DIS 401 lt A Dis 401 lt A om 401 lt ils 401 lt amp pi an 6 009 Ra GRio22 12c1NT 401 lt amp pit 9 GPIO16 CNTRL DC IN q lt SO GPIO18_12C_GENO_INT lt _ B308 B309 can be read via 12C or via backplane by the I 15 can only be read via I2C Mapping Aid summary of Digital Input jumpers and IO configuration You can see from this diagram that inputs DI 0 to DI 15 provide the digital input pins to the system The processed inputs are then made available on the backplane via the link options marked above as a diamond If the inputs are required to be read via the I2C bus then the link can be set differently DI 12 to DI 15 can only be read via the back plane and no 12C read option is available to them The 12C interface can be selected as either CNTRL I2G which is the main 12C bus within the RS EDP system or via the I20 GENO bus which is usually provided as the user own DC independent 12C bus Not all CMs have two 12C channels so the default is usually CNTRL_12C Software drivers are provided for all the CMs to talk to the Digital IO Modules over the 12C protocol The 12C device can generate an interrupt if required The user can select this interrupt source via the link options shown above Electrocomponents plc Page 14 EDP AM DIO54 Manual RS DI
10. nnected to the appropri own port pins ate I2C GPIO device rather than relying on the CPU s 1 6 Setting The Jumpers And Solder Bridges To make the Digital I O Module compatible with direct MCU drive from the I O pins the solder jumpers mentioned above B501 B508 and B602 B609 need to be set accordingly This means the user has the option to drive the output directly from the MCU s or via the PCA9555 serial latch depending on the jumper options O Electrocomponents pic Page 10 EDP AM DIO54 Manual RS In terms of compatibility with other modules it is worth noting that the STR9 has on board ADC These ADC channels are on Port4 so there is a potentially conflicting situation when used with the Analogue Module l e The analogue module will present analogue values to Port4 whilst Port4 is trying to drive the Digital Module outputs It is therefore prudent to reserve the Port4 pins for analogue input whilst using the Port6 pins for digital output This means having some idea of what MCU system resources you will require in your design and modifying both the source code and the hardware to suite The low level hardware drivers may therefore need to be modified when mixing modules to avoid this potential conflict The Digital I O Module can also read in external input signals via an input buffer The real world signals are referred to as DI y where y 0 to 15 Signals DI 0 to DI 11 have an input protection stage and hex Schmitt trigger in
11. on the CPU via the back plane This 2C0 channel is referred to as the CNTRL DC channel on the Baseboard Each of the two PCA9555 devices has its own unique 12C address to communicate on 1 5 3 Digital Outputs The PCA9555A device can be used to output data the raw logic level output signals for this are referred to as OUT PO x and OUT_P1 x where x 0 to7 These signals are available to probe on connector X203 and there are 16 logic level outputs in total These raw logic level outputs can be fed into a high current Darlington driver of the type ULN2003 This however is a board option and the user has to configure the board to do this via a series of solder bridges These bridges are B501 B508 and B602 B609 Check the board to ensure they are configured how you want them The Darlington drive output from the ULN2003 appears on another connector X202 as signal DO y where y 0 to 15 Note the output drive of DO 0 DO 11 is double that of DO 12 DO 15 due to the way the hardware has been implemented The CPU also has some direct I O capability and this feature is bought out onto the Baseboard The Digital WO Module has access to these signals and the user can use these rather than the signals produced by the 12 PCA9555 digital latches On the Digital I O Module these signals are referred to as EDP_DO y where y 0 to 15 The mapping between the CPU s port pins and the Output on the DO y pins is given later 1 5 4 Digital Inputs The
12. tings are given in the following table Set address bit AO for U300 input I2C GPIO device B307 Set address bit A2 for U301 output I2C GPIO device 1 2 E CPU output option may not be available with all EDP CPU modules Electrocomponents plc Page 12 EDP AM DIO54 Manual RS B501 Cut amp Solder Connect ULN2003 input to either CPU output pin or U301 I2C GPIO device CPU output B502 Cut amp Solder Connect ULN2003 input to either CPU output pin or U301 I2C GPIO device CPU output B508 Cut amp Solder Connect ULN2003 input to either CPU output pin or U301 I2C GPIO device CPU output 3401 Jumper Route DIO input to CPU digital input pin via EDP orto 2C GPIO U300 _ Notfited Open 34018 Jumper Route DIO input to CPU digital input pin via EDP orto 2C GPIO U300 _ Notfited Open J401G Jumper _ Route DIO input to CPU digital input pin via EDP orto 12C GPIO U900 Notfited Open 34010 Jumper Route DIO input to CPU digital input pin via EDP orto 12C GPIO U300 _ Notfited Open OTE Jumper Route DIO input to CPU digitel input pin via EDP orto 2C GPIO U300 Notfited Open OTF Jumper Route DIO input to CPU digital input pin via EDP orto 12C GPIO U300 Notfited Open Foer CPU output option may not be available with all EDP CPU modules O Electrocomponents pic Page 13 EDP AM DIO54 Manual RS DIO54 Digital 1 0 Module Inputs to RS EDP Backplane X205 Digital Input Conne
13. tput lo Don output 10 DO12500mAoutput 12 DO6 1A output DO14 500mA output DO7 1A output 1 DO15 500mA output 6 DO16 L logic output DO17 L logic output DO18 L logic output DO15 500mA output 21 CPU Vcc 22 12V GND Note Although the outputs DOO DO11 are rated at 1 Amp you should take care that the maximum total ULN2003 power dissipation is not exceeded DO5 1A output NES DO13 500mA output 1 1 4 2 12C GPIO Outputs 25mA GPIO OUT RO GPIO OUT P10 al GPIO OUT P01 4 GPIO OUT P11 3 GPIO OUT P02 e GPIO OUT P12 GPIO OUT P03 NS GPIO OUT_P13 oa GPIO OUT_P04 GPIO OUT P14 GPIO OUT PO GPIO OUT P15 GPIO OUT P06 GPIO OUT P16 GPIO OUT _P07 16 GPIO OUT 17 CPU Vcc 3V3 5V SGND Electrocomponents plc Page 5 EDP AM DIO54 Manual 1 43 12C GPIO Inputs unprotected GPIO IN POO r GPIO IN_P10 EN GPIO IN_PO1 GPIO IN_P11 GPIO IN P02 GPIO IN P12 GPIO IN P03 ra GPIO IN P13 GPIO IN_P04 GPIO IN_P14 GPIO IN P05 GPIO IN_P15 GPIO IN_P06 GPIO IN_P16 GPIO IN P07 GPIO IN P17 17 CPU Vcc 3V3 D 20 SGND 1 4 4 Protected Digital Inputs DIO input DI8 input EY DI1 input DI9 input ap aa a z pint 8 itt input DI6 input a DI14 input DI7 input EY DI15 input 17 CPU Vcc 3V3 19 mm SGND DI5 input DI13 input 15 Electrocomponents plc Page 6 EDP AM DIO54 Manual 1 4 5 Location Of Module Jumpers And Connectors O 1N4148 1 1N4148 Ve 1N4148 LABEBLS yy
14. ue to a potential shortage of IO pins on the CPU itself In such cases the duplicated or unavailable channels should be routed to one of the two 12C GPIO devices to make up the shortfall 1 2 Using Multiple Digital IO Modules Up to 3 Digital IO Modules may be fitted to a single baseboard 4 if no CPU is fitted Typically the first module would make use of the CPU modules own port pins Other modules would rely on the I2C GPIO devices for their connection to the CPU The full 8 I2C slave address variations is available to all these devices via solder links on the AM The user must make sure that there are no conflicts on IO pins on the backplane when more than one module is fitted Alternatively all digital IO modules could use 12C freeing up CPU pins for other purposes Where a second EDP baseboard is available the I2C GEN 0 I2C bus can be used to connect further digital IO modules 1 3 Software Drivers For Digital Module The module has two I2C GPIO devices both of which require special software drivers to access These are provided for each of the CPU Modules The software allows for control from both 12C bus commands and also via direct port control from the CPU Electrocomponents plc Page 3 EDP AM DIO54 Manual Electrocomponents plc Page 4 EDP AM DIO54 Manual 1 4 Digital 10 Module Connectors 1 4 1 500mA Outputs _x202 Description X202 Description DO2 1A output DO10 1A output z Dos ia output 8 Doum ou
15. verting buffer input whilst signals DI 12 to DI 15 have a different input protection arrangement There are no buffers or inversion of these signals The input signals after the protection stage can be routed via jumper links to either the serial input latches or to the STR9 MCU I O pins Jumpers J400 and J401 provide routing for 12 inputs DI 0 to DI 11 whilst input DI 12 to DI 15 have no routing capability and are fed directly into one of the PCA9555 serial latch device The signals which are passed into the latches are referred to as IN_PO x and IN_P1 x where x 0 to 7 whilst the signals which pass directly into the MCU pins are referred to as EDP_DI z where z 0 to 11 There is no problems at all when the devices are configured as serial latch input device although it s worth noting that the same logic level when presented to DI 0 to DI 11 will read differently when presented to DI 12 to DI 15 This is because the DI 0 to DI 11 inputs have the Schmitt inverter in series with them When the link options are organised for direct input digital reading it s worth noting that there may be a share conflict with other modules that may require these I O pins as output pins Electrocomponents plc Page 11 EDP AM DIO54 Manual RS 1 7 Digital IO Module Jumper Settings Before fitting the DIO54 module to your EDP baseboard you must configure the jumpers and solder bridges to suit the CPU module you are intending to use The possible set
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