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4519 Group User`s Manual

1. Instruction Do Do Number of Number of Flag CY Skip condition code o o lojojo ojo 1 0 0 0 6 PE oes 2 16 1 1 0 Operation CY 0 Grouping Arithmetic operation Description Clears 0 to carry flag CY RD Reset port D specified by register Y Instruction D9 Do Number of Number of Flag CY Skip condition code ololo ol o t o 1 o fo 1 a SONO J a 2 16 1 1 H Operation D Y 0 Grouping Input Output operation However Description Clears 0 to a bit of port D specified by reg Y 20107 ister Y RT ReTurn from subroutine Instruction D9 Do Number of Number of Flag CY Skip condition code o lo o t ojo o o o 4 4 Boe em 2 16 1 2 _ Operation PC SK SP Grouping Return operation SP SP 1 Description Returns from subroutine to the routine called the subroutine RTI ReTurn from Interrupt Instruction Dg Do Number of Number of Flag CY Skip condition code o olo 1 0 o 0 1 0 0 4 6 nri DE 2 16 1 1 E Operation PC SK SP Grouping Return operation SP SP 1 Description Returns from interrupt service routine to main routine Returns each value of data pointer X Y Z carry flag skip status NOP mode sta
2. Instruction Dg Do Number of Number of Flag CY Skip condition code 1lololililololo 1 3 words cycles 16 1 1 Operation A P3 Grouping Input Output operation Description Transfers the input of port P3 to register A IAP4 Input Accumulator from port P4 Instruction Dg Do Number of Number of Flag CY Skip condition code tlololi1lilolol1 0 4 words cycles 16 1 1 Operation A P4 Grouping Input Output operation Description Transfers the input of port P4 to register A IAP5 Input Accumulator from port P5 Instruction Dg Do Number of Number of Flag CY Skip condition code 1lololslslololt 1 5 words cycles 16 1 1 Operation A P5 Grouping Input Output operation Description Transfers the input of port P5 to register A IAP6 Input Accumulator from port P6 Instruction Do Do Number of Number of Flag CY Skip condition code 1 0 0 1 1 0 0 1 0 6 words cycles 16 1 1 Operation A P6 Grouping Input Output operation Description Transfers the input of port PG to register A Rev 1 00 Aug 06 2004 RENESAS 1 97 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY AL
3. 42P2R A Recommended Plastic 42pin 450mil SSOP EIAJ Package Code JEDEC Code Weight g Lead Material gl be SSOP42 P 450 0 80 0 63 Alloy 42 Cu Alloy H 7 y a 7 l3 5 1 q O E O F Recommended Mount Pad Y J Dimension in Millimeters Symbol Min Nom Max y E X A a 2 4 O ey B Ai 0 05 E D A2 2 0 G b 035 04 0 5 l C 0 13 0 15 0 2 E D 17 3 17 5 17 7 RH LH HAHH HHHH A2 A1 E 8 2 8 4 8 6 gt mE C e 0 8 e b HE 11 63 11 93 12 23 cl Y L 0 3 0 5 0 7 0 L1 1 765 os a Z 0 75 Zi 0 9 o y E 0 15 ES 0 0 10 Z l b2 0 5 Zi J Detail G Detail F ei 11 43 l2 1 27 Rev 1 00 Aug 06 2004 RENESAS 3 27 REJO9B0175 0100Z RENESAS 4 BIT CISC SINGLE CHIP MICROCOMPUTER USER S MANUAL 4519 Group Publication Data Rev 1 00 Aug 08 2004 Published by Sales Strategic Planning Div Renesas Technology Corp 2004 Renesas Technology Corp All rights reserved Printed in Japan 4519 Group User s Manual 21 NE SAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJO9B0175 0100Z
4. Instruction Dg Do Number of Number of Flag CY Skip condition code 1 0 0 0 1 0 1 1 1 0 2 2 E yor cycles 2 16 1 1 Operation PU1 A Grouping Input Output operation Description Transfers the contents of register A to pull up control register PU1 TQ1A Transfer data to register Q1 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jo olojojojo j1 o o j2Jo 4 words ae 2 16 1 1 H Operation Q1 A Grouping A D conversion operation Description Transfers the contents of register A to A D control register Q1 TQ2A Transfer data to register Q2 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition code 1 0 0 0 0 0 0 1 0 1 2 0 5 words cyclos 2 16 1 1 Operation Q2 A Grouping A D conversion operation Description Transfers the contents of register A to A D control register Q2 TQ3A Transfer data to register Q3 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1loololololol1l1 lo 2 lole words cycles 2 16 1 1 Operation Q3 A Grouping X A D conversion operation Description Transfers the contents of register A to A D control register Q3
5. Instruction Dg Do Number of Number of Flag CY Skip condition code o olol1lol1l1 lo 1 B words cycles 2 16 1 1 Operation POF instruction valid Grouping Other operation Description Makes the immediate after POF instruction valid by executing the EPOF instruction IAPO Input Accumulator from port PO Instruction D9 Do Number of Number of Flag CY Skip condition code 1 o o 1 1 o ojojo o 0 pto ME E 2 16 1 1 Operation A PO Grouping Input Output operation Description Transfers the input of port PO to register A IAP1 Input Accumulator from port P1 Instruction Dg Do Number of Number of Flag CY Skip condition code 1lolol1l1iololo 1 1 words cycles 2 16 1 1 i Operation A P1 Grouping Input Output operation Description Transfers the input of port P1 to register A IAP2 Input Accumulator from port P2 Instruction Dg Do Number of Number of Flag CY Skip condition code 11o o 1 lt lololo 0 2 welds cycles 2 16 1 1 Operation A2 Ao P22 P20 Grouping Input Output operation A3 0 Description Transfers the input of port P2 to register A Rev 1 00 Aug 06 2004 RENESAS 1 96 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued IAP3 Input Accumulator from port P3
6. Serial I O register SI A D conversion completion flag ADF A D control register Q1 A D control register Q2 A D control register Q3 Successive comparison register AD Comparator register X represents undefined Fig 2 6 3 Internal state at reset Rev 1 00 Aug 06 2004 RENESAS 2 68 REJ09B0175 0100Z APPLICATION 4519 Group 2 6 Reset Key on wakeup control register KO Key on wakeup control register K1 Key on wakeup control register K2 Pull up control register PUO Pull up control register PU1 Port output structure control register FRO Port output structure control register FR1 Port output structure control register FR2 Port output structure control register FR3 Carry flag CY Register A Register B Register D Register E Register X Register Y Register Z Stack pointer SP Operation source clock Ceramic resonator circuit Quartz crystal oscillation circuit RC oscillation circuit Oj lo o o jio oio o o O IOIO IOI IOl IOIO IOo Oj lo o o o ooo o o ax lalla Ia llia lollo X represents undefined Fig 2 6 4 Internal state at reset 2 6 3 Notes on use 1 2 Register initial value The initial value of the fo
7. Do Number of Number of Flag CY Skip condition d code ipee ape elo a aja les 7 h ee 1 1 Operation A PUO Grouping Input Output operation Description Transfers the contents of pull up control register PUO to register A TAPU1 Transfer data to Accumulator from register PU1 Instruction D9 Do Number of Number of Flag CY Skip condition l code Tael alla ala ela eE 1 1 Operation A PU1 Grouping Input Output operation Description Transfers the contents of pull up control register PU1 to register A TAQ1 Transfer data to Accumulator from register Q1 Instruction D9 Do Number of Number of Flag CY Skip condition code 1lo lolilolololilolol l 2l4l4 Males cycles 2 16 1 1 B H Operation A Q1 Grouping A D conversion operation Description Transfers the contents of A D control regis ter Q1 to register A Rev 1 00 Aug 06 2004 2tENESAS REJO9B0175 0100Z 1 115 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAQ2 Transfer data to Accumulator from register Q2 Instruction Dg Do Number of Number of
8. Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Timer 2 underflow Timer 3 underflow Address 8 in page 1 Address A in page 1 Timer 4 underflow A D conversion completed Address C in page 1 Serial I O transmit receive completed Address E in page 1 Fig 15 Interrupt system diagram 1 23 4519 Group 6 Interrupt control registers Interrupt control register V1 Interrupt enable bits of external 0 external 1 timer 1 and timer 2 are assigned to register V1 Set the contents of this register through register A with the TV1A instruction The TAV1 instruction can be used to transfer the contents of register V1 to register A Interrupt control register V2 The timer 3 timer 4 A D and serial I O interrupt enable bit is as signed to register V2 Set the contents of this register through register A with the TV2A instruction The TAV2 instruction can be used to transfer the contents of register V2 to register A Table 6 Interrupt control registers Interrupt control register V1 at reset 00002 HARDWARE FUNCTION BLOCK OPERATIONS at RAM back up 00002 R W TAV1 TV1A Interrupt disabled SNZT2 instruction is valid Timer 2 interrupt enable bit Interrupt enabled SNZT2 instruction is invalid Interrupt disabled SNZT1 instruction is valid Timer 1 interrupt enable bit Interr
9. PWM period 7 5 clock Be Note At PWM signal H interval extension function valid set 0116 or more to reload register R4H Fig 2 3 2 Timer 4 operation 6 Period measurement Outline The period of the followings can be measured by timer 1 on chip oscillator divided by 16 CNTRO pin input INTO pin input Specifications Timer 1 count is performed during one period from the rise of a CNTRO input to the next rise Timer 1 count source is XIN input Figure 2 3 9 and Figure 2 3 10 show the setting example of period measurement of a CNTRO pin input 7 Pulse width measurement Outline H pulse width or L pulse width of INTO pin input can be measured by Timer 1 Specifications Timer 1 count is performed during H pulse input from the rise of an INTO input to the next rise Timer 1 count source is XIN input Figure 2 3 11 and Figure 2 3 12 show the setting example of pulse width measurement of an INTO pin input Rev 1 00 Aug 06 2004 RENESAS 2 38 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers 8 Watchdog timer Watchdog timer provides a method to reset the system when a program run away occurs Accordingly when the watchdog timer function is set to be valid execute the WRST instruction at a certain period which consists of 16 bit timers 65534 counts or less execute WRST instruction at less than 65534 machine cycles Outline Execute the WRST instruction in 16 bit timer s 65534 counts a
10. Reset circuit Vss Reset 7 circuit Fig 3 4 2 Wiring for the RESET input pin 3 21 APPENDIX 4519 Group 3 4 Notes on noise 3 Wiring for clock input output pins 4 Wiring to CNVss pin Make the length of wiring which is connected Connect the CNVss pin to the Vss pin with to clock I O pins as short as possible the shortest possible wiring Make the length of wiring across the grounding lead of a capacitor which is O Reason connected to an oscillator and the VSs pin The operation mode of a microcomputer is of a microcomputer as short as possible influenced by a potential at the CNVss pin Separate the Vss pattern only for oscillation If a potential difference is caused by the from other Vss patterns noise between pins CNVss and Vss the operation mode may become unstable This may cause a microcomputer malfunction or a program runaway Fig 3 4 3 Wiring for clock I O pins Reason Fig 3 4 4 Wiring for CNVss pin If noise enters clock I O pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer Rev 1 00 Aug 06 2004 RENESAS 3 22 REJO9B0175 0100Z 4519 Group 5 Wiring to VPP pin of built in PROM version In the built in PROM version of the 4524 Group the CNVss pin is a
11. P10 pin pull up transistor control bit Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Pull up transistor OFF O jO JO O Pull up transistor ON Note R represents read enabled and W represents write enabled ENESAS 1 83 4519 Group Port output structure control register FRO HARDWARE CONTROL REGISTERS at reset 00002 at RAM back up state retained Ports P12 P13 output structure selection FR 03 Ln N channel open drain output CMOS output Ports P10 P11 output structure selection FRO2 bit N channel open drain output CMOS output Ports P02 P03 output structure selection FRO1 bit N channel open drain output CMOS output Ports P00 P01 output structure selection FROo bit Port output structure control register FR1 N channel open drain output ek J El ek l l ek IE l ek O CMOS output at reset 00002 at RAM back up state retained FR13 Port D3 output structure selection bit N channel open drain output CMOS output FR12 Port D2 output structure selection bit N channel open drain output CMOS output FR11 Port D1 output structure selection bit N channel open drain output CMOS output FR10 Port Do output structure selection bit Port output structure control register FR2 N channel open drain output k IES l ek LES lesk E leh TE CMOS output at reset 00002 at RA
12. sseseeneenne nenne 3 17 Fig 3 3 6 A D converter operating mode program example eee eee eee ee e e e 3 17 Fig 3 4 1 Selection of packages oonocccincccinnonccnoncinnnccnnanncc canon 3 21 Fig 3 4 2 Wiring for the RESET input lt U 3 21 Eig 9 4 3 Wiring Tor clock O DIIS nacen etes Rettore lt 3 22 Fig 3 4 4 Wiring for CNVSS Pit nnne nnne rnnt nnns nnne rennes 3 22 Fig 3 4 5 Wiring for the VPP pin of the built in PROM version 3 23 Fig 3 4 6 Bypass capacitor across the VSS line and the VDD lne sees eee eee eee eee ee 3 23 Fig 3 4 7 Analog signal line and a resistor and a capacitor sese eee eee eee 3 24 Fig 3 4 8 Wiring for a large current signal line sse sees eee eee eee eee 3 24 Fig 3 4 9 Wiring to a signal line where potential levels change frequently 3 25 Fig 3 4 10 Vss pattern on the underside of an oscillator sese 3 25 Fig 3 4 11 Watchdog timer by software T 3 26 Rev 1 00 Aug 06 2004 RENESAS vii 4519 Group List of tables List of tables CHAPTER 1 HARDWARE Table Selection of system Clock ici a ld 1 6 Table 1 ROM size and Dag88 s ertet edente bea cene det clas exe Rip nave gan 1 20 Table 2 RAM SIZE e TEE 1 21 Table 3 Interrupt SOUICES ottico cedros ere doce ca eee as 1 22 Table 4 Interrupt request flag interrupt enable bit and skip instruction 1 22 Table 5 Interrupt enable bit function sssssssseeeeennm nennen nennen 1 22 Table 6 I
13. Operation A3 A2 AD1 ADo Grouping A D conversion operation A1 Ao 0 Description Transfers the low order 2 bits AD1 ADo of register AD to the high order 2 bits A3 A2 of register A Note After this instruction is executed 0 is stored to the low order 2 bits A1 Ao of register A TAM j Transfer data to Accumulator from Memory Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jo 1 1Jo lol Hi Hi li 2 lc words cycles 2 16 1 1 B H Operation A M DP Grouping RAM to register transfer X X EXOR j Description After transferring the contents of M DP to j20to 15 register A an exclusive OR operation is performed between register X and the value j in the immediate field and stores the re sult in register X Rev 1 00 Aug 06 2004 RENESAS 1 114 REJO9B0175 0100Z HARDWARE 4519 Group MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAMR Transfer data to Accumulator from register MR Instruction D9 code 1 Do Number of Number of Flag CY Skip condition ololilolilololilol fz ls le words cycles 1 1 Operation A MR Grouping Clock operation Description Transfers the contents of clock control reg ister MR to register A TAPUO Transfer data to Accumulator from register PUO Instruction Dg
14. R27 R24 B T27 T24 B R23 R20 lt A T23 T20 A B T37 T34 A T33 T30 R37 R34 B T37 T34 lt B R33 R30 A T33 T30 A B T47 T44 A T43 T40 R4L7 R4La lt B T47 T44 lt B R4La R4Lo lt A T43 T40 A Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 118 136 127 136 118 138 127 138 118 138 127 138 112 138 Timer operation 123 138 110 138 T4HAB R4H7 R4Ha lt B R4H3 R4Ho A R17 R14 lt R37 R34 T47 T44 RAL7 RALA V1220 TTF 21 After skipping T1F 0 V12 2 1 NOP V13 0 T2F 21 After skipping T2F 0 V13 2 1 NOP V20 0 T3F 21 After skipping T3F 0 V20 1 NOP V21 0 T4F 21 After skipping T4F lt 0 V21 1 NOP B R13 R10 lt A B R33 R30 lt A 125 138 125 138 109 140 106 140 106 140 Input Output operation 7tENESAS A lt PO PO lt A A P1 P1 lt A A2 A0 P22 P20 A3 lt 0 P22 P20 A2 A0 A P3 P3 lt A A P4 P4 lt A A lt P5 P5 lt A A P6 96 140 99 140 96 140 99 140 96 140 99 140 97 140 100 140 97 140 100 140 97 140 100 140 97 140 100 140 1 88 4519 Group INDEX LIST OF INSTR
15. F O Set Transmit Data Transmit data is set to serial I O register Serial I O register SI XX16 TSIAB Set Start of Serial I O Operation Serial I O operation enabled state serial transfer started control signal L level output is set Serial transfer start SST Register Y 0 1 Specify bit position of port D TYA Port D3 output latch Set to L output RD Serial transmit receive by clock of master side y Receive Data Processing by Serial I O interrupt Serial I O operation disabled state control signal H level output is set and received data processing is performed b3 b0 Register Y 0101111 Specify bit position of port D TYA Port D3 output latch 1 Set to H output SD Register SI register A register B TABSI y When serial communication is executed repeat to X it can be 0 or 1 J instruction Fig 2 5 6 Setting example when a serial I O interrupt of slave side is used Rev 1 00 Aug 06 2004 RENESAS 2 65 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO 2 5 5 Notes on use 1 Note when an external clock is used as a synchronous clock An external clock is selected as the synchronous clock the clock is not controlled internally Serial transmit receive is continued as long as an external clock is input If an external clock is input 9 times or more and serial tra
16. HARDWARE 4519 Group LIST OF PRECAUTIONS GI Period measurement circuit When a period measurement circuit is used clear bit 0 of regis ter 11 to 0 and set a timer 1 count start synchronous circuit to be not selected Start timer operation immediately after operation of a period measurement circuit is started When the edge for measurement is input until timer operation is started from the operation of period measurement circuit is started the count operation is not executed until the timer opera tion becomes valid Accordingly be careful of count data When data is read from timer stop the timer and clear bit 2 of register W5 to 0 to stop the period measurement circuit and then execute the data read instruction Depending on the state of timer 1 the timer 1 interrupt request flag T1F may be set to 1 when the period measurement cir cuit is stopped by clearing bit 2 of register W5 to 0 In order to avoid the occurrence of an unexpected interrupt clear the bit 2 of register V1 to 0 refer to Figure 610 and then stop the bit 2 of register W5 to 0 to stop the period measurement circuit In addition execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction refer to Figure 610 Also set the NOP instruction for the case when a skip is per formed with the SNZT1 instruction refer to Figure 610 While a period measurement circuit is operating the time
17. HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TFR3A Transfer data to register FR3 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1 oJ ojo 1Jol1 o 1J1 o B wales cycles 2 16 1 1 Operation FR3 lt A TIA Transfer data to register 11 from Accumulator Grouping Input Output operation Description Transfers the contents of register A to the port output structure control register FR3 Instruction Dg Do Number of Number of Flag CY Skip condition code 1 oJojofoj1lo 1 Ji 1 2 7 welds EES 2 16 1 1 Operation 11 A Grouping Interrupt operation TI2A Transfer data to register I2 from Accumulator Description Transfers the contents of register A to inter rupt control register 11 Instruction Dg Do Number of Number of Flag CY Skip condition code to ofo of1 1folofo 2 wets mee 2 16 1 1 Operation 12 A Grouping Interrupt operation TJ1A Transfer data to register J1 from Accumulator Description Transfers the contents of register A to inter rupt control register 12 Instruction Dg Do Number of Number of F
18. INT1 H 122 2 0 INT1 L A e V1 V1 lt A A V2 V2 lt A A lt 11 I1 A A lt 12 I2 lt A 95 136 95 136 104 136 105 136 116 136 126 136 117 136 126 136 113 136 121 136 113 136 121 136 Return operation PC SK SP SP SP 1 PC SK SP SP SP 1 PC SK SP SP SP 1 Note p is 0 to 47 for M34519M6 p is 0 to 63 for M34519M8 E8 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 102 134 Timer operation 13 NE SAS PAo lt Ao A W1 W1 lt A A W2 W2 lt A A W3 W3 lt A 123 136 117 136 126 136 117 136 126 136 117 136 127 136 1 87 4519 Group INDEX LIST OF INSTRUCTION FUNCTION continued Mnemonic Function Page HARDWARE INDEX OF INSTRUCTION FUNCTION Mnemonic Function TAW4 TW4A TAW5 TW5A TAW6 TW6A TABPS c Q S o o o i o E E A W4 W4 lt A A W5 W5 lt A A W6 W6 lt A B TPS7 TPS4 A TPS3 TPSo RPS RPS4 B TPS TPS4 B RPSs RPSo lt A TPS3 TPSo lt A B T17 T14 A T13 T10 R17 R14 B T17 T14 B R13 R10 lt A T13 T10 A B T27 T24 A E T23 T20
19. Key on 4 Level detection circuit KT wakeup 7 TAL TYI IAP1 instruction 4 B TQ Do Level detection circuit A OP1A instruction Key on wakeup Notes 1 HARDWARE PORT BLOCK DIAGRAM Pull up transistor i mrt PUOI fas amp Note n t o Poo P01 Note 2 Pull peste E X Note 1 r4 pa i P02 POs Note 2 Note 1 e Pull up transistor fey Leu X Note 1 l Note 3 3 P10 P11 Note 2 Note 1 77 oc RS Pull up e O transistor i ey Pune X Note 1 d Note 4 4 P12 P13 Note 2 Note 1 777 Ts This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less 3 j represents bits 0 and 1 4 k represents bits 2 and 3 Port block diagram 3 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z RENESAS HARDWARE 4519 Group PORT BLOCK DIAGRAM IAP2 instruction Note 1 O P20 Sck Note 2 OP2A instruction Synchronous clock output for serial data transfer Synchronous clock input a for serial data transfer IAP2 instruction Note 1 p P21 SouT 11 A Note 2 Note 1 0 P22 SIN A Note 2 OP2A instruction Serial data input t Notes 1 This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less o l
20. REJO9B0175 0100Z when external 1 interrupt request flag EXF1 is 1 After skipping clears 0 to the EXF1 flag When the EXF1 flag is 0 executes the next instruction When V11 1 This instruction is equiva lent to the NOP instruction 1 104 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued SNZAD Skip if Non Zero condition of A D conversion completion flag Instruction Dg Do Number of Number of Flag CY Skip condition code 1lol1TofoJolo 11 Ta 7 wolgs cycles 9 i 1 1 V22 0 ADF 1 Operation V22 0 ADF 1 Grouping __A D conversion operation After skipping ADF 0 Description When V22 0 Skips the next instruction V22 1 SNZAD NOP V22 bit 2 of the interrupt control register V2 SNZIO Skip if Non Zero condition of external O Interrupt input pin when A D conversion completion flag ADF is 1 After skipping clears 0 to the ADF flag When the ADF flag is 0 executes the next instruction When V22 1 This instruction is equiva lent to the NOP instruction Instruction Dg Do Number of Number of Flag CY Skip condition code o0j oj0jo 1 1 1 o t o A Worcs i 2 16 1 1 H2 0 INTO L 112 1 INTO H Operation 112 0 INTO L Group
21. interrupt disable state In order to enable the interrupt at the same time when system returns from the interrupt write El and RTI instructions continuously P30 INTO pin When the external interrupt input pin INTO is used set the bit 3 of register 11 to 1 Even in this case port P30 I O function is valid Also the EXFO flag is set to 1 when bit 3 of register 11 is set to 1 by input of a valid waveform valid waveform causing external O interrupt even if it is used as an I O port P30 The input threshold characteristics VIH VIL are different between INTO pin input and port P30 input Accordingly note this difference when INTO pin input and port P30 input are used at the same time P31 INT1 pin When the external interrupt input pin INT1 is used set the bit 3 of register I2 to 1 Even in this case port P31 I O function is valid Also the EXF1 flag is set to 1 when bit 3 of register I2 is set to 1 by input of a valid waveform valid waveform causing external 1 interrupt even if it is used as an I O port P31 The input threshold characteristics ViH VIL are different between INT1 pin input and port P31 input Accordingly note this difference when INT1 pin input and port P31 input are used at the same time POF instruction When the POF instruction is executed continuously after the EPOF instruction system enters the RAM back up state Note that system cannot enter the RAM back up state when
22. p Note PCL DR2 DRo A3 A0 1 0 psp40 0 ps p2 p po 12 p p BMa O 1 0 a6 a5 a4 a3 a2 ai ao a a 1 1 SP lt SP 1 SK SP PC PCH 2 PCL ae ao S a BML p a 0 0 1 1 0 p pa p pi po 0 Cp 2 2 SP lt SP 1 QD p SK SP PC o PCH p Note o 1 0 p5 a6 a5 a4 a3 a2 ai ao 2p a PCL ae ao a 9 5 BMLA p 0 0001 1000 0 030 2 2 SP SP 1 e SK SP PC 1 0 p O 0 px p p po 2p p PCH p Note PCL DR2 DRo A3 Ao RTI 0 00 1 000 1 0 04 6 1 1 PC SK SP SP SP 1 c 9 RT 0 001 0 0 0 1 0 0 0 4 4 1 2 PC SK SP B SP SP 1 a RTS 0 00 1 0 0 O 1 0 1 045 1 2 PC lt SK SP SP SP 1 Note p is 0 to 47 for M34519M6 p is 0 to 63 for M34519M8 E8 Rev 1 00 Aug 06 2004 RENESAS 1 134 REJO9B0175 0100Z 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description Branch within a page Branches to address a in the identical page Branch out of a page Branches to address a in page p Branch out of a page Branches to address DR2 DR1 DRo A3 A2 A1 Ao 2 specified by registers D and A in page p Call the subroutine in page 2 Calls the subroutine at address a in page 2 Call the subroutine Calls the subroutine at address a in page p Call the subroutine Calls the subroutine at address DR2 DR1 DRo A3 A2 A1 Ao 2 specified by registers D and A in page p Skip at unc
23. 0 V21 1 NOP A Q1 Q1 lt A A Q2 Q2 A A Q3 Q3 A 115 144 124 144 116 144 124 144 116 144 124 144 1 89 HARDWARE 4519 Group INDEX OF INSTRUCTION FUNCTION INDEX LIST OF INSTRUCTION FUNCTION continued Mnemonic Function Page NOP PC PC 1 99 144 POF Transition to RAM back up mode 101 144 EPOF POF instruction valid 96 144 SNZP P 1 2 105 144 DWDT Stop of watchdog timer function 95 144 enabled c o 2 S o o O o lt O WDF1 12 128 144 After skipping WDF1 0 System reset occurrence 107 144 Rev 1 00 Aug 06 2004 RENESAS 1 90 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET A n Add n and accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 0 0 0 1 1 0 n n n n n ls WOO cycles 1 1 Overflow 0 Operation A A n Grouping Arithmetic operation n 0to 15 Description Adds the value n in the immediate field to register A and stores a result in register A The contents of carry flag CY remains
24. A D conversion completion flag ADF Serial I O transmission reception completion flag SIOF Interrupt enable flag INTE Watchdog timer flags WDF1 WDF2 X Note 4 Watchdog timer enable flag WEF X Note 4 Notes 1 O represents that the function can be retained and X repre sents that the function is initialized Registers and flags other than the above are undefined at RAM back up and set an initial value after returning 2 The stack pointer SP points the level of the stack register and is initialized to 7 at RAM back up 3 The state of the timer is undefined 4 Initialize the watchdog timer with the WRST instruction and then execute the POF instruction 5 The valid invalid of the voltage drop detection circuit can be con trolled only by VDCE pin 1 63 4519 Group 4 Return signal An external wakeup signal is used to return from the RAM back up mode because the oscillation is stopped Table 19 shows the return condition for each return source 5 Related registers Key on wakeup control register KO Register KO controls the ports PO and P1 key on wakeup func tion Set the contents of this register through register A with the TKOA instruction In addition the TAKO instruction can be used to transfer the contents of register KO to register A Key on wakeup control register K1 Register K1 c
25. HARDWARE FUNCTION BLOCK OPERATIONS 987 654 321 0 000016 007F16 008016 OOFF16 010016 017F16 018016 Interrupt address page Subroutine special page 1FFF16 Fig 10 ROM map of M34519M8 E8 9876543210 008016 008216 008416 008616 008816 008A16 008C16 008E16 Fig 11 Page 1 addresses 008016 to OOFF16 structure 1 20 4519 Group DATA MEMORY RAM 1 word of RAM is composed of 4 bits but 1 bit manipulation with the SB j RB j and SZB j instructions is enabled for the entire memory area A RAM address is specified by a data pointer The data pointer consists of registers Z X and Y Set a value to the data pointer certainly when executing an instruction to access RAM also set a value after system returns from RAM back up Table 2 shows the RAM size Figure 12 shows the RAM map Note Register Z of data pointer is undefined after system is released from reset Also registers Z X and Y are undefined in the RAM back up After System is returned from the RAM back up set these registers RAM 384 words X 4 bits 1536 bits NS Register Z HARDWARE FUNCTION BLOCK OPERATIONS Table 2 RAM size Part number M34519M6 M34519M8 E8 RAM size 384 words X 4 bits 1536 bits Register Y M34519M8 E8 384 words Fig 12 RAM map Rev 1 00 Aug 06 2004 REJ09B0175 0100Z 132 NE S
26. Interrupt enable flag INTE 0 All interrupts disabled DI b3 Interrupt control register V1 x X 10 b1 External 1 interrupt occurrence disabled TV1A b3 Interrupt control register V2 x O b0 Timer 3 interrupt occurrence disabled TV2A Initialize Valid Waveform TI2A INT1 pin is initialized b3 INT1 pin input disabled b2 Rising waveform Interrupt control register 12 b1 One sided edge detected b0 Timer 3 count start synchronous circuit not selected G Stop Timer 3 and Prescaler Operation Timer 3 and prescaler are temporarily stopped TW3A Timer 3 count source is selected b3 Timer 3 count auto stop circuit not selected b3 b2 Timer 3 stop Timer control register W3 0 b1 bO Prescaler output ORCLK selected for Timer 3 count source Timer control register PA Prescaler stop TPAA Set Port INT1 pin is set to input Port P31 output latch Set to input OP3A O Set Timer Value and Prescaler Value Timer 3 and prescaler count times are set The formula is shown A below Timer 3 reload register R3 5216 Timer count value 82 set T3AB Prescaler reload register RPS 0F16 Prescaler count value 15 set TPSAB Clear Interrupt Request Timer 3 interrupt activated condition is cleared Timer 3 interrupt request flag T3F 0 Timer 3 interrupt activated condition cleared SNZT3 When is executed considering the
27. L gt H or falling edge H L The external interrupt request flags EXFO EXF1 are not set 3 Start condition identification When system returns from both RAM back up mode and reset program is started from address 0 in page O Select the return level L level or H level with the registers 11 and I2 according to the external state and return condition return by level or edge with the register K2 before going into the RAM back up state The start condition warm start or cold start can be identified by examining the state of the power down flag P with the SNZP instruction Table 2 8 3 shows the start condition identification and Figure 2 8 4 shows the start condition identified example Table 2 8 3 Start condition identification Start condition P flag Timer 5 interrupt request flag Warm start External wakeup signal input 1 0 Cold start Reset pulse input to RESET pin 0 0 Reset Reset by watchdog timer Reset by voltage drop detection circuit SRST instruction execution Warm start Cold start Fig 2 8 2 Start condition identified example Rev 1 00 Aug 06 2004 RENESAS 2 73 REJO9B0175 0100Z APPLICATION 4519 Group 2 8 RAM back up 2 8 2 Related registers 1 Interrupt control register 11 Table 2 8 4 shows the interrupt control register 11 Set the contents of this register through register A with the TI1A instruction In addition the TAI1 instruction can b
28. Q13 bit 3 of A D control register Q1 Transfers the low order 2 bits AD1 ADo of register AD to the high order 2 bits AD3 AD2 of register A In the comparator mode Q13 1 transfers the contents of register B to the high order 4 bits AD7 AD4 of comparator register and the contents of register A to the low order 4 bits AD3 ADo of comparator register Q13 bit 3 of A D control register Q1 Clears 0 to A D conversion completion flag ADF and the A D conversion at the A D conversion mode Q13 0 or the comparator operation at the comparator mode Q13 1 is started Q13 bit 3 of A D control register Q1 When V22 0 Skips the next instruction when A D conversion completion flag ADF is 1 After skipping clears 0 to the ADF flag When the ADF flag is 0 executes the next instruction V22 bit 2 of interrupt con trol register V2 Transfers the contents of A D control register Q1 to register A Transfers the contents of register A to A D control register Q1 Transfers the contents of A D control register Q2 to register A Transfers the contents of register A to A D control register Q2 Transfers the contents of A D control register Q3 to register A Transfers the contents of register A to A D control register Q3 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z No operation Adds 1 to program counter value and others remain unchanged Puts the system in RAM back up state by executing the POF
29. X represents that the function is initialized Registers and flags other than the above are undefined at RAM back up and set an initial value after returning 2 The stack pointer SP points the level of the stack register and is initialized to 7 at RAM back up The state of the timer is undefined 4 Initialize the watchdog timer flag WDF1 with the WRST instruction and then go into the RAM back up state 5 The valid invalid of the voltage drop detection circuit can be controlled only by VDCE pin Rev 1 00 Aug 06 2004 RENESAS 2 12 REJO9B0175 0100Z 4519 Group Table 2 8 2 Return source and return condition Return source Return condition APPLICATION 2 8 RAM back up Remarks Ports POo P03 Return by an external H level or L level input or rising edge L gt H or falling edge H 5 L The key on wakeup function can be selected with 2 port units Select the return level L level or H level and return condition return by level or edge with the register K1 according to the external state before going into the RAM back up state Ports P10 P13 Return by an external L level input The key on wakeup function can be selected with 2 port units Set the port using the key on wakeup function to H level before going into the RAM back up state External wakeup signal Return by an external H level or L level input or rising edge
30. control bit Key on wakeup control register K1 Key on wakeup used reset 00002 at RAM back up state retained Ports P02 and P03 return condition selection Return by level bit Return by edge Ports P02 and P03 valid waveform Falling waveform L level level selection bit Rising waveform H level Ports P01 and POo return condition selection Return by level bit Return by edge Ports P01 and POo valid waveform Falling waveform L level AfOo fjO O O level selection bit Key on wakeup control register K2 Rising waveform H level reset 00002 at RAM back up state retained Return by level INT1 pin return condition selection bit Return by edge Key on wakeup not used INT1 pin key on wakeup contro bit Key on wakeup used Return by level INTO pin return condition selection bit Return by edge Key on wakeup not used AfOo O O O INTO pin key on wakeup contro bit Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7RENESAS Key on wakeup used 1 66 4519 Group HARDWARE FUNCTION BLOCK OPERATIONS Table 22 Key on wakeup control register pull up control register Pull up control register PUO at reset 00002 at RAM back up state retained P03 pin pull up transistor Pull up transistor OFF
31. 0 0 is output to specified port P5 If FR3i is 1 the output latch value is output to specified port P5 O Output The contents of register A is set to the output latch with the OP5A instruction and is output to port P5 N channel open drain or CMOS can be selected as the output structure of port P5 in 2 bits unit by setting FR3i 7 Port P6 Port P6 is a 4 bit I O port Port P60 P63 are also used as analog input pins AINO AINS3 O Input In the following conditions the pin state of port P6 is transferred as input data to register A when the IAP6 instruction is executed Set the output latch of specified port P6i i 0 1 2 or 3 to 1 with the OP6A instruction If the output latch is 0 0 is output to specified port P6 O Output The contents of register A is set to the output latch with the OP6A instruction and is output to port P6 The output structure is an N channel open drain Rev 1 00 Aug 06 2004 RENESAS 2 4 Port P40 P43 are also used as analog input pins AIN4 AIN7 O Input In the following conditions the pin state of port P4 is transferred as input data to register A when the IAP4 instruction is executed e Set the output latch of specified port P4i i 0 1 2 or 3 to 1 with the OP4A instruction If the output latch is 0 0 is output to specified port P4 O Output The contents of register A is set to the output latch with the OP4A instruction and is output to port P4 The
32. 1 Grouping Other operation Description Skips the next instruction when the P flag is oy After skipping the P flag remains un changed Executes the next instruction when the P flag is 0 Rev 1 00 Aug 06 2004 RENESAS 1 105 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued SNZSI Skip if Non Zero condition of Serial l o interrupt request flag Instruction Dg Do Number of Number of Flag CY Skip condition code 1 o 1 Jo o o 1 o o o 2 Je e Ke SIRE 1 1 V23 0 SIOF 1 Operation V23 0 SIOF 1 Grouping Serial I O operation After skipping SIOF lt O Description When V23 0 Skips the next instruction V23 1 SNZSI NOP when serial I O interrupt request flag SIOF V23 bit 3 of interrupt control register V2 is 1 After skipping clears 0 to the SIOF flag When the SIOF flag is 0 executes the next instruction When V23 1 This instruction is equiva lent to the NOP instruction SNZT1 Skip if Non Zero condition of Timer 1 interrupt request flag Instruction Dg Do Number of Number of Flag CY Skip condition code t
33. 1 mA L level output voltage DD 5V loL 12 mA PO P1 P2 P4 P5 P6 IOL 4 mA Sck SouT DD 3V loL 6 mA IOL 2 mA L level output voltage DD 5V loL 5 mA P3 RESET loL 1 mA DD lt 2 Y loL 2 2 mA L level output voltage DD 5V loL 2 15 mA Do D5 loL 2 5 mA DD lt 2 Y loL 2 9 mA IOL 3 mA L level output voltage DD 5V IOL 30 mA De D7 CNTRO CNTR1 loL 10 mA VDD 3V loL 2 15 mA IOL 5 mA H level input current Vi VDD PO P1 P2 P3 P4 P5 P6 Ports P4 P6 selected Do D7 VDCE RESET Sck SIN CNTRO CNTR1 INTO INT1 L level input current Vi 0V PO P1 P2 P3 P4 P5 P6 PO P1 No pull up Do D7 VDCE Ports P4 P6 selected Sck SIN CNTRO CNTR1 INTO INT1 Pull up resistor value 20V PO P1 RESET Hysteresis DD 5V Sck SIN CNTRO CNTR1 INTO INT1 DD 3V Hysteresis RESET DD 5V DD 3V On chip oscillator clock frequency DD 5V DD 3V ask ROM version VDD 1 8 V Frequency error DD 5 V 10 Ta 25 C with RC oscillation error of external R C not included DD 3 V t 10 Ta 25 C Note Note When RC oscillation is used use the external 30 pF or 33 pF capacitor C Rev 1 00 Aug 06 2004 RENESAS 3 6 REJ09B0175 0100Z 4519 Group Table 3 1 6 Electrical characteristics 2 Mask ROM version Ta 20 C to 85 C VDD 1 8 to 5 5 V unl
34. 2 16 1 1 B Operation A KO Grouping Input Output operation Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2RENESAS Description Transfers the contents of key on wakeup control register KO to register A 1 113 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAK1 Transfer data to Accumulator from register K1 Instruction Dg Do Number of Number of Flag CY Skip condition code tlojol1lo 1 1loJo 1 fe 9 Worgs cycles 2 16 1 1 H H Operation A lt K1 Grouping Input Output operation Description Transfers the contents of key on wakeup control register K1 to register A TAK2 Transfer data to Accumulator from register K2 Instruction Dg Do Number of Number of Flag CY Skip condition code 1 olols ol s slo s 0 fe A wores cycles 2 16 1 1 _ Operation A K2 Grouping Input Output operation Description Transfers the contents of key on wakeup control register K2 to register A TALA Transfer data to Accumulator from register LA Instruction Dg Do Number of Number of Flag CY Skip condition code 1 o o 1fo ol1rfo ol1 2 4 o oo ayers 2 16 1 1
35. 2004 RENESAS 2 47 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers Timer 1 interrupt occurrence period measurement completed O Stop Timer Operation Timer 1 interrupt is disabled TW1A Timer control register W1 b2 Timer 1 stop Disable Interrupts Timer 1 interrupt is disabled Interrupt control register V1 b2 Timer 1 interrupt occurrence disabled TV1A G Stop Period Measurement circuit Period measurement circuit is stopped Timer control register W5 b2 Period measurement circuit stop TW5A amp Execute NOP Instruction NOP y O Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction y O Measurement Data Processing Timer 1 count value is read out Timer 1 gt Register A Register B TAB1 X it can be 0 or 1 PP instruction Fig 2 3 12 Pulse width measurement of INTO pin input setting example 2 Rev 1 00 Aug 06 2004 RENESAS 2 48 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers Main Routine every 20 ms O Reset Flag WDF1 Watchdog timer flag WDF1 is reset 0 Watchdo
36. AIN1 O AIN2 1 AIN3 0 1 0 Table 2 4 2 A D control register Q1 A D control register Q1 R W Q13 A D operation mode control bit Q12 Q11 Analog input pin selection bits AIN4 AIN5 AIN6 AIN7 Notes 1 R represents read enabled and W represents write enabled 2 In order to select AIN7 AINO set register Q1 after setting regsiter Q2 Rev 1 00 Aug 06 2004 RENESAS 2 53 REJ09B0175 0100Z APPLICATION 4519 Group 2 4 A D converter 3 A D control register Q2 Table 2 4 3 shows the A D control register Q2 Set the contents of this register through register A with the TQ2A instruction The contents of register Q2 is transferred to register A with the TAQ2 instruction at reset 00002 at RAM back up state retained Table 2 4 3 A D control register Q2 A D control register Q2 R W Q2 P23 A nina TEE 0 P40 P41 P42 P43 3 3 AIN3 pin function selection bi 1 AN4 AINS ANE AN7 P62 AIN2 P63 AIN3 pin function 0 P62 P63 Q22 selection bit 1 AIN2 AIN3 0 P61 Q21 P61 AIN1 pin function selection bit 1 AIN1 0 P60 Q20 P60 AINO pin function selection bit 1 AINO Note R represents read enabled and W represents write enabled 4 A D control register Q3 Table 2 4 4 shows the A D control register Q3 Set the contents of this register through register A with the TQ3A instruction The contents of register Q3 is transfer
37. As oscillation stops with RAM and the state of reset circuit retained current dissipation can be reduced without losing the contents of RAM Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS 2 71 APPLICATION 4519 Group 2 8 RAM back up Table 2 8 1 Functions and states retained at RAM back up mode Function RAM back up Program counter PC registers A B carry flag CY stack pointer SP Note 2 x Contents of RAM O Interrupt control registers V1 V2 x Interrupt control registers 11 12 O Selected oscillation circuit O Clock control register MR O Timer 1 to timer 4 functions Note 3 Watchdog timer function x Note 4 Timer control registers PA W4 x Timer control registers O W1 to W3 W5 W6 Serial I O function x Serial I O control register J1 O A D function x A D control registers Q1 to Q3 O Voltage drop detection circuit O Note 5 Port level O Pull up control registers PUO PU1 O Key on wakeup control registers KO to K2 O Port output format control registers FRO to FR3 O External interrupt request flags EXFO EXF1 x Timer interrupt request flags T1F to T4F Note 3 A D conversion completion flag ADF x Serial I O transmit receive completion flag SIOF x Interrupt enable flag INTE x Watchdog timer flags WDF1 WDF2 X Note 4 Watchdog timer enable flag WEF X Note 4 Notes 1 O represents that the function can be retained and
38. DI b1 External 1 interrupt occurrence disabled TV1A Set to input OP3A TI2A b3 INT1 pin input enabled b2 b1 One sided edge detection and falling waveform selected Execute NOP Instruction NOP O Clear Interrupt Request External 1 interrupt activated condition is cleared External 1 interrupt request flag EXF1 0 y External 1 interrupt activated condition cleared SNZ1 Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag EXF1 insert the NOP instruction after the SNZ1 instruction Enable Interrupts y The External 1 interrupt which is temporarily disabled is enabled Interrupt control register V1 Interrupt enable flag INTE b3 bO X x 7 X 1 b1 External 1 interrupt occurrence enabled TV1A All interrupts enabled El External 1 interrupt enabled state X it can be 0 or 1 J instruction Fig 2 2 4 External 1 interrupt setting example Note The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS 2 25 APPLICATION 4519 Group 2 2 Interrupts O Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI Interrup
39. H pulse width from rising to fall ing when its level is L is measured When the input of P30 INTO pin is selected as the target for mea surement set the bit 3 of register 11 to 1 and set the input of INTO pin to be enabled 1 39 4519 Group 9 Count start synchronization circuit timer 1 timer 3 Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INTO pin and INT1 pin and can start the timer count operation Timer 1 count start synchronous circuit function is selected by set ting the bit O of register 11 to 1 and the control by INTO pin input can be performed Timer 3 count start synchronous circuit function is selected by set ting the bit O of register I2 to 1 and the control by INT1 pin input can be performed When timer 1 or timer 3 count start synchronous circuit is used the count start synchronous circuit is set the count source is input to each timer by inputting valid waveform to INTO pin or INT1 pin The valid waveform of INTO pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition Once set the count start synchronous circuit is cleared by clearing the bit 110 or 120 to 0 or reset However when the count auto stop circuit is selected the count start synchronous circuit is cleared auto stop at the timer 1 or timer 3 underflow 10 Count auto stop circuit timer 1
40. Port block diagram 6 Rev 1 00 Aug 06 2004 7tENESAS 1 14 REJO9B0175 0100Z HARDWARE 4519 Group PORT BLOCK DIAGRAM Note 3 IAP6 instruction ad A Note 1 P60 AINo P61 AIN1 5 8 a Note 2 a OP6A instruction Decoder Analog input TH Note 4 IAP6 instruction Ka A Note 1 doe P62 AIN2 P63 AIN3 A Note 2 777 OP6A instruction Analog input H pe Notes 1 This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less 3 j represents bits 0 and 1 4 k represents bits 2 and 3 Port block diagram 7 Rev 1 00 Aug 06 2004 RENESAS 1 15 REJO9B0175 0100Z HARDWARE 4519 Group PORT BLOCK DIAGRAM e E i I2 One sided edge Note DE Falling f i External 0 P3o INTOO H b os interrupt j S Period measurement iei Both edges idc 777 detection circuit Tus 1 oui start synchronous circuit Key on wakeup L P gt skip decision SNZIO instruction One sided edge detection circuit External 1 Y interrupt Timer 3 count start synchronous circuit Rising Key on wakeup p Skip decision SNZI1 instruction Notes 1 This symbol represents a parasitic diode on the port 2 112 122 0 L level detected 112 122 1 H level detected 3 112 122 0 Falling edge detected 112 122 1 Rising edge de
41. Set the contents of this register through register A with the TPAA instruction Table 2 3 5 Timer control register PA Timer control register PA PAo Prescaler control bit at RAM back up state retained Stop state initialized Note W represents write enabled 6 Timer control register W1 Operating Table 2 3 6 shows the timer control register W1 Set the contents of this register through register A with the TW1A instruction In addition the TAW1 instruction can be used to transfer the contents of register W1 to register A Table 2 3 6 Timer control register W1 Timer control register W1 at reset 00002 at RAM back up state retained R W W13 Timer 1 count auto stop circuit 0 Timer 1 count auto stop circuit not selected control bit Note 2 1 Timer 1 count auto stop circuit selected 0 Stop state retained W12 Timer 1 control bit 1 Operating W11W10 Count source Wit O 0 Instruction clock INSTCK Pus 1 count source selection o 1 Prescaler output ORCLK its Wio 1 O XIN input CNTRO input Notes 1 R represents read enabled and W represents write enabled 2 This function is valid only when the timer 1 count start synchronous circuit is selected l102 1 7 Timer control register W2 Table 2 3 7 shows the timer control register W2 Set the contents of this register through register A with the TW2A
42. TW6A b0 Set to CNTRO input port amp Set Timer Values Timer 1 count time is set Timer 1 reload register R1 Timer count value 99 set T1AB Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction O Start Timer Operation Timer 1 temporarily stopped is restarted Timer control register W1 b2 Timer 1 operation start TW1A O Enable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V1 X X Interrupt enable flag INTE 1 1 X b2 Timer 1 interrupt occurrence enabled TV1A All interrupts enabled El Input signal count started X it can be 0 or 1 lI instruction Fig 2 3 6 CNTRO input setting example However specify the pulse width input to CNTRO pin CNTR1 pin Refer to section 3 1 Electrical characteristics for the timer external input period condition Rev 1 00 Aug 06 2004 2 42 REJO9B0175 0100Z l ENESAS APPLICATION 4519 Group 2 3 Timers O Disable Interrupts Timer 3 interrupt and external interrupt are temporarily disabled
43. The interrupt enabled with the EI instruction is performed after the EI instruction and one more instruction Interrupt request flag The activated condition for each interrupt is examined Each interrupt request flag is set to 1 when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit Each interrupt request flag is cleared to 0 when either an interrupt occurs or the next instruction is skipped with a skip instruction Interrupt control register V1 Table 2 2 1 shows the interrupt control register V1 Set the contents of this register through register A with the TV1A instruction In addition the TAV1 instruction can be used to transfer the contents of register V1 to register A Table 2 2 1 Interrupt control register V1 Interrupt control register V1 at reset 00002 at RAM back up 00002 R W 0 Interrupt disabled SNZT2 instruction is valid MEL UL 1 Interrupt enabled SNZT2 instruction is invalid Note 2 ves Timer timemo Enable Dik 0 Interrupt disabled SNZT1 instruction is valid 1 Interrupt enabled SNZT1 instruction is invalid Note 2 Vir JExetabd mnterupt exsble Bit 0 Interrupt disabled SNZ1 instruction is valid 1 Interrupt enabled SNZ1 instruction is invalid Note 2 Vie Bastalo intenupt enable bi 0 Interrupt disabled SNZO instruction is valid 1 Interrupt enabled SNZO instruction is invalid Note
44. Timer 4 At CNTR1 output vaild if a timing of timer 4 underflow overlaps with a timing to stop timer 4 a hazard may be generated in a CNTR1 output waveform Please review sufficiently e When H interval extension function of the PWM signal is set to be valid set 0116 or more to reload register RAH Watchdog timer The watchdog timer function is valid after system is released from reset When not using the watchdog timer function stop the watchdog timer function and execute the DWDT instruction the WRST instruction continuously and clear the WEF flag to 0 The watchdog timer function is valid after system is returned from the RAM back up state When not using the watchdog timer function stop the watchdog timer function and execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back up state When the watchdog timer function and RAM back up function are used at the same time initialize the flag WDF1 with the WRST instruction before system enters into the RAM back up state Pulse width input to CNTRO pin CNTR1 pin Refer to section 3 1 Electrical characteristics for rating value of pulse width input to CNTRO pin CNTR1 pin Period measurement circuit O When a period measurement circuit is used clear bit O of register 11 to 0 and set a timer 1 count start synchronous circuit to be not selected O While a period measurement circuit is operati
45. less If the rising time exceeds 100 us connect a capacitor between the RESET pin and Vss at the shortest distance and input L level to RESET pin until the value of supply voltage reaches the minimum rating value of the recommended operating conditions 100 us or less von Note 3 Pull up transistor f Power on reset circuit output Note Y aH Note 2 RESET pin do Internal reset signal Power on reset circuit Note YA x LT SRST instruction de A L voltage drop detection circuit Internal reset signal LH Watchdog reset signal WEF Reset state Power on Reset released Notes 1 This symbol represents a parasitic diode 2 Applied potential to RESET pin must be VDD or less 3 Keep the value of supply voltage to the minimum value or more of the recommended operating conditions Fig 2 6 1 Structure of reset pin and its peripherals and power on reset operation Reset input li On chip oscillator internal oscillator is 1 machine cycle or more counted 120 to 144 times K 4 K Program starts address 0 in page 0 Note Keep the value of supply voltage to the minimum value or more of the recommended operating conditions Fig 2 6 2 Oscillation stabilizing time after system is released from reset Rev 1 00 Aug 06 2004 RENESAS 2 67 REJ09B0175 0100Z APPLICATION 4519 Group 2 6 Reset 2 6 2 Intern
46. or the next instruction is skipped with a skip instruction Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its in terrupt enable bit Once set the interrupt request flag retains set until a clear condition is satisfied Accordingly an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set If more than one interrupt request flag is set when the interrupt dis able state is released the interrupt priority level is as follows shown in Table 3 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z HARDWARE FUNCTION BLOCK OPERATIONS Table 3 Interrupt sources Priority level Interrupt name Activated condition Interrupt address External 0 interrupt Level change of INTO pin Address 0 in page 1 External 1 interrupt Level change of INT1 pin Address 2 in page 1 Timer 1 interrupt Timer 1 underflow Address 4 in page 1 Timer 2 interrupt Timer 2 underflow Address 6 in page 1 Timer 3 interrupt Timer 3 underflow Address 8 in page 1 Timer 4 interrupt Timer 4 underflow Address A in page 1 A D interrupt Completion of A D conversion Address C in page 1 Serial 1 O interrupt Completion of serial I O transmit receive Address E in page 1 Table 4 Interrupt request flag interrupt enable bit and skip in struction I
47. these bits are not used here X these bits are not used here Fig 62 External 0 interrupt program example 1 Fig 64 External 0 interrupt program example 3 O Note 2 on bit 3 of register 11 When the bit 3 of register 11 is cleared to 0 the RAM back up mode is selected and the input of INTO pin is disabled be careful about the following notes When the input of INTO pin is disabled register 113 0 set the key on wakeup function to be invalid register K20 0 before system enters to the RAM back up mode refer to Figure 630 XXX02 Input of INTO key on wakeup invalid RAM back up X these bits are not used here Fig 63 External 0 interrupt program example 2 Rev 1 00 Aug 06 2004 RENESAS 1 74 REJO9B0175 0100Z 4519 Group P31 INT1 pin Note 1 on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of reg ister I2 in software be careful about the following notes Depending on the input state of the P31 INT1 pin the external 1 interrupt request flag EXF1 may be set when the bit 3 of regis ter I2 is changed In order to avoid the occurrence of an unexpected interrupt clear the bit 1 of register V1 to 0 refer to Figure 650 and then change the bit 3 of register I2 In addition execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction refer to Figure 659 Also set the NOP
48. timer 3 Timer 1 has the count auto stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn chronous circuit is used The count auto stop cicuit is valid by setting the bit 3 of register W1 to 1 It is cleared by the timer 1 underflow and the count source to timer 1 is stopped This function is valid only when the timer 1 count start synchronous circuit is selected Timer 3 has the count auto stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start syn chronous circuit is used The count auto stop cicuit is valid by setting the bit 3 of register W3 to 1 It is cleared by the timer 3 underflow and the count source to timer 3 is stopped This function is valid only when the timer 3 count start synchronous circuit is selected Rev 1 00 Aug 06 2004 REJ09BO0175 0100Z RENESAS HARDWARE FUNCTION BLOCK OPERATIONS 11 Timer input output pin De CNTRO pin D7 CNTR1 pin CNTRO pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2 CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4 The De CNTRO pin function can be selected by bit 0 of register WG The selection of D7 CNTR1 output signal can be controlled by bit 3 of register W4 When the CNTRO input is selected for timer 1 count source timer 1 counts the rising or falling w
49. to the EXF1 flag When the EXF1 flag is 0 executes the next instruction When V11 1 This instruction is equivalent to the NOP instruction V11 bit 1 of interrupt control register V1 When I12 1 Skips the next instruction when the level of INTO pin is H 112 bit 2 of interrupt control reg ister 11 When 112 0 Skips the next instruction when the level of INTO pin is L When 122 1 Skips the next instruction when the level of INT1 pin is H 122 bit 2 of interrupt control reg ister 12 When 122 0 Skips the next instruction when the level of INT1 pin is L Transfers the contents of interrupt control register V1 to register A Transfers the contents of register A to interrupt control register V1 Transfers the contents of interrupt control register V2 to register A Transfers the contents of register A to interrupt control register V2 Transfers the contents of interrupt control register 11 to register A Transfers the contents of register A to interrupt control register l1 Transfers the contents of interrupt control register I2 to register A Transfers the contents of register A to interrupt control register 12 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Transfers the contents of register A to timer control register PA Transfers the contents of timer control register W1 to register A Transfers the contents of register A to timer control register W1 Transfers the contents of
50. 0 1 0 29A 1 1 Ceramic resonator selected S CRCK 1 0 1 0 O 1 1 0 1 1 2 9B 1 1 RC oscillator selected E CYCK 1 0 1 0 0 114 1 1 0 1 29D 1 1 Quartz crystal oscillator selected Q E TRGA 1 000001 00 1 209 1 1 RGo Ao 9 o TAMR 1 0 O 1 O 1 00 1 0 2 52 1 1 A MR TMRA 1 0000 101 1 0 216 1 1 MR lt A Rev 1 00 Aug 06 2004 RENESAS 1 142 REJO9B0175 0100Z 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description Transfers the contents of key on wakeup control register KO to register A Transfers the contents of register A to key on wakeup control register KO Transfers the contents of key on wakeup control register K1 to register A Transfers the contents of register A to key on wakeup control register K1 Transfers the contents of key on wakeup control register K2 to register A Transfers the contents of register A to key on wakeup control register K2 Transferts the contents of register A to port output format control register FRO Transferts the contents of register A to port output format control register FR1 Transferts the contents of register A to port output format control register FR2 Transferts the contents of register A to port output format control register FR3 SIOF 1 Transfers the high order 4 bits of serial I O register SI to register B and transfers the low order 4 bits of se rial I O register SI to register A Transfers the contents of register B to th
51. 1 A E 11 THA 1 0 1 0 1 1 1 217 1 1 11 A TAI2 1 0 1 0 1 0 0 254 1 1 A lt 12 TI2A 1 0 1 1 0 0 0 21 8 1 1 12 A TPAA 1 1 0 1 0 1 0 2AA 1 1 PAo Ao TAW1 1 0 0 1 0 1 1 24 B 1 1 A e W1 TW1A 1 0 0 415 1 1 0 20E 1 1 W1 A TAW2 1 0 0 1 1 0 0 24 1 1 A W2 TW2A 1 0 01 1 1 1 20F 1 1 W2 lt A 2 S TAWS 1 0 0 15 1 0 1 24D 1 1 A lt W3 o a e TW3A 1 0 1 0 0 0 0 210 1 1 W3 lt A o E E TAW4 1 0 0 415 1 1 0 24E 1 1 A e W4 TW4A 1 0 1 0 0 0 1 211 1 1 W4 lt A Rev 1 00 Aug 06 2004 RENESAS 1 136 REJO9B0175 0100Z 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description V10 0 EXFO 1 V11 0 EXF1 1 INTO H However 112 1 INTO L However 112 0 INT1 H However 122 1 INT1 L However 122 0 Clears 0 to interrupt enable flag INTE and disables the interrupt Sets 1 to interrupt enable flag INTE and enables the interrupt When V10 0 Skips the next instruction when external 0 interrupt request flag EXFO is 1 After skipping clears 0 to the EXFO flag When the EXFO flag is 0 executes the next instruction When V10 1 This instruction is equivalent to the NOP instruction V10 bit O of interrupt control register V1 When V11 0 Skips the next instruction when external 1 interrupt request flag EXF1 is 1 After skipping clears 0
52. 1 interrupt Reload register R1 8 Timer 1 underflow signal T1UDF drar Timer 2 interrupt Timer 2 underflow signal T2UDF TR1AB This eed is az le d o Es Notes 1 When CMCK instruction is executed ceramic resonance is selected register A ana register 0 only reload register x x E x v PWMOUT PWM output signal from timer 4 output unit When CRCK instruction is executed RC oscillation is selected When CYCK instruction is executed quartz crystal oscillator is selected Data is set automatically from each reload 2 Timer 1 count start synchronous circuit is set by the valid edge of P30 INTO pin register when timer underflows selected by bits 1 111 and 2 112 of register I1 auto reload function 3 XIN cannot be used for the count source when bit 1 MR1 of register MR is set to 1 and f XIN oscillation is stopped Fig 25 Timer structure 1 Rev 1 00 Aug 06 2004 ENESAS 1 33 REJO9B0175 0100Z HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS One sided edge 123 Ho Both edges detection circuit Timer 3 8 T3F interrupt Reload register R3 8 T3AB CD S S Timer 2 Register B Register A underflow signal T3UDF D7 CNTR1 01 oRcLK 1 2 0 ri T4F Timer 4 interrupt WRST instruction RESET signal Note 7 WEF DWDT instruction4R Watchdog reset s
53. 1 1 0 1 1 2 9 B BS cycles 2 16 1 1 Operation RC oscillation circuit selected Grouping Clock control operation Description Selects the RC oscillation circuit for main clock f XIN CYCK Clock select crYstal oscillation Clock Instruction Do Do Number of Number of Flag CY Skip condition code 1 0 1 0 0 1 1 1 0 1 D ores cyclos 2 16 1 1 x Operation Quartz crystal oscillation circuit selected Grouping Clock control operation Description Selects the quartz crystal oscillation circuit for main clock f XIN Rev 1 00 Aug 06 2004 RENESAS 1 94 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued DEY DEcrement register Y Instruction Dg Do Number of Number of Flag CY Skip condition code oJo ojo oj 1 o 1 1 1 o 1 7 words cycles 1 1 Y 15 Operation Y Y 1 Grouping RAM addresses Description Subtracts 1 from the contents of register Y As a result of subtraction when the con tents of register Y is 15 the next instruction is skipped When the contents of register Y is not 15 the next instruction is executed DI Disable Interrup
54. 10 shows the timer control register W5 Set the contents of this register through register A with the TW5A instruction In addition the TAW5 instruction can be used to transfer the contents of register W5 to register A at reset 00002 at RAM back up state retained Table 2 3 10 Timer control register W5 Timer control register W5 R W 0 A Re W53 Not used This bit has no function but read write is enabled W52 Period measurement circuit 0 Stop control bit 1 Operating 51 Wb5o Count source WS l 0 On chip oscillator f RING 16 S iio measurement o 1 CNTRo pin input selection bits TET W50 1 O INTO pin input 1 Not available Note R represents read enabled and W represents write enabled 11 Timer control register W6 Table 2 3 11 shows the timer control register W6 Set the contents of this register through register A with the TW6A instruction In addition the TAW6 instruction can be used to transfer the contents of register W6 to register A at reset 00002 at RAM back up state retained Table 2 3 11 Timer control register W6 Timer control register W6 R W W63 CNTR1 pin input count edge 0 Falling edge selection bit 1 Rising edge W62 CNTRO pin input count edge 0 Falling edge selection bit 1 Rising edge We CNTR1 output auto control circuit 0 CNTR1 output auto control circuit not selected selection bit 1 CNTR1 out
55. 2 3 16 Time to first underflow in Fig 2 3 16 is different from time among next underflow O in Fig 2 3 16 by the timing to start the timer and count source operations after count starts Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS Timer 1 operation is stopped bit 2 of register KX is cleared to 0 Timer 1 interrupt is disabled bit 2 of register Mi is cleared to 0 Period measurement circuit is stopped bit 2 of register T is cleared to 0 Execute at least one Instruction NOP Timer 1 interrupt request flag T1F is cleared e SNZT1 Considering the skip of the SNZT1 instruction insert the rC instruction Measurement data is read TAB1 Count source Timer value Timer underflow signal l I gt I l o l q Timer start Fig 2 3 15 Count start time and count time when operation starts PS T1 T2 and T3 I l l 1 l count source LIU ULU U ULL l l l Timer value sl2 t o s a o s I I Timer underflow signal O Timer start Fig 2 3 16 Count start time and count time when operation starts T4 2 51 APPLICATION 4519 Group 2 4 A D converter 2 4 A D converter The 4519 Group has an 8 channel A D converter with the 10 bit successive comparison method This A D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values This section describes the related registers application examples
56. 2 61 Fig 2 5 5 Setting example when a serial I O of master side is not used 2 64 Fig 2 5 6 Setting example when a serial I O interrupt of slave side is used 2 65 Fig 2 6 1 Structure of reset pin and its peripherals and power on reset operation 2 67 Fig 2 6 2 Oscillation stabilizing time after system is released from reset 2 67 Figs 2 6 3 Internal State at TeSeL iiem iia 2 68 Fig 2 6 4 Internal st te at roset ertt eerte o De cete tno niae 2 69 Fig 2 7 1 Voltage drop detection circuit essen nnns 2 70 Fig 2 7 2 Voltage drop detection circuit operation waveform example 2 70 Fige 2 8 1 State transition eer desert eed M Lex ruht oras ARR NR ctas idas ads 2 71 Fig 2 8 2 Start condition identified example sees 2 73 Fig 2 9 1 Structure of clock control circuit ssrin eee 2 79 Rev 1 00 Aug 06 2004 RENESAS vi 4519 Group List of figures CHAPTER 3 APPENDIX REJO9B0175 0100Z Fig 3 3 1 Period measurement circuit program example sse 3 16 Fig 3 3 2 Count start time and count time when operation starts PS T1 T2 and T3 3 16 Fig 3 3 3 Count start time and count time when operation starts T4 s 3 16 Fig 3 3 4 Analog input external circuit example 1 sees eee eee eee eee 3 17 Fig 3 3 5 Analog input external circuit example 2
57. 4 S 6 7 8 9 Setting of INTO interrupt valid waveform Set a value to the bit 2 of register 11 and execute the SNZO instruction to clear the EXFO flag to 0 after executing at least one instruction Depending on the input state of P30 INTO pin the external interrupt request flag EXFO may be set to 1 when the bit 2 of register I1 is changed Setting of INTO pin input control Set a value to the bit 3 of register 11 and execute the SNZO instruction to clear the EXFO flag to 0 after executing at least one instruction Depending on the input state of P30 INTO pin the external interrupt request flag EXFO may be set to 1 when the bit 3 of register I1 is changed Setting of INT1 interrupt valid waveform Set a value to the bit 2 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction Depending on the input state of P3 INT1 pin the external interrupt request flag EXF1 may be set to 1 when the bit 2 of register I2 is changed Setting of INT1 pin input control Set a value to the bit 3 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction Depending on the input state of P3 INT1 pin the external interrupt request flag EXF1 may be set to 1 when the bit 3 of register 12 is changed Multiple interrupts Multiple interrupts cannot be used in the 4
58. 54 shows the structure of the clock control circuit The 4519 Group operates by the on chip oscillator clock f RING which is the internal oscillator after system is released from reset Also the ceramic resonator the RC oscillation or quartz crystal os cillator can be used for the main clock f XIN of the 4519 Group The CMCK instruction CRCK instruction or CYCK instruction is ex ecuted to select the ceramic resonator RC oscillator or quartz crystal oscillator respectively O HARDWARE FUNCTION BLOCK OPERATIONS The CMCK CRCK and CYCK instructions can be used only to se lect main clock f XIN In this time the start of oscillation and the Switch of system clock are not performed The oscillation start stop of main clock f XIN is controlled by bit 1 of register MR The system clock is selected by bit 0 of register MR The oscillation start stop of on chip oscillator is controlled by register RG The oscillation circuit by the CMCK CRCK or CYCK instruction can be selected only at once The oscillation circuit corresponding to the first executed one of these instructions is valid Execute the main clock f XIN selection instruction CMCK CRCK or CYCK instruction in the initial setting routine of program ex ecuting it in address 0 in page 0 is recommended When the CMCK CRCK and CYCK instructions are never ex ecuted main clock f XIN cannot be used and system can be operated only by on chip oscillator T
59. 8 words cycles 16 1 1 Operation B SI7 Sl4 Grouping Serial I O operation A lt Sl3 Slo Description Transfers the high order 4 bits SI7 Sl4 of serial I O register SI to register B and transfers the low order 4 bits Sl3 Slo of serial I O register SI to register A TAD Transfer data to Accumulator from register D Instruction D9 Do Number of Number of Flag CY Skip condition code olololi 1 1 words cycles 16 1 1 Operation A2 Ao DR2 DRo Grouping Register to register transfer A3 0 Description Transfers the contents of register D to the low order 3 bits A2 Ao of register A Note When this instruction is executed 0 is stored to the bit 3 A3 of register A TADAB Transfer data to register AD from Accumulator from register B Instruction D9 Do Number of Number of Flag CY Skip condition code 1 lololo 1 9 words cycles 16 1 1 iU Grouping X A D conversion operation Operation VSA e B Description In the A D conversion mode Q13 0 this in ADs ADo lt A struction is equivalent to the NOP instruction In the comparator mode Q13 1 trans fers the contents of register B to the high order 4 bits AD7 AD4 of comparator register and the contents of register A to the low order 4 bits AD3 ADo of compara tor register Q13 bit 3 of A D control register Q1 Rev 1 00 Aug 06 2004 RENESAS 1 112 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY AL
60. A Transfers the contents of register A to pull up control register PUO Transfers the contents of pull up control register PU1 to register A Transfers the contents of register A to pull up control register PU1 RENESAS 1 141 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code o 15 25 29 Function 95099 Type of SIRE Hexadecimal E 2 E gt l De Ds D7 De Ds D4 D3 D2 Di Do El gt instruction notation z z TAKO 1 0 O 1 0 1 0 1 1 0 256 1 1 A lt KO TKOA 1 0000 1 1 0 1 1 21 B 1 1 K0 A TAK1 1 0 O 1 O 1 1 0 0 1 259 1 1 A K1 c TK1A 1 00001 01 0 0 214 1 1 K1 lt A 0 S TAK2 1 0 O 1 O 1 1 0 1 0 25A 1 1 A K2 5 2 TK2A 1 0000 1 O 1 0 1 215 1 1 K2 lt A O 2 TFROA 1 0001 01 0 0 0 228 1 1 FRO A c TFR1A 1 000 1 O 1 0 0 1 229 1 1 FR1 lt A TFR2A 1 0 0O O 1 O 1 0 1 0 22A 1 1 FR2 lt A TFR3A 1 000 1 0 1 0 1 1 22 B 1 1 FR3 A TABSI 1 0 O 1 1 1 1 0 0 0 278 1 1 B SI7 Sl4 A Sl3 Slo TSIAB 1 000 1 1 1 0 0 0 238 1 1 Sl7 Sl4 B Sl3 Slo A 2 S 9 SST 1 0 1 0 0 1 1 1 1 0 29E 1 1 KSIOF 0 E Serial 1 O starting Q T SNZSI 1 0O 1 0 0O O 1i 0 0 0 288 1 1 V23 0 SIOF 1 amp After skipping SIOF 0 V23 1 NOP TAJ1 1 0 O 1 0000 1 0 242 1 1 A J1 TJ1A 10000000 1 0 202 1 1 J1 A CMCK 1 O 1 0 O 1 1
61. A PCL DR2 DRo A3 Ao These bits 7 to O are the ROM pattern in ad ae dress DR2 DR1 DRo A3 A2 A1 Ao 2 specified by registers A and D in page p DR1 DRo ROM PC s 8 Note p is 0 to 47 for M34519M6 and p is 0 to 63 for B ROM PO 7 4 M34519M8E8 A ROM PC 3 0 When this instruction is executed be careful not to PC SK SP over the stack because 1 stage of stack register is SP SP 1 used Rev 1 00 Aug 06 2004 RENESAS 1 111 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TABPS Transfer data to Accumulator and register B from PreScaler Instruction Dg Do Number of Number of Flag CY Skip condition code t olol4 1 5 words cycles 16 1 1 Operation B TPS7 TPS4 Grouping Timer operation A TPS3 TPSo Description Transfers the high order 4 bits TPS7 TPS4 of prescaler to register B and transfers the low order 4 bits TPS3 TPSo of prescaler to register A TABSI Transfer data to Accumulator and register B from register SI Instruction Dg Do Number of Number of Flag CY Skip condition code Ta Tal 1 0
62. ALPHABET nee 1 91 MACHINE INSTRUCTIONS INDEX BY TYPES serrer 1 130 INSTRUCTION CODE TABLE unte m a 1 146 BUILT IN PROM VERSION icto aes m dade iti De i otl te ies tree 1 148 Rev 1 00 Aug 06 2004 RENESAS i REJO9B0175 0100Z 4519 Group CHAPTER 2 APPLICATION Table of contents WO DINS aes coe aerate a cece cen eec uence EEE E atest cencers e ea eutudeceesexetucecess 2 2 Ded ll he eei nina lio tilde lada 2 2 2 122 Related fegisters REED iE eee eee Ae 2 6 2 1 3 Port application examples ssssssssssssssseseeee ener nnne enne en 2 12 2 AeA NOS OM USG iori iii 2 13 2 2 INTOFrUPES cuina 2 15 2 211 Interr pt TUTICLIOTIS mm a 2 15 2 22 Related TOUS Sinn in n 2 18 2 2 3 Interrupt application examples anaa raaz aT S 2 21 2 24 NOLES ON US T ras 2 30 CERI A 2 31 23 11 TIMOR TURCIOMS il toc ee d s exo e diet ead dE Rod uu ot RE 2 31 2 0 2 Related registers aue eee alas 2 32 2 3 3 Timer application examples eeesseeseseseeeeeeseeene eene ennt giton 2 37 2 9 4 NOIOS On USO aene erit rr nene bra ee ex ds Era du anan du due eee eed 2 50 24 AD CONVE 2 52 2 41 Related registers viciosa ita 2 53 2 4 2 A D converter application examples egat araa RET a EYE ayna yS ranma 2 54 2 4 9 Notes On 186 aeter rec oe iidem aes id donat iadiedee shedouscte NT 2 56 225 Serial M 2 58 29 Serial 1 0 TUMCHOMS uere eee der
63. CNTRO pin input count edge selection bit Rising edge CNTR1 output auto control circuit CNTR1 output auto control circuit not selected selection bit CNTR1 output auto control circuit selected De I O CNTRO input ojjoj oj 2 o De CNTRO pin function selection bit Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7RENESAS CNTRO I O De input 1 36 4519 Group 1 Timer control registers Rev 1 00 Aug 06 2004 Timer control register PA Register PA controls the count operation of prescaler Set the contents of this register through register A with the TPAA instruc tion Timer control register W1 Register W1 controls the selection of timer 1 count auto stop cir cuit and the count operation and count source of timer 1 Set the contents of this register through register A with the TW1A instruc tion The TAW1 instruction can be used to transfer the contents of register W1 to register A Timer control register W2 Register W2 controls the selection of CNTRO output and the count operation and count source of timer 2 Set the contents of this register through register A with the TW2A instruction The TAW2 instruction can be used to transfer the contents of register W2 to register A Timer control register W3 Register W3 controls the selection of the count operation and count source of timer 3 count auto stop circui
64. Do Number of Number of Flag CY Skip condition code 11ololol4 1 2 8 4 words cycles 2 16 1 1 a Operation T27 T24 B Grouping Timer operation R27 R24 B Description Transfers the contents of register B to the T23 T20 A high order 4 bits of timer 2 and timer 2 re R23 R20 A load register R2 Transfers the contents of register A to the low order 4 bits of timer 2 and timer 2 reload register R2 Rev 1 00 Aug 06 2004 RENESAS 1 108 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued T3AB Transfer data to timer 3 and register R3 from Accumulator and register B Instruction Dg Do Number of Number of Flag CY Skip condition code 110101011100 1 0 2 words cycles 2 16 1 1 9 S Operation T37 T34 B Grouping Timer operation R37 R34 B Description Transfers the contents of register B to the T33 T30 lt A R33 R30 lt A A A A high order 4 bits of timer 3 and timer 3 re load register R3 Transfers the contents of register A to the low order 4 bits of timer 3 and timer 3 reload register R3 TAAB Transfer data to timer 4 and register R4L from Accumulator and register B Instruction Dg Do Number of Number of Flag CY Skip condition words cycles code 1 o0 0
65. INT1 pin return condition selection bit Return by edge Key on wakeup not used INT1 pin key on wakeup contro bit Key on wakeup used Return by level INTO pin return condition selection bit Return by edge Key on wakeup not used oj oi ioj 2 o INTO pin key on wakeup contro bit Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 1320 NE SAS Key on wakeup used 1 82 4519 Group Pull up control register PUO at reset 00002 HARDWARE CONTROL REGISTERS at RAM back up state retained R W TAPUO TPUOA P03 pin pull up transistor control bit Pull up transistor OFF Pull up transistor ON P02 pin pull up transistor control bit Pull up transistor OFF Pull up transistor ON P01 pin pull up transistor control bit Pull up transistor OFF Pull up transistor ON POo pin pull up transistor control bit Pull up control register PU1 Pull up transistor OFF oj oi o 2 o Pull up transistor ON at reset 00002 at RAM back up state retained R W TAPU1 TPU1A P13 pin pull up transistor control bit Pull up transistor OFF Pull up transistor ON P12 pin pull up transistor control bit Pull up transistor OFF Pull up transistor ON P11 pin pull up transistor control bit Pull up transistor OFF Pull up transistor ON
66. In the A D conversion mode Q13 0 trans A AD5 AD2 fers the high order 4 bits AD9 AD6 of In comparator mode Q13 1 register AD to register B and the middle or B AD7 ADa der 4 bits AD5 AD2 of register AD to A AD3 ADo register A In the comparator mode Q13 1 Q13 bit 3 of A D control register Q1 TABE Transfer data to Accumulator and register B from register E transfers the middle order 4 bits AD7 AD4 of register AD to register B and the low order 4 bits AD3 ADo of register AD to register A Instruction Dg Do Number of Number of Flag CY Skip condition code o ojo o 1 o 1 o 1 0 o 2 A MISION cyclos 2 16 1 1 H E Operation B E7 E4 Grouping Register to register transfer A E3 Eo Description Transfers the high order 4 bits E7 E4 of register E to register B and low order 4 bits of register E to register A TABP p Transfer data to Accumulator and register B from Program memory in page p Instruction Dg Do Number of Number of Flag CY Skip condition code 0 0 1 0 pal pal pal pel pl pol 0 3 p moras cycles 2 p 16 1 3 Operation SP SP 1 Grouping X Arithmetic operation SK SP PC Description Transfers bits 9 and 8 to register D bits 7 to 4 PCH p to register B and bits 3 to 0 to register
67. Main clock f XIN Main clock f RING at reset 02 at RAM back up 02 On chip oscillator f RING control bit Timer control register PA On chip oscillator f RING oscillation enabled On chip oscillator f RING oscillation stop at reset 02 at RAM back up 02 Prescaler control bit Timer control register W1 Stop state initialized at reset 00002 Operating R W at RAM back up state retained TAW1 TW1A Timer 1 count auto stop circuit selection bit Note 2 Timer 1 count auto stop circuit not selected Timer 1 count auto stop circuit selected Timer 1 control bit Stop state retained Operating Timer 1 count source selection bits Timer control register W2 Count source Instruction clock INSTCK Prescaler output ORCLK XIN input at reset 00002 CNTRO input R W at RAM back up state retained TAW2 TW2A CNTRO output signal selection bit Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Timer 2 control bit Stop state retained Operating Timer 2 count source selection bits Notes 1 R represents read enabled and W represents write enabled Count source System clock STCK Prescaler output ORCLK Timer 1 underflow signal T1UDF PWM signal PWMOUT 2 This function is valid only when the timer 1 co
68. Note Do D5 VDD lt B V VDD lt 2 Y loL avg L level average output current Note De D7 VDD lt B V CNTRO CNTR1 VDD lt 2 V YloH avg H level total average current P5 Do D7 CNTRO CNTR1 PO P1 YloL avg L level total average current P2 P5 Do D7 RESET CNTRO CNTR1 PO P1 P3 P4 P6 Note The average output current is the average value during 100 ms Rev 1 00 Aug 06 2004 REJ09B0175 0100Z zENESAS 3 3 4519 Group Table 3 1 3 Recommended operating conditions 2 Mask ROM version Ta 20 C to 85 C VDD 1 8 to 5 5 V unless otherwise noted One Time PROM version Ta 20 C to 85 C VDD 2 5 to 5 5 V unless otherwise noted Parameter Conditions APPENDIX 3 1 Electrical characteristics Limits Typ Oscillation frequency with a ceramic resonator Mask ROM version Through mode VDD 4 0 to 5 5 V VDD 2 7 to 5 5 V VDD 2 0 to 5 5 V VDD 1 8 to 5 5 V Frequency 2 mode VDD 2 7 to 5 5 V VDD 2 0 to 5 5 V VDD 1 8 to 5 5 V Frequency 4 8 mode VDD 2 0 to 5 5 V VDD 1 8 to 5 5 V One Time PROM Through mode version VDD 4 0 to 5 5 V VDD 2 7 to 5 5 V VDD 2 5 to 5 5 V Frequency 2 mode VDD 2 7 to 5 5 V VDD 2 5 to 5 5 V Frequency 4 8 mode VDD 2 5 to 5 5 V Oscillation frequency at
69. Operation PO A Grouping X Input Output operation Description Outputs the contents of register A to port PO OP1A Output port P1 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition code 1 ojo o 1 0 0 o o t Se 2 16 1 1 Operation P1 A Grouping Input Output operation Description Outputs the contents of register A to port P1 OP2A Output port P2 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition code words cycles 11010 0 j gt 16 1 1 Operation P2 A Grouping Input Output operation Description Outputs the contents of register A to port P2 Rev 1 00 Aug 06 2004 RENESAS 1 99 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued OP3A Output port P3 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1lololol1lololo 4 3 words cycles 16 1 1 Operation P3 A Grouping Input Output operation Description Outputs the contents of register A to port P3 OP4A Output port P4 from Accumulator Instruction Dg Do Number of N
70. Port function P20 P21 P22 selected SCk SOUT SIN not selected Serial I O port function selection bits Sck SOUT P22 selected P20 P21 SIN not selected Sck P21 SIN selected P20 SouT P22 not selected 0 1 0 1 J10 0 1 0 1 Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS Sck SOUT SIN selected P20 P21 P22 not selected 1 53 4519 Group At transmit D7 Do transfer data Serial I O register SI 7 De D5 D4 D3 D D1 Do D3 D2 D1 Do ps p bs bs y Fig 41 Serial I O register state when transferring 1 Serial 1 O register SI Serial 1 O register SI is the 8 bit data transfer serial parallel conver sion register Data can be set to register SI through registers A and B with the TSIAB instruction The contents of register A is transmit ted to the low order 4 bits of register SI and the contents of register B is transmitted to the high order 4 bits of register SI During transmission each bit data is transmitted LSB first from the lowermost bit bit 01 of register SI and during reception each bit data is received LSB first to register SI starting from the topmost bit bit 7 When register Sl is used as a work register without using serial UO do not select the Sck pin 2 Serial 1 O transmit receive completion flag SIOF Serial 1 O transmit receive comple
71. R W Synchronous clock J13 ME c 0 O Instruction clock INSTCK divided by 8 is PE ronous elec 0 11 Instruction clock INSTCK divided by 4 Jo E SES oe 1 0 Instruction clock INSTCK divided by 2 1 1 External clock Sck input J11 J10 Port function 0 O P20 P21 P22 selected Sck SOUT SIN not selected 0 1 ScK Sour P22 selected P20 P21 SIN not selected 1 0 Sck P21 SIN selected P20 Sour P22 not selected Sck SOUT SIN selected P20 P21 P22 not selected 411 Serial 1 O port function selection bits Notes 1 R represents read enabled and W represents write enabled 2 When setting the port J13 J12 are not used 4 A D control register Q2 Table 2 1 4 shows the A D control register Q2 Set the contents of this register through register A with the TQ2A instruction The contents of register Q2 is transferred to register A with the TAQ2 instruction Table 2 1 4 A D control register Q2 A D control register Q2 at reset 00002 at RAM back up state retained R W oes P40 AIN4 P41 AIN5 P42 AIN6 P43 O P4o P41 P42 P43 AIN7 pin function selection bit 1 AIN4 AIN5 AIN6 AIN7 Q22 P62 AIN2 P63 AIN3 pin function 0 P62 P63 selection bit 1 AIN2 AIN3 0 P61 Q21 P61 AIN1 pin function selection bit 1 AIN1 0 P60 Q20 P60 AlNO pin function selection bit 1 AINO Notes 1 R represents read enabl
72. Sensor 1 Apply the voltage withiin the specifications to an analog input pin Fig 3 3 5 Analog input external circuit example 2 Fig 3 3 4 Analog input external circuit example 1 3 Notes for the use of A D conversion 2 Do not change the operating mode of the A D converter by bit 3 of register Q1 during A D conversion A D conversion mode and comparator mode 4 Notes for the use of A D conversion 3 When the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode with bit 3 of register Q1 in a program be careful about the following notes Clear bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to the A D conversion mode refer to Figure 3 3 60 The A D conversion completion flag ADF may be set when the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode Accordingly set a value to bit 3 of register Q1 and execute the SNZAD instruction to clear the ADF flag to 0 Clear bit 2 of register V2 to 0 y Change of the operating mode of the A D converter from the comparator mode to the A D conversion mode Clear the ADF flag to 0 with the SNZAD instruction y Execute the NOP instruction for the case when a skip is performed with the SNZAD instruction Fig 3 3 6 A D converter operating mode program example Rev 1 00 Aug 06 2004 RENESAS 3 17 REJO9B0175 0100Z
73. T34 g A s T33 T30 T3AB 1 0 00 1 1 0 0 1 0 23 2 1 1 R37 R34 B T37 T34 B R33 R30 A T33 T30 A TAB4 1 00 1 1 1 00 1 1 27311 1 B e T47 T44 A T43 T40 T4AB 1 000 1 1 0 0 1 1 233 1 1 R4L7 R4L4 B T47 T44 B R4L3 R4Lo A T43 T40 A T4HAB 100 O 1 1 O 1 1 1 237 1 1 R4H7 R4H4 lt B R4H3 R4Ho A TR1AB 1 0 00 1 1 1 1 1 1 23 E 1 1 R17 R14 B R13 R10 A TRSAB 1 0 00 1 14 1 0 1 1 23 B 1 1 R37 R34 B R33 R30 A T4R4L 1 0 1 0 O 1 O 1 1 1 297 1 1 T47 T40 R4L7 R4Lo Rev 1 00 Aug 06 2004 RENESAS 1 138 REJO9B0175 0100Z HARDWARE 4519 Group MACHINE INSTRUCTIONS INDEX BY TYPES Skip condition Datailed description Transfers the contents of timer control register W5 to register A Transfers the contents of register A to timer control register W5 Transfers the contents of timer control register W6 to register A Transfers the contents of register A to timer control register W6 Transfers the high order 4 bits of prescaler to register B and transfers the low order 4 bits of prescaler to register A Transfers the contents of register B to the high order 4 bits of prescaler and prescaler reload register RPS and transfers the contents of register A to the low order 4 bits of prescaler and prescaler reload register RPS Transfers the high order 4 bits of timer 1 to register B and transfers the low order 4 bits of
74. The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set to 0 5 Timer 3 interrupt The interrupt request occurs by the timer 3 underflow B Timer 3 interrupt processing O When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the interrupt enable flag INTE are set to 1 When the timer 3 interrupt occurs the interrupt processing is executed from address 8 in page 1 When the interrupt is not used The interrupt is disabled and the SNZT3 instruction is valid when the bit O of register V2 is set to 0 6 Timer 4 interrupt The interrupt request occurs by the timer 4 underflow B Timer 4 interrupt processing O When the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the interrupt enable flag INTE are set to 1 When the timer 4 interrupt occurs the interrupt processing is executed from address A in page 1 When the interrupt is not used The interrupt is disabled and the SNZTA instruction is valid when the bit 1 of register V2 is set to 0 Rev 1 00 Aug 06 2004 RENESAS 2 16 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 7 A D interrupt The interrupt request occurs by the completion of A D conversion B A D interrupt processing O When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt
75. ae Mutual ey af Large d XiN current Hu Pul Fig 3 4 9 Wiring to a signal line where potential levels change frequently 3 Oscillator protection using Vss pattern As for a two sided printed circuit board print a VSS pattern on the underside soldering side of the position on the component side where an oscillator is mounted Connect the Vss pattern to the microcomputer VSS pin with the shortest possible wiring Besides separate this Vss pattern from other VSS patterns An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the Vss line for oscillation from other Vss lines Fig 3 4 10 Vss pattern on the underside of an oscillator Rev 1 00 Aug 06 2004 REJO9B0175 0100Z APPENDIX 3 4 Notes on noise 3 4 5 Setup for I O ports Setup I O ports using hardware and software as follows lt Hardware gt Connect a resistor of 100 or more to an I O port in series lt Software gt As for an input port read data several times by a program for checking whether input levels are equal or not As for an output port or an I O port since the output data may reverse because of noise rewrite data to its output latch at fixed periods Rewrite data to pull up control registers at fixed periods 3 4 6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others it can be detected by a softwar
76. at the beggining of software and then set the main clock f XIN oscillation to be valid MR1 0 Until the main clock f XIN oscillation becomes valid MR1 0 after ceramic resonance becomes valid XIN pin is fixed to H When an external clock is used insert a 1 kQ resistor to XIN pin in series for limits of current Be sure to select the output structure of ports Do D5 and the pull up function of POo P03 and P10 P13 with every one port Set the corresponding bits of registers for each port Be sure to select the output structure of ports POo P03 and P10 P13 with every two ports If only one of the two pins is used leave another one open The key on wakeup function is selected with every two bits When only one of key on wakeup function is used con sidering that the value of key on wake up control register K1 set the unused 1 bit to H input turn pull up transistor ON and open or L input connect to Vss or open and set the output latch to 0 The key on wakeup function is selected with every two bits When one of key on wakeup function is used turn pull up transistor of unused one ON and open Note when connecting to Vss and VDD O Connect the unused pins to Vss and VDD using the thickest wire at the shortest distance against noise Rev 1 00 Aug 06 2004 RENESAS 3 13 REJO9B0175 0100Z APPENDIX 4519 Group 3 3 List of precautions 3 3 4 Notes on interrupt 1 2 3
77. by bits O and 1 of register W3 and set the bit 2 of register W3 to 1 When a value set in reload register R3 is n timer 3 divides the count source signal by n 1 n 0 to 255 Once count is started when timer 3 underflows the next count pulse is input after the contents of timer 3 becomes 0 the timer 3 interrupt request flag T3F is set to 1 new data is loaded from reload register R3 and count continues auto reload function INT1 pin input can be used as the start trigger for timer 3 count op eration by setting the bit O of register 12 to 1 Also in this time the auto stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to 1 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS HARDWARE FUNCTION BLOCK OPERATIONS 6 Timer 4 interrupt function Timer 4 is an 8 bit binary down counter with two timer 4 reload reg isters R4L R4H Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction Data can be set in the reload register R4H with the T4HAB instruction The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction Data can be read from timer 4 with the TAB4 instruction Stop counting and then execute the T4AB or TABA instruction to read or set timer 4 data When executing the T4HAB instruction to set data to reload regis ter R4H while timer 4 is operati
78. condition code 1 0 0 0 0 0 1 0 0 1 2 0 9 DIES G 2 16 1 1 E B Operation RGo Ao Grouping Clock control operation Description Transfers the contents of register A to regis TSIAB Transfer data to register SI from Accumulator and regis ter B ter RG Instruction Do Do Number of Number of Flag CY Skip condition code 1 0 10 0 1 1 1 0 0 0 2 3 8 Notes Eyes 2 16 4 1 a Operation SI7 Sl4 B Grouping Serial I O operation Sl3 Slo A Description Transfers the contents of register B to the high order 4 bits SI7 Sl4 of serial I O reg ister SI and transfers the contents of register A to the low order 4 bits SI3 Slo of serial I O register SI Rev 1 00 Aug 06 2004 RENESAS 1 125 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TV1A Transfer data to register V1 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code olololo s i s s s s o a sE ees 2 16 1 1 Operation V1 A Grouping Interrupt operation Descripti
79. contents of register A to M Z X Y 0 0 2 O Transfer the high order 8 bits of converted data to registers A and B TABAD instruction O Transfer the contents of register A to M Z X Y 0 0 1 Transfer the contents of register B to register A and then store into M Z X Y 0 O 0 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS Bit 0 1 A D control register Q2 Aino pin function selected Bit 0 A D control register Q1 Aino pin selected A D conversion mode Bit 3 x 0010 Bit 0 A D control register Q3 Frequency divided by 6 Instruction clock X Set an arbitrary value Fig 37 Setting registers 1 50 4519 Group 9 Operation at comparator mode The A D converter is set to comparator mode by setting bit 3 of the register Q1 to 1 Below the operation at comparator mode is described 10 Comparator register In comparator mode the built in D A comparator is connected to the 8 bit comparator register as a register for setting comparison voltages The contents of register B is stored in the high order 4 bits of the comparator register and the contents of register A is stored in the low order 4 bits of the comparator register with the TADAB instruction When changing from A D conversion mode to comparator mode the result of A D conversion register AD is undefined However because the comparator register i
80. control bit Pull up transistor ON P02 pin pull up transistor Pull up transistor OFF control bit Pull up transistor ON P01 pin pull up transistor Pull up transistor OFF control bit Pull up transistor ON POo pin pull up transistor Pull up transistor OFF oj oi o 2 o control bit Pull up control register PU1 Pull up transistor ON R W TAPU1 TPU1A reset 00002 at RAM back up state retained P13 pin pull up transistor Pull up transistor OFF control bit Pull up transistor ON P12 pin pull up transistor Pull up transistor OFF control bit Pull up transistor ON P11 pin pull up transistor Pull up transistor OFF control bit Pull up transistor ON P10 pin pull up transistor Pull up transistor OFF oj oi o 2 o control bit Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS Pull up transistor ON 1 67 4519 Group CLOCK CONTROL The clock control circuit consists of the following circuits On chip oscillator internal oscillator Ceramic resonator RC oscillation circuit Quartz crystal oscillation circuit Multi plexer clock selection circuit Frequency divider Internal clock generating circuit The system clock and the instruction clock are generated as the Source clock for operation by these circuits Figure
81. control register V2 and the interrupt enable flag INTE are set to 1 When the A D interrupt occurs the interrupt processing is executed from address C in page 1 O When the interrupt is not used The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set to 0 8 Serial 1 O interrupt The interrupt request occurs by the completion of serial I O transmit receive B Serial I O interrupt processing O When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the interrupt enable flag INTE are set to 1 When the serial I O interrupt occurs the interrupt processing is executed from address E in page 1 O When the interrupt is not used The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set to 0 Rev 1 00 Aug 06 2004 RENESAS 2 17 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 2 2 2 1 2 3 Related registers Interrupt enable flag INTE The interrupt enable flag INTE controls whether the every interrupt enable disable Interrupts are enabled when INTE flag is set to 1 with the El instruction and disabled when INTE flag is cleared to 0 with the DI instruction When any interrupt occurs while the INTE flag is 1 the INTE flag is automatically cleared to 0 so that other interrupts are disabled until the EI instruction is executed Note
82. ence instruction TABP p is executed Program counter consists of PCH most significant bit to bit 7 which specifies to a ROM page and PCL bits 6 to 0 which speci fies an address within a page After it reaches the last address address 127 of a page it specifies address 0 of the next page Figure 7 Make sure that the PCH does not specify after the last page of the built in ROM 9 Data pointer DP Data pointer DP is used to specify a RAM address and consists of registers Z X and Y Register Z specifies a RAM file group reg ister X specifies a file and register Y specifies a RAM digit Figure 8 Register Y is also used to specify the port D bit position When using port D set the port D bit position to register Y certainly and execute the SD RD or SZD instruction Figure 9 Note Register Z of data pointer is undefined after system is released from reset Also registers Z X and Y are undefined in the RAM back up After System is returned from the RAM back up set these registers Rev 1 00 Aug 06 2004 REJ09B0175 0100Z 2RENESAS HARDWARE FUNCTION BLOCK OPERATIONS Program counter f MM po rp rej e e fol o NS J J Y Y PCH PCL Specifying page Specifying address Fig 7 Program counter PC structure Data pointer DP JERALA IAAI M A A y X Register Y 4 Specifying RAM digit Register X 4 Specifying RAM file Register Z 2 Sp
83. have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics C 7 D Im on lt D D ENESAS 4519 Group User s Manual RENESAS 4 BIT CISC SINGLE CHIP MICROCOMPUTER 720 FAMILY 4500 SERIES All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics www renesas com Rev 1 00 2004 08 Keep safety first in your circuit designs Renesas Technology Corp puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with ap propriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunct
84. i i 1 I CNTR1 output 1 CNTR1 output start CNTR1 output auto control function PWM T CNTR1 output start CNTR output stop When the CNTR1 output auto control function is set to be invalid while the CNTR1 output is invalid the CNTR1 output invalid state is retained When the CNTR1 output auto control function is set to be invalid while the CNTR1 output is valid the CNTR1 output valid state is retained When timer 3 is stopped the CNTR1 output auto control function becomes invalid Fig 30 CNTR1 output auto control function by timer 3 Rev 1 00 Aug 06 2004 RENESAS 1 43 REJO9B0175 0100Z HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group e Waveform extension function of CNTR1 output H interval Invalid W42 0 CNTR1 output valid W43 1 Count source XIN input selected W40 0 Reload register R4L 0316 Reload register R4H 0216 Timer 4 count start timing Machine cycle i TWAA instruction execution T W41 1 System clock f STCK K XIN 4 l XIN input i count source selecte I LULU UU UU L L LL LU L LL LL LLL Register W41 o Timer 4 count value Reload register Timer 4 underflow signal T PWM a Timer 4 count start timing Timer 4 count stop timing Machine cycle Mi TWAA instruction execution cycle W41 lt 0 System clock f STCK f Xin 4 a e LLL LL en count source selected Register W41 Timer 4 count value CED 1D G ED
85. instruction for the case when a skip is per formed with the SNZ1 instruction refer to Figure 65G XX0X2 The SNZ1 instruction is valid 1XXxX2 Control of INT1 pin input is changed The SNZ1 instruction is executed EXF1 flag cleared X these bits are not used here Fig 65 External 1 interrupt program example 1 8 Note 2 on bit 3 of register 12 When the bit 3 of register I2 is cleared to 0 the RAM back up mode is selected and the input of INT1 pin is disabled be careful about the following notes When the input of INT1 pin is disabled register 123 0 set the key on wakeup function to be invalid register K22 0 before system enters to the RAM back up mode refer to Figure 660 X0XX2 Input of INT1 key on wakeup invalid RAM back up X these bits are not used here Fig 66 External 1 interrupt program example 2 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS HARDWARE LIST OF PRECAUTIONS Note on bit 2 of register I2 When the interrupt valid waveform of the P31 INT1 pin is changed with the bit 2 of register 12 in software be careful about the following notes Depending on the input state of the P31 INT1 pin the external 1 interrupt request flag EXF1 may be set when the bit 2 of regis ter I2 is changed In order to avoid the occurrence of an unexpected interrupt clear the bit 1 of register V1 to 0 refer to Figure 670 and then change
86. on chip oscillator internal oscillator r gt clock is counted 120 to 144 times Note Detection voltage hysteresis of voltage drop detection circuit is 0 2 V Typ Fig 50 Voltage drop detection circuit operation waveform Table 18 Voltage drop detection circuit operation state VDCE pin At CPU operating At RAM back up L Invalid Invalid H Valid Valid Rev 1 00 Aug 06 2004 RENESAS 1 62 REJO9B0175 0100Z 4519 Group RAM BACK UP MODE The 4519 Group has the RAM back up mode When the EPOF and POF instructions are executed continuously system enters the RAM back up state The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex ecuted before the POF instruction As oscillation stops retaining RAM the function of reset circuit and states at RAM back up mode current dissipation can be reduced without losing the contents of RAM Table 18 shows the function and states retained at RAM back up Figure 51 shows the state transition 1 Identification of the start condition Warm start return from the RAM back up state or cold start re turn from the normal reset state can be identified by examining the state of the RAM back up flag P with the SNZP instruction 2 Warm start condition When the external wakeup signal is input after the system enters the RAM back up state by executing the EPOF and POF instruc tions continuously the CPU starts executing the program from
87. or re load regiser R4H while timer 1 timer 3 or timer 4 is operating avoid a timing when timer 1 timer 3 or timer 4 underflows Timer 4 At CNTR1 output vaild if a timing of timer 4 underflow overlaps with a timing to stop timer 4 a hazard may be generated in a CNTR1 output waveform Please review sufficiently When H interval extension function of the PWM signal is set to be valid set 1 or more to reload register R4H Period measurement function When a period measurement circuit is used clear bit 0 of regis ter 11 to 0 and set a timer 1 count start synchronous circuit to be not selected Start timer operation immediately after operation of a period measurement circuit is started When the target edge for measurement is input until timer opera tion is started from the operation of period measurement circuit is started the count operation is not executed until the timer opera tion becomes valid Accordingly be careful of count data When data is read from timer stop the timer and clear bit 2 of register W5 to 0 to stop the period measurement circuit and then execute the data read instruction Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2ENESAS HARDWARE FUNCTION BLOCK OPERATIONS Depending on the state of timer 1 the timer 1 interrupt request flag T1F may be set to 1 when the period measurement cir cuit is stopped by clearing bit 2 of register W5 to 0 In order to avoid the occur
88. output data changes from 0 to 1 Q Full scale transition voltage VFST This means an analog input voltage when the actual A D con version output data changes from 1023 to 1022 Linearity error This means a deviation from the line between VoT and VEST of a converted value between Vor and VFST Differential non linearity error This means a deviation from the input potential difference re quired to change a converter value between VoT and VFST by 1 LSB at the relative accuracy Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A D conversion characteristics Output data HARDWARE FUNCTION BLOCK OPERATIONS Vn Analog input voltage when the output data changes from n to n 1 n 0 to 1022 VFST VoT 1LSB at relative accuracy gt V 1022 VDD e 1LSB at absolute accuracy gt V 1024 Full scale transition voltage VFST 1023 b a a 1022 BEEN Differential non linearity error LSB Linearity error a LSB Actual A D conversion characteristics a 1LSB by relative accuracy b Vn 1 Vn c Difference between ideal Vn and actual Vn Y Z Ideal line of A D conversion between Vo V1022 Zero transition voltage VoT Fig 39 Definition of A D conversion accuracy Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS V1022 Analog voltage 1 52 4519 Group SERIAL I O The
89. output structure is an N channel open drain REJO9B0175 0100Z APPLICATION 4519 Group 2 1 1 0 pins 8 Port D Ports Do D7 are eight independent I O ports Port De is also used as CNTRO I O pin Port D7 is also used as CNTR1 I O pin B input output of port D Each pin of port D has an independent 1 bit wide I O function For I O of ports Do D7 select one of port D with the register Y of the data pointer first O Input The pin state of port D can be obtained with the SZD instruction In the following conditions if the pin state of port Dj j 0 1 2 3 4 5 6 or 7 is 0 when the SZD instruction is executed the next instruction is skipped If it is 1 when the SZD instruction is executed the next instruction is executed Set bit i i 0 1 2 or 3 of register FR1 or FR2 to 0 according to the port to be used Set the output latch of specified port Dj to 1 with the SD instruction If FR1i or FR2i is 0 and the output latch is 0 0 is output to specified port D If FR1i or FR2i is 1 the output latch value is output to specified port D O Output Set the output level to the output latch with the SD CLD and RD instructions The state of pin enters the high impedance state when the SD instruction is executed All port D enter the high impedance state or H level state when the CLD instruction is executed The state of pin becomes L level when the RD instruction is executed N channe
90. read from the built in PROM In the PROM mode the programming adapter can be used with a general purpose PROM programmer to write to or read from the built in PROM as if it were M5M27C256K Programming adapter is listed in Table 24 Contact addresses at the end of this data sheet for the appropriate PROM programmer Writing and reading of built in PROM Programming voltage is 12 5 V Write the program in the PROM of the built in PROM version as shown in Figure 73 2 Notes on handling OA high voltage is used for writing Take care that overvoltage is not applied Take care especially at turning on the power GFor the One Time PROM version shipped in blank Renesas Technology Corp does not perform PROM writing test and screening in the assembly process and following processes In order to improve reliability after writing performing writing and test according to the flow shown in Figure 74 before using is rec ommended Products shipped in blank PROM contents is not written in factory when shipped 3 Electric Characteristic Differences Between Mask ROM and One Tlme PROM Version MCU There are differences in electric characteristics operation margin noise immunity and noise radiation between Mask ROM and One Time PROM version MCUS due to the difference in the manufactur ing processes When manufacturing an application system with the One Time PROM version and then switching to use of the Mask ROM ver sion please perfor
91. renesas com en 720 Rev 1 00 Aug 06 2004 RENESAS 3 11 REJO9B0175 0100Z APPENDIX 4519 Group 3 3 List of precautions 3 3 List of precautions 3 3 1 Program counter Make sure that the PCx does not specify after the last page of the built in ROM 3 3 2 Stack registers SKs Stack registers SKs are eight identical registers so that subroutines can be nested up to 8 levels However one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction Accordingly be careful not to over the stack when performing these operations together 3 3 3 Notes on I O port 1 Note when an I O port is used as an input port Set the output latch to 1 and input the port value before input If the output latch is set to 0 L level can be input As for the port which has the output structure selection function select the N channel open drain output structure 2 Noise and latch up prevention Connect an approximate 0 1 uF bypass capacitor directly to the Vss line and the Von line with the thickest possible wire at the shortest distance and equalize its wiring in width and length The CNVss pin is also used as the Vere pin programming voltage 12 5 V at the One Time PROM version Connect the CNVss Vrer pin to Vss through an approximate 5 kQ resistor which is connected to the CNVss Vre pin at the shortest distance 3 Multifunction e Be careful that the output of p
92. setting example of an external 1 interrupt 3 Timer 1 interrupt Constant period interrupts by a setting value to timer 1 can be used Outline The constant period interrupts by the timer 1 underflow signal can be used Specifications Timer 1 divides the system clock frequency 2 0 MHz and the timer 1 interrupt occurs every 0 25 ms Figure 2 2 5 shows a setting example of the timer 1 constant period interrupt 4 Timer 2 interrupt Constant period interrupts by a setting value to timer 2 can be used Outline The constant period interrupts by the timer 2 underflow signal can be used Specifications Timer 2 and prescaler divide the system clock frequency 4 0 MHz and the timer 2 interrupt occurs every 1 ms Figure 2 2 6 shows a setting example of the timer 2 constant period interrupt Rev 1 00 Aug 06 2004 RENESAS 2 21 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 5 Timer 3 interrupt Constant period interrupts by a setting value to timer 3 can be used Outline The constant period interrupts by the timer 3 underflow signal can be used Specifications Prescaler and timer 3 divide the system clock frequency 6 0 MHz and the timer 3 interrupt occurs every 1 ms Figure 2 2 7 shows a setting example of the timer 3 constant period interrupt 6 Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used Outline The constant period interrupts by the timer 4 underflow signal can be used S
93. the RC instruction Measurement data is read TAB1 Count source Timer value Timer underflow signal I 9 l o l Timer start Fig 3 3 2 Count start time and count time when operation starts PS T1 T2 and T3 e I I I I countsource ALLI I I Timer value a 2 t o sja t1 o Ss l l l Timer underflow signal l J o l O Timer start Fig 3 3 3 Count start time and count time when operation starts T4 3 16 APPENDIX 4519 Group 3 3 List of precautions 3 3 6 Notes on A D conversion 1 Note when the A D conversion starts again When the A D conversion starts again with the ADST instruction during A D conversion the previous input data is invalidated and the A D conversion starts again 2 A D converter 1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage Accordingly when the analog voltage is input from the circuit with high impedance and charge discharge noise is generated and the sufficient A D accuracy may not be obtained Therefore reduce the impedance or connect a capacitor 0 01 uF to 1 uF to analog input pins Figure 3 3 4 shows the analog input external circuit example 1 When the overvoltage applied to the A D conversion circuit may occur connect an external circuit in order to keep the voltage within the rated range as shown the Figure 3 3 5 In addition test the application products sufficiently Sensor About 1kQ
94. the count source of a timer 1 and the bit 2 of register W1 is set to 1 timer 1 starts operation Timer 1 starts operation synchronizing with the falling edge of the target signal for period measurement and stops count operation synchronizing with the next falling edge one period generation circuit When selecting De CNTRO pin input as target signal for period measurement the period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register W6 to 1 When selecting P30 INTO pin input as target signal for period measurement period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register 11 to 1 A timer 1 interrupt request flag T1F is set to 1 after completing measurement operation When a period measurement circuit is set to be operating timer 1 interrupt request flag T1F is not set by timer 1 underflow sig nal but turns into a flag which detects the completion of period measurement In addition a timer 1 underflow signal can be used as timer 2 count source Once period measurement operation is completed even if period measurement valid edge is input next timer 1 is in a stop state and measurement data is held When a period measurement circuit is used again stop a period measurement circuit at once by setting the bit 2 of register W5 to 0 and change a period measurement circuit into a state of op eration by setting the bit 2 o
95. the first LA instruction is executed and other LA instructions coded continuously are skipped Transfers bits 9 and 8 to register D bits 7 to 4 to register B and bits 3 to O to register A These bits 7 to O are the ROM pattern in ad dress DR2 DR1 DRo A3 A2 A1 Ao 2 specified by registers A and D in page p When this instruction is executed be careful not to over the stack because 1 stage of stack register is used Adds the contents of M DP to register A Stores the result in register A The contents of carry flag CY re mains unchanged Adds the contents of M DP and carry flag CY to register A Stores the result in register A and carry flag CY Adds the value n in the immediate field to register A and stores a result in register A The contents of carry flag CY remains unchanged Skips the next instruction when there is no overflow as the result of operation Executes the next instruction when there is overflow as the result of operation Takes the AND operation between the contents of register A and the contents of M DP and stores the re sult in register A Takes the OR operation between the contents of register A and the contents of M DP and stores the result in register A Sets 1 to carry flag CY Clears 0 to carry flag CY Skips the next instruction when the contents of carry flag CY is 0 Stores the one s complement for register A s contents in register A Rotates 1 bit of the contents of register A including the co
96. the number of cycle because the count source of watchdog timer is the instruction clock Fig 32 Watchdog timer function Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS 1 45 4519 Group When the watchdog timer is used clear the WDF1 flag at the pe riod of 65534 machine cycles or less with the WRST instruction When the watchdog timer is not used execute the DWDT instruc tion and the WRST instruction continuously refer to Figure 33 The watchdog timer is not stopped with only the DWDT instruction The contents of WDF1 flag and timer WDT are initialized at the RAM back up mode When using the watchdog timer and the RAM back up mode ini tialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back up state refer to Figure 34 The watchdog timer function is valid after system is returned from the RAM back up When not using the watchdog timer function ex ecute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back up and stop the watchdog timer function Rev 1 00 Aug 06 2004 REJO9B0175 0100Z RENESAS HARDWARE FUNCTION BLOCK OPERATIONS WDF1 flag cleared Watchdog timer function enabled disabled WEF and WDF1 flags cleared WDF1 flag cleared Interrupt disabled POF instruction enabled EPOF POF y Oscillation stop Fig 34 Program example to enter the mode when using the watchdog timer 1 46 HARDW
97. the switch of system clock cannot be executed at the same time when main clock oscillation is started 3 In order to use the external clock input for the main clock select the ceramic resonance by executing the CMCK instruction at the beggining of soft ware and then set the main clock f XIN oscillation to be valid MR1 0 Until the main clock f XIN oscillation becomes valid MR1 0 after ceramic resonance becomes valid XIN pin is fixed to H When an external clock is used insert a 1 kQ resistor to XIN pin in series for limits of current 4 Be sure to select the output structure of ports Do Ds and the pull up function of POo P03 and P10 P13 with every one port Set the corresponding bits of registers for each port 5 Be sure to select the output structure of ports POo P03 and P10 P13 with every two ports If only one of the two pins is used leave another one open 6 The key on wakeup function is selected with every two bits When only one of key on wakeup function is used considering that the value of key on wake up control register K1 set the unused 1 bit to H input turn pull up transistor ON and open or L input connect to VSS or open and set the output latch to 0 7 The key on wakeup function is selected with every two bits When one of key on wakeup function is used turn pull up transistor of unused one ON and open Note when connecting to Vss and VDD Connect the unused pins to Vss a
98. timer 3 count value to make the interrupt occur every 30 ms are set as follows 30 ms 6 0 MHz X 3 X 249 1 X 239 1 System clock Instruction Prescaler Timer 3 count value clock count value X it can be 0 or 1 lI instruction Fig 2 2 7 Timer 3 constant period interrupt setting example Rev 1 00 Aug 06 2004 RENESAS 2 28 REJ09B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts O Disable Interrupts Timer 4 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI b0 Interrupt control register V2 X b1 Timer 4 interrupt occurrence disabled TV2A Q Stop Timer and Prescaler Operation TW4A Timer 4 and prescaler are temporarily stopped CNTR1 input Timer 4 count source is selected PWM signal H interval expansion function invalid b3 Timer 4 stop Timer control register W4 o o o Prescaler output ORCLK divided by 2 selected for Timer 4 count source Timer control register PA Prescaler stop TPAA Set Timer Value and Prescaler Value Timer 4 and prescaler count times are set The formula is shown A below Timer 4 reload register R4L DD16 Timer count value 221 set T4AB Prescaler reload register RPS 9516 Prescaler count value 149 set TPSAB Clear Interrupt Request Timer 4 interrupt activated condition is cleared Timer 4 interrupt request flag T4F 0 Timer 4 interrupt activated condition clear
99. to 1 When a value set in reload register R1 is n timer 1 divides the count source signal by n 1 n 0 to 255 Once count is started when timer 1 underflows the next count pulse is input after the contents of timer 1 becomes 0 the timer 1 interrupt request flag T1F is set to 1 new data is loaded from reload register R1 and count continues auto reload function INTO pin input can be used as the start trigger for timer 1 count op eration by setting the bit O of register 11 to 1 Also in this time the auto stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to 1 Timer 1 underflow signal divided by 2 can be output from CNTRO pin by clearing bit 3 of register W2 to 0 and setting bit O of regis ter W6 to 1 The period measurement circuit starts operating by setting bit 2 of register W5 to 1 and timer 1 is used to count the one period of the target signal for the period measurement In this time the timer 1 interrupt request flag T1F is not set by the timer 1 underflow sig nal it is the flag for detecting the completion of period measurement 1 37 4519 Group 4 Timer 2 interrupt function Timer 2 is an 8 bit binary down counter with the timer 2 reload reg ister R2 Data can be set simultaneously in timer 2 and the reload register R2 with the T2AB instruction Data can be read from timer 2 with the TAB2 instruction Stop counting and
100. to CNTRO input port and is set to be high impedance state b3 bO Register Y 0 1111 Specify bit position of port D TYA Port De output latch 1 Set to input SD b3 Timer control register W6 X X X b0 Set to CNTRO input port TW6A A The prescaler count value and timer 2 count value to make the underflow occur every 125 us are set as follows 125 us 4 0 MHz X 3 X 341 X 41 1 System clock Instruction Presclaer Timer 2 count value clock count value X it can be 0 or 1 J instruction Fig 2 3 5 CNTRO output setting example Rev 1 00 Aug 06 2004 RENESAS 2 41 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers O Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE Interrupt control register V1 Q Stop Timer Operation Timer 1 is temporarily stopped Timer 1 count source is selected Timer control register W1 G Set Port CNTRO I O port is set to CNTRO input port Register Y Port De output latch Port output structure control register FR2 Timer control register W6 All interrupts disabled DI b2 Timer 1 interrupt occurrence disabled TV1A TW1A b2 Timer 1 stop b1 b0 CNTRO input for Timer 1 count source Specify bit position of port D TYA Set to input SD b2 N channel open drain output selected TFR2A b2 Set count edge to rising
101. unchanged Skips the next instruction when there is no overflow as the result of operation Executes the next instruction when there is overflow as the result of operation ADST A D conversion STart Instruction Dg Do Number of Number of Flag CY Skip condition code i0 4 O01 0 414 0 4 F wolds cycles 16 1 1 _ i Operation ADF 0 Grouping A D conversion operation Q13 0 A D conversion starting Description Clears 0 to A D conversion completion Q13 1 Comparator operation starting flag ADF and the A D conversion at the A D Q13 bit 3 of A D control register Q1 conversion mode Q13 0 or the compara tor operation at the comparator mode Q13 1 is started AM Add accumulator and Memory Instruction Dg Do Number of Number of Flag CY Skip condition code ololo ololo t1 o 1 o S a G 1 1 Operation A lt A M DP Grouping Arithmetic operation Description Adds the contents of M DP to register A Stores the result in register A The contents of carry flag CY remains unchanged AMC Add accumulator Memory and Carry Instruction Dg Do Number of Number of Flag CY Skip condition code ololololololi1iol1 4 B words cycles 16 1 1 0 1 Operation A lt A M DP CY Grouping Arithmetic operation CY Carry Description Adds the contents of M DP and carry flag CY to register A Stores the result in regis ter A and carry flag CY Rev 1 00 Aug 06 2004 RENESAS 1 91 REJO9B0175 0100Z 4519 Gro
102. using the A D converter and notes Figure 2 4 1 shows the A D converter block diagram Register B 4 Register A 4 TQ2A IAP4 Y P4o P43 adore Q11 lard loza ceifaza Q32 Q31 los IAP6 P6o P63 Q31 Q3 OP4A P4o P43 OP6A m P6o P63 Instruction clock T A D conversion clock A D interrupt P60 AINo o 4 P61 AIN1 Dedi P62 AIN2 o4 Successive comparison register AD 10 P63 AIN3 o 44 P40 AIN4 oA P41 AIN5 o 44 P42 AIN6 o 4 P43 AIN7 o 8 channel multi plexed analog switch D A converter cr Comparator register 8 Notes 1 This switch is turned ON only when A D converter is operating and generates the comparison voltage 2 Writing reading data to the comparator register is possible only in the comparator mode Q13 1 The value of the comparator register is retained even when the mode is switched to the A D conversion mode Q13 0 because it is separated from the successive comparison register AD Also the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits Fig 2 4 1 A D converter structure Rev 1 00 Aug 06 2004 RENESAS 2 52 REJ09B0175 0100Z APPLICATION 4519 Group 2 4 A D converter 2 4 1 Related registers 1 Interrupt control register V2 Table 2 4 1 shows the interrupt control register V2 Set the contents of this register through register A with the TV2A
103. 0 1 1 0 0 1 1 ul Operation T47 T44 B Grouping Timer operation R4L7 R4La B T43 T40 lt A R4L3 R4Lo lt A PA A a T4HAB Transfer data to register R4H from Accumulator and register B Description Transfers the contents of register B to the high order 4 bits of timer 4 and timer 4 re load register R4L Transfers the contents of register A to the low order 4 bits of timer 4 and timer 4 reload register R4L Instruction Dg Do Number of Number of Flag CY Skip condition code 1100 0 1f19fo 1 111 7 ue cycles 2 16 1 1 NS Operation RA4H7 R4H4 B Grouping Timer operation R4H3 R4Ho A Description Transfers the contents of register B to the high order 4 bits of timer 4 and timer 4 re load register R4H Transfers the contents of register A to the low order 4 bits of timer 4 and timer 4 reload register R4H T4RAL Transfer data to timer 4 from register R4L Instruction Dg Do Number of Number of Flag CY Skip condition code 1 lo 35 o o s o 3 3 4 le 7 Words cycles 2 16 1 1 Operation T47 T44 RAL7 R4L4 Grouping Timer operation T43 T40 R4L3 R4Lo Description Transfers the contents of reload register RAL to timer 4 Rev 1 00 Aug 06 2004 RENESAS 1 109 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INST
104. 0 Grouping Arithmetic operation Description Skips the next instruction when the con tents of carry flag CY is 0 After skipping the CY flag remains un changed Executes the next instruction when the con tents of the CY flag is 1 SZD Skip if Zero port D specified by register Y Instruction D9 Do Number of Number of Flag CY Skip condition code olololol1 0 olala4 words cycles n 2 2 D Y 0 Y 0to 7 0 0 0 0 1 1 0 2 B lig Operation D Y 0 Grouping Input Output operation Y 2010 7 Description Skips the next instruction when a bit of port D specified by register Y is 0 Executes the next instruction when the bit is 1 T1AB Transfer data to timer 1 and register R1 from Accumulator and register B Instruction Dg Do Number of Number of Flag CY Skip condition code 1lololol4 0 21310 words cycles 2 16 1 1 Operation T17 T14 B Grouping Timer operation R17 R14 B Description Transfers the contents of register B to the T13 T10 A R13 R10 lt A high order 4 bits of timer 1 and timer 1 re load register R1 Transfers the contents of register A to the low order 4 bits of timer 1 and timer 1 reload register R1 T2AB Transfer data to timer 2 and register R2 from Accumulator and register B Instruction Dg
105. 0 Aug 06 2004 RENESAS 2 79 REJ09B0175 0100Z APPLICATION 4519 Group 2 9 Oscillation circuit 2 9 2 Related register 1 Clock control register MR Table 2 9 1 shows the clock control register MR Set the contents of this register through register A with the TMRA instruction The contents of register MR is transferred to register A with the TAMR instruction at reset 11112 at RAM back up state retained Table 2 9 1 Clock control register MR Clock control register MR R W MR3MR2 Operation mode MR3 O O Through mode frequency not divided Operation mode selection bits O 1 Frequency divided by 2 mode MR2 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode Main clock f XIN oscillation circuit 0 Main clock oscillation enabled MR1 control bit 1 Main clock oscillation stop System clock oscillation source 0 Main clock f XIN MRO selection bit 1 Sub clock f XcIN Note R represents read enabled and W represents write enabled 2 Clock control register RG Table 2 9 2 shows the clock control register RG Set the contents of this register through register A with the TRGA instruction at RAM back up state retained 0 On chip oscillator f RING oscillation enabled On chip oscillator f RING oscillation stop Table 2 9 2 Clock control register RG Clock control register RG On chip oscillator f RING control b
106. 0 N channel open drain output output structure selection bit 1 CMOS output Note W represents write enabled 10 Port output structure control register FR3 Table 2 1 10 shows the port output structure control register FR3 Set the contents of this register through register A with the TFR3A instruction Table 2 1 10 Port output structure control register FR3 at reset 00002 at RAM back up state retained Port output structure control register FR3 Port P53 0 N channel open drain output FR33 l output structure selection bit 1 CMOS output FR32 Port P52 0 N channel open drain output output structure selection bit 1 CMOS output FR34 Port P51 0 N channel open drain output output structure selection bit 1 CMOS output FR30 Port P50 0 N channel open drain output output structure selection bit 1 CMOS output Note W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 10 REJO9B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 11 Key on wakeup control register KO Table 2 1 11 shows the key on wakeup control register KO Set the contents of this register through register A with the TKOA instruction The contents of register KO is transferred to register A with the TAKO instruction Table 2 1 11 Key on wakeup control register KO at reset 00002 Key on wakeup control register KO at RAM back up state retained R W Pins P12 P13 0 Ke
107. 0XX2 Period measurement circuit stop TV1A LA 0 TW5A NOP SNZT1 The SNZT1 instruction is executed T1F flag cleared NOP these bits are not used here Fig 27 Period measurement circuit program example When a period measurement circuit is used select the suffi ciently higher speed frequency than the signal for measurement for the count source of a timer 1 When the target signal for period measurement is De CNTRO pin input do not select De CNTRO pin input as timer 1 count source The XIN input is recommended as timer 1 count source at the time of period measurement circuit use 8 Pulse width measurement function timer 1 period measurement circuit A period measurement circuit can measure H pulse width from rising to falling or L pulse width from falling to rising of P30 INTO pin input pulse width measurement function when the fol lowing is set Set the bit O of register W5 to 0 and set a bit 1 to 1 target for period measurement circuit 30 INTO pin input Set the bit 1 of register 11 to 1 INTO pin edge detection circuit both edges detection The measurement pulse width H or L is decided by the pe riod measurement circuit and the P30 INTO pin input level at the start time of timer operation At the time of the start of a period measurement circuit and timer operation L pulse width from falling to rising when the input level of P30 INTO pin is H or
108. 1 External clock Scx input J11 J1to Port function 0 0 P2o P21 P2 selected Sck Sour Sin not selected 0 1 Sckx Sour P2 selected P2o P21 Sin not selected Sck P21 Sin selected P2o Sour P22 not selected Sck Sour Sin selected P2o P21 P22 not selected Note R represents read enabled and W represents write enabled Ji Serial 1 0 port function selection bits Jio Rev 1 00 Aug 06 2004 RENESAS 2 59 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO 2 5 3 Operation description Figure 2 5 2 shows the serial I O connection example Figure 2 5 3 shows the serial I O register state and Figure 2 5 4 shows the serial I O transfer timing Master internal clock selected Slave external clock selected 4519 4519 Control signal D3 Sck SIN Note The control signal is used to inform the master by the pin level that the slave is in a ready state to receive The 4524 Group does not have a control pin exclusively used for serial I O Accordingly if a control signal is required use the normal input output ports Fig 2 5 2 Serial I O connection example Master M7 Mo transmit data Slave S7 So transmit data SIN pin SOUT pin os Serial I O register SI SOUT pin SIN pin Serial I O register Sl ec gt O Sz Ss Ss Se Sa Sal S1 So Transmit data set Transfer start Ma Mal M3 Me M Falling of clock Ms Ma Mal M
109. 1 2 P00 P03 P00 P03 High impedance Notes 1 2 3 P10 P13 P10 P13 High impedance Notes 1 2 3 P20 Sck P21 SOUT P22 SIN P20 P22 P30 INTO P31 INT1 P32 P33 P30 P33 High impedance Note 1 P40 AIN4 P43 AIN7 P40 P43 High impedance Note 1 P50 P53 P50o P53 High impedance Notes 1 2 P60 AINO P63 AIN3 P60 P63 Notes 1 Output latch is set to 1 2 Output structure is N channel open drain 3 Pull up transistor is turned OFF High impedance Note 1 High impedance Note 1 Rev 1 00 Aug 06 2004 RENESAS 1 59 REJO9B0175 0100Z 4519 Group 2 Internal state at reset Figure 47 and 48 show internal state at reset they are the same af ter system is released from reset The contents of timers registers flags and RAM except shown in Figure are undefined so set the initial value to them FUNCTION BLOCK OPERATIONS HARDWARE Program counter PC Address 0 in page 0 is set to program counter Interrupt enable flag INTE Power down flag P External 0 interrupt request flag EXFO External 1 interrupt request flag EXF1 Interrupt control register V1 Interrupt control register V2 Interrupt control register 11 Interrupt control register I2 Timer 1 interrupt request flag T1F Timer 2 interrupt request flag T2F Timer 3 interrupt request flag T3F Timer 4
110. 1 0 0 0 1 1 263 1 1 A1 Ao P31 P30 OP3A 100010001 1 2238 14 1 P31 P30 At Ao IAP4 1 0 O 1 1 0 0 1 0 0 26 4 1 1 A P4 OP4A 1 0 0 01 0 0 1 0 0 224 1 1 P4 lt A IAP5 1 0 O 1 1 0 O 1 0 1 265 1 1 A P5 2 OP5A 1000 1 0 0 1 0 1 225 1 1 P5 lt A amp IAP6 1 0 0 1 1 0 0 141 0 266 1 1 A P6 amp OP6A 10001003 10 226 1 1 P6 A a O 5 CLD 0 0000 1 0 0 0 1 0 1 1 1 1 D e1 o RD 0 0 0 0 0 1 0 1 0 0 014 1 1 D Y 0 Y 20107 SD 0 0 0 0 0 1 0 1 0 1 015 1 1 D Y 1 Y 20107 SZD 0 0001 00 1 0 0 024 1 1 D Y 0 Y 20107 0 00 0 1 O 1 O 1 1 02 B 1 1 TAPUO 1 0 0 1 0 1 0 1 1 1 257 1 1 A PUO TPUOA 1 0 0O O 1 O 1 1 0 1 22D 1 1 PUO lt A TAPU1 1 0 0 1 O 1 1 0 25E 1 1 A PU1 TPU1A 1 0 0 O 1 O 1 4 1 0 22E 1 1 PU1 lt A Rev 1 00 Aug 06 2004 RENESAS 1 140 REJO9B0175 0100Z 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description VIS 0 T1F 1 V13 0 T2F 1 V20 0 T8F 1 V21 0 T4F 1 Skips the next instruction when the contents of bit 2 V12 of interrupt control register V1 is 0 and the con tents of T1F flag is 1 After skipping clears 0 to T1F flag Skips the next instruction when the contents of bit 3 V13 of interrupt control register V1 is 0 and the con tents of T2F flag is 1 After skipping clears 0 to T2F flag Skips the next ins
111. 110 0 1 0 1 0 0 0 0 2 5 0 Woras mines 2 16 1 1 Operation A W6 Grouping Timer operation Description Transfers the contents of timer control reg ister W6 to register A TAX Transfer data to Accumulator from register X Instruction Do Do Number of Number of Flag CY Skip condition code 0 o0 o0 1 0 1 0 0 1 0 0 5 2 Worgs cyclos 2 16 1 1 i E Operation A X Grouping Register to register transfer Description Transfers the contents of register X to reg ister A Rev 1 00 Aug 06 2004 RENESAS 1 118 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAY Transfer data to Accumulator from register Y Instruction Dg Do Number of Number of Flag CY Skip condition code ololo o o 1 1 1 1 o 1 r oS ee 2 16 1 1 Operation A Y Grouping Register to register transfer Description Transfers the contents of register Y to regis ter A TAZ Transfer data to Accumulator from register Z Instruction Dg Do Number of Number of Flag CY Skip condition code 0 o0 o 1 0 1 0 0 1 1 Jo ELM 7 1 1 E Operation A1 Ao Z1 Zo Grouping Register to register transfer A3 A2 0 Description Transfers the contents of register Z to the low order 2 bits A1 Ao of re
112. 12 Frequency divided by 24 Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS Frequency divided by 48 1 81 4519 Group Key on wakeup control register KO at reset 00002 HARDWARE CONTROL REGISTERS at RAM back up state retained Pins P12 and P13 key on wakeup Key on wakeup not used control bit Key on wakeup used Pins P10 and P11 key on wakeup Key on wakeup not used control bit Key on wakeup used Pins P02 and P03 key on wakeup Key on wakeup not used control bit Key on wakeup used Pins POo and P01 key on wakeup Key on wakeup not used k l s l a leS l k LES lek LE control bit Key on wakeup control register K1 at reset 00002 Key on wakeup used at RAM back up state retained Ports P02 and P03 return condition selection Return by level bit Return by edge Ports P02 and P083 valid waveform Falling waveform L level level selection bit Rising waveform H level Ports P01 and POo return condition selection Return by level bit Return by edge Ports P01 and POo valid waveform Falling waveform L level Ooj oi i o 3 o level selection bit Key on wakeup control register K2 Rising waveform H level reset 00002 at RAM back up state retained Return by level
113. 2 Notes 1 R represents read enabled and W represents write enabled 2 These instructions are equivalent to the NOP instruction Rev 1 00 Aug 06 2004 RENESAS 2 18 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 4 Interrupt control register V2 Table 2 2 2 shows the interrupt control register V2 Set the contents of this register through register A with the TV2A instruction In addition the TAV2 instruction can be used to transfer the contents of register V2 to register A Table 2 2 2 Interrupt control register V2 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZSI instruction is valid 1 Interrupt enabled SNZSI instruction is invalid Note 2 0 Interrupt disabled SNZAD instruction is valid 1 Interrupt enabled SNZAD instruction is invalid Note 2 0 Interrupt disabled SNZTA instruction is valid 1 0 Interrupt control register V2 Serial I O interrupt enable bit Note 2 V23 V22 A D interrupt enable bit V21 Timer 4 interrupt enable bit P Interrupt enabled SNZTA instruction is invalid Note 2 Interrupt disabled SNZT3 instruction is valid 1 Interrupt enabled SNZT3 instruction is invalid Note 2 Notes 1 R represents read enabled and W represents write enabled 2 These instructions are equivalent to the NOP instruction V20 Timer 3 interrupt enable bit 5 Interrupt control register I1 Table 2 2 3 shows the inter
114. 2 8 8 Key on wakeup control register KO sss ssse es sese ee nenen ennenen 2 76 Table 2 8 9 Key on wakeup control register K1 sese seene 2 77 Table 2 8 10 Key on wakeup control register K2 sese 2 77 Table 2 9 1 Clock control register MR ssssssssssssseeeeeen ementi 2 80 Table 2 9 2 Clock control register RG ssssssssssssssssse eene 2 80 CHAPTER 3 APPENDIX Table 3 1 1 Absolute maximum ratings eee eee ee eee ee eee 3 2 Table 3 1 2 Recommended operating conditions 1 ooo eee esse ee sees enen eenn 3 3 Table 3 1 3 Recommended operating conditions 2 3 4 Table 3 1 4 Recommended operating conditions 9 3 5 Table 3 1 5 Electrical characteristics 1 sse eem eee 3 6 Table 3 1 6 Electrical characteristics 2 ooonnionnncnnnniccnnnnnnnccccnnnn nn 3 7 Table 3 1 7 A D converter recommended operating condong sss sese eee eee 3 8 Table 3 1 8 A D converter characteristics ssssssssseeeee nennen 3 9 Table 3 1 9 Voltage drop detection circuit characteristics sseeeneee 3 10 Table 3 3 1 Connections of unused pins sese 3 13 Rev 1 00 Aug 06 2004 RENESAS ix REJO9B0175 0100Z CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS CONTROL REGISTERS INSTRUCTIONS BUILT IN PROM VERSION 4519 Group HARDWARE DESCR
115. 2 or FRO3 is 0 and the output latch is 0 0 is output to specified port P1 If FRO2 or FRO3 is 1 the output latch value is output to specified port P1 O Output The contents of register A is set to the output latch with the OP1A instruction and is output to port P1 N channel open drain or CMOS can be selected as the output structure of port P1 in 2 bits unit by setting FRO2 or FROs Rev 1 00 Aug 06 2004 RENESAS 2 2 REJO9B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 3 Port P2 Port P2 is a 3 bit I O port P20 P23 are also used as serial I O pins Sck SOUT SIN O Input In the following condition the pin state of port P2 is transferred as input data to register A when the IAP2 instruction is executed Set the output latch of specified port P2i i 0 1 or 2 to 1 with the OP2A instruction If the output latch is 0 0 is output to specified port P2 O Output The contents of register A is set to the output latch with the OP2A instruction and is output to port P2 The output structure is an N channel open drain Notes 1 Port P20 is also used as the serial I O pin Sck Accordingly when port P20 is used as an input output port set bits J11 and J10 of register J1 to 002 Also set bits J13 and J12 of register J1 to 002 012 or 102 2 Port P21 is also used as the serial I O pin Sour Accordingly when port P21 is used as an input output port set bits J11 and J10 of register
116. 2 pi po 0 8 p 1 3 SP lt SP 1 p SK SP lt PC PCH p Note PCL DR2 DRo A3 A0 DR2 0 DR1 DRo ROM PO a 8 B ROM PC 7 4 A ROM PO 3 0 SK SP PC SP SP 1 AM 0 0 0 0 1 0 1 0 00A 1 1 A e A M DP S G AMC 0 0 0 0 1 01 1 00 B 1 1 A A M DP CY o CY Carry S 2 JAn 0 0 1 0 n n n n 06n 1 1 IA lt A n 2 n 0to15 lt AND 0 0 0 1 1 00 0 018 1 1 A A AND M DP OR 0 0 0 1 1 0 0 1 019 1 1 A lt A OR M DP SC 0 0 0 0 0 1 1 1 007 1 1 CY lt 1 RC 0 0 0 0 0 1 1 0 006 1 1 CY c 0 SZC 0 0 1 0 1 15 1 1 02F 1 1 CY CMA 0 0 0 1 1 1 0 0 01 1 1 A A RAR 0 0 O 1 1 1 0 1 01 D 1 1 HA CY AsA2A1A0 4 SBj 0 0 0 1 1 1 j j 05 1 1 Mj DP 1 j j 0to3 S 1HB 0 0 0 0 1 1 j j 04 1 1 Mj DP 0 o j j 0to 3 S in SZBj 0 0 1 000 j j 02 j 1 1 Mj DP 0 j Oto3 SEAM 0 0 1 0 O 1 0 026 1 1 A M DP S c 9 o S E g 9 SEAn 0 0 1 00 1 0 1 025 2 2 A n o O n 0to15 x 0 0 1 1 n n n n 07 n Note p is 0 to 47 for M34519M6 p is 0 to 63 for M34519M8 E8 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z RENESAS 1 132 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description Continuous description Overflow 0 Loads the value n in the immediate field to register A When the LA instructions are continuously coded and executed only
117. 2 yi yo 3xy 1 1 X xx 0to15 Y y y 20to 15 9 zz 0 0 0 1 0 0 1 0 zzo 048 1 1 Zezz 0to3 D Z 3 S INY 0 0000 1 00 1 1 013 1 1 Y e Y 1 E DEY 0 0000 1 O0 1 1 1 01711 1 Y Y 1 TAM j 1 0 1 1 0 0 j j j j 2 Cj 1 1 A e M DP X X EXOR j j20to 15 XAM j 1 0 1 1 0 1 j j j j 2 Dj 1 1 A M DP X X EXOR j j20to15 2 XAMD j 1 0 1 1 1 1 j j j j 2 Fj 1 1 A gt M DP X X EXOR j 3 j 0to 15 Y e Y 1 E XAMI j 1 0 1 1 1 0 j j j j 2E j 1 1 A e gt M DP z X X EXOR T j 0to15 Y e Y 1 TMA j 1 0 1 0 1 1 j j j j 2 Bj 1 1 M DP lt A X X EXOR j j20to 15 Rev 1 00 Aug 06 2004 RENESAS 1 130 REJO9B0175 0100Z 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description Transfers the contents of register B to register A Transfers the contents of register A to register B Transfers the contents of register Y to register A Transfers the contents of register A to register Y Transfers the contents of register B to the high order 4 bits E7 E4 of register E and the contents of regis ter A to the low order 4 bits E3 Eo of register E Transfers the high order 4 bits E7 E4 of register E to register B and low order 4 bits E3 Eo of register E to register A Transfers the contents of the low order 3 bits A2 A0 of register A to register D Transfers the contents of register D to the low order 3 b
118. 21 selection bit 1 Returned by edge INTO pin key on wakeup control 0 Key on wakeup not used nen bit Key on wakeup used Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 77 REJ09B0175 0100Z APPLICATION 4519 Group 2 8 RAM back up 2 8 3 Notes on use 1 POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back up state Note that system cannot enter the RAM back up state when executing only the POF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction 2 Key on wakeup function After checking none of the return condition for ports PO P1 INTO and INT1 specified with register K0 K2 with valid key on wakeup function is satisfied execute the POF instruction If at least one of return condition for ports with valid key on wakeup function is satisfied system returns from the RAM back upn state immediately after the POF instruction is executed 3 Return from RAM back up mode After system returns from RAM back up mode set the undefined registers and flags The initial value of the following registers are undefined at RAM back up After system is returned from RAM back up mode set initial values Register Z 2 bits Register X 4 bits Register Y 4 bits Register D 3 bits Register E 8 bits 4 Watchdog timer The watchdog timer
119. 33 Table 2 3 4 Interrupt control register 2 ieri da 2 33 Table 2 3 5 Timer control register PA cocinados ret endete eene e ext e t ed ER 2 34 Table 2 3 6 Timer control register W1 sese ee eee 2 34 Table 2 9 7 Timer control register W2 cocina 2 34 Table 2 3 8 Timer control register W3 i aset ederent eter Pe ree d er nr ett eevee 2 35 Table 2 3 9 Timer control register WA sssssssssssseeeeeene nennen nennen 2 35 Table 2 3 10 Timer control register Wb entente nnne 2 36 Table 2 3 11 Timer control register MO sien enero ebd dtr n e 2 36 Table 2 4 1 Interrupt control register V2 eene eene 2 53 Table 2 4 2 A D control register QT i i cerent ecc tea S ceo REP Pea eh 2 53 Table 2 4 3 A D control register Q2 sss seene 2 54 Table 2 4 4 A D control register Q3 sss sese 2 54 Table 2 5 1 Interrupt control register V2 aaaea dya SNNN T ata aad eran aa e da 2 59 Table 2 5 2 Serial l O mode register Jl sss 2 59 Table 2 7 1 Voltage drop detection circuit operation State eee eee 2 70 Table 2 8 1 Functions and states retained at RAM back up mode sss 2 72 Table 2 8 2 Return source and return condition 2 73 Table 2 8 3 Start condition identification eene 2 73 Table 2 8 4 Interrupt control register TI ooo aianas RESTR ah GLS aAA 2 74 Table 2 8 5 Interrupt control register 12 sss 2 74 Table 2 8 6 Pull up control register PUO serennu eaae nnne 2 75 Table 2 8 7 Pull up control register PUT resanensacsens non 2 76 Table
120. 45 Fig 2 3 10 Period measurement of CNTRO pin input setting example 2 2 46 Fig 2 3 11 Pulse width measurement of INTO pin input setting example 1 2 47 Fig 2 3 12 Pulse width measurement of INTO pin input setting example 2 2 48 Fig 2 3 13 Watchdog timer setting example eser eee eee eee eee 2 49 Fig 2 3 14 Period measurement circuit program example sss 2 51 Rev 1 00 Aug 06 2004 RENESAS V REJO9B0175 0100Z REJO9B0175 0100Z 4519 Group List of figures Fig 2 3 15 Count start time and count time when operation starts PS T1 T2 and T3 2 51 Fig 2 3 16 Count start time and count time when operation starts T4 2 51 Fig 2 4 1 A D converter SIrUctule ue edet ceres ede ee dant ned dd ended eu deca E eR RR 2 52 Fig 2 4 2 A D conversion mode setting example 2 55 Fig 2 4 3 Analog input external circuit example 1 sse essere eee eee neee 2 56 Fig 2 4 4 Analog input external circuit examole 2 sss sss svees sss sss vesv sese esse sees onne rca onenn 2 56 Fig 2 4 5 A D converter operating mode program example sees eee ee eee eee 2 56 Fig 2 5 1 Serial 1 0 block diagram niente tree cesta ede aul dte dede denda 2 58 Fig 2 5 2 Serial l O connection example 5 deii cti sedia ae av bg 2 60 Fig 2 5 3 Serial I O register state when transfer sssssssee 2 60 Fig 2 5 4 Serial 1 O transfer timing ccoo
121. 4519 Group has a built in clock synchronous serial I O which can serially transmit or receive 8 bit data Serial I O consists of serial I O register SI serial I O control register J1 serial I O transmit receive completion flag SIOF serial I O counter Registers A and B are used to perform data transfer with internal CPU and the serial I O pins are used for external data transfer The pin functions of the serial I O pins can be set with the register J1 Synchronous circuit P20 SiIn ON n Fig 40 Serial I O structure Table 15 Serial I O control register Serial I O control register J1 at reset 00002 HARDWARE FUNCTION BLOCK OPERATIONS Table 14 Serial 1 O pins Pin P20 Sck Pin function when selecting serial I O Clock I O Sck Serial data output SOUT Serial data input SIN P21 SOUT P22 SIN Note Even when the Sck SOUT SIN pin functions are used the input of P20 P21 P22 are valid Serial I O interrupt Serial I O counter 3 SIOF SST instruction Internal reset signal MSB Serial I O register 8 LSB TABSI x TSIAB Dye TABSI Register B 4 Register A 4 R W RAM k up i at back up state retained TAJ1 TJ1A J12 Synchronous clock Instruction clock INSTCK divided by 8 Serial I O synchronous clock selection bits Instruction clock INSTCK divided by 4 Instruction clock INSTCK divided by 2 External clock Sck input
122. 49 CHAPTER 2 APPLICATION Table 2 1 1 Timer control register YV Aasaa aE nent en eet endet eere tele nne ce ea 2 6 Table 2 1 2 Timer control register W6 eee eee eee ee eee ee 2 6 Table 2 1 3 Serial I O control register Jl sese 2 7 Table 2 1 4 A D control register Q2 iniciacion nn Ra en nee e agn 2 7 Table 2 1 5 Pull up control register PUO sees eee eee 2 8 Table 2 1 6 Pull up control register PUT 2i acer nee zo cre nana 2 8 Table 2 1 7 Port output structure control register FRO sem 2 9 Table 2 1 8 Port output structure control register FR1 sese ee sees eee 2 9 Table 2 1 9 Port output structure control register ERS sees ereer eee 2 10 Table 2 1 10 Port output structure control register EH3 sss ee senenn nenen 2 10 Table 2 1 11 Key on wakeup control register KO cece eenn 2 11 Table 2 1 12 Key on wakeup control register K2 sese eee 2 11 Table 2 1 13 Connections of unused pins sese eee eree eee eee eee 2 14 Table 2 2 1 Interrupt control register V1 eene 2 18 Table 2 2 2 Interrupt control register V2 enne nennen 2 19 Table 2 2 3 Interrupt control register ll 2 19 Table 2 2 4 Interrupt control register 12 ssssssssenenennm nennen 2 20 Table 2 3 1 Interrupt control register Vi aE eet tete eee neri 2 32 Table 2 3 2 Interrupt control register V2 rennen 2 32 Rev 1 00 Aug 06 2004 ENESAS viii REJO9B0175 0100Z 4519 Group List of tables Table 2 3 3 Interrupt control register ll ee eee eree 2
123. 519 Group Notes on interrupt processing When the interrupt occurs at the same time the interrupt enable flag INTE is cleared to 0 interrupt disable state In order to enable the interrupt at the same time when system returns from the interrupt write El and RTI instructions continuously P30 INTO pin When the external interrupt input pin INTO is used set the bit 3 of register 11 to 1 Even in this case port P3o I O function is valid Also the EXFO flag is set to 1 when bit 3 of register 11 is set to 1 by input of a valid waveform valid waveform causing external 0 interrupt even if it is used as an I O port P3 The input threshold characteristics ViH VIL are different between INTO pin input and port P30 input Accordingly note this difference when INTO pin input and port P30 input are used at the same time P3 INT1 pin When the external interrupt input pin INT1 is used set the bit 3 of register I2 to 1 Even in this case port P3 I O function is valid Also the EXF1 flag is set to 1 when bit 3 of register I2 is set to 1 by input of a valid waveform valid waveform causing external 1 interrupt even if it is used as an I O port P3 The input threshold characteristics ViH VIL are different between INT1 pin input and port P31 input Accordingly note this difference when INT1 pin input and port P31 input are used at the same time POF instruction When the POF instruction is executed
124. ADAB 1 000 1 1 1 0 0 1 239 1 1 AD7 AD4 B S AD3 ADo lt A s 0 amp ADST 1 01 00 1 1 1 1 1 29F 1 1 ADF 0 c A D conversion starting o Z SNZAD 1 01 0000 1 1 1 287 1 1 V2120 ADF 2 1 S After skipping ADF lt 0 V22 lt 1 NOP a Ed TAQ1 1 0 O 1 00 O 1 0 0 244 1 1 A Q1 TQ1A 1 0 0 O 0O 0O O 1 0 0 204 1 1 Q1 lt A TAQ2 1 001 00 O 1 0 1 245 1 1 A Q2 TQ2A 1000000 1 0 1 20 B 1 1 Q2 A TAQ3 1 0 O 1 000 1 1 0 246 1 1 A Q3 TQ3A 100000 O 1 0 206 1 1 Q3 A NOP 0 00 0 0 0 0 0 0 0 000 1 1 PC lt PC 1 POF o 00 0 0 0 0 0 1 0 002 1 1 Transition to RAM back up mode EPOF 0 0 0 1 O 1 1 0 1 1 05 B 1 1 POF instruction valid SNZP 00000000 1 1 003 1 1 P 1 S WRST 1 0101 0000 0 2 A0 1 1 WDF1 1 o After skipping WDF1 0 w A 9 DWDT 1 01 00 1 1 1 0 0 2 9 C 1 1 Stop of watchdog timer function enabled O SRST 0 00 0 0 0 0 0 0 1 0 0 1 1 1 System reset occurrence Rev 1 00 Aug 06 2004 RENESAS 1 144 REJO9B0175 0100Z 4519 Group Skip condition HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Datailed description In the A D conversion mode Q13 0 transfers the high order 4 bits AD9 AD6 of register AD to register B and the middle order 4 bits AD5 AD2 of register AD to register A In the comparator mode Q13 1 transfers the middle order 4 bits AD7 AD4 of register AD to register B and the low order 4 bits AD3 ADo of register AD to register A
125. APPENDIX 4519 Group 3 3 List of precautions 5 6 7 8 3 3 7 1 3 3 8 1 2 A D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison the contents of ADF flag retains 0 not set to 1 In this case the A D interrupt does not occur even when the usage of the A D interrupt is enabled Accordingly consider the time until the comparator operation is completed and examine the state of ADF flag by software The comparator operation is completed after 2 machine cycles A D conversion clock ADCK 1 clock Analog input pins When P40 AIN4 P43 AIN7 P60 AINO P63 AIN3 are set to pins for analog input they cannot be used as I O ports P4 and P6 TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A and simultaneously the low order 2 bits of register A is 0 Recommended operating conditions when using A D converter As for the supply voltage when A D converter is used and the recommended operating condition of the A D convesion clock frequency refer to the 3 1 Electrical characteristics Notes on serial I O Note when an external clock is used as a synchronous clock An external clock is selected as the synchronous clock the clock is not controlled internally Serial transmit receive is continued as long as an external c
126. ARE 4519 Group FUNCTION BLOCK OPERATIONS A D CONVERTER Comparator Table 11 A D converter characteristics The 4519 Group has a built in A D conversion circuit that performs Parameter Characteristics conversion by 10 bit successive comparison method Table 11 Conversion format Successive comparison method shows the characteristics of this A D converter This A D converter Resolution 10 bits can also be used as an 8 bit comparator to compare analog volt Relative accuracy Linearity error 2LSB 2 7 V lt VDD lt 5 5V ages input from the analog input pin with preset values Differential non linearity error 0 9LSB 2 2 V lt VDD lt 5 5V Conversion speed 31 us f XIN 6 MHz STCK f XIN XIN through mode ADCK INSTCK 6 Analog input pin Register B 4 Register A 4 IAP4 P40 P43 IAP6 P60 P63 OP4A gp A D conversion clock ADCK P60 P63 P60 AINO o P61 AIN1 o 44 P62 AIN2 o44 Successive comparison register AD 10 P63 AIN3 o 44 P40 AIN4 8 A D interrupt P41 AIN5 o 44 P42 AIN6 o 4 P43 AIN7 a a 8 channel multi plexed analog switch DA converter Comparator register 8 Notes 1 This switch is turned ON only when A D converter is operating and generates the comparison voltage 2 Writing reading data to the comparator register is possible only in the comparator mode Q13 1 The value
127. ARE DESCRIPTION cco esse tog acs ceceeedesds natcceceaa caste cree cee diatccset eect nae ied naieeeenag ees 1 2 O oo e e ee S M MM 1 2 APPEICATIONI S ob M ME ae ea 1 2 PIN CONFIGURATION cernerent e 1 2 BLOCK DIAGRAM 1 3 PERFORMANCE OVERVIEW 1 4 PIN DESCRIPTION e 1 5 MULTIFUNCTION codes 1 6 DEFINITION OF CLOCK AND CYCLE cinc eres 1 6 PORT FUNCTION A nus Pen S UE M E a E en 1 7 CONNECTIONS OF UNUSED PINS 1 8 PORT BLOCK DIAGRAMS cierres uses dese eite phus reset inci rupe 1 9 FUNCTION BLOCK OPERATIONS comic ans 1 17 DP S s LM RE M LE M E 1 17 PROGRAM MEMORY ROMI 1 20 DATA MEMORY RAM da 1 21 INTERRUPT FUNCTION nas 1 22 EXTERNAL INTERRUPTS oireann del mU LM D D LEE 1 26 A E 1 31 WATCHDOG TIMER terere entres ter erdts e iuo ttleseesbeei neo cst Dun cit Non Gd 1 45 A D CONVERTER COMPARATOR ccsscescsssscsssscssuccssecssseecceccssecessusessucersesersecesecessucerseser 1 47 A RM UR RCNH 1 53 RESET FUNCTION e 1 58 VOLTAGE DROP DETECTION CIRCUIT nnn 1 62 RAM BACK UP MODE rectc ad 1 63 CLOCK CONTROL Ss s ears mense deeds ED EAM EU 1 68 ROM ORDERING METHOD ns 1 71 LIST OF PRECAUTIONS ttt ttt ttt ttes tests sts ssa sUSS 1 72 CONTROL REGISTERS n nccccssssesccseconecsoeecoessueeccuseseeccueeonessutesneecneesonercssseconescneeraneonersaneccsesonse 1 78 OES TRU TONGS ccs umore eed tied ce d D E EE eta 1 85 SVMBOL ce eor RR een ML EU A LEE 1 85 INDEX LIST OF INSTRUCTION FUNCTION ettet 1 86 MACHINE INSTRUCTIONS INDEX BY
128. AS 1 21 4519 Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address interrupt address according to each interrupt source An interrupt occurs when the following 3 conditions are satisfied An interrupt activated condition is satisfied request flag 1 Interrupt enable bit is enabled 1 Interrupt enable flag is enabled INTE 1 Table 3 shows interrupt sources Refer to each interrupt request flag for details of activated conditions 1 Interrupt enable flag INTE The interrupt enable flag INTE controls whether the every inter rupt enable disable Interrupts are enabled when INTE flag is set to 1 with the El instruction and disabled when INTE flag is cleared to 0 with the DI instruction When any interrupt occurs the INTE flag is automatically cleared to 0 so that other interrupts are disabled until the EI instruction is executed 2 Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction Table 4 shows the interrupt request flag interrupt enable bit and skip instruction Table 5 shows the interrupt enable bit function 3 Interrupt request flag When the activated condition for each interrupt is satisfied the cor responding interrupt request flag is set to 1 Each interrupt request flag is cleared to 0 when either an interrupt occurs
129. Arithmetic operation Description Takes the OR operation between the con tents of register A and the contents of M DP and stores the result in register A POF Power OFf Instruction Dg Do Number of Number of Flag CY Skip condition code ololo o o o o0 o ol TA T VE 1 1 Operation Transition to RAM back up mode Grouping Other operation Description Puts the system in RAM back up state by executing the POF instruction after execut ing the EPOF instruction Note If the EPOF instruction is not executed before executing this instruction this instruction is equivalent to the NOP instruction RAR Rotate Accumulator Right Instruction Dg Do Number of Number of Flag CY Skip condition code ololtololol11111 1 D words cycles 1 1 0 1 Operation P OY gt AsA2A1 Aon Grouping Arithmetic operation Description Rotates 1 bit of the contents of register A in cluding the contents of carry flag CY to the right RB j Reset Bit Instruction Dg Do Number of Number of Flag CY Skip condition code ololol1lolol111 j C words cycles 2 116 1 1 Operation Mj DP 0 Grouping Bit operation j20to3 Description Clears 0 the contents of bit j bit specified by the value j in the immediate field of M DP Rev 1 00 Aug 06 2004 RENESAS 1 101 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued RC Reset Carry flag
130. Arithmetic operation Description Sets 1 to carry flag CY SD Set port D specified by register Y Instruction Dg Do Number of Number of Flag CY Skip condition code ololololo t lo 1 o 1 o 1 s words x ees 2 16 1 1 E B Operation D Y 1 Grouping Input Output operation Y 20107 Description Sets 1 to a bit of port D specified by regis ter Y Rev 1 00 Aug 06 2004 RENESAS 1 103 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued SEA n Skip Equal Accumulator with immediate data n Instruction Dg Do Number of Number of Flag CY Skip condition code o ololo 11o o 1 0 1 fo 2 5 wales i 2 2 A n 0 0 0 1 1 1 n n nj n P 0 7 n 16 Grouping Comparison operation Operation A 2n Description Skips the next instruction when the con n 0to 15 tents of register A is equal to the value n in the immediate field Executes the next instruction when the con tents of register A is not equal to the value n in the immediate field SEAM Skip Equal Accumulator with Memory Instruction Do Do Number of Number of Flag CY Skip condition code o ojo o 1 0o o 1 1 0 jo 2 6 words cycles 1 1 A M DP Operation A M DP Grouping Comparison operation Description Skips the nex
131. BM a gt LA 11 27 43 BL BL BM p gt LA 12 28 44 BL BL BM o gt LA 13 29 45 BL BL BM LA 14 30 46 BL BL BM Ee LA 15 31 47 BL BL BM The above table shows the relationship between machine language codes and machine language instructions D3 Do show the low order 4 bits of the machine language code and Dg D4 show the high order 6 bits of the machine language code The hexadecimal representa tion of the code is also provided There are one word instructions and two word instructions but only the first word of each instruction is shown Do not use code marked The codes for the second word of a two word instruction are described below The second word BL 1p paaa aaaa BML ip paaa aaaa BLA ip pp00 pppp BMLA 1p pp0O pppp SEA 00 0111 nnnn SZD 00 0010 1011 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z cannot be used in the M34519M6 7tENESAS 1 146 4519 Group INSTRUCTION CODE TABLE continued D3 DQ 100000 100001100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 HARDWARE INSTRUCTION CODE TABLE 101100 101101 101110 101111 Hex notation 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 0000
132. BPS instruction Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data Prescaler starts counting after the following process O set data in prescaler and set the bit O of register PA to 1 When a value set in reload register RPS is n prescaler divides the count source signal by n 1 n 0 to 255 Count source for prescaler is the instruction clock INSTCK Once count is started when prescaler underflows the next count pulse is input after the contents of prescaler becomes 0 new data is loaded from reload register RPS and count continues auto reload function The output signal ORCLK of prescaler can be used for timer 1 2 3 and 4 count sources 3 Timer 1 interrupt function Timer 1 is an 8 bit binary down counter with the timer 1 reload reg ister R1 Data can be set simultaneously in timer 1 and the reload register R1 with the T1AB instruction Data can be written to re load register R1 with the TR1AB instruction Data can be read from timer 1 with the TAB1 instruction Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data When executing the TR1AB instruction to set data to reload regis ter R1 while timer 1 is operating avoid a timing when timer 1 underflows Timer 1 starts counting after the following process O set data in timer 1 set count source by bits 0 and 1 of register W1 and set the bit 2 of register W1
133. Flag CY Skip condition code 11ololslolololslo s le 4 s Worgs cycles 2 16 1 1 Operation A Q2 Grouping X A D conversion operation Description Transfers the contents of A D control regis ter Q2 to register A TAQ3 Transfer data to Accumulator from register Q3 Instruction Dg Do Number of Number of Flag CY Skip condition code 1 0 0 1 0 0 0 1 1 0 2 4 6 M MS a 2 16 1 1 Operation A Q3 Grouping A D conversion operation TASP Transfer data to Accumulator from Stack Pointer Description Transfers the contents of A D control regis ter Q3 to register A Instruction Dg Do Number of Number of Flag CY Skip condition code ojojo tjo t ol ojo o o s o HE 2 16 1 1 H i Operation A2 Ao SP2 SPo Grouping Register to register transfer A3 0 Description Transfers the contents of stack pointer SP to the low order 3 bits A2 Ao0 of register A Note After this instruction is executed 0 is stored to the bit 3 A3 of register A TAV1 Transfer data to Accumulator from register V1 Instruction Do Do Number of Number of Flag CY Skip condition code 0 0 0 1 0 1 0 1 0 0 0 5 4 woras cycles 2 16 1 1 E Operation A V1 Grouping Interrupt operation Description Transfers the contents of interrupt control register V1 to regist
134. HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS CNTR1 output invalid W43 0 Timer 4 count source Timer 4 count value Reload register PWM signal output invalid PWM signal L Timer 4 start fixed CNTR1 output valid W43 1 PWM signal H interval extension function invalid W42 0 timer4countsource LJ LJ U L LU LT UU UU UU ET LT UU ET LT LT L Timer 4 count value Reload register Timer 4 underflow signal E O 9 rE iL L PWM 3 clock 3 clock signal H PWM period 7 clock P La PWM period 7 clock ae CNTR1 output valid W43 1 PWM signal H interval extension function valid W42 1 Note Timer 4 count source l l Timer 4 count value Reload register L U I 1 PWM 3 5 clock 3 5 clock signal i 1 1 n 4 start 148 PWM period 7 5 clock JM 48 PWM period 7 5 clock Be Note At PWM signal H interval extension function valid set 0116 or more to reload register RAH Fig 29 Timer 4 operation reload register R4L 0316 RAH 0216 Rev 1 00 Aug 06 2004 RENESAS 1 42 REJO9B0175 0100Z HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS CNTR1 output auto control circuit by timer 3 is selected CNTR1 output valid W43 1 CNTR1 output auto control circuit selected W61 1 PWM signal I I I Timer 3 underflow signal I T Timer 3 start i i
135. ID UD ED eer oor aa eload register B R4H R4L A R4H Timer 4 Fl underflow signal PWM signal J Note 1 i Timer 4 count stop timing Notes 1 At CNTR1 output vaild if a timing of timer 4 underflow overlaps with a timing to stop timer 4 a hazard may be generated in a CNTR1 output waveform Please review sufficiently 2 At CNTR1 output valid timer 4 stops after H interval of PWM signal set by reload register R4H is output Fig 31 Timer 4 count start stop timing Rev 1 00 Aug 06 2004 RENESAS REJ09B0175 0100Z 1 44 4519 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a pro gram run away occurs Watchdog timer consists of timer WDT 16 bit binary counter watchdog timer enable flag WEF and watchdog timer flags WDF1 WDF2 The timer WDT downcounts the instruction clocks as the count source from FFFF16 after system is released from reset After the count is started when the timer WDT underflow occurs after the count value of timer WDT reaches 000016 the next count pulse is input the WDF1 flag is set to 1 If the WRST instruction is never executed until the timer WDT un derflow occurs until timer WDT counts 65534 WDF2 flag is set to 1 and the RESET pin outputs L level to reset the microcom puter Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcom
136. IN not selected Sck Sour P22 selected P20 P21 SIN not selected Sck P21 SIN selected P20 Sour P22 not selected 1 0 1 0 1 1 0 1 0 1 at reset 00002 SCK SOUT SIN selected P20 P21 P22 not selected R W at RAM back up state retained TAQ1 TQ1A A D operation mode selection bit A D conversion mode Comparator mode Analog input pin selection bits A D control register Q2 Q12 Q11 Q10 Analog input pins 0 0 NO N1 N2 N3 N4 N5 N6 at reset 00002 I IE EI gt gt gt N7 R W at RAM back up state retained TAQ2 TQ2A P40 AIN4 P41 AIN5 P42 AIN6 P43 AIN7 pin function selection bit P40 P41 P42 P43 AIN4 AIN5 AIN6 AIN7 P62 AIN2 P63 AIN3 pin function selection bit P62 P63 AIN2 AIN3 P61 AIN1 pin function selection bit P61 AIN1 P60 AINO pin function selection bit A D control register Q3 P60 A Oo joj O O at reset 00002 AINO R W RAM back up state retained at back up state retaine TAQS TQ3A Not used This bit has no function but read write is enabled A D converter operation clock selection bit Instruction clock INSTCK On chip oscillator f RING A D converter operation clock division ratio selection bits Division ratio Frequency divided by 6 Frequency divided by
137. INT1 processing O When the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the external 1 interrupt occurs the interrupt processing is executed from address 2 in page 1 O When the interrupt is not used The interrupt is disabled and the SNZ1 instruction is valid when the bit 1 of register V1 is set to 0 3 Timer 1 interrupt The interrupt request occurs by the timer 1 underflow B Timer 1 interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the timer 1 interrupt occurs the interrupt processing is executed from address 4 in page 1 O When the interrupt is not used The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set to 0 Rev 1 00 Aug 06 2004 RENESAS 2 15 REJ09B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 4 Timer 2 interrupt The interrupt request occurs by the timer 2 underflow B Timer 2 interrupt processing O When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the timer 2 interrupt occurs the interrupt processing is executed from address 6 in page 1 When the interrupt is not used
138. IPTION FEATURES APPLICATION PIN CONFIGURATION DESCRIPTION The 4519 Group is a 4 bit single chip microcomputer designed with CMOS technology Its CPU is that of the 4500 series using a simple high speed instruction set The computer is equipped with serial I O four 8 bit timers each timer has one or two reload regis ters a 10 bit A D converter interrupts and oscillation circuit switch function The various microcomputers in the 4519 Group include variations of the built in memory size as shown in the table below FEATURES Minimum instruction execution time sse 0 5 us at 6 MHz oscillation frequency in XIN through mode L Interr pt sinis e tre cce koc e d re Perd curae 8 sources O Key on wakeup function PINS sss eee eee eee eee eee eee 10 Ia a 8 bits X 1 O A D converter 10 bit successive comparison method 8ch O Voltage drop detection circuit Reset occurrence ocomoconionncnoncnonananaranones Typ 3 5 V Ta 25 C Reset release eene Typ 3 7 V Ta 2 25 C e Watchdog timer O Clock generating circuit ceramic resonator RC oscillation quartz crystal oscillation on chip oscillator LED drive directly enabled port D Supply voltage Mask ROM version eee One Time PROM version 1 8 to 5 5 V 2 510 5 5 V It depends on operation source clock oscillation frequency and op eration mode Timers RUM di eeeteererecrcereerreercerrrrrrerrerre
139. J1 to 002 or 102 3 Port P22 is also used as the serial I O pin SIN Accordingly when port P22 is used as an input output port set bits J11 and J10 of register J1 to 002 or 102 4 Port P3 Port P3 is a 4 bit 1 O port P30 is also used as INTO input pin and P31 is also used as INT1 input pin Also the key on wakeup function of INTO and INT1 can be turned ON OFF by setting bits K20 and K22 of register K2 O Input In the following condition the pin state of port P3 is transferred as input data to register A when the IAP3 instruction is executed Set the output latch of specified port P3i i 0 1 2 or 3 to 1 with the OP3A instruction If the output latch is 0 0 is output to specified port P3 O Output The contents of register A is set to the output latch with the OP3A instruction and is output to port P3 The output structure is an N channel open drain 5 Port P4 Port P4 is a 4 bit I O port Rev 1 00 Aug 06 2004 RENESAS 2 3 REJO9B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 6 Port P5 Port P5 is a 4 bit I O port O Input In the following conditions the pin state of port P5 is transferred as input data to register A when the IAP5 instruction is executed e Set bit FR3i i20 1 2 or 3 of register FR3 to 0 according to the port to be used Set the output latch of specified port P5i i 0 1 2 or 3 to 1 with the OP5A instruction If FR3i is 0 and the output latch is
140. Jl synchronous clock b1 bO Serial I O ports Sck SOUT SIN selected amp Clear Interrupt Request Serial I O interrupt activated condition is cleared Serial I O transmit receive completion flag SIOF LO Serial I O interrupt activated condition cleared SNZS y us when the interrupt request is cleared F When 0 is executed considering the skip of the next instruction according to the flag SIO insert the NOP instruction after the SNZSI instruction O Set Interrupts Note Interrupts except serial I O interrupt is enabled O Set Transmit Data Transmit data is set to serial I O register Serial I O register SI XxX16 TSIAB Check Start Condition of Serial I O Operation Whether the transmit receive of the slave side can be performed pin level of control signal L or not is checked b3 bO Register Y 0101111 Specify bit position of port D TYA Port D3 output latch 1 Set to input SD Port D3 input level check SZD Start Serial I O Operation If the transmit receive of the slave side can be performed serial transfer is started SST O Check Serial I O Interrupt Request SIOF flag is checked SNZSI Receive Data Processing Data processing received by serial transfer is executed Register SI register A register B TABSI y When serial communication is executed repeat to X it can be 0 or 1 J instruction Fig 2 5 5 Setti
141. LK XIN input CNTRO input 1 to 256 Timer 2 count source CNTRO output Timer 1 interrupt Wi W2 w5 Timer 2 8 bit programmable binary down counter System clock STCK Prescaler output ORCLK Timer 1 underflow T1UDF PWM output PWMOUT 1 to 256 Timer 3 count source CNTRO output Timer 2 interrupt Timer 3 8 bit programmable binary down counter link to INT1 input PWM output PWMOUT Prescaler output ORCLK Timer 2 underflow T2UDF CNTR1 input 1 to 256 CNTR1 output control Timer 3 interrupt Timer 4 8 bit programmable binary down counter PWM output function XIN input Prescaler output ORCLK 1 to 256 Timer 2 3 count source CNTR1 output Timer 4 interrupt Watchdog timer 16 bit fixed dividing frequency Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Instruction clock INSTCK RENESAS e System reset count twice WDF flag decision 1 32 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS System clock STCK Q Divided by 8 Internal clock On chip oscillator generating circuit Instruction clock Divided by 2 INSTCK Ceramic resonance RC oscillation Quartz crystal oscillation T1UDF 1 H172 T2UDF On chip oscillator 1 16 De CNTRO P3o INTOO Timer
142. M back up state retained FR23 Port D7 CNTR1 output structure selection bit N channel open drain output CMOS output FR22 Port De CNTRO output structure selection bit N channel open drain output CMOS output FR21 Port D5 output structure selection bit N channel open drain output CMOS output FR20 Port D4 output structure selection bit Port output structure control register FR3 N channel open drain output o i oj oj o CMOS output at reset 00002 at RAM back up state retained FR33 Port P53 output structure selection bit N channel open drain output CMOS output FR32 Port P52 output structure selection bit N channel open drain output CMOS output FR31 Port P51 output structure selection bit N channel open drain output CMOS output FR30 Port P50 output structure selection bit N channel open drain output AjO O O fO CMOS output Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z RENESAS 1 84 HARDWARE 4519 Group INSTRUCTIONS INSTRUCTIONS SYMBOL The 4519 Group has the 153 instructions Each instruction is de The symbols shown below are used in the following list of instruc scribed as follows tion function and the machine instructions 1 Index list of instruction function 2 Machine instructions index by alphabet 3 Machine instruc
143. NOP X these bits are not used here X these bits are not used here Fig 21 External 1 interrupt program example 1 Fig 23 External 1 interrupt program example 3 Q Note 2 on bit 3 of register I2 When the bit 3 of register I2 is cleared to 0 the RAM back up mode is selected and the input of INT1 pin is disabled be careful about the following notes When the input of INT1 pin is disabled register 123 0 set the key on wakeup function to be invalid register K22 0 before System enters to the RAM back up mode refer to Figure 220 LA X0XX2 TK2A Input of INT1 key on wakeup invalid DI EPOF POF RAM back up X these bits are not used here Fig 22 External 1 interrupt program example 2 Rev 1 00 Aug 06 2004 RENESAS 1 30 REJO9B0175 0100Z HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS TIMERS Fixed dividing frequency timer The 4519 Group has the following timers The fixed dividing frequency timer has the fixed frequency divid Programmable timer ing ratio n An interrupt request flag is set to 1 after every n The programmable timer has a reload register and enables the count of a count pulse frequency dividing ratio to be set It is decremented from a set ting value n When it underflows count to n 1 a timer interrupt request flag is set to 1 new data is loaded from the reload reg ister and count continues auto reload function n Counter initial value Coun
144. NTO INT1 0 3 to VDD 0 3 Input voltage AINO AIN7 0 3 to VDD 0 3 Output voltage Output transistors in cut off state 0 3 to VDD 0 3 PO P1 P2 P3 P4 P5 P6 Do D7 RESET Output voltage Sck Sour CNTRO CNTR1 Output transistors in cut off state 0 3 to VDD 0 3 Output voltage XOUT 0 3 to VDD 0 3 Power dissipation Ta 25 C 42P2R A 300 Operating temperature range 20 to 85 Storage temperature range 40 to 125 Rev 1 00 Aug 06 2004 RENESAS 3 2 REJO9B0175 0100Z 4519 Group 3 1 2 Recommended operating conditions Table 3 1 2 Recommended operating conditions 1 Mask ROM version Ta 20 C to 85 C VDD 1 8 to 5 5 V unless otherwise noted One Time PROM version Ta 20 C to 85 C VDD 2 5 to 5 5 V unless otherwise noted Parameter Conditions APPENDIX 3 1 Electrical characteristics Min Supply voltage when ceramic resonator on chip oscillator is used N 4 O A Mask ROM version 4 0 2 7 2 0 1 8 One Time PROM version 4 0 2 7 ZA 2 2 2 2 2 2 IA IA IA IA IA IA IA 65 4 O A 2 5 Supply voltage when RC oscillation is used f STCK lt 4 4 MHz 2 7 Supply voltage when quartz crystal oscillator is used Mask ROM version f XIN x 50 kHz 2 0 One Time PROM version f XIN x 50 kHz 2 5 RAM back up voltage Mask ROM vers
145. NTR1 D7 Sck SOUT SIN INTO INT1 Notes 1 Pins except above have just single function The input output of D can be used even when CNTRO The input of D can be used even when CNTRO output The input output of D7 can be used even when CNTR1 The input of D7 can be used even when CNTR1 output NONANI DEFINITION OF CLOCK AND CYCLE Operation source clock The operation source clock is the source clock to operate this product In this product the following clocks are used Clock f XIN by the external ceramic resonator Clock f XIN by the external RC oscillation e Clock f XIN by the external input Clock f RING of the on chip oscillator which is the internal oscillator Clock f XIN by the external quartz crystal oscillation Table Selection of system clock Register MR MR2 MRi System clock lt a 3 AINO P60 AIN1 P61 AIN2 P62 AIN3 P63 AIN4 P40 AIN5 P41 AIN6 P42 AIN7 P43 The input output of P30 and P31 can be used even when INTO and INT1 are selected The input of ports P20 P22 can be used even when SIN SOUT and Sck are selected input is selected is selected input is selected is selected System clock STCK The system clock is the basic clock for controlling this product The system clock is selected by the clock control register MR shown as the table below Instruction clock INSTCK The instruction clock is the basic clock f
146. Open Connect to Vss P22 Sin Open Sin pin is not selected Connect to Vss P30 INTO Open 0 is set to output latch Connect to Vss P3iINT1 Open 0 is set to output latch Connect to Vss P32 P3s Open Connect to Vss P40 Aina P 43 Open Ain7 Connect to Vss P5o P55 Open Connect to Vss N channel open drain is selected for the output structure P60 Aino P 63 Open Ains Connect to Vss Notes 1 After system is released from reset the internal oscillation on chip oscillator is selected for system clock RGo 0 MRo 1 2 When the CRCK instruction is executed the RC oscillation circuit becomes valid Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution In order to start oscillation setting the main clock f XIN oscillation to be valid MR1 0 is required If necessary gen erate the oscillation stabilizing wait time by software Also when the main clock f XIN is selected as system clock set the main clock f XIN oscillation MR1 0 to be valid and select main clock f XiN MRo 0 Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started In order to use the external clock input for the main clock select the ceramic resonance by executing the CMCK in struction
147. P instruction for the case when a skip is performed with the SNZ1 instruction Set both the external 1 interrupt enable bit V11 and the INTE flag to 1 The external 1 interrupt is now enabled Now when a valid wave form is input to the P31 INT1 pin the EXF1 flag is set to 1 and the external 1 interrupt occurs 1 27 4519 Group 3 External interrupt control registers Interrupt control register 11 Register 1 controls the valid waveform for the external 0 inter rupt Set the contents of this register through register A with the TIA instruction The TAI1 instruction can be used to transfer the contents of register 11 to register A Table 8 External interrupt control register Interrupt control register 11 at reset 00002 HARDWARE FUNCTION BLOCK OPERATIONS Interrupt control register 12 Register I2 controls the valid waveform for the external 1 inter rupt Set the contents of this register through register A with the TI2A instruction The TAI2 instruction can be used to transfer the contents of register 12 to register A R W at RAM back up state retained TAH THA INTO pin input disabled INTO pin input control bit INTO pin input enabled Interrupt valid waveform for INTO pin Falling waveform L level L level is recognized with the SNZIO instruction return level selection bit Rising waveform H level H level is recognized with the SNZIO instruction O
148. PHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAM Transfer data to Accumulator from register 11 Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jolo 1Joji1fojoj1 1 2 s a NOUS Evers 2 16 1 1 Operation A lt 11 Grouping Interrupt operation Description Transfers the contents of interrupt control register 11 to register A TAI2 Transfer data to Accumulator from register I2 Instruction Dg Do Number of Number of Flag CY Skip condition code 1 To To J1 To 1 Jo T1ToTol le 5 4 wolds G 2 16 1 1 Operation A lt 12 Grouping Interrupt operation Description Transfers the contents of interrupt control register 12 to register A TAJ1 Transfer data to Accumulator from register J1 Instruction Dg Do Number of Number of Flag CY Skip condition code 1 olo 1 o olo o 1 o 2 4 e woro G 2 16 1 1 Operation A J1 Grouping Serial I O operation Description Transfers the contents of serial I O control register J1 to register A TAKO Transfer data to Accumulator from register KO Instruction D9 Do Number of Number of Flag CY Skip condition code 1lololiloli lolil lol 2 s e Moros cycles
149. PHABET continued INY INcrement register Y Instruction Dg Do Number of Number of Flag CY Skip condition code o lolo lolo li lolo 1 1 i 3 is words cycles 1 1 Y 20 Operation Y Y 1 Grouping RAM addresses Description Adds 1 to the contents of register Y As a re sult of addition when the contents of register Y is 0 the next instruction is skipped When the contents of register Y is not 0 the next instruction is executed LA n Load n in Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 0 0 01 1 1 n in nn l n words cycles 1 1 Continuous description Operation A n Grouping Arithmetic operation n 0 to15 Description Loads the value n in the immediate field to register A When the LA instructions are continuously coded and executed only the first LA in struction is executed and other LA instructions coded continuously are skipped LXY x y Load register X and Y with x and y Instruction Dg Do Number of Number of Flag CY Skip condition code 1 1 x3 x2 x1 xo ya y2 y1 yo y Wales 2 16 1 1 Continuous description Operation X xx 0to 15 Grouping RAM addresses Y y y 0t
150. PLICATION 4519 Group 2 2 Interrupts 6 Interrupt control register 12 Table 2 2 4 shows the interrupt control register 12 Set the contents of this register through register A with the TI2A instruction In addition the TAI2 instruction can be used to transfer the contents of register I2 to register A Table 2 2 4 Interrupt control register 12 at reset 00002 at RAM back up state retained 0 INT1 pin input disabled 1 INT1 pin input enabled Falling waveform L level L level is recognized with Interrupt control register I2 R W 123 INT1 pin input control bit Note 2 Int t valid f for INT1 as S Jt Epis e SE 9 the SNZI1 instruction in return level selection bi dl Rising waveform H level H level is recognized with Note 2 1 the SNZI1 instruction 121 INT1 pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected 120 INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit not selected synchronous circuit selection bit Timer 3 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 122 and 123 are changed the external interrupt request flag EXF1 may be set to 1 Accordingly clear EXF1 flag with the SNZ1 instruction when the bit 1 V11 of register V1 to 0 In this time set the NOP instruction after the SNZ1 instruction for the case when a
151. RAM back up state retained TAI2 TI2A INT1 pin input disabled INT1 pin input enabled Falling waveform L level L level is recognized with the SNZI1 Interrupt valid waveform for INT1 pin instruction return level selection bit Note 2 Rising waveform H level H level is recognized with the SNZI1 instruction One sided edge detected Both edges detected INT1 pin Timer 3 count start synchronous Timer 3 count start synchronous circuit not selected circuit selection bit Timer 3 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 112 113 122 and 123 are changed the external interrupt request flag EXFO EXF1 may be set to 1 INT1 pin input control bit Note 2 INT1 pin edge detection circuit control bit Rev 1 00 Aug 06 2004 RENESAS 1 78 REJO9B0175 0100Z 4519 Group Clock control register MR at reset 11112 HARDWARE CONTROL REGISTERS at RAM back up 11112 Operation mode selection bits Operation mode Through mode frequency not divided Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock f XIN oscillation circuit control bit Main clock f XIN oscillation enabled Main clock f XIN oscillation stop System clock oscillation source selection bit Clock control register RG
152. RC oscillation Note VDD 2 7 to 5 5 V Oscillation frequency with a ceramic resonator selected external clock input Note The frequency is affected by a capacitor a resistor and a microcomputer So set the constants within the range of the frequency limits lt System clock STCK operating condition map gt When ceramic resonance is used STCK MHz 44L rL Recommended operating operation 51 ETE MEN 5 l l Vop V y pereza 18 2 2 2 5 One Time PROM version Rev 1 00 Aug 06 2004 REJ09BO0175 0100Z Mask ROM version Through mode VDD 4 0 to 5 5 V VDD 2 7 to 5 5 V VDD 2 0to 5 5 V VDD 1 8 to 5 5 V Frequency 2 mode VDD 2 7 to 5 5 V VDD 2 0to 5 5 V VDD 1 8to 5 5 V Frequency 4 8 mode VDD 2 0to 5 5 V VDD 1 8 to 5 5 V One Time PROM Through mode version VDD 4 0 to 5 5 V VDD 2 7 to 5 5 V VDD 2 5 to 5 5 V Frequency 2 mode VDD 2 7 to 5 5 V VDD 2 5 to 5 5 V Frequency 4 8 mode When RC oscillation is used STCK MHz 44 L 2 Recommended operating operation Vop V 7tENESAS VDD 2 5 to 5 5 V When external clock is used f STCK MHz A 46 2 1 el SE a2Ep r i Recommended operating operation 1 5 5 4519 Group Table 3 1 4 Recommended operating conditi
153. RUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAB Transfer data to Accumulator from register B Instruction Dg Do Number of Number of Flag CY Skip condition code olololo 0 6 ile words cycles 1 1 Operation A B Grouping Register to register transfer Description Transfers the contents of register B to reg TAB1 Transfer data to Accumulator and register B from timer 1 ister A Instruction Dg Do Number of Number of Flag CY Skip condition code 1lolol1 0 2171 0 words cycles 2 16 1 1 Operation B T17 T14 Grouping Timer operation A T13 T10 Description Transfers the high order 4 bits T17 T14 of TAB2 Transfer data to Accumulator and register B from timer 2 timer 1 to register B Transfers the low order 4 bits T13 T10 of timer 1 to register A Instruction Dg Do Number of Number of Flag CY Skip condition code 14lolo 1 1 2 zl4 words cycles 2 16 1 1 Operation B T27 T24 Grouping X Timer operation A T23 T20 Description Transfers the high order 4 bits T27 T24 of TAB3 Transfer data to Accumulator and register B from timer 3 timer 2 to register B Transfers the low order 4 bits T23 T20 of timer 2 to re
154. Rev 1 00 Aug 06 2004 134 NE SAS REJO9B0175 0100Z 1 124 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TR1AB Transfer data to register R1 from Accumulator and register B Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jojojoj1 i 1 1 1 1 e a F worgs cycles 2 16 1 1 Operation R17 R14 B Grouping Timer operation R13 R10 A Description Transfers the contents of register B to the high order 4 bits R17 R14 of reload regis ter R1 and the contents of register A to the low order 4 bits R13 R10 of reload regis ter R1 TR3AB Transfer data to register R3 from Accumulator and register B Instruction Dg Do Number of Number of Flag CY Skip condition code 1 0 0 0 1 1 1 0 1 1 2 3 B wolds cycles 2 16 1 1 Operation R37 R34 B Grouping Timer operation R33 R30 A Description Transfers the contents of register B to the high order 4 bits R37 R34 of reload regis ter R3 and the contents of register A to the low order 4 bits R33 R30 of reload regis ter R3 TRGA Transfer data to register RG from Accumulator Instruction Dg Do Number of Number of Flag CY Skip
155. SNZT1 0001 SNZT2 0010 SNZT3 0011 SNZT4 0100 0101 TPSAB TABPS 0110 0111 T4HAB SNZAD T4R4L 1000 TFROATSIAB SNZSI 1001 ITFR1ATADAB 1010 ITFR2A 1011 ITFRSATRSAB 1100 1101 IIPUOA 1110 IIPU1A ITAPU1 1111 TR1AB The above table shows the relationship between machine language codes and machine language instructions D3 Do show the low order 4 bits of the machine language code and D9 D4 show the high order 6 bits of the machine language code The hexadecimal representation of the code is also provided There are one word instructions and two word instructions but only the first word of each instruction is shown Do not use code marked The codes for the second word of a two word instruction are described below The second word BL 1p paaa aaaa BML lp paaa aaaa BLA 1p pp00 pppp BMLA tp pp00 pppp SEA 00 0111 nnnn SZD 00 0010 1011 Rev 1 00 Aug 06 2004 REJ09B0175 0100Z 132 NE SAS 1 147 HARDWARE 4519 Group BUILT IN PROM VERSION BUILT IN PROM VERSION In addition to the mask ROM versions the 4519 Group has the One Time PROM versions whose PROMs can only be written to and not be erased The built in PROM version has functions similar to those of the mask ROM vers
156. T2 instruction O Start Timer Operation and Prescaler Operation Timer 2 and prescaler temporarily stopped are restarted b3 b0 Timer control register W2 111011 b2 Timer 2 operation start TW2A b0 Timer control register PA 1 Prescaler start TPAA Enable Interrupts The Timer 2 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V1 1 X X X b3 Timer 2 interrupt occurrence enabled TV1A Interrupt enable flag INTE 1 All interrupts enabled El y Constant period interrupt execution started A The prescaler count value and timer 2 count value to make the interrupt occur every 1 ms are set as follows 1 ms 4 0 MHz X 3 X 15 1 X 82 1 System clock Instruction Prescaler Timer 2 count value clock count value X it can be 0 or 1 J instruction Fig 2 2 6 Timer 2 constant period interrupt setting example Rev 1 00 Aug 06 2004 RENESAS 2 27 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts O Disable Interrupts Timer 3 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI Interrupt control register V2 b0 Timer 3 interrupt occurrence disabled TV2A Q Stop Timer Operation Timer 3 and prescaler are temporarily stopped Timer 3 count source is selected TW3A b3 b3 Timer 3 count auto stop circuit not selected Timer con
157. TAB2 TAB3 TAB4 to read its data Writing to the timer Stop timer 1 2 3 or 4 counting and then execute the data write instruction T1AB T2AB T3AB T4AB to write its data Mriting to reload register R1 R3 R4H When writing data to reload register R1 reload register R3 or re load regiser R4H while timer 1 timer 3 or timer 4 is operating avoid a timing when timer 1 timer 3 or timer 4 underflows Timer 4 In order to stop timer 4 while the PWM output function is used avoid a timing when timer 4 underflows When H interval extension function of the PWM signal is set to be valid set 1 or more to reload register R4H Watchdog timer The watchdog timer function is valid after system is released from reset When not using the watchdog timer function execute the DWDT instruction and the WRST instruction continuously and clear the WEF flag to 0 to stop the watchdog timer function The watchdog timer function is valid after system is returned from the RAM back up state When not using the watchdog timer func tion execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back up state and stop the watchdog timer function When the watchdog timer function and RAM back up function are used at the same time execute the WRST instruction before sys tem enters into the RAM back up state and initialize the flag WDF1 1 72
158. TO P12 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PU P11 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PULO P10 pin 0 Pull up transistor OFF pull up transistor control bit Pull up transistor ON Note R represents read enabled and W represents write enabled 5 Key on wakeup control register KO Table 2 8 8 shows the key on wakeup control register KO Set the contents of this register through register A with the TKOA instruction The contents of register KO is transferred to register A with the TAKO instruction Table 2 8 8 Key on wakeup control register KO at reset 00002 Key on wakeup control register KO at RAM back up state retained R W K03 Pins P12 and P13 key on wakeup 0 Key on wakeup not used control bit 1 Key on wakeup used K02 Pins P10 and P11 key on wakeup 0 Key on wakeup not used control bit 1 Key on wakeup used KO Pins P02 and P03 key on wakeup 0 Key on wakeup not used control bit 1 Key on wakeup used Koo Pins POo and P01 key on wakeup 0 Key on wakeup not used control bit Key on wakeup used Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 76 REJ09B0175 0100Z APPLICATION 4519 Group 2 8 RAM back up 6 Key on wakeup control register K1 Table 2 8 9 shows the key on wakeup control register K1 Set the contents of this r
159. Time PROM version VDD 4 0 to 5 5 V VDD 3 0 to 5 5 V Note Definition of A D conversion clock ADCK On chip oscillator clock RING Division circuit Divided by 8 MRs3 MR2 K System clock STCK Internal clock generating circuit Divided by 2 divided by 3 Instruction clock On chip oscillator INSTCK Ceramic resonance XIN E al2d RC oscillation Quartz crystal CMCK oscillation CRCK CYCK Instruction clock INSTCK On chip oscillator clock RING O Operating condition map of A D conversion clock ADCK gt f ADCK kHz 334 245 123 Recommended operating operation 3 9 15 3 oA 0000 Voo V 2 2227 4 5 5 3 0 One Time PROM version Rev 1 00 Aug 06 2004 RENESAS 3 8 REJO9B0175 0100Z 4519 Group Table 3 1 8 A D converter characteristics Ta 20 C to 85 C unless otherwise noted Parameter Test conditions APPENDIX 3 1 Electrical characteristics Resolution Linearity error 2 7 8 0 V lt VDD 5 5 V One Time PROM version Mask ROM version 2 2 V lt VDD lt 2 7 V Differential non linearity error 2 2 3 0 V lt VDD lt 5 5 V One Time PROM version Zero transition voltage Mask ROM version DD 5 12 V DD 3 072 V DD 2 56 V One Time PROM vers
160. Timer 1 interrupt occurrence period measurement completed O Stop Timer Operation Timer 1 interrupt is disabled TW1A Timer control register W1 b2 Timer 1 stop Disable Interrupts Timer 1 interrupt is disabled Interrupt control register V1 b2 Timer 1 interrupt occurrence disabled TV1A G Stop Period Measurement circuit Period measurement circuit is stopped Timer control register W5 b2 Period measurement circuit stop TW5A amp Execute NOP Instruction NOP y O Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction y O Measurement data processing Timer 1 count value is read out Timer 1 gt Register A Register B TAB1 X it can be 0 or 1 PP instruction Fig 2 3 10 Period measurement of CNTRO pin input setting example 2 Rev 1 00 Aug 06 2004 RENESAS 2 46 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers Disable Interrupts Timer 1 interrupt and External 0 interrupt are temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI bO Interrupt control regi
161. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 2 NE S AS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gr
162. UCTION FUNCTION continued Mnemonic Function HARDWARE INDEX OF INSTRUCTION FUNCTION Mnemonic Function Page CLD RD c 2 S o o O bs 2 2 2 2 O ES 2 2 A E PU1 PU1 A A K0 KO lt A A K1 K1 lt A A K2 K2 lt A FRO A FR1 lt A FR2 lt A FR3 A 103 140 Serial I O operation 115 140 123 140 TABSI TSIAB SST B Sl7 Sl4 A Sla Slo SI7 Sla B Sls Slo A SIOF 0 Serial 1 O starting V23 0 SIOF 1 After skipping SIOF 0 V23 1 NOP A 41 J1 A 112 142 125 142 107 142 115 140 124 140 113 142 122 142 114 142 122 142 114 142 122 142 120 142 A D operation 120 142 120 142 121 142 Clock operation Ceramic resonator selected RC oscillator selected Quartz crystal oscillator selected RGo Ao A MR MR lt A Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 94 142 94 142 94 142 125 142 110 142 123 142 ENESAS In A D conversion mode B ADe AD6 A AD5 AD2 In comparator mode B AD7 AD4 A AD3 ADo A3 A2 AD1 ADo A1 Ao 0 AD7 ADa lt B AD3 ADo lt A ADF 0 A D conversion starting V21 0 ADF 21 After skipping ADF
163. Voltage drop detection circuit I 1 1 I Voltage drop detection circuit Fig 2 7 1 Voltage drop detection circuit VDD VRST reset release voltage gt s VRST reset voltage I 4 I I 1 I 1 1 Voltage drop detection circuit i Reset signa I i Microcomupter starts operation after on chip oscillator internal oscillator gt clock is counted 120 to 144 times Note Detection voltage hysteresis of voltage drop detection circuit is 0 2 V Typ Fig 2 7 2 Voltage drop detection circuit operation waveform example Table 2 7 1 Voltage drop detection circuit operation state At CPU operating At RAM back up Invalid Invalid Valid Valid Rev 1 00 Aug 06 2004 RENESAS 2 70 REJ09B0175 0100Z 4519 Group 2 8 RAM back up The 4519 Group has the RAM back up mode Figure 2 8 1 shows the state transition A Operation state Operation source clock f RING f XIN Stop Note 2 MR1 lt 0 B Operation state Operation source clock f RING f XIN Operating Note 3 MRo 0 Operation state Operation source clock f XIN RING Operating Note 5 Key on wakeup POF instruction execution Note 4 POF instruction execution Note 4 POF instruction RG0c 1 D Operation state Operation source clock f XIN f RING Stop SENS POF instruction Note 4 execution N
164. Vss and VDD using the thickest wire at the shortest distance against noise Rev 1 00 Aug 06 2004 RENESAS 2 14 REJ09B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 2 2 Interrupts The 4519 Group has eight interrupt sources external INTO INT1 timer 1 timer 2 timer 3 timer 4 A D and serial I O This section describes individual types of interrupts related registers application examples using interrupts and notes 2 2 1 Interrupt functions 1 External 0 interrupt INTO The interrupt request occurs by the change of input level of INTO pin The interrupt valid waveform can be selected by the bits 1 and 2 and the INTO pin input is controlled by the bit 3 of the interrupt control register 11 B External 0 interrupt INTO processing When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the external O interrupt occurs the interrupt processing is executed from address 0 in page 1 O When the interrupt is not used The interrupt is disabled and the SNZO instruction is valid when the bit O of register V1 is set to 0 2 External 1 interrupt INT1 The interrupt request occurs by the change of input level of INT1 pin The interrupt valid waveform can be selected by the bits 1 and 2 and the INT1 pin input is controlled by the bit 3 of the interrupt control register 12 B External 1 interrupt
165. a capacitor Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7RENESAS APPENDIX 3 4 Notes on noise 3 4 4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals 1 Keeping oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows O Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance Pis Mutual P d W Large E Xin current mE eel Fig 3 4 8 Wiring for a large current signal line 3 24 4519 Group 2 Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise O Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a program runaway
166. a bypass capacitor across the Vss pin and the VDD pin with the shortest possible wiring Use lines with a larger diameter than other signal lines for Vss line and VDD line Connect the power source wiring via a bypass capacitor to the Vss pin and the VDD pin Fig 3 4 6 Bypass capacitor across the Vss line and the VDD line 3 23 4519 Group 3 4 3 Wiring to analog input pins Connect an approximately 100 O to 1 kQ resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin Besides connect the capacitor to the Vss pin as close as possible Also connect the capacitor across the analog input pin and the VSS pin at equal length Reason Signals which is input in an analog input pin such as an A D converter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise into the microcomputer which causes noise to an analog input pin Note Microcomputer Analog input pin Note The resistor is used for dividing resistance with a thermistor Fig 3 4 7 Analog signal line and a resistor and
167. activated conditions Name Input pin Activated condition HARDWARE FUNCTION BLOCK OPERATIONS Valid waveform selection bit External 0 interrupt P30 INTO When the next waveform is input to P30 INTO pin Falling waveform H L Rising waveform L H Both rising and falling waveforms 11 112 External 1 interrupt P31 INT1 When the next waveform is input to P31 INT1 pin Falling waveform H L Rising waveform L H Both rising and falling waveforms e E i 112 One sided edge Note D EM detection circuit 1 P30 INTOO 0 Ny N External 0 X 4 tn 1 E i j interrupt Rising Both edges o Period measurement ion circui circuit input Timer 1 count start synchronous circuit pr Note 2 Level detection circuit X Note 3 Edge detection circuit E gt gt gt Skip decision SNZIO instruction e ETT H 122 One sided edge Note X os detection circuit i External 1 PavINTIO 0 gt 4 E H j interrupt a Lot Ay Lor p i Both edges iaa detection circuit A Rising Level detection circuit 77 Timer 3 count start synchronous circuit D gt Edge detection circuit gt Skip decision SNZI1 instruction Notes 1 This symbol represents a parasitic diode on the port 2 112 122 0 L level detected 112 122 1 H level dete
168. address 0 in page O In this case the P flag is 1 3 Cold start condition The CPU starts executing the program from address 0 in page 0 when reset pulse is input to RESET pin or reset by watchdog timer is performed or voltage drop detection circuit detects the voltage drop or SRST instruction is executed In this case the P flag is 0 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS HARDWARE FUNCTION BLOCK OPERATIONS Table 19 Functions and states retained at RAM back up Function RAM back up Program counter PC registers A B carry flag CY stack pointer SP Note 2 Contents of RAM Interrupt control registers V1 V2 Interrupt control registers 11 12 Selection of oscillation circuit Clock control register MR Timer 1 function Timer 2 function Timer 3 function Timer 4 function Watchdog timer function Timer control register PA W4 Timer control registers W1 to W3 W5 W6 Serial 1 O function Serial I O mode register J1 A D conversion function A D control registers Q1 to Q3 Voltage drop detection circuit Port level Key on wakeup control register KO to K2 Pull up control registers PUO PU1 Port output direction registers FRO to FR3 External 0 interrupt request flag EXFO External 1 interrupt request flag EXF1 Timer 1 interrupt request flag T1F Timer 2 interrupt request flag T2F Timer 3 interrupt request flag T3F Timer 4 interrupt request flag T4F
169. al for the main clock f XIN is used connect the clock source to XIN pin and XOUT pin open In program after the CMCK instruction is executed set main clock f XIN oscillation start to be enabled MR1 0 For this product when RAM back up mode and main clock f XiN stop MR1 1 XIN pin is fixed to H in order to avoid the through current by floating of internal logic The XIN pin is fixed to H until main clock f XIN oscillation start to be valid MR120 by the CMCK instruction from reset state Accordingly when an external clock is used connect a 1 kQ or more resistor to XIN pin in series to limit of current by competitive signal Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board Accordingly consult the oscillator manufacturer for values of each part connected the oscillator Rev 1 00 Aug 06 2004 RENESAS 2 81 REJ09B0175 0100Z CHAPTER 3 APPENDIX 3 1 Electrical characteristics 3 2 Typical characteristics 3 3 List of precautions 3 4 Notes on noise 3 5 Package outline APPENDIX 4519 Group 3 1 Electrical characteristics 3 1 Electrical characteristics 3 1 1 Absolute maximum ratings Table 3 1 1 Absolute maximum ratings Parameter Conditions Ratings Supply voltage 0 3 to 6 5 Input voltage 0 3 to VDD 0 3 PO P1 P2 P3 P4 P5 P6 Do D7 RESET Xin VDCE Input voltage Sck SIN CNTRO CNTR1 I
170. al state at reset Figure 2 6 3 and Figure 2 6 4 show the internal state at reset The contents of timers registers flags and RAM other than shown in Figure 2 6 3 and Figure 2 6 4 are undefined so that set them to initial values Program counter PC 0 101010 Address 0 in page 0 is set to program counter Interrupt enable flag INTE Interrupt disabled Power down flag P External 0 interrupt request flag EXFO External 1 interrupt request flag EXF1 Interrupt control register V1 Interrupt disabled Interrupt control register V2 Interrupt disabled Interrupt control register 11 Interrupt control register 12 Interrupt control register I3 Timer 1 interrupt request flag T1F Timer 2 interrupt request flag T2F Timer 3 interrupt request flag T3F Timer 4 interrupt request flag T4F Watchdog timer flags WDF1 WDF2 Watchdog timer enable flag WEF Timer control register PA Prescaler stopped Timer control register W1 Timer 1 stopped Timer control register W2 Timer 2 stopped Timer control register W3 Timer 3 stopped Timer control register W4 Timer 4 stopped Timer control register W5 Timer control register W6 Period measurement circuit Clock control register MR Serial I O transmit receive completion flag SIOF Serial I O mode register J1 O External clock selected erial I O port not selected
171. am counter Make sure that the PC does not specify after the last page of the built in ROM Power on reset When the built in power on reset circuit is used the time for the supply voltage to rise from O V to the value of supply voltage or more must be set to 100 us or less If the rising time exceeds 100 us connect a capacitor between the RESET pin and Vss at the shortest distance and input L level to RESET pin until the value of supply voltage reaches the minimum operating voltage Clock control 7tENESAS Execute the main clock f XIN selection instruction CMCK CRCK or CYCK instruction in the initial setting routine of pro gram executing it in address 0 in page 0 is recommended The oscillation circuit by the CMCK CRCK or CYCK instruction can be selected only at once The oscillation circuit correspond ing to the first executed one of these instructions is valid The CMCK CRCK and CYCK instructions can be used only to select main clock f XIN In this time the start of oscillation and the switch of system clock are not performed When the CMCK CRCK and CYCK instructions are never ex ecuted main clock f XIN cannot be used and system can be operated only by on chip oscillator The no operated clock source f RING or f XIN cannot be used for the system clock Also the clock source f RING or f XIN selected for the system clock cannot be stopped On chip oscil
172. an external clock is not stopped when serial transfer is completed However the SIOF flag is set to 1 when the clock is counted 8 times after executing the SST in struction Be sure to set the initial level of the external clock to H Rev 1 00 Aug 06 2004 1 57 REJO9B0175 0100Z RENESAS HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS RESET FUNCTION System reset is performed by applying L level to RESET pin for 1 machine cycle or more when the following condition is satisfied the value of supply voltage is the minimum value or more of the recommended operating conditions Then when H level is applied to RESET pin software starts from address 0 in page 0 On chip oscillator internal oscillator T Program starts is counted 120 to 144 times address 0 in page 0 Note The number of clock cycles depends on the internal state of the microcomputer when reset is performed Fig 44 Reset release timing Reset input U On chip oscillator internal oscillator is 1 machine cycle or more counted 120 to 144 times 4 y Program starts address 0 in page 0 Note Keep the value of supply voltage to the minimum value or more of the recommended operating conditions Fig 45 RESET pin input waveform and reset operation Rev 1 00 Aug 06 2004 RENESAS 1 58 REJO9B0175 0100Z 4519 Group 1 Power on reset Reset can be automaticall
173. anted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document b
174. arily disabled Interrupt enable flag INTE 0 All interrupts disabled DI Interrupt control register V1 b2 Timer 1 interrupt occurrence disabled TV1A Q Stop Timer and Prescaler Operation Timer 1 and prescaler are temporarily stopped TW1A Timer 1 count source is selected b3 Timer 1 count auto stop circuit not selected b3 b2 Timer 1 stop Timer control register W1 0 b1 bO Prescaler output ORCLK selected for Timer 1 count source Timer control register PA Prescaler stop TPAA Set Timer and Prescaler Values Timer 1 and prescaler count times are set The formula is shown A below Timer 1 reload register R1 F916 Timer count value 249 set T1AB Prescaler reload register RPS OF16 Prescaler count value 15 set TPSAB amp Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction O Start Timer and Prescaler Operation Timer 1 and prescaler temporarily stopped are restarted bU Timer control register W1 1 b2 Timer 1 operation start TW1A bU Timer control register PA 1 Prescaler operation start TPAA O Enab
175. art connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board Accordingly consult the oscillator manufacturer for values of each part connected the oscillator 3 3 11 Electric characteristic differences between Mask ROM and One Time PROM version MCU There are differences in electric characteristics operation margin noise immunity and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version please perform sufficient evaluations for the commercial samples of the Mask ROM version 3 3 12 Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions the microcomputer does not operate normally and may perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation Rev 1 00 Aug 06 2004 RENESAS 3 20 REJO9B0175 0100Z 4519 Group 3 4 Notes on noise Countermeasures against noise are described below The following co
176. aveform of CNTRO input The count edge is selected by the bit 2 of register W6 When the CNTR1 input is selected for timer 3 count source timer 3 counts the rising or falling waveform of CNTR1 input The count edge is selected by the bit 3 of register W6 12 PWM output function D7 CNTR1 timer 3 timer 4 When bit 3 of register W4 is set to 1 timer 4 reloads data from re load register RAL and R4H alternately each underflow Timer 4 generates the PWM signal PWMOUT of the L interval set as reload register R4L and the H interval set as reload regis ter RAH The PWM signal PWMOUT is output from CNTR1 pin When bit 2 of register W4 is set to 1 at this time the interval PWM signal H interval set to reload register R4H for the counter of timer 4 is extended for a half period of count source In this case when a value set in reload register R4H is n timer 4 divides the count source signal by n 1 5 n 1 to 255 When this function is used set 1 or more to reload register R4H When bit 1 of register W6 is set to 1 the PWM signal output to CNTR1 pin is switched to valid invalid each timer 3 underflow However when timer 3 is stopped bit 2 of register W3 is cleared to 0 this function is canceled Even when bit 1 of a register W4 is cleared to 0 in the H interval of PWM signal timer 4 does not stop until it next timer 4 underflow At CNTR1 output vaild if a timing of timer 4 underflo
177. bit Operating 31 W30 Count source W31 Timer 3 count source selection 0 0 PWM signal PWMOUT bits O 1 Prescaler output ORCLK W30 1 O Timer 2 underflow signal T2UDF CNTR1 input Notes 1 R represents read enabled and W represents write enabled 2 This function is valid only when the timer 3 count start synchronous circuit is selected 120 1 9 Timer control register W4 Table 2 3 9 shows the timer control register W4 Set the contents of this register through register A with the TW4A instruction In addition the TAWA instruction can be used to transfer the contents of register W4 to register A at reset 00002 at RAM back up 00002 0 D7 1 0 CNTR1 input CNTR1 I O D7 input PWM signal H interval expansion function invalid PWM signal H interval expansion function valid Stop state retained Operating XIN input Prescaler output ORCLK divided by 2 Table 2 3 9 Timer control register W4 Timer control register W4 D7 CNTR1 pin function selection bit PWM signal H interval expansion function control bit W43 W42 W41 Timer 4 control bit Timer 4 count source selection bit W40 k l Ol k l Ol kl Ol k Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 35 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers 10 Timer control register W5 Table 2 3
178. by skip decision Eight independent l O ports Ports De and D7 are also used as CNTRO and CNTR1 respectively The output structure is switched by software P00 P03 1 0 4 bit I O port a pull up function a key on wakeup function and output structure can be switched by software P10 P13 1 0 4 bit I O port a pull up function a key on wakeup function and output structure can be switched by software P20 P22 y o 3 bit I O port ports P20 P21 and P22 are also used as Sck SOUT and SIN respectively P30 P33 1 0 4 bit I O port ports P30 and P31 are also used as INTO and INT1 respectively P40 P43 1 0 4 bit I O port ports P40 P43 are also used as AIN4 AIN7 respectively P50 P53 1 0 4 bit I O port the output structure is switched by software P60 P63 1 0 4 bit I O port ports P60 P63 are also used as AINO AIN3 respectively Timer 1 8 bit timer with a reload register is also used as an event counter Also this is equipped with a period pulse width measurement function Timer 2 8 bit timer with a reload register Timer 3 8 bit timer with a reload register is also used as an event counter Timer 4 8 bit timer with two reload registers and PWM output function A D converter 10 bit wide X 8 ch This is equipped with an 8 bit comparator function Serial I O 8 bit X 1 Interrupt Sources 8 two for exter
179. can be performed by using the signal rising waveform input from CNTRO pin as the event Specifications The low frequency pulse from external as the timer 1 count source is input to CNTRO pin and the timer 1 interrupt occurs every 100 counts Figure 2 3 6 shows the setting example of CNTRO input Rev 1 00 Aug 06 2004 RENESAS 2 37 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers 4 Timer operation timer start by external input Outline The constant period can be measured by external input Specifications Timer 3 operates by INT1 input as a trigger and an interrupt occurs after 1 ms Figure 2 3 7 shows the setting example of timer start 5 CNTR1 output control PWM output control Outline The PWM output from CNTR1 pin can be performed by timer 4 Specifications Timer 4 divides the main clock frequency f XIN 4 0 MHz and the waveform which H period is 0 875 us of the 1 875 us PWM periods is output from CNTR1 pin Figure 2 3 2 shows the timer 4 operation and Figure 2 3 8 shows the setting example of PWM output control CNTR1 output valid W43 1 PWM signal H interval extension function valid W42 1 Note Reload register RAL 0316 Reload register R4H 0216 Timer 4 count source l Timer 4 count value Reload register Timer 4 underflow signal L PWM signal 3 5 clock 3 5 clock 1 I 1 Timer 4 start 148 PWM period 7 5 clock gt 48
180. cessive comparison register AD Register AD stores the A D conversion result of an analog input in 10 bit digital data format The contents of the high order 8 bits of this register can be stored in register B and register A with the TABAD instruction The contents of the low order 2 bits of this reg ister can be stored into the high order 2 bits of register A with the TALA instruction However do not execute these instructions dur ing A D conversion When the contents of register AD is n the logic value of the com parison voltage Vret generated from the built in D A converter can be obtained with the reference voltage VDD by the following for mula Logic value of comparison voltage Vret VDD 1024 X Vref n The value of register AD n 0 to 1023 HARDWARE FUNCTION BLOCK OPERATIONS 4 A D conversion completion flag ADF A D conversion completion flag ADF is set to 1 when A D con version completes The state of ADF flag can be examined with the skip instruction SNZAD Use the interrupt control register V2 to select the interrupt or the skip instruction The ADF flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction 5 A D conversion start instruction ADST A D conversion starts when the ADST instruction is executed The conversion result is automatically stored in the register AD 6 Operation description A D conversion is started with th
181. changed XXX02 The SNZO instruction is valid 1XXX2 Control of INTO pin input is changed The SNZO instruction is executed EXFO flag cleared The SNZO instruction is executed EXFO flag cleared X these bits are not used here X these bits are not used here Fig 18 External 0 interrupt program example 1 Fig 20 External 0 interrupt program example 3 Note 2 on bit 3 of register 11 When the bit 3 of register 11 is cleared to 0 the RAM back up mode is selected and the input of INTO pin is disabled be careful about the following notes When the input of INTO pin is disabled register 113 0 set the key on wakeup function to be invalid register K20 0 before System enters to the RAM back up mode refer to Figure 190 LA XXX02 TK2A Input of INTO key on wakeup invalid DI EPOF POF RAM back up X these bits are not used here Fig 19 External 0 interrupt program example 2 Rev 1 00 Aug 06 2004 RENESAS 1 29 REJ09B0175 0100Z HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS 5 Notes on External 1 interrupt Note on bit 2 of register 12 O Note 1 on bit 3 of register 12 When the interrupt valid waveform of the P31 INT1 pin is When the input of the INT1 pin is controlled with the bit 3 of reg changed with the bit 2 of register I2 in software be careful about ister I2 in software be careful about the following notes the following notes Depending on
182. circuit stopped On chip oscillator operating External clock selected serial I O port not selected X represents undefined 1 60 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS Port output structure control register FRO Port output structure control register FR1 Port output structure control register FR2 Port output structure control register FR3 Carry flag CY Register A Register B Register D Register E Register X Register Y Register Z Stack pointer SP Operation source clock Ceramic resonator circuit RC oscillation circuit Quartz crystal oscillation circuit X represents undefined Fig 48 Internal state at reset 2 Rev 1 00 Aug 06 2004 RENESAS 1 61 REJO9B0175 0100Z HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS VOLTAGE DROP DETECTION CIRCUIT The built in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value p Voltage drop detection circuit Reset signal Voltage drop detection circuit Fig 49 Voltage drop detection reset circuit VDD VRST reset release voltage gt VRST reset voltage im min r mn im Voltage drop detection circuit Reset signa Microcomupter starts operation after
183. ck pointer 3 bits Carry flag Prescaler reload register 8 bits Timer 1 reload register 8 bits Timer 2 reload register 8 bits Timer 3 reload register 8 bits Timer 4 reload register 8 bits Timer 4 reload register 8 bits CERES DD 9 3 p m Prescaler Timer 1 Timer 2 Timer 3 Timer 4 Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A D conversion completion flag Serial I O transmit receive completion flag Port D 8 bits Port PO 4 bits Port P1 4 bits Port P2 3 bits Port P3 4 bits Port P4 4 bits Port P5 4 bits Port P6 4 bits Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A same for others Direction of data movement Data exchange between a register and memory Decision of state shown before Contents of registers and memories Negate Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address ae a5 a4 a3 a2 a1 a0 Label indicating address ae a5 a4 a3 a2 a1 ao in page p5 p4 p3 p2 p1 po Hex C Hex number x Note Some instructions of t
184. continuously after the EPOF instruction system enters the RAM back up state Note that system cannot enter the RAM back up state when executing only the POF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction continuously Rev 1 00 Aug 06 2004 RENESAS 3 14 REJO9B0175 0100Z APPENDIX 4519 Group 3 3 List of precautions 3 3 5 Notes on timer 1 2 3 4 5 6 7 8 9 Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data Stop counting and then execute the TPSAB instruction to set prescaler data Count source Stop timer 1 2 3 4 or LC counting to change its count source Reading the count values Stop timer 1 2 3 or 4 counting and then execute the TAB1 TAB2 TAB3 or TABA instruction to read its data Writing to the timer Stop timer 1 2 3 4 or LC counting and then execute the T1AB T2AB T3AB T4AB or TLCA instruction to write its data Writing to reload register R1 reload register R3 and reload register RAH When writing data to reload register R1 while timer 1 is operating respectively avoid a timing when timer 1 underflows When writing data to reload register R3 while timer 3 is operating respectively avoid a timing when timer 3 underflows When writing data to reload register R4H while timer 4 is operating respectively avoid a timing when timer 4 underflows
185. cted 3 112 122 0 Falling edge detected 112 122 1 Rising edge detected Fig 17 External interrupt circuit structure Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS 1 26 4519 Group 1 External 0 interrupt request flag EXFO External 0 interrupt request flag EXFO is set to 1 when a valid waveform is input to P30 INTO pin The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock Refer to Figure 16 The state of EXFO flag can be examined with the skip instruction SNZO Use the interrupt control register V1 to select the interrupt or the skip instruction The EXFO flag is cleared to 0 when an in terrupt occurs or when the next instruction is skipped with the skip instruction External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30 INTO pin The valid waveform can be selected from rising waveform falling waveform or both rising and falling waveforms An example of how to use the external 0 interrupt is as follows Set the bit 3 of register 11 to 1 for the INTO pin to be in the in put enabled state Select the valid waveform with the bits 1 and 2 of register I1 Clear the EXFO flag to 0 with the SNZO instruction Set the NOP instruction for the case when a skip is performed with the SNZO instruction Set both the external 0 inte
186. cuit in order to keep the voltage within the rated range as shown the Figure 2 4 4 In addition test the application products sufficiently About 1kQ Sensor j Apply the voltage withiin the specifications to an analog input pin Fig 2 4 4 Analog input external circuit example 2 Fig 2 4 3 Analog input external circuit example 1 3 Notes for the use of A D conversion 2 Do not change the operating mode of the A D converter by bit 3 of register Q1 during A D conversion A D conversion mode and comparator mode 4 Notes for the use of A D conversion 3 When the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode with bit 3 of register Q1 in a program be careful about the following notes Clear bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to the A D conversion mode refer to Figure 2 4 50 The A D conversion completion flag ADF may be set when the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode Accordingly set a value to bit 3 of register Q1 and execute the SNZAD instruction to clear the ADF flag to 0 Clear bit 2 of register V2 to 0 y Change of the operating mode of the A D converter from the comparator mode to the A D conversion mode Clear the ADF flag to 0 with the SNZAD instruction y Execute the NOP instruction for the case when a skip is
187. cute the SNZO instruction to clear the EXFO flag to Q after executing at least one instruction Depending on the input state of P30 INTO pin the external interrupt request flag EXFO may be set to 1 when the bit 2 of register I1 is changed Setting of INTO pin input control Set a value to the bit 3 of register 11 and execute the SNZO instruction to clear the EXFO flag to Q after executing at least one instruction Depending on the input state of P30 INTO pin the external interrupt request flag EXFO may be set to 1 when the bit 3 of register 11 is changed Setting of INT1 interrupt valid waveform Set a value to the bit 2 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction Depending on the input state of P31 INT1 pin the external interrupt request flag EXF1 may be set to 1 when the bit 2 of register 12 is changed Setting of INT1 pin input control Set a value to the bit 3 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag to Q after executing at least one instruction Depending on the input state of P31 INT1 pin the external interrupt request flag EXF1 may be set to 1 when the bit 3 of register 12 is changed Multiple interrupts Multiple interrupts cannot be used in the 4519 Group Notes on interrupt processing When the interrupt occurs at the same time the interrupt enable flag INTE is cleared to 0
188. d R W PUT P13 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PU12 P12 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PU P11 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PULO P10 pin 0 Pull up transistor OFF pull up transistor control bit Pull up transistor ON Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 8 REJ09B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 7 Port output structure control register FRO Table 2 1 7 shows the port output structure control register FRO Set the contents of this register through register A with the TFROA instruction Table 2 1 7 Port output structure control register FRO at reset 00002 at RAM back up state retained Port output structure control register FRO z FRO3 Ports P12 P13 0 N channel open drain output output structure selection bit 1 CMOS output FRO Ports P10 P11 0 N channel open drain output output structure selection bit 1 CMOS output FRO Ports P02 P03 0 N channel open drain output output structure selection bit 1 CMOS output FROG Ports P01 POO 0 N channel open drain output output structure selection bit 1 CMOS output Note W represents write enabled 8 Port output structure control register FR1 Table 2 1 8 shows the port output st
189. d comparison result x8 8th comparison result gt lt A 10th comparison result Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS 1 49 4519 Group 7 A D conversion timing chart Figure 36 shows the A D conversion timing chart HARDWARE FUNCTION BLOCK OPERATIONS ADST instruction 88 2 machine cycles 10 f ADCK e A D conversion completion flag ADF DAC operation signal Fig 36 A D conversion timing chart 8 How to use A D conversion How to use A D conversion is explained using as example in which the analog input from P60 AINo pin is A D converted and the high order 4 bits of the converted data are stored in address M Z X Y 0 O 0 the middle order 4 bits in address M Z X Y 0 O 1 and the low order 2 bits in address M Z X Y 0 0 2 of RAM The A D interrupt is not used in this example Instruction clock 6 is selected as the A D converter operation clock Select the Alno pin function with the bit 0 of the register Q2 Se lect the AINo pin function and A D conversion mode with the register Q1 Also the instruction clock divided by 6 is selected with the register Q3 refer to Figure 37 O Execute the ADST instruction and start A D conversion G Examine the state of ADF flag with the SNZAD instruction to de termine the end of A D conversion O Transfer the low order 2 bits of converted data to the high order 2 bits of register A TALA instruction O Transfer the
190. e 12 5 V at the One Time PROM version Connect the CNVss VPP pin to Vss through an approximate 5 kQ resistor which is connected to the CNVss VPP pin at the shortest distance 3 Multifunction e Be careful that the output of ports P30 and P31 can be used even when INTO and INT1 pins are selected e Be careful that the input of ports P20 P22 can be used even when SIN SOUT and SCk pins are selected Be careful that the input output of port De can be used even when input of CNTRO pin is selected Be careful that the input of port De can be used even when output of CNTRO pin is selected e Be careful that the input output of port D7 can be used even when input of CNTR1 pin is selected e Be careful that the input of port D7 can be used even when output of CNTR1 pin is selected 4 Connection of unused pins Table 2 1 13 shows the connections of unused pins 5 SD RD SZD instructions When the SD RD or SZD instructions is used do not set 10002 or more to register Y 6 Port P30 INTO pin When the RAM back up mode is used by clearing the bit 3 of register 11 to 0 and setting the input of INTO pin to be disabled be careful about the following note When the input of INTO pin is disabled register 113 0 clear bit O of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode 7 Port P31 INT1 pin When the RAM back up mode is used by clearing the bit 3 of register I2 to 0 and setting
191. e 3 10 3 2 Typical characteristics esasan crec 3 11 3 3 List of precautions eeeeeesseeseeeeeeeeee nennen eene nnnnnr nan nn nnnm hann in nnns inset tnr nan nn nnne nnn 3 12 mcos a Ce a A T A E E E E E A T A E E 3 12 3 3 2 Stack registers SKS eiie ettet tetecee oer tie eaaa E TA NSE aS 3 12 3 9 9 Notes on VO POircaroaita lios herir data il fetes 3 12 3 3 4 Notes on aT e uec eret aaa 3 14 3 3 5 NOLES On RST a tod 3 15 3 3 5 Notes on A D CONVEISIOM sse tenero catarata 3 17 3 3 7 Notes on serial VO ied icti dete nudes enden a ER 3 18 3 3 8 NOLES JON Odia AAA E Fee A A EA 3 19 3 9 9 Notes on RAM back up xu eco lle avus cd Et ode dx RR n e eu d 3 19 3 3 10 Notes on clock control I 3 20 3 3 11 Electric characteristic differences between Mask ROM and One Time PROM version MCU 3 20 3 3 12 Note on Power Source Voltage sse nnne nnne 3 20 3 4 Notes oh nols nue neret as 3 21 3 4 1 Shortest wirlng length iier ce Eine iii 3 21 3 4 2 Connection of bypass capacitor across VSS line and VDD line 3 23 3 4 3 Wiring to analog input pins oomoccccccononcccccnononcnnnonnnonnnnnnann eene nnne nnns 3 24 3 4 4 Oscillator COIIGeFTIS eed eere a rr gh he a ee e ac ua 3 24 3 4 5 Setup for VO ports sessssssissssesessesesee nennen nnt n anni narran sette tenias asta nnn nn 3 25 3 4 6 Providing of watchdog timer function by software sse sese eee ee eee 3 25 3 95 eC dee
192. e Mi Rising of clock So M7 Me Falling of clock ww n annnm Fig 2 5 3 Serial I O register state when transfer Rev 1 00 Aug 06 2004 RENESAS 2 60 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO Master mo X M X pe X MS X Ma X MS A Mo OM R so X si A se X S Ms X_ss ss XS SST instruction Control signal aT Sour sr AS As A se SA S Ass Aso MS Mo Mr Contents of master serial I O register So S7 Contents of slave serial I O register Rising of Sck Serial input Falling of Sck Serial output M7 S7 Contents of previous master slave MSB Fig 2 5 4 Serial I O transfer timing Rev 1 00 Aug 06 2004 RENESAS 2 61 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO The full duplex communication of master and slave is described using the connection example shown in Figure 2 5 2 1 Transmit receive operation of master O Set the transmit data to the serial I O register SI with the TSIAB instruction When the TSIAB instruction is executed the contents of register A are transferred to the low order 4 bits of register SI and the contents of register B are transferred to the high order 4 bits of register SI Check whether the microcomputer on the slave side is ready to transmit receive or not In the connection example in Figure 2 5 2 check that the input level of control signal is L level Start serial transmit receive with the SST instruction When th
193. e 8 bit timer with a reload register TIMET 2 nnani 8 bit timer with a reload register A 8 bit timer with a reload register Tie iran 8 bit timer with two reload registers Part number ROM PROM size X 10 bits APPLICATION Electrical household appliance consumer electronic products of fice automation equipment etc RAM size X 4 bits Package ROM type M34519M6 XXXFP 6144 words 384 words 42P2R A Mask ROM M34519M8 XXXFP 8192 words 384 words 42P2R A Mask ROM M34519E8FP Note Note Shipped in blank PIN CONFIGURATION De CNTRo D7 CNTR1 P5o P51 P52 P53 P20 Sck P21 SouT P22 Sin 8192 words 384 words d3836 1SvElN AJXXXXN6 LSVEN RESET CNVss Xour Vss WT A dA AT O EHEBHBHEHEHRHEHEHEHBEHAE 42P2R A lt gt Pie lt gt P11 lt gt Pto lt P03 lt P02 lt gt P01 lt P00 lt gt P43 AIN7 lt gt P42 AiN6 lt gt P41 Aln5 lt gt P4o0 Ain4 lt gt P63 AiN3 lt P62 Ain2 lt gt P61 AIN1 lt gt P6o AiNo lt gt P33 lt gt P32 lt gt P31 1NT1 lt gt P30 INTO lt VDCE VDD OUTLINE 42P2R A Pin configuratio
194. e A D conversion start instruction ADST The internal operation during A D conversion is as follows When the A D conversion starts the register AD is cleared to 00016 Next the topmost bit of the register AD is set to 1 and the com parison voltage Vret is compared with the analog input voltage VIN When the comparison result is Vref lt VIN the topmost bit of the register AD remains set to 1 When the comparison result is Vref VIN it is cleared to 0 The 4519 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value A D con version stops after 2 machine cycles A D conversion clock 31 us when f XIN 6 0 MHz in XIN through mode f ADCK f INSTCK 6 from the start and the conversion result is stored in the register AD An A D interrupt activated condition is satisfied and the ADF flag is set to 1 as soon as A D conversion completes Figure 36 Table 13 Change of successive comparison register AD during A D conversion At starting conversion Change of successive comparison register AD Comparison voltage Vref value 1st comparison 2nd comparison gt 1 3rd comparison 1 2 After 10th comparison A D conversion result completes 1 2 3 x1 1st comparison result x3 3rd comparison result x9 9th comparison result 2 2n
195. e SST instruction is executed the serial I O transmit receive completion flag SIOF is cleared to 0 The transmit data is output from the SOUT pin synchronously with the falling edges of the shift clock The transmit data is output bit by bit beginning with the LSB of register SI Each time one bit is output the contents of register SI is shifted one bit position toward the LSB O Also the receive data is input from the SIN pin synchronously with the rising edges of the shift clock The receive data is input bit by bit to the MSB of register SI A serial I O interrupt request occurs when the transmit receive data is completed and the SIOF flag is set to 1 O The receive data is taken in within the serial I O interrupt service routine or the data is taken in after examining the completion of the transmit receive operation with the SNZSI instruction without using an interrupt Also the SIOF flag is cleared to 0 when an interrupt occurs or the SNZSI instruction is executed Notes 1 Repeat steps O through to transmit receive multiple data in succession 2 For the program on the master side start to transmit the next data at the next timing control signal turns L Do not start to transmit the next data during the previous data transfer control signal L Rev 1 00 Aug 06 2004 RENESAS 2 62 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO 2 Transmit receive operation of slave O Set the t
196. e high order 4 bits of serial I O register Sl and transfers the con tents of register A to the low order 4 bits of serial I O register SI Clears 0 to SIOF flag and starts serial I O Skips the next instruction when the contents of bit 3 V23 of interrupt control register V2 is O and contents of SIOF flag is 1 After skipping clears 0 to SIOF flag Transfers the contents of serial I O control register J1 to register A Transfers the contents of register A to serial I O control register J1 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Selects the ceramic resonator for main clock f XIN Selects the RC oscillation circuit for main clock f XIN Selects the quartz crystal oscillation circuit for main clock f XIN Transfers the contents of clock control regiser RG to register A Transfers the contents of clock control regiser MR to register A Transfers the contents of register A to clock control register MR RENESAS 1 143 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code S5 15 xw 0 0 Mnemonic E S Function Hexadecimal 2 TES D Ds D7 De Ds D4 Ds D2 D Do 0 bou 53 50 instruction notation z z TABAD 1 0 O 1 1 1 1 0 0 1 279 1 1 Q13 0 B AD9 AD6 A AD5 AD2 Q13 1 B AD7 ADa A AD3 ADo TALA 1 001 001 0 0 1 249 1 1 A3 A2 AD1 ADo A1 Ao O T
197. e j in the immediate field and stores the result in register X XAMD j eXchange Accumulator and Memory data and Decrement register Y and skip Instruction Dg Do Number of Number of Flag CY Skip condition code tlolJijililiaii li lili 2 j words cycles A m 1 1 Y 15 ee Grouping RAM to register transfer Operation A gt M DP Description After exchanging the contents of M DP X X EXOR j with the contents of register A an exclusive j 0to 15 OR operation is performed between regis Y e Y 1 ter X and the value j in the immediate field and stores the result in register X Subtracts 1 from the contents of register Y As a result of subtraction when the con tents of register Y is 15 the next instruction is skipped When the contents of register Y is not 15 the next instruction is executed Rev 1 00 Aug 06 2004 RENESAS 1 128 REJO9B0175 0100Z HARDWARE 4519 Group MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued XAMI j eXchange Accumulator and Memory data and Increment register Y and skip Instruction Dg Do Number of Number of Flag CY Skip condition code tlolilialalolj li lj di l 2 elj a words cycles 1 1 Y 20 Operation A lt gt M DP Grouping __RAM to register transfer Description After excha
198. e next instruction V20 1 SNZT3 NOD when timer 3 interrupt request flag T3F is V20 bit O of interrupt control register V2 1 After skipping clears 0 to the T3F flag When the T3F flag is 0 executes the next instruction When V20 1 This instruction is equiva lent to the NOP instruction Rev 1 00 Aug 06 2004 RENESAS 1 106 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued SNZTA Skip if Non Zero condition of Timer 4 inerrupt request flag Instruction D9 Do Number of Number of Flag CY Skip condition code 1 oe s o o o o o s ET S eyes 1 1 V21 0 T4F 1 Operation V21 0 T4F 21 Grouping Timer operation After skipping T4F 0 Description When V21 0 Skips the next instruction V21 1 SNZT4 NOP when timer 4 interrupt request flag T4F is V21 bit 1 of interrupt control register V2 1 After skipping clears 0 to the T4F flag When the T4F flag is 0 executes the next instruction When V21 1 This instruction is equiva lent to the NOP instruction SRST System ReSeT Instruction D9 Do Number of N
199. e time PROM version and then switching to use of the Mask ROM ver sion please perform sufficient evaluations for the commercial samples of the Mask ROM version amp Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions the microcomputer does not operate normally and may perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation Rev 1 00 Aug 06 2004 RENESAS 1 77 REJO9B0175 0100Z HARDWARE 4519 Group CONTROL REGISTERS CONTROL REGISTERS R W Interrupt control register V1 at reset 00002 at RAM back up 00002 TAVA TVAA Interrupt disabled SNZT2 instruction is valid Interrupt enabled SNZT2 instruction is invalid Interrupt disabled SNZT1 instruction is valid Interrupt enabled SNZT1 instruction is invalid Interrupt disabled SNZ1 instruction is valid Interrupt enabled SNZ1 instruction is invalid Interrupt disabled SNZO instruction is valid Interrupt enabled SNZO instruction is invalid Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 inte
200. e used to transfer the contents of register 11 to register A Table 2 8 4 Interrupt control register I1 at reset 00002 at RAM back up state retained Interrupt control register 11 R W 13 INTO pin input control bit Note 2 _ 10 Pin Input disabled 1 INTO pin input enabled interval Wavelolm for INTO 0 Falling waveform L level L level is recognized with 112 pin return level selection bit pra Presion Note 2 4 Rising waveform H level H level is recognized with the SNZIO instruction T INTO pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected to INTO pin Timer 1 count start 0 Timer 1 count start synchronous circuit not selected synchronous circuit selection bit 1 Timer 1 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 112 and l13 are changed the external interrupt request flag EXFO may be set to 1 Accordingly clear EXFO flag with the SNZO instruction when the bit 0 V10 of register V1 to 0 In this time set the NOP instruction after the SNZO instruction for the case when a skip is performed with the SNZO instruction 3 When setting the RAM back up 111 110 are not used 2 Interrupt control register 12 Table 2 8 5 shows the interrupt control register 12 Set the contents of this register through register A with the TI2A instr
201. e watchdog timer and the microcomputer can be reset to normal operation This is equal to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the following example to reset a microcomputer to normal operation the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is repeated multiple times in a single main routine processing 13 NE SAS 3 25 APPENDIX 4519 Group 3 4 Notes on noise The main routine Assigns a single word of RAM to a software watchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition Counts of interrupt processing executed in N 1 gt each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin e Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set e Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents do not change after
202. ecifying RAM file group Fig 8 Data pointer DP structure Specifying bit position Set D3 De D Do OO EO Port D output latch COUE Register Y 4 Fig 9 SD instruction execution example 4519 Group PROGRAM MEMORY ROM The program memory is a mask ROM 1 word of ROM is composed of 10 bits ROM is separated every 128 words by the unit of page addresses 0 to 127 Table 1 shows the ROM size and pages Fig ure 10 shows the ROM map of M34519M8 E8 Table 1 ROM size and pages ROM PROM size X 10 bits 6144 words 8192 words Part number M34519M6 M34519M8 E8 A part of page 1 addresses 008016 to OOFF16 is reserved for in terrupt addresses Figure 11 When an interrupt occurs the address interrupt address corresponding to each interrupt is set in the program counter and the instruction at the interrupt address is executed When using an interrupt service routine write the in struction generating the branch to that routine at an interrupt address Page 2 addresses 010016 to 017F16 is the special page for sub routine calls Subroutines written in this page can be called from any page with the 1 word instruction BM Subroutines extending from page 2 to another page can also be called with the BM in struction when it starts on page 2 ROM pattern bits 9 to 0 of all addresses can be used as data ar eas with the TABP p instruction Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS
203. ect to Vss N channel open drain is selected for the output structure The pull up function is not selected The key on wakeup function is not selected P20 SCK Open ScK pin is not selected Connect to Vss P21 SOUT Open Connect to Vss P22 SIN Open SIN pin is not selected Connect to Vss P30 INTO Open 0 is set to output latch Connect to Vss P31 INT1 Open 0 is set to output latch Connect to Vss P32 P33 Open Connect to Vss P40 AIN4 P43 AIN7 Open Connect to Vss P50o P53 Open Connect to Vss N channel open drain is selected for the output structure P60 AINo P63 AIN3 Open Notes 1 After system is released from reset the internal oscillation on chip oscillator is selected for system clock RGo 0 MRo 1 Connect to Vss 2 When the CRCK instruction is executed the RC oscillation circuit becomes valid Be careful that the swich of system clock is not executed at oscilla tion start only by the CRCK instruction execution In order to start oscillation setting the main clock f XIN oscillation to be valid MR1 0 is required If necessary generate the oscillation stabilizing wait time by software Also when the main clock f XIN is selected as system clock set the main clock f XIN oscillation MR1 0 to be valid and select main clock f XIN MRo 0 Be careful that
204. ed SNZT4 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T4F insert the NOP instruction after the SNZTA instruction O Start Timer Operation and Prescaler Operation Timer 4 and prescaler temporarily stopped are restarted bO Timer control register W4 1 b1 Timer 4 operation start TW4A bO Timer control register PA 1 Prescaler start TPAA Enable Interrupts The Timer 4 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V2 X X 1 X bt Timer 4 interrupt occurrence enabled TV2A Interrupt enable flag INTE 1 All interrupts enabled El y Constant period interrupt execution started A The prescaler count value and timer 4 count value to make the interrupt occur every 50 ms are set as follows 50 ms 4 0 MHz X 3 X 149 1 X 2 X 221 1 System clock Instruction Prescaler Timer 4 Timer 4 count value clock count value count X it can be 0 or 1 SOUICE lI instruction Fig 2 2 8 Timer 4 constant period interrupt setting example Rev 1 00 Aug 06 2004 RENESAS 2 29 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 2 2 4 Notes on use 1 2 3 4 S 6 7 8 9 Setting of INTO interrupt valid waveform Set a value to the bit 2 of register 11 and exe
205. ed and W represents write enabled 2 In order to select AIN3 AINO set register Q1 after setting register Q2 Rev 1 00 Aug 06 2004 RENESAS 2 7 REJ09B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 5 Pull up control register PUO Table 2 1 5 shows the pull up control register PUO Set the contents of this register through register A with the TPUOA instruction The contents of register PUO is transferred to register A with the TAPUO instruction Table 2 1 5 Pull up control register PUO at reset 00002 at RAM back up state retained Pull up control register PUO RAN PUOS P03 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUO P02 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUD P01 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUOO POo pin 0 Pull up transistor OFF pull up transistor control bit Pull up transistor ON Note R represents read enabled and W represents write enabled 6 Pull up control register PU1 Table 2 1 6 shows the pull up control register PUT Set the contents of this register through register A with the TPU1A instruction The contents of register PU1 is transferred to register A with the TAPU1 instruction Table 2 1 6 Pull up control register PU1 Pull up control register PU1 at reset 00002 at RAM back up state retaine
206. ed by software P10 P13 I O port P1 Port P1 serves as a 4 bit I O port The output structure can be switched to N channel open drain or CMOS by software For input use set the latch of the specified bit to 1 and select the N channel open drain Port P1 has a key on wakeup function and a pull up function Both functions can be switched by software P20 P23 1 0 port P2 Port P2 serves as a 3 bit I O port The output structure is N channel open drain For input use set the latch of the specified bit to 1 Ports P20 P22 are also used as SCK SOUT SIN respectively P30 P33 I O port P3 Port P3 serves as a 4 bit I O port The output structure is N channel open drain For input use set the latch of the specified bit to 1 Ports P30 and P31 are also used as INTO pin and INT1 pin respectively P40 P43 I O port P4 Port P4 serves as a 4 bit I O port The output structure can be switched to N channel open drain For input use set the latch of the specified bit to 1 Ports P40 P43 are also used as AIN4 AIN7 respectively P50o P53 UO port P5 Port P5 serves as a 4 bit I O port The output structure can be switched to N channel open drain or CMOS by software For input use set the latch of the specified bit to 1 and select the N channel open drain P60 P63 I O port P6 Port P6 serves as a 4 bit I O port The output structure can be switched to N channel open drain For inp
207. egister through register A with the TK1A instruction The contents of register K1 is transferred to register A with the TAK1 instruction Table 2 8 9 Key on wakeup control register K1 at reset 00002 at RAM back up state retained Key on wakeup control register K1 R W Kia Ports P02 and P03 return 0 Return by level condition selection bit 1 Return by edge Ports P02 and POz3 valid 0 Falling waveform L level da waveform level selection bit 1 Rising waveform H level Ports P01 and POo return 0 Return by level i condition selection bit 1 Return by edge Ports P01 and POo valid 0 Falling waveform L level i waveform level selection bit Rising waveform H level Note R represents read enabled and W represents write enabled 7 Key on wakeup control register K2 Table 2 8 10 shows the key on wakeup control register K2 Set the contents of this register through register A with the TK2A instruction The contents of register K2 is transferred to register A with the TAK2 instruction Table 2 8 10 Key on wakeup control register K2 at reset 00002 at RAM back up state retained Key on wakeup control register K2 RAN INT1 pin return condition 0 Return by level inis selection bit 1 Return by edge K22 INT1 pin key on wakeup control 0 Key on wakeup not used bit 1 Key on wakeup used INTO pin return condition 0 Returned by level K
208. er A Rev 1 00 Aug 06 2004 RENESAS 1 116 REJO9B0175 0100Z 4519 Group MACHINE INSTRUCTIONS INDEX BY ALPH TAV2 Transfer data to Accumulator from register V2 HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET ABET continued Instruction Dg Do Number of Number of Flag CY Skip condition code 0 o o0 1 0 1 0 1 0 1 0 5 5 Sii cyclos 2 16 1 1 Operation A V2 Grouping Interrupt operation Description Transfers the contents of interrupt control register V2 to register A TAW1 Transfer data to Accumulator from register W1 Instruction Dg Do Number of Number of Flag CY Skip condition code 1lolo slo o s3 o s 13 l2 a words cycles 2 16 1 1 Operation A W1 Grouping Timer operation Description Transfers the contents of timer control reg ister W1 to register A TAW2 Transfer data to Accumulator from register W2 Instruction Dg Do Number of Number of Flag CY Skip condition code 1jojo 1 ofo 1 1 o o 2 4 cC NIB cycles 2 16 1 1 Operation A W2 Grouping Timer operation Description Transfers the contents of timer control reg ister W2 to register A TAWS Transfer data to Accumulator from registe
209. er operation of a period measurement circuit is started O Even when the edge for measurement is input by timer operation is started from the operation of period measurement circuit is started timer 1 is not operated When data is read from timer 1 stop the timer 1 and the period measurement circuit and then execute the data read instruction Depending on the state of timer 1 the timer 1 interrupt request flag T1F may be set to 1 when the period measurement circuit is stopped by clearing bit 2 of register W5 to 0 In order to avoid the occurrence of an unexpected interrupt disable the timer 1 interrupt and then stop the period measurement circuit Figure 2 3 14 shows the setting example to read measurement data of period measurement circuit 10 Prescaler timer 1 timer 2 and timer 3 count start time and count time when operation starts Count starts from the first rising edge of the count source in Fig 2 3 15 after prescaler timer 1 timer 2 and timer 3 operations start O in Fig 2 3 15 Time to first underflow in Fig 2 3 15 is shorter for up to 1 period of the count source than time among next underflow in Fig 2 3 15 by the timing to start the timer and count source operations after count starts 11 Timer 4 count start time and count time when operation starts Count starts from the rising edge in Fig 2 3 16 after the first falling edge of the count source after timer 4 operation starts O in Fig
210. errupt is used O Check A D Interrupt Request A D Interrupt Occurs A D conversion completion flag is checked SNZAD y y SSS O Execute A D Conversion High order 8 bits of register AD Register A and register B TABAD Low order 2 bits of register AD High order 2 bits of register A TALA 0 is set to low order 2 bits of register A When A D conversion is executed by the same channel repeat to When A D conversion is executed by another channel repeat O to O X it can be 0 or 1 instruction Fig 2 4 2 A D conversion mode setting example Rev 1 00 Aug 06 2004 RENESAS 2 55 REJ09B0175 0100Z APPLICATION 4519 Group 2 4 A D converter 2 4 3 Notes on use 1 Note when the A D conversion starts again When the A D conversion starts again with the ADST instruction during A D conversion the previous input data is invalidated and the A D conversion starts again 2 A D converter 1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage Accordingly when the analog voltage is input from the circuit with high impedance and charge discharge noise is generated and the sufficient A D accuracy may not be obtained Therefore reduce the impedance or connect a capacitor 0 01 uF to 1 uF to analog input pins Figure 2 4 3 shows the analog input external circuit example 1 When the overvoltage applied to the A D conversion circuit may occur connect an external cir
211. errupts Note 1 Timer 4 interrupt is temporarily disabled Interrupt enable flag INTE Interrupt control register V2 Q Stop Timer Operation Timer 4 is temporarily stopped Timer 4 count source is selected PWM signal H interval expansion function control is set Timer control register W4 Set Port PWM signal output from CNTR1 pin is set Timer control register W6 Register Y Port D7 output latch Port output structure control register FR2 Set Timer Value Timer 4 count time is set Timer 4 reload register R4L Timer 4 reload register R4H O Start Timer Operation Timer 4 temporarily stopped is restarted CNTR1 output control is set to be valid Timer control register W4 O Set Interrupts Note 1 b3 bo 0 1 0 0 Interrupts except Timer 4 interrupt is enabled APPLICATION 2 3 Timers All interrupts disabled DI b1 Timer 4 interrupt occurrence disabled TV2A TW4A b2 PWM signal H interval expansion function valid b1 Timer 4 stop b0 XIN selected for Timer 4 count source b1 CNTR1 output auto control circuit not selected TW6A Specify bit position of port D TYA Set to L output RD b3 Port D7 CMOS output selected TFR2A Timer count value 3 set T4AB Timer count value 2 set T4HAB TW4A b3 CNTR1 output valid b1 Timer 4 operation start El PWM o
212. ess otherwise noted One Time PROM version Ta 20 C to 85 C VDD 2 5 to 5 5 V unless otherwise noted Parameter Test conditions APPENDIX 3 1 Electrical characteristics Limits Typ Supply current Rev 1 00 Aug 06 2004 REJ09B0175 0100Z at active mode with a ceramic resonator on chip oscillator stop VDD 5 V f XIN 6 MHz 14 1 6 2 0 2 8 VDD lt B VY f XIN 4 MHz 1 1 1 2 1 5 2 0 VDD 3V f XIN 4 MHz 0 4 0 5 0 6 0 8 at active mode with a quartz crystal oscillator on chip oscillator stop VDD 5V f XIN 32 kHz 55 60 65 70 VDD 3 V f XIN 32 kHz 12 13 14 15 at active mode with an on chip oscillator f XIN stop 50 70 at RAM back up mode POF instruction execution zENESAS 3 7 APPENDIX 4519 Group 3 1 Electrical characteristics 3 1 4 A D converter recommended operating conditions Table 3 1 7 A D converter recommended operating conditions Comparator mode included Ta 20 C to 85 C unless otherwise noted Limits Typ Parameter Conditions Supply voltage Mask ROM version One Time PROM version Analog input voltage A D conversion clock Mask ROM version VDD 4 0 to 5 5 V frequency VDD 2 7 to 5 5 V Note VDD 2 2 to 5 5 V VDD 2 0 to 5 5 V One
213. executing only the POF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction continuously Rev 1 00 Aug 06 2004 RENESAS 2 30 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers 2 3 Timers The 4519 Group has four 8 bit timers each has a reload register and the watchdog timer function This section describes individual types of timers related registers application examples using timers and notes 2 3 1 Timer functions 1 Timer 1 B Timer operation Timer 1 has the timer 1 count start trigger function from P30 INTO pin input 2 Timer 2 B Timer operation 3 Timer 3 B Timer operation Timer 3 has the timer 3 count start trigger function from P31 INT1 pin input 4 Timer 4 B Timer operation Timer 4 has the PWM output function 5 Watchdog timer E Watchdog function Watchdog timer provides a method to reset the system when a program run away occurs System operates after it is released from reset When the timer count value underflows the WDF1 flag is set to 1 Then if the WRST instruction is never executed until timer WDT counts 65534 WDFe2 flag is set to 1 and system reset occurs When the DWDT instruction and the WRST instruction are executed continuously the watchdog timer function is invalid The WRST instruction has the skip function When the WRST instruction is executed while the WDF1 flag is 1 the n
214. ext instruction is skipped and then the WDF1 flag is cleared to 0 Rev 1 00 Aug 06 2004 RENESAS 2 31 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers 2 3 2 Related registers 1 Interrupt control register V1 Table 2 3 1 shows the interrupt control register V1 Set the contents of this register through register A with the TV1A instruction In addition the TAV1 instruction can be used to transfer the contents of register V1 to register A Table 2 3 1 Interrupt control register V1 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZT2 instruction is valid 1 Interrupt enabled SNZT2 instruction is invalid 0 Interrupt disabled SNZT1 instruction is valid 1 Interrupt enabled SNZT1 instruction is invalid 0 Interrupt disabled SNZ1 instruction is valid 1 0 Interrupt control register V1 R W V13 Timer 2 interrupt enable bit Note 2 V12 Timer 1 interrupt enable bit Note 2 V11 i i EMI SEE nape Interrupt enabled SNZ1 instruction is invalid Note 2 Interrupt disabled SNZO instruction is valid 1 Interrupt enabled SNZO instruction is invalid Note 2 Notes 1 R represents read enabled and W represents write enabled 2 These instructions are equivalent to the NOP instruction 3 When timer is used V11 and V10 are not used Vio External 0 interrupt enable bit 2 Interrupt control register V2 Table 2 3 2 shows the i
215. f register W5 to 1 again When a period measurement circuit is used clear bit 0 of regis ter 11 to 0 and set a timer 1 count start synchronous circuit to be not selected Start timer operation immediately after operation of a period measurement circuit is started When the target edge for measurement is input until timer opera tion is started from the operation of period measurement circuit is started the count operation is not executed until the timer opera tion becomes valid Accordingly be careful of count data When data is read from timer stop the timer and clear bit 2 of register W5 to 0 to stop the period measurement circuit and then execute the data read instruction Depending on the state of timer 1 the timer 1 interrupt request flag T1F may be set to 1 when the period measurement cir cuit is stopped by clearing bit 2 of register W5 to 0 In order to avoid the occurrence of an unexpected interrupt clear the bit 2 of register V1 to 0 refer to Figure 270 and then stop the bit 2 of register W5 to 0 to stop the period measurement circuit 3 NE SAS HARDWARE FUNCTION BLOCK OPERATIONS In addition execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction refer to Figure 270 Also set the NOP instruction for the case when a skip is per formed with the SNZT1 instruction refer to Figure 27G X0XX2 The SNZT1 instruction is valid X
216. fo 1 ofofojolofofo 2 a o h m cycles 1 1 V12 0 T1F 1 Operation V12 0 T1F 21 Grouping X Timer operation After skipping T1F 0 Description When V12 0 Skips the next instruction V12 2 1 SNZT1 NOP when timer 1 interrupt request flag T1F is V12 bit 2 of interrupt control register V1 1 After skipping clears 0 to the T1F flag When the T1F flag is 0 executes the next instruction When V12 1 This instruction is equiva lent to the NOP instruction SNZT2 Skip if Non Zero condition of Timer 2 interrupt request flag Instruction Dg Do Number of Number of Flag CY Skip condition code o 1 o o o o o o a e 1 9 SLE 1 1 V13 0 T2F 1 Operation V13 0 T2F 21 Grouping Timer operation After skipping T2F 0 Description When V13 0 Skips the next instruction V13 2 1 SNZT2 NOP when timer 2 interrupt request flag T2F is V13 bit 3 of interrupt control register V1 1 After skipping clears 0 to the T2F flag When the T2F flag is 0 executes the next instruction When V13 1 This instruction is equiva lent to the NOP instruction SNZT3 Skip if Non Zero condition of Timer 3 interrupt request flag Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jo 1 o lojo ojo 1 o 2 e o Words cycles 1 1 V20 0 T3F 1 Operation V20 0 T3F 21 Grouping Timer operation After skipping T3F 0 Description When V20 0 Skips th
217. function is valid after system is returned from the RAM back up state When not using the watchdog timer function stop the watchdog timer function with the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back up When the watchdog timer function and RAM back up function are used at the same time initialize the flag WDF1 with the WRST instruction before system goes into the RAM back up state 5 Port P30 INTO pin When the RAM back up mode is used by clearing the bit 3 of register 11 to 0 and setting the input of INTO pin to be disabled be careful about the following note When the input of INTO pin is disabled register 113 0 clear bit O of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode 6 Port P31 INT1 pin When the RAM back up mode is used by clearing the bit 3 of register 12 to 0 and setting the input of INT1 pin to be disabled be careful about the following note When the input of INT1 pin is disabled register 123 0 clear bit 2 of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode Rev 1 00 Aug 06 2004 RENESAS 2 78 REJO9B0175 0100Z APPLICATION 4519 Group 2 9 Oscillation circuit 2 9 Oscillation circuit The 4519 Group has an internal oscillation circuit to produce the clock required for microcomputer operation The 4519 Group operates by the on chip oscillator cloc
218. g timer flag WDF1 cleared WRST Note when the watchdog timer flag is cleared When is executed considering the skip of the next instruction according to the watchdog timer flag WDF1 insert the NOP instruction after the WRST instruction Main Routine Execution Repeat In the interrupt service routine do not clear watchdog timer flag WDF1 Interrupt may be executed even if program run away occurs When going to RAM back up mode WRST WDF flag cleared NOP DI Interrupt disabled EPOF POF instruction enabled POF y Oscillation stop RAM back up mode In the RAM back up mode WEF WDF1 and WDF2 flags are initialized However when WDF2 flag is set to 1 at the same time system goes into RAM back up mode microcomputer may be reset When watchdog timer and RAM back up mode are used execute the WRST instruction to initialize WDF1 flag before system goes into the RAM back up mode Fig 2 3 13 Watchdog timer setting example Rev 1 00 Aug 06 2004 RENESAS 2 49 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers 2 3 4 Notes on use 1 2 3 4 5 6 7 8 9 Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data Stop counting and then execute the TPSAB instruction to set prescaler data Count source Stop timer 1 2 3 4 or LC counting to change its count source Reading the count values Stop timer 1 2 3 or 4 counting and then e
219. gister A Note After this instruction is executed 0 is stored to the high order 2 bits A3 A2 of register A TBA Transfer data to register B from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code o ojo o o o 1 1 1 0 fo wors Cyc eS 2 16 1 1 Operation B lt A Grouping Register to register transfer Description Transfers the contents of register A to regis ter B TDA Transfer data to register D from Accumulator Instruction Do Do Number of Number of Flag CY Skip condition code ololololilolilololi 0 words cycles 2 16 1 1 Operation DR2 DRo lt A2 Ao Grouping Register to register transfer Description Transfers the contents of the low order 3 bits A2 A0 of register A to register D Rev 1 00 Aug 06 2004 RENESAS 1 119 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TEAB Transfer data to register E from Accumulator and register B Instruction Dg Do Numbe
220. gister A Instruction Dg Do Number of Number of Flag CY Skip condition code tlolol1 0 2 7l2 words cycles 2 16 1 1 Operation B T37 T34 Grouping Timer operation A T33 T30 Description Transfers the high order 4 bits T37 T34 of timer 3 to register B Transfers the low order 4 bits T33 T30 of timer 3 to register A Rev 1 00 Aug 06 2004 RENESAS 1 110 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TABA Transfer data to Accumulator and register B from timer 4 Instruction Dg Do Number of Number of Flag CY Skip condition code i50 o 1 1 1 o0 0 1 1 e Y 8 MORE press 2 16 1 1 Operation B T47 T44 Grouping Timer operation A T43 T40 Description Transfers the high order 4 bits T47 T44 of TABAD Transfer data to Accumulator and register B from register AD timer 4 to register B Transfers the low order 4 bits T43 T40 of timer 4 to register A Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jojof1 1 1 1 oloj 1 2 o words cycles 2 16 1 1 E m Operation In A D conversion mode Q13 0 Grouping X A D conversion operation B ADo AD6 Description
221. he 4519 Group has the skip function to unexecute the next described instruction The 4519 Group just invalidates the next instruc tion when a skip is performed The contents of program counter is not increased by 2 Accordingly the number of cycles does not change even if skip is not performed However the cycle count becomes 1 if the TABP p RT or RTS instruction is skipped Rev 1 00 Aug 06 2004 ENESAS REJO9B0175 0100Z 1 85 4519 Group INDEX LIST OF INSTRUCTION FUNCTION Mnemonic Function Page HARDWARE INDEX OF INSTRUCTION FUNCTION Mnemonic Function TAB TBA TAY TYA TEAB E7 E4 B E3 Eo lt A B E7 E4 A E3 Eo DR2 DRo A2 A0 A2 A0 A3 0 DR2 DRo Register to register transfer A1 Ao Z1 Zo A3 A2 0 A X A2 A0 A3 0 SP2 SPo 110 130 119 130 119 130 128 130 RAM to register transfer 120 130 XAMI j M DP a EXOR j 0to 15 c Y 1 M DP A X X EXOR j 0to 15 111 130 119 130 112 130 119 130 118 130 116 130 X xx20to 15 Y yy 20to 15 2 zz 0to03 Y Y 1 RAM addresses Y e Y 1 98 130 Arithmetic operation 98 130 95 130 A M DP X XEXOR j 0to 15 A 2 M DP X X EXOR j 0to 15 A gt M DP X X EXOR j RAM to register
222. he P30 INTO pin the external 0 Depending on the input state of the P30 INTO pin the external 0 interrupt request flag EXFO may be set when the bit 3 of regis interrupt request flag EXFO may be set when the bit 2 of regis ter 11 is changed In order to avoid the occurrence of an ter 11 is changed In order to avoid the occurrence of an unexpected interrupt clear the bit 0 of register V1 to 0 refer to unexpected interrupt clear the bit O of register V1 to 0 refer to Figure 61 and then change the bit 3 of register I1 Figure 640 and then change the bit 2 of register I1 In addition execute the SNZO instruction to clear the EXFO flag to In addition execute the SNZO instruction to clear the EXFO flag to 0 after executing at least one instruction refer to Figure 62 0 after executing at least one instruction refer to Figure 649 Also set the NOP instruction for the case when a skip is per Also set the NOP instruction for the case when a skip is per formed with the SNZO instruction refer to Figure 62 formed with the SNZO instruction refer to Figure 64G LA XXX02 TV1A The SNZO instruction is valid LA 12 X1XX2 THA Interrupt valid waveform is changed NOP XXxX02 The SNZO instruction is valid 0XXX2 Control of INTO pin input is changed SNZO The SNZO instruction is executed EXFO flag cleared The SNZO instruction is executed EXFO flag cleared NOP X
223. he no operated clock source f RING or f XIN cannot be used for the system clock Also the clock source f RING or f XIN se lected for the system clock cannot be stopped System clock STCK Internal clock generating circuit divided by 3 Instruction clock INSTCK n chip oscillator internal oscillator XINO Ceramic XouT O resonance A RC oscillation CMCK instruction CRCK instruction Quartz crystal oscillation Fig 54 Clock control circuit structure Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS Internal reset signal Key on wakeup signal EPOF instruction POF instruction 1 68 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS 1 Main clock generating circuit f XIN The ceramic resonator RC oscillation or quartz crystal oscillator can be used for the main clock of this MCU After system is released from reset the MCU starts operation by the clock output from the on chip oscillator which is the internal os cillator When the ceramic resonator is used execute the CMCK instruc tion When the RC oscillation is used execute the CRCK instruction When the quartz crystal oscillator is used execute the CYCK instruction The oscillation start stop of main clock f XIN is controlled by bit 1 of register MR The system clock is selected by bit 0 of register MR The oscillation circuit by the CMCK CRCK or CYCK instruction can be selected
224. ield and stores the result in register X After exchanging the contents of M DP with the contents of register A an exclusive OR operation is per formed between register X and the value j in the immediate field and stores the result in register X Subtracts 1 from the contents of register Y As a result of subtraction when the contents of register Y is 15 the next instruction is skipped When the contents of register Y is not 15 the next instruction is executed After exchanging the contents of M DP with the contents of register A an exclusive OR operation is per formed between register X and the value j in the immediate field and stores the result in register X Adds 1 to the contents of register Y As a result of addition when the contents of register Y is 0 the next in struction is skipped When the contents of register Y is not 0 the next instruction is executed After transferring the contents of register A to M DP an exclusive OR operation is performed between reg ister X and the value j in the immediate field and stores the result in register X RENESAS 1 131 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code l5 Mnemonic ge FE Function Type of Hexadecimal E 2 EJ YB Do Ds D7 De Ds D4 Ds De Di Do 313 instruction notation z z LAn 0 0 1 1 n n n n 07 n 1 1 A n n 0to 15 TABP p 0 0 p5 p4 p3 p
225. ignal WRST instruction Note 6 TOR RESET signal TR3AB This instruction is used to transfer the contents of Notes 3 Xin cannot be used for the count source when bit 1 MR1 of register A and register B to only reload register R3 register MR is set to 1 and f XIN oscillation is stopped TARAL ed the contents of 4 Timer 3 count start synchronous circuit is set by the valid edge INSTCK Instruction clock system clock divided by 3 of P31 INT1 pn selected by bits 1 121 and 2 122 of register B ORCLK Prescaler output Sap clock divided B 1 to 256 5 SUE Pes dedic S PI RH DA Data is set automatically from each reload The next instruction is not skipped even when the WRST register when timer underflows instruction is executed while flag WDF1 0 auto reload function 6 Flag WEF is cleared to 0 and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously 7 The WEF flag is set to 1 at system reset or RAM back up mode Fig 26 Timer structure 2 Rev 1 00 Aug 06 2004 RENESAS 1 34 REJO9B0175 0100Z 4519 Group Table 10 Timer related registers Timer control register PA HARDWARE FUNCTION BLOCK OPERATIONS at reset 02 at RAM back up 02 Prescaler control bit Timer control register W1 Stop state initialized Operating R W TAW1 TW1A at reset 00002 at RAM back up state retained Timer 1 count auto
226. imer 1 count time is set Timer 1 reload register R1 FF16 Timer count value 255 set T1AB Clear Interrupt Request Timer 1 interrupt activated condition is peara Timer 1 interrupt request flag T1F Timer 1 interrupt activated condition cleared SNZT1 Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction Check Input level of INTO Pin to Measure H Pulse Width Whether an input level of INTO pin is L is checked SNZIO Start Period Measurement Circuit If an input level of INTO pin is L the period measurement circuit operation is started b3 bO Timer control register W5 111 b2 period measurement circuit operating TW5A O Start Timer Operation Timer 1 temporarily stopped is restarted Timer control register W1 b2 Timer 1 operation start TW1A Enable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V1 x 1 x Xx b2 Timer 1 interrupt occurrence enabled TV1A Interrupt enable flag INTE 1 All interrupts enabled El Timer 1 count started synchronizing with a rise of INTO pin input X it can be 0 or 1 instruction Fig 2 3 11 Pulse width measurement of INTO pin input setting example 1 Rev 1 00 Aug 06
227. iming Re T CT 1 51 Fig 39 Definition of A D conversion accuracy sse eee eee eee eee 1 52 Fig 40 Serial 1O Structure alicia ias 1 53 Fig 41 Serial I O register state when transferring sese eree eee eee eee eee eee eee 1 54 Fig 42 Serial l O connection example 1 55 Fig 43 Timing of serial I O data transfer sse 1 56 Fig 44 Reset release timing iet retener nnii ERE Rana sa LEAN A Ehe uS RA ew Rea iEn 1 58 Fig 45 RESET pin input waveform and reset operation e e e 1 58 Fig 46 Structure of reset pin and its peripherals and power on reset operation 1 59 Fig 47 Internal state at reset 1 e ter er etuer eh eer Er e e n 1 60 Rev 1 00 Aug 06 2004 RENESAS iv REJO9B0175 0100Z 4519 Group Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig List of figures 48 Internal state at reset 2 ener nennen nnne nnne nins 1 61 49 Voltage drop detection reset circuit sseesssssssssssseseseeee eene 1 62 50 Voltage drop detection circuit operation waveform sse eee eee eee eee 1 62 51 State transito Mistica e 1 65 52 Set source and clear source of the P flag 1 65 53 Start condition identified example using the SNZP instruction sssss 1 65 54 Clock control circuit structure T 1 68 55 Switch to ceramic resonance RC oscillation quartz crystal oscillation 1 69 56 Ha
228. ing Interrupt operation H2 1 INTO H Description When 112 0 Skips the next instruction 112 bit 2 of the interrupt control register 11 when the level of INTO pin is L Executes the next instruction when the level of INTO pin is H When l12 1 Skips the next instruction when the level of INTO pin is H Executes the next instruction when the level of INTO pin is L SNZI1 Skip if Non Zero condition of external 1 Interrupt input pin Instruction Dg Do Number of Number of Flag CY Skip condition words cycles code o o olo 1 1 1 0 1 1 B Jis y 1 1 122 0 INT1 L 122 1 INT1 H Operation 122 0 INT1 L 7 Grouping Interrupt operation 122 1 INT1 H Description When 122 0 Skips the next instruction 122 bit 2 of the interrupt control register 12 when the level of INT1 pin is L Executes the next instruction when the level of INT1 pin is H When 122 1 Skips the next instruction when the level of INT1 pin is H Executes the next instruction when the level of INT1 pin is L SNZP Skip if Non Zero condition of Power down flag Instruction Do Do Number of Number of Flag CY Skip condition code 0 0j0 0 0 0 0 0 1 t1 3 wales cycles 8 1 1 P 1 Operation P
229. instruction In addition the TAV2 instruction can be used to transfer the contents of register V2 to register A Table 2 4 1 Interrupt control register V2 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZSI instruction is valid 1 Interrupt enabled SNZSI instruction is invalid Note 2 0 Interrupt disabled SNZAD instruction is valid 1 Interrupt enabled SNZAD instruction is invalid Note 2 0 Interrupt disabled SNZTA instruction is valid 1 0 Interrupt control register V2 Serial lO interrupt enable bit V23 Note 2 V22 A D interrupt enable bit V21 Ti 4 int t ble bit M EIL d d Interrupt enabled SNZTA instruction is invalid Note 2 Interrupt disabled SNZTS instruction is valid 1 Interrupt enabled SNZTS instruction is invalid Note 2 Notes 1 R represents read enabled and W represents write enabled 2 These instructions are equivalent to the NOP instruction 3 When setting the A D converter V23 V21 and V20 are not used V20 Timer 3 interrupt enable bit 2 A D control register Q1 Table 2 4 2 shows the A D control register Q1 Set the contents of this register through register A with the TQ1A instruction In addition the TAQ instruction can be used to transfer the contents of register Q1 to register A at reset 00002 at RAM back up state retained 0 A D conversion mode 1 Comparator mode Qt2 Q 1 Q o Analog input pins O AINo 1
230. instruction In addition the TAW2 instruction can be used to transfer the contents of register W2 to register A Table 2 3 7 Timer control register W2 Timer control register W2 at reset 00002 at RAM back up state retained R W W23 CNTRO output selection bit 0 Timer 1 underflow signal divided by 2 output 1 Timer 2 underflow signal divided by 2 output 0 Stop state retained W22 Timer 2 control bit 1 Operating 21 W20 Count source W21 Timer 2 count source selection 0 0 System clock STCK bits 0 1 Prescaler output ORCLK W20 1 O Timer 1 underflow signal T1UDF PWM signal PWMOUT Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z l ENESAS 2 34 APPLICATION 4519 Group 2 3 Timers 8 Timer control register W3 Table 2 3 8 shows the timer control register W3 Set the contents of this register through register A with the TW3A instruction In addition the TAW3 instruction can be used to transfer the contents of register W3 to register A at reset 00002 at RAM back up state retained 0 Timer 3 count auto stop circuit not selected 1 Timer 3 count auto stop circuit selected 0 Stop state retained 1 Table 2 3 8 Timer control register W3 Timer control register W3 R W Timer 3 count auto stop circuit control bit Note 2 W33 W32 Timer 3 control
231. instruction after executing the EPOF instruction Makes the immediate after POF instruction valid by executing the EPOF instruction Skips the next instruction when the P flag is 1 After skipping the P flag remains unchanged Skips the next instruction when watchdog timer flag WDF1 is 1 After skipping clears 0 to the WDF1 flag Also stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction System reset occurs RENESAS 1 145 4519 Group INSTRUCTION CODE TABLE 000009000001 000010000011 000100 000101 000110 000111 001000 001001 001010 001011 HARDWARE INSTRUCTION CODE TABLE 001100 001101 001110 001111 010000 010111 notation 00 01 02 03 04 05 e o 07 08 09 0A 0B 0C 0D 0E OF 10 17 LA 0 16 32 BL BL BM LA 1 17 33 BL BL BM LA 2 18 34 BL BL BM LA 3 19 35 BL BL BM LA 4 20 36 BL BL BM LA 5 21 37 BL BL BM LA 6 22 38 BL BL BM LA 7 23 39 BL BL BM LA 8 24 40 BL BL BM LA 9 25 41 BL BL BM lw KIO bI lon lO lE lG IM lI lO gt esk o LA 10 26 42 BL BL
232. interrupt processing lt The interrupt processing routine Decrements the SWDT contents by 1 at each interrupt processing Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles at the fixed interrupt processing count Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less Main routine Interrupt processing routine gt SWDT N SWDT t SWDT 1 El Interrupt processing Main processing N SWDT N N Y Interrupt processing Main routine routine errors errors Fig 3 4 11 Watchdog timer by software Rev 1 00 Aug 06 2004 RENESAS 3 26 REJO9B0175 0100Z APPENDIX 4519 Group 3 5 Package outline 3 5 Package outline
233. interrupt request flag T4F Watchdog timer flags WDF1 WDF2 Watchdog timer enable flag WEF Timer control register PA Timer control register W1 Timer control register W2 Timer control register W3 Timer control register W4 Timer control register W5 Timer control register W6 Clock control register MR Clock control register RG Serial 1 O transmit receive completion flag SIOF Serial I O mode register J1 Serial I O register SI x A D conversion completion flag ADF A D control register Q1 A D control register Q2 A D control register Q3 o Successive comparison register AD Comparator register Key on wakeup control register KO Key on wakeup control register K1 Key on wakeup control register K2 Pull up control register PUO Pull up control register PU1 Fig 47 Internal state at reset 1 Rev 1 00 Aug 06 2004 7tENESAS REJ09B0175 0100Z ID JO lO JO oO x xilol o ojojo ooxx OoOo ojlollollollollxi ixi lollolo Interrupt disabled Interrupt disabled Interrupt disabled Prescaler stopped Timer 1 stopped Timer 2 stopped Timer 3 stopped Timer 4 stopped Period measurement
234. inuously every system is returned from the RAM back up state When the watchdog timer function and RAM back up function are used at the same time initialize the flag WDF1 with the WRST instruction before system enters into the RAM back up state Pulse width input to CNTRO pin CNTR1 pin Refer to section 3 1 Electrical characteristics for rating value of pulse width input to CNTRO pin CNTR1 pin Period measurement circuit O When a period measurement circuit is used clear bit O of register 11 to 0 and set a timer 1 count start synchronous circuit to be not selected O While a period measurement circuit is operating the timer 1 interrupt request flag T1F is not set by the timer 1 underflow signal it is the flag for detecting the completion of period measurement O When a period measurement circuit is used select the sufficiently higher speed frequency than the signal for measurement for the count source of a timer 1 Rev 1 00 Aug 06 2004 RENESAS 2 50 REJ09B0175 0100Z 4519 Group APPLICATION 2 3 Timers O When the signal for period measurement is De CNTRO pin input do not select De CNTRO pin input as timer 1 count source The XIN input is recommended as timer 1 count source at the time of period measurement circuit use e When the input of P30 INTO pin is selected for measurement set the bit 3 of a register 11 to 1 and set the input of INTO pin to be enabled O Start timer operation immediately aft
235. ion the TAI2 instruction can be used to transfer the contents of register I2 to register A Table 2 3 4 Interrupt control register 12 at reset 00002 at RAM back up state retained Interrupt control register I2 RAN NE 0 INT1 pin input disabled 123 INT1 pin input control bit Note 2 D I TERRE Falling waveform L level L level is recognized with Interrupt valid waveform for INT1 0 the SNZI1 instruction 122 pin return level selection bit s Note 2 Rising waveform H level H level is recognized with the SNZI1 instruction 101 INT1 pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected 120 INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit not selected synchronous circuit selection bit Timer 3 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 122 and 123 are changed the external interrupt request flag EXF1 may be set Accordingly clear EXF1 flag with the SNZ1 instruction when the bit 1 V11 of register V1 to 0 In this time set the NOP instruction after the SNZ1 instruction for the case when a skip is performed with the SNZ1 instruction Rev 1 00 Aug 06 2004 RENESAS 2 33 REJO9B0175 0100Z APPLICATION 2 3 Timers 4519 Group 5 Timer control register PA Table 2 3 5 shows the timer control register PA
236. ion DD 5 12 V DD 3 072 V Full scale transition voltage DD 3 072 V DD 2 56 V One Time PROM version DD 5 12 V V V V V Mask ROM version VDD 5 12V V V V V DD 3 072 V Absolute accuracy Quantization error excluded Mask ROM version 2 0V VDD 2 2V A D operating current VDD 5V Note 1 VDD 3V A D conversion time f XIN 6 MHz f STCK f XIN XIN through mode ADCK INSTCK 6 Comparator resolution Comparator error Note 2 Mask ROM version VDD 5 12V VDD 3 072 V VDD 2 56 V One Time PROM version VDD 5 12 V VDD 3 072 V Comparator comparison time r Logic value of comparison voltage Vref VDD Vref Xn 256 n Value of register AD n 0 to 255 f XIN 6 MHz f STCK f XIN XIN through mode ADCK INSTCK 6 Notes 1 When the A D converter is used IADD is added to IDD supply current 2 As for the error from the ideal value in the comparator mode when the contents of the comparator register is n the logic value of the comparison voltage Vref which is generated by the built in D A converter can be obtained by the following formula Rev 1 00 Aug 06 2004 REJ09B0175 0100Z zENESAS 3 9 APPENDIX 4519 Group 3 1 Electrical characteristics 3 1 5 Voltage drop detection circuit characteristics Table 3 1 9 Voltage drop detection circu
237. ion at RAM back up mode 1 6 One Time PROM version at RAM back up mode 2 0 Supply voltage H level input voltage PO P1 P2 P3 P4 P5 P6 Do D7 VDCE XIN 0 8VDD H level input voltage RESET 0 85VDD H level input voltage Sck Sin CNTRO CNTR1 INTO INT1 0 85VDD L level input voltage PO P1 P2 P3 P4 P5 P6 Do D7 VDCE XIN 0 VIL L level input voltage RESET 0 VIL L level input voltage Sck SIN CNTRO CNTR1 INTO INT1 0 lt lt lt lt lt lt lt lt lt lt lt loH peak H level peak output current PO P1 P5 Do D7 VDD lt B VY 3 gt CNTRO CNTR1 VDD 3V loH avg H level average output current Note PO P1 P5 Do D7 VDD 5V 3 gt CNTRO CNTR1 VDD 3V loL peak L level peak output current PO P1 P2 P4 P5 P6 VoD 5V Sck SOUT VDD 3V loL peak L level peak output current P3 RESET VDD 5V VDD lt 2 Y loL peak L level peak output current Do D5 VDD 5V VDD 3V loL peak L level peak output current De D7 VDD 5 V CNTRO CNTR1 VDD 3V loL avg L level average output current Note PO P1 P2 P4 P5 P6 Vop 5V Sck SOUT VDD 3 V loL avg L level average output current Note P3 RESET VDD 5V VDD 3V loL avg L level average output current
238. ion or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corp or a third party Renesas Technology Corp assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts pro grams algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts pro grams and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corp without notice due to product improvements or other reasons It is therefore recommended that customers con tact Renesas Technology Corp or an authorized Renesas Technology Corp product dis tributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by vari
239. ions but it has PROM mode that enables writing to built in PROM Table 23 shows the product of built in PROM version Figure 73 shows the pin configurations of built in PROM versions The One Time PROM version has pin compatibility with the mask ROM version Table 24 Product of built in PROM version Part number PROM 5129 PAM dne Package ROM type X 10 bits X 4 bits M34519E8FP 8192 words 384 words 42P2R A One Time PROM shipped in blank PIN CONFIGURATION TOP VIEW lt gt P12 lt Pili lt gt Pio lt gt P03 lt gt P02 lt gt P01 lt gt P0o lt gt P43 AIn7 lt gt P42 Ain6 lt gt P41 AiN5 lt gt P4o AiN4 lt gt P63 Ain3 lt gt P6 2 AiN2 lt gt P61 AIN1 lt gt P6o AiNo lt gt P33 lt gt P32 lt gt P31 INT1 lt gt P30 INTO lt VDCE VDD ha De CNTRo D7 CNTR1 P5o P51 P52 P53 P20 Sck P21 SouT P22 Sin RESET CNVss Xour XIN Vss ET TIS A A NI E B BEERE AEREE HHNH h H AN Q d4836 SVEN HHEHHHHHHEHHEHHHBHH Fig 71 Pin configuration of built in PROM version Rev 1 00 Aug 06 2004 RENESAS 1 148 REJO9B0175 0100Z 4519 Group 1 PROM mode The built in PROM version has a PROM mode in addition to a nor mal operation mode The PROM mode is used to write to and
240. is enabled Instruction clock INSTCK A D converter operation clock selection bit On chip oscillator f RING Division ratio Frequency divided by 6 A D converter operation clock division Frequency divided by 12 ratio selection bits Frequency divided by 24 Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7RENESAS Frequency divided by 48 1 48 4519 Group 1 A D control register A D control register Q1 Register Q1 controls the selection of A D operation mode and the selection of analog input pins Set the contents of this register through register A with the TQ1A instruction The TAQ1 instruc tion can be used to transfer the contents of register Q1 to register A A D control register Q2 Register Q2 controls the selection of P40 AIN4 P43 AIN7 P60 AIN0 P63 AIN3 Set the contents of this register through register A with the TQ2A instruction The TAQ2 instruction can be used to transfer the contents of register Q2 to register A A D control register Q3 Register Q3 controls the selection of A D converter operation clock Set the contents of this register through register A with the TQ3A instruction The TAQ3 instruction can be used to transfer the contents of register Q3 to register A 2 Operating at A D conversion mode The A D conversion mode is set by setting the bit 3 of register Q1 to 0 3 Suc
241. ister X 4 bits Register Y 4 bits Register D 3 bits Register E 8 bits lI L 5 Stack registers SKs Stack registers SKs are eight identical registers so that subrou tines can be nested up to 8 levels However one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction Accord ingly be careful not to over the stack when performing these operations together amp Multifunction The input output of P30 and P31 can be used even when INTO and INT1 are selected The input of ports P20 P22 can be used even when SIN SOUT and Sck are selected The input output of De can be used even when CNTRO input is selected The input of De can be used even when CNTRO output is selected The input output of D7 can be used even when CNTR1 input is selected The input of D7 can be used even when CNTR1 output is selected Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS HARDWARE LIST OF PRECAUTIONS Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data Stop counting and then execute the TPSAB instruction to set prescaler data Timer count source Stop timer 1 2 3 and 4 counting to change its count source Reading the count value Stop timer 1 2 3 or 4 counting and then execute the data read instruction TAB1
242. it RGo Rev 1 00 Aug 06 2004 RENESAS 2 80 REJ09B0175 0100Z APPLICATION 4519 Group 2 9 Oscillation circuit 2 9 3 Notes on use 1 2 3 4 Clock control Execute the main clock f XIN selection instruction CMCK CRCK or CYCK instruction in the initial setting routine of program executing it in address 0 in page 0 is recommended The oscillation circuit by the CMCK CRCK or CYCK instruction can be selected only at once The oscillation circuit corresponding to the first executed one of these instructions is valid The CMCK CRCK or CYCK instructions can be used only to select main clock f XIN In this time the start of oscillation and the switch of system clock are not performed When the CMCK CRCK or CYCK instructions are never executed main clock f XIN cannot be used and system can be operated only by on chip oscillator The no operated clock source f RING or f XIN cannot be used for the system clock Also the clock source f RING or f XIN selected for the system clock cannot be stopped On chip oscillator The clock frequency of the on chip oscillator depends on the supply voltage and the operation temperature range Be careful that margin of frequencies when designing application products When considering the oscillation stabilize wait time at the switch of clock be careful that the margin of frequencies of the on chip oscillator clock External clock When the external clock sign
243. it characteristics Ta 20 C to 85 C unless otherwise noted Limits Typ Detection voltage 3 5 reset occurs Note 1 Parameter Test conditions Detection voltage reset release Note 2 Detection voltage hysteresis Operation current Note 3 VDD 5V VDD 3V Detection time VDD gt VRST 0 1 V Note 4 Notes 1 The detected voltage VRST is defined as the voltage when reset occurs when the supply voltage VDD is falling 2 The detected voltage VRST is defined as the voltage when reset is released when the supply voltage VDD is rising from reset occurs 3 When the voltage drop detection circuit is used VDCE pin H IRST is added to IDD power current 4 The detection time TRST is defined as the time until reset occurs when the supply voltage VDD is falling to VRST 0 1 V 3 1 6 Basic timing diagram System clock Port D output Port D input Ports PO P1 P2 P3 POo POs P4 P5 P6 output P1o Pa P20 P23 P30 P33 P4o P43 P5o P53 P60 P63 Ports PO P1 P2 P3 PO0 PO3 P4 P5 P6 input Plo P1a P2o P23 P30 P33 P40 P43 P5o P53 P60 P63 Interrupt input INTO INT1 Rev 1 00 Aug 06 2004 RENESAS 3 10 REJO9B0175 0100Z APPENDIX 4519 Group 3 2 Typical characteristics 3 2 Typical characteristics As for the standard characteristics refer to Renesas Technology Corp Homepage http www
244. its A2 Ao of register A Transfers the contents of register Z to the low order 2 bits A1 Ao of register A Transfers the contents of register X to register A Transfers the contents of stack pointer SP to the low order 3 bits A2 Ao of register A Continuous description Loads the value x in the immediate field to register X and the value y in the immediate field to register Y When the LXY instructions are continuously coded and executed only the first LXY instruction is executed and other LXY instructions coded continuously are skipped Loads the value z in the immediate field to register Z Adds 1 to the contents of register Y As a result of addition when the contents of register Y is O the next in struction is skipped When the contents of register Y is not 0 the next instruction is executed Subtracts 1 from the contents of register Y As a result of subtraction when the contents of register Y is 15 the next instruction is skipped When the contents of register Y is not 15 the next instruction is executed Rev 1 00 Aug 06 2004 REJO9B0175 0100Z After transferring the contents of M DP to register A an exclusive OR operation is performed between reg ister X and the value j in the immediate field and stores the result in register X After exchanging the contents of M DP with the contents of register A an exclusive OR operation is per formed between register X and the value j in the immediate f
245. k f RING which is the internal oscillator after system is released from reset Also the ceramic resonator the RC oscillation or quartz crystal oscillator can be used for the main clock f XIN of the 4519 Group The CMCK instruction CRCK instruction or CYCK instruction is executed to select the ceramic resonator RC oscillator or quartz crystal oscillator respectively 2 9 1 Oscillation operation System clock is supplied to CPU and peripheral device as the base clock for the microcomputer operation The system clock f XIN or f RING is selected by bit O of register MR The oscillation start stop of main clock f XIN is controlled by bit 1 of register MR Also an operation mode of a selected clock is selected from the followings by bits 3 and 2 of register MR e through mode f XIN not divided frequency divided by 2 mode f XIN 2 frequency divided by 4 mode f XIN 4 or frequency divided by 8 mode f XIN 8 Figure 2 9 1 shows the structure of the clock control circuit Division circuit Mba MR2 System clock STCK Dl Instruction clock enerating circui On chip oscillator Divided by 2 a S G 3 INSTEN internal oscillator Ceramic resonance RC oscillation CMCK instruction Quartz crystal oscillation CYCK instruction Internal reset signal Key on wakeup signal EPOF instruction POF instruction Fig 2 9 1 Structure of clock control circuit Rev 1 0
246. l open drain or CMOS can be selected as the output structure of ports Do D7 in 1 bit unit by setting registers FR1 FR2 Notes 1 When the SD and RD instructions are used do not set 10002 or more to register Y 2 Port De is also used as CNTRO pin Accordingly when using port De set bit 0 W60 of register W6 to 0 3 Port D7 is also used as CNTR1 pin Accordingly when using port D7 set bit 3 W43 of register W4 to 0 Rev 1 00 Aug 06 2004 RENESAS 2 5 REJ09B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 2 1 2 Related registers 1 Timer control register W4 Table 2 1 1 shows the timer control register W4 Set the contents of this register through register A with the TW4A instruction The contents of register W4 is transferred to register A with the TAWA instruction at reset 00002 at RAM back up state retained Table 2 1 1 Timer control register W4 Timer control register W4 R W W4o Timer 4 count source selection bit Was D7 CNTR1 pin function selection 0 D7 I O CNTR1 input bit 1 CNTR1 1 0 D7 input PWM signal H interval 0 PWM signal H interval expansion function invalid W42 l expansion function control bit 1 PWM signal H interval expansion function valid Stop state retained W41 Timer 4 control bit 9 P s 1 Operating 0 XIN input 1 Prescaler output ORCLK divided by 2 Notes 1 R represents read enabled and W represents w
247. lag CY Skip condition code 1 ojoljolo o olo 1 ol 2 o e wares cycles 2 16 1 1 _ Operation J1 A Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Grouping Serial l O operation Description Transfers the contents of register A to serial UO control register J1 RENESAS 1 121 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TKOA Transfer data to register KO from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1ijololololsls ols sl le B wolgs G 2 16 1 1 H B Operation KO A Grouping Input Output operation Description Transfers the contents of register A to key on wakeup control register KO TK1A Transfer data to register K1 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1JoloToJol1 oJ o o 2 4 wales cycles 2 16 1 1 H Operation K1 A Grouping Input Output operation Description Transfers the contents of register A to key on wakeup control register K1 TK2A Transfer data to register K2 from Accumulator Instruction Do Do Number of Number of Flag CY Skip condi
248. lator The clock frequency of the on chip oscillator depends on the sup ply voltage and the operation temperature range Be careful that variable frequencies when designing application products When considering the oscillation stabilize wait time at the switch of clock be careful that the margin of frequencies of the on chip oscillator clock 1 76 HARDWARE 4519 Group LIST OF PRECAUTIONS 9 External clock When the external clock signal for the main clock f XIN is used connect the clock source to XIN pin and XOUT pin open In pro gram after the CMCK instruction is executed set main clock f XIN oscillation start to be enabled MR1 0 For this product when RAM back up mode and main clock f XIN stop MR1 1 XIN pin is fixed to H in order to avoid the through current by floating of internal logic The XIN pin is fixed to H until main clock f XIN oscillation start to be valid MR1 0 by the CMCK instruction from reset state Accordingly when an external clock is used connect a 1 KQ or more resistor to XIN pin in series to limit of current by competitive signal E Characteristic Differences Between Mask ROM and Onel Time PROM Version MCU There are differences in electric characteristics operation mar gin noise immunity and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes When manufacturing an application system with the On
249. le Interrupts The Timer 1 interrupt which is temporarily disabled is enabled b3 bo Interrupt control register V1 X11 xX xX b2 Timer 1 interrupt occurrence enabled TV1A Interrupt enable flag INTE 1 All interrupts enabled El y Constant period interrupt execution started A The prescaler count value and timer 1 count value to make the interrupt occur every 3 ms is set as follows 3 ms 4 0 MHz X 3 X 15 1 X 249 1 System clock Instruction Prescaler Timer 1 count value clock count value X it can be 0 or 1 J instruction Fig 2 3 4 Constant period measurement setting example Rev 1 00 Aug 06 2004 RENESAS 2 40 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers Disable Interrupts Timer 2 interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI Interrupt control register V1 b3 Timer 2 interrupt occurrence disabled TV1A Q Stop Timer and Prescaler Operation Timer 2 and prescaler are temporarily stopped TW2A Timer 2 count source and CNTRO output are selected b3 Timer 2 underflow signal divided by 2 selected for b3 CNTRO output Timer control register W2 11010 b2 Timer 2 stop b1 bO Prescaler output ORCLK selected for Timer 2 count source Timer control register PA Prescaler stop TPAA G Set CNTRO Output The output structure of the CNTRO pin is set to N cha
250. lected 3 Generate the wait time by software until the oscillation is stabilized and then switch the system clock 4 Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back up state 5 System returns to state A certainly when returning from the RAM back up mode However the selected contents CMCK CRCK CYCK instruction execution state of f XIN oscillation circuit is retained Fig 51 State transition EPOF POF Power down flag P instruction instruction S Q Program start Reset input 9 R Warm start O Set source EPOF instruction POF instruction Cold start O Clear source Reset input Fig 52 Set source and clear source of the P flag Fig 53 Start condition identified example using the SNZP in struction Rev 1 00 Aug 06 2004 RENESAS 1 65 REJO9B0175 0100Z 4519 Group HARDWARE FUNCTION BLOCK OPERATIONS Table 21 Key on wakeup control register pull up control register Key on wakeup control register KO at reset 00002 at RAM back up state retained Pins P12 and P13 key on wakeup Key on wakeup not used control bit Key on wakeup used Pins P10 and P11 key on wakeup Key on wakeup not used control bit Key on wakeup used Pins P02 and P03 key on wakeup Key on wakeup not used control bit Key on wakeup used Pins POo and P01 key on wakeup Key on wakeup not used Ooj oi2i oj 3j o
251. level L level or H level with the registers 11 and I2 ac cording to the external state and return condition return by level or edge with the register K2 before going into the RAM back up state 1 64 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS Note 5 E A Key on wakeup Operation state RAM back up mode Operation source clock l f RING POF instruction c execution f XIN Stop Note 4 Note 2 e B Operation state K Operation source clock POF instruction f RING execution e f XIN Operating Note 4 Note 3 MRo 0 Operation state s i lock l a SURE POF instruction RING Operating execution Note 4 RGoc 1 D Operation state Operation source clock POF instruction f XIN execution f RING stop RING Stop Note 4 f XIN stop Notes 1 Microcomputer starts its operation after counting f RING 120 to 144 times 2 The f XIN oscillation circuit ceramic resonance RC oscillation or quartz crystal oscillation is selected by the CMCK CRCK or CYCK instruction the start of oscillation and the operation source clock is not switched by these instructions The start stop of oscillation and the operation source is switched by register MR Surely select the f XIN oscillation circuit by executing the CMCK CRCK or CYCK instruction before clearing MR1 to 0 MR1 cannot be cleared to 0 when the oscillation circuit is not se
252. llation and the switch of system clock are not performed When the CMCK CRCK or CYCK instructions are never executed main clock f Xw cannot be used and system can be operated only by on chip oscillator The no operated clock source f RING or f Xin cannot be used for the system clock Also the clock source f RING or f Xin selected for the system clock cannot be stopped 2 On chip oscillator The clock frequency of the on chip oscillator depends on the supply voltage and the operation temperature range Be careful that margin of frequencies when designing application products When considering the oscillation stabilize wait time at the switch of clock be careful that the margin of frequencies of the on chip oscillator clock 3 External clock When the external clock signal for the main clock f Xw is used connect the clock source to Xin pin and Xour pin open In program after the CMCK instruction is executed set main clock f Xmw oscillation start to be enabled MR 0 For this product when RAM back up mode and main clock f Xin stop MRi 1 Xm pin is fixed to H in order to avoid the through current by floating of internal logic The Xin pin is fixed to H until main clock f Xin oscillation start to be valid MR 0 by the CMCK instruction from reset state Accordingly when an external clock is used connect a 1 kQ or more resistor to Xm pin in series to limit of current by competitive signal 4 Value of a p
253. llowing registers are undefined after system is released from reset After system is released from reset set initial values Register Z 2 bits Register D 3 bits Register E 8 bits Power on reset When the built in power on reset circuit is used the time for the supply voltage to rise from 0 V to the minimum rating value of the recommended operating conditions must be set to 100 us or less If the rising time exceeds 100 us connect a capacitor between the RESET pin and Vss at the shortest distance and input L level to RESET pin until the value of supply voltage reaches the minimum rating value of the recommended operating conditions Refer to section 3 1 Electrical characteristics for the reset voltage of the recommended operating conditions Rev 1 00 Aug 06 2004 RENESAS 2 69 REJO9B0175 0100Z APPLICATION 4519 Group 2 7 Voltage drop detection circuit 2 7 Voltage drop detection circuit The built in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value Figure 2 7 1 shows the voltage drop detection circuit and Figure 2 7 2 shows the operation waveform example of the voltage drop detection circuit Table 2 7 1 shows the voltage drop detection circuit operation state Refer to section 3 1 Electrical characteristics for the reset voltage of the voltage drop detection circuit Reset signal 1 i I A y
254. lock is input If an external clock is input 9 times or more and serial transmit receive is continued the receive data is transferred directly as transmit data so that be sure to control the clock externally Note also that the SIOF flag is set to 1 when a clock is counted 8 times Be sure to set the initial input level on the external clock pin to H level e Refer to section 3 1 Electrical characteristics when using serial I O with an external clock Notes on reset Register initial value The initial value of the following registers are undefined after system is released from reset After system is released from reset set initial values Register Z 2 bits Register D 3 bits Register E 8 bits Power on reset When the built in power on reset circuit is used the time for the supply voltage to rise from 0 V to the minimum rating value of the recommended operating conditions must be set to 100 us or less If the rising time exceeds 100 us connect a capacitor between the RESET pin and Vss at the shortest distance and input L level to RESET pin until the value of supply voltage reaches the minimum rating value of the recommended operating conditions Refer to section 3 1 Electrical characteristics for the reset voltage of the recommended operating conditions Rev 1 00 Aug 06 2004 RENESAS 3 18 REJO9B0175 0100Z APPENDIX 4519 Group 3 3 List of precautions 3 3 9 Notes on RAM back up 1 POF instructio
255. lso used as the built in PROM power supply input pin VPP When the VPP pin is also used as the CNVss pin Connect an approximately 5 kQ resistor to the VPP pin the shortest possible in series and also to the Vss pin When not connecting the resistor make the length of wiring between the VPP pin and the Vss pin the shortest possible refer to Figure 3 4 5 Note Even when a circuit which included an approximately 5 kQ resistor is used in the Mask ROM version the microcomputer operates correctly O Reason The VPP pin of the built in PROM version is the power source input pin for the built in PROM When programming in the built in PROM the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM Because of this noise can enter easily If noise enters the VPP pin abnormal instruction codes or data are read from the built in PROM which may cause a program runaway When the VPP pin is also used as the CNVss pin Approximately 5kQ CNVss VPP Vss In the shortest distance Fig 3 4 5 Wiring for the VPP pin of the built in PROM version Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS APPENDIX 3 4 Notes on noise 3 4 2 Connection of bypass capacitor across Vss line and VDD line Connect an approximately 0 1 uF bypass capacitor across the Vss line and the VDD line as follows Connect a bypass capacitor across the Vss pin and the VDD pin at equal length Connect
256. m sufficient evaluations for the commercial samples of the Mask ROM version Rev 1 00 Aug 06 2004 REJ09B0175 0100Z 2RENESAS HARDWARE BUILT IN PROM VERSION Table 25 Programming adapter Name of Programming Adapter M34519E8FP PCA7441 Ds De Di Do LLL Low order 5 bits Da De Di Do High order 5 bits Fig 72 PROM memory map Writing with PROM programmer Screening Leave at 150 C for 40 hours Note Verify test with PROM programmer Note Since the screening temperature is higher than storage temperature never expose the microcomputer to 150 C exceeding 100 hours Fig 73 Flow of writing and test of the product shipped in blank 1 149 CHAPTER 2 APPLICATION 2 1 I O pins 2 2 Interrupts 2 3 Timers 2 4 A D converter 2 5 Serial l O 2 6 Reset 2 7 Voltage drop detection circuit 2 8 RAM back up 2 9 Oscillation circuit APPLICATION 4519 Group 2 1 I O pins 2 1 I O pins The 4519 Group has thirty five I O pins Port Port Port Port Port Port Port This P2 is also used as Serial I O pins SCK SOUT SIN P30 is also used as INTO input pin P31 is also used as INT1 input pin P4 is also used as analog input pins AIN4Q AIN7 P6 is also used as analog input pins AINo AIN3 De is also used as CNTRO lO pin D7 is also used as CNTR1 lO pin section describes each port I O function related registers application example using each port function and
257. measurement selection bits Timer control register W6 Count source On chip oscillator f RING 16 CNTRo pin input INTO pin input Not available R W at reset 00002 TAW6 TW6A at RAM back up state retained CNTR1 pin input count edge selection bit Falling edge Rising edge CNTRO pin input count edge selection bit Falling edge Rising edge CNTR1 output auto control circuit selection bit CNTR1 output auto control circuit not selected CNTR1 output auto control circuit selected De CNTRO pin function selection bit De 1 0 CNTRO input Ooj o 2 oj o CNTRO 1 0 De input Notes 1 R represents read enabled and W represents write enabled 2 This function is valid only when the timer 3 count start synchronous circuit is selected 120 1 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7RENESAS 1 80 4519 Group Serial I O control register J1 at reset 00002 HARDWARE CONTROL REGISTERS R W at RAM back up state retained TAJA TJTA Serial lO synchronous clock selection bits J12 Synchronous clock Instruction clock INSTCK divided by 8 Instruction clock INSTCK divided by 4 Instruction clock INSTCK divided by 2 External clock SCK input Serial 1 O port function selection bits A D control register Q1 J10 Port function P20 P21 P22 selected SCK SOUT S
258. n Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back up state Note that system cannot enter the RAM back up state when executing only the POF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction 2 Key on wakeup function After checking none of the return condition for ports PO P1 INTO and INT1 specified with register K0 K2 with valid key on wakeup function is satisfied execute the POF instruction If at least one of return condition for ports with valid key on wakeup function is satisfied system returns from the RAM back upn state immediately after the POF instruction is executed 3 Return from RAM back up mode After system returns from RAM back up mode set the undefined registers and flags The initial value of the following registers are undefined at RAM back up After system is returned from RAM back up mode set initial values e Register Z 2 bits Register D 3 bits Register X 4 bits Register E 8 bits Register Y 4 bits 4 Watchdog timer The watchdog timer function is valid after system is returned from the RAM back up state When not using the watchdog timer function stop the watchdog timer function with the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back up When the watchdog timer function and RAM back up function are used at the same
259. n top view 4519 Group Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS One Time PROM 1 2 HARDWARE BLOCK DIAGRAM 4519 Group SHA X SPIOM HEE NV suq 0L X SPIOM 2618 vr 19 INOH JOUJS A IJe e 1 das 1eisi881 xoeis 1dnuejul s 8A8 8 MS 19481691 40819 suq 8 3 19181694 sig q 1Jeisibeu suq y g je1siDeu sig y v Jarsibay sua p NIV 3109 nd seues 009 L x sua 8 O I 1248S uo 8 x sig OL JeueAuoo C V ynoJro uonoejep doup eBe1joA Jojejjoso diuo uo Ou is o zuenpy oruegJe 1NOX NIX 119119 onejeuob 4909 uleis S suonounj ersydilad eulajuj suq 91 sawn Bopyarem SH 8 p Jeu L s q 8 e saw SUQ g z Jeu sua 8 Jeu Jeull p odwd OA O I Y Block diagram 4519 Group 1 3 32 NE SAS Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 4519 Group PERFORMANCE OVERVIEW Parameter HARDWARE PERFORMANCE OVERVIEW Function Number of basic instructions 153 Minimum instruction execution time 0 5 us at 6 0 MHz oscillation frequency in XIN through mode Memory sizes ROM M34519M6 6144 words X 10 bits M34519M8 E8 8192 words X 10 bits RAM M34519M6 M8 E8 384 words X 4 bits Input Output ports Do D7 1 O Input is examined
260. n aia 2 58 2 0 2 Related registers iecit E 2 59 2 5 3 Operation description ii 2 60 2 5 4 Serial I O application example sees ee eee eee eee eee ee eee 2 63 25 5 Notes OI S95 teen ii dao iria Anido 2 66 2 6 ROGOL E EU 2 67 2 6 1 Reset Circle a ia 2 67 2 6 2 Internal state at reSOtiuiiainaia at 2 68 216 3 NOLES OM USO EE 2 69 2 7 Voltage drop detection CirCuit sseccecseceseseeeeeeeeeeseeeeeeeeeeeseeseseeeeeeseeseeneeeenseeeeeneeeneeees 2 70 2 8 RAM Dack UP occ cocicccioiicci a 2 71 2 81 RAM Dacks Up MOUS ee tee tenere rne re Parm rend e Deer tern no i anan 2 71 2 0 2 Related registers viii tere eee redde dehet rere a eda eb FOE RR Oden 2 74 2 8 3 Notes ON S6 erii dr Dee god cca eee 2 78 229 meridiei 2 79 2 9 1 Oscillation sele 2 79 2 9 2 Related register incida 2 80 259 3 Notes OM USC ERE 2 81 Rev 1 00 Aug 06 2004 RENESAS i REJO9B0175 0100Z 4519 Group Table of contents CHAPTER 3 APPENDIX 3 1 Electrical characteristics eeeeeeeeeeeeeeeeeeeee eene nn AAAA 3 2 3 1 1 Absolute maximum ratings ssssssesseeeeeenenn enne nnne nnne enne nnns 3 2 3 1 2 Recommended operating conditions sss eee 3 3 3 1 3 Electrical characteristics esses eene enne nnns 3 6 3 1 4 A D converter recommended operating conditions eene 3 8 3 1 5 Voltage drop detection circuit characteristics sse 3 10 3 1 6 Basic timing Eeee l
261. n be used to transfer the contents of register 11 to register A Table 2 3 3 Interrupt control register 11 at reset 00002 at RAM back up state retained Interrupt control register 11 R W i 0 INTO pin input disabled 113 INTO pin input control bit Note 2 ud 1 INTO pin input enabled Falling waveform L level L level is recognized with Interrupt valid waveform for INTO 0 Rs xg uin at UD S the SNZIO instruction 112 pin return level selection bit Note 2 Rising waveform H level H level is recognized with the SNZIO instruction 114 INTO pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected He INTO pin Timer 1 count start 0 Timer 1 count start synchronous circuit not selected synchronous circuit selection bit Timer 1 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 112 and 113 are changed the external interrupt request flag EXFO may be set Accordingly clear EXFO flag with the SNZO instruction when the bit 0 V10 of register V1 to 0 In this time set the NOP instruction after the SNZO instruction for the case when a skip is performed with the SNZO instruction 4 Interrupt control register 12 Table 2 3 4 shows the interrupt control register 12 Set the contents of this register through register A with the TI2A instruction In addit
262. n the timer 1 count start synchronous circuit is selected 110 1 3 This function is valid only when the timer 3 count start synchronous circuit is selected 120 1 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS 1 35 4519 Group Timer control register W4 HARDWARE FUNCTION BLOCK OPERATIONS R W at RAM back up 00002 TAW4 TW4A at reset 00002 D7 1 0 CNTR1 input D7 CNTR1 pin function selection bit CNTR1 I O D7 input PWM signal PWM signal H interval expansion function invalid H interval expansion function control bit PWM signal H interval expansion function valid Stop state retained Timer 4 control bit Operating XIN input zlol lol lol o Timer 4 count source selection bit Timer control register W5 Prescaler output ORCLK divided by 2 R W at reset 00002 TAW5 TW5A at RAM back up state retained Not used This bit has no function but read write is enabled Stop Period measurement circuit control bit Operating Count source On chip oscillator f RING 16 Signal for period measurement selection bits CNTRo pin input INTO pin input Timer control register W6 Not available R W RAM k up state retained at Da UP Pelale TAW6 TW6A at reset 00002 Falling edge CNTR1 pin input count edge selection bit Rising edge Falling edge
263. nal Bit 0 1 Serial I O control register J1 Serial I O port SCK SOUT SIN Instruction clock 8 selected as synchronous clock 0 Interrupt control x x x register V2 Serial I O interrupt enable bit SNZSI instruction valid Fig 42 Serial I O connection example Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 2tENESAS Serial I O control register J1 Serial I O port SCK SOUT SIN External clock selected as synchronous clock Interrupt control register V2 Serial I O interrupt enable bit SNZSI instruction valid X Set an arbitrary value 1 55 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS Master Soo s SST instruction SRDY signal Y Sour sy AX ASXSASASASASXS Mm Mo A MA Me X Mo Ma X Ms X Me X Mr Mo M7 Contents of master serial I O register So S7 Contents of slave serial I O register Rising of Sck Serial input Falling of Sck Serial output Fig 43 Timing of serial I O data transfer Rev 1 00 Aug 06 2004 RENESAS 1 56 REJO9B0175 0100Z HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS Table 16 Processing sequence of data transfer from master to slave Master transmission Slave reception Initial setting Setting the serial I O mode register J1 and inter rupt control register V2 shown in Figure 42 Initial setting Setting serial l O mode register J1 and in
264. nal four for timer one for A D and one for serial I O Nesting 1 level Subroutine nesting 8 levels Device structure CMOS silicon gate Package 42 pin plastic molded SSOP 42P2R A Operating temperature range 20 C to 85 C Supply voltage Mask ROM version 1 8 V to 5 5 V It depends on operation source clock oscillation frequency and operating mode One Time PROM version 2 5 V to 5 5 V It depends on operation source clock oscillation frequency and operating mode Power dissipation typical value Active mode 2 8 mA Ta 25 C VDD 5V f XIN 6 MHz STCK f XIN on chip oscillator stop 70 pA Ta 25 C VoD 5V f XIN 32 kHz STCK f XIN on chip oscillator stop 150 LA Ta 25 C VDD 5V on chip oscillator is used f STCK f RING f XIN stop RAM back up mode Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 0 1 uA Ta 25 C VDD 5 V output transistors in the cut off state RENESAS 1 4 4519 Group Pin PIN DESCRIPTION Name Input Output HARDWARE PIN DESCRIPTION Function VDD Power supply Connected to a plus power supply Vss Ground Connected to a 0 V power supply CNVss CNVss Connect CNVss to Vss and apply L 0V to CNVss certainly Voltage drop detection circuit enable Input This pin is used to operate stop the voltage drop detection circuit When H level is input t
265. ncy of the on chip oscillator depends on the sup ply voltage and the operation temperature range Be careful that the margin of frequencies when designing applica tion products 3 Ceramic resonator When the ceramic resonator is used as the main clock f XIN connect the ceramic resonator and the external circuit to pins XIN and Xour at the shortest distance Then execute the CMCK in struction A feedback resistor is built in between pins XIN and XOUT Figure 57 4 RC oscillation When the RC oscillation is used as the main clock f XIN connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open Then execute the CRCK instruction Figure 58 The frequency is affected by a capacitor a resistor and a micro computer So set the constants within the range of the frequency limits 5 Quartz crystal oscillator When a quartz crystal oscillator is used as the main clock f XIN connect this external circuit and a quartz crystal oscillator to pins XIN and Xour at the shortest distance Then execute the CYCK in struction A feedback resistor is built in between pins XIN and XOUT Figure 59 6 External clock When the external clock signal for the main clock f XIN is used connect the clock source to XIN pin and XOUT pin open In program after the CMCK instruction is executed set main clock f XIN os cillation start to be enabled MR1 0 For thi
266. nd VDD using the thickest wire at the shortest distance against noise Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS 1 8 HARDWARE 4519 Group PORT BLOCK DIAGRAM PORT BLOCK DIAGRAMS Skip decision Register Y SZD instruction i Note 1 instruction Do Ds Note 2 SD instruction A Note 1 RD e Man Z 7777 Skip decision SZD instruction CLD instruction SD instruction RD instruction CLD instruction SD instruction RD instruction Notes 1 This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less 3 i represents bits 0 to 3 Port block diagram 1 Rev 1 00 Aug 06 2004 RENESAS 1 9 REJ09B0175 0100Z HARDWARE 4519 Group PORT BLOCK DIAGRAM Register Y Skip decision SZD instruction instruction j Note 1 SD instruction De CNTRO a Note 2 RD instruction Clock input for timer 1 event count or period measurement signal input C o ws Register Y Aa Note 1 SD instruction LO D7 CNTR1 RD instruction Note 2 Clock input for timer 3 event count Notes 1 4 This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less Port block diagram 2 Rev 1 00 Aug 06 2004 RENESAS 1 10 REJO9B0175 0100Z 4519 Group IAPO instruction Do
267. ndling of XIN and XOUT when operating on chip oscillator s 1 70 57 Ceramic resonator external circuit ee eee eee ee eee 1 70 58 External RC oscillation Circulo ia a 1 70 59 External quartz crystal circuit ssssssssssssssessese eene eene nnns 1 70 60 External clock input CCU coccion iii dic 1 70 61 Period measurement circuit program example sss 1 73 62 External O interrupt program example 1 ss eee ee eee eee eee eee ereer 1 74 63 External 0 interrupt program example 2 ssseee mene 1 74 64 External 0 interrupt program example 3 sesser aN nnnm 1 74 65 External 1 interrupt program example 1 sse eee ee eee eee eee eee eee eree 1 75 66 External 1 interrupt program example 2 sse 1 75 67 External 1 interrupt program example 3 seeeeessseeeseseenenee ener 1 75 68 A D converter program example 38 sse sees eee sees eee neee ennenen 1 76 69 Analog input external circuit example 1 sees sees eee eee eee eee eee eser 1 76 70 Analog input external circuit example 2 ssssssseee mene 1 76 71 Pin configuration of built in PROM version eee eee eee eee eee 1 148 7Z2 PROM MEMORY IMAP cont pete ro a ede 1 149 73 Flow of writing and test of the product shipped in blank sese eee 1 149 CHAPTER 2 APPLICATION Fig 2 1 1 Key Input Dy Key SCA eet edet hx genie ck basa aucune passed b cacas clones 2 12 Fig 2 1 2 Key sean Inpu
268. ne sided edge detected INTO pin edge detection circuit control bit Both edges detected INTO pin Timer 1 count start synchronous Timer 1 count start synchronous circuit not selected circuit selection bit Interrupt control register I2 at reset 00002 Timer 1 count start synchronous circuit selected R W at RAM back up state retained TAI2 TI2A INT1 pin input disabled INT1 pin input control bit Note 2 INT1 pin input enabled Interrupt valid waveform for INT1 pin Falling waveform L level L level is recognized with the SNZI1 instruction return level selection bit Note 2 Rising waveform H level H level is recognized with the SNZI1 instruction One sided edge detected INT1 pin edge detection circuit control bit Both edges detected INT1 pin Timer 3 count start synchronous Timer 3 count start synchronous circuit not selected circuit selection bit Notes 1 R represents read enabled and W represents write enabled Timer 3 count start synchronous circuit selected 2 When the contents of 112 113 122 and 123 are changed the external interrupt request flag EXFO EXF1 may be set Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS 1 28 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS 4 Notes on External 0 interrupt Note on bit 2 of register I1 O Note 1 on bit 3 of register 11 When the interrupt valid waveform of the P30 INTO
269. ng avoid a timing when timer 4 underflows Timer 4 starts counting after the following process O set data in timer 4 Q set count source by bit O of register W4 and set the bit 1 of register W4 to 1 When a value set in reload register R4L is n timer 4 divides the count source signal by n 1 n 0 to 255 Once count is started when timer 4 underflows the next count pulse is input after the contents of timer 4 becomes 0 the timer 4 interrupt request flag T4F is set to 1 new data is loaded from reload register RAL and count continues auto reload function The PWM signal generated by timer 4 can be output from CNTR1 pin by setting bit 3 of the timer control register W4 to 1 Timer 4 can control the PWM output to CNTR1 pin with timer 3 by setting bit 1 of the timer control register W6 to 1 1 38 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 4519 Group 7 Period measurement function Timer 1 period measurement circuit Timer 1 has the period measurement circuit which performs timer count operation synchronizing with the one cycle of the signal di vided by 16 of the on chip oscillator De CNTRO pin input or P30 INTO pin input one cycle H or L pulse width at the case of a P30 INTO pin input When the target signal for period measurement is set by bits 0 and 1 of register W5 a period measurement circuit is started by setting the bit 2 of register W5 to 1 Then if a XIN input is set as
270. ng the timer 1 interrupt request flag T1F is not set by the timer 1 underflow signal it is the flag for detecting the completion of period measurement O When a period measurement circuit is used select the sufficiently higher speed frequency than the signal for measurement for the count source of a timer 1 Rev 1 00 Aug 06 2004 RENESAS 3 15 REJO9B0175 0100Z 4519 Group APPENDIX 3 3 List of precautions O When the signal for period measurement is De CNTRO pin input do not select De CNTRO pin input as timer 1 count source The Xin input is recommended as timer 1 count source at the time of period measurement circuit use e When the input of P3vINTO pin is selected for measurement set the bit 3 of a register I1 to 1 and set the input of INTO pin to be enabled O Start timer operation immediately after operation of a period measurement circuit is started O Even when the edge for measurement is input by timer operation is started from the operation of period measurement circuit is started timer 1 is not operated When data is read from timer 1 stop the timer 1 and the period measurement circuit and then execute the data read instruction Depending on the state of timer 1 the timer 1 interrupt request flag T1F may be set to 1 when the period measurement circuit is stopped by clearing bit 2 of register W5 to 0 In order to avoid the occurrence of an unexpected interrupt disable the timer 1 interrup
271. ng a data store sequence to stack register Write the branch instruction to an interrupt service routine at an in terrupt address Use the RTI instruction to return from an interrupt service routine Interrupt enabled by executing the EI instruction is performed after executing 1 instruction just after the next instruction is executed Accordingly when the EI instruction is executed just before the RTI instruction interrupts are enabled after returning the main routine Refer to Figure 13 Main routine Interrupt service routine Interrupt occurs Interrupt is enabled Interrupt enabled state Fig 13 Program example of interrupt processing Rev 1 00 Aug 06 2004 REJ09B0175 0100Z 132 NE SAS HARDWARE FUNCTION BLOCK OPERATIONS Program counter PC Each interrupt address The address of main routine to be executed when returning Interrupt enable flag INTE 0 Interrupt disabled Interrupt request flag only the flag for the current interrupt Source 0 Data pointer carry flag registers A and B skip flag Stored in the interrupt stack register SDP automatically Fig 14 Internal state when interrupt occurs Activated condition Request flag Enable bit Enable flag state retained oo EXFO INT1 pin interrupt O waveform input EXF1 Timer 1 underflow INTO pin interrupt waveform input Address 0 in page 1
272. ng example when a serial I O of master side is not used Rev 1 00 Aug 06 2004 RENESAS 2 64 REJO9B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO O Disable Interrupts Serial I O interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI Interrupt control register V2 b3 Serial I O interrupt occurrence disabled TV2A Q Set Port Port for control signal is set to H output Register Y Specify bit position of port D TYA Port D3 output latch Set to H output SD Port output structure control register FR1 b3 Port D3 CMOS output selected Set Serial lO TJ1A b3 b2 External clock is selected for synchronous clock Serial I O control regsiter Jl b1 bO Serial I O ports Sck Sour SIN selected T Clear Interrupt Request Serial I O interrupt activated condition is cleared Serial 1 O transmit receive completion flag SIOF LO Serial 1 O interrupt activated condition cleared SNZSI When is executed considering the skip of the next instruction according to the flag SIO insert the NOP instruction after the SNZSI instruction O Set Interrupts The Serial I O interrupt which is temporarily disabled is enabled b3 b0 Interrupt control register V2 1 x X X b3 Serial I O interrupt occurrence enabled TV2A Interrupt enable flag INTE 1 All interrupts enabled El us when the interrupt request is cleared
273. nging the contents of M DP X E X EXOR with the contents of register A an exclusive j 0to 15 OR operation is performed between regis Men 1 ter X and the value j in the immediate field and stores the result in register X Adds 1 to the contents of register Y As a re sult of addition when the contents of register Y is 0 the next instruction is skipped when the contents of register Y is not 0 the next instruction is executed Rev 1 00 Aug 06 2004 RENESAS 1 129 REJO9B0175 0100Z 4519 Group MACHINE INSTRUCTIONS INDEX BY TYPES HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES Parameter Instruction code 5 5 o i 99 82 Function a a Type of MODE Hexadecimal E E gt NA D9 Ds D7 De Ds D4 Ds D2 Di Do 3 3 instruction notation z TAB 0 00 00 1 1 1 1 0 01E 1 1 A B TBA 0 00000 1 1 1 0 00 E 1 1 B A TAY o 0 0 O0 O 1 1d 1d 1 4 01 F 1 1 A e Y TYA 0 000001 1 0 0 00 C 1 1 Y A TEAB 0 0000 1 1 0 1 0 TAIA 1 E7 E4 B S Es Eo A E TABE 0 0 00 1 0 1 0 1 0 02 A 1 1 B lt E7 E4 gt A E3 Eo 2 ITDA 0 0 00 1 0 1 0 0 1 029 1 1 DR2 DRo e A2 A0 o TAD 0 0 0 1 0 1 0 0 0 1 05 1 1 1 A2 A0 DR2 DRo D 3 A3 0 ra TAZ 0 0 0 1 0 1 1 0 0 1 1 053 1 1 A1 Ao Z1 Zo A3 A2 0 TAX 0 0 0 1 0 100 1 0 052 1 1 A e 09 TASP 0 00 1 01 000 0 050 1 1 A2 Ao SP2 SPo A3 0 LXY x y 1 1 x3 x2 x1 xo y3 y
274. nnel open drain output b3 b0 Port output structure control register FR2 X 0 X X b2 N channel open drain output selected TFR2A b3 b0 Timer control register W6 X Xx Xx 1 b0 CNTRO output port set TW6A Set Timer Value and Prescaler Value Timer 2 and prescaler count times are set The formula is shown A below Timer 2 reload register R2 2916 Timer count value 41 set T2AB Prescaler reload register RPS 0316 Prescaler count value 3 set TPSAB O Clear Interrupt Request Timer 2 interrupt activated condition is cleared Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared SNZT2 Note when the interrupt request is cleared When O is executed considering the skip of the next instruction according to the interrupt request flag T2F insert the NOP instruction after the SNZT2 instruction O Start Timer Operation and Prescaler Operation Timer 2 and prescaler temporarily stopped are restarted b0 Timer control register W2 1 b2 Timer 2 operation start TW2A b0 Timer control register PA 1 Prescaler start TPAA Enable Interrupts The Timer 2 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V1 1 X X X b3 Timer 2 interrupt occurrence enabled TV1A Interrupt enable flag INTE 1 All interrupts enabled El Buzzer output start l Stop CNTRO Output CNTRO I O port is set
275. notes 2 1 1 I O ports 1 Port PO Port PO is a 4 bit I O port Port PO has the key on wakeup function which turns ON OFF with register KO and pull up transistor which turns ON OFF with register PUO O Input In the following conditions the pin state of port PO is transferred as input data to register A when the IAPO instruction is executed e Set bit FROo or bit FRO1 of register FRO to 0 according to the port to be used e Set the output latch of specified port POi i20 1 2 or 3 to 1 with the OPOA instruction If FROo or FRO1 is 0 and the output latch is 0 0 is output to specified port PO If FROo or FRO1 is 1 the output latch value is output to specified port PO O Output The contents of register A is set to the output latch with the OPOA instruction and is output to port PO N channel open drain or CMOS can be selected as the output structure of port PO in 2 bits unit by setting FROo or FROt 2 Port P1 Port P1 is a 4 bit I O port Port P1 has the key on wakeup function which turns ON OFF with register KO and pull up transistor which turns ON OFF with register PUT O Input In the following conditions the pin state of port P1 is transferred as input data to register A when the IAP1 instruction is executed e Set bit FRO2 or bit FRO3 of register FRO to 0 according to the port to be used e Set the output latch of specified port P1i i0 1 2 or 3 to 1 with the OP1A instruction If FRO
276. ns equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions F
277. nsmit receive is continued the receive data is transferred directly as transmit data so that be sure to control the clock externally Note also that the SIOF flag is set to 1 when a clock is counted 8 times Be sure to set the initial input level on the external clock pin to H level e Refer to section 3 1 Electrical characteristics when using serial I O with an external clock Rev 1 00 Aug 06 2004 RENESAS 2 66 REJ09B0175 0100Z APPLICATION 4519 Group 2 6 Reset 2 6 Reset System reset is performed by applying L level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied the value of supply voltage is the minimum value or more of the recommended operating conditions Then when H level is applied to RESET pin the program starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time On chip oscillator internal oscillator clock is counted for 120 to 144 times Figure 2 6 2 shows the structure of reset pin and its peripherals and power on reset operation 2 6 1 Reset circuit The 4519 Group has the voltage drop detection circuit 1 Power on reset Reset can be automatically performed at power on power on reset by the built in power on reset circuit When the built in power on reset circuit is used the time for the supply voltage to rise from O V to the minimum rating value of the recommended operating conditions must be set to 100 us or
278. ntents of carry flag CY to the right Sets 1 the contents of bit j bit specified by the value j in the immediate field of M DP Clears 0 the contents of bit j bit specified by the value j in the immediate field of M DP Skips the next instruction when the contents of bit j bit specified by the value j in the immediate field of M DP is 0 Executes the next instruction when the contents of bit j of M DP is 1 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Skips the next instruction when the contents of register A is equal to the contents of M DP Executes the next instruction when the contents of register A is not equal to the contents of M DP Skips the next instruction when the contents of register A is equal to the value n in the immediate field Executes the next instruction when the contents of register A is not equal to the value n in the immediate field RENESAS 1 133 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code o 15 25 29 Function 95099 Type of Mnemonic Hexadecimal E gt l De Ds D7 De D5 D4 D3 D2 Di Do 2 2 instruction notation Ba 0 1 1 a6 a5 a4 a3 a2 ai ao 18a 1 1 PCL lt ae ao a 5 BLp a 0 00 1 1 1 p4p3p2pt po 0 E p 2 2 PCH p Note 2 p PCL ae ao o o 1 0 p5 a6 a5 a a3 a2 ai ao 2 pa lt a e 5 BLA p 0 00 0 01 0 0 0 0 010 2 2 PCH
279. nterrupt control register V2 Set the contents of this register through register A with the TV2A instruction In addition the TAV2 instruction can be used to transfer the contents of register V2 to register A Table 2 3 2 Interrupt control register V2 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZSI instruction is valid 1 Interrupt enabled SNZSI instruction is invalid Note 2 0 Interrupt disabled SNZAD instruction is valid 1 Interrupt enabled SNZTAD instruction is invalid Note 2 0 Interrupt disabled SNZTA instruction is valid 1 0 Interrupt control register V2 R W V23 Serial I O interrupt enable bit V22 A D interrupt enable bit V21 Timer 4 i le bi aill Interrupt enabled SNZTA instruction is invalid Interrupt disabled SNZT3 instruction is valid 1 Interrupt enabled SNZT3 instruction is invalid Notes 1 R represents read enabled and W represents write enabled 2 These instructions are equivalent to the NOP instruction 3 When timer is used V23 and V22 is not used wa Note 2 V20 Timer 3 interrupt enable bit Note 2 Rev 1 00 Aug 06 2004 RENESAS 2 32 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers 3 Interrupt control register I1 Table 2 3 3 shows the interrupt control register 11 Set the contents of this register through register A with the TI1A instruction In addition the TAI1 instruction ca
280. nterrupt control registers miii 1 24 Table 7 External interrupt activated conditions sese eee ee eee eee 1 26 Table 8 External interrupt control register eene 1 28 Table 9 Funcion related tIImers uou coi etre ee tlt rene de d e teh i allas 1 32 Table 10 Timer related registers sssssssssssssssseseeee eene nnne 1 35 Table 11 A D converter characteristics c 0ooooninnnncccnnnniccccnnnnnccnnnnn crono cnn nn non rn eene nennen 1 47 Table 12 A D Control TegIStO Scotia 1 48 Table 13 Change of successive comparison register AD during A D conversion 1 49 Sable 14 Serial eh PINS MEE 1 53 Table 15 Serial l O control register accionista cda nna adde E Ree a 1 53 Table 16 Processing sequence of data transfer from master to slave suusss 1 57 Table 17 Port state at TOSCO acid 1 59 Table 18 Voltage drop detection circuit operation state sese eee eee eee eee 1 62 Table 19 Functions and states retained at RAM back up s 1 63 Table 20 Return source and return condition sse 1 64 Table 21 Key on wakeup control register pull up control register sees eee eee eee 1 66 Table 22 Key on wakeup control register pull up control register sse eee eee eee eee 1 67 Table 23 Glock conttrol registers e ecce retener re cet Peru er sad eu rrt gea Ebr eue 1 71 Table 24 Product of built in PROM version esse sees eee eee eee eee 1 148 Table 25 Programming adapter essrecer sics cnn rre 1 1
281. nterrupt name Interrupt request flag Skip instruction Interrupt enable bit External 0 interrupt EXFO SNZO Vio External 1 interrupt EXF1 SNZ1 V11 Timer 1 in terrupt TIF SNZT1 V12 Timer 2 in terrupt T2F SNZT2 V13 Timer 3 in terrupt TSF SNZT3 V20 Timer 4 in terrupt T4F SNZT4 V21 A D interrupt ADF SNZAD V22 Serial I O interrupt SIOF SNZSI Table 5 Interrupt enable bit function V23 7tENESAS Interrupt enable bit Occurrence of interrupt 1 Enabled 0 Disabled Skip instruction Invalid Valid 1 22 4519 Group 4 Internal state during an interrupt The internal state of the microcomputer during an interrupt is as fol lows Figure 14 Program counter PC An interrupt address is set in program counter The address to be executed when returning to the main routine is automatically stored in the stack register SK Interrupt enable flag INTE INTE flag is cleared to 0 so that interrupts are disabled Interrupt request flag Only the request flag for the current interrupt source is cleared to 0 Data pointer carry flag skip flag registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register SDP 5 Interrupt processing When an interrupt occurs a program at an interrupt address is ex ecuted after branchi
282. o 15 Description Loads the value x in the immediate field to register X and the value y in the immediate field to register Y When the LXY instruc tions are continuously coded and executed only the first LXY instruction is executed and other LXY instructions coded continu ously are skipped LZ z Load register Z with z Instruction Dg Do Number of Number of Flag CY Skip condition code o o o 1 o o 1 o z z 8 MS Ie eS 2 z 116 1 1 Operation Z zz 0to3 Grouping RAM addresses Description Loads the value z in the immediate field to register Z Rev 1 00 Aug 06 2004 RENESAS 1 98 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued NOP No OPeration Instruction Dg Do Number of Number of Flag CY Skip condition words cycles code 0101010101091010 0 lee 1 1 Operation PC PC 1 Grouping Other operation Description No operation Adds 1 to program counter value and others remain unchanged OPOA Output port PO from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition words cycles coge 1101019011101010 0 0 he 1 1
283. o this pin the circuit starts operating When L level is input to this pin the circuit stops operating Reset input output 1 0 An N channel open drain l O pin for a system reset When the SRST instruction watchdog timer the built in power on reset or the voltage drop detection circuit causes the system to be reset the RESET pin outputs L level Main clock input Input Main clock output Output I O pins of the main clock generating circuit When using a ceramic resonator connect it between pins XIN and Xour When using a 32 kHz quartz crystal oscillator connect it between pins XIN and XOUT A feedback resistor is built in between them When using the RC oscillation connect a resistor and a capacitor to XIN and leave XOUT pin open I O port D Input is examined by skip decision 1 0 Each pin of port D has an independent 1 bit wide I O function The output structure can be switched to N channel open drain or CMOS by software For input use set the latch of the specified bit to 1 and select the N channel open drain Ports De D7 is also used as CNTRO pin and CNTR1 pin respectively I O port PO Port PO serves as a 4 bit I O port The output structure can be switched to N channel open drain or CMOS by software For input use set the latch of the specified bit to 1 and select the N channel open drain Port PO has a key on wakeup function and a pull up function Both functions can be switch
284. of the comparator register is retained even when the mode is switched to the A D conversion mode Q13 0 because it is separated from the successive comparison register AD Also the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits Fig 35 A D conversion circuit structure Rev 1 00 Aug 06 2004 ENESAS REJ09B0175 0100Z 1 47 4519 Group Table 12 A D control registers A D control register Q1 at reset 00002 HARDWARE FUNCTION BLOCK OPERATIONS R W AM k up i at R back up state retained TAQ1 TQ1A A D conversion mode A D operation mode selection bit Comparator mode Q12 Q11 Q10 Analog input pins 0 0 0 NO N1 N2 Analog input pin selection bits N3 N4 N5 N6 A D control register Q2 at reset 00002 I IE EI EE gt N7 R W at RAM back up state retained TAQ2 TQ2A P40 AIN4 P41 AIN5 P42 AIN6 P43 AIN7 P40 P41 P42 P43 pin function selection bit AIN4 AIN5 AIN6 AIN7 P62 AIN2 P63 AIN3 pin function selection bit P62 P63 AIN2 AIN3 P61 P61 AIN1 pin function selection bit AIN1 P60 a o 2joi2liloi i2 o P60 AlNO pin function selection bit A D control register Q3 at reset 00002 AINO R W t RAM back up state retained n TAQ3 TQ3A Not used This bit has no function but read write
285. on Transfers the contents of register A to inter rupt control register V1 TV2A Transfer data to register V2 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition words cycles code 0 ojojo 1 1 1 1 1 0 0 3 E hes 4 1 1 Operation V2 A Grouping Interrupt operation Description Transfers the contents of register A to inter rupt control register V2 TW1A Transfer data to register W1 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition code lolo o lo o li lili ol l2lo words oyces 2 16 1 1 Operation W1 A Grouping Timer operation Description Transfers the contents of register A to timer control register W1 TW2A Transfer data to register W2 from Accumulator Instruction Do Do Number of Number of Flag CY Skip condition code tTeTe Te e oe sTi Ta 2 o E 09 eyes 1 1 Operation W2 A Grouping Timer operation Description Transfers the contents of register A to timer control register W2 Rev 1 00 Aug 06 2004 7RENESAS REJO9B0175 0100Z 1 126 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TW3A Transfer data to register W3 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip c
286. on voltage the ADF flag is set to 4 13 Notes for the use of A D conversion TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A si multaneously the low order 2 bits of register A is 0 Operation mode of A D converter Do not change the operating mode both A D conversion mode and comparator mode of A D converter with the bit 3 of register Q1 while the A D converter is operating Clear the bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to A D conver sion mode The A D conversion completion flag ADF may be set when the operating mode of the A D converter is changed from the com parator mode to the A D conversion mode Accordingly set a value to the register Q1 and execute the SNZAD instruction to clear the ADF flag ADST instruction 78 2 machine cycles 1 f ADCK Comparison result store flag ADF DAC operation signal Fig 38 Comparator operation timing chart Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS Comparator operation completed The value of ADF is determined 1 51 4519 Group 14 Definition of A D converter accuracy The A D conversion accuracy is defined below refer to Figure 39 Relative accuracy O Zero transition voltage VoT This means an analog input voltage when the actual A D con version
287. on wakeup functions and output structure selection functions P22 SIN P20 Sck P21 SoUT N channel open drain P32 P33 P30 INTO P31 INT1 N channel open drain P40 AIN4 P43 AIN7 N channel open drain P50o P53 N channel open drain CMOS Output structure selection function programmable Rev 1 00 Aug 06 2004 REJO9B0175 0100Z P60 AINO P63 AIN3 N channel open drain 2RENESAS 1 7 4519 Group CONNECTIONS OF UNUSED PINS Connection HARDWARE CONNECTION OF UNUSED PINS Usage condition Open Internal oscillator is selected Open Internal oscillator is selected RC oscillator is selected External clock input is selected for main clock Open Connect to Vss N channel open drain is selected for the output structure De CNTRO Open CNTRO input is not selected for timer 1 count source Connect to Vss N channel open drain is selected for the output structure D7 CNTR1 Open CNTR1 input is not selected for timer 3 count source Connect to Vss N channel open drain is selected for the output structure P00o P03 Open The key on wakeup function is not selected Connect to Vss N channel open drain is selected for the output structure The pull up function is not selected The key on wakeup function is not selected Open The key on wakeup function is not selected Conn
288. ondition Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Returns from interrupt service routine to main routine Returns each value of data pointer X Y Z carry flag skip status NOP mode status by the continuous de scription of the LA LXY instruction register A and register B to the states just before interrupt Returns from subroutine to the routine called the subroutine Returns from subroutine to the routine called the subroutine and skips the next instruction at uncondition RENESAS 1 135 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code l5 9 3 Function i os 25 Type of MES Hexadecimal E 2 E gt l De Ds D7 De Ds D4 D3 D2 Di Do 3 3 instruction notation Z z DI 0 0 00 1 0 0 004 1 1 INTE 0 EI 0 0 0 0 1 0 1 005 1 1 INTE 1 SNZO 0 1 1 1 0 0 0 03 8 1 1 V1o 2 0 EXFO 1 After skipping EXFO 0 Vio 1 SNZO NOP SNZ1 0 1 1 1 0 0 1 039 1 1 V11 20 EXF1 21 After skipping EXF1 0 V11 2 1 SNZ1 NOP SNZIO 0 1 1 1 0 1 0 03A 1 1 112 1 INTO H 1220 INTO L 7 c 2 S amp SNZI1 0 1 1 1 0 1 1 03 B 1 1 l222 1 INT1 H a 2 9 122 2 0 INT1 L TAV1 0 0 1 0 1 0 0 054 1 1 A V1 TV1A 0 1 1 1 1 1 1 0 3 F 1 1 V1 e A TAV2 0 0 1 0 1 0 1 055 1 1 A lt V2 TV2A 0 1 1 1 0 03E 1 1 V2 A TAI 1 0 1 0 0 141 1 253 1
289. ondition words cycles coge i Jojo o 0 1 0 0 0 0 2 1 0 lus 4 1 1 Operation W3 lt A Grouping Timer operation Description Transfers the contents of register A to timer control register W3 TWAA Transfer data to register W4 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition words cycles code 1 ojo o o 1 0o 0 0 1 2 1 the 4 1 1 Operation W4 A Grouping Timer operation TW5A Transfer data to register W5 from Accumulator Description Transfers the contents of register A to timer control register W4 Instruction D9 Do Number of Number of Flag CY Skip condition code words cycles 11010 0 2 j 1 1 Operation W5 A Grouping Timer operation TW6A Transfer data to register W6 from Accumulator control register W5 Description Transfers the contents of register A to timer REJO9B0175 0100Z Instruction Do Do Number of Number of Flag CY Skip condition code words cycles 1 00 1 16 1 1 Operation W6 A Grouping Timer operation Description Transfers the contents of register A to timer control register W6 Rev 1 00 Aug 06 2004 RENESAS 1 127 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TYA Transfer data to registe
290. only at once The oscillation cir cuit corresponding to the first executed one of these instructions is valid Execute the CMCK CRCK or CYCK instruction in the initial setting routine of program executing it in address 0 in page 0 is recom mendea Also when the CMCK CRCK or CYCK instruction is not executed in program this MCU operates by the on chip oscillator i On chip oscillator operation Main clock ceramic resonance Main clock RC oscillation circuit Main clock Quartz crystal circuit On chip oscillator operating On chip oscillator operating On chip oscillator operating System clock on chip oscillator clock System clock on chip oscillator clock System clock on chip oscillator clock Set the main clock f XiN oscillation by bit 1 of register MR Switch the system clock by bit 0 of register MR Also when system clock is switched after main clock oscillation is started generate the oscillation stabilizing wait time by program if necessary Set the on chip oscillator clock oscillation by register RG Fig 55 Switch to ceramic resonance RC oscillation quartz crystal oscillation Rev 1 00 Aug 06 2004 RENESAS 1 69 REJ09B0175 0100Z 4519 Group 2 On chip oscillator operation When the MCU operates by the on chip oscillator as the main clock f XiN without using the ceramic resonator RC oscillator or quartz crystal oscillation leave XIN pin and Xour pin open Figure 56 The clock freque
291. ons 3 Mask ROM version Ta 20 C to 85 C VDD 1 8 to 5 5 V unless otherwise noted One Time PROM version Ta 20 C to 85 C VDD 2 5 to 5 5 V unless otherwise noted Symbol Parameter Conditions APPENDIX 3 1 Electrical characteristics f XIN Oscillation frequency with a quartz crystal oscillator Mask ROM version VDD 2 0 to 5 5 V One Time PROM version VDD 2 5 to 5 5 V f CNTR Timer external input frequency CNTRO CNTR1 iw CNTR Timer external input period H and L pulse width CNTRO CNTR1 STCK f Sck Serial I O external input frequency Sck Serial I O external input frequency H and L pulse width Sck ASTEK Power on reset circuit valid supply voltage rising time Rev 1 00 Aug 06 2004 REJ09B0175 0100Z Mask ROM version VDD 0 gt 1 8V One Time PROM version VDD20 2 5V 34 NE SAS 3 5 APPENDIX 4519 Group 3 1 Electrical characteristics 3 1 3 Electrical characteristics Table 3 1 5 Electrical characteristics 1 Mask ROM version Ta 20 C to 85 C VDD 1 8 to 5 5 V unless otherwise noted One Time PROM version Ta 20 C to 85 C VDD 2 5 to 5 5 V unless otherwise noted Limits Typ Parameter Test conditions H level output voltage DD 5V loH 10 mA PO P1 P5 Do D7 CNTRO CNTR1 loH 3 mA DD lt 2 Y loH 5 mA loH
292. ontrols the return condition and valid waveform level selection for port PO Set the contents of this register through register A with the TK1A instruction In addition the TAK1 instruction can be used to transfer the contents of register K1 to register A Key on wakeup control register K2 Register K2 controls the INTO and INT1 key on wakeup functions and return condition function Set the contents of this register through register A with the TK2A instruction In addition the TAK2 instruction can be used to transfer the contents of register K2 to register A Table 20 Return source and return condition Return source Return condition HARDWARE FUNCTION BLOCK OPERATIONS Pull up control register PUO Register PUO controls the ON OFF of the port PO pull up transis tor Set the contents of this register through register A with the TPUOA instruction In addition the TAPUO instruction can be used to transfer the contents of register PUO to register A Pull up control register PU1 Register PU1 controls the ON OFF of the port P1 pull up transis tor Set the contents of this register through register A with the TPU instruction In addition the TAPU1 instruction can be used to transfer the contents of register PUO to register A External interrupt control register 11 Register 11 controls the valid waveform of external 0 interrupt in put control of INTO pin and return input level Set the contents of this register through
293. onverter A D conversion mode is selected to A D operation mode Analog input pin Alno is selected Instruction clock 6 is selected for A D converter operation clock b3 bO A D control register Q2 X X X 1 b0 Alno pin function selected TQ2A b3 b0 A D control register Q1 O O O O b3 A D conversion selected b2 b0 AINo selected TQ1A b3 bo TQ3A A D control register Q3 xX O b2 A D converter operation clock Instruction clock b1 b0 Frequency divided by 6 is selected for A D converter operation clock G Clear Interrupt Request A D interrupt activated condition is cleared A D conversion completion flag ADF A D interrupt activated condition cleared SNZAD y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the flag ADF insert the NOP instruction after the SNZAD instruction y 0__ Y When interrupt is not used When interrupt is used Set Interrupt 5 Set Interrupt Interrupts except A D conversion is enabled El A D interrupt temporarily disabled is enabled b3 b0 Interrupt control register V2 X 1 X X b2 A D interrupt occurrence enabled TV2A Interrupt enable flag INTE 1 All interrupt enabled El y SR O Start A D Conversion A D conversion operation is started ADST y When interrupt is not used When int
294. or controlling CPU The instruction clock INSTCK is a signal derived by dividing the System clock STCK by 3 The one instruction clock cycle gen erates the one machine cycle Machine cycle The machine cycle is the standard cycle required to execute the instruction Operation mode N N through mode ING n chip oscillator through mode N 2 N divided by 2 mode ING 2 N 4 N divided by 4 mode ING 4 n chip oscillator divided by 4 mode N 8 X O X On chip oscillator divided by 2 mode X O X N divided by 8 mode X o lx lo xoxo alo i2joi2ilo 2a o X 0 or 1 Note The f RING 8 is selected after system is released from reset When on chip oscillator clock is selected for main clock set the on chip oscillator to be operating state Rev 1 00 Aug 06 2004 REJO9B0175 0100Z On chip oscillator divided by 8 mode RENESAS 1 6 4519 Group PORT FUNCTION Output structure Control instructions Control registers HARDWARE PORT FUNCTION Remark Do Ds De CNTRO D7 ONTR1 N channel open drain CMOS SD RD SZD CLD FR1 FR2 W6 WA Output structure selection function programmable P00 P03 N channel open drain CMOS OPOA IAPO Built in programmable pull up functions key on wakeup functions and output structure selection functions N channel open drain CMOS Built in programmable pull up functions key
295. or read the data after examining the completion of the transmit receive operation with the SNZSI instruction without using an interrupt Also the SIOF flag is cleared to 0 when an interrupt occurs or the SNZSI instruction is executed Set the control signal pin level to H after the receive operation is completed Note Repeat steps O through to transmit receive multiple data in succession 2 5 4 Serial I O application example 1 Serial I O Outline The 4519 Group can communicate with peripheral ICs Specifications Figure 2 5 2 Serial I O connection example Figure 2 5 5 shows the setting example when a serial I O interrupt of master side is not used and Figure 2 5 6 shows the slave serial I O setting example Rev 1 00 Aug 06 2004 RENESAS 2 63 REJO9B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO O Disable Interrupts Note Serial I O interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI Interrupt control register V2 b3 Serial I O interrupt occurrence disabled TV2A O Set Port Port for control signal is set to input Register Y Specify bit position of port D TYA Port D3 output latch Set to input SD TFR1A Port output structure control register FR1 b3 Port D3 N channel open drain output selected Set Serial I O TJ1A b3 b2 Instruction clock divided by 4 is selected for Serial I O control regsiter
296. or the country of destination is prohibited Please contact Renesas Technology Corp for further details on these materials or the products contained therein REVISION HISTORY 4519 Group User s Manual Summary 1 00 Aug 06 200 First edition issued BEFORE USING THIS USER S MANUAL This user s manual consists of the following three chapters Refer to the chapter appropriate to your conditions such as hardware design or software development 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions based mainly on setting examples of related registers CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer such as the electrical characteristics the list of registers As for the Mask ROM confirmation form the ROM programming confirmation form and the Mark specification form which are to be submitted when ordering refer to the Renesas Technology Corp Hompage http www renesas com en rom As for the Development tools and related documents refer to the Product Info 4519 Group http www renesas com eng products mpumcu specific Icd_mcu expand e4519 htm of Renesas Technology Corp Homepage 4519 Group Table of contents Table of contents CHAPTER 1 HARDW
297. orts P30 and P3 can be used even when INTO and INT1 pins are selected e Be careful that the input of ports P2o P22 can be used even when Sm Sour and Scx pins are selected Be careful that the input output of port Ds can be used even when input of CNTRO pin is selected Be careful that the input of port De can be used even when output of CNTRO pin is selected Be careful that the input output of port Dz can be used even when input of CNTR1 pin is selected Be careful that the input of port D7 can be used even when output of CNTR1 pin is selected 4 Connection of unused pins Table 3 3 1 shows the connections of unused pins 5 SD RD SZD instructions When the SD RD or SZD instructions is used do not set 10002 or more to register Y 6 Port P30o INTO pin When the RAM back up mode is used by clearing the bit 3 of register 11 to 0 and setting the input of INTO pin to be disabled be careful about the following note When the input of INTO pin is disabled register 11s 0 clear bit O of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode 7 Port P31 INT1 pin When the RAM back up mode is used by clearing the bit 3 of register 12 to 0 and setting the input of INT1 pin to be disabled be careful about the following note e When the input of INT1 pin is disabled register 123 0 clear bit 2 of register K2 to 0 to invalidate the key on wakeup before s
298. ote 4 Notes 1 Microcomputer starts its operation after counting f RING 120 to 144 times 2 The f XIN oscillation circuit ceramic resonance RC oscillation or quartz crystal oscillation is selected by the CMCK CRCK or CYCK instruction the start of oscillation and the operation source clock is not switched by these instructions The start stop of oscillation and the operation source is switched by register MR Surely select the f XIN oscillation circuit by executing the CMCK CRCK or CYCK instruction before clearing MR1 to 0 MR1 cannot be cleared to 0 when the oscillation circuit is not selected 3 Generate the wait time by software until the oscillation is stabilized and then switch the system clock 4 Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back up state 5 System returns to state A certainly when returning from the RAM back up mode However the selected contents CMCK CRCK CYCK instruction execution state of f XIN oscillation circuit is retained Fig 2 8 1 State transition 2 8 1 RAM back up mode APPLICATION 2 8 RAM back up E RAM back up mode f RING stop f XIN stop The system goes into RAM back up mode when the POF instruction is executed immediately after the EPOF instruction is executed Table 2 8 1 shows the function and state retained at RAM back up mode Also Table 2 8 2 shows the return source from this state 1 RAM back up mode
299. ount start synchronous circuit not selected O Set Timer Value Timer 1 count time is set Timer 1 reload register R1 FF16 Timer count value 255 set T1AB Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction O Start Period Measurement Circuit The period measurement circuit operation is started b3 Timer control register W5 110 b2 period measurement circuit operating TW5A Start Timer Operation Timer 1 temporarily stopped is restarted Timer control register W1 b2 Timer 1 operation start TW1A O Enable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V1 X 1 X X bt Timer 1 interrupt occurrence enabled TV1A Interrupt enable flag INTE All interrupts enabled El Timer 1 count started synchronizing with a fall of CNTRO pin input X it can be 0 or 1 instruction Fig 2 3 9 Period measurement of CNTRO pin input setting example 1 Rev 1 00 Aug 06 2004 RENESAS 2 45 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers
300. oup has a clock synchronous serial I O which can be used to transmit and receive 8 bit data This section describes serial I O functions related registers application examples using serial I O and notes 2 5 1 Serial 1 O functions Serial I O consists of the serial I O register Sl serial I O control register J1 serial I O transmit receive completion flag SIOF and serial I O counter A clock synchronous serial I O uses the shift clock generated by the clock control circuit as a synchronous clock Accordingly the data transmit and receive operations are synchronized with this shift clock In transmit operation data is transmitted bit by bit from the Sour pin synchronously with the falling edges of the shift clock In receive operation data is received bit by bit from the SIN pin synchronously with the rising edges of the shift clock Note 4519 Group only supports LSB first transmit and receive B Shift clock When using the internal clock of 4519 Group as a synchronous clock eight shift clock pulses are output from the Sck pin when a transfer operation is started Also when using some external clock as a synchronous clock the clock that is input from the SCK pin is used as the shift clock B Data transfer rate baudrate When using the internal clock the data transfer rate can be determined by selecting the instruction clock divided by 2 4 or 8 When using an external clock the clock frequency input to the Sck pin determines the data
301. ous means including the Renesas Technology Corp Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all informa tion as a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liabil ity or other loss resulting from the information contained herein Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corp is necessary to reprint or repro duce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be im ported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and
302. p Description Branch out of a page Branches to address PCL ae to ao a in page p Note p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8 BLA p Branch Long to address D A in page p Instruction Dg Do Number of Number of Flag CY Skip condition code ololo lo o t o o o o o 1 o words ORE 2 16 2 2 1 O p5 p4 O O p3 p2 p1 poj 2 P P he Grouping Branch operation Operation PCH p Description Branch out of a page Branches to address PCL DR2 DRo A3 Ao DR2 DR1 DRo Az A2 A1 Ao 2 specified by registers D and A in page p Note p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8 Rev 1 00 Aug 06 2004 RENESAS 1 92 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued BM a Branch and Mark to address a in page 2 Instruction Dg Do Number of Number of Flag CY Skip condition code o 1 0 a6 as aal as a2 arj ao 1 a a lis m Operation SP lt SP 1 Grouping Subroutine call operation SK SP PC Description Call the subroutine in page 2 Calls the PCH 2 subroutine at address a in page 2 PCL ae ao Note Subroutine extending from page 2 to an other page can also be called with the BM instruction when it sta
303. pecifications Timer 4 and prescaler divide the system clock frequency 4 0 MHz and the timer 4 interrupt occurs every 50 ms Figure 2 2 8 shows a setting example of the timer 4 constant period interrupt rum P3o INTO vM s P3o INTO M B interrupt occurs after the valid waveform falling is detected An interrupt occurs after the valid waveform rising is detected Fig 2 2 1 External 0 interrupt operation example Rev 1 00 Aug 06 2004 RENESAS 2 22 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts O Disable Interrupts External 0 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI Interrupt control register V1 b0 External O interrupt occurrence disabled TV1A Q Set Port Port used for external 0 interrupt is set to input port Port P30 output latch Set to input OP3A Set Valid Waveform Valid waveform of INTO pin is selected TH A Interrupt control register 11 b3 INTO pin input enabled b1 Both edges detection selected amp Execute NOP Instruction O Clear Interrupt Request External 0 interrupt activated condition is cleared External 0 interrupt request flag EXFO 0 External 0 interrupt activated condition cleared SNZO y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interru
304. pen drain is selected for the output structure Note 5 The pull up function is not selected Note 4 The key on wakeup function is not selected Note 7 P20 SCK Open Sck pin is not selected Connect to Vss P21 SOUT Open Connect to Vss P22 SIN Open SIN pin is not selected Connect to Vss P30 INTO Open 0 is set to output latch Connect to Vss P31 INT1 Open 0 is set to output latch Connect to Vss P32 P33 Open Connect to Vss P40 AIN4 P 43 Open AIN7 Connect to Vss P5o P53 Open Connect to Vss N channel open drain is selected for the output structure P60 AINo P63 Open AIN3 Connect to Vss Notes 1 After system is released from reset the internal oscillation on chip oscillator is selected for system clock RG 0 0 MRo 1 2 When the CRCK instruction is executed the RC oscillation circuit becomes valid Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution In order to start oscillation setting the main clock f XIN oscillation to be valid MR1 0 is required If necessary gen erate the oscillation stabilizing wait time by software Also when the main clock f XIN is selected as system clock set the main clock f XIN oscillation MR1 0 to be valid and select main clock f XIN MRo 0 Be careful that
305. performed with the SNZAD instruction Fig 2 4 5 A D converter operating mode program example Rev 1 00 Aug 06 2004 RENESAS 2 56 REJ09B0175 0100Z APPLICATION 4519 Group 2 4 A D converter 5 6 7 8 A D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison the contents of ADF flag retains 0 not set to 1 In this case the A D interrupt does not occur even when the usage of the A D interrupt is enabled Accordingly consider the time until the comparator operation is completed and examine the state of ADF flag by software The comparator operation is completed after 2 machine cycles A D conversion clock ADCK 1 clock Analog input pins When P40 AIN4 P43 AIN7 P60 AINO P63 AIN3 are set to pins for analog input they cannot be used as I O ports P4 and P6 TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A and simultaneously the low order 2 bits of register A is 0 Recommended operating conditions when using A D converter As for the supply voltage when A D converter is used and the recommended operating condition of the A D convesion clock frequency refer to the 3 1 Electrical characteristics Rev 1 00 Aug 06 2004 RENESAS 2 57 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO 2 5 Serial I O The 4519 Gr
306. pin is When the input of the INTO pin is controlled with the bit 3 of reg changed with the bit 2 of register 11 in software be careful about ister 11 in software be careful about the following notes the following notes Depending on the input state of the P30 INTO pin the external 0 Depending on the input state of the P30 INTO pin the external 0 interrupt request flag EXFO may be set when the bit 3 of regis interrupt request flag EXFO may be set when the bit 2 of regis ter 11 is changed In order to avoid the occurrence of an ter I1 is changed In order to avoid the occurrence of an unexpected interrupt clear the bit 0 of register V1 to 0 refer to unexpected interrupt clear the bit 0 of register V1 to 0 refer to Figure 18 and then change the bit 3 of register I1 Figure 200 and then change the bit 2 of register I1 In addition execute the SNZO instruction to clear the EXFO flag to In addition execute the SNZO instruction to clear the EXFO flag to 0 after executing at least one instruction refer to Figure 18 0 after executing at least one instruction refer to Figure 200 Also set the NOP instruction for the case when a skip is per Also set the NOP instruction for the case when a skip is per formed with the SNZO instruction refer to Figure 18 G formed with the SNZO instruction refer to Figure 200 XXxX02 The SNZO instruction is valid X1XxX2 Interrupt valid waveform is
307. pt request flag EXFO insert the NOP instruction after the SNZO instruction y Enable Interrupts The External 0 interrupt which is temporarily disabled is enabled b3 b0 Interrupt control register V1 X X X 1 b0 External 0 interrupt occurrence enabled TV1A Interrupt enable flag INTE 1 All interrupts enabled El y External 0 interrupt enabled state X it can be 0 or 1 J instruction Fig 2 2 2 External 0 interrupt setting example Note The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock Rev 1 00 Aug 06 2004 RENESAS 2 23 REJO9B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts raeg P31 INT1 vA H gt A ik x ja P31 INT1 An interrupt occurs after the valid waveform falling is detected Fig 2 2 3 External 1 interrupt operation example Rev 1 00 Aug 06 2004 RENESAS 2 24 REJO9B0175 0100Z 4519 Group O Disable Interrupts External 1 interrupt is temporarily disabled Interrupt enable flag INTE Interrupt control register V1 O Set Port Port used for external 1 interrupt is set to input port Port P31 output latch Set Valid Waveform Valid waveform of INT1 pin is selected Interrupt control register 12 b3 b0 x x 1 APPLICATION 2 2 Interrupts All interrupts disabled
308. put auto control circuit selected W60 D6 CNTRO pin function selection 0 De 1 O CNTRO input bit 1 CNTRO input output De input Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 36 REJ09B0175 0100Z APPLICATION 4519 Group 2 3 Timers 2 3 3 Timer application examples 1 Timer operation measurement of constant period The constant period by the setting timer count value can be measured Outline The constant period by the timer 1 underflow signal can be measured Specifications Timer 1 and prescaler divide the system clock frequency f XIN 4 0 MHz and the timer 1 interrupt occurs every 3 ms Figure 2 3 4 shows the setting example of the constant period measurement 2 CNTRO output operation buzzer output Outline Square wave output from timer 2 can be used for buzzer output Specifications 4 kHz square wave is output from the CNTRO pin at system clock frequency f XIN 4 0 MHz Also timer 2 interrupt occurs simultaneously Figure 2 3 1 shows the peripheral circuit example and Figure 2 3 5 shows the setting example of CNTRO output In order to reduce the current dissipation output is high impedance state during buzzer output stop 4519 CNTRO AA US In order to set Y timer 2 underflow cycle to 125 us set the dividing ratio Fig 2 3 1 Peripheral circuit example 3 CNTRO input operation event count Outline Count operation
309. puter operating normally HARDWARE FUNCTION BLOCK OPERATIONS When the WEF flag is set to 1 after system is released from reset the watchdog timer function is valid When the DWDT instruction and the WRST instruction are ex ecuted continuously the WEF flag is cleared to 0 and the watchdog timer function is invalid The WEF flag is set to 1 at system reset or RAM back up mode The WRST instruction has the skip function When the WRST in struction is executed while the WDF1 flag is 1 the WDF1 flag is cleared to 0 and the next instruction is skipped When the WRST instruction is executed while the WDF1 flag is 0 the next instruction is not skipped The skip function of the WRST instruction can be used even when the watchdog timer function is invalid Reset released 65534 count Note WRST instruction executed skip executed O System reset O After system is released from reset after program is started timer WDT starts count down When timer WDT underflow occurs WDF1 flag is set to 1 When the WRST instruction is executed WDF1 flag is cleared to 0 the next instruction is skipped When timer WDT underflow occurs while WDF1 flag is 1 WDF2 flag is set to 1 and the watchdog reset signal is output The output transistor of RESET pin is turned ON by the watchdog reset signal and system reset is executed Note The number of count is equal to
310. r 1 in terrupt request flag T1F is not set by the timer 1 underflow signal it is the flag for detecting the completion of period mea surement When a period measurement circuit is used select the suffi ciently higher speed frequency than the signal for measurement for the count source of a timer 1 When the signal for period measurement is De CNTRO pin input do not select De CNTRO pin input as timer 1 count source The XIN input is recommended as timer 1 count source at the time of period measurement circuit use When the input of P30 INTO pin is selected for measurement set the bit 3 of a register 11 to 1 and set the input of INTO pin to be enabled LA X0XX2 TV1A The SNZT1 instruction is valid LA 0 XOXX2 TW5A Period measurement circuit stop NOP SNZT1 The SNZT1 instruction is executed T1F flag cleared NOP X these bits are not used here Fig 61 Period measurement circuit program example Rev 1 00 Aug 06 2004 RENESAS 1 73 REJ09B0175 0100Z HARDWARE 4519 Group LIST OF PRECAUTIONS amp P30 INTO pin Note on bit 2 of register I1 Note 1 on bit 3 of register 11 When the interrupt valid waveform of the PS3o INTO pin is When the input of the INTO pin is controlled with the bit 3 of reg changed with the bit 2 of register 11 in software be careful about ister 11 in software be careful about the following notes the following notes Depending on the input state of t
311. r PUO Table 2 8 6 shows the pull up control register PUO Set the contents of this register through register A with the TPUOA instruction The contents of register PUO is transferred to register A with the TAPUO instruction Table 2 8 6 Pull up control register PUO at reset 00002 at RAM back up state retained Pull up control register PUO RAN PUOS P03 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUO P02 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUO P01 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUOO POo pin 0 Pull up transistor OFF pull up transistor control bit Pull up transistor ON Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 75 REJ09B0175 0100Z APPLICATION 4519 Group 2 8 RAM back up 4 Pull up control register PU1 Table 2 8 7 shows the pull up control register PUT Set the contents of this register through register A with the TPU1A instruction The contents of register PU1 is transferred to register A with the TAPU1 instruction ister PU1 at reset 00002 at RAM back up state retained Table 2 8 7 Pull up control re Pull up control register PU1 R W PU13 P13 pin 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PU
312. r W3 Instruction Do Do Number of Number of Flag CY Skip condition code 11olol olols s o sl 2 4 b KE cycles 2 16 1 1 Operation A W3 Grouping Timer operation Description Transfers the contents of timer control reg ister W3 to register A Rev 1 00 Aug 06 2004 2tENESAS REJO9B0175 0100Z 1 117 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TAWA Transfer data to Accumulator from register W4 Instruction Dg Do Number of Number of Flag CY Skip condition code 11 0 0 1 0 0 1 1 1 0 2 4 E isl cycies 2 16 1 1 Operation A W4 Grouping Timer operation Description Transfers the contents of timer control reg ister W4 to register A TAW5 Transfer data to Accumulator from register W5 Instruction Do Do Number of Number of Flag CY Skip condition code words cycles 1 0 40 1 F lis 1 1 Operation A W5 Grouping Timer operation Description Transfers the contents of timer control reg ister W5 to register A TAW6 Transfer data to Accumulator from register W6 Instruction Dg Do Number of Number of Flag CY Skip condition code
313. r Y from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code o o o o o o i l lo o o o c words i yes 2 16 1 1 E S Operation Y A Grouping Register to register transfer Description Transfers the contents of register A to regis ter Y WRST Watchdog timer ReSeT Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jol 1 o 1 o fo o o ol 2 0 words Eyes 18 1 1 WDF1 1 Operation WDF1 21 Grouping Other operation After skipping WDF1 0 Description Skips the next instruction when watchdog timer flag WDF1 is 1 After skipping clears 0 to the WDF1 flag When the WDF1 flag is 0 executes the next instruction Also stops the watchdog timer function when ex ecuting the WRST instruction immediately after the DWDT instruction XAM j eXchange Accumulator and Memory data Instruction Dg Do Number of Number of Flag CY Skip condition code 1lolililolh Hj lili Hi 2 j words cycles 2 16 1 1 E Operation A gt M DP Grouping RAM to register transfer X E X EXOR j Description After exchanging the contents of M DP J 0to 15 with the contents of register A an exclusive OR operation is performed between regis ter X and the valu
314. r is changed from comparator mode to A D conversion mode X these bits are not used here Fig 68 A D converter program example 3 AAD converter 2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage Accordingly when the analog volt age is input from the circuit with high impedance and charge discharge noise is generated and the sufficient A D accuracy may not be obtained Therefore reduce the impedance or connect a capacitor 0 01 uF to 1 uF to analog input pins Figure 69 When the overvoltage applied to the A D conversion circuit may occur connect an external circuit in order to keep the voltage within the rated range as shown the Figure 70 In addition test the application products sufficiently Sensor l Apply the voltage withiin the specifications to an analog input pin Fig 69 Analog input external circuit example 1 About 1kQ Sensor Fig 70 Analog input external circuit example 2 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z HARDWARE LIST OF PRECAUTIONS POF instruction When the POF instruction is executed continuously after the EPOF instruction system enters the RAM back up state Note that system cannot enter the RAM back up state when ex ecuting only the POF instruction Be sure to disable interrupts by executing the DI instruction be fore executing the EPOF instruction and the POF instruction continuously Progr
315. r of Number of Flag CY Skip condition code o lo lololo 1 1 o 1 o l olila words __cycies 2 16 1 1 Operation E7 E4 B Grouping Register to register transfer E3 Eo A Description Transfers the contents of register B to the high order 4 bits E7 E4 of register E and the contents of register A to the low order 4 bits E3 Eo of register E TFROA Transfer data to register FRO from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1Jojojo 1 o 1 o o o j2 2 8 words cycles 2 16 1 1 E E Operation FRO lt A Grouping Input Output operation Description Transfers the contents of register A to the port output structure control register FRO TFR1A Transfer data to register FR1 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code Te ee od ee 0 21215 words cycles 2 16 1 1 n Operation FR1 lt A Grouping Input Output operation Description Transfers the contents of register A to the port output structure control register FR1 TFR2A Transfer data to register FR2 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1 lolo o o 1 o t o 2 fz fa words eyeles 2 16 1 1 E B Operation FR2 A Grouping Input Output operation Description Transfers the contents of register A to the port output structure control register FR2 Rev 1 00 Aug 06 2004 RENESAS 1 120 REJO9B0175 0100Z 4519 Group
316. r to Figure 16 Interrupt enabled SNZT3 instruction is invalid Rev 1 00 Aug 06 2004 7tENESAS REJO9B0175 0100Z 1 24 HARDWARE peysnes si uonipuoo pejeAnoe 1dnuejui uoee uaym aun eui 1e uogonasui pajnoexe eui uo spuadep sojo o Jo enua ul SIUL z ejofo 1se eui 0 pexoeis SI sseJppe au SAJON Z L seioN ssouppe saj9 9 aulyoeu e 0 Z t idnueju euj woy O I lees sue s welbold eu lt parea Bejy pue q v p Jeu g Jeu Z eui Jeu y JOIS 40V dv1 3e1 Je1 41L FUNCTION BLOCK OPERATIONS Peysnes S uonpuoo peireAnoe jdnueiu 1 i 13X3 03X3 jdnuejur lessa99u si jeusa xy alow JO Sponad y 10 490 9 was s jo jo e Bulurejay SSS OOS LLNI OLNI 9jejs p jqeu dnu1 u ALNI Bey jqeu 1dnueiu ajo o uopno x uononuisul 3 i el ZL L ZL L el ZL Ll Eri pec perd Na 7 aj9 9 aulyoeu 1 9I0N payqeua si 1dnueiul sy Jaye jas s Be 1senbai 1dn1a ul ue ueuM 4519 Group Fig 16 Interrupt sequence 1 25 132 NE SAS Rev 1 00 Aug 06 2004 REJ09B0175 0100Z 4519 Group EXTERNAL INTERRUPTS The 4519 Group has the external 0 interrupt and external 1 inter rupt An external interrupt request occurs when a valid waveform is input to an interrupt input pin edge detection The external interrupt can be controlled with the interrupt control registers l1 and I2 Table 7 External interrupt
317. ransmit data into the serial I O register SI with the TSIAB instruction When the TSIAB instruction is executed the contents of register A are transferred to the low order bits of register SI and the contents of register B are transferred to the high order bits of register SI At this time the Sck pin must be at the H level Start serial transmit receive with the SST instruction However in Figure 2 5 2 where an external clock is selected transmit receive is not started until the clock is input When the SST instruction is executed the serial I O transmit receive completion flag SIOF is cleared to 0 The microcomputer on the master side is informed that the receiving side is ready to receive In the connection example in Figure 2 5 2 the control signal L level is output The transmit data is output from the SOUT pin synchronously with the falling edges of the shift clock O The transmit data is output bit by bit beginning with the LSB of register Sl Each time one bit is output the contents of register SI are shifted to one bit position toward the LSB O Also the receive data is input from the SIN pin synchronously with the rising edges of the shift clock The receive data is input bit by bit to the MSB of register SI A serial I O interrupt request occurs when the transmit receive is completed and the SIOF flag is set to 1 O Read the receive data within the serial I O interrupt service routine
318. red to register A with the TAQ3 instruction at reset 00002 at RAM back up state retained This bit has no function but read write is enabled Table 2 4 4 A D control register Q3 A D control register Q3 R W Q33 Not used A D converter operation clock Q32 d 0 1 0 Instruction clock INSTCK 1 selection bit On chip oscillator f RING Q31 Q30 Division ratio Q31 O O Frequency divided by 6 A D converter operation clock division ratio selection bits A AN Q30 1 0 Frequency divided by 24 Frequency divided by 48 Notes 1 R represents read enabled and W represents write enabled 2 In order to select AIN7 AIN4 set register Q1 after setting regsiter Q3 2 4 2 A D converter application examples 1 A D conversion mode Outline Analog input signal from a sensor can be converted into digital values Specifications Analog voltage values from a sensor is converted into digital values by using a 10 bit successive comparison method Use the AINo pin for this analog input Figure 2 4 2 shows the A D conversion mode setting example Rev 1 00 Aug 06 2004 RENESAS 2 54 REJO9B0175 0100Z APPLICATION 4519 Group 2 4 A D converter Disable Interrupts A D interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI b0 Interrupt control register V2 b2 A D interrupt occurrence disabled TV2A Q Set A D C
319. register A with the TI1A instruction In addi tion the TAI1 instruction can be used to transfer the contents of register 11 to register A External interrupt control register I2 Register I2 controls the valid waveform of external 1 interrupt in put control of INT1 pin and return input level Set the contents of this register through register A with the TI2A instruction In addi tion the TAI2 instruction can be used to transfer the contents of register I2 to register A Remarks Rev 1 00 Aug 06 2004 Ports PO0 PO3 Return by an external H level or L level input or rising edge L gt H or falling edge H 5 L The key on wakeup function can be selected with 2 port units Select the re turn level L level or H level and return condition return by level or edge with the register K1 according to the external state before going into the RAM back up state Ports P10 P13 Return by an external L level in put The key on wakeup function can be selected with 2 port units Set the port using the key on wakeup function to H level before going into the RAM back up state INTO INT1 Return by an external H level or L level input or rising edge L gt H or falling edge PL The external interrupt request flags EXFO EXF1 are not set T c e o o 5 o x o c o o E Lu REJO9B0175 0100Z 7tENESAS Select the return
320. rence of an unexpected interrupt clear the bit 2 of register V1 to 0 refer to Figure 280 and then stop the bit 2 of register W5 to 0 to stop the period measurement circuit In addition execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction refer to Figure 280 Also set the NOP instruction for the case when a skip is per formed with the SNZT1 instruction refer to Figure 280 LA X0XX2 The SNZTI instruction is valid X0XX2 Period measurement circuit stop TV1A LA 0 TW5A NOP SNZT1 The SNZT1 instruction is executed T1F flag cleared NOP X these bits are not used here Fig 28 Period measurement circuit program example While a period measurement circuit is operating the timer 1 in terrupt request flag T1F is not set by the timer 1 underflow signal it is the flag for detecting the completion of period mea surement When a period measurement circuit is used select the suffi ciently higher speed frequency than the signal for measurement for the count source of a timer 1 When the target signal for period measurement is De CNTRO pin input do not select De CNTRO pin input as timer 1 count source The XIN input is recommended as timer 1 count source at the time of period measurement circuit use When the input of P30 INTO pin is selected for measurement set the bit 3 of a register 11 to 1 and set the input of INTO pin to be enabled 1 41
321. represents write enabled ROM ORDERING METHOD 1 Mask ROM Order Confirmation Form 2 Mark Specification Form 3 Data to be written to ROM sese one floppy disk For the mask ROM confirmation and the mark specifications refer to the Renesas Technology Corp Homepage http www renesas com en rom Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS On chip oscillator f RING oscillation stop 1 71 4519 Group LIST OF PRECAUTIONS Noise and latch up prevention Connect a capacitor on the following condition to prevent noise and latch up connect a bypass capacitor approx 0 1 uF between pins VDD and Vss at the shortest distance equalize its wiring in width and length and use relatively thick wire In the One Time PROM version CNVss pin is also used as VPP pin Accordingly when using this pin connect this pin to Vss through a resistor about 5 kQ connect this resistor to CNVss VPP pin as close as possible Register initial values 1 The initial value of the following registers are undefined after sys tem is released from reset After system is released from reset set initial values Register Z 2 bits Register D 3 bits Register E 8 bits G Register initial values 2 The initial value of the following registers are undefined at RAM back up After system is returned from RAM back up set initial values Register Z 2 bits Reg
322. ria 3 27 Rev 1 00 Aug 06 2004 ENESAS iii REJO9B0175 0100Z 4519 Group List of figures List of figures CHAPTER 1 HARDWARE Fig 1 AMC instruction execution example c occcnnccccnnncccnncccnononcnnnnc ccoo nn naar cnn nennen nnns 1 17 Fig 2 RAR instruction execution example eessseseesesseneeee nennen nennen nennen 1 17 Fig 3 Registers A B and register E sssssssssssee eene ennemis 1 17 Fig 4 TABP p instruction execution Ten e 1 17 Fig 5 Stack registers SKS structure TT 1 18 Fig 6 Example of operation at Subroutine call ssee cnn cnc nana rca 1 18 Fig 7 Program counter PC Structure iii na 1 19 Fig 8 Data pointer DP structure T 1 19 Fig 9 SD instruction execution example sse 1 19 Fig 10 ROM map Of M34519MB8 EOG T 1 20 Fig 11 Page 1 addresses 008016 to OOFF16 structure sss 1 20 Fig 12 RAM AD RH EET 1 21 Fig 13 Program example of interrupt processing ococccccconoonccccnononcnnnonanoncnncnanan em 1 23 Fig 14 Internal state when interrupt OCCUIS eee eee eee eee ee eee eee 1 23 Fig 15 Interrupt system diagralm otii teen a c dia cp triada 1 23 Fig 16 Interrupt sSequ Gn Ce nre EE ede utt eeu ea edu 1 25 Fig 17 External interrupt circuit structure sse sees sees sees eee ee esse ee essere eene eene rennen 1 26 Fig 18 External O interrupt program example 1 ssssssssseeenennns 1 29 Fig 19 External O in
323. rite enabled 2 When setting the port W42 W40 are not used 2 Timer control register W6 Table 2 1 2 shows the timer control register W6 Set the contents of this register through register A with the TW6A instruction The contents of register W6 is transferred to register A with the TAWS instruction at reset 00002 Table 2 1 2 Timer control register W6 Timer control register W6 at RAM back up state retained R W Wes CNTR1 pin input count edge 0 Falling edge selection bit 1 Rising edge Wee CNTRO pin input count edge 0 Falling edge selection bit 1 Rising edge Wet CNTR1 output auto control circuit 0 CNTR1 output auto control circuit not selected selection bit 1 CNTR1 output auto control circuit selected Wo De CNTRO pin function selection 0 De I O CNTRO input bit Note 2 CNTRO input output De input Notes 1 R represents read enabled and W represents write enabled 2 When setting the port W63 W61 are not used Rev 1 00 Aug 06 2004 RENESAS 2 6 REJ09B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 3 Serial I O control register J1 Table 2 1 3 shows the serial I O control register J1 Set the contents of this register through register A with the TJ1A instruction The contents of register J1 is transferred to register A with the TAJ1 instruction Table 2 1 3 Serial I O control register J1 at reset 00002 Serial I O control register J1 at RAM back up state retained
324. rrupt disabled SNZSI instruction is valid 1 Interrupt enabled SNZSI instruction is invalid Note 2 0 Interrupt disabled SNZAD instruction is valid 1 Interrupt enabled SNZAD instruction is invalid Note 2 0 Interrupt disabled SNZTA instruction is valid 1 0 Interrupt control register V2 Timer 4 serial I O interrupt enable bit V2 A D interrupt enable bit V2 Timer 4 i le bi Mu on Interrupt enabled SNZTA instruction is invalid Note 2 Interrupt disabled SNZT3 instruction is valid 1 Interrupt enabled SNZT3 instruction is invalid Note 2 Notes 1 R represents read enabled and W represents write enabled 2 These instructions are equivalent to the NOP instruction 3 When setting the serial I O V2 V2 and V2o are not used V2o Timer 3 interrupt enable bit 4 Serial I O mode register J1 Table 2 5 2 shows the serial I O mode register J1 Set the contents of this register through register A with the TJ1A instruction In addition the TAJ1 instruction can be used to transfer the contents of register J1 to register A Table 2 5 2 Serial I O mode register J1 Serial I O control register J1 at RAM back up state retained Synchronous clock J1s 0 O Instruction clock INSTCK divided by 8 Serial I O synchronous clock 0 1 instruction clock INSTCK divided by 4 jio SP Oeon pits 1 0 Instruction clock INSTCK divided by 2 1
325. rrupt enable bit o o Jo j4i o R W Interrupt control register V2 at reset 00002 at RAM back up 00002 TAV2 TV2A Interrupt disabled SNZSI instruction is valid Interrupt enabled SNZSI instruction is invalid Interrupt disabled SNZAD instruction is valid Interrupt enabled SNZAD instruction is invalid Interrupt disabled SNZT4 instruction is valid Interrupt enabled SNZT4 instruction is invalid Interrupt disabled SNZT3 instruction is valid Interrupt enabled SNZT3 instruction is invalid Serial I O interrupt enable bit A D interrupt enable bit Timer 4 interrupt enable bit O O O 0O Timer 3 interrupt enable bit R W Interrupt control register 11 at reset 00002 at RAM back up state retained TAM THA INTO pin input disabled INTO pin input enabled Falling waveform L level L level is recognized with the SNZIO Interrupt valid waveform for INTO pin instruction return level selection bit Note 2 Rising waveform H level H level is recognized with the SNZIO instruction One sided edge detected Both edges detected INTO pin Timer 1 count start synchronous Timer 1 count start synchronous circuit not selected circuit selection bit Timer 1 count start synchronous circuit selected INTO pin input control bit Note 2 INTO pin edge detection circuit control bit R W Interrupt control register 12 at reset 00002 at
326. rrupt enable bit V10 and the INTE flag to 1 The external 0 interrupt is now enabled Now when a valid wave form is input to the P30 INTO pin the EXFO flag is set to 1 and the external 0 interrupt occurs Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS HARDWARE FUNCTION BLOCK OPERATIONS 2 External 1 interrupt request flag EXF1 External 1 interrupt request flag EXF1 is set to 1 when a valid waveform is input to P31 INT1 pin The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock Refer to Figure 16 The state of EXF1 flag can be examined with the skip instruction SNZ1 Use the interrupt control register V1 to select the interrupt or the skip instruction The EXF1 flag is cleared to 0 when an in terrupt occurs or when the next instruction is skipped with the skip instruction External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31 INT1 pin The valid waveform can be selected from rising waveform falling waveform or both rising and falling waveforms An example of how to use the external 1 interrupt is as follows Set the bit 3 of register 12 to 1 for the INT1 pin to be in the in put enabled state O Select the valid waveform with the bits 1 and 2 of register 12 Clear the EXF1 flag to 0 with the SNZ1 instruction Set the NO
327. rts on page 2 Be careful not to over the stack because the maximum level of subroutine nesting is 8 BML p a Branch and Mark Long to address a in page p Instruction Dg Do Number of Number of Flag CY Skip condition code o o 1 o pa pa pr o o S e e eyes 2 2 1 0 ps ae a5 a4 as a2 at aoj 2 T a lig Grouping Subroutine call operation Operation SP lt SP 1 Description Call the subroutine Calls the subroutine at SK SP PC address a in page p PCH p Note p is O to 47 for M34519M6 and p is O to 63 PCL ae ao for M34519M8E8 BMLA p Branch and Mark Long to address D A in page p Be careful not to over the stack because the maximum level of subroutine nesting is 8 Instruction Dg Do Number of Number of Flag CY Skip condition code o ojo o 1 1fo o o o jo 3 fo wie cycles 2 16 2 2 1 0 ps p4 0 0 ps p2 p1 po 2 P P lag Grouping Subroutine call operation Operation SP SP 1 Description Call the subroutine Calls the subroutine at SK SP PC address DR2 DR1 DRo A3 A2 A1 Ao 2 speci PCH p fied by registers D and A in page p PCL DR2 DRo As Ao Note p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8 Be careful not to over the stack because the maximum level of s
328. ructure control register FR1 Set the contents of this register through register A with the TFR1A instruction Table 2 1 8 Port output structure control register FR1 at reset 00002 at RAM back up state retained Port output structure control register FR1 FR13 Port D3 0 N channel open drain output output structure selection bit 1 CMOS output FR12 Port D2 0 N channel open drain output output structure selection bit 1 CMOS output ERA Port D1 0 N channel open drain output output structure selection bit 1 CMOS output FR10 Port Do 0 N channel open drain output output structure selection bit 1 CMOS output Note W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 9 REJO9B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 9 Port output structure control register FR2 Table 2 1 9 shows the port output structure control register FR2 Set the contents of this register through register A with the TFR2A instruction Table 2 1 9 Port output structure control register FR2 at reset 00002 at RAM back up state retained Port output structure control register FR2 z FR23 Port D7 CNTR1 0 N channel open drain output output structure selection bit 1 CMOS output FR22 Port De CNTRO 0 N channel open drain output output structure selection bit 1 CMOS output FR2 Port D5 0 N channel open drain output output structure selection bit 1 CMOS output FR20 Port D4
329. rupt control register 11 Set the contents of this register through register A with the TI1A instruction In addition the TAM instruction can be used to transfer the contents of register 11 to register A at reset 00002 at RAM back up state retained 0 INTO pin input disabled 1 INTO pin input enabled Table 2 2 3 Interrupt control register 11 Interrupt control register 11 R W 113 INTO pin input control bit Note 2 Falling waveform L level L level is recognized with the SNZIO instruction Rising waveform H level H level is recognized with the SNZIO instruction Interrupt valid waveform for INTO 112 pin return level selection bit Note 2 INTO pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected aa INTO pin Timer 1 count start 0 Timer 1 count start synchronous circuit not selected synchronous circuit selection bit Timer 1 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 112 and l13 are changed the external interrupt request flag EXFO may be set to 1 Accordingly clear EXFO flag with the SNZO instruction when the bit 0 V10 of register V1 to 0 In this time set the NOP instruction after the SNZO instruction for the case when a skip is performed with the SNZO instruction Rev 1 00 Aug 06 2004 RENESAS 2 19 REJ09B0175 0100Z AP
330. s product when RAM back up mode and main clock f XIN stop MR1 1 XIN pin is fixed to H in order to avoid the through current by floating of internal logic The XIN pin is fixed to H until main clock f XIN oscillation starts to be valid MR1 0 by the CMCK instruction from reset state Accordingly when an external clock is used connect a 1 kQ or more resistor to XIN pin in series to limit of current by competitive signal Rev 1 00 Aug 06 2004 REJO9B0175 0100Z RENESAS HARDWARE FUNCTION BLOCK OPERATIONS M34519 Do not use the CMCK CRCK and CYCK instructions in program XOUT Fig 56 Handling of XIN and XouT when operating on chip oscillator M34519 Execute the CMCK instruc tion in program Note Externally connect a damping resistor Rd depending on the oscillation frequency A feedback resistor is built in Use the resonator manu facturer s recommended value because constants such as ca pacitance depend on the resonator M34519 Execute the CRCK instruction in program XOUT prog Fig 58 External RC oscillation circuit Execute the CYCK instruction M34519 in program Note Externally connect a damping resistor Rd depending on the oscillation frequency A feedback resistor is built in Use the quartz crystal manu facturer s recommended value because constants such as ca pacitance depend on the resonator XOUT Fig 59 External quartz crystal circuit Execu
331. s separated from regis ter AD the value is retained even when changing from comparator mode to A D conversion mode Note that the comparator register can be written and read at only comparator mode If the value in the comparator register is n the logic value of com parison voltage Vret generated by the built in D A converter can be determined from the following formula Logic value of comparison voltage Vret ref n The value of register AD n 0 to 255 11 Comparison result store flag ADF In comparator mode the ADF flag which shows completion of A D conversion stores the results of comparing the analog input volt age with the comparison voltage When the analog input voltage is lower than the comparison voltage the ADF flag is set to 1 The state of ADF flag can be examined with the skip instruction SNZAD Use the interrupt control register V2 to select the inter rupt or the skip instruction The ADF flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction HARDWARE FUNCTION BLOCK OPERATIONS 12 Comparator operation start instruction ADST instruction In comparator mode executing ADST starts the comparator oper ating The comparator stops 2 machine cycles A D conversion clock f ADCK 1 clock after it has started 4 us at f XIN 6 0 MHz in XIN through mode f ADCK f INSTCK 6 When the analog input voltage is lower than the comparis
332. skip is performed with the SNZ1 instruction Rev 1 00 Aug 06 2004 RENESAS 2 20 REJ09B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts 2 2 3 Interrupt application examples 1 External 0 interrupt The INTO pin is used for external 0 interrupt of which valid waveforms can be chosen which can recognize the change of falling edge H L rising edge L H and both edges H L or L H Outline An external 0 interrupt can be used by dealing with the falling edge H gt L rising edge L 5 H and both edges H 5 L or L 5 H as a trigger Specifications An interrupt occurs by the change of an external signal edge both edges H gt L or L gt H Figure 2 2 1 shows an operation example of an external 0 interrupt and Figure 2 2 2 shows a setting example of an external O interrupt 2 External 1 interrupt The INT1 pin is used for external 1 interrupt of which valid waveforms can be chosen which can recognize the change of falling edge H L rising edge L H and both edges H L or L H Outline An external 1 interrupt can be used by dealing with the falling edge H gt L rising edge L 5 H and both edges H gt L or L 5 H as a trigger Specifications An interrupt occurs by the change of an external signal edge falling edge H L Figure 2 2 3 shows an operation example of an external 1 interrupt and Figure 2 2 4 shows a
333. skip of the next instruction according to the interrupt request flag T3F Note when the interrupt request is cleared insert the NOP instruction after the SNZT3 instruction Set INT1 Input INT1 pin input is set to be valid El b3 INT1 pin input enabled TI2A 1 b0 Timer 3 count start synchronous circuit selected Interrupt control register 12 Start Timer Operation and Prescaler Operation Timer 3 and prescaler temporarily stopped are restarted TW3A Timer 3 count auto stop circuit is selected b3 bo 63 Timer 3 count auto stop circuit selected Timer control register W3 111 0 b2 Timer 3 operation start Timer control register PA Prescaler start TPAA O Enable Interrupts The Timer 3 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V2 X X X 1 b0 Timer 3 interrupt occurrence enabled TV2A Interrupt enable flag INTE 1 All interrupts enabled El Ready for timer start by external input completed A The prescaler count value and timer 3 count value to make the interrupt occur every 1 ms are set as follows 1 ms 4 0 MHz X 3 X 15 1 X 82 1 System clock Instruction Presclaer Timer 3 count value clock count value X it can be 0 or 1 lI instruction Fig 2 3 7 Timer start by external input setting example Rev 1 00 Aug 06 2004 RENESAS 2 43 REJ09B0175 0100Z 4519 Group O Disable Int
334. ster V1 X 0 b2 b0 Timer 1 interrupt and External 0 interrupt occurrence disabled TV1A Q Stop Timer Operation Timer 1 interrupt is temporarily disabled Timer 1 count source is set TW1A b2 Timer 1 stop Timer control register W1 b1 bO XIN input for Timer 1 count source Select Period Measurement signal P30 INTO pin is set as an input port INTO pin input is enabled and both edges detection are set INTO pin input is selected for period measurement signal b3 b0 Port P30 output latch X X X 1 Set to input OP3A b3 bo TIA Interrupt control register 11 1 0 110 b3 INTO pin input enabled b2 L level is recognized with the SNZIO instruction b1 Both edges selected b0 Timer 1 count start synchronous circuit not selected Timer control register W5 b2 Period measurement circuit stop TW5A b1 b0 INTO pin input for period measurement signa Clear Interrupt Request execute this after executing at least one instruction from is executed External 0 interrupt activated condition is cleared External 0 interrupt request flag EXFO 0 External 0 interrupt activated condition cleared SNZO Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag EXFO insert the NOP instruction after the SNZO instruction O Set Timer Value T
335. stop circuit selection bit Note 2 Timer 1 count auto stop circuit not selected Timer 1 count auto stop circuit selected Timer 1 control bit Stop state retained Operating Timer 1 count source selection bits Timer control register W2 Count source Instruction clock INSTCK Prescaler output ORCLK XIN input CNTRO input R W at reset 00002 TAW2 TW2A at RAM back up state retained CNTRO output signal selection bit Note 2 Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Timer 2 control bit Stop state retained Operating Timer 2 count source selection bits Timer control register W3 Count source System clock STCK Prescaler output ORCLK Timer 1 underflow signal T1 UDF PWM signal PWMOUT R W TAW3 TW3A at reset 00002 at RAM back up state retained Timer 3 count auto stop circuit selection bit Note 3 Timer 3 count auto stop circuit not selected Timer 3 count auto stop circuit selected Timer 3 control bit Stop state retained Operating Timer 3 count source selection bits Notes 1 R represents read enabled and W represents write enabled Count source PWM signal PWMOUT Prescaler output ORCLK Timer 2 underflow signal T2UDF CNTR1 input 2 This function is valid only whe
336. t J11 Port block diagram 4 Rev 1 00 Aug 06 2004 RENESAS 1 12 REJO9B0175 0100Z 4519 Group OP3A instruction External 0 interrupt IAP3 instruction Note 3 External 0 interrupt circuit Key on wakeup input Timer 1 count start synchronous circuit input Period measurement circuit input OP3A instruction External 1 interrupt IAP3 instruction HARDWARE PORT BLOCK DIAGRAM ad A Note 1 L 1 4 0 P30 INTO A Note 2 77 Ka Note 1 tte P31 INT1 Note 3 External 1 interrupt circuit Key on wakeup input Timer 3 count start synchronous circuit input OP3A instruction IAP3 instruction IAP3 instruction a Note 2 hr Notes 1 This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less 3 As for details refer to the external interrupt circuit structure Port block diagram 5 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS HARDWARE 4519 Group PORT BLOCK DIAGRAM Note 3 IAP4 instruction A Note 1 w P40 AIN4 P43 AIN7 A Note 2 T OPAA instruction Analog input Note 3 Register A P5o P53 X Note 2 gt al de Notes 1 This symbol represents a parasitic diode on the port 2 Applied potential to these ports must be VDD or less 3 i represents bits O to 3
337. t Instruction Dg Do Number of Number of Flag CY Skip condition code olololololololilolol lo o 4 words cycles 2 16 1 1 S Operation INTE 0 Grouping Interrupt control operation Description Clears 0 to interrupt enable flag INTE and disables the interrupt Note Interrupt is disabled by executing the DI in struction after executing 1 machine cycle DWDT Disable WatchDog Timer Instruction Dg Do Number of Number of Flag CY Skip condition code 1 1o 1lo o 1 1 1 o o 2 e c Words cycles 2 16 1 1 Operation Stop of watchdog timer function enabled Grouping Other operation Description Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction El Enable Interrupt Instruction Dg Do Number of Number of Flag CY Skip condition code 0 1010101010101110 1 01015 words cycles 2 16 1 1 Z Operation INTE 1 Grouping Interrupt control operation Description Sets 1 to interrupt enable flag INTE and enables the interrupt Note Interrupt is enabled by executing the EI in struction after executing 1 machine cycle Rev 1 00 Aug 06 2004 RENESAS 1 95 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued EPOF Enable POF instruction
338. t Set the contents of this register through register A with the TW3A instruction The TAW3 instruction can be used to transfer the contents of register W3 to register A Timer control register W4 Register W4 controls the D7 CNTR1 output the expansion of H interval of PWM output and the count operation and count source of timer 4 Set the contents of this register through regis ter A with the TW4A instruction The TAWA instruction can be used to transfer the contents of register W4 to register A Timer control register W5 Register W5 controls the period measurement circuit and target signal for period measurement Set the contents of this register through register A with the TW5A instruction The TAW5 instruc tion can be used to transfer the contents of register W5 to register A Timer control register W6 Register W6 controls the count edges of CNTRO pin and CNTR1 pin selection of CNTR1 output auto control circuit and the De CNTRO pin function Set the contents of this register through reg ister A with the TW6A instruction The TAW6 instruction can be used to transfer the contents of register W6 to register A REJO9B0175 0100Z ENESAS HARDWARE FUNCTION BLOCK OPERATIONS 2 Prescaler Prescaler is an 8 bit binary down counter with the prescaler reload register PRS Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction Data can be read from reload register RPS with the TA
339. t and then stop the period measurement circuit Figure 3 3 1 shows the setting example to read measurement data of period measurement circuit 10 Prescaler timer 1 timer 2 and timer 3 count start time and count time when operation starts Count starts from the first rising edge of the count source in Fig 3 3 2 after prescaler timer 1 timer 2 and timer 3 operations start Q in Fig 3 3 2 Time to first underflow Z in Fig 3 3 2 is shorter for up to 1 period of the count source than time among next underflow O in Fig 3 3 2 by the timing to start the timer and count source operations after count starts 11 Timer 4 count start time and count time when operation starts Count starts from the rising edge in Fig 3 3 3 after the first falling edge of the count source after timer 4 operation starts O in Fig 3 3 3 Time to first underflow in Fig 3 3 3 is different from time among next underflow in Fig 3 3 3 by the timing to start the timer and count source operations after count starts Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS Timer 1 operation is stopped bit 2 of register KX is cleared to 0 Timer 1 interrupt is disabled bit 2 of register gi is cleared to 0 Period measurement circuit is stopped bit 2 of register Bs is cleared to 0 Execute at least xk Instruction NOP Timer 1 interrupt request flag T1F is cleared my SNZT1 Considering the skip of the SNZT1 instruction insert
340. t control register V1 b2 Timer 1 interrupt occurrence disabled TV1A Q Stop Timer Operation Timer 1 is temporarily stopped TW1A Timer 1 count source is selected b3 Timer 1 count auto stop circuit not selected b2 Timer 1 stop Timer control register W1 b1 bO Instruction clock INSTCK selected for Timer 1 count source Set Timer Value Timer 1 count time is set The formula is shown A below Timer 1 reload register R1 A616 Timer count value 166 set T1AB amp Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction O Start Timer Operation Timer 1 temporarily stopped is restarted Timer control register W1 b2 Timer 1 operation start TW1A O Enable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V1 X 1 Xx X b2 Timer 1 interrupt occurrence enabled TV1A Interrupt enable flag INTE 1 All interrupts enabled El y Constant period interrupt execution started A The timer 1 count value to make the interrupt occur every 0 25 ms is set as follows 0 25 ms 2 0 MH
341. t instruction when the con SNZO Skip if Non Zero condition of external 0 interrupt request flag tents of register A is equal to the contents of M DP Executes the next instruction when the con tents of register A is not equal to the contents of M DP Instruction D9 Do Number of Number of Flag CY Skip condition code 0 o0 o o 1 11 0 0 0 0 3 8 words ee 2 a 1 1 E V10 0 EXFO 1 Operation Vio 0 EXFO 1 Grouping Interrupt operation After skipping EXFO 0 Description When V10 0 Skips the next instruction Vio 1 SNZO NOP V10 bit 0 of the interrupt control register V1 SNZ1 Skip if Non Zero condition of external 1 interrupt request flag when external 0 interrupt request flag EXFO is 1 After skipping clears 0 to the EXFO flag When the EXFO flag is 0 executes the next instruction When V10 1 This instruction is equiva lent to the NOP instruction Instruction Dg Do Number of Number of Flag CY Skip condition code ojojolo 1 t1 1 0o o 1 o a e wes cycles m 1 1 Vt1 0 EXF1 1 Operation V11 20 EXF1 21 Grouping Interrupt operation After skipping EXF1 0 Description When V11 0 Skips the next instruction Rev 1 00 Aug 06 2004 V11 2 1 SNZ1 NOP V11 bit 1 of the interrupt control register V1 RENESAS
342. t ouia acoge a E E gan Se uS DARE RRRO dE 2 12 Fig 2 2 1 External 0 interrupt operation example eee eee eee eee eee 2 22 Fig 2 2 2 External 0 interrupt setting example sse 2 23 Fig 2 2 3 External 1 interrupt operation example srein inanasan 2 24 Fig 2 2 4 External 1 interrupt setting example see eee eee eee eee eee eee eee eee 2 25 Fig 2 2 5 Timer 1 constant period interrupt setting example eee ee eee ee eee eee eee e 2 26 Fig 2 2 6 Timer 2 constant period interrupt setting example sese e essere eee ee eee sees eee e 2 27 Fig 2 2 7 Timer 3 constant period interrupt setting example eee eee eee ee eee 2 28 Fig 2 2 8 Timer 4 constant period interrupt setting example sene 2 29 Fig 2 9 1 Peripheral Circuit example eet ertt aeu a edu ee e ER ud e kt ed dut 2 37 Fig 2 3 2 Timer 4 operation ee cet rene ea Rae aen ep exa Ren eR EL etai eaaa EISE 2 38 Fig 2 3 3 Watchdog timer fUlctioniiss uoi cada 2 39 Fig 2 3 4 Constant period measurement setting example seer eee eee eee eee ee eee 2 40 Fig 2 3 5 CNTRO output setting example see ee eee yeee eee eee eee 2 41 Fig 2 3 6 CNTRO input setting example sss eene ener 2 42 Fig 2 3 7 Timer start by external input setting example ss 2 43 Fig 2 3 8 PWM output control setting example sse men 2 44 Fig 2 3 9 Period measurement of CNTRO pin input setting example 1 2
343. t starts Reload Reload y y 1st underflow 2nd underflow x o m E 3 o o i o 7 2 E g s Q O o x l n 1 count amp An interrupt occurs or a skip instruction is executed Timer interrupt l request flag Fig 24 Auto reload function The 4519 Group timer consists of the following circuits Prescaler 8 bit programmable timer Timer 1 8 bit programmable timer Timer 2 8 bit programmable timer Timer 3 8 bit programmable timer Timer 4 8 bit programmable timer Watchdog timer 16 bit fixed dividing frequency timer Timers 1 2 3 and 4 have the interrupt function respectively Prescaler and timers 1 2 3 and 4 can be controlled with the timer control registers PA W1 to W6 The watchdog timer is a free counter which is not controlled with the control register Each function is described below Rev 1 00 Aug 06 2004 RENESAS 1 31 REJO9B0175 0100Z 4519 Group Table 9 Function related timers Circuit Structure Count source Frequency dividing ratio HARDWARE FUNCTION BLOCK OPERATIONS Use of output signal Control register Prescaler 8 bit programmable binary down counter Instruction clock INSTCK 1 to 256 Timer 1 2 3 amd 4 count sources PA Timer 1 8 bit programmable binary down counter link to INTO input period pulse width measurement function Instruction clock INSTCK Prescaler output ORC
344. t the normal operation If a program runs incorrectly the WRST instruction is not executed and system reset occurs Specifications System clock frequency f XIN 4 0 MHz is used and program run away is detected by executing the WRST instruction in 49 ms Figure 2 3 3 shows the watchdog timer function and Figure 2 3 13 shows the example of watchdog timer FFFF16 Value of 16 bit timer WDT BL CT 000016 WDF1 flag S S 65534 count Note WDF2 flag RESET pin output U I O Reset WRST instruction O System reset released executed skip executed O After system is released from reset after program is started timer WDT starts count down When timer WDT underflow occurs WDF1 flag is set to 1 When the WRST instruction is executed WDF1 flag is cleared to 0 the next instruction is skipped amp When timer WDT underflow occurs while WDF1 flag is 1 WDF2 flag is set to 1 and the watchdog reset signal is output The output transistor of RESET pin is turned ON by the watchdog reset signal and system reset is executed Note The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock Fig 2 3 3 Watchdog timer function Rev 1 00 Aug 06 2004 RENESAS 2 39 REJO9B0175 0100Z APPLICATION 4519 Group 2 3 Timers O Disable Interrupts Timer 1 interrupt is tempor
345. te the CMCK instruction in program and set the main clock M34519 f XIN to be enabled MR1 0 XOUT E Open R Vss 1kQ or more External oscillation circuit Fig 60 External clock input circuit 1 70 4519 Group 7 Clock control register MR Register MR controls system clock Set the contents of this register through register A with the TMRA instruction In addition the TAMR instruction can be used to transfer the contents of register MR to register A Table 23 Clock control registers Clock control register MR at reset 11112 HARDWARE FUNCTION BLOCK OPERATIONS 8 Clock control register RG Register RG controls start stop of on chip oscillator Set the con tents of this register through register A with the TRGA instruction at RAM back up 11112 Operation mode Through mode frequency not divided Operation mode selection bits Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock f XIN oscillation enabled Main clock f XIN oscillation circuit control bit Main clock f XIN oscillation stop System clock oscillation source selection bit Main clock f XIN Clock control register RG at reset 02 Main clock f RING at RAM back up 02 On chip oscillator f RING control bit On chip oscillator f RING oscillation enabled Note R represents read enabled and W
346. tected Port block diagram 8 Rev 1 00 Aug 06 2004 RENESAS 1 16 REJO9B0175 0100Z 4519 Group FUNCTION BLOCK OPERATIONS CPU 1 Arithmetic logic unit ALU The arithmetic logic unit ALU performs 4 bit arithmetic such as 4 bit data addition comparison AND operation OR operation and bit manipulation 2 Register A and carry flag Register A is a 4 bit register used for arithmetic transfer ex change and I O operation Carry flag CY is a 1 bit flag that is set to 1 when there is a carry with the AMC instruction Figure 1 It is unchanged with both A n instruction and AM instruction The value of Ao is stored in carry flag CY with the RAR instruction Fig ure 2 Carry flag CY can be set to 1 with the SC instruction and cleared to 0 with the RC instruction 3 Registers B and E Register B is a 4 bit register used for temporary storage of 4 bit data and for 8 bit data transfer together with register A Register E is an 8 bit register It can be used for 8 bit data transfer with register B used as the high order 4 bits and register A as the low order 4 bits Figure 3 Register E is undefined after system is released from reset and re turned from the RAM back up Accordingly set the initial value 4 Register D Register D is a 3 bit register It is used to store a 7 bit ROM address together with register A and is used as a pointer within the specified page when the TABP p BLA p or BMLA p ins
347. ter B to the high order 4 bits of timer 1 reload register R1 and transfers the contents of register A to the low order 4 bits of timer 1 reload register R1 Transfers the contents of register B to the high order 4 bits of timer 3 reload register R3 and transfers the contents of register A to the low order 4 bits of timer 3 reload register R3 Transfers the contents of timer 4 reload register R4L to timer 4 Rev 1 00 Aug 06 2004 RENESAS 1 139 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code S5 5 89 99 Function Su eo Type of MSIE Hexadecimal E E gt NA D9 Ds D7 De Ds D4 Ds D2 Di Do 3 3 instruction notation z z SNZT1 1 01 000000 0 280 1 1 V1220 T1F 1 After skipping T1F 0 V12 2 0 NOP S snzt2 1 0 10000001 281 1 1 Vl3 0 T2F 1 After skipping T2F 0 V13 0 NOP 2 e SNZT3 1 0 1 0 0 0 0 0 1 0 28 2 1 1 V20 0 T3F 1 After skipping T3F 0 g V20 0 NOP E SNZT4 1 01 00000 1 1 283 1 1 V21 0 T4F 1 After skipping T4F 0 V21 2 0 NOP APO 1 0 O 1 1 0000 0 260 1 1 A lt PO OPOA 1 0 0 O 1 0000 0 220 1 1 PO lt A IAP1 1 0 O 1 1 0 0 0 0 1 26 1 1 1 A P1 OP1A 1 0001 00 0 0 1 22 1 1 1 P1 A IAP2 1 0 O 1 1 0 0 0 1 0 262 1 1 A2 Ao P22 P20 A3 lt 0 OP2A 100010001 0 222 1 1 P22 P20 A2 Ao IAP3 1 0 O 1
348. terrupt control register V2 shown in Figure 42 TJ1A and TV2A instructions TJ1A and TV2A instructions Setting the port received the reception enable signal SRDY to the input mode Port D3 is used in this example Setting the port transmitted the reception enable signal SRDY and outputting H level reception impossible Port D3 is used in this example SD instruction SD instruction Transmission enable state Storing transmission data to serial I O register SI Reception enable state The SIOF flag is cleared to 0 TSIAB instruction SST instruction L level reception possible is output from port D3 RD instruction Transmission Check port D3 is L level SZD instruction Serial transfer starts SST instruction Check transmission completes Reception Check reception completes SNZSI instruction SNZSI instruction Wait timing when continuously transferring H level is output from port D3 SD instruction Data processing 1 byte data is serially transferred on this process Subsequently data can be transferred continuously by repeating the process from When an external clock is selected as a synchronous clock the clock is not controlled internally Control the clock externally be cause serial transfer is performed as long as clock is externally input Unlike an internal clock
349. terrupt program example 2 sss eene 1 29 Fig 20 External O interrupt program example 3 sse eene 1 29 Fig 21 External 1 interrupt program example 1 sssssseeeenmeens 1 30 Fig 22 External 1 interrupt program example 2 sse eee eee ee eee eee eee eee 1 30 Fig 23 External 1 interrupt program example 3 sss eee 1 30 Fig 24 Auto reload TUN CUO exorcista altas 1 31 Fig 25 Timer structure Dacia ed dl 1 33 F19 26 Tier SUUCIUULES 2 taa es 1 34 Fig 27 Period measurement circuit program example sse ee see ee esse esse ee ee essere sese enen 1 39 Fig 28 Period measurement circuit program example eee eee eee eee eee eee eee eee 1 41 Fig 29 Timer 4 operation reload register R4L 0316 RAH 0216 se 1 42 Fig 30 CNTR1 output auto control function by timer 3 sssssssssssseeeeee 1 43 Fig 31 Timer 4 count start stop timing sssssssssseeeeeeneeeen nennen ens 1 44 Fig 32 Watchdog timer FUNCION cocina e ede eti eed adit and site ed deuda 1 45 Fig 33 Program example to start stop watchdog timer ssssee 1 46 Fig 34 Program example to enter the mode when using the watchdog timer 1 46 Fig 35 A D conversion circuit structure oooconncccnnnnnnoccccnnn arena 1 47 19 96 A D conversion UMINO CNA eene eer eerta qut drea eene Bac tne dada illa 1 50 Fig 97 Setting TOS Sucina ias 1 50 Fig 38 Comparator operation t
350. terrupt service routine referred to as an inter rupt service routine performing a subroutine call or executing the table reference instruction TABP p Stack registers SKs are eight identical registers so that subrou tines can be nested up to 8 levels However one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction Accordingly be care ful not to over the stack when performing these operations together The contents of registers SKs are destroyed when 8 lev els are exceeded The register SK nesting level is pointed automatically by 3 bit stack pointer SP The contents of the stack pointer SP can be transferred to register A with the TASP instruction Figure 5 shows the stack registers SKs structure Figure 6 shows the example of operation at subroutine call 6 Interrupt stack register SDP Interrupt stack register SDP is a 1 stage register When an inter rupt occurs this register SDP is used to temporarily store the contents of data pointer carry flag skip flag register A and regis ter B just before an interrupt until returning to the original routine Unlike the stack registers SKs this register SDP is not used when executing the subroutine call instruction and the table refer ence instruction 7 Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip ins
351. the bit 2 of register 12 In addition execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction refer to Figure 670 Also set the NOP instruction for the case when a skip is per formed with the SNZ1 instruction refer to Figure 67G LA XX0X2 TV1A The SNZ1 instruction is valid LA 12 X1XX2 TI2A Interrupt valid waveform is changed NOP SNZ1 The SNZ1 instruction is executed EXF1 flag cleared NOP X these bits are not used here Fig 67 External 1 interrupt program example 3 1 75 4519 Group A D converter 1 When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A si multaneously the low order 2 bits of register A is 0 Do not change the operating mode both A D conversion mode and comparator mode of A D converter with the bit 3 of register Q1 while the A D converter is operating Clear the bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to A D conversion mode The A D conversion completion flag ADF may be set when the operating mode of the A D converter is changed from the com parator mode to the A D conversion mode Accordingly set a value to the register Q1 and execute the SNZAD instruction to clear the ADF flag X0XX2 The SNZAD instruction is valid 0XXX2 Operation mode of A D converte
352. the input of INT1 pin to be disabled be careful about the following note When the input of INT1 pin is disabled register 123 0 clear bit 2 of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode Rev 1 00 Aug 06 2004 RENESAS 2 13 REJ09BO0175 0100Z APPLICATION 4519 Group 2 1 1 0 pins Table 2 1 13 Connections of unused pins Pin Connection Usage condition XIN Open Internal oscillator is selected Note 1 XOUT Open Internal oscillator is selected Note 1 RC oscillator is selected Note 2 External clock input is selected for main clock Note 3 Do D5 Open Connect to Vss N channel open drain is selected for the output structure Note 4 De CNTRO Open CNTRO input is not selected for timer 1 count source Connect to Vss N channel open drain is selected for the output structure Note 4 D7 CNTR1 Open CNTR1 input is not selected for timer 3 count source Connect to Vss N channel open drain is selected for the output structure Note 4 P00o P03 Open The key on wakeup function is not selected Note 6 Connect to Vss N channel open drain is selected for the output structure Note 5 The pull up function is not selected Note 4 The key on wakeup function is not selected Note 6 P10 P13 Open The key on wakeup function is not selected Note 7 Connect to Vss N channel o
353. the input state of the P31 INT1 pin the external 1 Depending on the input state of the P31 INT1 pin the external 1 interrupt request flag EXF1 may be set when the bit 3 of regis interrupt request flag EXF1 may be set when the bit 2 of regis ter 12 is changed In order to avoid the occurrence of an ter 12 is changed In order to avoid the occurrence of an unexpected interrupt clear the bit 1 of register V1 to 0 refer to unexpected interrupt clear the bit 1 of register V1 to 0 refer to Figure 210 and then change the bit 3 of register I2 Figure 230 and then change the bit 2 of register I2 In addition execute the SNZ1 instruction to clear the EXF1 flag to In addition execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction refer to Figure 210 0 after executing at least one instruction refer to Figure 239 Also set the NOP instruction for the case when a skip is per Also set the NOP instruction for the case when a skip is per formed with the SNZ1 instruction refer to Figure 21G formed with the SNZ1 instruction refer to Figure 23G LA XX0X2 TV1A The SNZ1 instruction is valid LA 12 X1XX2 TI2A Interrupt valid waveform is changed NOP XX0X2 The SNZ1 instruction is valid 01XXX2 Control of INT1 pin input is changed SNZ1 The SNZ1 instruction is executed EXF1 flag cleared The SNZ1 instruction is executed EXF1 flag cleared
354. the switch of system clock cannot be executed at the same time when main clock oscillation is started In order to use the external clock input for the main clock select the ceramic resonance by executing the CMCK in struction at the beggining of software and then set the main clock f XIN oscillation to be valid MR1 0 Until the main clock f XIN oscillation becomes valid MR1 0 after ceramic resonance becomes valid XIN pin is fixed to H When an external clock is used insert a 1 kO resistor to XIN pin in series for limits of current Be sure to select the output structure of ports Do D5 and the pull up function of POo P03 and P10 P13 with every one port Set the corresponding bits of registers for each port Be sure to select the output structure of ports POo P03 and P10 P13 with every two ports If only one of the two pins is used leave another one open The key on wakeup function is selected with every two bits When only one of key on wakeup function is used con sidering that the value of key on wake up control register K1 set the unused 1 bit to H input turn pull up transistor ON and open or L input connect to Vss or open and set the output latch to 0 The key on wakeup function is selected with every two bits When one of key on wakeup function is used turn pull up transistor of unused one ON and open Note when connecting to Vss and VDD Connect the unused pins to
355. then execute the T2AB or TAB2 instruction to read or set timer 2 data Timer 2 starts counting after the following process O set data in timer 2 select the count source with the bits 0 and 1 of register W2 and set the bit 2 of register W2 to 1 When a value set in reload register R2 is n timer 2 divides the count source signal by n 1 n 0 to 255 Once count is started when timer 2 underflows the next count pulse is input after the contents of timer 2 becomes 0 the timer 2 interrupt request flag T2F is set to 1 new data is loaded from reload register R2 and count continues auto reload function Timer 2 underflow signal divided by 2 can be output from CNTRO pin by setting bit 3 of register W2 to 1 and setting bit 0 of register WG to 1 5b Timer 3 interrupt function Timer 3 is an 8 bit binary down counter with the timer 3 reload reg ister R3 Data can be set simultaneously in timer 3 and the reload register R3 with the T3AB instruction Data can be written to re load register R3 with the TR3AB instruction Data can be read from timer 3 with the TAB3 instruction Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data When executing the TR3AB instruction to set data to reload regis ter R3 while timer 3 is operating avoid a timing when timer 3 underflows Timer 3 starts counting after the following process O set data in timer 3 Q set count source
356. time initialize the flag WDF1 with the WRST instruction before system goes into the RAM back up state 5 Port P30 INTO pin When the RAM back up mode is used by clearing the bit 3 of register 11 to 0 and setting the input of INTO pin to be disabled be careful about the following note When the input of INTO pin is disabled register l1s 0 clear bit O of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode 6 Port P3 INT1 pin When the RAM back up mode is used by clearing the bit 3 of register I2 to 0 and setting the input of INT1 pin to be disabled be careful about the following note e When the input of INT1 pin is disabled register 12s 0 clear bit 2 of register K2 to 0 to invalidate the key on wakeup before system goes into the RAM back up mode Rev 1 00 Aug 06 2004 RENESAS 3 19 REJ09BO0175 0100Z APPENDIX 4519 Group 3 3 List of precautions 3 3 10 Notes on clock control 1 Clock control Execute the main clock f Xin selection instruction CMCK CRCK or CYCK instruction in the initial setting routine of program executing it in address O in page 0 is recommended The oscillation circuit by the CMCK CRCK or CYCK instruction can be selected only at once The oscillation circuit corresponding to the first executed one of these instructions is valid The CMCK CRCK or CYCK instructions can be used only to select main clock f Xin In this time the start of osci
357. timer 1 to regis ter A Transfers the contents of register B to the high order 4 bits of timer 1 and timer 1 reload register R1 and transfers the contents of register A to the low order 4 bits of timer 1 and timer 1 reload register R1 Transfers the high order 4 bits of timer 2 to register B and transfers the low order 4 bits of timer 2 to regis ter A Transfers the contents of register B to the high order 4 bits of timer 2 and timer 2 reload register R2 and transfers the contents of register A to the low order 4 bits of timer 2 and timer 2 reload register R2 Transfers the high order 4 bits of timer 3 to register B and transfers the low order 4 bits of timer 3 to regis ter A Transfers the contents of register B to the high order 4 bits of timer 3 and timer 3 reload register R3 and transfers the contents of register A to the low order 4 bits of timer 3 and timer 3 reload register R3 Transfers the high order 4 bits of timer 4 to register B and transfers the low order 4 bits of timer 4 to regis ter A Transfers the contents of register B to the high order 4 bits of timer 4 and timer 4 reload register R4L and transfers the contents of register A to the low order 4 bits of timer 4 and timer 4 reload register R4L Transfers the contents of register B to the high order 4 bits of timer 4 reload register R4H and transfers the contents of register A to the low order 4 bits of timer 4 reload register RAH Transfers the contents of regis
358. timer control register W2 to register A Transfers the contents of register A to timer control register W2 Transfers the contents of timer control register W3 to register A Transfers the contents of register A to timer control register W3 Transfers the contents of timer control register W4 to register A Transfers the contents of register A to timer control register W4 3 NE SAS 1 137 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY TYPES MACHINE INSTRUCTIONS INDEX BY TYPES continued Parameter Instruction code S5 5 89 99 Function gojege Type of aiiai Hexadecimal 2 t gt l De Ds D7 De Ds D4 D3 D2 Di Do 2 2 instruction notation TAW5 1 0 0 1 0 O 1 1 1 1 24F 1 1 A W5 TW5A 1 00001 00 1 0 212 1 1 W5 lt A TAW6 1 0 O 1 01 000 0 250 1 1 A W6 TW6A 1 00001 0 0 1 1 213 1 1 W6 lt A TABPS 1 0 O 1i 1 10 0 1 0 1 275 1 1 B e TPS7 TPS4 A TPSs TPSo TPSAB 1000 1 1 0 1 0 1 235 1 1 RPS7 RPS4 B TPS7 TPSa B RPSs RPSo0 A TPS3 TPSo A TAB1 1 00 111000 0 97011 1 B e T17 T14 A T13 T10 T1AB 10001 10000 230 11 1 R17 R14 B T17 T14 B R13 R10 e A T13 T10 A TAB2 1 00 11 100 0 1 271 1 1 B T27 T24 A T23 T20 T2AB 1 000 1 1 0 0 0 1 23 1 1 1 R27 R24 B E T27 T24 B S R23 R20 A I T23 T20 A oO Q 9 TAB3 1 00 11 100 1 0 272 11 1 B T37
359. tion code 1 0 0 0 0 1 0 1 0 1 2 5 o EE 2 16 1 1 E H Operation K2 A Grouping Input Output operation Description Transfers the contents of register A to key on wakeup control register K2 TMA j Transfer data to Memory from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1lo lilolili lili lili 2 j words cycles 2 16 1 1 Operation M DP A Grouping RAM to register transfer X E X EXOR j Description After transferring the contents of register A j 0to 15 to M DP an exclusive OR operation is per formed between register X and the value j in the immediate field and stores the result in register X Rev 1 00 Aug 06 2004 RENESAS 1 122 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TMRA Transfer data to register MR from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1 lo lo lolo 1 o 1 1 o 2 1 o Wes i Solos 2 16 1 1 Operation MR A Grouping Other operation TPAA Transfer data to register PA from Accumulator Description Transfers the contents of register A to clock control register MR Instruction Dg Do Number of Number of Flag CY Skip condition code 1 0 1 0 1 0 1 0 1 0 2 A A
360. tion flag SIOF is set to 1 when serial data transmission or reception completes The state of SIOF flag can be examined with the skip instruction SNZSI Use the in terrupt control register V2 to select the interrupt or the skip instruction The SIOF flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Transfer data set Transfer start Transfer complete 7tENESAS HARDWARE FUNCTION BLOCK OPERATIONS At receive Serial I O register SI 3 Serial I O start instruction SST When the SST instruction is executed the SIOF flag is cleared to 0 and then serial I O transmission reception is started 4 Serial 1 O control register J1 Register J1 controls the synchronous clock P20 Sck P21 SouT and P22 SIN pin function Set the contents of this register through register A with the TJ1A instruction The TAJ1 instruction can be used to transfer the contents of register J1 to register A 1 54 4519 Group 5 How to use serial I O Figure 42 shows the serial I O connection example Serial I O inter rupt is not used in this example In the actual wiring pull up the Master clock control HARDWARE FUNCTION BLOCK OPERATIONS wiring between each pin with a resistor Figure 42 shows the data transfer timing and Table 16 shows the data transfer sequence Slave external clock SRDY sig
361. tions index by function 4 Instruction code table Contents Contents Register A 4 bits Register B 4 bits Register DR 3 bits Register E 8 bits Interrupt control register V1 4 bits Interrupt control register V2 4 bits Interrupt control register 11 4 bits Interrupt control register I2 4 bits Clock control register MR 4 bits Clock control register RG 1 bit Timer control register PA 1 bit Timer control register W1 4 bits Timer control register W2 4 bits Timer control register W3 4 bits Timer control register W4 4 bits Timer control register W5 4 bits Timer control register W6 4 bits Serial I O control register J1 4 bits A D control register Q1 4 bits A D control register Q2 4 bits A D control register Q3 4 bits Pull up control register PUO 4 bits Pull up control register PU1 4 bits Port output format control register FRO 4 bits Port output format control register FR1 4 bits Port output format control register FR2 4 bits Port output format control register FR3 4 bits Key on wakeup control register KO 4 bits Key on wakeup control register K1 4 bits Key on wakeup control register K2 4 bits Register X 4 bits Register Y 4 bits Register Z 2 bits Data pointer 10 bits It consists of registers X Y and Z Program counter 14 bits High order 7 bits of program counter Low order 7 bits of program counter Stack register 14 bits X 8 Sta
362. transfer 0to 15 Y Y 1 Note p is 0 to 47 for M34519M6 p is 0 to 63 for M34519M8 E8 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 114 130 128 130 128 130 7tENESAS oR A3 A0 DR1 e B ROM PC 7 4 A ROM PO 3 0 PC SK SP SP SP 1 lt ROM PC 9 A lt A M DP A A M DP CY Carry CY A A n n 0to 15 A A AND M DP A A OR M DP CY 1 CY 0 ASA2A1A0 8 111 132 92 132 101 132 103 132 102 132 108 132 94 132 101 132 1 86 4519 Group INDEX LIST OF INSTRUCTION FUNCTION continued Mnemonic Function HARDWARE INDEX OF INSTRUCTION FUNCTION Mnemonic Function Page SBj RBj Bit operation SZB j Mj DP lt 1 j Oto3 Mj DP 0 j20t03 Mj DP 0 j20t03 Comparison operation A M DP 7 A 2n n 0to 15 104 132 104 132 Branch operation PCL ae ao PCH p PCL ae ao PCH p PCL DR2 DRo A3 Ao 92 134 92 134 Interrupt operation 92 134 Subroutine operation DI EI INTE 0 INTE 1 V10 0 EXF0 21 After skipping EXFO 0 V10 1 NOP V11 20 EXF1 21 After skipping EXF1 0 V11 2 1 NOP H2 1 INTO H H2 lt 0 INTO lt L 122 1
363. transfer rate Figure 2 5 1 shows the serial I O block diagram Synch Serial I O counter 3 SIOF Serial I O INSTCK interrupt P2o Sck C ES SST instruction Internal reset signal P21 Sour St lt 4 pasan ON gt a MSB Serial I O register 8 LS B TABSI a TSIAB TABSI Register B 4 Register A 4 Fig 2 5 1 Serial I O block diagram Rev 1 00 Aug 06 2004 RENESAS 2 58 REJ09B0175 0100Z APPLICATION 4519 Group 2 5 Serial lO 2 5 2 Related registers 1 Serial I O register SI Serial I O register Sl is the 8 bit data transfer serial parallel conversion register Data can be set to register SI through registers A and B with the TSIAB instruction Also the low order 4 bits of register Sl is transferred to register A and the high order 4 bits of register SI is transferred to register B with the TABSI instruction 2 Serial I O transmit receive completion flag SIOF Serial I O transmit receive completion flag SIOF is set to 1 when serial data transmit or receive operation completes The state of SIOF flag can be examined with the skip instruction SNZSI 3 Interrupt control register V2 Table 2 5 1 shows the interrupt control register V2 Set the contents of this register through register A with the TV2A instruction In addition the TAV2 instruction can be used to transfer the contents of register V2 to register A Table 2 5 1 Interrupt control register V2 at reset 00002 at RAM back up 00002 0 Inte
364. trol register W3 0 b2 Timer 3 stop b1 bO Prescaler output ORCLK selected for Timer 3 count source Timer control register PA Prescaler stop TPAA Set Timer Value and Prescaler Value Timer 3 and prescaler count times are set The formula is shown A below Timer 3 reload register R3 EF16 Timer count value 239 set T3AB Prescaler reload register RPS F916 Prescaler count value 249 set TPSAB amp Clear Interrupt Request Timer 3 interrupt activated condition is cleared Timer 3 interrupt request flag T3F 0 Timer 3 interrupt activated condition cleared SNZT3 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T3F insert the NOP instruction after the SNZT3 instruction y O Start Timer Operation and Prescaler Operation Timer 3 and prescaler temporarily stopped are restarted b3 b0 Timer control register W3 0111011 b2 Timer 3 operation start TW3A bO Timer control register PA 1 Prescaler start TPAA O Enable Interrupts The Timer 3 interrupt which is temporarily disabled is enabled b3 bO Interrupt control register V2 X X X 1 b0 Timer 3 interrupt occurrence enabled TV2A Interrupt enable flag INTE 1 All interrupts enabled El y Constant period interrupt execution started A The prescaler count value and
365. truction is executed Also when the TABP p instruction is executed the high order 2 bits of the reference data in ROM is stored to the low order 2 bits of register D and the con tents of the high order 1 bit of register D is 0 Figure 4 Register D is undefined after system is released from reset and re turned from the RAM back up Accordingly set the initial value TABP p instruction HARDWARE FUNCTION BLOCK OPERATIONS Carry Result Fig 1 AMC instruction execution example Clear RC instruction Set SC instruction FEA lt Rotation gt Y RAR instruction STT Fig 2 RAR instruction execution example Register B TAB instruction Register A Register B TBA instruction Register A Specifying address J PCH pe ps ps ps pe pt po Immediate field value p register D Fig 4 TABP p instruction execution example Rev 1 00 Aug 06 2004 REJ09B0175 0100Z x PCL DRADRiDRd As A2 A1 Ao The contents of The contents of register A 2tENESAS Low order 4bits Register A 4 Middle order 4 bits Register B 4 High order 2 bits Register D 3 High order 1 bit of reaister D is 0 4519 Group b Stack registers SKs and stack pointer SP Stack registers SKs are used to temporarily store the contents of program counter PC just before branching until returning to the original routine when branching to an in
366. truction when the contents of bit O V20 of interrupt control register V2 is 0 and the con tents of T3F flag is 1 After skipping clears 0 to T3F flag Skips the next instruction when the contents of bit 1 V21 of interrupt control register V2 is 0 and the con tents of T4F flag is 1 After skipping clears 0 to T4F flag D Y 0 However Y 0 to 7 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Transfers the input of port PO to register A Outputs the contents of register A to port PO Transfers the input of port P1 to register A Outputs the contents of register A to port P1 Transfers the input of port P2 to register A Outputs the contents of register A to port P2 Transfers the input of port P3 to register A Outputs the contents of register A to port P3 Transfers the input of port P4 to register A Outputs the contents of register A to port P4 Transfers the input of port P5 to register A Outputs the contents of register A to port P5 Transfers the input of port P6 to register A Outputs the contents of register A to port P6 Sets 1 to all port D Clears 0 to a bit of port D specified by register Y Sets 1 to a bit of port D specified by register Y Skips the next instruction when a bit of port D specified by register Y is 0 Executes the next instruction when a bit of port D specified by register Y is 1 Transfers the contents of pull up control register PUO to register
367. tructions When an interrupt oc curs the contents of skip flag is stored automatically in the interrupt stack register SDP and the skip condition is retained Rev 1 00 Aug 06 2004 REJO9B0175 0100Z 7tENESAS HARDWARE FUNCTION BLOCK OPERATIONS Program counter PC Executing BM Executing RT instruction instruction 0 1 2 3 4 5 6 7 Stack pointer SP points 7 at reset or returning from RAM back up mode It points 0 by executing the first BM instruction and the contents of program counter is stored in SKo When the BM instruction is executed after eight stack registers are used SP 7 SP 0 and the contents of SKo is destroyed Fig 5 Stack registers SKs structure SP 0 SKo 000116 PC SUB1 Main program Subroutine Address 000016 NOP 000116 BM SUB1 000216 NOP Note Returning to the BM instruction execution address with the RT instruction and the BM instruction becomes the NOP instruction Fig 6 Example of operation at subroutine call 4519 Group 8 Program counter PC Program counter PC is used to specify a ROM address page and address It determines a sequence in which instructions stored in ROM are read It is a binary counter that increments the number of instruction bytes each time an instruction is executed However the value changes to a specified address when branch instructions subroutine call instructions return instructions or the table refer
368. tus by the continuous description of the LA LXY in struction register A and register B to the states just before interrupt Rev 1 00 Aug 06 2004 RENESAS 1 102 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued RTS ReTurn from subroutine and Skip Instruction Dg Do Number of Number of Flag CY Skip condition code o lolol lololo i lola o a s le ms rs f 1 2 Skip at uncondition Operation PC SK SP Grouping Return operation SP SP 1 Description Returns from subroutine to the routine called the subroutine and skips the next in struction at uncondition SB j Set Bit Instruction Dg Do Number of Number of Flag CY Skip condition code C words cycles 0j0 0 1 0 1 1 1 j j 0 5 tihe 1 1 Operation Mj DP 1 Grouping Bit operation j 0to3 Description Sets 1 the contents of bit j bit specified by the value j in the immediate field of M DP SC Set Carry flag Instruction Dg Do Number of Number of Flag CY Skip condition code oloele o ololo 1 1 lo o z XR EES 2 16 1 1 1 Operation CY 1 Grouping
369. ubroutine nesting is 8 CLD CLear port D Instruction Dg Do Number of Number of Flag CY Skip condition code ojo jo ojo 1lololo 1 o 1 1 wees ous 2 16 1 1 E E Operation D 1 Grouping Input Output operation Description Sets 1 to port D Rev 1 00 Aug 06 2004 RENESAS 1 93 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued CMA CoMplement of Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code ololololol111l1lolo C is words cycles 1 1 Operation A lt A Grouping Arithmetic operation Description Stores the one s complement for register A s contents in register A CMCK Clock select ceraMic oscillation ClocK Instruction D9 Do Number of Number of Flag CY Skip condition code 1lol lolo lilifolilo l l2fl la wore cycles 2 16 1 1 Operation Ceramic oscillation circuit selected Grouping Clock control operation Description Selects the ceramic oscillation circuit for main clock f XIN CRCK Clock select Rc oscillation ClocK Instruction Dg Do Number of Number of Flag CY Skip condition code 1 0 1 0 0
370. uction In addition the TAI2 instruction can be used to transfer the contents of register I2 to register A Table 2 8 5 Interrupt control register 12 at reset 00002 at RAM back up state retained Interrupt control register 12 R W 123 INT1 pin input control bit Note 2 9 E 1 INT1 pin input enabled interrupt valid waveform tor INTI 0 Falling waveform L level L level is recognized with 122 pin return level selection bit Me eeu etn Note 2 1 Rising waveform H level H level is recognized with the SNZI1 instruction 101 INT1 pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected 120 INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit not selected synchronous circuit selection bit Timer 3 count start synchronous circuit selected Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 122 and 123 are changed the external interrupt request flag EXF1 may be set to 1 Accordingly clear EXF1 flag with the SNZ1 instruction when the bit 1 V11 of register V1 to 0 In this time set the NOP instruction after the SNZ1 instruction for the case when a skip is performed with the SNZ1 instruction 3 When setting the RAM back up 121 120 are not used Rev 1 00 Aug 06 2004 RENESAS 2 74 REJO9B0175 0100Z APPLICATION 4519 Group 2 8 RAM back up 3 Pull up control registe
371. umber of Flag CY Skip condition code 1lo o o 1folof1folo 4 Words _ cycles P 1 1 z Operation P4 A Grouping Input Output operation Description Outputs the contents of register A to port P4 OP5A Output port P5 from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1 1olo o s o o s1 o 1 5 Walks cycles 2 16 1 1 Operation P5 A Grouping Input Output operation Description Outputs the contents of register A to port P5 OP6A Output port P6 from Accumulator Instruction D9 Do Number of Number of Flag CY Skip condition code 1 o o o 1 o o 1 1 o Worgs cycles 2 16 1 1 Operation P6 A Grouping Input Output operation Description Outputs the contents of register A to port P6 Rev 1 00 Aug 06 2004 RENESAS 1 100 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued OR logical OR between accumulator and memory Instruction Do Do Number of Number of Flag CY Skip condition words cycles code 0 0 0 0 0 1 1 0 1 Be y 1 1 Operation A A OR M DP Grouping
372. umber of Flag CY Skip condition code ololojlolo o o olo 1 o o words _ cycles 2 16 1 1 E H Operation System reset occurrence Grouping Other operation Description System reset occurs SST Serial i o transmission reception STart Instruction Dg Do Number of Number of Flag CY Skip condition code 1 0 1 0 0 1 1 1 1 0 2 9 E XR cycles 2 16 1 1 Operation SIOF 0 Grouping Serial I O operation Serial I O transmission reception start Description Clears 0 to SIOF flag and starts serial I O SZB j Skip if Zero Bit Instruction Dg Do Number of Number of Flag CY Skip condition code o 1010101110101011 ji jo 2 i he words cycles 1 1 Mj DP 0 j20t03 Operation Mj DP 0 Grouping Bit operation j20to3 Description Skips the next instruction when the con tents of bit j bit specified by the value j in the immediate field of M DP is 0 Executes the next instruction when the con tents of bit j of M DP is 1 Rev 1 00 Aug 06 2004 RENESAS 1 107 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued SZC Skip if Zero Carry flag Instruction Do Do Number of Number of Flag CY Skip condition code olololol4 1 o 2 r words cycles 1 1 CY 0 Operation CY
373. unt start synchronous circuit is selected 1102 1 Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS 1 79 4519 Group Timer control register W3 HARDWARE CONTROL REGISTERS R W at reset 00002 TAW3 TW3A at RAM back up state retained Timer 3 count auto stop circuit selection bit Note 2 Timer 3 count auto stop circuit not selected Timer 3 count auto stop circuit selected Timer 3 control bit Stop state retained Operating Timer 3 count source selection bits Timer control register W4 Count source PWM signal PWMOUT Prescaler output ORCLK Timer 2 underflow signal T2UDF CNTR1 input R W at RAM back up 00002 TAW4 TW4A at reset 00002 D7 CNTR1 pin function selection bit D7 I O CNTR1 input CNTR1 1 0 D7 input PWM signal H interval expansion function control bit PWM signal H interval expansion function invalid PWM signal H interval expansion function valid Timer 4 control bit Stop state retained Operating Timer 4 count source selection bit Timer control register W5 XIN input Oo joOj O 0O Prescaler output ORCLK divided by 2 R W at reset 00002 TAW5 TW5A at RAM back up state retained Not used This bit has no function but read write is enabled Period measurement circuit control bit Stop Operating Signal for period
374. untermeasures are effective against noise in theory however it is necessary not only to take measures as follows but to evaluate before actual use 3 4 1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less the possibility of noise insertion into a microcomputer 1 Package Select the smallest possible package to make the total wiring length short O Reason The wiring length depends on a microcom puter package Use of a small package for example QFP and not DIP makes the total wiring length short to reduce influence of noise Fig 3 4 1 Selection of packages Rev 1 00 Aug 06 2004 REJO9B0175 0100Z ENESAS APPENDIX 3 4 Notes on noise 2 Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible Especially connect a capacitor across the RESET input pin and the Vss pin with the shortest possible wiring O Reason In order to reset a microcomputer correctly 1 machine cycle or more of the width of a pulse input into the RESET pin is required If noise having a shorter pulse width than this is input to the RESET input pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway
375. up HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued AND logical AND between accumulator and memory Instruction Dg Do Number of Number of Flag CY Skip condition code 0 o0 o olo 1 1 0 0 0 lolis words cyclos 2 16 1 1 Operation A A AND M DP Grouping Arithmetic operation Description Takes the AND operation between the con tents of register A and the contents of M DP and stores the result in register A B a Branch to address a Instruction Dg Do Number of Number of Flag CY Skip condition code o 1 1 agl as aal aal agl a1 aol 1 S a NORIS cyeles 2 a 16 1 1 H H Operation PCL lt ae to ao Grouping Branch operation Description Branch within a page Branches to address a in the identical page Note Specify the branch address within the page including this instruction BL p a Branch Long to address a in page p Instruction Dg Do Number of Number of Flag CY Skip condition code E words cycles 079 1 1 1 Ba p3 p l pt po O Jap P he 2 2 1 O p5s a6 a5 a4 a3 a2 at a0 2 EET Grouping Branch operation Operation PCH
376. up by connecting keys externally because port D output structure is an N channel open drain and port PO has the pull up resistor Outline The connecting required external part is just keys Specifications Port D is used to output L level and port PO is used to input 16 keys Figure 2 1 1 shows the key input and Figure 2 1 2 shows the key input timing M34519 Fig 2 1 1 Key input by key scan Switching key input selection port Do gt D1 Stabilizing wait time for input Reading port key input Key input period Ey d E n IAPO Input to Input to Input to Input to Input to SW1 SW4 SW5 SW8 SW9 SW12 SW13 SW16 SW1 SWA Note H output of port D becomes high impedance state Fig 2 1 2 Key scan input timing Rev 1 00 Aug 06 2004 RENESAS 2 12 REJO9B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 2 1 4 Notes on use 1 Note when an I O port is used as an input port Set the output latch to 1 and input the port value before input If the output latch is set to 0 L level can be input As for the port which has the output structure selection function select the N channel open drain output structure 2 Noise and latch up prevention Connect an approximate 0 1 uF bypass capacitor directly to the Vss line and the VDD line with the thickest possible wire at the shortest distance and equalize its wiring in width and length The CNVSs pin is also used as the VPP pin programming voltag
377. upt enabled SNZT1 instruction is invalid Interrupt disabled SNZ1 instruction is valid External 1 interrupt enable bit Interrupt enabled SNZ1 instruction is invalid Interrupt disabled SNZO instruction is valid ojloj oj o External 0 interrupt enable bit Interrupt control register V2 at reset 00002 Interrupt enabled SNZO instruction is invalid at RAM back up 00002 R W TAV2 TV2A Interrupt disabled SNZSI instruction is valid Serial I O interrupt enable bit Interrupt enabled SNZSI instruction is invalid Interrupt disabled SNZAD instruction is valid A D interrupt enable bit Interrupt enabled SNZAD instruction is invalid Interrupt disabled SNZTA instruction is valid Timer 4 interrupt enable bit Interrupt enabled SNZTA instruction is invalid Interrupt disabled SNZT3 instruction is valid Timer 3 interrupt enable bit O O O O0 Note R represents read enabled and W represents write enabled 7 Interrupt sequence Interrupts only occur when the respective INTE flag interrupt en able bits V10 V13 V20 V23 and interrupt request flag are 1 The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied The interrupt occurs after 3 machine cycles only when the three interrupt conditions are sat isfied on execution of other than one cycle instructions Refe
378. urther Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you
379. ut Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communicatio
380. ut use set the latch of the specified bit to 1 Ports P60 P63 are also used as AINO AIN3 respectively CONTRO CNTR1 Timer input output CNTRO pin has the function to input the clock for the timer 1 event counter and to output the timer 1 or timer 2 underflow signal divided by 2 CNTR 1 pin has the function to input the clock for the timer 3 event counter and to output the PWM signal generated by timer 4 CNTRO pin and CNTR1 pin are also used as Ports De and D7 respectively INTO INT1 Interrupt input Input INTO pin and INT1 pin accept external interrupts They have the key on wakeup func tion which can be switched by software INTO pin and INT1 pin are also used as Ports P30 and P31 respectively AINO AIN7 Analog input Input A D converter analog input pins AINO AIN7 are also used as ports P60 P63 and P40 P43 respectively Sck Serial I O data I O 1 0 Serial I O data transfer synchronous clock I O pin Sck pin is also used as port P20 SOUT Serial I O data output Output Serial I O data output pin SOUT pin is also used as port P21 SIN Serial 1 O clock input Rev 1 00 Aug 06 2004 REJO9B0175 0100Z Input Serial I O data input pin SIN pin is also used as port P22 2tENESAS 4519 Group MULTIFUNCTION Multifunction Multifunction HARDWARE MULTIFUNCTION DEFINITION OF CLOCK AND CYCLE Multifunction Multifunction CNTRO De C
381. utput started X it can be 0 or 1 lI instruction Fig 2 3 8 PWM output control setting example Rev 1 00 Aug 06 2004 2 44 REJO9B0175 0100Z 7RENESAS APPLICATION 4519 Group 2 3 Timers O Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI Interrupt control register V1 b2 Timer 1 interrupt occurrence disabled TV1A Q Stop Timer Operation Timer 1 interrupt is temporarily disabled Timer 1 count time is set TW1A b2 Timer 1 stop Timer control register W1 b1 b0 XiN input for Timer 1 count source G Select Period Measurement signal CNTR I O port is set as a CNTR input port CNTRO pin input is selected as the period measurement signal b3 b0 Register Y 0 101111 Specify bit position of port D TYA Port De output latch Set to H input SD b3 TFR2A Port output structure control register FR2 X x b2 Port D N channel open drain output selected b3 TW6A Timer control register W6 x X10 b2 Select rising edge b0 Set CNTRO input port TW5A Timer control register W5 b2 Period measurement circuit stop b1 b0 CNTRO pin input for period measurement signa No select Timer 1 Count Start Synchronous Circuit Timer 1 count start synchronous circuit is set to be not selected b3 bo TI1A Interrupt control register 1 x x x 0 bo Timer 1 c
382. w overlaps with a timing to stop timer 4 a hazard may be generated in a CNTR1 output waveform Please review sufficiently 1 40 4519 Group 13 Timer interrupt request flags T1F T2F T3F T4F Each timer interrupt request flag is set to 1 when each timer underflows The state of these flags can be examined with the skip instructions SNZT1 SNZT2 SNZT3 SNZT4 Use the interrupt control register V1 V2 to select an interrupt or a skip instruction An interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction The timer 1 interrupt request flag T1F is not set by the timer 1 under flow signal it is the flag for detecting the completion of period measurement 14 Precautions Note the following for the use of timers Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data Stop counting and then execute the TPSAB instruction to set prescaler data Timer count source Stop timer 1 2 3 and 4 counting to change its count source Reading the count value Stop timer 1 2 3 or 4 counting and then execute the data read instruction TAB1 TAB2 TAB3 TAB4 to read its data Writing to the timer Stop timer 1 2 3 or 4 counting and then execute the data write instruction T1AB T2AB T3AB T4AB to write its data Writing to reload register R1 R3 RAH When writing data to reload register R1 reload register R3
383. wolds cyclos 2 16 1 1 Operation PAo Ao Grouping Timer operation Description Transfers the contents of lowermost bit Ao register A to timer control register PA TPSAB Transfer data to Pre Scaler from Accumulator and register B Instruction Dg Do Number of Number of Flag CY Skip condition code 1 o o o s s o s o l 2 a 5 meres oes 2 16 1 1 Operation RPS7 RPS4 B Grouping Timer operation TPS TPS4 lt B RPS3 RPSo A TPS3 TPSo lt A NE rr Description Transfers the contents of register B to the high order 4 bits of prescaler and prescaler reload register RPS and transfers the con tents of register A to the low order 4 bits of prescaler and prescaler reload register RPS TPUOA Transfer data to register PUO from Accumulator Instruction Dg Do Number of Number of Flag CY Skip condition code 1100 1 D words cycles 2 16 1 1 Operation PUO A Grouping Input Output operation Description Transfers the contents of register A to pull up control register PUO Rev 1 00 Aug 06 2004 RENESAS 1 123 REJO9B0175 0100Z 4519 Group HARDWARE MACHINE INSTRUCTIONS INDEX BY ALPHABET MACHINE INSTRUCTIONS INDEX BY ALPHABET continued TPU1A Transfer data to register PU1 from Accumulator
384. xecute the TAB1 TAB2 TAB3 or TABA instruction to read its data Writing to the timer Stop timer 1 2 3 4 or LC counting and then execute the T1AB T2AB T3AB T4AB or TLCA instruction to write its data Writing to reload register R1 reload register R3 and reload register RAH When writing data to reload register R1 while timer 1 is operating respectively avoid a timing when timer 1 underflows When writing data to reload register R3 while timer 3 is operating respectively avoid a timing when timer 3 underflows When writing data to reload register R4H while timer 4 is operating respectively avoid a timing when timer 4 underflows Timer 4 At CNTR1 output vaild if a timing of timer 4 underflow overlaps with a timing to stop timer 4 a hazard may be generated in a CNTR1 output waveform Please review sufficiently e When H interval extension function of the PWM signal is set to be valid set 0116 or more to reload register RAH Watchdog timer The watchdog timer function is valid after system is released from reset When not using the watchdog timer function stop the watchdog timer function and execute the DWDT instruction the WRST instruction continuously and clear the WEF flag to 0 The watchdog timer function is valid after system is returned from the RAM back up state When not using the watchdog timer function stop the watchdog timer function and execute the DWDT instruction and the WRST instruction cont
385. y on wakeup not used iiis key on wakeup control bit 1 Key on wakeup used Pins P10 P11 0 Key on wakeup not used pee key on wakeup control bit 1 Key on wakeup used Pins P02 P03 0 Key on wakeup not used in key on wakeup control bit 1 Key on wakeup used Pins POo P01 0 Key on wakeup not used ma key on wakeup control bit Key on wakeup used Note R represents read enabled and W represents write enabled 12 Key on wakeup control register K2 Table 2 1 12 shows the key on wakeup control register K2 Set the contents of this register through register A with the TK2A instruction The contents of register K2 is transferred to register A with the TAK2 instruction Table 2 1 12 Key on wakeup control register K2 at reset 00002 at RAM back up state retained Key on wakeup control register K2 R W INT1 pin return condition 0 Return by level K23 S selection bit 1 Return by edge K22 INT1 pin key on wakeup control 0 Key on wakeup invalid bit 1 Key on wakeup valid INTO pin return condition 0 Returned by level K21 selection bit 1 Returned by edge Ko INTO pin key on wakeup control 0 Key on wakeup invalid bit Key on wakeup valid Note R represents read enabled and W represents write enabled Rev 1 00 Aug 06 2004 RENESAS 2 11 REJO9B0175 0100Z APPLICATION 4519 Group 2 1 I O pins 2 1 3 Port application examples 1 Key input by key scan Key matrix can be set
386. y performed at power on power on re set by the built in power on reset circuit When the built in power on reset circuit is used the time for the supply voltage to rise from 0 V until the value of supply voltage reaches the minimum operating voltage must be set to 100 us or less HARDWARE FUNCTION BLOCK OPERATIONS If the rising time exceeds 100 us connect a capacitor between the RESET pin and Vss at the shortest distance and input L level to RESET pin until the value of supply voltage reaches the minimum operating voltage er Pull up transistor Note X pa H Note 2 1 i RESET pin O Dro Internal reset signal gt 4100 us or less vob Note 3 Power on reset circuit output Note TA pr lt 4 Power on reset circuit 1 SRST instruction L BER Voltage drop detection circuit Internal reset signal Watchdog reset signal Reset state Power on Reset released Notes 1 This symbol represents a parasitic diode 2 Applied potential to RESET pin must be VDD or less 3 Keep the value of supply voltage to the minimum value or more of the recommended operating conditions Fig 46 Structure of reset pin and its peripherals and power on reset operation Table 17 Port state at reset Function State Do Ds Do Ds High impedance Notes 1 2 De CNTRO De High impedance Notes 1 2 D7 CNTR1 D7 High impedance Notes
387. ystem goes into the RAM back up mode Rev 1 00 Aug 06 2004 RENESAS 3 12 REJO9B0175 0100Z 4519 Group APPENDIX 3 3 List of precautions Table 3 3 1 Connections of unused pins Pin Connection Usage condition XiN Open Internal oscillator is selected Note 1 Xour Open Internal oscillator is selected Note 1 RC oscillator is selected Note 2 External clock input is selected for main clock Note 3 Do Ds Open Connect to Vss N channel open drain is selected for the output structure Note 4 Ds CNTRO Open CNTRO input is not selected for timer 1 count source Connect to Vss N channel open drain is selected for the output structure Note 4 Dz CNTR1 Open CNTR1 input is not selected for timer 3 count source Connect to Vss N channel open drain is selected for the output structure Note 4 P0c P05 Open The key on wakeup function is not selected Note 6 Connect to Vss N channel open drain is selected for the output structure Note 5 The pull up function is not selected Note 4 The key on wakeup function is not selected Note 6 P1o P 15 Open The key on wakeup function is not selected Note 7 Connect to Vss N channel open drain is selected for the output structure Note 5 The pull up function is not selected Note 4 The key on wakeup function is not selected Note 7 P20 Sck Open Sex pin is not selected Connect to Vss P21 Sout
388. z X 3 X 166 1 System clock Instruction Timer 1 count value clock X it can be 0 or 1 J instruction Fig 2 2 5 Timer 1 constant period interrupt setting example Rev 1 00 Aug 06 2004 RENESAS 2 26 REJ09B0175 0100Z APPLICATION 4519 Group 2 2 Interrupts O Disable Interrupts Timer 2 interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI Interrupt control register V1 b3 Timer 2 interrupt occurrence disabled TV1A Q Stop Timer and Prescaler Operation Timer 2 and prescaler are temporarily stopped Timer 2 count source is selected TW2A b3 b2 Timer 2 stop Timer control register W2 x b1 bO Prescaler output ORCLK selected for Timer 2 count source Timer control register PA Prescaler stop TPAA Set Timer Value and Prescaler Value Timer 2 and prescaler count times are set The formula is shown A below Timer 2 reload register R2 5216 Timer count value 82 set T2AB Prescaler reload register RPS OF16 Prescaler count value 15 set TPSAB Clear Interrupt Request Timer 2 interrupt activated condition is cleared Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared SNZT2 y Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T2F insert the NOP instruction after the SNZ

4519 Group User`s Manual

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