PowerDNA Layer User Manual - United Electronic Industries
Contents
1. 3 Add channels into DMap DqDmapSetEntry pBcb DEVNIN DQ_SSOIN 0 DO_ACB_DATA_RAW 1 amp ioffset DqDmapSetEntry pBcb DEVNOUT DQ_SSOOUT 0 DQ_ACB_DATA_RAW 1 amp ooffset DqDmapInitOps pBcb DgeSetEvent pBcb DQ_eDataAvailable DQ_ePacketLost DQ_eBufferError DQ_ePacketOOB 4 Start operation DqeEnable TRUE amp pBcb 1 FALSE 5 Process data while keep_looping DgeWaitForEvent amp pBcb 1 FALSE timeout amp eventsin if eventsin DQ eDataAvailable datarcvtt printf ndata 08x uint32 ioffset uint32 ooffset datarcv United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 6 Stop operation DgeEnable FALSE amp pBcb 1 FALSE 7 Clean up DqDmapDestroy pBcb DqStopDQEngine pDge DaClosel0M hd0 ifndef _WIN32 DqCleanUpDAQLib tendif United Electronic Industries Inc Tel 508 921 4600 16 www ueidag com Fax 508 668 2350 PowerDNA DIO 40x Layer 17 4 Appendix Appendix A Accessories The following cables and STP boards are available for the DIO 401 2 5 layer DNA PC 902 24V power conversion layer supplies 24V to external devices at up to 40W DNA CBL 37 3ft 37 way flat ribbon cable connects layers to terminal panel DNA DIO 022 Accessory panel for PowerDNA DIO layers DNA STP 37 37 way2. 12 don t matter 3 3 Configuration settings Configuration setting are passed in DgCmdSetCfg function Not all configuration bits apply to DIO 40x layers The following bits are used define DQ_LN_MAPPED 1L lt lt 15 For WRRD DMAP devices automatically selected define DQ_LN_ACTIVE 1L lt lt 1 STS LED status define DQ_LN_ENABLED 1L lt lt 0 enable operations The AO 40x has a range of layer specific settings as follows Upper part of the configuration word DIO 40x specific define DO _1401_HYSTEN 1UL lt lt 18 hysteresis programming is enabled The following modes are reserved for future use define DO_L401_MODESCAN FIFO_MODESCAN single scan update mod no buffer define DQ_L401_MODEDGE 1UL lt lt 16 edge detect mod define DO_L401_MODEFIFO FIFO_MODEFIFO continuous acquisition with FIFO simplified buffer define DO_L401_MODECONT FIFO_MODECONT continuous acquisition buffered DQ_LN_ACTIVE is needed to switch on STS LED on CPU layer DQ_LN_ENABLE enables all operations with the layer 3 4 Channel list settings Channel list is not required United Electronic Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 14 3 5 Layer specific commands and parameters There are two layer specific functions defined e DgAdv40xWrite This function writes 24 bit word to the DIO 40x
3. GND_LEVEL YCC D INPUT 7 EN D LOGIC 3 uS H D 1uF R1 Y 4 DGND 1K CBI D_CONN c1 MF MSMDO14CT PS2502 D 1uF GND 3 3V1 To switch input to a logical one the user should provide current flowing through the LED in the optical isolator The minimum current requirement is 2 4mA The current is limited by resistor R4 and can be as high as 36mA at the maximum input voltage The user can put a current limiting resistor in series with input to limit both current flowing through the LED and the power dissipation inside the PowerDNA cube VCC is required to power ground level DACs to provide ground level reference Inputs will not work properly without supplying VCC unless ground layer feature is disabled internally by shorting ground level to DGND by jumpers United Electronic Industries Inc Tel 508 921 4600 www ueidag com Fax 508 668 2350 PowerDNA DIO 40x Layer 5 Every output circuit is built as follows vec D OUTPUT c2 D LOGIC R5 0 O 1uF 2 DGND CB1 R2 A D_ CONN ct MF MSMDO14CT PS2502 10K O 1uF GND 3 3V1 DGND The maximum current thru the transistor should is limited to 100mA by the CB fuse User should supply VCC to collector of the transistor For testing place a 1k to 10k resistor in line between the Digital Output and ground The voltage across the resistor is the output plus loss United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax
4. 22 4 Dina DOUT3 22 4 DOUTA DIN3 DIN2 21 3 DGND DOUT2 21 3 DGND DIN2 DINO 20 2 DINI pouTo 20 2 pouT DINO A DGND 1_ DGND 19 1 000000000000090909090 35 eeeoeeoeeeegeeeest ees 37 20 Please notice that DIO 405 outputs are numbered from DOut0 through DOut 1 All layers in the DIO 40x family have similar connector layout Note the VCC pins This layer must be supplied power in one of two forms By use of the VCC pins on the DNA STP 37 or STP 37D or DNA DIO 022 terminal panels connect a 5 36V source to the VCC pins By use of the PC 902 power conversion layers which supply power internally and will not break any isolation When power is provided to the layer the RDY LED turns on When no power is supplied the RDY LED is off and the DNA DIO 40x layer will not operate CAUTION To prevent damage to board components VCC must always be equal to or greater than the DIN voltage United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 1 3 Layer capabilities 4 Inputs and outputs of these layers are powered externally The user has to supply from 5V to 24V external power to VCC line Depending on power supply the layer accepts the following levels VCC Input 0 Input 1 Output 0 Output 1 5V 1 2V 3 0V 0 6V 4 5V 24V 5V 12V 2V 22V 36V TV 12V Every input circuit is built as follows
5. 508 668 2350 PowerDNA DIO 40x Layer 7 2 Programming using the UeiDaq Framework This section describes how to control the PowerDNA DIO 401 2 5 using the UeiDaq s framework API The UeiDaq framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C Visual Basic or LabVIEW The following section will focus on the C API but the concept stays the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual to get more information on using other programming languages 2 1 Creating a session The Session object controls all operations on your PowerDNA device Therefore the first task is to create a session object CUeiSession session 2 2 Configuring the resource string The framework uses resource strings to select which device subsystem and channels to use within a session The resource string syntax is similar to a web URL lt device class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA the device class is pdna For example the following resource string selects digital input channels 0 1 2 3 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Di0 3 In the framework a digital channel corresponds to a physical port on the device You cannot configure a session to only access a subset of the lines within a digital port Configure s
6. layer using DOCMD_WRCHNL e DqAdv40xRead This function reads input status using DOCMD_RDCHNL e DqAdv40xSetHyst This function sets hysteresis levels These functions can be called anytime in configuration and operation mode 3 6 Using layer in ACB mode DIO 40x layers currently do not support ACB mode 3 7 Using layer in DMap mode This example shows communication between two layers a layer 0 DI 401 and a layer 1 DO 402 For a DIO 405 DEVNIN and DEVNOUT would be the same and we d assign a value only to bits 0 11 of oof f set and read bits 0 11 ofioff set include PDNA h 1 Start DQE engine ifndef _WIN32 DqInitDAQLIib endif Start engine DgStartDOEngine 1000 10 pDge NULL open communication with IOM DqOpenIOM IOM_IPADDRO DQ_UDP_DAQ PORT TIMEOUT_DELAY amp DORAC g United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 15 Set hysteresis at this point DgAdv40xSetHyst hd0 DEVNIN 0x132 0x2CA Receive IOM crucial identification data DqCmdEcho hd0 DOQRdCfg for i 0 i lt DO_MAXDEVN i if DORdCfg gt devmod i printf Model x Option x n DORdCfg gt devmod i DORdCfg gt option i else break 2 Create and initialize host and IOM sides DqDmapCreate pDge hd0 amp pBcb UPDATE_PERIOD amp dmapin amp dmapout
7. screw terminal panel DNA STP 37D 37 way direct connect screw terminal panel Appendix B Layer verification The DIO 40x layers do not require calibration Layer verification is performed using simod 1 command To access it the user should attach serial interface to the PowerDNA cube and run serial terminal program on the host PC For DIO 40x simod 1 command allows to read and write port r and w command as well as select hysteresis DAC 1 and 2 and adjust it using keys q or Esc causes the routine to exit The verification is done by setting up hysteresis levels default are 25 for low and 75 for high ground levels and continuously reading inputs while changing voltage on inputs The easiest way to verify output is to attach LEDs between layer outputs and DGND in series with proper resistors For example you can use 2 to 4 7 KOhm resistors to limit current flowing thru LEDs United Electronic Industries Inc www ueidag com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 40x Layer 19 United Electronic Industries Inc www ueidaq com Tel 781 821 2890 Fax 781 821 2891
8. 50 PowerDNA DIO 40x Layer 2 1 1 Device architecture Control Logic he o v 1 2 oO x Dd a 32 bit 66 MHz bus Optical Isolation Power In The DIO 40x layers have similar architecture The I O part of the layer is isolated from the logic interface via optocouplers United Electronic Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 3 1 2 Layer connectors and wiring DNA DIO 401 DNA DIO 402 DNA DIO 405 vcc 37497 vcc vcc Bag vcc VCC DGND 36 18 vcc DGND 36 48 vcc DGND DIN23 35 17 DGND DOUT23 35 17 DGND DOUTII DIN21 34 16 DIN22 DOUT21 34 46 DOUT22 DOUT9 DIN20 83 45 DGND DOUT20 33 15 DGND DOUT8 DIN18 32 14 DINI9 DOUT18 82 14 DOUTIS DOUT6 DIN17 3713 DGND DOUT17 34 43_ DGND DOUTS DIN15 30 12 DINI6 DOUTIS 30 42 DOUT16 DOUT3 DIN14 29 41 DGND DOUTI4 29 11 DGND DOUT2 DIN12 28 40 DIN13 DOUTI2 28 40 DOUTI3 DOUTO DIN11 27 9 DGND pouTi 27 9 DGND DIN DIN9 26 8 DINIO DOUT9 26 8 DOUTIO DIN9 DIN8 25 7 DGND DOUT8 25 7 DGND DIN8 DING 24 6 DIN7 DOUT6 24 6 DOUT7 DING DINS 23 5 DGND DOUTS 23 5 DGND DINS DIN3
9. 508 668 2350 PowerDNA DIO 40x Layer ji Table of Contents Introduction nun iii Organization of this manual uueennnnnsnnnnnnnnnnnnnnnnnnnnnnnnnn iii CONVENIO Star iv 1 The DIO 40X Layer cicocinicinic nincanadano caca iaa 1 1 1 Device architecture inci wann 2 1 2 Layer connectors and wiring uuuuuuunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 3 1 3 Layer capabilities isaac rn 4 2 Programming using the UeiDaq Framework ooonccccccccooooooooooooooooooo0os 7 2 1 Creating a session ococcccccnnnnnnnnancccnnnononnnnnnnnnnccnnnr nr renacer 7 2 2 Configuring the resource String ccoonnmnnnnccccncncnnnnnnnananannns 7 2 3 Configuring the timing cccceeeeeseeeeeeeeeeeeeeeeeeeeeeseenenees 8 2 4 Reading data nee 8 2 5 Cleaning up the session uunuuuuunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 9 3 Programming using the Low Level API sssccccccccccceseessesesenenensnes 11 3 1 Programming hysteresis uuuuunnssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 11 3 2 Data representation ciar 12 3 3 Configuration settings uuuruuuu00000000nnnnnnnnnnnnnnnnnnnnnnnn 13 3 4 Channel list settings aan 13 3 5 Layer specific commands and parametels 01 0000 14 3 6 Using layer in ACB mode uunuusssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 14 3 7 Using layer in DMap mode uussuussnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 14 4 AI A A ct oevensueitven ssucssueseeabracestesawess 17 United Electronic Indu
10. PowerDNA DIO 40x User Manual 24 channel Digital O layer for the PowerDNA Cube December 2010 Edition PN Man DNA DIO 40x 1210 Copyright 1998 2010 United Electronic Industries Inc All rights reserved United Electronic Industries Inc Version 3 3 PowerDNA DIO 40x Layer i No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See UEI s website for complete terms and conditions of sale http www ueidag com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidag com FTP Site ftp ftp ueidaq com United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax
11. arameters di_session CleanUp United Electronic Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 11 3 Programming using the Low Level API This section describes how to program the PowerDNA cube using the low level API The low level API offers direct access to PowerDNA DAQBios protocol and also allows you to directly access device registers We recommend that you use the UeiDaq framework see Section 2 above which is easier to use You should only need to use the low level API if you are using an operating system other than Windows 3 1 Programming hysteresis The ground level of the inputs can be set from DGND level to VCC level in 1024 steps increments For the optical isolator to open input level it should be above ground level to at least 2 4V to supply enough current for isolator LED When programmable hysteresis mode is disabled input becomes 1 if input voltage is 2 4V above selected ground level to provide enough current to the isolating LED When programmable hysteresis mode is selected the device logic constantly changes ground level between two programmed levels This change of ground level occurs at 2kHz rate Every time the logic changes ground level it performs read Then the logic produces output based on two consecutive reads at low and high ground level The following table summarizes the result Logic level Read atlow Read
12. at Result Read result High 0 0 1 0 Keep previous value 1 1 1 United Electronic Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 12 The following diagram shows the hysteresis feature The input stays at 0 until it crosses both low and high ground levels If the signal falls below high ground level but never crosses low ground level for more than Ims it remains at 1 Hysteresis is a specific feature of DIO 40x layers To access this feature you should enable it in the configuration word define DO_1401_HYSTEN 1UL lt lt 18 hysteresis programming is enabled By default hysteresis levels are selected at 25 of VCC low and 75 of VCC high User can set hysteresis levels using the layer specific function DqAdv40xSetHyst int hd int devn uintl6 levelO uintl6 levell level0 and levell are 10 bit relative values for low and high hysteresis levels 3 2 Data representation Layer Bits DIO 401 reserved DIn23 12 DIn11 0 DIO 402 reserved DOut23 12 DOut11 0 DIO 405 reserved N A DIn Out11 0 United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 13 Data representation is straightforward Please note that output lines on DIO 405 layer used to occupy bits 11 0 Thus to set up all lines into one you have to write Ox000fff to DIO 405 State of bits 31
13. ession to read from port 0 on device 1 di_session CreateDIChannel pdna 192 168 100 2 Dev1 Di0 Configure session to write to port 0 on device 1 do_session CreateDOChannel pdna 192 168 100 2 Dev1 Do0 United Electronic Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 8 Sessions are unidirectional If your device has both input and output ports or has bidirectional ports you need to configure two sessions one for input and one for output 2 3 Configuring the timing You can configure the DIO 401 2 5 to run in simple mode point by point or buffered mode ACB mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by the DIO 401 2 5 on board clock The following sample shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use the other timing modes di_session ConfigureTimingForSimplel0 2 4 Configuring the hysteresis The PowerDNA DIO 401 2 5 layers are equipped with a hysteresis circuitry whose low and high threshold levels can be programmed using custom properties e lowhysteresis A floating point value representing the low hysteresis voltage as a percentage of the power supply voltage Vcc e highhysteresis A floating point value representing the high hysteresis voltage as a percentage of
14. stries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer iii Introduction This document outlines the feature set and use of the DIO 401 DIO 402 and DIO 404 5 digital input layers for the PowerDNA I O Cube Organization of this manual This PowerDNA DIO 401 2 5 User Manual is organized as follows Introduction This chapter provides an overview of PowerDNA Digital Input Series board features the various models available and what you need to get started The DIO 401 2 5 layer This chapter provides an overview of the device architecture connectivity and logic of the DIO 401 2 5 series layer Programming using the UeiDaq Framework High Level API This chapter provides an overview of the how to create a session configure the session for digital data acquisition output and format relevant output Programming using the Low Level API Low level API commands for configuring and using the DIO 401 2 5 series layer Appendix A Accessories This appendix outlines accessories available for DIO 401 2 5 series layer Appendix B Layer Verification This appendix outlines how to verify calibration for the DIO 401 2 5 series layer United Electronic Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer iv Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight q
15. the power supply voltage Vcc Program low threshold to 10 and high threshold to 90 double lowHyst 0 1 double highHyst 0 9 di_session SetCustomProperty lowhysteresis sizeof double amp lowHyst di_session SetCustomProperty highhysteresis sizeof double amp highHyst 2 5 Reading and Writing data Reading data from the DIO 401 2 5 is done using a reader object The following sample code shows how to create a scaled reader object and read samples United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 9 Create a reader and link it to the session s stream CUeiDigitalReader reader di_session GetDataStream read one scan the buffer must be big enough to contain one value per channel uInt16 data reader ReadSingleScan amp data Writing data is done using a writer object The following sample shows how to create a writer object and write data Create a writer and link it to the session s stream CUeiDigitalWriter writer do_session GetDataStream write one scan the buffer must contain one value per channel ulnt16 data OxFEFE writer WriteSingleScan amp data 2 6 Cleaning up the session The session object will clean itself up when it goes out of scope or when it is destroyed However you can manually clean up the session to reuse the object with a different set of channels or p
16. uick ways to get the job done or reveal good ideas you might not discover on your own Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 40x Layer 1 1 The DIO 40x Layer The DIO 40x layers have the following functions DIO 401 2 5 are digital I O layers DIO 401 has 24 digital inputs DIO 402 has 24 digital outputs DIO 405 has 12 digital inputs and 12 digital outputs Lines handle levels to 36V max VCC on inputs and outputs Lines protected to 1000V peak peak and 7 kV electrostatic Over and under voltage protection to 36V Input rate is 2k samples sec with hysteresis enabled Outputs provide drive capability of 80 mA channel resetable fuse protected to 100mA Inputs have 1024 point programmable low and high hysteresis settings Peak detection Ims Triggering edge detection event time stamping is available on digital inputs at software level Power consumption 2 5W at full load United Electronic Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 23
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