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Senior Project Report - Cal Poly San Luis Obispo

1. Net fpga 0 Ethernet PHY tx en pin LOC P15 Net fpga 0 Ethernet PHY Net fpga 0 Ethernet PHY tx data pin lt 0 gt Net fpga 0 Ethernet PHY tx data pi Net fpga 0 Ethernet PHY tx data pi Net fpga 0 Ethernet PHY tx data pi Net fpga 0 Ethernet PHY tx data pi Net fpga 0 Ethernet PHY tx data pi Net fpga 0 Ethernet PHY tx data pi Net fpga 0 Ethernet PHY tx data pi Net fpga O DDR CLK FB LOC B9 Net fpga 0 DDR CLK FB IOSTANDARD LVCMOS33 Avnet added begin Net fpga 0 DDR CLK FB TNM NET fpga_ TIMESPEC TS fpga 0 DDR CLK FB PERIO NET ddr clk 90 s NM NET DD F NET ddr clk 90 n s NM NET DD E NET dlmb port BRAM Clk NM NET OP NET ddr dev clk s NM NET DD NET ddr dev clk 90 s NM NET DD IMESPEC TS OPB TO Devi FROM OPB CLOCK DDR DEVICE CLOCK TIG IMESPEC TS OPB TO Device90 FROM OPB CLOCK DDR DEVICE CLOCK PHASI TIG IMESPEC TS Device FROM DDR D TIG IMESPEC TS Device TO OPB90 FROM DDR D TIG IMESPEC TS OPB TO DDR FROM OPB CLOCK DDR FEEDBACK CLOCK PHASE 90 TIG IMESPEC TS DDR TO OPB FROM DDR FE TIG OFFSET constraints must be manually adjusted to account for phase OFFSET IN 0 750 ns VALID 3 5 ns BEFORE DDR FEEDBACK CLOCK 90 LOC R11 IOSTANDARD LOC T15 IOSTANDARD LOC R5 IOSTANDARD LOC T5 IOSTANDARD R CLK FB pga 0 DDR CLK FB 1 EDBACK CLOCK PHA
2. config SPI XILINX tristate Xilinx SPI controller depends on SPI MASTER select SPI_BITBANG k help This exposes the SPI controller IP from the Xilinx EDK Experimental Add new SPI master controllers in alphabetical order above this line AR 143 6 151 13 EG config SPI S3C24XX comment SPI Protocol Masters depends on SPI MASTER config SPI SPIDEV tristate User mode SPI device driver support help This supports user mode SPI protocol drivers Note that this application programming interface is EXPERIMENTAL and hence SUBJECT TO CHANGE WITHOUT NOTICE while it stabilizes T Add new SPI protocol masters in alphabetical order above this line diff rupN petalinux svn orig software linux 2 6 x petalogix drivers spi Makefile petalinux svn software linux 2 6 x petalogix drivers spi Makefile petalinux svn orig software linux 2 6 x petalogix drivers spi Makefile 2007 03 30 07 49 34 000000000 0200 petalinux svn software linux 2 6 x petalogix drivers spi Makefile 2009 03 02 10 38 05 000000000 0100 19 9 19 11 obj S CONFIG SPI S3C24XX GPIO spi s obj CONFIG SPI S3C24XX spi s3c24xx o obj CONFIG MCFOSPI mcf_qspi o obj CONFIG DS1305 DS1305RTC o obj CONFIG SPI XILINX xilinx spi o add above this line
3. finclude lt linux types h gt include lt linux version h gt if LINUX VERSION CODE lt KERNEL VERSION 2 6 15 tinclude lt linux device h gt else include lt linux platform_device h gt ffendif 10 100 Mb Ethernet Controller IP XEMAC AR 51 14 47 23 RE define XEMAC DMA SIMPLI simple 2 channel DMA define XEMAC DMA SGDMA 3 scatter gather DMA Gl N 10 100 Mb Ethernet Controller IP XEMACLITE struct xemaclite_platform_data u32 tx ping pong u32 rx ping pong u8 mac addr 6 10 100 1000 Mb Ethernet Controller IP XTEMAC struct xtemac platform data ifdef XPAR TEMAC 0 INCLUDE RX CSUM u8 tx dre rx dre tx csum rx csum phy type CO CO CO CO u u u u endif u8 dma_mode u32 rx_pkt_fifo_depth u32 tx_pkt_fifo_depth AR 74 6 79 7 define XTEMAC DMA SIMPLI simple 2 channel DMA define XTEMAC DMA SGDMA 3 scatter gather DMA Gl N LLTEMAC platform data struct xlltemac platform data u8 tx csum u8 rx csum AQ 86 23 92 22 G u32 ll dev fifo ira u8 mac addr 6 LocalLink TYPE Enumerations define XPAR_LL FI define XPAR_LL_ PE SPT A SPI Controller FO 1 DMA 2 IP struct xspi platfo
4. return 0 8 42 412 27 EG rk with hotplug and coldplug E ALIAS platform XILINX SPI NAME c int exit xilinx spi of remove struct of device op return xilinx spi remove op 64 static struct of device id xilinx spi of match compatible xlnx xps spi 2 00 a compatible xlnx xps spi 2 00 b MODULE DEVICE TABLE of xilinx spi of match static struct of platform driver xilinx spi of driver owner THIS MODULE name xilinx xps spi match table xilinx spi of match probe xilinx_spi_of_probe remove exit p xilinx spi of remove static struct platform driver xilinx spi driver probe xilinx spi probe remov devexit p xilinx spi remove driver name xilinx xps spi s name XILINX SPI NAME static int owner THIS MODULE _ init xilinx spi init void return of register platform driver amp xilinx spi of driver return pl module in it xilinx spi inrt static voi d exit xi latform driver register amp xilinx spi driver inx spi exit void of unregister platform driver amp xilinx spi of driver plat module exi t xilinx spi form driver unregister amp xilinx spi driver exit MODULE AU
5. HOR MontaVista Software Inc lt source mvista com gt MODULE_DESCRIPTION Xilinx SPI driver MODULE_LICENSE GPL diff rupN petalinux svn orig software linux 2 6 x petalogix petalogix i include linux spi spi h petalinux svn software linux 2 6 x nclude linux spi spi h petalinux svn orig software linux 2 6 x petalogix include linux spi spi h 2007 03 30 04 57 33 000000000 0200 petalinux svn software linux 2 6 2009 03 02 10 43 22 000000000 0100 x petalogix include linux spi spi h 680 4 680 15 spi unregister device struct spi device device unregister amp spi gt dev device driver data 65 static inline void spi set drvdata struct spi device spi void data dev set drvdata amp spi gt dev data static inline void spi get drvdata struct spi device spi return dev get drvdata amp spi gt dev endif LINUX SPI H diff rupN petalinux svn orig software linux 2 6 x petalogix include linux xilinx devices h petalinux svn software linux 2 6 x petalogix include linux xilinx devices h petalinux svn orig software linux 2 6 x petalogix include linux xilinx devices h 2009 05 22 14 13 12 000000000 0700 petalinux svn software linux 2 6 x petalogix include linux xilinx devices h 2009 05 18 23 44 56 000000000 0700 ee 18 11 18 7 G
6. Return the final value read in from the SPI return value void writeSPI unsigned int device unsigned int value unsigned int numBytes Int us Force the maximum send width to be four bytes if numBytes gt 4 numBytes 4 Wait for the last transaction to finish while SPISSR deviceMask Lower the SS line for the specified device SPISSR amp device Special case for writing to the amplifiers if device SPI AMP Send the same byte to the Tx FIFO four times to ensure the amps get the new settings for i 0 i c 4 itt SPIDTR value Other cases else 78 Put the bytes of the data into the Tx FIFO MSB first for numBytes numBytes SPIDTR value gt gt numBytes 1 8 amp OxFF Wait for data in the Tx FIFO to be transmitted by polling the status bit for if SPISR 0x04 break Raise the SS lines when finished SPISSR 0 double getAdcVoltage double adc_val int gain double vin Based on the User s Guide on the ADC p 76 double divisor 8192 0 Set the divisor for calculating the ADC voltage based on the given gain setting switch gain case 0x1 divisor 1 0 break case 0x2 divisor 2 0 break case 0x3 divisor 5 0 break case 0x4 divisor 10 0 break case 0x5 diviso
7. a amp 0x07 1 Function prototypes void initSPI void void clearSPI void int readSPI unsigned int numBytes device unsigned int value void wr iteSPI unsigned int numBytes void readADC unsigned int adc doub fendif le getAdcVoltage double adc val writeSPI SPI DAC define SPI AMP 0x02 define SPI ADC 0x04 define DAC A 0x00 define DAC B 0x01 define DAC C 0x02 define DAC D 0x03 define DAC ALL 0x0F define sendDAC n val n 0x0F lt lt 16 val amp OxOFFF 4 4 define sendAmp a b writeSPI SPI AMP Jf KKKKK kok k k kk k KKK ARA RA k Inec KKKKKK KKK KKK KKK KKK ARA def def def def def Defined Macros defi initIntc M defi ine XPAR OPB INTC 0 BASEA defi XPAR OPB INTC 0 BAS ne ine XPAR OPB INTC 0 BAS ine XPAR OPB INTC 0 BAS ine XPAR OPB INTC 0 BAS define XPAR OPB INTC 0 BAS defi XPAR OPB INTC 0 BAS ine XPAR OPB INTC 0 BAS ne ne LNe ifndef INTC H define INTC H Register Settings ISR IPR Ci A IER BJ A IAR ti D SI E ti Dp CI E ti Dp IVR ti D MER ti D pendingIntc x volatile unsigned R 0x00 volatile unsigned R 0x04 volatile unsigned R 0x08 volatile unsigned R 0x0C volatile unsigned R 0x10 volatile uns
8. Amplifier gain settings all values are negative define xl 0x01 define x2 0x02 define x5 0x03 define x10 0x04 define x20 0x05 define x50 0x06 define x100 0x07 Regiser settings define FLASH ADC SEL DD volatile unsigned long define FLASH ADC SEL volatile unsigned long define AD CONV DD volatile unsigned long define AD CONV volatile unsigned long define SPICR volatile unsigned long CONFIG XILINX SPI 0 BASEADDR 0x60 define SPISR volatile unsigned long CONFIG XILINX SPI 0 BASEADDR 0x64 define SPIDTR volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x68 define SPIDRR volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x6C define SPISSR volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x70 define SPIGIE volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x1C define SPIISR volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x20 define SPIIER volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x28 define SPIRXF volatile unsigned CONFIG XILINX SPI 0 BASEADDR 0x78 Defined constants and macros fide fine SPI DAC 0x01 x2 X5 X10 0x42000000 0x04 0x42000000 0x00 0x41900000 0x04 0x41900000 0x00 long long long long long long long 81
9. Name Net Direction Class Sensitivity Range Frequency IP Type p EP Reset GPIO opb gplo 3 0 proc sys reset 1 0 opb spi 1 01 opb gpio 3 0 flash adc ctl sys clk s y 1 flash adc ctl 0 PINS io 7 0 FLASH DQ I flash adc ct 0 FLASH Da 1 Jo 7 0 FLASH DQ O ash adc ct 0 FLASH DO O li 7 0 FLASH DO T Mash ade ct O FLASH DaT li 7 0 SPI MISO I flash adc ctl 0 SPI MISO lo FLASH GEN 1 ash adc ct 0 FLASH GENT li FLASH CEN O ash adc ct 0 FLASH GEN O lo v flash adc ctl O SEL zl flash adc sel 6 Picd opb gplo 3 0 Block Diagrami System Assembly View1 Figure 9 The Flash ADC Control IP core configuration in Xilinx EDK Filters ide Bus Interface Ports C Addresses Ee Filters Applied Add External Port AE Reset GPIO fopb spi 0 SCK b 10 flash ade ct O SPI MISO I I fopb spi 0 MOSI x IO spi 0 SS io 0 C fopb spi O IP2INTG It vjo INTE LEVEL HI sys cik s w I CLK flash adc ct O ES flash adc sel I sf Block Diagram1 System Assembly View Figure 10 The SPI IP core configuration in Xilinx EDK 43 y Filters Applied 4 Add External Port a ein O Tren TN amp 9LEDs 8Bit opb gpio 3 0 DIP Switches 4Bit opb gpio 3 0 bin rotary decoder opb btn decoder 1 01 SP FLASH 16Mx8 opb emc 2 01 Filters ide Bus Interface Ports C Addresses Name y sys cik
10. x2 x5 x10 f strcmp argv 1 DAC A 0 amp amp argc 3 Send value to DAC A sendDAC DAC A atoi argv 2 se if stromp argv 1 DAC B 0 amp amp argc 3 Send value to DAC B sendDAC DAC_B atoi argv 2 se if stremp argv l DAC C 0 amp amp argc 3 Send value to DAC C sendDAC DAC_C atoi argv 2 se if stromp argv 1 DAC D 0 amp amp argc 3 Send value to DAC D sendDAC DAC_D atoi argv 2 se if strcmp argv 1 DAC ALL 0 amp amp argc 3 Send value to all DACs sendDAC DAC_ALL atoi argv 2 se if strcmp argv 1 ADC ALL 0 amp amp argc 4 ADC set gain settings with those entered f strcmp argv 2 x1 0 gain a xl lse if strcmp argv 2 x2 0 gain_a x2 lse if strcmp argv 2 x5 0 gain a x5 lse if strcmp argv 2 x10 0 gain a x10 lse if strcmp argv 2 x20 0 gain a x20 lse if strcmp argv 2 x50 0 gain a x50 lse if strcmp argv 2 x100 0 gain a xl00 gain a xl if strcmp argv 3 x1 0 gain b xl else if strcmp argv 3 x2 0 gain b x2 else if strcmp argv 3 x5 0 gain b x5 else if strcmp argv 3 x10 0 gain b xl0 else if strcmp argv 3 x20 0 gain b x20 else if strcmp argv 3 x50 0 gain b x50 else if strcmp argv 3 x100 0 gain b xl00 else gain
11. msg display_num displays the given number up to 7 digits on the LCD void display_num double n int i Write out negative sign if needed if n lt 0 writeLcd LCD CHAR l Convert each digit for up to 7 digits into a character to output unsigned char millions int n 1000000 48 unsigned char hun thousands int n 1000000 100000 48 unsigned char ten thousands int n 100000 10000 48 unsigned char thousands int n 10000 1000 48 unsigned char hundreds int n 1000 100 48 unsigned char tens int n 100 10 48 unsigned char ones int n 10 48 unsigned char tenths unsigned char hundredths Calculate the decimal remainder by subtracting the other places from the inputted number double decimal n millions 48 hun thousands 48 ten thousands 48 thousands 48 hundreds 48 ones 48 If a decical portion exists calculate the tenths and hundredths values if decimal gt 0 tenths int decimal 10 48 hundredths int decimal 100 10 48 Write out the millions digit if gt 0 if n gt 1000000 writeLcd LCD_CHAR millions Write out the hundred thousands digit if gt 0 if n gt 100000 writeLcd LCD_CHAR hun_thousands Write out the ten thousands digit if gt 0 if
12. n gt 10000 writeLcd LCD CHAR ten thousands TE if if Wr n wr ite out gt 10 ite ou gt 10 iteLcd ite ou gt 10 iteLcd L he thousands digit if gt 0 D CHAR thousands the hundreds digit if gt 0 LCD CHAR hundreds the tens digit gt 0 iteLcd LCD CHAR tens Write out the ones digit writeLcd LCD CHAR ones Check if there s a decimal and that it is made up of valid number characters if decimal gt 0 amp amp tenths gt 47 amp amp tenths lt 58 Write out the decimal to the hundredths place writeLcd wr wr iteLcd iteLcd CD CHAR LCD CHAR tenths LCD CHAR hundredths Oko k kok k kok k k kok k ARA ARA k led h KKKKKK KKK KKK KKK kck ck kok ck X k X ifndef LCD H define LCD H Register Settings define LCD volatile unsigned long 0x41800000 0x00 define LCD DD volatile unsigned long 0x41800000 0x04 define LCD_DATA 0x0F define CD E 0x10 define LCD RS 0x20 define LCD RW 0x40 define LCD BUSY 0x80 define LCD CMD 0x00 define LCD CHAR LCD RS Function Prototypes void initLcd void writeLcd int rs int value void printLcd char msg void display num double n endif 86 87 Appendix E Analysis of Senior Project Design Summary of Functional
13. 16Mx8 Mem A pin lt 23 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 22 gt LOC k12 Net fpga 0 FLASH 16Mx8 Mem A pin lt 22 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 21 gt LOC k13 Net fpga 0 FLASH 16Mx8 Mem A pin lt 21 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 20 gt LOC 115 Net fpga 0 FLASH 16Mx8 Mem A pin lt 20 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 19 gt LOC 116 Net fpga 0 FLASH 16Mx8 Mem A pin lt 19 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 18 gt LOC t18 Net fpga 0 FLASH 16Mx8 Mem A pin lt 18 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 17 gt LOC r18 Net fpga 0 FLASH 16Mx8 Mem A pin lt 17 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 16 gt LOC t17 Net fpga 0 FLASH 16Mx8 Mem A pin lt 16 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 15 gt LOC ul8 Net fpga 0 FLASH 16Mx8 Mem A pin lt 15 gt IOSTANDARD LVCMOS33 70 Net fpga 0 FLASH 16Mx8 Mem A pin lt 14 gt LOC t16 Net fpga 0 FLASH 16Mx8 Mem A pin lt 14 gt IOSTANDARD LVCMOS33
14. 2 INSTANCE XSPI PLATFORM DATA INITIALISER 2 endif static struct platform device xilinx spi devicel ifdef CONFIG XILINX SPI 0 INSTANCE XSPI PLATFORM DEVICE INITIALISER 0 endif ifdef CONFIG XILINX SPI 1 INSTANCE XSPI PLATFORM DEVICE INITIALISER 1 endif ifdef CONFIG XILINX SPI 2 INSTANCE XSPI PLATFORM DEVICE INITIALISER 2 endif static int _ init xspi platform init void int lt for i 0 i lt ARRAY SIZE xilinx spi device itt platform device register amp xilinx_spi_device i return 0 device initcall xspi platform init arch microblaze platform common xspi c 4 platform device initialisation for Xilinx SPI devices Based on arch microblaze platform common xspi c and xilspi c from someone posting to the uclinux mailing list Modified for the Xilinx xilinx spi driver include lt linux autoconf h gt include lt linux init h gt include lt linux resource h gt include lt linux xilinx devices h gt include lt linux serial 8250 h gt define XSPI PLATFORM DATA INITIALISER n N bus num n num chipselect CONFIG XILINX SPI_ n NUM SS BITS N speed hz CONFIG XILINX CPU CLOCK FREQ CONFIG XILINX SPI tHtttnttt OPB SCK RATIO defi
15. 59 SPI protocol drivers device link on bus obj CONFIG SPI SPIDEV spidev o add above this line SPI slave controller drivers upstream link diff rupN petalinux svn orig software linux 2 6 x petalogix drivers spi spidev c petalinux svn software linux 2 6 x petalogix drivers spi spidev c petalinux svn orig software linux 2 6 x petalogix drivers spi spidev c 2009 03 02 11 09 02 000000000 0100 petalinux svn software linux 2 6 x petalogix drivers spi spidev c 2009 03 02 11 20 39 000000000 0100 AR 37 6 37 7 G include lt asm uaccess h gt typedef unsigned int uintptr t This supports acccess to SPI devices using normal userspace I O calls AG 52 9 53 11 Qe particular SPI bus or device Eh define SPIDEV_MAJOR 153 assigned define N_SPI_MINORS 32 up to 256 define N SPI MINORS 32 up to 256 define N SPI MINORS 8 up to 256 static unsigned long minors N SPI MINORS BITS PER LONG static unsigned long minors N SPI MINORS BITS PER LONG static unsigned long minors 1 Bit masks for spi_device mode management Note that incorrect AR 561 7 564 7 static int spidev probe struct spi devic struct spidev_data spidev int status unsigned long minor Allocate driver data spidev kzalloc sizeof spidev GFP KERNEL if spidev GR 584 9 587 10 static int
16. CentOS is installed be sure to install the libcurl and libmotif packages These are required by the Xilinx ISE and EDK software Otherwise the programs may not open after installation is complete After logging in go to Add Remove Software search for libcurl and libmotif and install the development libraries Disabling Security Enabled Linux SELinux By default CentOS enables Security Enabled Linux SELinux which enables additional security features in Linux as well as a firewall However SELinux causes issues with both Xilinx s software and file transfers over serial USB and Ethernet To prevent these issues disable SELinux on your CentOS installation In CentOS go to the menu bar at the top and click System gt Administration gt Security Level and Firewall Enter the root password at the prompt In the Security Level Configuration Window click on the SELinux tab and change the SELinux setting to Disabled Apply the settings and restart your computer to allow the changes to take effect If you still have trouble with transfers especially over Ethernet try disabling the firewall as well This ensures that all protocols are sent through directly to your computer you may also wish to try turning on specific ports In CentOS go to the menu bar at the top and click System gt Administration gt Security Level and Firewall Enter the root password at the prompt In the Security Level Configuration Window click on the Firewall Op
17. D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 0 CF cf ct ctf ct cf cf ctf ctf ctf cf ctf ctf ctf cf cf ct cf cf cf ctf cf ctf cf cf cf cf T cf cf cf ctf cf cf cf ctf cf T KT cf cf T T cf cf ATA ctf cf K fpga RAM 32M DR Addr pin lt 3 gt LOC N se 4 fpga RAM 32M DDR Addr pin lt 3 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 4 gt LOC H2 fpga RAM 32M DDR Addr pin lt 4 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 5 gt LOC H1 fpga RAM 32M DDR Addr pin lt 5 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 6 gt LOC H3 fpga RAM 32M DDR Addr pin lt 6 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 7 gt LOC H4 fpga RAM 32M DDR Addr pin 7 IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 8 gt LOC F4 fpga RAM 32M DDR Addr pin lt 8 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 9 gt LOC P1 fpga RAM 32M DDR Addr pin lt 9 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 10 gt LOC R2 fpga RAM 32M DDR Addr pin lt 10 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR Addr pin lt 11 gt LOC R3 fpga RAM 32Mx16 DDR Addr pin lt ll gt IOSTANDARD SSTI2 I fpga RAM 32Mx16 DDR Addr pin lt 12 gt LOC T1 fpga RAM 32M DDR Addr pin lt 12 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR BankAddr pin lt 0 gt LOC K6 fpga RAM 32M DDR BankAddr pin l
18. DAC using C or C A sample user application for the SPI interface using the DAC and ADC has already been provided for use in Appendix D Please note that the copy of the program provided is for use as a user application for Petalinux To convert this project to your test development 37 EDK project the constants need to be changed as described in the section entitled Creating a Test Development EDK Project Once you have written the software recompile the hardware design and load the download bit file onto your Spartan board If you are using a test EDK project load the Spartan 3E Starter Kit through IMPACT to verify that the DAC is working using your code Once your are satisfied with the results copy your hardware configuration settings and UCF file changes to the Petalinux reference design and translate your software project into a user application as discussed above in the section entitled Creating a Test Development EDK Project If you are using Petalinux or are translating your changes over to Petalinux be sure to create and compile your code as a user application as discussed in the section entitled Creating User Applications for uClinux in Brian and Patrick s paper 2 Program your board with the bit file reload the U boot configuration and kernel image and then boot Petalinux to test your user application and communication with the DAC Implementing the Analog to Digital Converter ADC in uClinux The onboard ADC chip of the
19. Reguirements For this project I first developed the best environment to work with uClinux under Next I developed a SPI driver for the Spartan 3E Starter Kit in uClinux This driver will be used in future extensions of the SuPER project to convert the current control system from a laptop to a Spartan 3E FPGA to save power Finally I wrote a basic user application in uClinux to implement the DAC and ADC on the starter kit for testing Primary Constraints For the project the primary constraint was access to information Much of the work surrounding SPI driver development in uClinux is very bare and it can be hard to find a driver that works for your exact system I was fortunate enough to have some great people on uclinux microblaze mailing list to help me work on the SPIDEV driver throughout my project Another difficulty was finding a way around the shared pin between the flash data bus and the SPI core This caused bus contention whenever the two devices were turned on The solution was to create a custom IP core that forced Xilinx EDK to allow both devices to access the pin through a MUX This MUX was controlled by a manual select controlled by a GPIO Economics There was no cost for my project since the parts required for development had been purchased already for previous SuPER projects Everything was provided and returned at the end of the project 88 The development time for the project turned out to be guite long since much
20. SPI is located in the Xilinx git directory under linux 2 6 xInx Documentation spi spidev test c Another test script was provided by the uclinux microblaze mailing list and is available at http www itee ug edu au listarch microblaze uclinux archive 2009 03 msg00000 html Install these scripts into Petalinux as user applications The process for doing so can be found in the section entitled Creating User Applications for uClinux in Brian and Patrick s paper 2 48 XI Recommendations Now that the SPIDEV driver has been successfully tested and implemented using the instructions included in this paper there are several improvements and modifications that can be made to both improve the functionality of the driver as well as fix some issues that I faced while working on the driver Custom U Boot Auto Configuration Script As suggested in the section entitled Configure TFTP in Petalinux above the current implementation of Ethernet in the U Boot environment requires the user to set static IP addresses In addition these settings must be redone every time a new U Boot auto configuration script is run ub config img Some improvements include using DHCP instead of static IP addresses and customizing the configuration script so that your settings will not be overwritten Please see the section suggested for links to information regarding these modifications Upgrade Petalinux from SVN Build The latest build at the onset of my proj
21. Spartan 3E Starter Kit provides 2 ADCs connected to an onboard preamplifier each with a different analog range depending on the gain settings For more specifications regarding the setup and communication with the ADC please see the Users Guide 8 For testing you may wish to try building the ADC into your test development EDK project first as suggested in the section entitled Creating a Test Development EDK Project above That way you can program your board directly and test the ADC and your software without needing to recompile and load Petalinux onto the board 38 To connect the ADC add the lines to the UCF for the ADC as specified in the sample UCF file in Appendix C Please note that in the sample file the Preamp chip select CS is connected to bit 1 of the SPI Slave Select SS Vector Both the Preamp CS and SS Vector are active low signals so it is possible to using the SS vector to enable the Preamp device directly Controlling this signal also controls the ADC since the ADC is connected directly to the preamp internally The ADC is selected using the AD CONV signal which is an active high control signal Since it is active high and due to the nature of how the AD CONV signal must be triggered it cannot be connected to the SS vector directly Please see the User s Guide for more information regarding the nature and operation of the AD CONV signal 8 To control the ADC with the AD CONV signal we must create a GPIO that control
22. a SPI IP core Please see the section entitled SPI IP Core in Alex s paper 3 for a design description regarding adding the SPI core in the Xilinx EDK software However unlike Alex s paper this paper will leave the Ethernet IP core installed so that it may be used to speed up development in Petalinux by providing a faster transfer of the kernel image SPI User Application To develop the user application the C programming language is used The application to interface with the SPI devices will be created in a similar fashion to that described in Brian and Patrick s paper 2 This application will provide a user interface in Petalinux that will be used to access the various SPI devices that were implemented in the Xilinx EDK This includes both the DACs and ADCs that are necessary for the SuPER project to function properly The user application will provide the access to the SPI devices that the SuPER s software program will use once the code is ported from the laptop currently in the system to Petalinux on the Spartan 3E Starter Kit 15 V Setting up the Desktop Linux Environment This section describes how to setup the Linux environment on your computer In order to develop in uClinux a system needs to be set up to communicate with the Spartan 3E Starter Kit Board Previous papers have suggested using a virtual machine VM of Linux running on top of Windows While this allows the user to continue to use Windows for development it als
23. b xl For safety assert the CPHA bit in the SPI Control Register before sending values to the amps SPICR 0x08E Send settings to amp sendAmp gain a gain b Reset SPI Control Register SPICR 0x086 Read value in from the ADC readADC adc Output ADC A information to LCD writeLcd LCD_CMD 0x01 printLcd A display num getAdcVoltage twosComplement adc 0 14 0x2 printLcd v display num twosComplement adc 0 14 printLcd Output ADC B information to LCD writeLcd LCD CMD 0xC0 printLcd B display num getAdcVoltage twosComplement adc 1 14 0x3 printLcd v display num twosComplement adc 1 14 printLcd Run command based on arguments else printf nusage spi device options Mn printf nCurrently supported devices n n printf DAC A value NnDAC B lt value gt nDAC_C lt value gt nDAC_D lt value gt XnDAC ALL value NnADC ALL gain a gain b gt n n printf Possible DAC value entries n n0O 4095 n n x20 printf Possible ADC gain a gt gain b gt entries n nxl y X50 x100 Reset flash ADC control select to enable all values negative Ann flash and disable ADC FLASH_ADC_SEL 0x00 return 0 ERRAR RARA ke kk KKKKKKKKK KKK X kk kok ck A spi h ifndef SPI H define SPI H
24. code open the flash adc ctl ISE project edit the VHDL code and run Synthesize to verify the code compiles correctly The Flash ADC Control IP Core needs to be added to the reference design and test development EDK project if you are using it to run the ADC properly in Petalinux In EDK go to Hardware gt Create or Import Peripheral In the Create and Import peripheral wizard hit Next select Import Existing Peripheral and hit Next again Select To an XPS Project and hit Next Enter flash adc ctrl as the VHDL top entity name and hit Next Check HDL Source Files and hit Next Select Browse to your HDL source and dependent library files in next step and hit Next Click Add Files browse to the flash adc ctl vhd file hit Open and then hit Next Uncheck Select Bus Interface s and hit Next Uncheck Select and Configure Interrupt s and hit Next Hit Next and Finish to complete the import of the IP Core Next add and configure the custom IP core in the reference design or test design EDK project In the System Assembly View add the flash adc ctl IP Core from the IP Catalog by 42 double clicking on it under Project local pcores Configure the Flash ADC Control SPI and Flash IP Cores as shown below Be sure to pay careful attention to all connections and bus widths 7 0 and 0 7 are different so set it up as shown Filters Be Bus Interface Ports C Addresses Bv Filters Applied 2 Add External Port
25. file Please add other user constraints to this file based on customer design specifications HEH HEH HE HHH HEH EE EH EE HE EH EH tt tt tt EE EE EEE EEE HEE EE EE EE EE tt dt EE tt tt dt EEE E dt HEE dt Net sys_clk_pin LOC c9 Net sys clk pin IOSTANDARD LVCMOS33 System level constraints Net sys_clk_pin TNM_NET sys_clk_pin IMESPEC TS_sys_clk_pin PERIOD sys_clk_pin 20000 ps IO Devices constraints Module RS232 DTE constraints Net fpga 0 RS232 DTE RX pin LOC U8 DTE connector J10 AVNET Net fpga 0 RS232 DTE RX pin LOC R7 DCE connector J9 Net fpga 0 RS232 DTE RX pin IOSTANDARD LVCMOS33 Net fpga 0 RS232 DTE TX pin LOC M13 DTE connector J10 AVNET Net fpga 0 RS232 DTE TX pin LOC M14 DCE connector J9 Net fpga 0 RS232 DTE TX pin IOSTANDARD LVCMOS33 Module LEDs 8Bit constraints Net fpga 0 LEDs 8Bit GPIO d out pin lt 0 gt LOC F9 Net fpga 0 LEDs 8Bit GPIO d out pin 0 IOSTANDARD LVCMOS33 Net fpga 0 LEDs 8Bit GPIO d out pin lt l gt LOC E9 Net fpga O LEDs 8Bit GPIO d out pin lt l gt IOSTANDARD LVCMOS33 Net fpga 0 LEDs 8Bit GPIO d out pin lt 2 gt LOC D11 Net fpga 0 LEDs 8Bit GPIO d out pin lt 2 gt IOSTANDARD LVCMOS33 Net fpga O LEDs 8Bit GPIO d out pin lt 3 gt LOC C11 Net fpga 0 LEDs 8Bit GPIO d out pin lt 3 gt IOSTANDARD LVCMOS33 Net fpga O LEDs 8Bit GPIO d out pin lt 4 gt LOC F11 Net fpga 0 LEDs 8Bit GPIO d out pin lt 4 gt IOSTANDARD LVCMOS33 Net fpga 0 LEDs 8Bit GPIO d out pin lt 5
26. finish while SPISSR deviceMask Set the Tx FIFO Reset and Rx FIFO Reset Bits SPICR 0x60 Clear the Tx FIFO Reset and Rx FIFO Reset Bits SPICR amp 0x60 void readADC unsigned int adc unsigned int value 0x00 Change the SPI control register clock phase CPHA bit to 1 to change the phase for the ADC SPICR 0x08E Manually trigger the AD CONV signal to begin reading in data to the ADC AD CONV DD 0x0 AD CONV 0x0 Wait for the last transaction to finish Allows data to be converted while SPISSR deviceMask Manually trigger the AD CONV signal again to begin output of converted data AD CONV 0x1 AD CONV 0x0 Read in values from the ADC seperate the two ADC A and B values and store them into an array value readSPI 4 TT adc 0 value gt gt 16 amp 0x00003FFF adc 1 value amp 0x00003FFF Reset the clock phase for the SPI bus in case another device is being used such as the DAC SPICR 0x086 int readSPI unsigned int numBytes int value 0 Force the maximum send width to be four bytes if numBytes gt 4 numBytes 4 Wait for the last transaction to finish while SPISSR deviceMask Read in each byte from the Rx FIFO for numBytes numBytes Append the current byte to the LSB of the value value value lt lt 8 SPIDRR amp OxOFF
27. gt LOC E11 Net fpga 0 LEDs 8Bit GPIO d out pin lt 5 gt IOSTANDARD LVCMOS33 Net fpga 0 LEDs 8Bit GPIO d out pin 6 LOC E12 Net fpga 0 LEDs 8Bit GPIO d out pin 6 IOSTANDARD LVCMOS33 Net fpga 0 LEDs 8Bit GPIO d out pin lt 7 gt LOC F12 Net fpga 0 LEDs 8Bit GPIO d out pin lt 7 gt IOSTANDARD LVCMOS33 Module DIP Switches 4Bit constraints Net fpga 0 DIP Switches 4Bit GPIO in pin lt 0 gt LOC N17 PULLDOWN Net fpga 0 DIP Switches 4Bit GPIO in pin lt 0 gt IOSTANDARD LVCMOS33 Net fpga O DIP Switches 4Bit GPIO in pin lt l gt LOC H18 PULLDOWN Net fpga 0 DIP Switches 4Bit GPIO in pin lt l gt IOSTANDARD LVCMOS33 Net fpga 0 DIP Switches 4Bit GPIO in pin lt 2 gt LOC L14 PULLDOWN Net fpga 0 DIP Switches 4Bit GPIO in pin 2 IOSTANDARD LVCMOS33 Net fpga 0 DIP Switches 4Bit GPIO in pin lt 3 gt LOC L13 PULLDOWN Net fpga 0 DIP Switches 4Bit GPIO in pin lt 3 gt IOSTANDARD LVCMOS33 Directional buttons and rotary encoder Net fpga 0 Buttons west pin LOC D18 PULLDOWN Net fpga 0 Buttons west pin IOSTANDARD LVCMOS33 Net fpga 0 Buttons east pin LOC H13 PULLDOWN Net fpga 0 Buttons east pin IOSTANDARD LVCMOS33 Net fpga 0 Buttons north pin LOC V4 PULLDOWN Net fpga 0 Buttons north pin IOSTANDARD LVCMOS33 Net fpga 0 Buttons south pin LOC K17 PULLDOWN Net fpga 0 Buttons south pin IOSTANDARD LVCMOS33 Ne
28. has been downloaded copy the following files into your Petalinux directory root localhost cp linux 2 6 x1nx drivers spi xilinx_spi c petalinux svn software linux 2 6 x petalogix drivers spi xilinx spi c root localhost cp linux 2 6 x1nx drivers spi spidev c petalinux svn software linux 2 6 x petalogix drivers spi spidev c root localhost cp linux 2 6 xlnx include linux spi spidev h petalinux svn software linux 2 6 x petalogix include linux spi spidev h After you have copied the correct files from the Xilinx git directory the SPIDEV patch needs to be applied to Petalinux Please see Appendix B for the patch file Take note of the areas in bold within the patch These are to emphasize specific sections of the patch that need to be configured First be sure to check the CONFIG XILINX SPI entries in the script against the constants in the generated petalinux svn software linux 2 6 x petalogix include linux autoconf h file Second update the SPI board info initdata entries for the setup c file with the SPI settings for your SPI bus such as speed and bus number Comment out any of the dummy structures in this section that you are not using Finally I d recommend adding some print statements to the petalinux svn software linux 2 6 x petalogix drivers spi spidev c file for debugging purposes These will show up during the Petalinux boot process and
29. kernstart S kernsize U Boot gt cp b clobstart S kernstart filesize All of the files have now been successfully loaded into the flash on the Spartan 3E Starter Kit Reset your board be downloading the download bit file again Petalinux should now successfully boot to the logon prompt as it did previously 28 Whenever you make kernel changes or software changes such as adding user applications the image ub file is the only file that needs to be uploaded again For this you can use TFTP dramatically cutting down the development time for software in Petalinux However if you need to modify the hardware then you must go through the entire process outlined in Brian and Patrick s paper 2 again and upload all the files again via TFTP Remember the IP environment variables will be reset once you run a new auto configuration script 29 VIII Implementing the SPIDEV Driver in uClinux The Petalinux kernel already includes SPI drivers that can be configured These include a bit banging driver and SPI character driver These drivers are quite old and do not work correctly with the Spartan 3E Starter Kit Instead another driver is needed to access the SPI bus configured on the FPGA The solution is a SPI driver known as SPIDEV This driver implements each SPI bus interface as a block device rather than a character device assigning each SPI interface a name dev spi x where x denotes the bus For example if you implement
30. make it easy to tell if your SPI device is setup correctly The kernel uses the printk command instead of a printf but the formatting is exactly the same I d add the printk s to the spidev probe function specifically since this is the function that initializes the device Once you have modified the patch install it patch diff by copying it into your base petalinux directory and running the following command root localhost petalinux svn patch pl lt patch diff 32 All hunks that are patched should display succeeded messages If you see a FAILED message the failed portion of the patch will be saved into a file with the same name as the file to be patched with a rej file extension appended If this occurs apply the changes in the rej file manually in the Petalinux kernel Once the patch has been applied set the SPI settings in the Petalinux kernel Open a console window and change into the petalinux svn software petalinux dist directory and type make menuconfig to open up the kernel configuration In the uClinux Configuration window select Kernel Library Defaults Selection and check Customize Kernel Settings Hit Exit twice and then Yes to save the configuration The Linux Kernel Configuration window will load Select Device Drivers and then SPI Support Be sure to check SPI Support Xilinx SPI Controller and User mode SPI device driver support Everything else should be unchecked If one or mor
31. max speed hz 1000000 bus num 0 chip select 2 dummy gt spi 3 modalias spidev max speed hz 1000000 bus num 0 chip select 3 second bus on expansion board only 4 devices dummy gt spi 4 modalias spidev max speed hz 1000000 bus num 1 chip select 0 dummy gt spi 5 modalias spidev max speed hz 1000000 bus num 1 chip select 1 dummy gt spi 6 modalias spidev max speed hz 1000000 bus num 1 chip select 2 dummy gt spi 7 modalias spidev max speed hz 1000000 bus num 1 chip select 3 57 58 static int board init spi void spi register board info spi board info ARRAY SIZE spi board info ER return 0 arch initcall board init spi diff rupN petalinux svn orig software linux 2 6 x petalogix drivers spi Kconfig petalinux svn software linux 2 6 x petalogix drivers spi Kconfig petalinux svn orig software linux 2 6 x petalogix drivers spi Kconfig 2007 03 30 07 49 34 000000000 0200 petalinux svn software linux 2 6 x petalogix drivers spi Kconfig 2009 03 02 10 37 45 000000000 0100 ee 103 6 103 14 AR config SPI S3C24XX GPIO GPIO lines to provide the SPI bus This can be used where the inbuilt hardware cannot provide the transfer mode or where the board is using non hardware connected pins
32. of the time was spent researching possible solutions to problems that occurred Overall the project took about 10 hours a week to finish on time This was the approximate estimate given at the beginning of the quarter Environmental and Sustainability The SuPER project will have an enormous impact on the environment in the third world The project was developed as a way to provide renewable energy to those who currently lack the infrastructure and access to energy Each station will provide a supply of solar energy to power a small village that would otherwise not have power The part I have worked on has helped increase the amount of energy available to the people who will use the system By replacing the laptop with the Spartan 3E Starter Kit I developed my driver for the consumption of the control system will drop to less than 3W allowing the rest of the energy previously taken by the laptop to be distributed among the micro grid within the village Social and Political The SuPER project will greatly affect the people in the third world It will give them access to a resource they did not have before providing energy to villages all over the world Development During this project I learned a great deal of new knowledge about the Linux kernel Working with the uClinux kernel and patching the SPIDEV driver into my build taught me a great deal about how the kernel works and how drivers are written in Linux I also expanded my knowledg
33. spidev probe struct spi devic spidev gt devt MKDEV SPIDEV MAJOR minor dev device create spidev class amp spi gt dev spidev gt devt spidev spidev d d spidev spidev d d spi gt master gt bus num spi gt chip select status IS ERR dev PTR ERR dev 0 dev dbg amp spi gt dev spidev d d created n spi gt master gt bus num spi gt chip select else dev dbg amp spi gt dev no minor number available n status ENODEV 60 668 6 672 7 static int __init spidev init void class destroy spidev class unregister chrdev SPIDEV MAJOR spidev spi driver name return status module init spidev init diff rupN petalinux svn orig software linux 2 6 x petalogix drivers spi xilinx spi c petalinux svn software linux 2 6 x petalogix drivers spi xilinx spi c petalinux svn orig software linux 2 6 x petalogix drivers spi xilinx spi c 2009 05 22 14 13 52 000000000 0700 petalinux svn software linux 2 6 x petalogix drivers spi xilinx spi c 2009 03 04 22 18 58 000000000 0800 15 15 15 12 finclude lt linux init h gt include lt linux interrupt h gt include lt linux platform device h gt A include inux of platform h gt include inux of device h gt include linux of spi h gt A include lt linux spi spi h gt include lt l
34. to display the input of the ADC on the LCD screen This is not reguired but it is a nice feature for testing The code and UCF file provided in Appendices C and D include the LCD module This module is a standard GPIO with a 7 bit IO bus Please see Figure 14 below for pin settings and memory mappings 44 The Flash ADC Control IP Core does not need to be added to a bus or have address space allocated to it Add the appropriate external port connections to the UCF file as shown in Appendix C In addition to the Flash CEN signal an external CEN must be added that is controlled manually This signal is ORed with the Flash CEN overriding it in the case we want to disable the flash flash CEN set to 1 We must create a GPIO that controls this pin and then set it manually in the software code In the EDK open System Assembly View and switch to the Ports Filter Add a new General Purpose IO GPIO IP Core from the IP Catalog on the left hand side by double clicking the core Rename it to flash adc sel to match the UCF file Right click on the new IP core and hit Configure IP In the Properties window change GPIO Data Bus Width to 1 and hit OK to close the Properties window In the Ports view connect the IP core as shown in the following figure E Filters dr Bus Interface Ports C Addresses Yr Filters Applied 2 Add External Port name recon css senos range rennes Tes CE devcik90_inv util vector l
35. use another tool in Linux to program the board There are a variety of open source tools available to program Spartan based boards This paper focuses on using the libusb driver in conjunction with Xilinx s iMPACT program to download bit files onto the starter kit with a regular USB cable More information about the USB driver installation can also be found on the SuPER wiki 4 as well as the libusb project website at http www rmdir de michael xilinx 18 To install the USB driver obtain a copy of usb driver head tar gz from http www rmdir de michael xilinx Extract the files in the archive and follow the instructions in the included README to install the driver Once the driver is compiled and installed copy the usb driver folder to the opt pkg xilinx directory Before running IMPACT initialize the driver with the following command root localhost export LD PRELOAD opt pkg xilinx usb driver libusb driver so root localhost impact port auto To avoid having to run this command everytime you run iMPACT copy the export command above into a file and save it as a bash script under etc profile d bin bash export LD PRELOAD opt pkg xilinx usb driver libusb driver so Be sure to save the file with a sh extension Once IMPACT is started you can program the Spartan 3E Starter Kit as follows In the main window go to File gt Initialize Chain An open dialog box will pop up for the first device on the Spart
36. 41800000 0x418001FF 512 ja moop z ad conv SOPB 6x41980000 0x419001FF 5172 vi moo z flash adc sel SOPB 8x42000000 6x420001FF 512 0 mb opb E lopb intc O SOPB 0x41200000 6x4120ffff esk va moop y debug module SOPB 0x41400000 oxa140ftft eak JO mb opb E lopb spi 0 SOPB 6x41000000 oxaieo3rFF ek O mb opb z lopb_timer_1 SOPB 6x41c08000 ex4iceffft eak Ja mb opb E RS232 DTE SOPB 0x49600000 px4060ffff leak vid mb opb x DDR SDRAM 32Mx16 SOPB MCHO MCH1 MCH2 MCH3 MEMO 0x24000000 0x27ffffff sm jE NE a Q nse HH n Eg x Block Diagram1 E System Assembly View Figure 14 The memory mappings for all the devices needed to implement the DAC and ADC in Xilinx EDK Next write your user application to interface to the ADC Td recommend that you first write it as a software project in your EDK test development project and then translate it to a Petalinux user application To do so open your software project under the Applications tab in EDK If you have not created a test project or software project yet please see the section entitled Creating a Test Development EDK Project above Write software to interface with the ADC using C or C A sample user application for the SPI interface using the DAC and ADC has already been provided for use in Appendix D Please note that the copy of the program provided is for use as a user application for Petalinux This code also includes the LCD code to display values of the ADC to th
37. Also there are no issues with bus contention since the SS will control when the DAC has access to the SPI bus P Filters r Bus Interface Ports C Addresses Yr Connection Filters a Add External Port Name net proton Sensitivity i fpga O Ethemet MAG PHY col pin ipga O Ethernet MAG PHY col l Jl fpga 0 Ethernet MAC PHY rx er pin fipga O Ethernet MAG PHY rx er j fpga 0 Ethernet MAC PHY tx en pin ipaa O Ethernet MAG PHY tx en 7110 fpga 0 Ethemet MAC PHY tx data pin ipga O Ethernet MAC PHY tx da lo 4 4 4 3 0 Na a KEENE fpga 0 DDR CLK FB dor feedback s v JI sys clk pin acm cik s v J CLK fpga 0 spi SCK pin opo spi 0 SCK J 10 fpga 0 spi MOSI pin opo spi 0 MOSI IO SS pin opb sp 0 SS c Elo El El 4 14 44 I 0 1 2 microblaze O af 4 Block Diagram1 th System Assembly View1 B system ucf Figure 4 The DAC CLR external port configuration in Xilinx EDK Next write your user application to interface to the DAC Pd recommend that you first write it as a software project in your EDK test development project and then translate it to a Petalinux user application To do so open your software project under the Applications tab in EDK If you have not created a test project or software project yet please see the section entitled Creating a Test Development EDK Project above Write software to interface with the
38. Applications for uClinux in Brian and Patrick s paper for information regarding this topic 2 Be aware that you will need to convert the 21 constants and some of the header files in your software code Remove any of the following header references include lt xparameters h gt include lt xio h gt He Add the following include to your files instead include lt linux autoconf h gt Rename all the Xilinx you used in your code with those in Petalinux Most of these may be found under petalinux svn software linux 2 6 x petalogix include linux autoconf h The following examples are based on the code in Appendix D For example the constant XPAR OPB SPI 0 BASEADDR converts to CONFIG XILINX SPI 0 BASEADDR in Petalinux using the constant from autoconf h In some cases there will not be an entry for constant in your code in autoconf h For these use the hard coded hardware address for the IP core These values can be found in the EDK under the System Assembly View when the Addresses Filter applied For example the constant XPAR FLASH ADC SEL BASEADDR converts to 0x42000000 in Petalinux Once these changes are applied you should be able to compile your project in Petalinux as a user application 22 VI Setting up uClinux on a Spartan 3E Board This topic is discussed in depth in Brian and Patrick s paper 2 Please see the section in their paper entitled Installing uClinux on a Spartan 3
39. C F2 fpga RAM 32Mx16 DDR DO pin lt 4 gt IOSTANDARD SSTL2 I 2 2 292 22 59292255 22352 52 22222352 9223 LE LE 2323222 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e Ct CR Gh et CCE ct 6b GFOGE e Cb cb Et GR cb ck cock cb GER cb CE GE eb EG fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga ODO DO On OCO GS CCO SC OO DOS 010 0 0 0 0 DS OO CO 0 00 fpga sn On OS ee OO On OO Oe On Oe CO OU CO OO as V VE OO OO OO D D UJ UJ UJ D UJ UJ UJ D D UJ UJ D D UJ UJ UJ D UJ UJ UJ UJ D D UJ UJ UJ UJ UJ DDD Module DLA A Z Z E EZ E EZ Z Z E EZ A ZE 22 22 D D D D 0 D D D D D D D D D D D D 00 VAC E CR qu ER RER p AE ER C RER GEN GT CL ARE AA AT fpga O0 fpga O fpga 0 fpga 0 fpga 0 fpga_0_ fpga_0_ fpga 0 fpga 0 fpga 0 fpga 0 fpga_0_ fpga 0 fpga 0 fpga 0 fpga 0 fpga 0 fpga_0_ fpga 0 fpga 0 Ej Ed Ed Ed Dd Dd Dd EH Dd Dd Dd
40. E Starter Board This will give you a Spartan 3E Starter Kit with a booting base Petalinux system A Note on Kermit Whenever you use Kermit the following command must be run in a console window each time you boot your computer user localhost sudo chmod a rw dev ttyS0 This ensures that all users are given read and write privileges to the serial port This allows Kermit to work properly There may be an easier way to implement this using a script I ran it once every time I started my system Also note that you may be using a different serial port from ttySO so change the command above accordingly depending on your serial port 23 VII Setting up Ethernet File Transfer By default the Petalinux EDK reference design for the Spartan 3E Start Kit includes an Ethernet Lite IP core that is implemented in the hardware Xilinx doesn t include the core as part of its suite of IP cores However the license file for the Ethernet Lite core can be downloaded for free from their website Once this core is licensed you can compile the hardware reference design successfully with the Ethernet hardware block included If you wish to develop without the Ethernet core please see the section entitled Removing Ethernet IP Core If license is expired in Alexis paper 3 With the Ethernet Lite core implemented in Petalinux s reference design you can configure the uClinux kernel to include Ethernet drivers This will allow you to communicate ove
41. EH td Dd Dd EH Dd Ed Dd Dd ct ct E ct ct ct ct ct ct ct ct ct ct ct ct ct ct ct ct ctf ct th ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne SDRAM 32Mx16 DDR DO pin lt 4 gt PULLUP SDRAM 32Mx16 DDR DO pin lt 5 gt LOC F1 SDRAM 32Mx16 DDR DO pin lt 5 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 5 gt PULLUP SDRAM 32Mx16 DDR DO pin lt 6 gt LOC E1 SDRAM 32Mx16 DDR DO pin lt 6 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 6 gt PULLUP SDRAM 32Mx16 DDR DO pin lt 7 gt LOC E2 SDRAM 32Mx16 DDR DO pin lt 7 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 7 gt PULLUP SDRAM 32Mx16 DDR DO pin lt 8 gt LOC M6 SDRAM 32Mx16 DDR DO pin lt 8 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 8 gt PULLUP SDRAM 32Mx16 DDR DO pin lt 9 gt LOC M5 SDRAM 32Mx16 DDR DO pin lt 9 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 9 gt PULLUP SDRAM 32Mx16 DDR DO pin lt 10 gt LOC M4 SDRAM 32Mx16 DDR DO pin lt 10 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 10 gt PULLUP SDRAM 32Mx16 DDR DO pin lt ll gt LOC M3 SDRAM 32Mx16 DDR DO pin lt ll gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt ll gt PULLUP SDRAM 32Mx16 DDR DO pin lt l2 gt LOC L4 SDRAM 32Mx16 DDR DO pin lt 12 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 12 g
42. Hold time i Wait 750ns Send command to return the LCD cursor to the home position sendLcd LCD_CMD Kf 0x02 void writeLcd int rs int value 84 int i d if rs rs LCD_RS Wait for the LCD to not be busy while readLcdStatus amp LCD BUSY Send upper nibble sendLcd rs value gt gt 4 amp LCD DATA Send lower nibble sendLcd rs value amp LCD DATA for i 0 i lt 10 i LCD 0 Wait 1000ns void initLcd int 1i Set LCD data lines to outputs LCD_DD 0 for i 0 i lt 20 5500 i LCD 0 20ms delay Set to 8 bit operation sendLcd LCD CMD 0x03 for i 0 i lt 500 i LCD 0 9lus delay Set to 8 bit operation sendLcd LCD CMD 0x03 for i 0 i lt 500 i LCD 0 9lus delay Set to 8 bit operation sendLcd LCD CMD 0x03 for i 0 i lt 500 i LCD 0 9lus delay Set to 4 bit operation sendLcd LCD CMD 0x02 for i 0 i lt 500 i LCD 0 9lus delay Function Set writeLcd LCD CMD 0x28 Display On writeLcd LCD CMD 0x0C Clear Screen writeLcd LCD CMD 0x01 Set Entry Mode writeLcd LCD CMD 0x06 void printLcd char msg 85 Write out the message a character at a time until msg points to NULL while msg writeLcd LCD CHAR
43. IMPLEMENTING A SPI DRIVER IN UCLINUX FOR CAL POLY SUPER PROJECT By Matt Staniszewski Senior Project COMPUTER ENGINEERING DEPARTMENT California Polytechnic State University San Luis Obispo 2009 Table of Contents EE EEE nta dd raciales 6 AcEnowIedomentsonu tao emu Eb ou ei pde meta asi tutt 7 E A dr tn 8 Naming CONVENTIONS sn 9 II BIK SONNE ME CPC Dm 10 HL REQUIEM oe e bed e rete cident oba b ir nce c OV AO uet m odb 12 IV Blu e e 14 or EDR SO Wanda Tal 14 SPIL USE Application dtu ne neta age 14 V Setting up the Desktop Linux Environment sus 15 Installing Linux on your Comp aaret 15 Disabling Security Enabled Linux SELInux ss 16 Bastallime Xilinx ISE and EDK sound id S 17 install the USB DIE K 17 Downloading Petalinix uie pee vaere 19 Creating a Test Development EDK Project eiie aret edente tetti nente ie tacna 19 Converting from a Test EDK Project to Petalinux si n 20 VI X Setting up uClinux on a Spartan 3E Board eene 22 A Note on Kermi PPP ee ee Pe p st tt Ores Mn isses HS 22 VII Setting up Ethernet File Transfer it 23 Installing the Ethernet Core LICeDSeu eed his ai 23 Configuring TETP in CentOS ti Mes ind eu dana tek 24 Configuring TFTP mn PetoliBUX acc Ads 26 VIII Implementing the SPIDEV Driver in uClinux ss 29 Adding the SPI IP Core to Xilinx EDK ona 29 Installme SPIDEY mn Petalin k A AAA r s add 30 IX Implementing SPI Devices in uC lin
44. LVCMOS33 LCD Data 2 NE led pin lt 3 gt LOC M15 IOSTANDARD LVCMOS33 LCD Data 3 NE led pin lt 2 gt LOC M18 IOSTANDARD LVCMOS33 LCD E NE led pin lt 1 gt LOC L18 IOSTANDARD LVCMOS33 LCD RS NE led pin lt 0 gt LOC L17 IOSTANDARD LVCMOS33 LCD RW SPI Devices Added by Matt Staniszewski Spring 2009 SPI Main Connections NET fpga 0 spi MISO pin LOC N10 IOSTANDARD LVCMOS33 4 ISO NET fpga 0 spi MOSI pin LOC T4 IOSTANDARD LVCMOS33 OSI NET fpga 0 spi SCK pin LOC U16 IOSTANDARD LVCMOS33 SCK SPI Device Control Connections NE dac clr pin LOC Pg IOSTANDARD LVCMOS33 DAC CLR NET amp shdn pin LOC P7 IOSTANDARD LVCMOS33 f Preamp shutdown pin NET flash CEN pin lt 0 gt LOC D16 IOSTANDARD LVCMOS33 Flash Chip Enable SPI DAC Connections NET fpga 0 spi SS pin lt 0 gt LOC N8 IOSTANDARD LVCMOS33 DAC CS SPI Preamp Connections NET fpga 0 spi SS pin lt 1 gt LOC N7 IOSTANDARD LVCMOS33 4 Preamp CS NET fpga 0 amp dout pin lt 0 gt LOC E18 IOSTANDARD LVCMOS33 Preamp data out SPI ADC Connections NE ad conv pin lt 0 gt LOC P11 IOSTANDARD LVCMOS33 ADC CS Flash ADC Shared Pin NET fpga 0 flash adc ctl pin lt 7 gt LOC N10 IOSTANDARD LVCMOS33 Appendix D SPI User Application Jf KKKKK KKK KKK KKK KKK AA ARA Spice KKKKK KKK Ck kck ck kck ARA RA e e x include
45. Net fpga 0 FLASH 16Mx8 Mem A pin lt 13 gt LOC ul5 Net fpga 0 FLASH 16Mx8 Mem A pin lt 13 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 12 gt LOC v15 Net fpga 0 FLASH 16Mx8 Mem A pin lt 12 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 11 gt LOC t12 Net fpga 0 FLASH 16Mx8 Mem A pin lt 11 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 10 gt LOC v13 Net fpga 0 FLASH 16Mx8 Mem A pin lt 10 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 9 gt LOC v12 Net fpga 0 FLASH 16Mx8 Mem A pin lt 9 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 8 gt LOC n11 Net fpga 0 FLASH 16Mx8 Mem A pin lt 8 gt IOSTANDARD LVCMOS33 Data DO Pins for Flash go through ADC Flash Control Net fpga 0 flash adc ctl pin lt 6 gt LOC p10 Net fpga 0 flash adc ctl pin lt 6 gt IOSTANDARD LVCMOS33 Net fpga 0 flash adc ctl pin lt 5 gt LOC r10 Net fpga 0 flash adc ctl pin lt 5 gt IOSTANDARD LVCMOS33 Net fpga 0 flash adc ctl pin lt 4 gt LOC v9 Net fpga 0 flash adc ctl pin lt 4 gt IOSTANDARD LVCMOS33 Net fpga 0 flash adc ctl pin lt 3 gt LOC u9 Net fpga 0 flash adc ctl pin lt 3 gt IOSTANDARD LVCMOS33 Net fpga 0 flash adc ctl pin lt 2 gt LOC r Net fpga 0 flash adc ctl pin lt 2 gt IOSTANDARD LVCMOS33 Net fpga O flash adc ctl pin lt l gt LOC m9 Net fpga 0 flash adc ctl pin lt 1 gt IOSTANDARD LVCMOS33 Net fpga 0 flash adc ctl pin lt 0 gt LOC n9 Net
46. SI tx en pin IOSTANDARD LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 P I EDBACK CLOCK PHASI P LOCK EVICE CLOCK EVICE CLOCK PHAS EVICE CLOCK EVICE CLOCK PHAS clock cycle 0 uncertainty 0 T DDR FEEDBACK CLOCK OFFSET IN 5 75 ns VALID 3 5 ns B clock cycle 1 5ns valid EDBACK CLOCK PHASI 90 90 E EFOR 270 clock cycle 0 uncertainty 0 DDR DO I DDR DQ O DDR DQ T DDR DOS I DDR DQS O DDR DOS T FF ZZ Z Z un Bd pd bd Dl bd E Z E LAY NON LAY NON LAY NON LAY NON LAY NON LAY NON Avnet added end lcd pin lt 6 gt LOC clock cycle se e se se EE ERE ET Ez s se R15 IOSTANDARD valid clock cycle DDR Tac LVCMOS33 fpga 0 DDR CLK FB TIM clock cycle fpga 0 DDR CLK FB TIM 0000 ps TO OPB CLOCK TO OPB CLOCK O OPB CLOCK LCD Data 0 74 NE led pin lt 5 gt LOC R16 IOSTANDARD LVCMOS33 LCD Data 1 NE led pin lt 4 gt LOC P17 IOSTANDARD
47. SS lo dac_cir_pin net vcc rio gt ad A LE conv GPIO IO zie E micrblaze 0 amp sP mb opb Block Diagram1 System Assembly View1 B system ucf Figure 7 The AMP SHDN external port configuration in Xilinx EDK EI EE Fin 40 3 0 0 1 0 0 Unlike the DAC the ADC has special bus contention issues The ADC uses the SPI MISO signal which shares a pin with bit 0 of the flash s data DO bus The flash is used to by Petalinux to hold the U Boot and kernel information To avoid this issue the correct devices must be selected as described in the User s Manual 8 However in the EDK there is no way to select between the flash and ADC for this single pin To solve this issue a new IP core was developed The Flash ADC Control IP Core sends the information on the shared pin to the correct location based on both the flash chip enable CEN and a manual CEN controlled by a GPIO as shown in the diagram in Figure 8 below 41 FLASH ADC CTL FLASH ADC SEL I l FLASH_16Mx8 l I DQ 7 0 je 0 i I MUX la x CEN DO U D DQ 7 0 1 I OPB SPI 0 i EE D 7 1 I 7 I MISO e I I I I I I I D FLASH CEN SEL CLK gt N Figure 8 A diagram of the Flash ADC Control IP Core implementation The IP core was developed in VHDL using the Xilinx ISE If changes need to be made to this
48. a person could communicate with and use the SPI devices on the Spartan 3E Starter Kit using the console in Petalinux Future implementations might also include a wider range of devices besides the DAC and ADC They may also expand the number of command line arguments and make it easier for the user to understand Ultimately the code from the SuPER project will need to be ported from the laptop to the Spartan 3E so a friendly user command for accessing the SPI devices would be very helpful and make updating the code much easier 50 XII Conclusion This project built on the previous successes of Brian Patrick and Alex who worked on the initial development of Petalinux for the SuPER project The reason we wish to develop a working system in Petalinux is to allow the SuPER team to port the program that collects data from the SuPER and sends out control signals on to the Spartan 3E Starter Kit board This would eliminate the laptop and other microcontrollers that are currently used on the SuPER and would cut the power consumption down greatly At the start of this project I focused on finding the best development environment for working with uClinux which turned out to be a standalone CentOS installation Next I implemented and tested the Ethernet interface on the Spartan 3E and used it to update the Petalinux kernel on the board much faster than the old serial interface Next I worked on the development of the SPIDEV driver in uClinux and implem
49. an 3E chain This is the chip we wish to program Select the bit file by browsing to the appropriate directory the file is under selecting the bit file and hitting Open Next hit Bypass twice to skip programming the other two devices on the board Once you are ready to program right click on the xc3s500e device in the main window and hit Program Hit OK in the Programming Properties window to program the board If successful a Programming Succeeded message will appear Otherwise you will get a Programming Failed message If iMPACT says the connection has failed be sure to check that your cable is plugged in correctly and the board is powered on To verify the cable is plugged in open a console window type sudo sbin Isusb and hit enter If the cable is connected and the Spartan 3E is working properly an entry for the Xilinx device should appear such as below 19 user localhost sudo sbin lsusb Bus 003 Device 001 ID 0000 0000 Bus 004 Device 001 ID 0000 0000 Bus 002 Device 001 ID 0000 0000 Bus 005 Device 001 ID 0000 0000 Bus 001 Device 017 ID 03fd 0008 Xilinx Inc Bus 001 Device 001 ID 0000 0000 s 001 Device 002 ID 413c a005 Dell Computer Corp Internal 2 0 Hub Once you have verified the board is connected correctly try detecting the cable manually instead of using auto detect Sometimes auto detect will fail to run when using libusb To do so in IMPACT go to Output gt Cable Setup In the Cab
50. application you created Implementing the Digital to Analog Converter DAC in uClinux The onboard DAC chip of the Spartan 3E Starter Kit provides 4 DACs each with an 12 bit output For more specifications regarding the setup and communication with the DAC please see the User s Guide 8 For testing you may wish to try building the DAC into your test development EDK project first as suggested in the section entitled Creating a Test Development EDK Project above That way you can program your board directly and test the DAC and your software without needing to recompile and load Petalinux onto the board To connect the DAC add the lines to the UCF for the DAC as specified in the sample UCF file in Appendix C Please note that in the sample file the DACs chip select CS is connected to bit 0 of the SPI Slave Select SS Vector Both the DAC CS and SS Vector are active low signals so it is possible to use the SS vector to enable the DAC device directly 36 In the EDK open System Assembly View and switch to the Ports Filter Hit Add External Port to add a new external port to the bottom of the list Rename the new port dac clr pin to match the sample UCF file set its direction to output O and connect it to the net vcc net since we wish the DAC to always be on Clearing the DAC can also be performed in software using a GPIO connected to the DAC CLR pin and sending a 1 to clear the DAC Add the correct entry into the UCF file
51. ce r mem amp r mem struct int re 0 const u32 prop int len struct xspi platform data pdata struct resource r Get sources memory IRQ associated with the device master spi alloc master amp ofdev gt dev sizeof struct xilinx spi master spi alloc master amp dev gt dev sizeof struct xilinx spi H if master NULL return ENOMEM dev set drvdata amp ofdev gt dev master platform set drvdata dev master pdata dev gt dev platform data rc of address to resource ofdev gt node 0 r mem If tre dev warn amp ofdev gt dev invalid address if pdata NULL ret ENODEV goto put master rc of irg to resource ofdev gt node 0 r irq if rc NO IRO dev warn amp ofdev gt dev no IRO found n r platform get resource dev IORESOURCE MEM 0 if r NULL ret ENODEV goto put master 342 84 341 69 xspi gt bitbang master gt setup xilinx spi setup init completion amp xspi gt done 62 xspi gt irq r irg gt start if request mem region r mem gt start r mem gt end r mem gt start 1 XILINX SPI NAME rc ENXIO dev warn amp ofdev gt dev memory request failure if request mem region r gt start r gt end r gt start 1 XILINX SPI NAME ret ENXIO goto put master xsp
52. ceive one after several minutes try clicking on Send me download instructions Once you receive the confirmation email download the core licenses full zip attachment and follow the instructions in the email to set up your license The Ethernet Lite OPB Core should now be successfully installed To test this try to build the hardware for the Spartan 3E RevD reference design for Petalinux located under petalinux svn hardware reference designs hardware reference designs Xilinx Spartan3E500 RevD edk91 system xmp If you receive errors such as the following the IP core license is not installed correctly lt IMAGE gt Please reread this section as well as the guide from the SuPER wiki 5 for more information Configuring TFTP in CentOS Once the core is successfully installed and tested on the computer the next step is to configure CentOS as the TFTP server so that files can be uploaded to the FPGA On your CentOS computer install TFTP by running the following command in the Console root localhost yum install tftp tftp server Install the software packages along with any dependencies it prompts to install After TFTP is installed open up etc xinetd d tftp with your favorite text editor If the file doesn t exit create a new file with this name Be sure to edit this file as root either directly or using the sudo command Set up the file with the following information 25 service tftp disable no socket typ
53. cell phone towers are deployed in the third world This allows people to communicate with phones while eliminating the need to the infrastructure The SuPER project aims at applying the same local grid idea for power in the third world 1 A SuPER module would operate a micro grid micro grid as the name suggests is a much smaller grid such as the size of a small village in Africa Using the SuPER as the main power source in this grid an entire village could be powered using power from renewable sources such as solar and wind energy Currently the initial SuPER system is operational and the next phase of development is in progress Part of the next phase includes replacing the laptop that controls the inputs and outputs to the sensors and controls to the SuPER system It currently consumes around 60W of instantaneous power To lower power consumption to under 3W a Spartan3E FPGA will be used to control the system and read inputs and outputs Brian Estrada and Patrick Mariano have already developed and tested a working Linux system known as uClinux on the Spartan3E 2 However while the base Linux system is running on the FPGA there currently is no driver to control the SPI devices such as the digital to analog converter DAC and analog to digital converter ADC These devices are essential to reading the sensor input and sending out the control signals and PWM output voltage to the SuPER system This paper focuses on the next iteration o
54. e dgram protocol udp wait yes user root server usr sbin in tftpd server args s tftpboot per source 11 cps 100 2 flags IPv4 Be sure to verify that all the entries are correct The user root line is the same regardless of whether you are logged in as root or not Once the file has been verified restart the xinetd service by going to System gt Administration gt Services and entering the root password In the Service Configuration window scroll down select the xinetd service and hit Restart Hit OK to the success message and close the Service Configuration window Run the following commands to set up the tftpboot directory if it hasn t already been created to use with TFTP root localhost mkdir tftpboot root localhost chown R nobody nobody tftpboot root localhost chmod R 777 tftpboot You may also wish to chown the tftpboot directory to your user name instead otherwise you will have to use the sudo command when running make all under the petalinux svn software petalinux dist directory To test TFTP copy or create a file under tftpboot and then try to download it locally to your computer using TFTP root localhost touch tftpboot some_file root localhost tftp localhost tftp gt get some_file tftp gt quit 26 If successful and run Is to view your current directory The file you placed in tftpboot and downloaded with TFTP shou
55. e LCD screen If you wish to use the LCD be sure to add an LCD GPIO to your project and add the correct pins in the UCF file Otherwise remove the references to the LCD functions To convert this project to your test development EDK project the constants need to be changed as described in the section entitled Creating a Test Development EDK Project 46 Once you have written the software recompile the hardware design and load the download bit file onto your Spartan board If you are using a test EDK project load the Spartan 3E Starter Kit through IMPACT to verify that the ADC is working using your code Once your are satisfied with the results copy your hardware configuration settings and UCF file changes to the Petalinux reference design and translate your software project into a user application as discussed above in the section entitled Creating a Test Development EDK Project If you are using Petalinux or are translating your changes over to Petalinux be sure to create and compile in your code as a user application as discussed in the section entitled Creating User Applications for uClinux in Brian and Patrick s paper 2 Program your board with the bit file reload the U boot configuration and kernel image and then boot Petalinux to test your user application and communication with the ADC 47 X Testing To test SPIDEV there are several test scripts that can be implemented to test the SPIDEV driver The default test script for
56. e of Xilinx ISE and EDK by writing my own IP core which I had not done before
57. e of these options does not appear please exit and reapply the patch properly SPI support ESET St Figure 1 Settings for the SPI device driver section of the uClinux kernel 33 Exit out of the current screen and select Character Devices Be sure that Xilinx OPB SPI Support is unchecked Also check Xilinx OPB GPIO Support since GPIOS are used for many devices in the EDK design including the custom IP core discussed in the section entitled Adding the Custom Flash ADC Control IP Core Character devices i Figure 2 Settings for the character device driver section of the uClinux kernel Hit Exit three times and hit Yes to save the new configuration Type make all to build the new kernel When Petalinux boots up a message for spi and xilinx spi should be listed as shown in the figure below 0x00000000 0x00040000 boot 0x00040000 0x00080000 bootenv 0x00080000 0x000c0000 config Ox000c0000 0x005c0000 image 0x005c0000 0x00fc0000 spare uclinux mtd RAM probe address 0x242239d8 size 0x230000 Creating 1 MTD partitions on RAM 0x00000000 0x00230000 ROMfs uclinux mtd set ROMfs to be root filesystem index 5 spi spi0 0 xilinx spi setup transfer unsupported clock rate 1000000Hz bus uses 1562500Hz xilinx spi xilinx spi 0 at 0x41000000 mapped to 0x41000000 irq 0 i8042 c 18042 controller self test timeout input Button Keypad as class input inputo Directional Button amp Ro
58. ect was petalinux v0 30 rcl However since then the uclinux microblaze mailing list has updated the code to petalinux v0 40 rc3 Although I have not confirmed this many of the developers on the mailing list suggested that the SPIDEV driver be added to the latest release As of petalinux v0 40 rc3 which I used to test the procedures I ve outlined in this paper there is still no SPIDEV support in the kernel by default If newer releases emerge it may be worth looking into them since then it would be unnecessary to run the patch and make manual modifications to the uClinux kernel This is merely 49 suggestion the SVN build which is the latest will be based off of petalinux vO 40 rc3 and will also include the latest software updates so either build may already include the SPIDEV driver now The code I have used and developed was provided to Dr Harris on a CD to allow the next student working on the uClinux part of the SuPER project to continue development from where I have left of so the best suggestion regarding the software would be to use the version on the CD to develop your changes since it is where I left off in my work User Friendly SPI Interface Although the code provided in Appendix D provides a good framework for accessing the SPI devices in Petalinux a much better program could be written to provide more functionality and easier user access The user application used in this paper was merely a simple interface to verify that
59. enable Ethernet 27 U Boot gt setenv ipaddr lt IP Address gt U Boot gt setenv serverip lt Server IP gt U Boot gt saveenv Where lt IP Address is a valid IP address on your network and lt Server IP is the IP of your Cent OS workstation Once these settings are saved run the following to download the auto configuration script for Petalinux U Boot gt tftp clobstart ub config img U Boot gt autoscr fileaddr The auto configuration will update all the U boot settings for Petalinux Please note that this will also reset your IP settings In the future these IP settings should be written into the auto configuration script You may also wish to use DHCP to get an IP address rather than using static addresses For more information regarding these topics see Petalinux website regarding customizing U Boot 6 and setting up DHCP 7 Rerun the environment variable settings above again From this point forward these IP settings will be saved until the next time your load a new ub config img file Load the u boot s bin file next using the following commands U Boot gt tftp clobstart u boot s bin U Boot gt protect off bootstart bootsize U Boot gt erase bootstart S bootsize U Boot gt cp b clobstart bootstart filesize Next load the kernel image ub file using the following commands U Boot gt tftp clobstart image ub U Boot gt protect off kernstart S kernsize U Boot gt erase
60. ented the driver with help from the uclinux microblaze mailing list Once the interface was up and testing well I added the DAC into the Petalinux user application for SPI access Finally I worked on the addition of the ADC to the SPI interface in Petalinux including development of a new IP core that would handle the contention on the pin that is shared between the flash memory and ADC The main hurdles in this project were the documentation regarding SPI drivers for Petalinux and the bus contention issues with the ADC Thanks to the mailing list I was able to develop and implement the SPIDEV driver successfully The ADC works correctly under the test environment and Xilinx s lack of information regarding use of the ADC and flash together presented a considerable roadblock which I was able to overcome with a custom IP core The uclinux microblaze mailing list was very helpful for learning about previous implementations as 51 well as providing support and advice regarding pieces of this project such as the SPIDEV driver All the previous work done by Brian Patrick and Alex also helped greatly in understanding Petalinux and SPI devices Without their work this project would not have been possible in the twenty weeks that it lasted 52 Appendix A Bibliography 1 James G Harris White Paper for Sustainable Power for Electrical Resources SuPER Available http courseware ee calpoly edu jharris research super project white pap
61. er susper pdf 2 Brian Estrada and Patrick Mariano Development of uClinux Platform for Cal Poly SuPER Project Available http courseware ee calpoly edu jharris research super project be pm sp pdf 3 Alex Diaz Development of uClinux SPI interface On Spartan 3e Development board For Cal Poly Super Project Available http courseware ee calpoly edu jharris research super project ad sp pdf 4 Matt Staniszewski HOWTO Setup the CentOS and Xilinx Development Environment Available http super ceng calpoly edu doku php id howto setup centos xilinx 5 Matt Staniszewski HOWTO Obtain and Install the Ethernet Lite OPB Core Available http super ceng calpoly edu doku php id howto ethernet lite 6 Petalogix Customizing U Boot Available http developer petalogix com wiki UserGuide Bootloaders UBoot CustUBoot 7 Petalogix System Setting Configuration Menu Available http developer petalogix com Wiki UserGuide Customising SystemConfigMenu 8 Xilinx Spartan 3E FPGA Starter Kit Board User Guide Available http www xilinx com support documentation boards and kits ug230 pdf 53 Appendix B SPIDEV Kernel Patch diff rupN petalinux svn orig software linux 2 6 x petalogix arch microblaze platform common Makefile petalinux svn software linux 2 6 x petalogix arch microblaze platform common Makefile petalinux svn orig software linux 2 6 x petalogix arch m
62. erms of the GNU General Public License version 2 This program is licensed as is without any warranty of any kind whether express or implied tinclude lt linux autoconf h gt tinclude lt linux init h gt finclude lt linux resource h gt finclude linux xilinx devices h gt finclude linux serial 8250 h gt define XSPI PLATFORM DATA INITIALISER n X 54 device flags CONFIG XILINX SPI iini FIFO EXIST XSPI HAS FIFOS 0 IN CONFIG XILINX SPI_ n SPI SLAVE ONLY XSPI SLAVE ONLY 0 num slave bits CONFIG XILINX_SPI_ n _NUM_SS_ BITS define XSPI PLATFORM DEVICE INITIALISER n N s name xilinx spi sid HY N dev platform data amp xspi pdata n N num resources 2 N resource struct resource X start CONFIG XILINX SPI n BASEADDR end CONFIG XILINX_SPI_ n HIGHADDR X flags IORESOURCE_MEM ys N start CONFIG XILINX SPI tittntttt IRO X m end CONFIG XILINX SPI iini IRO flags IORESOURCE IRO j N a static struct xspi_platform_data xspi_pdata ifdef CONFIG XILINX SPI 0 INSTANCE XSPI PLATFORM DATA INITIALISER 0 endif ifdef CONFIG XILINX SPI 1 INSTANCE XSPI PLATFORM DATA INITIALISER 1 endif ifdef CONFIG XILINX SPI
63. etting me bounce ideas off of them at our meetings Your suggestions and ideas helped me greatly in advancing the SPI driver development part of our project To Dr John Williams Michal Simek Carsten Bartsch and all the other contributors to the microblaze uclinux mailing list thank you for your guidance and help Your hints tips and examples helped me overcome all the hurdles in developing the SPI driver and I thank you I hope that my comments and updates on the mailing list will be helpful in developing future releases of uClinux as well as helpful to those seeking to implement a SPI driver using Microblaze Finally thanks Tom Hickok for your vast knowledge of Microblaze and Xilinx Thanks for your help implementing components on the Spartan 3E Starter Kit in the EDK as well as your design ideas for an IP core that helped me with the last hurdle in my project I Introduction The Sustainable Power for Electronic Resources SuPER project is aimed at bringing affordable and sustainable energy to the third world Currently 2 billion people in the world do not have electricity US Department of Energy However the costs and emissions of a traditional grid system can be very expensive to implement especially in the third world where no infrastructure exists An alternate approach would be to set up small localized grids in different areas This idea has already been applied to phone systems Instead of setting up a traditional phone network
64. f development on using uClinux on the Spartan3E Starter Kit with a focus on the development of a SPI driver It first gives an overview of the project and the objectives to be met Next it discusses design using Xilnx s ISE and EDK software Then the paper describes setup of the development environment as well as setup and usage of the SPI driver in uClinux After it discusses the implementation of the DAC and ADC in uClinux Finally the testing applications used for this project are presented as well as recommendations for future development The appendices contain references the SPIDEV kernel patch a sample UCF File and the SPI user application for Petalinux Naming Conventions In this paper several terms are used to represent the same object or concept Although Petalinux is a specific version of uClinux the terms uClinux and Petalinux are synonymous with each other in this paper Also the Spartan 3E Starter Kit is given a variety of names throughout this paper Some examples include Spartan 3E Starter Kit Spartan 3E FPGA Spartan 3E FPGA and board Please bear in mind that all these terms describe the exact same board that is being used to implement the SuPER control system 10 II Background Currently the SuPER system uses a laptop to gather sensor data from various inputs and send out the PWM output to the PIC microcontroller However the laptop consumes a large amount of power 60W instantaneous An alternati
65. files over to the board at the fastest rate Next this project will develop a SPI driver for uClinux It will continue the work of Alex 3 in SPI driver development considering his ideas as well as new ones developed by myself as well as suggestions from the uclinux microblaze mailing list The SPI driver will be implemented in the Petalinux kernel to allow a user to write an application to easily interface to a SPI device inside the uClinux environment If possible the code will be developed in such a way that it is as similar to software written in courses such as CPE 329 that interface with SPI devices without the use of Petalinux Finally SPI devices necessary for the operation of the SuPER project will be implemented using the new driver First digital to analog converters DACs will be implemented that take digital values and send out analog outputs such as the PWM control signal to the PIC Second analog to digital converters ADCs will be implemented that take 13 analog inputs from sensors on the SuPER system and convert them to digital values that can be stored for logging data 14 IV Design Xilinx EDK Software The initial design work regarding Petalinux has been carried out and explained by Brian and Patrick in their paper 2 Similarly this project will use the Xilinx EDK software to develop the hardware and software necessary to implement a SPI driver in Petalinux The SPI core will be implemented in the EDK using
66. fpga 0 flash adc ctl pin lt 0 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem OEN pin LOC c18 Net fpga 0 FLASH 16Mx8 Mem OEN pin IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem WEN pin LOC d17 Net fpga 0 FLASH 16Mx8 Mem WEN pin IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem CEN pin lt 0 gt LOC d16 Net fpga 0 FLASH 16Mx8 Mem CEN pin lt 0 gt IOSTANDARD LVCMOS33 Net flash CEN pin lt 0 gt LOC d16 Net flash CEN pin 0 IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 emc ben gnd pin LOC c17 Net fpga 0 FLASH 16Mx8 emc ben gnd pin IOSTANDARD LVCMOS33 Module DDR SDRAM 32Mx16 constraints Net fpga 0 DDR SDRAM 32Mx16 DDR Clk pin LOC J5 Net fpga 0 DDR SDRAM 32Mx16 DDR Clk pin IOSTANDARD SSTL2 I Net fpga 0 DDR SDRAM 32Mx16 DDR Clkn pin LOC J4 Net fpga 0 DDR SDRAM 32Mx16 DDR Clkn pin IOSTANDARD SSTL2 I Net fpga 0 DDR SDRAM 32Mx16 DDR Addr pin lt 0 gt LOC P2 Net fpga O DDR SDRAM 32Mx16 DDR Addr pin lt 0 gt IOSTANDARD SSTL2 I Net fpga 0 DDR SDRAM 32Mx16 DDR Addr pin lt 1 gt LOC N5 Net fpga O DDR SDRAM 32Mx16 DDR Addr pin lt 1 gt IOSTANDARD SSTL2 I Net fpga 0 DDR SDRAM 32Mx16 DDR Addr pin lt 2 gt LOC T2 Net fpga O DDR SDRAM 32Mx16 DDR Addr pin lt 2 gt IOSTANDARD SSTL2 I MDA A Z EE E EE Z EZ E E EZ EZ EZ EZ E EM ZZ EE UE UE Z UZ UZ UE EZZ Z a UE UZ UZ Z UZ UZ UE ZE UZ ZZ ZM UM UM UM A A N AES D D D 0 D D D D D D D D D D D D D D D D D
67. i gt regs loremap r mem gt start r mem gt end r mem gt start 1 xspi gt regs ioremap r gt start r gt end r gt start 1 if xspi gt regs NULL rc ENOMEM dev warn amp ofdev dev ioremap failureln goto release mem xspi gt irq r irq gt start dynamic bus assignment master gt bus num 1 number of slave select bits is reguired prop of get property ofdev gt node xlnx num ss bits Glen if prop len lt sizeof prop dev warn amp ofdev dev no xlnx num ss bits property ret ENOMEM goto put master ret platform get irq dev 0 if ret lt 0 ret ENXIO goto unmap io master gt num chipselect prop xspi gt irq ret master gt bus num pdata gt bus num master num chipselect pdata gt num chipselect xspi gt speed hz pdata gt speed hz SPI controller initializations xspi init hw xspi gt regs Register for SPI Interrupt rc request irg xspi gt irg xilinx spi irg 0 XILINX SPI NAME xspi if re 0 1 dev warn amp ofdev gt dev irq request failure d n xspi gt ira ret request irq xspi gt irq xilinx spi irg 0 XILINX SPI NAME xspi if ret 0 goto unmap io rc spi bitbang start amp xspi gt bitbang 63 if rc 0 dev err amp ofdev gt dev spi bitbang start FAILED ret spi bitbang start amp x
68. icroblaze platform common Makefile 2009 01 30 12 24 12 000000000 0100 petalinux svn software linux 2 6 x petalogix arch microblaze platform common Makefile 2009 03 02 10 38 46 000000000 0100 RG 14 7 14 7 QA EXTRA CFLAGS IS TOPDIR drivers xili platobj S CONFIG MTD PHYSMAP physmap flash o platobj S CONFIG XILINX GPIO xgpio o platobj CONFIG XILINX SPI xspi o platobj S CONFIG SPI XILINX xspi o platobj CONFIG SERIAL UARTLITE xuartlite o platobj CONFIG SERIAL 8250 x16550 0 platobj CONFIG XILINX SYSACE xsysace o diff rupN petalinux svn orig software linux 2 6 x petalogix arch microblaze platform common xspi c petalinux svn software linux 2 6 x petalogix arch microblaze platform common xspi c petalinux svn orig software linux 2 6 x petalogix arch microblaze platform common xspi c 2007 04 01 22 54 51 000000000 0700 petalinux svn software linux 2 6 x petalogix arch microblaze platform common xspi c 2009 05 18 23 44 51 000000000 0700 GR 1 83 1 80 arch microblaze pla tform common xspi c platform device initialisation for Xilinx SPI devices cm E Copyright 2007 PetaLogix UAE based on original kernel platform c which was Copyright 2007 LynuxWorks o e This file is licensed under the t
69. igned R 0x14 volatile unsigned R 0x18 volatile unsigned R 0x1C ER 0x03 IAR IPR amp X pending interrupt and acknowledge fendi int gain long long long long long long long long IPR amp x 0x00300000 b amp 0x07 lt lt 4 unsigned int Check for 82 83 OKO k kok k kok k k kk k kk k ARA KKK KKK k Lede FR I A X kA RARA include lt linux autoconf h gt finclude lcd h int readLcdStatus VIE Ty E Set LCD data lines to inputs LCD DD LCD DATA Set data lines to inputs First read cycle CD LCD RW CD Fh h or i 0 i lt 5 LCD LCD RW LCD RW LCD E 125ns LCD amp LCD DATA i 125ns E high for 250ns i Wait 750ns Second read cycle r lt lt 4 LCD LCD RW LCD E 125ns r LCD amp LCD DATA 125ns E high for 250ns for i 0 i lt 5 i Wait 750ns LCD LCD_RW Set LCD back to output LCD_DD 0 Send back status byte return r amp OxFF void sendLcd int rs int i int d First write cycle LCD rs LCD rs LCD LCD rs LCD LCD rs d for i 0 i lt 5 LCD rs Et Ed void returnLcdHome di 125ns d 125ns total E high for 250ns 125ns
70. inux spi spi_bitbang h gt include lt linux io h gt include lt linux xilinx_devices h gt define XILINX_SPI_NAME xilinx_spi Register definitions as per OPB Serial Peripheral Interface SPI v1 00e 147 11 144 20 Qee struct spi_transfer t u8 bits_per_word u32 hz struct xilinx_spi xspi spi_master_get_devdata spi gt master bits per word t t gt bits per word spi gt bits per word hz t t gt speed hz spi gt max speed hz if bits per word 8 dev err amp spi gt dev s unsupported bits per word din func bits per word t dev err amp spi gt dev s unsupported bits per word d bus supports 8 n fune return EINVAL bits per word if hz amp amp xspi gt speed hz gt hz dev err amp spi gt dev s unsupported clock rate uHz bus uses SuHzin func hz xspi gt speed_hz return EINVAL ee stati ee stati 61 299 38 304 32 Qe return IRO HANDLED c int init xilinx spi of probe struct of device ofdev const struct of device id match c int init xilinx spi probe struct platform device dev int ret 0 struct spi master master struct xilinx spi xspi struct resource r irg struct struct resource r mem struct struct resource r irg amp r irg struct struct resour
71. ld be in the current working directory If not go back and verify the settings in the section above Also restart your computer to make sure all the settings have taken effect Configuring TFTP in Petalinux After TFTP has been installed and test in CentOS Petalinux must be configured to use Ethernet and TFTP for file transfer By default the Petalinux kernel is already set up to use and implement Ethernet so no additional software settings are needed Only the hardware reference design must be rerun with the core license installed Please note that while this method is much faster serial is still used primarily for uploading the SREC file and monitoring the console output from the Spartan 3E board The TFTP transfer is used for uploading the ub config img u boot s bin and image ub files which take a long time to upload via serial connection After the hardware reference design has been recompiled rerun petalinux copy autoconfig under petalinux svn hardware reference designs hardware reference designs Xilinx Spartan3 E500 RevD edk91 and run make all under the petalinux svn software petalinux dist directory to recompile the kernel Program the board with the new bit file and upload the SREC file as per instructions in Brian and Patrick s paper 2 Once the SREC file is loaded press any key in the Kermit serial console to stop U boot from automatically booting To use TFTP configure the following environment variables to
72. le Communication Setup window click Xilinx USB Cable as the Communication Mode and hit OK Try to initialize the chain once more in iMPACT If this fails to work try power cycling your board reseating the USB cable and then reopening iMPACT Downloading Petalinux Petalinux is a distribution of uClinux that was created by Petalogix For this paper the latest testing or SVN release was used for the SPI driver development Please remember that the words uClinux and Petalinux are used interchangeably throughout this paper To download the latest SVN build follow the instructions on Petalinux s website at http devloper petalogix com After the file has been downloaded extract it to a directory under your home directory For this paper the Petalinux directory was extracted to petalinux svn and this directory will be referred to throughout this paper The Petalinux archive contains a lot of files so the extraction process may take a long time Creating a Test Development EDK Project While the Ethernet module makes updating the kernel faster it is still a slow process to update Petalinux if you are just testing a small hardware change or software bug Therefore it is 20 recommended to create a second EDK project based on the reference design This design can be used to program the Spartan 3E without the need to recompile a kernel and boot into uClinux That way you can test design changes such as adding a new SPI device or maki
73. linx EDK 36 Figure 5 The AD CONV external port configuration in Xilinx EDK 39 Figure 6 The AD CONV GPIO configuration in Xilinx EDK 39 Figure 7 The AMP SHDN external port configuration in Xilinx EDK 40 Figure 8 A diagram of the Flash ADC Control IP Core implementation 41 Figure 9 The Flash ADC Control IP core configuration in Xilinx EDK 42 Figure 10 The SPI IP core configuration in Xilinx EDK sees 42 Figure 11 The Flash IP core configuration in Xilinx EDK 43 Figure 12 The external port configuration for all the devices needed to implement the DAC and ADC in Xilinx EDR en ni nent tienne etant 43 Figure 13 The Flash ADC Select GPIO and LCD GPIO configuration in Xilinx EDK 44 Figure 14 The memory mappings for all the devices needed to implement the DAC and ADEIT BON adi ia 45 Acknowledgments I would like to first thank Dr Harris for getting me interested in the SuPER project and helping me understand the importance of both sustainable energy and the need to bring affordable energy to everyone It has been great working with everyone on the SuPER team who are just as dedicated Also Pd like to thank my fellow computer engineers Khanh Nguyen and Frank Scarfo for being a great team and l
74. lt stdio h gt include stdlib h include lt string h gt include linux autoconf h include spi h include intc h include lcd h static unsigned int deviceMask int twosComplement unsigned int num int n int num_2s 0 int i Function only works up to 32 bits Return 0 if n is gt 32 if n gt 32 return 0 If the MSB of the number is a one then perform two s complement and negate value else if num 0x1 lt lt n 1 Take the complement of the number and add 1 to get the two s complement value num 2s num 1 Zero out the upper bits from the nth to the 32nd bit for i nj i lt 32 i num_2s amp 0x1 lt lt i If the MSB of the number is a one then negate the two s complement value if num amp 0x1 lt lt n 1 num 2s 1 Positive number which is the same as the two s complement equivalent else num_2s num return num_2s 75 76 void initSPI void Set all salve select lines high SPISSR 0 Set up SPI control register SPICR 0x086 Enable SPI interrupts SPIGIE 0 Set up device mask which is the status when all the SS lines are high deviceMask SPISSR Enable the interrupt in Intc SIE XPAR OPB SPI 0 IP2INTC IRPT MASK void clearSPI void Wait for the last transaction to
75. ne XSPI PLATFORM DEVICE INITIALISER n N name xilinx spi X id n dev platform data amp xspi pdata n N t num resources 2 N resource struct resource X T start CONFIG XILINX SPI _ n BASEADDR end CONFIG XILINX SPI_ n HIGHADDR flags IORESOURCE MEM X T tr start CONFIG XILINX SPI ttitintttt IRO end CONFIG XILINX SPI n IRO flags IORESOURCE IRO X t static struct xspi platform data xspi pdata 55 x E oun FU H Fh Hh FU be Ho U tU H Fh Hh U x n FU H HAD XSPI PL XSPI PL XSPI PL PLAT PLAT PLAT CONFIG XILINX SPI 0 INS FORM DATA INITIALISER 0 CONFIG XILINX SPI 1 INS FORM DATA INITIALISER 1 CONFIG XILINX SPI 2 INS FORM DATA INITIALISER 2 struct platform device xil CONFIG XILINX SPI 0 INS ANCE ANCE ANCE ANCE ATFORM D CONFIG X EVICE INI ILINX SPI IALISER 0 1 INS ATFORM D CONFIG X EVICE INI ILINX SPI 2 INS IALISER 1 ATFORM D int __init xspi platform init void EVICE INI IALISER re TRES for i 0 i lt ARRAY SIZI turn 0 diff E xilinx spi device platform device register 6x device initcall xspi platform init Jinx spi de
76. necessary for the SuPER to work correctly in uClinux First the digital to analog converter DAC which would be used to send out an 11 analog signal to the MOSFET switches as well as the PWM control signal Second the analog to digital converter ADC would be used to take analog inputs from the sensors on the SuPER system and convert them to digital signals that could be saved for logging purposes Alex Diaz began work on this next iteration and discusses the use of SPI with Petalinux in his paper 3 However he was unable to find a driver that worked correctly in Petalinux which proved to be quite difficult due to the lack of information regarding SPI driver development in uClinux 12 III Requirements This project will develop the Petalinux development environment further as well as a SPI driver that will interface SPI devices using Petalinux First the project will focus on the finding the best environment to develop hardware and software for Petalinux This includes previous approaches discussed in both Brian and Patrick s 2 and Alex s papers 3 The optimal operating system environment will be described as well as setup and installation of Xilinx EDK and ISE as well as the other tools necessary to develop the Petalinux environment Faster methods of file transfer to the Spartan 3E Start Kit will also be examined such as USB and Ethernet The optimal interface will be chosen for its ability to transfer the uClinux kernel
77. ng a software change to your user application To do so copy over the entire hardware reference design in the petalinux svn hardware reference designs Xilinx Spartan3E500 RevD edk91 directory Rename the folder to something else such as test dev so that it doesn t conflict with the reference design Open the project in EDK It will open an exact copy of the reference design from Petalinux To develop software the Petalinux kernel and U boot software information must first be removed Go to the Applications tab right click on the fs boot project and hit Delete Project Add a new Software Project by double clicking Add Software Application Project typing a name in the Project Name field and hitting OK Be sure to right click on it and hit Mark to Initialize BRAMS otherwise the project will not compile into the download bit file Add your headers and source files to the new project to develop your software code If you do not at source files you will receive an error about your elf file during compile time Once you are ready to test your code compile your EDK design and download the bit file to your Spartan 3E Starter Kit via IMPACT to test your design Converting from a Test EDK Project to Petalinux When you are ready to test your code in Petalinux copy the source and header files into a directory located under petalinux svn software user apps and compile it as a user application Please see the section entitled Creating User
78. o causes several issues that can cause serious delays As Alex suggests in the section entitled Environment Setup 3 running a VM can make serial operations slower The VM buffers data before sending it to the host operating system port This can cause delays between sending and receiving serial data This slows down the process of loading a new kernel image on to the Spartan 3E dramatically In some cases such as with VirtualBox the serial communication is delayed so much by the VM software that data is not sent in the correct order which can corrupt file downloads to the Spartan 3E FPGA Therefore it is suggested that you use a standalone installation of Linux to develop in instead of a VM whether it is on a dual boot system or by itself This eliminates the serial communication issues as well as gives a slight performance boost when downloading files to the Spartan 3E Starter Kit Installing Linux on your Computer For this project CentOS has been chosen as the best Linux operating system to develop Petalinux This distribution of Linux is recommended and supported by Xilinx and thus used as the main development platform Install the current version of CentOS from their website at http www centos org At the time of the writing this paper CentOS 5 was the most current version More detailed instructions regarding the installation of CentOS as well as initial setup can be found on the SuPER wiki 4 and in Alex s paper 3 16 Once
79. oftware petalinux dist vendors Xilinx Spartan3E500 RevD config linux 2 6 x petalinux s etc init d checkroot etc rc d S0lcheckroot svn software petalinux dist vendors Xilinx Spartan3E500 RevD config linux 2 6 x petalinux svn orig software petalinux dist vendors Xilinx Spartan3E500 RevD config linux 2 6 x 2009 02 02 11 55 59 000000000 0100 petalinux svn software petalinux dist vendors Xilinx Spartan3E500 RevD config linux 2 6 x 2009 02 05 19 31 09 000000000 0100 1541 8 1541 20 CONFIG XILINX IIC y 1 SPI support 1 CONFIG SPI is not set CONFIG SPI MASTER is not set CONFIG SPI y 4 4 CONFIG_SPI_MASTER y SPI Master Controller Drivers CONFIG_SPI_BITBANG y CONFIG_SPI_XILINX y CONFIG MCFOSPI is not set SPI Protocol Masters ONFIG_SPI_SPIDEV y Dallas s 1 wire bus Appendix C Sample UCF File 68 HEH HEH HE HEE HEH EE EE HE HE EH EH EEE EEE EE EEE EEE HEE dt tt EE Ga Gad tt tt tt gt dt dt dt dt tt HEE dt This system ucf file is generated by Base System Builder based on the settings in the selected Xilinx Board Definition
80. ogic 1 01 2 dar cik90 inv util vector logic 1 01 Adem O dem module 1 0 amp 9dcm 1 dcm module 1 01 dom 2 dem module 1 01 Reset GPIO opb gplo 3 0 cpu reset proc sys reset 1 0 amp SPopb sp O opb spl 1 01 ad conv opb_gplo 3 0 Prflash adc ctl O flash adc ctl a 2 flash adc sel opb gpio 3 0 opm ok sys cik s ji Cik GPIO 10 O Mash adc ct O SEL zlo 0 C lcd opb_gpio 3 0 OPB Gkk sys cik s Cik GPIO IO lcd GPIO IO rio 0 C gt A f Block Diagram1 System Assembly View Figure 13 The Flash ADC Select GPIO and LCD GPIO configuration in Xilinx EDK Change the Filter to Bus Interface and hook up the new flash adc sel GPIO to the OPB bus by clicking the green circle to the left of the SOPB connection Change the Filter to 45 Addresses and assign the flash adc sel GPIO 512 bytes starting at 0x42000000 to match the code in Appendix D Filters El Bus Interface C Ports Addresses if Generate Addresses min e eee ilmb cntlr SLMB 0x00000000 0x00001fff BK 71O E bin rotary decoder SOPB 0x400a0000 ex460afftt lsak vid moop FLASH 16Mx8 SOPB MEMO 9x21000000 oxntttitt fim JH O a mob Ethernet MAG SOPB ox40e00000 ox4seofttt sx O ae E LEDs 8Bit SOPB ex40000000 ox40ooffff les va moop z DIP_Switches_4Bit SOPB 6x40828000 exaee2ttft sak v O mb opb E Reset GPIO SOPB 6x40830080 exace3ftft eak Ja mb opb z lcd SOPB 0x
81. onfiguration in Xilinx EDK Filters Be Bus Interface Ports C Addresses Ej Filters Applied 58 Add External Port devcik90 inv 2 dar clk90 inv dcm 1 dem 2 Reset GPIO sys clk s Se Gik dd conv GrIO IO io DC y Block Diagram1 tb System Assembly View1 B system ucf Figure 6 The AD CONV GPIO configuration in Xilinx EDK Next we need to add an external connection to the AMP SHDN net Hit Add External Port to add a new external port to the bottom of the list Rename the new port amp shdn pin to match the sample UCF file set its direction to output O and connect it to the net gnd net since we wish the Preamp and ADC to always be on Add the correct entry into the UCF file Shutting down the Preamp can also be performed in software using a GPIO connected to the AMP SHDN pin and sending a 0 to shut off the Preamp There are no issues with bus contention since the SS will control when the amp and thus ADC has access to the SPI bus Filters Be Bus Interface Ports C Addresses Yr Filters Applied 32 Add External Port Y ix en pin O Ethernet MAC PHY Tv AC P en fpga O Ethemet MAC PHY tx data pin TETA MAC PHY tx da Jo al J fpga O DDR CLK FB dor feedback s lux sys cik pin dom clk s feu fpga O spi SCK pin opo spi 0 SCK ho fpga O spi MOS pin spi O MOSI Io d fpga O spi SS pin spi 0
82. r 20 0 break case 0x6 divisor 50 0 break case 0x7 divisor 100 0 break default break Calculate ADC input voltage based on the formula in the User s Guide p 76 vin adc_val divisor 1 25 1 65 Send input voltage value back return vin int main int argc char argv unsigned int adc 2 0x00 0x00 unsigned int gain a gain b Initialize the SPI and LCD devices and clear the SPI bus initSPI clearSPI initLcd Set FLASH ADC S the 79 flash ADC control GPIO to an output and enable the ADC while disabling the flash by setting FLASH ADC S Ed 1 the value to DD 0x00 0x01 Print help message if arge 3 arge gt printf nusage printf nCurrent printf DAC A val pri pri x20 x50 x100 else Y Kf Run command based on arguments i e e e e e 1Se if incorrect number of arguments 4 n spi device lt options gt n n ly supported devices n n n lue gt nDAC_B lt value gt nDAC_C lt value gt nDAC_D lt value gt nDAC_ALL lt value gt nADC_ALL lt gain a gt lt gain b gt n n ntf Possible DAC value entries n n0O 4095 n n ntf Possible ADC gain a gt gain b entries ininxl all values negative Ann
83. r the built in Ethernet port on the Spartan 3E Specifically you will be able to use the Trivial File Transfer Protocol TFTP to upload files to your board via Ethernet Using TFTP the kernel image can be downloaded in about ten seconds rather than ten minutes with a serial connection This dramatically reduces the wait time while doing development and can be very useful Installing the Ethernet Core License Before using TFTP the Ethernet Core License must be installed first The following section provides information regarding installation of the core license For more information please see the guide on the SuPER wiki 5 What follows is a summary of that guide Go to the Ethernet Lite IP Core website on Xilinx s website at http www xilinx com products ipcenter xps ethernetlite htm and click on Access Lounge Log on to the site with your Xilinx user name and password If you do not have a logon register for free at Xilinx s website Once you enter your user name and password you 24 will be logged into the Access Lounge site for the Ethernet Lite IP Core Scroll down to the bottom of the page and select Generate the OPB 10 100 Ethernet MAC Lite License Key Fill out the form with the reguested information If you need help obtaining your Host ID please follow the link on the form to the help site Submit the form when you are finished filling it out A confirmation page will appear telling you to check your email If you do not re
84. rm data u32 device fl ags u8 num slave bits sl6 bus num ul6 num chips u32 speed hz Flags related t define XSPI HAS FIFOS define XSPI SLAVE GPIO Flags related t di dist vendors PetaLo d dist vendors PetaLo petalinux svn s 180 6 180 7 AE endif I2C MAJOR 89 SPIDEV MAJOR 153 elect 66 o XSPI device features 0x00000001 ONLY 0x00000002 o XGPIO devic features iff rupN petalinux svn orig software petalinux gix common common mak petalinux svn software petalinux ist vendors PetaLogix common common mak petalinux svn orig software petalinux gix common common mak 2009 01 15 18 08 10 000000000 0100 oftware petalinux dist vendors PetaLogix common common mak 2009 03 02 11 08 21 000000000 0100 DEVICES N ifndef CONFIG SYS CONFIG SYSTEM ROO 231 6 4232 15 done endif IIC make SPI nodes i EM ROOT PASSWD _PASSWD root ifdef CONFIG I2C f necessary max number of for i in 0 done endif SPI_SPID else 67 SPIDEV MAJOR taken from spidev c see definition above devices matches spidev c ifdef CONFIG SPI SPIDEV 12345 67 do touch ROMFSDIR dev spi i c SPIDEV_MAJOR i EV ROMFSINST COMMON etc rc checkroot etc init d checkroot ROMFSINS diff rupN petalinux svn orig s
85. s this pin and then set it manually in the software code In the EDK open System Assembly View and switch to the Ports Filter Add a new General Purpose IO GPIO IP Core from the IP Catalog on the left hand side by double clicking the core Rename it to ad conv to match the UCF file Right click on the new IP core and hit Configure IP In the Properties window change GPIO Data Bus Width to 1 and hit OK to close the Properties window In the Ports view connect OPB_CIk to sys clk s and click Make External under GPIO IO Scroll up and rename the External Port to ad conv pin to match the UCF file Change the Filter to Bus Interface and hook up the new ad conv GPIO to the OPB bus by clicking the green circle to the left of the SOPB connection Change the Filter to Addresses and assign the ad conv GPIO 512 bytes starting at 0x41900000 to match the code in Appendix D 39 Filters He Bus Interface Ports C Addresses jvFilters Applied Add External Port fpga 0 Ethemet MAG PHY tx data pin fpga O Ethernet MAC PHY tx da fpga 0 DDR CLK FB dor feedback s feux sys cik pin acm cik s y x ek t fpga 0 sp SCK pin opo spi 0 SCK Io fpga 0 spi MOS pin Job spi o Mos Io y y fpga O spi SS pin fopb spi o ss o y 0 1 net vcc 3 0 GPIO IO ad conv Block Diagram1 System Assembly View1 B system ucf Figure 5 The AD CONV external port c
86. s wal Clk Mem A fpga O FLASH 16Mx8 Mem A sr JO 0 C Mem DQ I flash adc ctl 0 FLASH DQ I zji 0 C Mem DQ O flash adc ctl 0 FLASH DO O hd Le 0 C Mem DO T flash adc ctl O FLASH DO T jo 0 C Mem CEN flash adc ctl 0 FLASH CEN I hd Le 0 C Mem OEN fpga O FLASH 16Mx8 Mem OEN JO 0 C Mem WEN fpga O FLASH 16Mx8 Mem WEN JO 4 2 DDR SDRAM 32Mx16 mch opb ddr 1 8 Ethemet MAC opb ethernetlite 1 0 DP pb timer 1 opb timer 10 RS anh inte 9 anh inte 102 A A AAA AA AAA A AAA ggm tt aad Block Diagrami System Assembly View1 Figure 11 The Flash IP core configuration in Xilinx EDK r Filters Be Bus Interface Ports C Addresses Ejv Filters Applied 3 Add External Port ys cik pin acm cik s Jl Sr feux y t fpga O spi SCK pin fopb spi 0 SCK Io pga O spi MOS pin fopb spi o MOS 10 hd pga O spi SS pin fopb spi o SS Io y 0 1 dac cir pin het voc jl x Jl x ad conv pin ad conv GPIO IO Io y 0 0 amp shdn pin net qnd fpga O flash adc ctl pin fran adc ctl 0 PINS o y 0 7 pga O FLASH 16Mx8 Mem CEN pin friasn adc ctl O FLASH GEN O y 0 0 fica GPIO IO Io y 0 8 Block Diagram1 System Assembly Vlew1 Figure 12 The external port configuration for all the devices needed to implement the DAC and ADC in Xilinx EDK Please note that a LCD GPIO has also been added
87. spi gt bitbang if ret 0 dev err amp dev gt dev spi bitbang start FAILED goto free irg dev info amp ofdev gt dev at 0x 08X mapped to 0x 08X irg din unsigned int r mem gt start u32 xspi gt regs xspi gt irg Add any subnodes on the SPI bus of register spi devices master ofdev gt node dev info amp dev gt dev at 0x 08X mapped to 0x 08X irg din r gt start u32 xspi gt regs xspi gt irg return rc return ret free ird free irq xspi gt irq xspi unmap io iounmap xspi gt regs release mem release mem region r mem gt start resource size r mem put master stati spi master put master return re return ret c int __devex ilinx spi remove struct of device ofdev stati it x it X 42 wo MODUL stati c int __devex ilinx spi remove struct platform device dev struct xilinx spi xspi struct spi master master struct resource r mem master platform get drvdata ofdev master platform get drvdata dev xspi spi master get devdata master spi bitbang stop amp xspi gt bitbang free irq xspi gt irq xspi iounmap xspi gt regs if of address to resource ofdev gt node 0 amp r mem release mem region r mem start resource size amp r mem dev set drvdata amp ofdev gt dev 0 platform set drvdata dev 0 spi master put xspi bitbang master
88. t PULLUP SDRAM 32Mx16 DDR DO pin lt 13 gt LOC L3 SDRAM 32Mx16 DDR DO pin lt 13 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 13 gt PULLUP SDRAM 32Mx16 DDR DO pin lt l4 gt LOC L1 SDRAM 32Mx16 DDR DO pin lt l4 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt l4 gt PULLUP SDRAM 32Mx16 DDR DO pin lt l5 gt LOC L2 SDRAM 32Mx16 DDR DO pin lt l5 gt IOSTANDARD SSTL2 I SDRAM 32Mx16 DDR DO pin lt 15 gt PULLUP ernet MAC constraints rnet MAC PHY tx clk pin LOC T7 rnet MAC PHY tx clk pin IOSTANDARD LVCMOS33 rnet MAC PHY rx clk pin LOC V3 rnet MAC PHY rx clk pin IOSTANDARD LVCMOS33 rnet MAC PHY crs pin LOC U13 rnet MAC PHY crs pin IOSTANDARD LVCMOS33 rnet MAC PHY dv pin LOC V2 rnet MAC PHY dv pin IOSTANDARD LVCMOS33 rnet MAC PHY rx data pin lt 0 gt LOC V8 rnet MAC PHY rx data pin lt 0 gt IOSTANDARD LVCMOS33 rnet MAC PHY rx data pin lt l gt LOC T11 rnet MAC PHY rx data pin 1 IOSTANDARD LVCMOS33 rnet MAC PHY rx data pin lt 2 gt LOC U11 rnet MAC PHY rx data pin lt 2 gt IOSTANDARD LVCMOS33 rnet MAC PHY rx data pin lt 3 gt LOC V14 rnet MAC PHY rx data pin lt 3 gt IOSTANDARD LVCMOS33 rnet MAC PHY col pin LOC U6 rnet MAC PHY col pin IOSTANDARD LVCMOS33 rnet MAC PHY rx er pin LOC U14 rnet MAC PHY rx er pin IOSTANDARD LVCMOS33 72
89. t 0 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR BankAddr pin lt 1 gt LOC K5 fpga RAM 32M DDR BankAddr pin lt 1 gt IOSTANDARD SSTL2 I RAM 32M RAM 32M RAM 32M RAM 32M 32M RAM 32M RAM 32M RAM 32M DR CASn pin LOC C2 DR CASn pin IOSTANDARD SSTL2 I DR CKE pin LOC K3 DR CKE pin IOSTANDARD SSTL2 I DR CSn pin LOC K4 DR CSn pin IOSTANDARD SSTL2 I DR RASn pin LOC C1 DR RASn pin IOSTANDARD SSTL2 I fpga fpga fpga fpga fpga fpga fpga fpga LT b g SO OO 10 0 9 GO Ove CO 0 00 O SO 0 00 DIO COT CIL C9 OS COS OO OC OO DOS Ove 0 0 0 O DS OO COS CS F F S ER RER S pc pe RER O RER RR FEE Ph PRE RTP Ez pop 1p ah OVOVOV O o o GY OY OY OY OY O S OY OY OY OY OY O1 OY OY OY OY OY OY OY OY OY O1 OY DINDINDMA QU OO UU OO OO OO OO OO OO OO OO OO OO OO OO OO OO CO QUU UL UU UU OO OO OO OO CO OO OO os CO D UJ UJ D D UJ UJ UJ D D UJ UJ UJ D D UJ UJ D UJ UJ UJ UJ D UJ UJ UJ UJ D D UJ UJ UJ D UJ UJ UJ D D UJ UJ UJ D UJ UJ UJ UJ D D UJ UJ UJ UJ UJ UJ UO UO UJ Qo uu uututuu utcututuuutututuutcutuutcuutututuucututututuuutuuuutuutuututu
90. t fpga 0 Rotary A pin LOC K18 PULLUP Net fpga 0 Rotary A pin IOSTANDARD LVCMOS33 Net fpga 0 Rotary B pin LOC G18 PULLUP Net fpga 0 Rotary B pin IOSTANDARD LVCMOS33 Net fpga 0 Rotary center pin LOC V16 PULLDOWN Net fpga 0 Rotary center pin IOSTANDARD LVCMOS33 Module FLASH 16Mx8 constraints Net fpga 0 FLASH 16Mx8 Mem A pin lt 31 gt LOC h17 Net fpga 0 FLASH 16Mx8 Mem A pin lt 31 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 30 gt LOC j13 Net fpga 0 FLASH 16Mx8 Mem A pin lt 30 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 29 gt LOC 312 Net fpga 0 FLASH 16Mx8 Mem A pin lt 29 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 28 gt LOC j14 Net fpga 0 FLASH 16Mx8 Mem A pin lt 28 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 27 gt LOC j15 Net fpga 0 FLASH 16Mx8 Mem A pin lt 27 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 26 gt LOC 516 Net fpga 0 FLASH 16Mx8 Mem A pin lt 26 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 25 gt LOC j17 Net fpga 0 FLASH 16Mx8 Mem A pin lt 25 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 24 gt LOC k14 Net fpga 0 FLASH 16Mx8 Mem A pin lt 24 gt IOSTANDARD LVCMOS33 Net fpga 0 FLASH 16Mx8 Mem A pin lt 23 gt LOC k15 Net fpga 0 FLASH
91. tary Encoder Driver c 2007 PetaLogix CP cubic registered ET Registered protocol family 1 VFS Mounted root cramfs filesystem readonly Freeing unused kernel memory 88k freed Mounting proc Mounting var Running local start scripts Mounting etc config Populating etc config Clock old time 1970 01 01 00 00 04 GMT Clock new time 1970 01 01 00 00 25 GMT flatfsd Created 6 configuration files 193 bytes Mounting sysfs Setting hostname Setting up interface lo Setting up interface eth0 Starting portmap Starting httpd Starting thttpd luclinux login Figure 3 A typical boot screen in Kermit showing the SPIDEV drive initialization This message verifies that you have set up the SPIDEV driver correctly in Petalinux 34 35 IX Implementing SPI Devices in uClinux Once Petalinux has been configured to use the SPIDEV devices that use the SPI bus such as the digital to analog converter DAC and analog to digital converter ADC can be easily implemented in the EDK by adding the correct modules and connecting the proper pins in the UCF file Once the hardware reference design has been recompiled a user application needs to be created to access the device and compiled into the Petalinux kernel Finally boot the Spartan 3E Starter Kit with the new hardware bit file and load the flash with the new U boot configuration and kernel images The SPI device will now be accessible using the user
92. tions tab and change the Firewall setting to Disabled Apply the settings to disable the firewall With the firewall disabled communication over the interface you are using serial USB Ethernet should work correctly now 17 Installing Xilinx ISE and EDK Please see the section in their paper entitled Installing the Xilinx ISE k EDK on a Linux Workstation in Brian and Patrick s paper 2 or the SuPER wiki 4 for more information regarding the installation of Xilinx ISE and EDK Once you have completed installing ISE and EDK copy each program s settings sh file over to etc profile d This forces the Xilinx environment variables to be applied every time the computer starts up This allows you to load the program without the need to source the settings sh files every time Use the following commands to do this root localhost ise9 1 cp settings sh etc profile d ise settings sh root localhost edk9 1 cp settings sh etc profile d edk settings sh The next time you start the computer your Xilinx environment variables will be automatically set Installing the USB Driver Once you have installed and setup Xilinx ISE and EDK correctly you must install the drivers to communicate with the Spartan 3E Starter Kit in order to download hardware bit files Previous papers have discussed using Xilinx s JTAG cable with Digilent Export to program the Spartan3E board However there is no Export for Linux Instead we must
93. to this bus For example if you want to use the DAC and ADC you would set this value to 2 Depending on the SPI device connected to the bus you may also wish to set the Ratio of OPB Clock Frequency to SCK Frequency setting As the name implies this is the OPB _ Clk ratio of SCK and is 32 by default This means that if you re using the default 50 MHz 50MHz 2 clock the SCK frequency will be 1 5625MHz The default setting is fine for the DAC and ADC but if you connect a slower device to the SPI bus such as a SD card module you may need to increase this ratio to lower the SCK frequency All other settings should be left the same in the SPI IP core properties window Click OK to close the window to save any changes and save the project Recompile your EDK project to include the SPI IP core Installing SPIDEV in Petalinux To use SPIDEV the correct kernel files need to first be updated or patched to integrate the driver into the default uClinux kernel The latest SPI driver from Xilinx is used to implement the SPIDEV driver and must first be downloaded and copied over to your Petalinux directory Xilinx uses git repositories to allow users to download the latest drivers for their devices Install git and obtain the Xilinx Linux repository using the following commands 31 root localhost yum install git root localhost git clone git git xilinx com linux 2 6 xlnx git Once the Xilinx git repository
94. tutuututututututuututut QU UUQuUUWUWuuxutuXuduuuuuuUWuuuuwduuuuuuudouuusxuuuuuuuuuuuuuuuuuuuuuuuuutuutuuuuuu by D z UUUUUUUUUUUUUUUULUUUCUULUUUUUUULULUULUUUUUKUUUUUUu u u u u uuuuuuuutuuu x xm X X X X X X X X MM X X MX KX X MM X X X MM X X MM X MM X X MX MM MM MM X X MM X X MX KX X MM XXX X X fpga RAM 32M DDR WEn pin LOC D1 fpga RAM 32M DDR WEn pin IOSTANDARD SSTL2 I fpga RAM 32M DDR DM pin lt 0 gt LOC J1 fpga RAM 32M DDR DM pin lt 0 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR DM pin lt 1 gt LOC J2 fpga RAM 32M DDR DM pin lt 1 gt IOSTANDARD SSTL2 I fpga RAM 32Mx16 DDR DOS pin lt 0 gt LOC G3 fpga RAM 32M DDR DOS pin lt 0 gt IOSTANDARD SSTL2 I Fpga RAM 32Mx16 DDR DOS pin lt l gt LOC L6 fpga RAM 32M DDR DOS pin lt 1 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR DOS pin lt 1 gt PULLUP fpga RAM 32M DDR DO pin lt 0 gt LOC H5 fpga RAM 32M DDR DQ pin lt 0 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR DO pin lt 0 gt PULLUP fpga RAM 32M DDR DO pin lt 1 gt LOC H6 fpga RAM 32M DDR DQ pin lt 1 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR DO pin lt 1 gt PULLUP fpga RAM 32M DDR DQ pin lt 2 gt LOC G5 fpga RAM 32M DDR DQ pin lt 2 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR DO pin lt 2 gt PULLUP fpga RAM 32M DDR DO pin lt 3 gt LOC G6 fpga RAM 32M DDR DQ pin lt 3 gt IOSTANDARD SSTL2 I fpga RAM 32M DDR DO pin lt 3 gt PULLUP fpga RAM 32M DDR DO pin lt 4 gt LO
95. two SPI buses in your Xilinx EDK hardware design and use SPIDEV you will use dev spi 0 and dev spi 1 in Petalinux to access devices on these buses Once the SPIDEV driver is properly set up and initialized accessing SPI devices such as DACs and ADCs can be done using code written for a Xilinx EDK project such as in CPE 329 For more information on interfacing with a specific SPI device see the section entitled Implementing SPI Devices in uClinux Adding the SPI IP Core to Xilinx EDK Please see the section entitled SPI IP Core in Alex s paper 3 for information about adding the SPI core in EDK Once added please also verify that the OPB_Clk signal is connected to the sys_clk_s net otherwise your SPI devices will not operate correctly To view all signal connections select the System Assembly View in EDK Change Filters at the top to Ports and then select Connection Filters gt All to the right of that Expand the port view of the 30 SPI module by click the plus sign next to the SPI device Check that the clock signal is correctly set up Once all bus port and address settings are connected correctly configure the SPI module for the number of devices you wish to use In the System Assembly View under the Ports filter right click on the SPI module and hit Configure IP to change the core s settings Change Total Number of Slave Select Bits in SS Vector to the number of SPI devices you plan on having connected
96. ux disant etat eese dat e 35 Implementing the Digital to Analog Converter DAC in uClinux 35 Implementing the Analog to Digital Converter ADC in uClinux 37 X Temes medi 47 AL v Kecom nend ationsz sszem ere ane dota 48 Custom U Boot Auto Configuration Script eeressreosnrosneasnensnnesnnrsnvnnsnesnnnssssnssasnnvassasenee 48 Upgrade Petalinux from SVN Build rai 48 Per Friendly SPL Interface nta des 49 PAL God dp 50 Appendix A Bibliography oet ener ane osv meae ea duc A ade ee tu e al 52 Appendix B SPIDEV Kernel Patch sens ess nine das 53 Appendix C Sample UCF File si id ena eR eae Ra nns 68 Appendix D SPI User Applications ns beetle 75 Appendix E Analysis of Senior Project Design 87 Summary of Functional Requirements ani Seta edet eqeri v e ee e rate Utd e ve e ape 87 Primary Constraints os peces an dale pe Pata AA NG 87 ECONO tail E EEEE E T E E EE E EE 87 Environmental and Sustainability sise near eine 88 Social and POolitical iia vo dixo Fa ete Dr UD 88 Developer A a e E EET E EAER 88 List of Figures Figure 1 Settings for the SPI device driver section of the uClinux kernel 32 Figure 2 Settings for the character device driver section of the uClinux kernel 33 Figure 3 A typical boot screen in Kermit showing the SPIDEV drive initialization 34 Figure 4 The DAC CLR external port configuration in Xi
97. ve solution is to use a Spartan 3E FPGA implemented on a Spartan 3E Starter Kit to read the sensor inputs and send out output signals to the MOSFET switches as well as the PWM output signal This would eliminate the need for the PIC and National Semiconductor devices currently in use on the SuPER system as well as reduce power consumption to less than 3W using the Spartan 3E FPGA To do so requires an operating system to be installed on the FPGA to operate the SuPER system For this project a variant of uClinux called Petalinux has been chosen to develop the user environment to operate the next phase of the SuPER project In their paper Brian and Patrick 2 discuss the installation and development of both development environment for Petalinux as well as configuration and installation of the Petalinux kernel on a Spartan 3E Starter Kit This paper provides an initial road map for starting to use uClinux on the Spartan 3E for the purposes of the SuPER project Once the Petalinux operating system was implemented on the starter kit board the next iteration of this project will focus on implementing the necessary devices in the Petalinux environment Several drivers are already available in Petalinux to access many of the devices that can be added to the Spartan 3E Start Kit in the Xilinx EDK such as General Purpose IO GPIO devices However to use this FPGA with the SuPER project a SPI driver is needed This driver would allow several important devices
98. vice i ilinx spi 56 _device i rupN petalinux svn orig software linux 2 6 x petalogix arch microblaze platform Xilinx Spartan3E500 RevD setup c petalinu Spartan3 peta petalogi peta petalog 03 02 11 7 4 x Nothing to do x svn so E500 Rev linux sv 16 06 0 22 45 0 7 76 D setup c n orig so 00000000 00000000 ftware linux 2 6 x petalogix arc ftware linux 2 6 x x arch microblaze platform Xi 01 14 10 0100 linux svn software linux 2 6 x ix arch microblaze platform Xi 0100 inx Spartan3E500 RevD setup c inx Spartan3E500 RevD setup c h microblaze platform Xilinx 2009 2009 but we need this C file to keep kbuild happy This is not true We are now registering SPI slaves here include lt linux device h gt include lt linux spi spi h gt static struct spi_board_info spi_board_info __initdata order of busses here has no influence on numbering first bus on EVM only 4 devices SPI flash on the Spartan EVM gt spi 0 modalias spidev max speed hz 1000000 bus num 0 chip select 0 dummy gt spi 1 modalias spidev max speed hz 1000000 bus num 0 chip select 1 dummy gt spi 2 modalias spidev

Senior Project Report - Cal Poly San Luis Obispo

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