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FMC122/FMC125/FMC126 User Manual

1. ei 17 eee e 20 EE EA ENEEIER 20 6 2 MONITO INO ETT TS 0E 20 63 COOLING re S 20 6 3 1 Convection oia DM UEM MU EEEE 20 6 3 2 p C dies 21 7 JSalely ec ee 21 BEING aes 21 MES 21 Appendix EDEL etnies 22 Appendix B HPC pin out FMC125 FMC122 eeeeeeeeeeeeeeeeeeenn nnns 24 Appendix G 26 28 Appendix D CPLD eect ects 31 www 4dsp com UM009 FMC12x User Manual Er r1 17 1 Acronyms and related documents 1 1 Acronyms ADC DDR _ DoubleDataRate FMC LED LSB Least Significant Bit s MGT MSB Most Significant Bit s PCB PLL Table 1 Glossary 1 2 Related Documents e FPGA Mezzanine Card FMC standard ANSI VITA 57 1 2008 e Datasheet AD9517 1 E2V e Datasheet EV8AQ160 E2V e Datasheet EV10AQ190 E2V Datasheet ADT7411 Rev B Analog Devices e Datasheet SC18IS602B Rev 04 NXP www 4dsp com
2. www 4dsp com 21 UM009 FMC12x User Manual Er r1 17 Appendix A LPC pin out FMC122 AV57 1 LPCPin FMC122 Signal AV57 1 LPCPin FMC122 Signal AV57 1 LPCPin FMC122 Signal CLKO_M2C_N H5 CLK FPGA N GBTCLKO_M2C_N DS GBTCLKO_N CLKO_M2C_P CLK TO FPGA P GBTCLKO 2 P D4 GBTCLKO_P CLK1_M2C_N G3 TRIGGER TO FPGA N CLK1 M2C P G2 TRIGGER TO FPGA P 1 00 N CC G7 ADR N LA17 N CC D21 BDR N DPO C2M N C3 DP C2M N lt 0 gt LAO P CC G6 ADR P LA17 P CC D20 BDR_P DPO C2M P C2 DP C2M P 0 LAO1 N CC D9 ALD N 0 LA18 N CC C23 BLD DPO 2 N C7 DP M2C N 0 LAO1 P CC D8 ALD P 0 LA18 P CC C22 BLD P 0 DPO M2C P C6 DP M2C P 0 LAO2 N H8 AHD_N lt O gt LA19 N H23 BHD N 0 LAO2 P H7 AHD _P lt 0 gt LA19_P H22 BHD P 0 LAO3 N G10 ALD N lt 1 gt LA20 G22 BLD N lt 1 gt LA03 P G9 ALD P 1 LA20 P G21 BLD P lt 1 gt LAO4_N H11 AHD N 1 LA21 N H26 BHD N lt 1 gt 404 P H10 AHD_P lt 1 gt LA21 P H25 BHD P lt 1 gt LAOS N D12 ALD N lt 2 gt LA22 N 625 BLD N lt 2 gt LA05 P D11 ALD_P lt 2 gt LA22 P G24 BLD P 2 LAO6 N c11 AHD N 2 LA23 N D24 BHD N 2 LAO6 P C10 AHD P lt 2 gt LA23 P D23 BHD P lt 2 gt LAO7 N H14 ALD N lt 3 gt LA24 N H29 BLD N 3 LAO7 P H13 ALD P 3 LA24 P H28 BLD P lt 3 gt LA08 N G13 AHD N lt 3 gt LA25
3. 11 N H17 N C HA11_N 113 N C HB11_N J31 N C 11 P H16 N C HA11_P 12 N C HB11 P 130 N C LA12 N 616 NC HA12 N F14 N C HB12 N F32 N C LA12 P 615 NC HA12 P F13 N C HB12 P F31 N C LA13 N D18 N C HA13_N E13 N C HB13_N E31 N C LA13_P D17 N C HA13_P E12 N C HB13_P E30 N C LA14_N C19 NC HA14 N 16 N C HB14 N K35 N C LA14 P C18 NC HA14 P 115 N C HB14 P K34 N C LA15 N H20 N C HA15 N F17 N C HB15 N J34 N C LA15_P H19 N C HA15 P F16 N C HB15 P 133 N C LA16 N G19 N C HA16_N E16 N C HB16 N F35 N C LA16 P G18 NC HA16 P E15 N C HB16 P F34 N C LA17 N CC D21 BDR N HA17 N CC K17 CORN HB17_N_CC K38 DOR_N LA17_P_CC D20 BDR_P HA17_P_CC K16 CORP HB17_P_CC K37 DOR_P LA18_N_CC C23 BD N O HA18 N 119 N C HB18 N 137 N C LA18 P CC C22 BD_P lt 0 gt HA18 P 18 N C HB18 P 136 N C LA19 N H23 BD N lt 1 gt HA19 N F20 AORN HB19 N E34 FMC_TO_CPLD lt 3 gt LA19 P H22 BD P lt 1 gt HA19 P F19 AORP HB19 P E33 FMC CPLD 2 LA20 N G22 BD N22 HA20 N E19 N C HB20 N F38 FRONT IO FMC lt 1 gt UM009 www 4dsp com 28 UM009 FMC12x User Manual Lp Er LA20 P G21 BD P 2 HA20 P E18 N C HB20 P F37 FRONT IO FMC 0 LA21 N H26 BD N 3 HA21 N 20 B
4. 3 7 P 27 DLD_P lt 3 gt LA08 N G13 AHD N lt 3 gt HAO8 N F11 CHD N lt 3 gt HBO8 N F29 DHD_N lt 3 gt LA08 P G12 AHD P lt 3 gt P F10 CHD_P lt 3 gt HBO8_P F28 DHD_P lt 3 gt 09 D15 ALD_N lt 6 gt N E10 CLD_N lt 6 gt HBO9 N E28 DLD_N lt 6 gt LAO9 P D14 ALD P 6 HAO9 P 9 CLD_P lt 6 gt HBO9_P E27 DLD_P lt 6 gt LA10 N C15 ALD N lt 7 gt HA10 N K14 CLD N lt 7 gt HB10 N K32 DLD_N lt 7 gt LA10 P c14 ALD P lt 7 gt HA10 P K13 CLD_P lt 7 gt HB10 P K31 DLD_P lt 7 gt 11 N H17 ALD N lt 4 gt HA11_N 113 CLD_N lt 4 gt HB11_N 131 DLD_N lt 4 gt 11 P H16 ALD P lt 4 gt 1 P 12 CLD P lt 4 gt HB11 P 130 DLD_P lt 4 gt LA12 N G16 AHD N lt 4 gt HA12 N F14 CHD N lt 4 gt HB12 N F32 N 4 LA12 P G15 AHD P 4 HA12 P F13 CHD_P lt 4 gt HB12_P F31 DHD_P lt 4 gt LA13 N D18 ALD HA13 N E13 CLD N lt 5 gt HB13 N E31 DLD N 5 LA13 P D17 ALD P 5 HA13 P E12 CLD P lt 5 gt HB13 P E30 DLD_P lt 5 gt LA14 N C19 AHD_N lt 5 gt HA14 N 16 CHD_N lt 5 gt HB14_N K35 DHD N 5 LA14 P C18 AHD P 5 HA14 P 115 CHD P lt 5 gt HB14 P K34 DHD P lt 5 gt LA15 N H20 AHD N lt 6 gt HA15 N F17 CHD N 6 HB15 N J34 DHD_N lt 6 gt LA15_P H19 AHD_P lt 6 gt HA15_P F16 CHD_P lt 6 gt HB15_P J33 DHD_P lt 6 gt LA16_N G19 AHD_N lt 7 gt HA16_N E16 CHD_N lt 7 gt HB16_N F35 DHD_N lt 7 gt LA16_P G18 AHD_P lt 7 gt HA16_P E15 CHD_P lt 7 gt HB16_P F34 DHD_P lt 7
5. 3 DP1 C2M P A22 DP_C2M_P lt 1 gt DP1 M2C P A2 DP M2C P 1 LA26 N D27 BLD N 6 DP2 C2M N A27 DP C2M N 2 DP2 M2C N A7 DP M2C N 2 LA26 P D26 BLD P 6 DP2 C2M P A26 DP_C2M_P lt 2 gt DP2_M2C_P A6 DP_M2C_P lt 2 gt LA27_N C27 BLD N 7 DP3 CM N A31 DP C2M N 3 DP3 M2C N A11 DP M2C N 3 LA27 P C26 BLD P 7 DP3 C2M P A30 DP C2M P 3 DP3 M2C P A10 DP M2C P 3 LA28 N H32 BLD N 4 DP4 C2M N A35 DP C2M N 4 DP4 M2C N A15 DP M2C N lt 4 gt LA28 P H31 BLD P lt 4 gt DP4 C2M P A34 DP C2M P lt 4 gt DP4 M2C P A14 DP_M2C_P lt 4 gt LA29_N G31 BHD_N lt 4 gt DP5_C2M_N A39 DP_C2M_N lt 5 gt DP5_M2C_N A19 DP_M2C_N lt 5 gt LA29_P G30 BHD_P lt 4 gt DP5 C2M P A38 DP C2M P 5 DP5 M2C P A18 DP M2C P 5 LA30 N H35 BLD N 5 DP6 C2M N B37 DP C2M N 6 DP6 M2C N B17 DP M2C N 6 LA30 P H34 BLD P 5 DP6 C2M P B36 DP C2M P 6 DP6 M2C P B16 DP M2C P 6 LA31 N G34 N 5 DP7 C2M N B33 DP_C2M_N lt 7 gt DP7_M2C_N B13 DP_M2C_N lt 7 gt LA31 P G33 BHD P 5 DP7 C2M P B32 DP_C2M_P lt 7 gt DP7 M2C P B12 DP M2C P 7 LA32 N H38 BHD N 6 DP8 C2M N B29 DP C2M N 8 DP8 M2C N B9 DP M2C N 8 LA32 P H37 BHD P 6 DP8 C2M P B28 DP C2M P 8 DP8 M2C P B8 DP M2C P 8 LA33 N G37 BHD N 7 DP9 CM N B25 DP C2M N 9 DP9 M2C N B5 DP M2C N 9 LA33 P G36 BHD_P lt 7 gt DP9_C2M_P B24 DP_C2M_P lt 9 gt DP9 M2C P B4 DP_M2C_P lt 9 gt Table 10 FMC125 FMC122 signal description Signal Group Direction VO Description Standard
6. ADR_N AIDA Output LVDS Digital data clock from ADR_P ADC The ADC can operate in mux mode using data port L ow and data port H igh ALD N 7 0 A D A Output LVDS Data port L ow data is ALD P 7 0 valid on both edges of the clock DDR ALOR N A D A Output LVDS Over range bit ALOR P synchronous to the samples present on port L ow AHD N 7 0 A D A Output LVDS Data port H igh data is AHD_P lt 7 0 gt valid on both edges of the clock DDR AHOR_N AIDA Output LVDS Over range bit AHOR_P synchronous to the UMO009 www 4dsp com 25 r1 17 UM009 FMC12x User Manual samples present on port H igh BDR_N A DB Output LVDS Digital data clock from BDR_P ADC The ADC can operate in mux mode using data port L ow and data port H igh BLD_N lt 7 0 gt A D B Output LVDS Data port L ow data is BLD P lt 7 0 gt valid on both edges of the clock DDR BLOR N A D B Output LVDS Over range bit BLOR P synchronous to the samples present on port L ow BHD N 7 0 A D B Output LVDS Data port H igh data is BHD P 7 0 valid on both edges of the clock DDR BHOR N A D B Output LVDS Over range bit BHOR P synchronous to the samples present on port H igh CDR_N A D C Output LVDS Digital data clock from CDR P ADC The ADC can operate in mux mode using data port L ow and data port H igh CLD_N lt 7 0 gt A D
7. LA31 P G33 N C DP7 C2M P B32 DP_C2M_P lt 7 gt DP7 M2C P B12 DP M2C P 7 LA32 N H38 N C DP8 C2M N B29 DP C2M N 8 DP8 M2C N B9 DP M2C N 8 LA32 P H37 N C DP8 C2M P B28 DP C2M P lt 8 gt DP8 M2C P B8 DP M2C P lt 8 gt LA33 N G37 N C DP9_C2M_N B25 DP_C2M_N lt 9 gt DP9_M2C_N BS DP_M2C_N lt 9 gt LA33 P G36 N C DP9 C2M P B24 DP C2M P 9 DP9 M2C P B4 DP_M2C_P lt 9 gt Table 11 FMC126 signal description Signal Group Direction 1 0 Description standard ADR_N A D A Output LVDS Digital data clock from ADR_P ADC AD_N lt 9 0 gt A D A Output LVDS Data port data is valid on AD_P lt 9 0 gt both edges of the clock DDR AOR_N A D A Output LVDS Over range bit AOR_P synchronous to the samples present on data port BDR_N A D B Output LVDS Digital data clock from BDR_P ADC BD_N lt 9 0 gt A D B Output LVDS Data port data is valid on BD_P lt 9 0 gt both edges of the clock DDR BOR_N A D B Output LVDS Over range bit BOR_P synchronous to the UM009 www 4dsp com 29 r1 17 UM009 FMC12x User Manual samples present on data port CDR N A D C Output LVDS Digital data clock from CDR P ADC CD 9 0 A D C Output LVDS Data port data is valid on CD P 9 0 both edges of the clock DDR COR N A D C Output LVDS Over range bit COR P synchronous to the samples present on data port DDR
8. eeeeeeeeeeeeeeeeeeeeeeeennnnnnnnn nnne nnn 4 1 gui ctm 4 1 2 Related Documents bud eii Ces a sees 4 2 General 65 5 ee ner en eer 7 3 1 Requirements and handling instructions eesssseseseeeeeeeee 7 3 2 LVDS requirements eroe rx t cr e 7 08 preme 8 4 1 Phycisal specifications OUT 8 4 1 1 Board Dimensions sssssereerrer 8 4 1 2 OUI Ae 8 4 1 3 Front panel HDMI EO iub Er rite ene teint ame 9 LT MEME T 10 nar NS 10 SEE JAG 10 42 3 FPMO Onn 10 424 Main characteristies TEE 10 4 3 Analog input channels sees renerne 12 4 4 External clock input re nessen nnenn nenene 12 4 5 External trigger sync a incu 12 AO AGNI crece 12 4 7 Multi Gigabit Transceivers Optional ssseee 13 48 Power SUPP rrr 15 49 SEE P M DM 17 5 Controlling the
9. inverted INT is not asserted INT is asserted access to the ADT7411 trough the 120 bus is required to determine the source of the interrupt Logic function NOT REFMON AND LD AND STATUS AND INT All status signals indicate OK One or more status signals indicate ERROR Table 17 Register CPLD REG2 description read Reserved LED SEL Table 18 Register CPLD REG2 definition write www 4dsp com 32 UM009 FMC12x User Manual Er r1 17 Writing to this register determines which status signal is reflected on the LED XXXX1 REFMON XXX10 LD XX100 STATUS VM IRQ Table 19 Register CPLD_REG2 description write X1000 71000907 www 4dsp com 33
10. 1 15 A 2 3W r1 17 Table 5 FMC standard power specification The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC12x card to minimize the effect of power supply noise on clock generation and data conversion Clean analog supply 3 3V is derived from 12V in two steps for maximum efficiency The first step uses a highly efficient switched regulator to generate a 3 8V power rail From this power rail the analog supply is derived with a low dropout low noise high PSRR linear regulator There is additional noise filtering at several stages in the power supply The regulators have sufficient copper area to dissipate the heat in combination with proper airflow see section 6 3 Cooling Power plane Typical Maximum VADJ 665mA 685mA 3P3V 50mA 95mA 12POV 900mA 920mA 3P3VAUX Operating 0 1 mA 3 mA 3P3VAUX Standby 0 01 UA 1 yA Table 6a Typical Maximum current drawn from FMC12X revision 1 Power plane Typical Maximum VADJ 25mA 25mA 3P3V 540mA 610mA 12P0V 900mA 920mA 3P3VAUX Operating 0 1 mA 3 mA 3P3VAUX Standby 0 01 UA 1 HA Table 6b Typical Maximum current drawn from FMC12X revision 2 The total power consumption 13W www 4dsp com 16 UM009 FMC12x User Manual ft Er r1 17 4 9 DIP Switches The DIP Switches should be in the state as indicated in the following table Any other
11. 4 UM009 FMC12x User Manual Er r1 17 2 General description The FMC125 FMC126 is a four channel 1 25Gsps ADC FMC daughter card The card provides four 8 bit FMC125 or 10 bit FMC126 ADC channels that enable simultaneous sampling of four two or one channel at a maximum sample rate of 1 25Gsps 2 5Gsps or 5Gsps respectively The FMC122 is a low pin count variant supporting 2 channels at 1 25Gsps or 1 channel at 2 5Gsps maximum sample rate The sample clock can be supplied externally through a coax connection or supplied by an internal clock source optionally locked to an external reference The clock tree enables cascading of multiple boards for phase locked sampling Additionally a trigger input for customized sampling control is available The FMC12x daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The card has a high pin count connector front panel I O and can be used in a conduction cooled environment The design is based on E2V s 8 bit EV8AQ160 FMC122 FMC125 or 10 bit EV10AQ190 FMC126 Quad 1 25Gsps ADC with DDR LVDS outputs The analog signal inputs are available on the front panel on coax connections and have individual calibration circuits for fine tuning of gain offset and phase The FMC12x allows flexible control on clock source sampling frequency and calibration through serial IC communication Furthermore the card is equipped with power supply and temperature monitoring
12. Manual Er r1 17 4 2 Electrical specifications The FMC12X uses high speed LVDS outputs Revision 1 boards require 2 5V on VADJ power supply supplied by the carrier card Revision 2 boards can operate with a VADJ voltage range of 1 65V to 3 3V but typically VADJ will be 1 8V or 2 5V for LVDS operation The voltage on VIO B pins will be at the same level as VADJ as it is connected directly to VADJ on the FMC12X The data converters operate in LVDS mode clock and data pairs All other status and control signals like serial communication busses operate at LVCMOS level Vou VADJ 4 2 1 EEPROM The FMC12X card carries a 2Kbit EEPROM which is accessible from the carrier card through the PC bus The EEPROM is powered by 3P3VAUX The standby current is only 0 01 when SCL and SDA are kept 3P3VAUX level These signals may also be left floating since pull up resistors are present on the card 4 2 2 JTAG The CPLD device is included in the JTAG chain accessible from the FMC connection The user should NOT reprogram or erase the CPLD 4 2 3 FMC Connector The high pin count connector has four dedicated LVDS clock pairs and can host up to 80 LVDS data pairs of which some are defined as clock capable The 80 pairs are divided into three banks Bank LA with 34 pairs of which four are clock capable Bank HA with 24 pairs of which three are clock capable Bank HB with 22 pairs of which three are clock capable The l
13. N A DD Output LVDS Digital data clock from DDR P ADC DD N 9 0 A D D Output LVDS Data port data is valid on DD P lt 9 0 gt both edges of the clock DDR DOR N A D D Output LVDS Over range bit DOR P synchronous to the samples present on data port CLK TO FPGA N MONITOR Output LVDS Spare clock signal from CLK TO FPGA P the clock tree Can be used to monitor onboard external clock TRIGGER TO FPGA N I O Output LVDS Representation of the TRIGGER TO FPGA P signal connected to the external trigger input FRONT 1O 3 0 I O Bidir CMOS VADJ Connected to the transceivers on the HDMI connector Table 2 The direction of the transceivers is controlled through a CPLD register DP M2C P N 1 0 O Output CML ECL Gigabit transceiver from HDMI connector DP_C2M_P N lt 3 2 gt Input CML ECL Gigabit transceiver to HDMI connector SYNC FROM FPGA N CONTROL Input LVDS Signal used to apply a SYNC FROM FPGA P sync pulse to both ADC in order to align the digital outputs on sample basis FMC TO CPLD 3 0 CONTROL Bidir CMOS VADJ Reserved I2C_SCL CONTROL Input LVTTL 3 3V I2C Clock The I2C bus is the main control bus 20 SDA CONTROL Bidir LVTTL 3 3V I2C Data The 20 bus is the main control bus UMO09 www 4dsp com 30 UM009 FMC12x User Manual Er r1 17 Appendix D CPLD Register map 0 ADCR CLKR SYNCSRC CLKSRC Table 12 Register CPLD_REGO definition Selection
14. N G28 BHD_N lt 3 gt LAOB P G12 AHD P lt 3 gt LA25 P G27 BHD P lt 3 gt LA09 N D15 ALD_N lt 6 gt LA26 N D27 BLD N 6 LAO9 P D14 ALD P 6 LA26 P D26 BLD P 6 LA10 N C15 ALD N lt 7 gt LA27 N C27 BLD N lt 7 gt LA10 P c14 ALD P lt 7 gt LA27 P C26 BLD P lt 7 gt 11 N H17 ALD N lt 4 gt LA28 N H32 BLD N lt 4 gt 11 P H16 ALD P lt 4 gt LA28 P H31 BLD P 4 LA12 N G16 AHD_N lt 4 gt LA29 N G31 BHD N 4 LA12 P G15 AHD P 4 LA29 P G30 BHD_P lt 4 gt LA13 N D18 ALD LA30 N H35 BLD LA13 P D17 ALD P 5 LA30 P H34 BLD P 5 LA14 N C19 AHD LA31 N 634 BHD N 5 LA14 P C18 AHD P 5 LA31 P G33 BHD P lt 5 gt LA15 N H20 N 6 LA32 N H38 BHD N 6 15 P H19 AHD P 6 LA32 P H37 BHD_P lt 6 gt LA16 N G19 AHD_N lt 7 gt LA33 N 637 BHD_N lt 7 gt SCL C30 12C SCL LA16 P G18 AHD P lt 7 gt LA33 P G36 BHD P lt 7 gt SDA C31 I2C SDA www 4dsp com 22 UM009 FMC12x User Manual DSP Table 9 FMC122 signal description Signal Group Direction y o Description Standard ADR N A DA Output LVDS Digital data clock from ADR P ADC The ADC can operate in mux mode using data port L ow and data port H igh ALD N 7 0 A D A Output LVDS Data port L ow dat
15. and offers several power down modes to switch off unused functions or protect the card from overheating Board LVTTL 4 Monitoring EEPROM fia ey 1 Clock Reference Clock Sync al Tree 95 zea9 9 11 29 Control LVDS Sync 1 Sigi LVDS Clock 1 Ess Trigger er LVDS Trigger 1 8 Sync E LVDS Overrange 4 hn RE J A Q LVDS Clock 1 LVDS Data 10 z I i E 1 E 3 LVDS Clock 1 B LVDS Data 10 1 23 esa 5 LVDS Clock 1 9 Q ig LVDS Data 10 33 8 LVDS Clock 1 as D 82 LVDS Data 10 MESE MESE I REE Figure 1 FMC126 block diagram UMO009 www 4dsp com 5 UM009 FMC12x User Manual Er r1 17 MGT 4 EEPROM LVTTL 4 Toe ad Oe I Clock _ EO Reference Clock Sync Contro Tree TT o Status se 4i D amp Bs 9 l Control LVDS Sync 1 5 ag LVDS Clock 1 38 Trigger ey LVDS Trigger 1 l aE Sync p LVDS Overrange 4 p 7 LVDS Clock 1 A LVDS Data 2x8 X LVDS Clock 1 EY B 9 LVDS Data 2x8 2 5 eq 3 LVDS Clock 1 35 i LVDS Data 2x8 228 LVDS Clock 1 2 i D gt Q 8 LVDS Data 2x8
16. configuration might affect the analog conversion performance FMC122 FMC125 FMC126 Table 6 Default DIP Switch state 5 Controlling the FMC12x The FMC12x is fully controlled from the carrier hardware through a single IC communication bus Three devices are connected refer to Table 7 The device addresses depend on the global address pins defined by the FMC standard GAO GA1 Note that the ADT7411 uses only GAO Device Description I C Address 24LC02B 2K PC Serial EEPROM 1 0 1 0 0 GA1 GAO SC18IS602B C bus to SPI bridge 0 1 0 1 0 GA1 GAO ADT7411 Digital Temperature Sensor and A D 1 0 O 1 0 GAO GAO Table 7 C devices The I C bus to SPI bridge SC18IS602B supports four SPI slaves The following slaves are assigned 580 AD9517 SS1 A D device SS2 SS3 CPLD 5544 24 0028 ADT7411 SC181S602B N CS N CS N CS AD9517 ADC CPLD Figure 10 PC SPI architecture www 4dsp com 17 UM009 FMC12x User Manual Lp Er r1 17 The CPLD has the following tasks Select clock source based on a SPI command CLKSRC SEL Select sync source based on a SPI command SYNCSRC SEL Generate SPI reset for AD9517 CLK N RESET a
17. may be connecter to either one of the four inputs A B C or D On the FMC122 a maximum of two analog inputs A and B can be sampled simultaneously 4 4 External clock input The actual sampling clock Fs can be derived from the external clock input as follows 4 channel mode Fs 2 Fs max 1 25Gsps 2 channel mode Fs Fexr Fs max 2 50Gsps 1 channel mode Fs Fexrx 2 Fs max 5 00Gsps 4 5 External trigger sync input The external trigger input can be configured in different ways build options The trigger input can be 50Q terminated accepting most common high speed signalling standards like single ended LVPECL By default the 500 termination is not mounted in order to support LVTTL LVCMOS and similar input standards Differential input is also possible using the coax shield as inverted signal By default the input is single ended DC coupled with an impedance of approximately 2 5kO The input threshold is approximately 1 25V Optionally the trigger input can be used as sync input synchronizing local A D converters or multiple FMC12x cards to FMC TRIGGER Any Level to LVDS 1 2 Fanout SYNC FROM FPGA P N From Clock Tree i SYNCSRC SEL 1 0 Figure 6 A D Synchronization topology 4 6 Clock Tree The FMC12x offers a clock architecture that combines flexibility and high performance Components have been chosen in order to minimize jitter and phase noise to reduce degradation of the da
18. of clock source External clock Internal clock External Reference Internal clock Internal Reference Do not use Selection of synchronisation source External Trigger Carrier trough SYNC FROM FPGA P N Clock Tree No Sync Clock tree SPI reset Normal operation Reset resetting the clock tree is normally not required This bit is not self clearing A D device SPI reset Normal operation Reset resetting the A D device is normally not required This bit is not self clearing Table 13 Register CPLD REGO description Rsvd FAN1 FANO DIR3 DIR2 DIR1 DIRO Table 14 Register CPLD REG1 definition www 4dsp com 31 UM009 FMC12x User Manual Er r1 17 Direction of Front IO transceiver x 0 to 3 Signal x is input FMC12X is receiver Signal x is output FMC12X is transmitter Power control for FAN header x 0 to 1 Apply power to FAN header x Cut power to FAN header x Table 15 Register CPLD REG1 description Reserved IRQ VM STATUS LD REFMON Table 16 Register CPLD REG2 definition read Reflect the status of the REFMON output of the AD9517 Reflect the status of the LD output of the AD9517 Reflect the status of the STATUS output of the AD9517 Reflect the status of the INT output of the ADT7411
19. tree It is recommended that the carrier card and or host software uses the power down features of the Quad ADC and the clock tree if the temperature is too high Normal operations can resume once the temperature is within the operating conditions boundaries Parameter Device 1 Formula On chip temperature ADT7411 Die Temperature On chip AINO Vpp 3 3V ADC Die Temperature External temperature External AIN3 VADJ AIN3 External AIN4 2 5V Analog AIN4 External AIN5 3 3V Digital AIN5 2 External AIN6 3 3V Analog 2 External AIN7 VCP AIN7 2 External AIN8 1 8V Digital AIN8 Table 8 Temperature and voltage parameters 6 3 Cooling Two different types of cooling are available for the FMC12x 6 3 1 Convection cooling The air flow provided by the fans of the chassis the FMC12x is enclosed in will dissipate the heat generated by the onboard components A minimum airflow of 300 LFM is recommended Optionally a low profile heat sink fan can be glued on top of the Quad ADC The card has a fan power connection that can be switch on and off under carrier card control The FAN power voltage is 3 3V and can be switched on and off through a CPLD register refer to Table 14 For standalone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed
20. 50 AC coupled 10 100 MHz reference clock Frequency range 400 2500 MHz sample clock External Clock Output optional Output level AdBm to EO C Output waveform Square AC coupled 000000000 AC coupled External Trigger Sync input Input threshold level 1 25V typical LVTTL level supported Input impedance 2 5kO DC coupled EUM Frequency range Up to 625 MHz ADC Output LVDS 1 2 8x 8 pairs DDR FMC122 FMC125 LVDS 1 1 4x 10 pairs DDR FMC126 Data Format Offset binary FMC connector type HPC ASP 134488 01 200 1250 MHz 4 channel mode Sampling Frequency Range 400 2500 2 channel mode 800 5000 MHz 1 channel mode Internal Clock Reference 100 MHz reference clock 2500MHz sample clock enables full speed sampling in 4 2 and 1 Frequency Range channel mode Optionally the onboard VCXO clock 2500MHz can be divided down to allow lower sampling frequencies Divider factors are 2 3 4 5 and 6 Output data width UMO009 www 4dsp com 11 UM009 FMC12x User Manual Er r1 17 Table 3 FMC12x daughter card main characteristics 4 3 Analog input channels The FMC125 FMC126 has four analog inputs which are AC coupled to the Quad ADC There is a flexible analog input switch enabling 4 2 and 1 channel mode In two channel mode one input connects to either input A or B The other input connects to either input C or D In one channel mode the analog signal
21. A01 N CC D9 AD N 0 HAO1 N CC E3 CD N 0 N 125 DD N lt 0 gt LAO1 P CC D8 AD P 0 HAO1 P CC E2 CD 0 P 124 DD P 0 LAO2 N H8 AD N 1 HAO2_N K8 CD N lt 1 gt HBO2 F23 DD N lt 1 gt LA02 P H7 AD P lt 1 gt HAO2 P K7 CD P lt 1 gt HBO2 P F22 DD P lt 1 gt LA03 N G10 AD N lt 2 gt 3 N 17 CD N lt 2 gt HBO3 N E22 DD N lt 2 gt LA03 P G9 AD P 2 HAO3 P J6 CD P 2 P E21 DD P 2 LAO4_N H11 AD N lt 3 gt HAO4_N F8 CD N 3 HBO4 N F26 DD N 3 404 P H10 AD P 3 P F7 CD P 3 P F25 DD P 3 LAOS N D12 AD N 4 5 N 7 CD N lt 4 gt HBO5 N E25 DD N 4 405 P D11 AD P 4 5 P E6 CD_P lt 4 gt HBO5 P E24 DD P lt 4 gt LA06 N c11 AD N lt 5 gt HAO6_N Kil 1 CD N lt 5 gt HBO6 N CC 29 DD N lt 5 gt LA06 P C10 AD P lt 5 gt 06 P K10 CD P lt 5 gt HBO6 P CC K28 DD P lt 5 gt LAO7 H14 AD N lt 6 gt HAO7 110 CD N lt 6 gt HBO7_N J28 DD N lt 6 gt LAO7 P H13 AD P 6 7 P J9 CD P 6 7 P 27 DD 6 LA08 N G13 AD N lt 7 gt HAO8 N Fil CD N lt 7 gt HBO8 N F29 DD N lt 7 gt LA08 P G12 AD P lt 7 gt P F10 CD P lt 7 gt HBO8 P F28 DD P 7 LAO9 N D15 AD N 8 N E10 CD N lt 8 gt HBO9 N E28 DD N lt 8 gt LAO9 P D14 AD P 8 HAO9 P 9 CD P 8 P E27 DD P 8 LA10 N C15 AD N 9 HA10 N k14 CD N 9 HB10 N K32 DD N 9 LA10 P 614 AD P 9 HA10 P K13 CD P 9 HB10 P K31 DD P 9
22. C Output LVDS Data port L ow data is CLD_P lt 7 0 gt valid on both edges of the clock DDR CLOR_N A D C Output LVDS Over range bit CLOR P synchronous to the samples present on port L ow CHD N 7 0 A D C Output LVDS Data port H igh data is CHD_P lt 7 0 gt valid on both edges of the clock DDR CHOR_N A D C Output LVDS Over range bit CHOR P synchronous to the samples present on port H igh DDR N A D D Output LVDS Digital data clock from DDR P ADC The ADC can operate in mux mode using data port L ow and data port H igh DLD N 7 0 A D D Output LVDS Data port L ow data is DLD P lt 7 0 gt valid on both edges of the clock DDR DLOR N A D D Output LVDS Over range bit DLOR P synchronous to the UMO009 www 4dsp com 26 UM009 FMC12x User Manual samples present on port L ow DHD_N lt 7 0 gt A D D Output LVDS Data port H igh data is DHD P lt 7 0 gt valid on both edges of the clock DDR DHOR N A D D Output LVDS Over range bit DHOR P synchronous to the samples present on port H igh CLK_TO_FPGA_N MONITOR Output LVDS Spare clock signal from CLK_TO_FPGA_P the clock tree Can be used to monitor onboard external clock TRIGGER TO FPGA N I O Output LVDS Representation of the TRIGGER TO FPGA P signal connected to the external trigger input FRONT 1O 3 0 I O Bidir CMOS VADJ Connected to the transc
23. I Ss Figure 2 FMC125 block diagram MGT 1 MGT 1 e Clock Q Reference Clock Sync Tree Status amp Control LVDS Clock 1 Trigger LVDS Trigger 1 Sync LVDS Clock 1 LVDS Data 2x8 LVDS Clock 1 LVDS Data 2x8 Figure 3 FMC122 block diagram www 4dsp com 6 UM009 FMC12x User Manual Er r1 17 3 Installation 3 1 Requirements and handling instructions The FMC12x daughter card must be installed on a carrier card compliant to the FMC standard The FMC carrier card must support the high pin count connector 400 pins for FMC125 FMC126 and may be installed on a low pin count connector for FMC122 The carrier card must support VADJ VIO B voltage of 2 5V LVDS support for FMC12X revision 1 The carrier card can support VADJ VIO B voltage range of 1 65V to 3 3V for FMC12X revision 2 but typically VADJ will be 1 8V or 2 5V for LVDS operation Do not flex the board and prevent electrostatic discharges by observing ESD precautions when handling the card 3 2 LVDS requirements The FMC12x features parallel DDR LVDS outputs The FMC122 FMC125 has a 1 2 DMUX feature In 1 2 DMUX mode eight 8 bit LVDS busses run at a maximum of 625Mbps each The FMC126 does not offer a DMUX mode and has four 10 bit busses running at a maximum of 1 25Gbps each The FMC12x can output a training pattern on the LVDS outputs
24. ND RX3_N 24 23 RX6 N GND TX6N 24 25 GND GND GND 26 25 GND GND GND 26 27 TX4_P GND RX4 P 28 27 RX5 P GND TX5 P 28 29 TXA N GND RX4 N 30 29 RX5_N GND TX5 N 30 31 GND GND GND 32 31 GND GND GND 32 33 100 GND 34 33 102 GND 34 35 101 GND 36 35 103 GND 36 37 GND GND GND 38 37 GND GND GND 38 Table 4 MGT connector pinout A low phase noise 125MHz XTAL is used as reference clock A 1 2 LVDS fan out buffer is used to feed to reference clock to both connections on the FMC connector The pairs marked with connects to either the MICTOR header or the HDMI connector The assembly is determined with resistors A maximum of four pairs can connect to the HDMI connector Contact 4DSP for custom configurations NOTE These connectors will breach the FMC specification and are therefore a build option Please contact the factory for more information N B These connectors are not available on the FMC12X revision 2 4 8 Power supply Power is supplied to the FMC12x card through the FMC connector The pin current rating is 2 7A but the overall maximum as specified by the FMC standard is limited according to Table 5 2 Signals IO 0 3 connects to the CPLD and has no defined function yet www 4dsp com 15 UM009 FMC12x User Manual LE Voltage pins Max Amps Max Watt 3 3V 4 3A 10 W 12V 2 1A 12 W VADJ 2 5V 4 4A 10 W VIO B 2 5V 2
25. OR N HB21 N E37 FRONT FMC 3 LA21 P H25 BD P 3 HA21 P K19 BOR P HB21 P E36 FRONT FMC 2 LA22 N G25 BD N 4 HA22 N J22 N C LA22_P G24 BD_P lt 4 gt HA22_P 23 N C LA23 N D24 BD N 5 HA23 N K23 FMC TO CPLD 1 SCL C30 126 SCL LA23 P D23 BD P 5 HA23 P K22 FMC TO CPLD 0 SDA C31 I2C SDA LA24 N H29 BD N 6 DPO C2M N C3 DP C2M N 0 DPO M2C N C7 DP M2C N 0 LA24 P H28 BD P 6 DPO C2M P C2 DP C2M P 0 DPO M2C P C6 DP M2C P 0 LA25 N G28 BD N 7 DP1 COM N A23 DP C2M N 1 DP1 M2C N A3 DP M2C N 1 LA25 P G27 BD P 7 DP1 C2M P A22 DP_C2M_P lt 1 gt DP1 M2C P A2 DP M2C P 1 LA26 N D27 BD N 8 DP2 C2M N A27 DP C2M N 2 DP2 M2C N A7 DP M2C N 2 LA26 P D26 BD P 8 DP2 C2M P A26 DP_C2M_P lt 2 gt DP2_M2C_P A6 DP_M2C_P lt 2 gt LA27_N 27 BD N 9 DP3 CM N A31 DP C2M N 3 DP3 M2C N A11 DP M2C N 3 LA27 P C26 BD P 9 DP3 C2M P A30 DP C2M P 3 DP3 M2C P A10 DP M2C P 3 LA28 N H32 N C DP4 C2M N A35 DP C2M N 4 DP4 M2C N A15 DP M2C N lt 4 gt LA28 P H31 N C DP4 C2M P A34 DP C2M P lt 4 gt DP4 M2C P A14 DP_M2C_P lt 4 gt LA29_N G31 N C DP5_C2M_N A39 DP C2M N 5 DP5 M2C N A19 DP M2C N 5 LA29 P G30 N C DP5 C2M P A38 DP C2M P 5 DP5 M2C P A18 DP M2C P 5 LA30 N H35 N C DP6 C2M N B37 DP C2M N 6 DP6 M2C N B17 DP M2C N 6 LA30 P H34 N C DP6 C2M P 836 DP C2M P 6 DP6 M2C P B16 DP M2C P 6 LA31 G34 N C DP7 C2M N B33 DP_C2M_N lt 7 gt DP7_M2C_N B13 DP_M2C_N lt 7 gt
26. P M2C N lt 0 gt 18 N C 4 DP M2C P I 17 N C 5 Shield 16 FRONT lO 1 6 DP M2C N lI 15 FRONT 05 7 DP C2M P lt 2 gt 14 FRONT 10 lt 3 gt 8 Shield 13 FRONT lO 2 9 DP C2M N lt 2 gt 12 DP C2M N lt 3 gt 10 DP C2M P lt 3 gt 11 Shield Table 2 HDMI connector pin out 4 1 3 1 Multi gigabit transceivers Two Tx pairs and two Rx pairs of multi gigabit transceivers connect directly from the HDMI connector to the FMC connector Refer to Table 2 for the pin locations on the HDMI connector The signal names match with AV57 1 DP M2C P NO and DP M2C P N1 are mezzanine to carrier pairs and are inputs on the HDMI connector DP C2M P N2 and DP C2M P NS are carrier to mezzanine pairs and are outputs of the HDMI connector Note the DP C2M P N pairs start with pair number 2 instead of 0 By default the FMC122 LPC only supports the DP M2C P NO pair The transceivers are DC coupled contact 4DSP for other configurations 4 1 3 2 Front I O LVTTL TTL A voltage translator is used for the LV TTL signals available on the front panel The front side is either 3 3V for LVTTL default or 5 0V for TTL build option These inputs are 5V tolerant when powered with 3 3V One side of the voltage translator connects to the front I O signals the other side connects directly to the FMC connector with levels that operate at VADJ The direction of each front I O signal is controlled by the CPLD www 4dsp com 9 UM009 FMC12x User
27. S GBTCLKO_N CLKO_M2C_P CLK FPGA P CLK2 BIDIR SYNC FROM FPGA P GBTCLKO M2C P D4 GBTCLKO_P CLK1_M2C_N G3 TRIGGER FPGA N CLK3 BIDIR N J3 N C GBTCLK1_M2C_N B21 GBTCLK1_N CLK1 M2C P G2 TRIGGER TO FPGA P CLK3 BIDIR P 12 N C GBTCLK1 M2C P B20 GBTCLK1_P 1 00 G7 ADR N N CC F5 CDR N HBOO N CC K26 DDR N LAO P CC G6 ADR P HAO0 P CC F4 CDR_P HBOO CC K25 DDR P LA01 N CC D9 ALD N 0 HAO1 N CC E3 CLD N 0 N 125 DLD N 0 LAO1 P CC D8 ALD P 0 HAO1 P CC E2 CLD P 0 P 124 DLD_P lt 0 gt LA02_N H8 AHD_N lt 0 gt HAO2_N K8 CHD N 0 HBO2 F23 DHD N 0 LAO2 P H7 AHD _P lt 0 gt HAO2 P K7 CHD _P lt 0 gt HBO2_P F22 DHD _P lt 0 gt LA03 N G10 ALD N lt 1 gt 3 N 17 CLD N lt 1 gt HBO3 N E22 DLD N lt 1 gt LA03 P G9 ALD P 1 HAO3 P J6 CLD_P lt 1 gt HBO3_P E21 DLD_P lt 1 gt LAO4_N H11 AHD N 1 HAO4_N F8 CHD N lt 1 gt HBO4 F26 DHD N lt 1 gt LA04 P H10 AHD P lt 1 gt P F7 CHD P lt 1 gt P F25 DHD_P lt 1 gt LAOS_N D12 ALD_N lt 2 gt HAOS_N E7 CLD N lt 2 gt HBO5 N E25 DLD N lt 2 gt LA05 P D11 ALD_P lt 2 gt 5 P E6 CLD_P lt 2 gt HBO5 P E24 DLD P lt 2 gt LA06 N c11 AHD_N lt 2 gt HAO6_N Kil 1 CHD N lt 2 gt HBO6 N CC 29 DHD N 2 LAO6 P C10 AHD P lt 2 gt 06 P K10 CHD_P lt 2 gt HBO6_P_CC 28 DHD P 2 LAO7 N H14 ALD N lt 3 gt HAO7_N 110 CLD_N lt 3 gt HBO7_N 128 DLD N lt 3 gt LAO7 P H13 ALD P 3 7 P J9 CLD P
28. UM009 FMC12x User Manual te r1 17 FMC122 FMC125 FMC126 User Manual 4DSP LLC USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2015 UM009 FMC12x User Manual Sr Revision History 2010 04 13 Initial release 2010 09 08 Added signal description to pin out tables monitoring device parameters 2011 04 14 Added FMC connector type specification 1 7 Updated trigger input specification 2011 08 01 Update external clock reference input level 2011 09 09 Added optional clock output specification 1 9 Added 12C signals to the pin out tables 2011 10 04 Corrected internal clock specification and clock 1 10 tree diagram Added DIP Switch description 2012 01 10 Updated power consumption Updated performance numbers Added FAN control details 2012 10 08 Added changes between revision 1 and revision 2 boards 2013 08 17 Changed the number of channels available on FMC122 2014 03 06 Changed input power level of external reference 2014 04 07 Revised some descriptions and fixed typos 2014 06 19 Changed pin 20 into shell in Table 2 HDMI 1 16 connector pin out 2015 04 30 Updated description of front panel HDMI 1 17 section 4 1 3 www 4dsp com r1 17 UM009 FMC12x User Manual Table of Contents JS n 1 Acronyms and related documents
29. a is ALD P 7 0 valid on both edges of the clock DDR AHD N 7 0 A D A Output LVDS Data port H igh data is AHD 7 05 valid on both edges of the clock DDR BDR N A D B Output LVDS Digital data clock from BDR P ADC The ADC can operate in mux mode using data port L ow and data port H igh BLD N 7 0 A D B Output LVDS Data port L ow data is BLD 7 05 valid on both edges of the clock DDR BHD_N lt 7 0 gt A D B Output LVDS Data port H igh data is BHD P 7 0 valid on both edges of the clock DDR CLK TO FPGA N MONITOR Output LVDS Spare clock signal from CLK TO FPGA P the clock tree Can be used to monitor onboard external clock TRIGGER TO FPGA N I O Output LVDS Representation of the TRIGGER TO FPGA P signal connected to the external trigger input l2C SCL CONTROL Input LVTTL 3 3V 120 Clock The I2C bus is the main control bus 20 5 CONTROL Bidir LVTTL 3 3V 20 Data The 20 bus is the main control bus DP M2C P NO O Output CML ECL Gigabit transceiver from HDMI connector UM009 www 4dsp com 23 UM009 FMC12x User Manual Er r1 17 Appendix B HPC pin out FMC125 FMC122 AV57 1 HPC Pin FMC125 Signal AV57 1 HPC Pin FMC125 Signal AV57 1 HPC Pin FMC125 Signal CLKO_M2C_N H5 CLK FPGA N CLK2_BIDIR_N K5 SYNC_FROM_FPGA_N GBTCLKO_M2C_N D
30. eivers on the HDMI connector Table 2 The direction of the transceivers is controlled through a CPLD register DP M2C P N 1 0 O Output CML ECL Gigabit transceiver from HDMI connector DP_C2M_P N lt 3 2 gt Input CML ECL Gigabit transceiver to HDMI connector SYNC FROM FPGA N CONTROL Input LVDS Signal used to apply a SYNC FROM FPGA P sync pulse to both ADC in order to align the digital outputs on sample basis FMC TO CPLD lt 3 0 gt CONTROL Bidir CMOS VADJ Reserved I2C_SCL CONTROL Input LVTTL 3 3V I2C Clock The I2C bus is the main control bus 20 5 CONTROL Bidir LVTTL3 3V I2C Data The 20 bus is the main control bus UMO009 www 4dsp com 27 UM009 FMC12x User Manual Er r1 17 Appendix C HPC pin out FMC126 AV57 1 HPC Pin FMC126 Signal AV57 1 HPCPin FMC126 Signal AV57 1 HPC Pin FMC126 Signal CLKO_M2C_N H5 CLK FPGA N CLK2_BIDIR_N K5 SYNC_FROM_FPGA_N GBTCLKO_M2C_N DS GBTCLKO_N CLKO_M2C_P CLK TO FPGA P CLK2 BIDIR SYNC FROM FPGA P GBTCLKO M2C P D4 GBTCLKO_P CLK1_M2C_N G3 TRIGGER FPGA N CLK3 BIDIR N J3 N C GBTCLK1_M2C_N B21 GBTCLK1_N CLK1 M2C P G2 TRIGGER TO FPGA P CLK3 BIDIR P 12 N C GBTCLK1_M2C_P B20 GBTCLK1_P 1 00 G7 ADR N N CC F5 CDR N HBOO N CC K26 DDR N 00 P CC G6 ADR P HAO0 P CC F4 CDR_P HBOO P CC K25 DDR P L
31. gt LA17_N_CC D21 BDR_N HA17_N_CC K17 CLOR_N HB17_N_CC K38 DLOR_N LA17_P_CC D20 BDR_P HA17_P_CC CLOR_P HB17 P CC K37 DLOR P LA18 N CC C23 BLD 0 HA18 N 119 CHOR N HB18 N 137 DHOR LA18 P CC C22 BLD P 0 HA18 P 18 CHOR P HB18 P 136 DHOR P LA19 N H23 BHD N 0 HA19 N F20 ALORN HB19 N E34 FMC_TO_CPLD lt 3 gt LA19 P H22 BHD P 0 HA19 P F19 ALOR P HB19 P E33 FMC CPLD 2 LA20 N G22 BLD Nei HA20 N E19 AHOR N HB20 N F38 FRONT IO FMC lt 1 gt UM009 www 4dsp com 24 UM009 FMC12x User Manual Lp Er LA20 P G21 BLD P 1 HA20 P E18 AHOR_P HB20_P F37 FRONT_IO_FMC lt 0 gt LA21_N H26 BHD_N lt 1 gt HA21_N K20 BLOR_N HB21_N E37 FRONT IO FMC lt 3 gt LA21 P H25 BHD P lt 1 gt HA21 P K19 BLOR P HB21 P E36 FRONT IO FMC 2 LA22 N G25 BLD N 2 HA22 N 122 BHOR LA22 P G24 BLD P 2 HA22 P 121 BHOR P LA23 N D24 BHD N 2 HA23 N K23 FMC TO CPLD 1 SCL C30 126 SCL LA23 P D23 BHD P 2 HA23 P K22 FMC TO CPLD 0 SDA C31 I2C SDA LA24 N H29 BLD N 3 DPO C2M N C3 DP C2M N 0 DPO M2C N C7 DP M2C N 0 LA24 P H28 BLD P 3 DPO C2M P C2 DP C2M P 0 DPO M2C P C6 DP M2C P 0 LA25 N G28 BHD N 3 DP1 C2M N A23 DP_C2M_N lt 1 gt DP1_M2C_N A3 DP M2C N lt 1 gt LA25 P G27 BHD P
32. nd A D ADC N RESET e Control the direction of the front I O transceivers FRONT DIR Control the FAN header power FAN N EN e Collect local status signals and store them in a register which can be accessed from the carrier hardware Drive a LED according to the level of the status signals Local Side CPLD i lt Shift register gt CLKSRC_SEL 0 2 yy SYNCSRC_SEL 0 1 Ctrl CLK_N_RESET ADC_N_RESET FRONT_IO_DIR 0 3 FAN N EN 0 1 REFMON LD gt STATUS We AND VM N INT LED a Figure 11 CPLD architecture N CS Nos al nas en be Door e os s MISO 8 bit instruction 8 bit register data Figure 12 Write instruction to CPLD registers A1 A0 SPI Side SCLK CPLD N CS MOSI MISO FMC TO CPLD 3 N INT UMO009 www 4dsp com 18 UM009 FMC12x User Manual Er r1 17 N CS 8 bit instruction 8 bit register data Figure 13 Read instruction to CPLD registers A1 A0 www 4dsp com 19 n UM009 FMC12x User Manual 6 Environment 6 1 Temperature Operating temperature 0C to 70 C Commercial Storage temperature 40 to 120 C 6 2 Monitoring The onboard monitoring may be used to monitor the voltage on the different power rails as well as the temperature of the Quad ADC and the clock
33. ow pin count connector has only bank LA available and only two of the four dedicated LVDS clock pairs The following arrangement is used e ADC output port A and port B will connect to bank LA 32 data pairs and 2 clock capable pairs on FMC122 FMC125 20 data pairs and 2 clock capable pairs on FMC126 e ADC output port C will connect to bank HA 16 data pairs and 1 clock capable pairs on FMC122 FMC125 10 data pairs and 1 clock capable pairs on FMC126 e ADC output port D will connect to bank HB 16 data pairs and 1 clock capable pairs on FMC122 FMC125 10 data pairs and 1 clock capable pairs on FMC126 The over range signal pairs are connected to bank HA HB and are therefore not available on carrier boards with a low pin count connector 4 2 4 Main characteristics Analog inputs Number of channels 4 2 or 1 programmable x 8 bit FMC122 FMC125 Channel resolution 10 bit FMC126 UM009 www 4dsp com 10 UM009 FMC12x User Manual Er r1 17 ee voltage range 0 5Vp p Imputimpedance impedance 500 AC 502 AC coupled 0000 0 Anal input bandwidth 500 600 1500 2000MHz programmable FMC122 FMC125 M PDU DADAY 1000 3000MHz programmable FMC126 Performance SFDR 56 dBc SNR 44 dBFS FMCI22 FMCI25 1 25Gsps mode Fin 406 MHz SFDR 61 dBc SNR 50 dBFS FMC126 1 25Gsps mode Gain 18 Calibration Offset x50mV Phase 14ps External Clock Reference input Input level 6dBm to 7dBm Input impedance
34. ower supply e CLKSRC SEL2 enables disables the onboard reference oscillator 4 7 Multi Gigabit Transceivers optional The FMC connector hosts 10 MGT pairs 10 Tx and 10 Rx pairs These are connected to two 38 pins MICTOR headers in an arrangement that supports different interconnect topologies The VCXO should be powered down to avoid interference with the external clock when external clock is used UMO009 www 4dsp com 13 UM009 FMC12x User Manual ef SE r1 17 Figure 8 MGT interconnect topologies TOP VIEW MICTOR 1 Rx Tx 0 4 MICTOR 2 Rx Tx 5 9 Figure 9 4DSP CPCI board stack slot to slot www 4dsp com 14 UM009 FMC12x User Manual Er r1 17 MICTOR 1 MICTOR 2 Pin Signal Midplate Signal Pin Pin Signal Midplate Signal Pin 1 GND GND GND 1 GND GND GND 3 TXOP GND RXO_P 3 RX9 P GND TX9 P 5 TXON GND RXO_N 6 5 N GND TXYN 6 7 GND GND GND 7 GND GND GND 8 9 TXLP GND RX1P 10 9 8 GND TX8 P 10 11 T1N GND RXLN 12 11 RX8 N GND TX8N 12 13 GND GND GND 14 13 GND GND GND 14 15 TX2P GND 2 16 15 RX7_P GND TX7_P 16 17 D2N GND RX2_N 18 17 RX7_N GND TX7_N 18 19 GND GND GND 20 19 GND GND GND 20 21 TX3P GND RX3_P 22 21 RX6 P GND TX6 P 22 23 D3 N G
35. ta conversion performance The user may choose to use an external or internal sampling clock The clock tree has a PLL and clock distribution section The PLL ensures locking of the internal clock to an external supplied reference The onboard reference is used if no external reference is present www 4dsp com 12 UM009 FMC12x User Manual te T r1 17 A 2500MHz VCO CRO2500A LF is used as internal clock source and can connect to the distribution section instead of the external clock input The distribution section drives the Quad ADC One additional clock signal is connected to the FMC connector for test and monitoring purposes Note that the LF input on the AD9517 is not connected to the loop filter It is therefore not possible to use the internal VCO of the AD9517 RF Clock OH Switch SWITCHOVER AND MONITOR RF Switch ove mea Oe ourt gs clk out wem SO ours Emu owe Ey vores cr awe ove Tiene Poco m ene a SERIAL CONTROL PORT e AND cm DIGITAL LOGIC Figure 7 Clock tree CTRL2 Control The clock tree contains two RF switches ADG918 and requires the following control signals driven from the CPLD e CLKSRC SELO connects the external clock input to the reference input of the AD9517 or the 2 RF switch e CLKSRC SEL1 connect either the onboard VCXO or the external clock to the clock input of the AD9517 This signal also controls the VCXO p
36. to enable phase alignment on the carrier card It should be noted that successful implementation of LVDS connections running at 1 25Gbps FMC126 highly depends on carrier board design and layout www 4dsp com 7 UM009 FMC12x User Manual Er r1 17 4 Design 4 1 Phycisal specifications 4 1 1 Board Dimensions The FMC12x card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O The front area holds connectors that might conflict with the front rib keep out area 4Tx 4Rx 4 LVTTL Trigger Input Clock Input og D og C og B og A 4mm low profile Heatsink optional Figure 4 FMC122 FMC125 FMC126 dimensions 4 1 2 Front panel There are six coax connectors available from the front panel From top to bottom 1 analog input A 214 analog input B 3 analog input C 4 analog input D clock input CL trigger input TR www 4dsp com 8 UM009 FMC12x User Manual Er r1 17 Figure 5 Bezel drawing 4 1 3 Front panel HDMI I O The 19 pins HDMI connector on the front panel 10 holds four Multi gigabit transceivers two Tx pairs two Rx pairs and 4x LVTTL 5V tolerant Contact 4DSP for other configurations Pin Number Signal Name Pin Number Signal Name 1 DP M2C 0 SHELL GND 2 Shield 19 N C 3 D
37. www 4dsp com 20 UM009 FMC12x User Manual Er r1 17 range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 3 2 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the device manufacturers mostly 85 The FMC 12x is designed for maximum heat transfer to conduction cooled ribs A customized cooling frame that connects directly to the surface of the Quad ADC is allowed contact 4DSP for detailed mechanical information This conduction cooling mechanism should be applied in combination with proper chassis air flow 7 Safety This module presents no hazard to the user 8 EMC This module is designed to operate within an enclosed host system built to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 9 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional

FMC122/FMC125/FMC126 User Manual

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