MC68030 Second-Generation 32-Bit .. Enhanced Microprocessor
Contents
1. This parameter specifies the maximum allowable skew between DSACKO to DSACK1 asserted or DSACK1 to DSACKO asserted specification 47A must be met by DSACKO DSACK1 This specification applies to the first DSACKO or DSACK1 DSACKx signal asserted In the absence of DSACKx BERR is an asynchronous input using the asynchronous input setup time 47A DBEN may stay asserted on consecutive write cycles __ The minimum values must be met to guarantee proper operation If this maximum value is exceeded BG be reasserted This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately by another cache hit a cache miss or an operand cycle This specification guarantees operation with the MC68881 MC68882 which specifies a minimum time for DS negated to AS asserted specification 13A in the MC68881 MC68882 User s Manual Without this specification incorrect interpretation of specifications 9A and 15 would indicate that the MC68030 does not meet the MC68881 MC68882 requirements This specification allows a system designer to guarantee data hold times on the output side of data buffers that have output enable signals generated with DBEN The timing on DBEN precludes its use for synchronous READ cycles with no wait states These specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus2. Operand 32BitOperand RM Register Select Specifies CPU Register or Mask R Instruction Address RW RAW Condition Word Condition to be Evaluated Since the CIRs are accessed via normal read and write cycles coprocessors can be used as peripheral devices by other M68000 Family members that do not support the coprocessor interface The communication protocol can be easily emulated by appropriately addressing the CIRs and by passing the re quired coprocessor commands and operands In addition to the CIRs the co processor contains those registers added to the MC68030 programmer s model MC68030 TECHNICAL DATA MOTOROLA for specific coprocessor operations For example the Motorola floating point coprocessors contain the CIRs as well as eight 80 bit floating point data reg isters and three 32 bit control status registers Up to eight coprocessors are supported in a single MC68030 system with a system unique coprocessor identifier encoded in the coprocessor instruction When accessing a coprocessor the MC68030 executes standard bus cycles in CPU address space as encoded by the function codes and places the copro cessor identifier on the address bus to be used by chip select logic to select the particular coprocessor Since standard bus cycles are used the coprocessor may be located according to system design requirements whether it is located on the microprocessor local bus on another board on the system bus
3. 0 017 0022 LK 432 495 0 170 0195 MOTOROLA MC68030 TECHNICAL DATA 49 RP Suffix Case No 789F 01 1 DIMENSIONING AND TOLERANCING PER ANSI 14 5 1982 3 DIMENSION D INCLUDES LEAD FINISH 2 CONTROLLING DIMENSION INCH NOTES oja oja e e o e s e MOTOROLA MC68030 TECHNICAL DATA 50 FE Suffix Case No 831 01 eR S l 0 20 0 008 TIXO YO 2b Dia 0 51 0 020 YO a re Up ij K EN M 4 D up MILLIMETERS INCHES NOTES MN MAX Di SJ 00 MIN MAX 1 DIMENSIONING AND TOLERANCING 2185 2286 0860 090 PER ANSI Y14 5M 1982 B 2185 22 86 0860 0900 2 CONTROLLING DIMENSION INCH e 394 431 0155 0170 3 DIM A AND B DEFINE MAXIMUM CERAMIC BODY DIMENSIONS INCLUDING GLASS PROTRUSION AND MISMATCH OF CERAMIC BODY TOP AND D 024 0292 0 0080 0 0115 G 064 5 0 025 BSC H 064 088 0025 0 035 BOTTOM 013 020 0005 0008 4 DATUM PLANE W IS LOCATED AT THE UNDERSIDE OF LEADS WHERE LEADS EXIT PACKAGE BODY DATUMS X Y AND Z TO BE DETERMINED WHERE CENTER LEADS EXIT PACKAGE BODY AT DATUM W DIM S AND V TO BE DETERMINED AT SEATING PLANE DATUM DIM A AND B TO BE DETERMINED AT DATUM PLANE W K 051 076 0020 0 030 20 32 REF 0 800 REF 0 8 L
4. An Xn bd An Xn Memory Indirect Memory Indirect Postindexed bd An Xn od Memory Indirect Preindexed bd An Xn od Program Counter Indirect with Displacement 16 Program Counter Indirect with Index PC Indirect with Index 8 Bit Displacement PC Indirect with Index Base Displacement dg PC Xn bd PC Xn Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed bd PC Xn od bd PC Xn od Absolute Absolute Short xxx W Absolute Long xxx L NOTES Dn Data Register 00 07 An Address Register 0 7 dg 416 A twos complement or sign extended displacement added as part of the effective address calculation size is 8 dg or 16 416 bits when omitted assemblers use a value of zero Xn Address or data register used as an index register form is Xn SIZE SCALE where SIZE is W or L indicates index register size and SCALE is 1 2 4 or 8 index register is multiplied by SCALE use of SIZE and or SCALE is optional bd A twos complement base displacement when present size be 16 32 bits MOTOROLA MC68030 TECHNICAL DATA 9 Table 1 Addressing Modes Continued od Outer displacement added as part of effective address calculation after any memory indirection use is optional with a size of 16 or 32 bits PC Program Counter data Immediate value of 8 16 or 32 bits
5. Data Strobe Data Buffer Enable Data Transfer and Size Acknowledge Synchronous Termination Cache Inhibit In Cache Inhibit Out Cache Burst Request Cache Burst Acknowledge Interrupt Priority Level Interrupt Pending Autovector Bus Request Bus Grant 28 Table 5 Signal Index Mnemonic Function FCO FC2 3 bit function code used to identify the address space of each bus cycle A0 A31 32 bit address bus DO D31 32 bit data bus used to transfer 8 16 24 or 32 bits of data per bus cycle SIZO SIZ1 Indicates the number of bytes remaining to be trans ferred for this cycle These signals together with AO 1 define the active sections of the data bus OCS Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transfer ECS Provides an indication that a bus cycle is beginning R Defines the bus transfer as a processor read or write RMC Provides an indicator that the current bus cycle is part of an indivisible read modify write operation AS Indicates that a valid address is on the bus DS Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the MC68030 Provides an enable signal for external data buffers DSACKO Bus response signals that indicate the requested data DSACK1 transfer operation has been completed In addition these two lines indicate the size of the ext
6. burst operation The caches can not be manipulated directly by the programmer except by the use of the CACR which provides cache clearing and cache entry clearing facilities The caches can also be enabled disabled by this register Finally the system hardware can disable the on chip caches at any time by asserting of the CDIS signal MOTOROLA MC68030 TECHNICAL DATA 13 LONG WORD SELECT TAG INDEX iN ais 3 22221111111111000000000 0 ACCESS ADDRESS 21011 321098765432109876543210 1 OF 16 SELECT DATA FROM INSTRUCTION TAG REPLACE CACHE DATA BUS DATA TO INSTRUCTION CACHE HOLDING REGISTER ENTRY HIT COMPARATOR CACHE CONTROL LOGIC LINE HIT CACHE SIZE 64 LONG WORDS LINE SIZE 4 LONG WORDS SET SIZE 1 Figure 5 On Chip Instruction Cache Organization DATA CACHE The organization of the data cache see Figure 6 is similar to that of the in struction cache However the tag is composed of the upper 24 address bits the four valid bits and all three function code bits explicitly specifying the address space associated with each line The data cache employs a write through policy with programmable write allocation of data writes i e if a cache hit occurs on a write cycle both the data cache and the external device are updated with the new data If a write cycle generates a cache miss the external device is updated and a new dat
7. or any other place supported by the chip select and coprocessor protocol using stand ard bus cycles COPROCESSOR PROTOCOL Interprocessor transfers are all initiated by the main processor during copro cessor instruction execution When processing a coprocessor instruction the main processor transfers instruction information and data to the associated coprocessor and receives data requests and status information from the co processor These transfers are all based on standard read and write bus cycles The typical coprocessor protocol for the main processor is as follows A The main processor initiates the communication by writing command in formation to a location in the coprocessor interface B The main processor reads the coprocessor response to that information 1 The response may indicate that the coprocessor is busy and the main processor should requery the coprocessor allowing the main processor and coprocessor to synchronize their concurrent operations 2 The response may indicate some exception condition the main pro cessor acknowledges the exception and begins exception processing 3 The response may indicate that the coprocessor needs the main pro cessor to perform some service such as transferring data to or from the coprocessor The coprocessor may also request that the main processor requery the coprocessor after the service is complete 4 The response may indicate that the main processor is not needed for f
8. sists of the address and data pads the multiplexers required to support dynamic bus sizing and a microbus controller that schedules the bus cycles on the basis of priority The micromachine contains the execution unit and all related control logic Microcode control is provided by a modified two level store of microROM and nanoROM contained in the micromachine Programmed logic arrays PLAs are used to provide instruction decode and sequencing information The in struction pipe and other individual control sections provide the secondary de code of instructions and generate the actual control signals that result in the decoding and interpretation of nanoROM and microROM information The instruction and data cache blocks operate independently from the rest of the machine storing information read by the bus controller for future use with very fast access time Each cache resides on its own address bus and data bus allowing simultaneous access to both Both caches are organized as a total of 64 long word entries 256 bytes with a line size of four long words The data cache uses a write through policy with programmable write allocation for cache misses Finally the MMU controls the mapping of addresses for page sizes ranging from 256 bytes to 32K bytes Mapping information stored in descriptors resides in translation tables in memory that are automatically searched by the MC68030 on demand Recently used descriptors are maintained in a 22 entry f
9. AS Asserted and DS Asserted Read Clock Low to AS DS CBREO 20 18 10 Negated 12 Clock Low to Clock Low to ECS OCS Negated Clock Low to ECS OCS Negated AS DS Negated to Function Code Size RMC CIOUT Address Invalid TE pu e DS Read Width Asserted 70 45 Asynchronous pu e 141 DS Width Asserted Write 38 Ia lil tl ed 18 13 AS and DS Read Width Asserted 35 30 23 18 13 Synchronous Cycle 15 DS Width Negated 38 DS Negated to AS Asserted Clock High to AS DS R W DBEN CBREQ High Impedance BEN XI DICT TRECE 0 EE EC L N gt Clock High to R W Low R W High to AS Asserted MOTOROLA MC68030 TECHNICAL DATA 37 AC ELECTRICAL SPECIFICATIONS continued sum Characteristic 20MHz 25MHz 33 33MHz 40MHz 0 MHz Min Max Min Max Min Max Min Max Min Max Ee Data Out Valid to Negating Edge of AS 2511 JAS DS Negated to Data Out Invalid 25 9 11 IDS Negated to DBEN Negated 10 7 Write 2611 Data Out Valid to Asserting Edge of DS Asserted Write Data In Valid to Clock Low Setup 27 Late BERR HALT Asserted to 10 Clock Low Setup AS DS Negated to DSACKx 15 BERR HALT AVEC Negated Asynchronous Hold Clock Low to DSACKx BERR HALT AVEC Negated S
10. Data to Predefined Addresses i e Graphics Applications e Pipelined Architecture with Parallelism Allows Accesses from Internal Caches to Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped This document contains information on a new product Specifications and information herem are supject to cnange without notice M MOTOROLA 9MOTOROLA INC 1991 Rev 3 Enhanced Bus Controller Supports Asynchronous Bus Cycles three clocks minimum Synchronous Bus Cycles two clocks minimum and Burst Data Transfers one cock minumum all to the Physical Address Space Dynamic Bus Sizing Supports 8 16 32 Bit Memories and Peripherals e Complete Support for Coprocessors with the M68000 Coprocessor Inter face Internal Status Indication for Hardware Emulation Support 4 Gbyte Direct Addressing Range Implemented Motorola s HCMOS Technology That Allows CMOS and HMOS High Density NMOS Gates To Be Combined for Maximum Speed Low Power and Small Die Size Processor Speeds Beyond 20 MHz INTRODUCTION The MC68030 is an integrated processor that incorporates the capabilities of the MC68020 microprocessor the memory management structure defined by the MC68851 paged memory management unit PMMU data cache an in struction cache and an improved bus controller on one VLSI device It maintains the 32 bit registers available with the entire M68000 Family as well a
11. entry The results of the search are available in the MMU status register MMUSR and often useful in determining the cause of a fault PLOAD Takes an address and function code and searches the translation tables for the corresponding page descriptor It then loads the ATC with the appropriate information PFLUSH Flushes the ATC by function code function code and logical address PFLUSHA Flushes all ATC entries TRANSPARENT TRANSLATION Two transparent translation registers are provided on the MC68030 MMU to allow portions of the logical address space to be transparently mapped and accessed without corresponding entries resident in the ATC Each register is used to define a range of logical addresses from 16 Mbytes to 2 Gbytes with a base address and a mask All addresses within these ranges will not be mapped and protection is provided only on a basis of read write and function code COPROCESSOR INTERFACE The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family The interface provided on the MC68030 is the same as that on the MC68020 Examples of these extensions are the addition of specialized data operands for the existing data types or for the case of floating point the inclusion of new data types and operations implemented by the MC68881 MC68882 floating point coprocessors MOTOROLA MC68030 TECHNICAL DATA 23 24 Coprocessors divided into two types by their bus uti
12. of a long word operand it will attempt to read 32 bits during the first bus cycle to a long word address boundary If the port responds that it is 32 bits wide the MC68030 latches all 32 bits of data and continues If the port responds that it is 16 bits wide the MC68030 latches the 16 valid bits of data and runs a second cycle to obtain the remaining 16 bits of data An 8 bit port is handled similarly but has four bus read cycles Each port is fixed in the assignment to particular sections of the data bus However the MC68030 has no restrictions concerning the alignment of operands in memory long word operands need not be aligned to long word address boundaries When misaligned data requires multiple bus cycles the MC68030 automatically runs the minimum number of bus cycles Instructions must still be aligned to word boundaries The timing of asynchronous bus cycles is also determined by the assertion of the DSACKx signals on a cycle by cycle basis If the DSACKx signals are valid 1 5 clocks after the beginning of the bus cycle with the appropriate setup time the cycle terminates in the minimum amount of time corresponding to three clock cycles total The cycle can be lengthened by delaying DSACKx effectively inserting wait states in one clock increments until the device being accessed is able to terminate the cycle This flexibility gives the processor the ability to communicate with devices of varying speeds while operating at the faste
13. the tables for most programs since only a portion of the complete tree needs to exist at any one time The root of a translation table tree is pointed to by one or two root pointer registers that are part of the programmer s model the CPU and supervisor Table entries at the higher levels of the tree pointer tables contain pointers to other tables Entries at the leaf level page tables contain page descriptors The mechanism for performing table searches uses portions of the logical address as indices for each level of the lookup All addresses in the translation table entries are physical addresses MOTOROLA MC68030 TECHNICAL DATA 21 22 Figure 7 illustrates the translation table structure Several determinants of the detailed table structure are software selectable The first level of lookup in the table normally uses the function codes as an index but this may be suppressed if desired In addition up to 15 of the logical address lines can be ignored for the purposes of the table searching The number of levels in the table indexed by the logical address can be set from one to four and up to 15 logical address bits can be used as an index at each level A major advantage to using this tree structure for the translation tables is the ability to deallocate large portions of the logical address space with a single entry at the higher levels of the tree Additionally portions of the tree itself may reside on a secondary storage device or may
14. this way the access to the page is aborted and the processor initiates bus error exception processing for this address The operating system can then control the allocation of a new page in physical memory and can load the page during the bus error handling routine ADDRESS TRANSLATION CACHE An integral part of the translation function previously described is the cache memory that stores recently used logical to physical address translation in formation or page descriptors This cache consists of 22 entries and is fully associative The ATC compares the logical address and function code of the incoming access against its entries If one of the entries matches there is a hit and the ATC sends the physical address to the bus controller which then starts the external bus cycle provided no hit occurred in the instruction or data caches for the access The ATC is composed of three major components the content addressable memory CAM containing the logical address and function code information to be compared against incoming logical addresses the physical address store containing the physical address associated with a particular CAM entry and the control section containing the entry replacement circuitry that implements the replacement algorithm a variation of the least recently used algorithm TRANSLATION TABLES The translation tables supported by the MC68030 have a tree structure mini mizing the amount of memory necessary to set up
15. when the MC68030 regains control of the bus after an arbitration sequence DS will not be asserted for synchronous write cycles with no wait states These hold times are specified with respect to strobes asynchronous and with respect to the clock synchronous The designer is free to use either time Synchronous inputs must meet specifications 60 and 61 with stable logic levels for rising edges of the clock while AS is asserted These values are specified relative to the high level of the rising clock edge The values originally published were specified relative to the low level of the rising clock edge m This specification allows system designers to qualify the CS signal of an MC68881 MC68882 with AS allowing 7 ns for a gate delay and still meet the CS to DS setup time requirement specification 8B of the MC68881 MC68882 User s Manual MC68030 TECHNICAL DATA MOTOROLA 50 51 52 53 54 55 CLK A31 A0 FC2 FCO 6171 5170 6 gt 64 RMC 20 we VN PLE VON TI oa 5 031 00 e N D mn N ALL 48 ASYNCHRONOUS INPUTS e amp 12 Figure 11 Asynchronous Read Cycle Timing Diagram MOTOROLA MC68030 TECHNICAL DATA 41 50 51 52 53 54 55 50 A AY O yO eo tT TI S TE EGS TE V ts ep re TT a e M o gt a p iE zie RW y 7 2 IN 23 p
16. Dynamically disables the on chip cache to assist em ulator support MMU Disable MMUDIS Dynamically disables the translation mechanism of the MMU MOTOROLA MC68030 TECHNICAL DATA 29 ELECTRICAL SPECIFICATIONS MAXIMUM RATINGS Rating Supply Voltage Vcc Input Voltage Vin Operating Temperature Range Minimum Ambient Temperature Maximum Ambient Temperature TA PGA PPGA lt 33MHz Maximum Junction Temperature TJ Storage Temperature Range Tstg Rated clock speed of device THERMAL CONSIDERATIONS 0 3 to 7 0 0 5 to 7 0 0 70 115 Unit This device contains protective cir cuitry against damage due to high static voltages or electrical fields however it is advised that normal precautions be taken to avoid appli cation of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of op eration is enhanced if unused inputs are tied to an appropriate logic volt age level e g either GND or Vcc The average chip junction temperature Ty in C can be obtained from TJ TAHPp OJA 1 where TA Ambient Temperature C OJA Package Thermal Resistance Junction to Ambient C W PD PINT PI O PINT Icc x Vcc Watts Chip Internal Power Power Dissipation on Input Output Pins User Determined For most applications lt and be neglected An approximate relationship between Pp and Ty if Pjjp is n
17. Effective Address Use as indirect access to long word address INSTRUCTION SET OVERVIEW MC68030 instruction set is listed in Table 2 Each instruction with few exceptions operates on bytes words and long words and most instructions can use any of the 18 addressing modes The MC68030 is upward source and object code compatible with the M68000 Family because it supports all instruc tions of previous family members Included in this set are the bit field opera tions binary coded decimal support bounds checking additional trap conditions and additional multiprocessing support CAS and CAS2 instruc tions offered by the MC68020 The new instructions supported by the MC68030 a subset of the instructions introduced by the 68851 PMMU are used to communicate with the MMU For detailed information on the MC68030 instruc tion set refer to M68000 PM AD M68000 Programmer s Reference Manual Table 2 Instruction Set Add Decimal with Extend Compare and Swap Operands Add Compare and Swap Dual Operands Add Address Check Register Against Bound Add Immediate Check Register Against Upper and Add Quick Lower Bounds Add with Extend Clear Logical AND Compare Logical AND Immediate Compare Address Arithmetic Shift Left and Rig Compare Immediate Branch Conditionally Compare Memory to Memory Test Bit and Change Compare Register Against Upper Test Bit and Clear and Lower Bounds Test Bit Field and Change DBcc Test Conditi
18. HNICAL DATA 19 printers or terminals The MC68030 MMU provides support for a virtual system and virtual memory In addition it protects supervisor areas from accesses by user programs and provides write protection on a page basis All this capability is provided as well as maximum performance because address translations occur in parallel with other processor activities DEMAND PAGED IMPLEMENTATION A typical MC68030 system with a large addressing range provides a limited amount of high speed physical memory that can be accessed directly by the processor while maintaining an image of a much larger virtual memory on secondary storage devices such as large capacity disk drives When the pro cessor attempts to access a location in the virtual memory map that 15 not resident in physical memory the access to that location is temporarily sus pended while the necessary data is fetched from secondary storage and placed in physical memory the suspended access is then either restarted or continued A paged system is one in which the physical memory is subdivided into equal sized blocks called page frames and the logical untranslated address space of a task is divided into pages having the same size as the page frames The operating system controls the allocation of pages to page frames bringing in data on a page basis as it is needed from the secondary storage device The MC68030 memory management scheme is called a demand implementation because a
19. M R 064 002 L S 2731 27 55 1075 1085 LV 2731 755 1 075 1085 e o MOTOROLA MC68030 TECHNICAL DATA 51 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity A
20. Order this document by MC68030 D MOTOROLA TECHNICAL DATA MC68030 Summary Second Generation 32 Bit Enhanced Microprocessor The MC68030 is a 32 bit virtual memory microprocessor that integrates the functionality of an MC68020 core with the added capabilities of an on chip paged memory management unit MMU and an on chip 256 byte data cache Additionally the MC68030 is enhanced with multiple internal address and data buses as well as a more versatile bus controller that can support two clock bus accesses and one clock burst accesses to maximize performance The rich in struction set and addressing mode capabilities of the MC68020 have been maintained allowing a clear migration path for M68000 systems For detailed information on the MC68030 refer to MC68030UM AD MC68030 Enhanced 32 Bit Microprocessor User s Manual The main features of the MC68030 are as follows e Object Code Compatible with 68020 Earlier 68000 Micropro cessors Complete 32 Bit Nonmultiplexed Address and Data Buses e 16 32 Bit General Purpose Data and Address Registers Two 32 Bit Supervisor Stack Pointers and 10 Special Purpose Control Reg _ isters 256 Byte Instruction Cache and 256 Byte Data Cache Can Be Accessed Simultaneously e Paged MMU Translates Addresses in Parallel with Instruction Execution Two Transparent Segments Allow Untranslated Blocks To Be Defined for Systems That Transfer Large Blocks of
21. PTESTR PTESTW cpSAVE cpScc cpTRAPcc Flush Entry ies the Flush All Entries in the ATC Load Entry into the ATC Move to from MMU Registers Move to from MMU Registers with Flush Disable Test a Logical Address Reset External Devices Rotate Left and Right Return and Deallocate Return from Exception Return and Restore Codes Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand sor Save Internal State of Coprocessor Set Conditionally MOTOROLA MC68030 TECHNICAL DATA 11 INSTRUCTION AND DATA CACHES Studies have shown that typical programs spend most of their execution time in a few main routines or tight loops This phenomenon known as locality of reference has an impact on program performance The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can be used with the DBcc instruction The MC68030 takes further advantage of cache technology to provide the system with two on chip caches one for instructions and one for data MC68030 CACHE GOALS 12 Similar to the MC68020 there were two primary design goals for the MC68030 microprocessor caches The first design goal was to reduce the processor ex ternal bus activity even more than what was acc
22. S D29 D27 D24 D22 D20 D17 D14 tE O 0 0 0 0 00 5120 RW 030 GND Voc GND GND GND D7 K O O O O CBREQ DS SIZ1 Voc NC D5 J O O O CBACK AS GND GND STATUS REFILL Hi O O O O O BERR HALT Voc ee Vcc CDIS iPLO G BOTTOM VIEW O O O STERM DSACKi GND GND iPL2 PLi F O O O O O_O O DSACKO Vcc GND NC NC Vcc RESET MMUDIS O QOO E O O AVEC GND NC IPEND O O O JO O FC2 FCO OCS NC A3 A2 O FC1 BGACK 1 GND GND 18 GND A5 M O O O A31 29 A27 A25 A22 A20 16 014 012 08 7 O O 0 O OO O BR 0 A30 28 26 24 A23 21 19 17 A15 A13 gt U O O m MOTOROLA MC68030 TECHNICAL DATA 132 Lead Ceramic Surface Mount FE Suffix MC68030 100 1 GND TOP VIEW 5 GND D11 D10 Do D8 z a lt 58 NC Do not connect to this pin 48 MC68030 TECHNICAL DATA MOTOROLA PACKAGE DIMENSIONS RC Suffix Case No 789C 01 N OO0 MOOO 1990 KIOO 590 H GOOO FIO E GG y 00000 c oooco 5 OOOO A 12345 67 8 9 10111213 EE 8 D 605008 O 9 8 5 128 PL NOTES 1 AAND B ARE DATUMS AND TIS A DATUM SURFACE 2 DIMENSIONING AND TOLERANCING PER Y14 5M 1982 3 CONTROLLING DIMENSION INCH MAX MIN MAX ee B 3404 3505 1 340 1 380 Tai LD 044 055
23. a cache entry can be replaced or allocated for that address depending on the state of the write allocate WA bit in the CACR 14 MC68030 TECHNICAL DATA MOTOROLA LONG WORD SELECT TAG INDEX Vendi pl FFFIIA AAAAAAAAAAAAAAAAAAAAAAAA 000 2222111111111100000000 00 ACCESS ADDRESS 21011 321098765432109876543210 Eme ed ES HE HAE ES ES ES ES Er TAG REPLACE DATA FROM DATA CACHE DATA BUS DATA TO EXECUTION UNIT ENTRY HIT CACHE CONTROL LOGIC COMPARATOR LINE HIT CACHE SIZE 64 LONG WORDS LINE SIZE 4 LONG WORDS SET SIZE 1 Figure 6 On Chip Data Cache Organization OPERAND TRANSFER MECHANISM The MC68030 offers three different mechanisms by which data can be trans ferred into and out of the chip Asynchronous bus cycles compatible with the asynchronous bus on the MC68020 can transfer data in a minimum of three clock cycles the amount of data transferred on each cycle is determined by the dynamic bus sizing mechanism on a cycle by cycle basis with the data transfer and size acknowledge DSACKx signals Synchronous bus cycles are terminated with the synchronous termination STERM signal and always trans fer 32 bits of data in a minimum of two clock cycles increasing the bus band width available for other bus masters therefore increasing possible performance Burst mode transfers can be used to fill lines of the instruction and data caches when the MC68030 a
24. as the following condition codes extend X negate zero 2 overflow V and carry C Additional control bits indicate that the processor is in the trace mode T1 or TO supervisor user state S and master interrupt state M MC68030 TECHNICAL DATA MOTOROLA SYSTEM BYTE USER BYTE 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0 o _ INTERRUPT SUPERVISOR PRIORITY MASK USER STATE MASTERANTERRUPT STATE EXTEND NEGATIVE ZERO OVERFLOW CARRY CONDITION CODES Figure 4 Status Register All microprocessors of the M68000 Family support instruction tracing via the TO status bit in the MC68030 where each executed instruction is followed by a trap to a user defined trace routine The MC68030 also has the capability to trace only on change of flow instructions branch jump subroutine call and return etc using the T1 status bit These features are important for software program development and debug Since the vector base register is used to determine the run time location of the exception vector table in memory it supports multiple vector tables thus each process or task can properly manage exceptions independent of each other The M68000 Family processors distinguish address spaces as supervisor user program data and CPU space These five combinations are specified by the function code pins 1 2 during bus cycles ind
25. convection and no heatsink Characteristic Natural Convection and No Heatsink Thermal Resistance PGA Package PPGA Package Package Resistance is to bottom center pin side of case for PGA and PPGA packages top center of case for COFP package COFP Package Table 6 provides typical and worst case thermal charastics for the COFP package both with and without a heatsink The heatsink used is black anodized alluminum alloy 0 72 x0 75 x0 6 high with an omnidirectional 5x6 array of fins Attachment was made using Epolite 6400 one part epoxy Table 6 0JA Vs Airflow COFP package Airflow in linear feet minute 200 50 Maximum estimated No Heatsink 46 With Heatsink 35 No Heatsink 43 25 With Heatsink 32 17 Natural convection Table 7 shows the maximum allowable ambient temperature C assuming operation at maximum junction temperature power dissipation and 6jA These worst case operating conditions are used for thermal management design Table 7 Maximum Ambient Temperature C vs Airflow and Rated Frequency COFP Package Rated Pp Maximum No Heatsink With Heatsink Frequency at Ty Airflow in linear Airflow in linear Maximum feet minute feet minute M E ee LE 31 62 69 37 65 72 54 78 81 52 74 79 65 84 87 57 78 82 70 87 89 Natural convection MOTOROLA MC68030 TECHNICAL DATA 31 Table 8 shows typical operating conditions both with and without a heat
26. ctions gt The 18 addressing modes listed Table 1 include nine basic types Register Direct Register Indirect Register Indirect with Index Memory Indirect Program Counter Indirect with Displacement Program Counter Indirect with Index Program Counter Memory Indirect Absolute Immediate OONDORWH MC68030 TECHNICAL DATA MOTOROLA The register indirect addressing modes support postincrement predecrement offset and indexing These capabilities are particularly useful for handling advanced data structures common to sophisticated applications and high level languages The program counter relative mode also has index and offset ca pabilities this addressing mode is generally required to support position independent software In addition to these addressing modes the MC68030 provides data operand sizing and scaling these features provide performance enhancements for the programmer Table 1 Addressing Modes Addressing Modes Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement An An An d16 An Register Indirect with Index Address Register Indirect with Index 8 Bit Displacement Address Register Indirect with Index Base Displacement dg
27. cution Condition True False Instruction Manipulation Transfer Operation Word Transfer Words from Instruction Stream Exception Handling Take Privilege Violation If S Bit Not Set Take Pre Instruction Exception Take Mid Instruction Exception Take Post Instruction Exception General Operand Transfer Evaluate and Pass ea Evaluate ea and Transfer Data Write to Previously Evaluated ea Take Address and Transfer Data Transfer to from Top of Stack Register Transfer Transfer CPU Register Transfer CPU Control Register Transfer Multiple CPU Registers Transfer Multiple Coprocessor Registers Transfer CPU SR and or ScanPC 26 MC68030 TECHNICAL DATA MOTOROLA SIGNAL DESCRIPTION Figure 8 illustrates the functional signal groups and Table 5 describes the signals and their function z e FUNCTION lt FOF CODES 5 r ADDRESS RM IPL2 INTERRUPT BUS IPEND CONTROL BUS 5120 TRANSFER 5171 BG BUS ARBITRATION SIZE BGACK CONTROL OCS RESET ECS HALT BUS EXCEPTION RW 68030 BERR CONTROL RMC ASYNCHRONOUS AS STERM SYNCHRONOUS BUS CONTROL DS BUS CONTROL DBEN REFILL DSACKO STATUS EMULATOR DSACK1 CDIS SUPPORT MMUDIS CIOUT CAS CONTROL CBREQ 10 GND 14 Figure 8 Functional Signal Groups MOTOROLA MC68030 TECHNICAL DATA 27 Signal Name Function Codes Address Bus Operand Cycle Start External Cycle Start Read Write Read Modify Write Cycle Address Strobe
28. d as shown Inputs to the MC68030 are specified with minimum and as appropriate maximum setup and hold times and are measured as shown Finally the measurements for signal to signal specifications are also shown Note that the testing levels used to verify conformance of the MC68030 to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics MOTOROLA MC68030 TECHNICAL DATA 33 DC ELECTRICAL SPECIFICATIONS Vcc 5 0 5 GND 0 Vdc Temperature in defined ranges memes Input Low Voltage ViL GND 0 5 Input Leakage Current BERR BR BGACK CLK IPLO IPL2 AVEC 25 25 GND lt Vin lt CDIS DSACKO DSACK1 HALT RESET 20 20 Hi Z Off State Leakage Current A0 A31 AS DBEN DS 00 031 FCO FC2 Igi 20 20 pA 9 2 4 V 0 5 V RAV 5120 5121 d eal n Sl Output High Voltage A0 A31 AS BG 00 031 DBEN DS ECS RAW IPEND 400 pA OCS 5120 5121 FCO FC2 CBREO CIOUT STATUS REFILL Output Low Voltage 01 3 2 mA A0 A31 FCO FC2 5120 5171 00 031 Ig 5 3 mA CBREO AS DS RAW RMC DBEN IPEND 01 72 0 mA STATUS REFILL CIOUT EE oes 10 7 Capacitance see Note Vin 9 V Ta 25 C f 1 MHz Load Capacitance ECS OCS CIOUT STATUS REFILL All Other NOTE Ca
29. egister VBR to determine the memory address of the exception vector The new program counter is fetched from the exception vector The instruction at the address given in the exception vector is fetched and normal instruction de coding and execution is started STATUS and REFILL The MC68030 provides the STATUS and REFILL signals to identify internal microsequencer activity associated with the processing of pipelined data Since bus cycles are independently controlled and scheduled by the bus controller information concerning the processing state of the microsequencer is not avail able by monitoring bus signals by themselves The internal activity identified by the STATUS and REFILL signals include instruction boundaries some ex ception conditions when the microsequencer has halted and instruction pipe line refills STATUS and REFILL track only the internal microsequencer activity and are not directly related to bus activity ON CHIP MEMORY MANAGEMENT UNIT The full addressing range of the MC68030 is 4 Gbytes 4 294 967 296 bytes however most MC68030 systems implement a smaller physical memory None theless by using virtual memory techniques the system can be made to appear to have the full 4 Gbytes of physical memory available to each user program In a similar fashion a virtual system provides user program access to other devices not physically present in the system such as tape drives disk drives MOTOROLA MC68030 TEC
30. eglected is Solving Equations 1 and 2 for K gives TJ4273 C 2 TA 273 C 0JA P p 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at thermal equilibrium for a known TA Using this value of the values of Pp and Ty can be obtained by solving equations 1 and 2 iteratively for any value of Ta The total thermal resistance of a package 0JA can be separated into two components 0JC and OCA represents the barrier to heat flow from the semiconductor junction to the package case surface and represents the barrier to heat flow from the case to the ambient air These terms are related by the equation 30 MC68030 TECHNICAL DATA 0JA 0JC 4 MOTOROLA is device related and cannot be influenced by the user However is user dependent and can be minimized by such thermal management techniques as heat sinks forced air cooling and use of thermal convection to increase air flow over the device Thus good thermal design on the part of the user can significantly reduce so that approximately equals 0Jc Substitution of for OJA in equation 1 results a lower semiconductor junction temperature Thermal Resistance C W The following table provides thermal resistance characteristic for junction to ambient and junction to case for the different packages with natural
31. ernal bus port on a cycle by cycle basis and are used for asyn chronous transfers STERM Bus response signal that indicates a port size of 32 bits and that data may be latched on the next falling clock edge CIIN Prevents data from being loaded into the MC68030 instruction and data caches IOUT Reflects the bit in entries or TTx register in dicates that external caches should ignore these ac cesses BREQ Indicates a burst request for the instruction or data cache CBACK Indicates that the accessed device can operate in burst mode 0 IPL2 i VEC BG L Provides an encoded interrupt level to the processor Indicates that an interrupt is pending AVEC JPLOHPL2 Requests autovector during an interrupt acknowl edge cycle L Indicates that an external device reguires bus master ship Indicates that an external device may assume bus mastership MC68030 TECHNICAL DATA MOTOROLA Table 5 Signal Index Continued Signal Name Mnemonc Function Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership Rest RESET System reset RESET Halt HALT Indicates that the processor should suspend bus ac tivity Bus Error BERR Indicates that an erroneous bus operation is being at tempted CDIS K D Pipe Refill REFILL Indicates when the MC68030 is beginning to fill pipe line Ground connection Cache Disable
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33. for all other specifications are used to calculate a typical junction temperature for reliability analysis 32 MC68030 TECHNICAL DATA MOTOROLA Table 11 Typical Junction Temperature for Operation at TA Max above PGA Package Rated Pp Typical No Heatsink With Heatsink Frequency Airflow in linear feet minute Airflow in linear Watts 0 200 400 64 EBEN 5 e feet minute e 21202000 IKS _ e e Natural Convection Values for thermal resistance presented in this document were derived using the procedure described in Motorola Reliability Report 7843 Thermal Resistance Measurement Method for MC68XX Microcomponent Devices and are provided for design purposes only Thermal measurements are complex and dependent on procedure and setup User derived values for thermal resistance may differ AC ELECTRICAL SPECIFICATIONS DEFINITIONS The AC specifications presented consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of the MC68030 clock input and possibly relative to one or more other signals The measurement of the AC specifications is defined by the waveforms in Figure 9 To test the parameters guaranteed by Motorola inputs must be driven to the voltage levels specified in Figure 9 Outputs of the MC68030 are specified with minimum and or maximum limits as appropriate and are measure
34. icating the particular address space Using the function codes the memory subsystem hardware can distinguish between supervisor accesses and user accesses as well as program accesses data accesses and CPU space accesses Additionally the system software can configure the on chip MMU so that supervisor user priv ilege checking is performed by the address translation mechanism and the lookup of translation descriptors can be differentiated on the basis of function code To support the full privileges of the supervisor the alternate function code registers allow the supervisor to specify the function code for an access by appropriately preloading the SFC DFC registers The cache registers allow supervisor software manipulation of the on chip instruction and data caches Control and status accesses to the caches are provided by the cache control register CACR the cache address register CAAR specifies the address for those cache control functions that require an address MOTOROLA MC68030 TECHNICAL DATA 7 All MMU registers CRP SRP 0 1 and MMUSR accessible by the supervisor only The central processor unit CPU root pointer contains a descriptor for the first pointer to be used in the translation table search for page descriptors pertaining to the current task If the supervisor root pointer enable SRE bit of the translation control register is set the supervisor root pointer is used as a pointer to the translat
35. ion tables for all supervisor accesses If the SRE bit is clear this register is unused and the CPU root pointer is used for both supervisor and user translations The translation control register con figures the table lookup mechanism to be used for all table searches as well as the page size and any initial shift of logical address required by the operating system In addition this register has an enable bit that enables the MMU The transparent translation registers can be used to define two transparent windows for transferring large blocks of data with untranslated addresses Finally the MMU status register MMUSR contains status information related to a specific address translation and the results generated by the PTEST instruction This information can be useful in locating the cause of an MMU fault DATA TYPES AND ADDRESSING MODES Seven basic data types are supported by the MC68030 Bits Bit Fields String of consecutive bits 1 32 bits long BCD Digits Packed 2 digits byte Unpacked 1 digit byte Byte Integers 8 bits Word Integers 16 bits Long Word Integers 32 bits Quad Word Integers 64 bits In addition operations on other data types such as memory addresses status word data etc are provided in the instruction set The coprocessor mechanism allows direct support of floating point data types with the MC68881 MC68882 floating point coprocessors as well as specialized user defined data types and fun
36. ister two 32 bit transparent translation registers and a 16 bit MMU status register Registers 00 07 are used as data registers for bit and bit field 1 to 32 bit byte 8 bit word 16 bit long word 32 bit and quad word 64 bit operations Registers A0 A6 and the user interrupt and master stack pointers are address registers that may be used as software stack pointers or base address registers In addition the address registers may be used for word and long word operations All 16 general purpose registers D0 D7 A0 A7 can used as index registers 31 16 15 8 7 0 DATA REGISTERS 31 16 15 0 AO Al A2 ADDRESS REGISTERS 21 ls KAS USP POINTER 31 0 PROGRAM 21 15 7 0 OL LEES CONDITION CODE MET ON j CCR REGISTER Figure 2 User Programming Model MOTOROLA MC68030 TECHNICAL DATA 5 ISP STACK POINTER 31 16 15 0 MSP STACK POINTER 15 8 7 0 STATUS CCR SR REGISTER 31 0 VECTOR 2 eR Rasen apra ae 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS 31 0 CACHE CONTROL 2 en 31 0 CACHE ADDRESS 22 BES ui 63 32 CPU ROOT POINTER 63 92 285 SUPERVISOR POINTER REGISTER 31 0 REGISTER 31 0 REGISTER 0 31 0 TRANSPARENT TRANSLATION REGISTER 1 15 0 Jes Figure 3 Supervisor Programming Model Supplement The status register see Figure 4 contains the interrupt priority mask three bits as well
37. lization characteristics A DMA coprocessor can control the bus independent of the main processor A non DMA coprocessor cannot control the bus Both coprocessor types utilize the same protocol and main processor resources Implementation of a copro cessor as a or non DMA is based primarily on coprocessor bus bandwidth requirements performance and cost The communication protocol between the main processor and the coprocessor necessary to execute a coprocessor instruction is based on a group of copro cessor interface registers CIRs which are defined for the M68000 Family see Table 3 and are implemented on the coprocessor The MC68030 hardware uses standard read and write cycles to access the registers Thus the copro cessor interface does not require special bus hardware the bus interface im plemented by a coprocessor for its interface register set must only satisfy the MC68030 address data and control signal timing to guarantee proper com munication with the CPU Since the MC68030 implements the communication protocol with all coprocessors in hardware and microcode and handles all operations automatically the programmer is only concerned with the instruc tions and data types provided by the coprocessor as extensions to the MC68030 instruction set and data types Table 3 Coprocessor Interface Registers Register Function RM Response Requests Action from CPU R Save Initiate Save of Internal State
38. n be latched by the processor in as little as one clock for each 32 bits Burst read cycles can be performed only when the MC68030 requests them with the assertion of CBREQ and only when the first cycle is a synchronous cycle as previously described If the cache burst acknowledge CBACK input is valid at the appropriate time in the synchronous bus cycle the processor keeps the original AS DS R W address function code and size outputs as serted and latches 32 bits from the data bus at the end of each subsequent clock cycle that has STERM asserted This procedure continues until the burst is complete the entire block has been transferred BERR is asserted in lieu of or after STERM the cache inhibit in CIIN input is asserted or the CBACK input is negated MOTOROLA MC68030 TECHNICAL DATA 17 EXCEPTIONS The types of exceptions and the exception processing sequence are discussed in the following paragraphs TYPES OF EXCEPTIONS Exceptions can be generated by either internal or external causes The exter nally generated exceptions are interrupts bus error BERR and reset RESET Interrupts are requests from peripheral devices for processor action whereas BERR and RESET are used for access control and processor restart The inter nally generated exceptions come from instructions address errors tracing or breakpoints The TRAP TRAPcc TRAPVcc cpTRAPcc CKH2 and DIV instructions can all generate e
39. n used to generate the address of the exception vector The third step is to save the current processor status The exception stack frame is created and filled on the current supervisor stack To minimize the amount of machine state that is saved various stack frame sizes are used to contain the processor state depending on the type of exception and where it occurred MC68030 TECHNICAL DATA MOTOROLA during instruction execution If the exception is an interrupt and the bit is set the M bit is then cleared and the short four word exception stack frame that is saved on the master stack is also saved on the interrupt stack If the exception is a reset the M bit is simply cleared and the reset vector is accessed The MC68030 provides the same extensions to the exeption stacking process as the MC68020 If the M bit is set the master stack pointer MSP is used for all task related exceptions When nontask related exception occurs i e an interrupt the M bit is cleared and the interrupt stack pointer ISP is used This feature allows all the task s stack area to be carried within a single pro cessor control block and new tasks can be initiated by simply reloading the master stack pointer and setting the M bit The fourth and last step of exception processing is the same for all exceptions The exception vector offset is determined by mutliplying the vector number by four This offset is then added to the contents of the vector base r
40. not exist at all until they are required by the system ROOT POINTER gt POINTER TABLES E L f aM TABLES Figure 7 MMU Translation Table Structure The entries in the translation tables contain status information pertaining to the pointers for the next level of lookup or for the pages themselves These bits can be used to designate certain pages or blocks of pages as supervisor only write protected or noncachable If a page is marked as noncachable accesses within the page will not be cached by the instruction or data caches and the cache inhibit out CIOUT signal is asserted for those accesses In addition the MMU automatically maintains history information for the pointers and pages in the descriptors via the used U and modified M bits MC68030 TECHNICAL DATA MOTOROLA MMU INSTRUCTIONS The MMU instructions supported by the MC68030 the PMOVE PTEST PLOAD PFLUSH and PFLUSHA instructions are completely compatible with the cor responding instructions introduced by the MC68851 PMMU Whereas the 68851 required the coprocessor interface to execute its instructions the MC68030 MMU instructions execute just like all other CPU instructions All MMU instructions are privileged can be executed by the supervisor only and are summarized as follows PMOVE Used to move data to or from MMU registers PTEST Takes an address and function code and searches the ATC or the translation tables for the corresponding
41. omplished with the MC68020 The second design goal was to increase effective CPU throughput as larger memory sizes or slower memories increased average access time By placing a high speed cache between the processor and the rest of the memory system the effective memory access time becomes tacc h tcache 1 h text where tacc is the effective system access time tcache is the cache access time text is the access time of the rest of the system and h is the hit ratio or the percentage of time that the data is found in the cache Thus for a given system design two MC68030 on chip caches provide an even more substantial CPU performance increase over that obtainable with the MC68020 instruction cache Alternately slower and less expensive memories can be used for the same processor performance The throughput increase in the MC68030 is gained in three ways First the MC68030 caches are accessed in less time than is required for external accesses providing improvement in the access time for items residing in the cache Second the burst filling of the caches allows instruction and data words to be found in the on chip caches the first time they are accessed by the micro machine minimizing time required to bring those items into the cache Burst filling lowers the average access time for items found in the caches even further Third the autonomous nature of the caches allows instruction stream fetches data fetches and a third ex
42. on Decrement and Test Bit Field and Clear Branch Signed Bit Field Extract DIVS DIVSL Signed Divide Unsigned Bit Field Extract DIVU DIVUL ned Divide Bit Field Find First One Bit Field Insert Test Bit Field and Set Test Bit Field Sian Extend Breakpoint Branch ILLEGAL Take Illegal Instruction Trap Test Bit and Set JMP Jump Branch to Subroutine JSR Jump to Subroutine Test Bit Logical Exclusive OR 10 MC68030 TECHNICAL DATA MOTOROLA Table 2 Instruction Set Continued Load Effective Address Link and Allocate Logical Shift Left and Rio LSL LSR MOVEA MOVE CCR MOVE SR MOVE USP Move Address Move Condition Code Register Move Status Register Move User Stack Pointer MOVEC Move Control Register MOVEM Move Multiple Registers MOVEP Move Peripheral MOVEO Move Quick MOVES Move Alternate Address Space MULS Signed Multiply MULU Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement OR ORI ORI CCR Logical Inclusive OR Logical Inclusive OR Immediate Logical Inclusive OR Immediate to Condition Codes Logical Inclusive OR Immediate to Status Register PACK Pack BCD PEA Push Effective Address ORI SR Branch Conditionally Test Coprocessor Condition Decrement and Branch Coprocessor General Instruction PFLUSH PFLUSHA PLOADR PLOADW PMOVE PMOVEFD
43. pacitance is periodically sampled rather than 100 tested 34 MC68030 TECHNICAL DATA MOTOROLA DRIVE TO 2 4 V CLK DRIVE TO 0 5V 2 0V 20V VALID VALID OPIS EES OUTPUT OUTPUT 1 0 8 V 0 8 V VALID OUTPUT n VALID OUTPUTS 2 CLK OUTPUT n4 DRIVE TO gt 24V INPUTS 3 CLK DRIVETO gt 0 5V DRIVE 5 1024 INPUTS 4 CLK DRIVE 7 T005V 20V ALL SIGNALS 5 08V E F 20V 08V NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This output timing is applicable to all parameters specified relative to the falling edge of the clock 3 This input timing is applicable to all parameters specified relative to the rising edge of the clock 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters specified relative to the assertion negation of another signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Signal valid to signal valid specification maximum or minimum F Signal valid to signal invalid specification maximum or minimum Figure 9 Drive Levels and Test Points for AC Specifications MOTOROLA MC68030 TECHNICAL DATA 35 AC ELECTRICAL SPECIFICATIONS CLOCK INPUT see Figure 10 40 MH
44. process does not need to specify in advance the required areas of its logical address space An access to a logical address is interpreted by the system as a request for the corresponding page The MC68030 MMU employs the same address translation mechanism intro duced by the MC68851 PMMU with possible page sizes ranging from 256 bytes to 32K bytes TRANSLATION MECHANISM 20 Since logical to physical address translation is the most frequently executed operation of the MC68030 MMU this task has been optimized and can function autonomously The MMU initiates address translation by searching for the address translation information a page descriptor in the on chip address trans lation cache ATC The ATC is a very fast fully associative cache memory that stores recently used page descriptors If the descriptor does not reside in the ATC then the MMU requests external bus cycles of the bus controller to search the translation tables in physical memory After being located the page de scriptor is loaded into the ATC and the address is correctly translated for the access if no exception conditions are encountered MC68030 TECHNICAL DATA MOTOROLA status of the page question is easily maintained the translation tables When a page must be brought in from a secondary storage device the table entry can signal that this descriptor is invalid so that the table search results in an invalid descriptor being loaded into the ATC In
45. ret ear is BERR LY CIOUT D 5 m Figure 12 Asynchronous Write Cycle Timing Diagram 42 68030 TECHNICAL DATA MOTOROLA iz men X K 5121 5120 8 D e KO NS R D Wis DBEN IA B CIOUT DSACKO DSACK1 STERM 60 UA VY D D31 D0 Figure 13 Synchronous Read Cycle Timing Diagram MOTOROLA MC68030 TECHNICAL DATA 43 AK A31 A0 FC2 FCO 5 5171 5120 gt 5 RMC amp 2 te o 5 DEEN 8 k DSACKO DSACK1 o TERM G zu CBREQ Figure 14 Synchronous Write Cycle Timing Diagram 44 MC68030 TECHNICAL DATA MOTOROLA 5 51 S2 53 54 55 CLK we XS DSACKO DSACK1 BR poer 7 abe BG Na NOTE Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 8 V and 2 0 V Figure 15 Bus Arbitration Timing Diagram MOTOROLA MC68030 TECHNICAL DATA 46 CLK IPEND MMUDIS CDIS STATUS REFILL Figure 16 Other Signal Timings MC68030 TECHNICAL DATA MOTOROLA MECHANICAL DATA PIN ASSIGNMENTS 128 Lead Pin Grid Array RC and RP Suffix N O O O O O O O O O D31 D28 D26 025 023 021 019 018 016 MI Or 0O 0O 0O 0 0 0 0 DBEN EC
46. s the 32 bit address and data paths rich instruction set versatile addressing modes and flexible coprocessor interface provided with the MC68020 In addition the internal operations of this integrated processor are designed to operate in parallel allowing multiple instructions to be executed concurrently It allows instruction execution to proceed in parallel with accesses to the internal caches the on chip MMU and the bus controller The MC68030 fully supports the nonmultiplexed asynchronous bus of the MC68020 as well as the dynamic bus sizing mechanism that allows the pro cessor to transfer operands to or from external devices while automatically determining device port size on cycle by cycle basis In addition to the asyn chronous bus the MC68030 also supports a fast synchronous bus for off chip caches and fast memories Furthermore the MC68030 bus is capable of fetching up to four long words of data in a burst mode compatible with DRAM chips that have burst capability Burst mode can reduce up to 50 percent the time necessary to fetch the four long words The four long words are used to prefill the on chip instruction and data caches so that the hit ratio of the caches is improved and the average access time for operand fetches is minimized MC68030 TECHNICAL DATA MOTOROLA The block diagram shown Figure 1 depicts the major sections of the 68030 and illustrates the autonomous nature of these blocks The bus controller con
47. sink maximum ambient temperatures calculated in the previous worst case analysis and typical values for all other specifications are used to calculate typical junction temperatures for reliability analysis Table 8 Typical Junction Temperature for Operation at Ta Max above COFP Package Rated Pp Typical No Heatsink With Heatsink Frequency Airflow in linear Airflow in linear feet minute feet minute Watts 33 71 25 Natural convection PGA Package Table 9 provides typical and worst case thermal charastics for the COFP package both with and without a heatsink Table 9 Oja Vs Airflow PGA package Airflow in linear feet minute 0JA Maximum estimated No Heatsink With Heatsink Typical estimated No Heatsink With Heatsink Natural Convection Table 10 shows the maximum allowable ambient temperature C assuming operation at maximum junction temperature power dissipation and 0JA These worst case operating conditions are used for thermal management design Table 10 Maximum Ambient Temperature C vs Airflow and Rated Frequency PGA Package Rated Pp Maximum No Heatsink With Heatsink Frequency at TJ Airflow in linear Airflow in linear Maximum feet minute feet minute Natural Convection Table 11 shows typical operating conditions both with and without a heatsink The maximum ambient temperatures calculated in the previous worst case analysis and typical values
48. sserts cache burst request CBREQ After completing the first cycle with STERM subsequent cycles may accept data on every clock cycle where STREM is asserted until the burst is completed Use of this mode can MOTOROLA MC68030 TECHNICAL DATA 15 further increase the available bus bandwidth in systems that use DRAMs with page nibble or static column mode operation ASYNCHRONOUS TRANSFERS Though the MC68030 has a full 32 bit data bus it offers the ability to auto matically and dynamically downsize its bus to 8 or 16 bits if peripheral devices are unable to accommodate the entire 32 bits This feature allows the pro grammer to write code that is not bus width specific For example long word 32 bit accesses to peripherals may be used in the code yet the MC68030 will transfer only the amount of data that the peripheral can manage at one time This feature allows the peripheral to define its port size as 8 16 or 32 bits wide and the MC68030 will dynamically size the data transfer accordingly using multiple bus cycles when necessary Hence programmers are not required to program for each device port size or know the specific port size before coding hardware designers have the flexibility to choose hardware implementations regardless of software implementations The dynamic bus sizing mechanism is invoked by DSACKx and occurs on a cycle by cycle basis For example if the processor is executing an instruction that requires the reading
49. st rate possible for each device MC68030 TECHNICAL DATA MOTOROLA asynchronous transfer mechanism allows external errors to abort cycles upon the assertion of bus error BERR or allows individual bus cycles to be retried with the simultaneous assertion of BERR and HALT SYNCHRONOUS TRANSFERS Synchronous bus cycles are terminated by asserting STERM which automat ically indicates that the port size is 32 bits Since this is asynchronous input two clock cycle bus accesses can be performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup time However the bus cycle may be lengthened by delaying STERM inserting wait states in one clock increments until the device being accessed is able to terminate the cycle Additionally these cycles may be aborted upon the assertion of BERR or they may be retried with the simultaneous assertion of BERR and HALT BURST READ CYCLES The MC68030 provides support for burst filling of its on chip instruction and data caches adding to the overall system performance The on chip caches are organized with a line size of four long words with one tag for the four long words in a line Since locality of reference is present to some degree in most programs filling of all four entries when a single entry misses can be advan tageous especially if the time spent filling the additional entries is minimal When the caches are burst filled data ca
50. ternal access to occur simultaneously with instruc tion execution For example if the 68030 requires both an instruction stream access and an external peripheral access and if the instruction is resident in the on chip cache the peripheral access proceeds unimpeded rather than being queued behind the instruction fetch If a data operand is also required and is resident in the data cache it can also be accessed without hindering either the MC68030 TECHNICAL DATA MOTOROLA instruction access or the external peripheral access The parallelism designed into the MC68030 also allows multiple instructions to execute concurrently so that several internal instructions those that do not require any external ac cesses can execute while the processor is performing an external access for a previous instruction INSTRUCTION CACHE MC68030 instruction cache is a 256 byte direct mapped cache organized as 16 lines consisting of four long words per line Each long word is inde pendently accessible yielding 64 possible entries with address bit A1 selecting the correct word during an access Thus each line has a tag field composed 24 address bits the FC2 supervisor user value four valid bits one for each long word entry and the four long word entries see Figure 5 The instruction cache is automatically filled by the MC68030 whenever a cache miss occurs using the burst transfer capability up to four long words can be filled in one
51. ully as sociative cache called the address translation cache ATC allowing address translation and other MC68030 functions to occur simultaneously Additionally the MC68030 contains two transparent translation registers that be used to define a one to one mapping for two segments ranging in size from 16 Mbytes to 2 Gbytes each MOTOROLA MC68030 TECHNICAL DATA 3 VLVd 0 0892IN VIOHOLON ADDRESS BUS lt a ADDRESS PADS PHYSICAL ADDRESS L MMU WRITE PENDING BUFFER MICROBUS CONTROLLER BUS CONTROL SIGNALS BUS CONTROLLER PREFETCH PENDING BUFFER INSTRUCTION ADDRESS LOGICAL ADDRESS E MICROSEQUENCER AND CONTROL INSTRUCTION PIPE STAGE STAGE STAGE S M ES TA INTERNAL CONTROL LOGIC DATA BUS INSTRUCTION CACHE BUS C PADS SIZE MULTIPLEXER MISALIGNMENT MULTIPLEXER DATA CACHE Figure 1 MC68030 Block Diagram DATA BUS PROGRAMMING MODEL As shown in the programming models see Figures 2 and 3 the MC68030 has 16 32 bit general purpose registers a 32 bit program counter two 32 bit super visor stack pointers a 16 bit status register a 32 bit vector base register two 3 bit alternate function code registers two 32 bit cache handling address and control registers two 64 bit root pointer registers used by the MMU a 32 bit translation control reg
52. urther processing of the instruction The communication is terminated and the main processor is free to begin execution of the next instruction At this point in the coprocessor protocol as the main processor contin ues to execute the instruction stream the main processor may operate concurrently with the coprocessor MOTOROLA MC68030 TECHNICAL DATA 25 When the main processor encounters the next coprocessor instruction the main processor queries the coprocessor until the coprocessor is ready mean while the main processor can service interrupts and perform a context switch to execute other tasks Each coprocessor instruction type has specific requirements based on this simplified protocol The coprocessor interface may use as many extension words as required to implement a coprocessor instruction PRIMITIVE RESPONSE The coprocessor response register communicates service requests to the main processor The content of the coprocessor response register is a primitive Instruction to the main processor which is read during coprocessor commu nication by the main processor The main processor executes this primitive thereby providing the services required by the coprocessor Table 4 summarizes the coprocessor primitives accepted by the MC68030 Table 4 Coprocessor Primitives Processor Synchronization Busy with Current Instruction Proceed with Next Instruction If No Trace Service Interrupts and Requery If Trace Enabled Proceed with Exe
53. xceptions as part of instruction execution Tracing behaves like a very high priority internally generated interrupt whenever it is processed The other internally generated exeptions are caused by illegal in structions instruction fetches from odd addresses and privilege violations Finally the MMU can generate exceptions when it detects an invalid translation in the address translation cache ATC and an access to the corresponding address is attempted or when it is unable to locate a valid translation for an address in the translation tables EXCEPTION PROCESSING SEQUENCE 18 Exception processing occurs in four steps During the first step an internal copy is made of the status register After the copy is made the special processor state bits in the status register are changed 5 bit is set putting the cessor into the supervisor state Also the T1 and TO bits are negated allowing the exception handler to execute unhindered by tracing For the reset and interrupt exceptions the interrupt priority mask is also updated In the second step the vector number of the exception is determined For interrupts the vector number is obtained by a processor read that is classified as an interrupt acknowledge cycle For coprocessor detected exceptions the vector number is included in the coprocessor exception primitive response For all other exceptions internal logic provides the vector number This vector number is the
54. ynchronous Hold 2912 5 DS Negated to Data In Invalid Asynchronous Hold 29412 AS DS Negated to Data In 30 25 _ High Impedance 3012 Low to Data In Invalid 12 Synchronous Hold 30A12 Clock Low to Data In High Impedance Read followed by Write DSACKx Asserted to Data In 43 28 20 Valid Asynchronous Data Setup 31A3 DSACKx Asserted to DSACKx 10 Valid CEA ccc pessum Kara Kara Ka e e dede Tas tcck tow o BE epe ape fefe ess RMC Not Asserted 37 BGACK Asserted to BG sica e eem Tarno BOACK memi BR o 15 o is 15 o 15 40 Clock High to DBEN Asserted 25 20 14 Read 28A12 N 38 68030 TECHNICAL DATA MOTOROLA AC ELECTRICAL SPECIFICATIONS continued Clock Low to DBEN Negated Read Clock Low to DBEN Asserted Write Clock High to Negated Write R W Low to DBEN Asserted Write DBEN Width Asserted Asynchronous Read Asynchronous Write DBEN Width Asserted 41 42 43 44 5 455 30 22 20 60 45 40 30 45A9 Synchronous Read Synchronous Write R W Width Asserted Asynchronous Write or Read 46A R W Width Asserted Synchronous 75 45 30 25 Write or Read e N R RB c N E 1 Es Ei E Lr LX E 47A Asynchronous Input Setup Time to Clock Low As
55. ynchronous Input Hold Time 12 from Clock Low DSACKx Asserted to BERR HALT Asserted Data Out Hold from Clock High R W Asserted to Data Bus 25 Impedance Change RESET Pulse Width Reset Instruction BERR Negated to HALT Negated Rerun 5810 Negated to Bus Driven BG Negated to Bus Driven 6013 Synchronous Input Valid to pi Clock High Setup Time 6113 High to Synchronous Input Invalid Hold Time Clock Low to STATUS REFILL Asserted k Cloc Low to STATUS REFILL Negated Ei bal Gt S d fl ud et ad Pee Ga Kad ad ed add a a ee 2 47 484 53 L Ro IH IB 5 55 56 57 62 63 MOTOROLA MC68030 TECHNICAL DATA 39 ELECTRICAL SPECIFICATIONS conciudea NOTES Temperature must be in the range described in MAXIMUM RATINGS 1 2 10 11 12 13 14 40 This number be reduced to 5 ns if strobes have equal loads If the asynchronous setup time 47A requirements are satisfied the DSACKx low to data setup time 31 and DSACKx low to BERR low setup time 48 can be ignored The data must only satisfy the data in clock low setup time 27 for the following clock cycle and BERR must only satisfy the late BERR low to clock low setup time 27A for the following clock cycle
56. z 50 MHz pinami pus res as as pes 2 o os o we wu oo ao so zs o Clock Pulse Width Measured 23 57 61 14 36 11 5 29 9 5 30 5 from 1 5 V to 1 5 V Clock Rise and Fall Times NOTE Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 8 V and 2 0 V Figure 10 Clock Input Timing Diagram 36 MC68030 TECHNICAL DATA MOTOROLA AC ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES Vcc 5 0 5 GND 0 Temperature in defined ranges Characteristic ee eee a Min Max Max E Te ia Size RMC IPEND CIOUT Address Valid as o 10 ns Function Code Size RMC IPEND CIOUT Address ___ Valid to Negating Edge of ECS Clock High to Function Code Size RMC CIOUT Address Data High Impedance Clock High to Function Code Size RMC IPEND CIOUT Address Invalid Low AS DS Asserted 20 3 18 2 2 2 10 o Valid to DS Assertion Skew IAS to DS Assertion Skew Read 10 10 9814 5 Asserted to DS Asserted 32 27 22 E Write e TTT S ECA ECB EA ESI MEMSEIEIEAERERESERESER ERES Function Code Size RMC CIOUT 5 Address Valid to Asserting Edge of
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