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1. nenne 29 NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 6 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 TABLE 3 4 ADDRESS MAP IN MCST OPERATIONS eseeeeeeeeeeeetnenee enne nennen nnne nnne enn 29 TABLE 5 1 WORD TYPE IN THE MULTI EVENT 2 4 enne enne enne nn nnne 57 NPO Filename 00103 99 TAPSy MUTx 01 V874A REVI DOC Number of pages Page 67 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 1 General description 1 1 Overview The Model V874 Ais a 1 unit wide VME 6U module housing 4 general purpose channels The outputs of the channels analog sections are converted by a fast 12 bit ADC module 10 us for all channels The ADC module uses a sliding scale technique to reduce the differential non linearity Programmable zero suppression multievent buffer memory trigger counter and test features complete the flexibility of the unit The module works in A32 and GEO mode The data transfer occurs in D16 D32 BLT32 or MBLT64 mode The unit supports also
2. NN RR us bb EN 34 NPO Filename Number of pages Page 3 00103 99 5 01 V874A REVI DOC 67 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 11 INTERRUPT LEVEL REGISTER hn ei dep here tri BER dde e en pd pe erre e repetat 35 3 12 INTERRUPT VECTOR REGISTER BIAN NAN BAN EN NA NN debt AN nana 35 3 13 STATUS REGISTER Ui sas nh ata bana RA RN ANN 35 3 14 CONTROL REGISTER T ee ea ae AN ANA HA e ba bed ee te Nahan 37 3 15 ADDRESS DECODER REGISTER ee hedge tree ete t P repere terr epe 38 3 16 SINGLE SHOT RESET REGISTER UR WE REGE UR RR REC EA ee ERREUR 38 3 17 MEST CBET CONTROL nada 38 3 18 SW REGISTER AANG SEN EN BNN EN SEN NN gn 39 3 19 EVENT TRIGGER REGISTER spin AR GA AN eter RAN i dde aeterne euh 39 3 20 STATUS REGISTER 2 is ASSET SOOO OSEE 39 3 21 EVENT COUNTER LOW REGISTER hi Aa an nana 40 3 22 EVENT COUNTER HIGH REGISTER 5 ena ata henna ede be pede Nada ade Naas 41 3 23 INCREMENT EVENT REGISTER nanah rp Hep gre ler ebbe rito e 41 3 24 INCREMENT OFFSET REGISTER aon entes ene tet nente tenente toten ente testen ete ten tne retento tese ene ne tenerent 41 3 25 FAST CLEAR WI
3. 66 8 13 25 PPACKRA CING aa Po uan 13 222 13 2 3 EXTERNAL 8 1 15 2 3 1 ba c abad eiecti ioi 15 2 3 2 CONTROL CONNECHOL eccccccccccccsscccccccsssssscceccccssssssscceccccssssssscccsscececcsssccessscsssssssccsssccesssecsssssesessssssssesess 15 2 3 3 BE BEE EUR EE 16 2 4 OTHER FRONT PANEL COMPONENTS ecce edd dede da eere 17 2 4 T e PER san 17 2 5 INTERNAL HARDWARE 8 0 4 17 2 5 1 SW ee S Sereni certe e ao Nec mem Rer Ee ed CM 17 2 9 2 DUTP OTS ca usu UI ERA 18 2 6 BEREORMANGES AND TEST RESULTS e ee de RR 20 3 aee eee enin bee PER Re 21 ADDRESSING CAPABILITY S nee cite tete eere
4. 67 42 CAER Document type Title PRELIMINARY Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 TEST ACQ SLIDE ENABLE AUX BUS DIR COMM STOP AUTO INCR EMPTY PROG 0 low threshold check enabled only data above the threshold are written into the output buffer zero suppression default 1 low threshold check disabled all the data are written into the output buffer no zero suppression Allows to select the Acquisition Test Mode see 6 4 2 0 normal operation mode i e the data to be stored in the buffer are the real data default 1 Acquisition Test Mode selected i e the data to be stored in the buffer are taken from an internal FIFO Test Event Write Register see 3 32 Allows to enable disable the sliding scale 0 the sliding scale is disabled and the DAC of the sliding scale is set with a constant value Slide Constant see 3 39 1 the sliding scale is enabled default Allows to set the Auxiliary Bus direction see 3 42 0 Mother Board to Piggy Back Board 1 Piggy Back Board to Mother Board Allows to select the operation mode for the module The status of this bit corresponds to the level of the SSB pin of the J13 connector to the piggy back board see Fig 2 3 0 COMMON START mode selected default see 6 1 COMMON STOP mode selected see 6 Allows to enable disable the automatic
5. ener ennt 33 Fig 3 12 BITSET 1 REGISTER 5 ttr vtri BNN eee O 34 FIG 33 3 INTERRUPT LEVEL REGISTER ee nee rete eet bo se pete ue eo e robe ee rct e deed 35 FIG INTERRUPT VECTOR REGISTER oret eee dte idee edere ee eve ce teda 35 FIG 3 157 STATUS REGISTER rei ter re RR RI I e e T ET ER 36 Fic 3 16 CONTROL REGISTER T onenei Peri ERO BNN er e RR e nde E 37 EG 3 el 7 PADER REGISTER 38 FIG 3 18 MCST ADDRESS REGISTER onere ete ter nde e ee e eie dee ente etii de ede eden 38 3 19 EVENT TRIGGER REGISTER e tenete eene tenni ten S netten E E aiaee S 39 FIG 3 20 STATUS REGISTER 2 eee ote tcr He REESE RE BSK 40 EiG 3 21 EVENT COUNTER LOW REGISTER heme ae ANN ete e eve NN 40 E1G 3 22 EVENT COUNTER HIGH REGISTER ehe studs dle deter anang 41 3 23 BITSET 2 REGISTER 6 ete re IA te e i e e edens 42 Fic 3 24 W MEMORY TEST ADDRESS REGISTER sese enne ennt tenerte trennen nennen enne 44 E1G 3 25 TEST WORD REGISTER e e TH TANE NN LSN 44 FIG 3 26 TEST WORD LOW REGISTER ede e XP a edet dee lend E Eee e den 45 FIG 3 2 ECRATESBERCT REGISTER BARA NN BEE SEE SANKEN NE 45 FiG 3 28 TEST EVENT WRITE REGISTER nenene ar E EE E E E e a E 45 Fic 3 29
6. bee dea teer bet ea bue e 21 3 1 1 Addressing via Base Address moon 21 3 1 2 Addressing via GEOgraphical address esee 22 3 1 3 Base GEO addressing examples eee 22 3d 4 MESI CBET addressing t uada t e d CR 23 3 1 5 MCST CBLT addressing examples eee eese tentent tenente tenentes 24 3 2 VINTERRUPTER CAPABILITY na E ERE ERREUR URN EUER ia 26 3 12 15 s RR RA 26 eed Umen sema 26 292292 iJnierr pt Generation AE ERP d uere i eei uii idi Es 26 3 2 4 Interrupt Request 1 26 3 3 DATA TRANSEER CAPABILITY coc ete ier eere inre ee inen rte ene ie de een e eh ie ANN 27 3 4 REGISTER ADDRESS 0 0 27 3 5 OUTPUT BUFFER REGISTER 55555 NA EA MERE REGE RE NU UY 30 3 6 FIRMWARE REVISION REGISTER c ccsssccssscessscsssccsssscssssessscsssscsesscssssessssessecsssscssssssessessssessscessscssssessssesseces 32 3 1 JGBO ADDRESS REGISTER Nun 33 3 8 MCST CBLT ADDRESS REGISTER nana 33 PKN ALAN NANAH AR EN AN ANN Abe 34 3 10
7. 874 4 channel General Purpose Converter 15 01 2004 1 5 2 Analog to digital conversion The output of the analog sections is converted by a fast 12 bit ADC The ADC supports the sliding scale technique to reduce the differential non linearity see references 1 2 This technique see Fig 5 2 consists in adding a known value to the analog level to be converted thus spanning different ADC conversion regions with the same analog value The known level is then digitally subtracted after the conversion and the final value is sent to the threshold comparator If the sliding scale is enabled it reduces slightly the dynamic range of the ADC the 12 bit digital output is valid from 0 to 3840 while the values from 3841 to 4095 not correct OVER RANGE to the Control Logic Input channels to the memories SLIDE ZERO SLIDE ENABLE Fig 5 2 Block diagram of the sliding scale section 5 3 Zero suppression The output of the ADC is fed to a threshold comparator to perform the zero suppression If the converted value from a channel is greater than or equal to the relevant low threshold value set via VME in the Thresholds memory Base Address 0x1080 Ox10BE see 3 41 the result is fed to the dual port memory and will be available for the readout If the converted value is lower than the threshold the value is stored in the memory only if the LOW TRESHOLD PROG bit of the Bit Set 2 Register is set to
8. A write access with a bit set to 1 resets that bit e g writing 0x4 to this register resets the CLEAR DATA bit A write access with the bits set to 0 does NOT clear the register content The structure of the register is identical to the Bit Set 2 Register A read access returns the status of Bit Set Clear 2 Register 3 28 W Memory Test Address Register Base Address 0x1036 write only This register contains the address of the memory on which data can be written for the memory test W TEST ADDRESS 10 0 Fig 3 24 W Memory Test Address Register N B The output buffer is a FIFO so the read address R Test Address Register must be different from the write address W Test Address Register 3 29 Memory Test Word High Register Base Address 0x1038 write only The Memory Test Word is a 32 bit word used for the memory test The higher 16 bits are set via this register while the lower 16 bits are set via the Test Word Low Register These registers are used in TEST mode as follows set the module in test mode bit O of the Bit Set 2 Register see 6 3 26 write the memory address see 8 3 28 write the 16 MSBs in the TESTWORD HIGH register write the 16 LSBs in the TESTWORD LOW register With the latter operation the 32 bit pattern is transferred to the memory If operations 3 and 4 are inverted the content of the 16 MSBs may be meaningless TESTW
9. CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 9 Bit Set 1 Register 3 10 NPO Base Address 0x1006 read write This register allows to set the RESET logic of the module and to enable the change of the base address via VME A write access with the bits to 1 sets the relevant bits to 1 in the register i e writing Ox10 to this register sets the SEL ADDR bit to 1 A write access with the bits set to 0 does NOT clear the register content in order to clear the register content the Bit Clear 1 Register must be used see 3 10 A read access returns the status of this register The register content is the following Eg BERR FLAG SEL ADDR SOFT RESET Fig 3 12 Bit Set 1 Register BERR FLAG Bus Error Flag Bit meaningful in BLT CBLT modes only The user may set this flag for test purposes only Its content is cleared both via an hardware and via a software reset 0 board has not generated Bus Error default 1 board has generated Bus Error SELECT ADDRESS Select Address bit 0 base address is selected via Rotary Switches default 1 base address is selected via internal register SOFTW RESET Sets the module to a permanent RESET status The RESET is released only via write access with the relevant bit set to 1 in the Bit Clear Register see 3 10 This register is reset via
10. Set to 1 the Bit 6 TEST ACQ of the Bit Set 2 Register see S 3 26 this action selects the Acquisition Test Mode and resets the write pointer in the FIFO Set to 0 the Bit 6 TEST ACQ of the Bit Set 2 Register see S 3 26 this action resets the read pointer in the FIFO and releases the write pointer e Write 4 data words each word consisting of a 13 bit word corresponding to the ADC converted value the overflow bit see 3 32 in the Test Event Write Register Base Address Ox103E These data constitute the event to obtain as output of the channels The test data must be written in this FIFO in the same order as they will be read from the output buffer Set to 1 the Bit 6 TEST ACQ of the Bit Set 2 Register see S 3 26 this action resets again the write pointer in the FIFO and releases the read pointer at each COM signal an event based on the data previously written in the FIFO will be transferred to the output buffer The data will be read via VME in the same order as they were written into the FIFO N B To operate in normal mode again the Bit 6 of the Bit Set 2 Register must be set again to 0 NPO Filename Number of pages Page 00103 99 5 01 V874A 67 63 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 6 5 Block Transfer Mode NPO The module supports the Standard BLT32 and M
11. n tg Technical Information M anual Revision n 1 15 January 2004 MOD V 874A 4 CHANNEL GENERAL PURPOSE CONVERTER NPO 00103 99 T APSy M UTx 01 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 TABLE OF CONTENTS 1 5 bakalan 8 1 PLOVERVIEW tots treated tous 8 1 25 BEOCK DIAGRAM it eei see lode bee e BNN enakan 9 1 3 BUNGIIONAL DESCRIPTION ea e else elem us Na 10 1 4 TECHNICAL SPECIFICATION 12 2 TECHNICAL
12. Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 7 GEO Address Register Base Address 0x1002 read only This register contains the geographical address of the module i e the slot number picked up from the JAUX connector on the VME backplane The register is filled up upon arrival of a RESET The register content is the following GEO ADDR 0 GEO ADDR 1 GEO ADDR 2 GEO ADDR 3 GEO ADDR 4 Fig 3 10 Geographical address register GEO 4 0 corresponds to A23 A19 in the address space of the CR CSR area each slot has a relevant number whose binary encoding consists of the GEO ADDR 4 to 0 N B after a write access to the GEO register it is necessary to perform a reset to make the change active 3 8 MCST CBLT Address Register Base Address 0x1004 read write This register contains the most significant bits of the MCST CBLT address of the module set via VME i e the address used in MCST CBLT operations Refer to 3 1 4 for details about MCST CBLT addressing mode The register content is the following EEEEBEEBHEEBBBUE MCST CBLT ADDR 0 MCST CBLT ADDR 1 MCST CBLT ADDR 2 MCST CBLT ADDR 3 MCST CBLT ADDR 4 MCST CBLT ADDR 5 MCST CBLT ADDR 6 MCST CBLT ADDR 7 Fig 3 11 MCST CBL T address register Default setting i e at power on or after hardware reset is OxAA NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 33
13. e g some terminations are on and other are off 3 14 Control Register 1 Base Address 01010 read write This register allows performing some general settings of the module age BLKEND EED ENABLE PROG RESET BERR ENABLE L BLKEND EED ENABLE PROG RESET BERR ENABLE Fig 3 16 Control Register 1 End of Block bit Used in Block Transfer modes only 0 The module sends all requested data to the CPU when the Output Buffer is empty it will send no valid data If BERR_VME is enabled see bit 5 below BERR ENABLE a Bus Error is generated with the readout of the last word in the Output Buffer default 1 The module sends all data to the CPU until the first EOB word end of first event is reached afterwards it will send no valid data If BERR VME is enabled a Bus Error is generated at the readout of the EOB word Empty Event Discard bit Used in Chained Block Transfer only 0 Empty Events are manged as valid data during CBLT 1 Empty Events are loaded into the in order to keep data aligned but not read out during CBLT they are simply erased from the MEB Programmable Reset Mode setting bit 0 the front panel RESET acts only data data reset default 1 the front panel RESET acts on the module software reset N B This bit is cleared only via hardware reset Bus Error enable bit Used in Block Transfer mode only Present in Firmware Rev 04 06 and later NPO
14. the Event Counter is increased each time a pulse is sent through the COM input and acts also as an absolute time counter In the second case Mode B the Event Counter is increased each time a pulse sent through the COM input is accepted i e VETO FCLR and BUSY are not active The value of the Event Counter is stored in the EOB of the Multi Event Buffer see S 3 5 The Event Counter is also stored in two registers the Event Counter Low and Event Counter High Registers which respectively contain the 16LSBs and the 8MSBs of the Event Counter see 8 3 21 and 3 22 Busy Logic The board is BUSY either during the conversion sequence or during the reset of the analog section or when the MEB is not ready to accept data MEB Full or when the board is in Random Memory Access Test mode see 5 6 4 1 On the occurrence of one of these conditions the front panel BUSY signal CONTROL bus is active the red BUSY LED is on and the bit 2 BUSY and bit 3 GLOBAL BUSY of the Status Register 1 set to 1 see 3 13 The BUSY LED lights up also while the board is configuring power on The BUSY signal on the CONTROL bus allows to obtain a wired OR NAND GLOBAL BUSY signal of a chain of many units connected together via the CONTROL bus Actually each module sets to 1 its BUSY output at the occurrence of the leading edge of the trigger and drops it at the end of the conversion sequence When the module is busy it does not accept another trig
15. 1 6 4 1 Random Memory Access Test Mode This test mode allows the user to write and read a word in the output buffer To perform such test follow these steps 1 2 Set to 1 the Bit O of the Bit Set 2 Register see S 3 26 Write into the W Memory Test Address Register see 8 3 28 the 11 bit address where to write the test word Write the high and low part of the 32 bit test word respectively in the Testword High and Testword Low Registers see 3 29 and 3 30 As the Testword Low register is accessed the whole test word is written into the memory Write in the R Test Address Register see 3 34 the 11 bit reading memory address and read out the buffer please note that this address must be different from the write address written in the W Memory Test Address Register N B please note that the R Memory Test Address must be different from the W Memory Test Address at any step of the procedure If the user tries to write an address in one of these registers that is equal to the address contained in the other register write cycles step 3 above will not write the correct value 6 4 2 Acquisition Test Mode This test mode allows the user to simulate the real operation of the board without using any channel input signals but just writing the data into a FIFO via an appropriate register Test Event Write Register see 3 32 and reading them after a COM signal To operate the acquisition test follow these steps 1
16. 35 us with respect to the trailing edge of the COM signal it clears the analog sections of the unit and aborts completely the conversion in progress After a FAST CLEAR a COM signal can occur after 600 ns RST Electrical specifications active high diff ECL input signal min width 30 ns Function clears the analog sections resets the Multi Event Buffer status stops pending ADC conversions and depending on the user s settings see PROG RESET 83 14 may clear the control registers DRDY Electrical specifications diff ECL output signal Function wired OR NAND Global Data Ready signal from the boards belonging to the same chain on the CONTROL bus DATA READY indicates the presence of data in the output buffer of the board COMM Electrical specifications active high diff ECL input signal Function input pulse common to all channels to control data acquisition timing If a FAST CLEAR signal is sent in the following COM signal must occur at least about 600 ns after the FAST CLEAR signal TP Electrical specifications diff ECL signal min width 30 ns Function control output signal to the piggy back board NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 15 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 VETO Electrical specifications active high diff ECL input signal Function
17. D32 BLT32 MBLT64 CBLT32 and CBLT64 is available for the data buffer 3 4 Register address map The Address map for the Model V874 A is listed in Table 3 2 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address The Table gives also information about the effects of RESET on the registers In particular column 2 through 4 refer to the following RESET operations DR gt Data RESET e SR Software RESET e Hardware RESET If a register has a mark in these columns it means that the relevant RESET operation resets that register For further details on the RESET Logic please refer to 5 5 8 Table 3 3 and Table 3 4 list register addresses offset in CBLT and MCST operations respectively NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 27 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 Table 3 2 Address for the Model V874 Register content DR SR HR Address Type noces mode Output Buffer Y Y Y 0x0000 0x07FF Read only D32 D64 Firmware Revision 0x1000 Read only D16 Geo Address 0x1002 Read only D16 MCST CBLT Address Y 0x1004 Read Write D16 Bit
18. Examples B and D above is suggested only if the VME CPU can handle the Bus Error BERR in an effective way N B Please note that according to the VME standard a Block Transfer readout can be performed with 256 read cycles maximum as a consequence a readout with a greater number of read cycles may require more BLT operations This limit is not due to the board itself but only to the VME standard if it is possible to disable or delay the timeout of the BUS Timer BTO x a Block Transfer readout with more than 256 read cycles can be performed as well Filename Number of pages Page 00103 99 5 01 V874A 67 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 6 6 Advanced Setting and Readout Modes Chained Block Transfer CBLT and Multicast MCST operations allow to enhance the set and readout time of the 4 channels These operations allow accessing several boards at the same time CBLT operations are used for reading cycles only while MCST operations are used for write cycles only CBLT and MCST modes use the IACKIN and IACKOUT VME lines for the control transfer from one board to the following one the interrupt daisy chain is used to pass the token from one board to the following one see Ref 4 The board which has received the token stores sends the data from to the master via MCST CBLT accesses
19. Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 37 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 0 the module sends a DTACK signal until the CPU inquires the module default 1 the module is enabled to generate a Bus error to finish a block transfer Bits 6 to 15 are meaningless This register is reset both via software and via hardware reset see 5 8 except for the bit 4 PROG RESET which is reset only via hardware reset 3 15 Address Decoder Register Base Address 0x1012 read write This register contains A31 A24 bits of the address of the module it can be set via VME for a relocation of the Base Address of the module as described in Ref 4 The register content is the following e Fig 3 17 ADER Register 3 16 Single Shot Reset Register Base Address 0x1016 write only A write access to this dummy register performs a module reset This register must be used very carefully and for debugging purposes only In order to reset the board it is recommended to use the Bit Set 1 Register see 3 9 3 17 MCST CBLT Control Register NPO Base Address 0x101A write only This register allows performing some general MCST CBLT settings of the module ERES ED LAST BOARD FIRST BOARD Fig
20. No empty slots must thus be left in the chain or in alternative empty slots can be left only in case VME crates with automatic IACKIN IACKOUT short circuiting are used In order to perform CBLT and MCST cperations the higher Base Address bits of all the involved modules i e bits 31 to 24 must be set in common to all boards via the MCST CBLT Address Register see 3 8 This means that all boards must have the same setting on bits 31 to 24 The resulting MCST CBLT Base Address for all boards is MCST Base Address 000000 Once the addresses have been set the first and last board a chain must have respectively only the FIRST BOARD and only the LAST BOARD bit set to 1 in the MCST Control Register see 8 3 8 Conversely all intermediate boards must have both the FIRST BOARD and the LAST BOARD bits set either to 1 or to 0 For further details on the CBLT MCST addressing mode please refer to 3 1 4 and 3 1 5 6 6 1 Chained Block Transfer Mode NPO Once set the address of the boards as described in the above section the boards can be accessed in Chained Block Transfer mode CBLT see Ref 4 This mode allows for sequential readout of a certain number of contiguous boards in a VME crate A CBLT access is allowed with the BLT32 and MBLT64 address modifiers only CBLT32 and CBLT64 accesses respectively N B The CBLT operation can be performed only for the readout of the Multi Event Buffer its address
21. Nuclear Paris Nov 1963 G Bianchetti et al Specification for VMEbus CRATE Type V430 CERN EP January 1990 VME64 extensions draft standard Vita 1 1 199x draft 1 8 June 13 1997 VMEBus for Physics Application Recommendations amp Guidelines Vita23 199x draft 1 0 22 May 1997 Both documents are available from URL http www vita com NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 67
22. THE BOARD ADDRESS IN GEO MODE eee 22 Fic 3 2 BINARY HEXADECIMAL REPRESENTATION OF BIT SET 1 REGISTER ADDRESS IN GEO MODE 22 Fic 3 3 BASE GEO ADDRESSING EXAMPLE 1 ooooooooooo momo 23 Fic 3 4 MCST CBLT ADDRESSING EXAMPLE eere tenete nennen ente nennnn ene tenen eren nene tenete ea eese E e EEEN ea eE 25 Fic 3 5 OUTPUT BUFFER THE 5 go o OE IUOS Sana bhn ib REOS 30 FIG 3 6 OUTPUT BUFFER THE DATA WORD FORMAT eerte nne enitn nn 30 NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A_REV1 DOC 67 5 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 7 OUTPUT BUFFER THE END OF 30 Fic 3 8 OUTPUT BUFFER NOT VALID DATUM nisihi E a ennt 31 Fic 3 9 FIRMWARE REVISION REGISTER eria entente tete tinent ia manek 32 FIG 3 10 GEOGRAPHICAL ADDRESS 8 eterne nente nenn ennt ennt ennt 33 Fic 3 11 MCST CBLT ADDRESS REGISTER eerte nennen nennen nete ttes
23. a hardware reset see 5 8 Only the bit 3 BERR FLAG is reset both via hardware reset and software reset Bit Clear 1 Register Base Address 0x1008 read write This register allows to clear the bits in the above described Bit Set 1 Register A write access with a bit set to 1 resets that bit e g writing Ox4 to this register resets the BERR FLAG bit A write access with the bits set to 0 does NOT clear the register content The structure of the register is identical to the Bit Set 1 Register A read access returns the status of the Bit Set Clear 1 Register Filename Number of pages Page 00103 99 5 01 V874A 67 34 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 11 Interrupt Level Register Base Address 0x100A read write The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless Default setting is 0x0 In this case interrupt generation is disabled Fig 3 13 Interrupt Level Register 3 12 Interrupt Vector Register Base Address 0x100C read write This register contains the value of the Interrupt STATUS ID that the V874 A INTERRUPTER places on the VME data bus during the Interrupt Acknowledge cycle Bits 8 to 15 are meaningless Default setting is 0 00 Fig 3 14 Interrupt Vector Register 3 13 Status Register 1 Base
24. bits are reset with the same type of RESET see the description of the relevant register for details NPO Filename Number of pages Page 00103 99 5 01 V874A 67 28 CAER Document type User s Manual MUT PRELIMINARY Revision date Revision 15 01 2004 1 Title Mod V874A 4 channel General Purpose Converter Table 3 3 Address Map in CBLT operation Register content Address Access mode Type Output Buffer 0x0000 0x07FF Read only D32 D64 Table 3 4 Address Map in MCST operations Register content Address Type Access mode Bit Set 1 0x1006 Write only D16 Bit Clear 1 0x1008 Write only D16 Interrupt Vector 0x100C Write only D16 ADER 0x1012 Write only D16 SW Berr 0x101C Write only D16 Increment Event 0x1028 Write only D16 Load Test Register 0x102C Write only D16 0x102E Write only D16 Bit Set 2 0x1032 Write only D16 W Memory Test Address 0x1036 Write only D16 0x1038 Write only D16 Memory Test Word Low 0x103A Write only D16 0x103C Write only D16 Event Counter Reset 0x1040 Write only D16 0x1060 Write only D16 0x1062 Write only D16 Clear Time 0x1066 Write only D16 0x1068 Write only D16 Slide Constant 0x106A Write only D16 0x1080 OX10BF Write only D16 AUX Bus 0x1200 Ox12FF Write only D16 NPO Filename Number of pages Page 00103 99 5 01 V874A 67 29 CAER Document type User
25. contains the low threshold and kill option for each channel The address is different for each channel 0 gt 0x1080 1 gt 0x1082 ch30 gt 0x10BA ch31 gt Ox1lOBE Each threshold is as shown in the figure 2 THRESHOLD VALUE Fig 3 32 Threshold Register KILL K allows to abort memorisation of the data from the relevant channel 0 channel data memorised 1 channel data memorisation is aborted THRESHOLD VALUE this is a amp bit value which is compared with the 8MSB of the 12 bit value to be memorised Default settings are not defined NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 47 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 Please note that the KILL option can be used to disable some channels N B the threshold values are reset only when the board is switched off 3 42 AUX Bus Base Address 0x1200 0x12FF read write This register allows access to an auxiliary 8 bit bus connecting the VME to the piggy back board The bus is bi directional refer to 3 26 for the direction setting NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 48 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 4 Hardware s
26. in CBLT mode corresponds to the set of offsets listed in Table 3 3 to be added to the address common to all boards set by the user via the MCST CBLT Address Register which contains the most significant bits of the address see S 3 8 The CBLT uses the VME Bus Error BERR generated by the last board in the chain as a data readout completion flag This feature is very useful if the VME CPU handles the Bus Error in an efficient way For a correct board operation it is MANDATORY that a VME Bus Error is generated The user must thus perform a number of CBLT accesses that allows for the readout of all data in all boards of the chain in all possible occupancy conditions E g if the user has a chain of 10 boards the total number of words for a given event lies between 0 i e no data and 34x10 340 32 bit words i e each board has an event each event consists of a Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 65 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 Header 32 data End of Block In order to be sure that a BERR is generated the user must thus perform 11 CBLT accesses of 34 word each In CBLT32 mode the first board of the chain starts sending data if there are any i e if it is not purged see 3 13 as it has sent all data and the EOB is met the board becomes purged i e the relev
27. inhibits the conversion of the detected signals BUSY Electrical specifications diff ECL output signal Function wired OR NAND Global Busy signal from the boards belonging to the same chain on the CONTROL bus a BUSY status indicates that the board is either converting or resetting or in MEMORY TEST mode or the MEB is full HALT Electrical specifications diff ECL output signal min width 30 ns Function control signal to the piggy back board 2 3 3 COMMON connectors Mechanical specifications two 00 type LEMO connectors Electrical specifications NIM std input signals high impedance If used daisy chain configuration 50 Q termination must be inserted on the last board of the chain COMMON Function input signal common to all channels to control data acquisition timing This signal is internally OR wired with the COM of the CONTROL connector FCLR FCLR RST RST DRDY DRDY O COM O p VETO O BUSY BUSY HALT HALT O Q2 01 lt Fig 2 2 CONTROL connector pin assignment NPO Filename 00103 99 TAPSy MUTx 01 V874A_REV1 DOC Number of pages 67 Page 16 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 2 4 Other front panel components 2 4 1 Displays The front panel refer
28. red LED alight during conversion reset or Memory Test mode or as the MEB is full DRDY yellow LED alight as there is one event in the MEB TERM orange green red LED alight according to line terminations status OVC PWR green orange LED green at board PWR ON if orange it indicates that there is an over current status 12V 120mA 12V 70mA 5V 590mA 5V 235mA 2V 175mA Control inputs Control outputs Displays Power requirements ttastclear IS VME programmable see 3 25 NPO Filename Number of pages Page 00103 99 5 01 V874A 67 12 CAER Document type Title User s Manual MUT PRELIMINARY Revision 1 Revision date Mod V874A 4 channel General Purpose Converter 15 01 2004 2 Technical specifications 2 1 Packaging The Model V874 A is housed in a 6U high 1U wide VME unit The board hosts the VME P1 P2 connectors and the PAUX connector The board requires the VME V430 backplane 2 2 Front Panel The front panel of the Mod V874 A is shown in Fig 2 1 NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 13 CAER Document type User s Manual MUT NPO 00103 99 TAPSy MUTx 01 Title Mod 874 4 channel General Purpose Converter DTACK VME selected LED Suck hb OVC PWR Gic overcurrent power on status LED TERM termination status LED INPUT connector CO
29. s Manual MUT PRELIMINARY Title Revision date Revision Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 5 Output Buffer Register Base Address 0x0000 0x07FC read only This register allows the user to access the multiple event buffer to readout the converted values The output buffer contains the output data organised in 32 bit words The data in the buffer are organised in events Each event consists of the header that contains the geographical address the crate number and the number of converted channels one or more data words each of which contains the geographical address the number of the channel the Under Threshold UN bit the Overflow OV bit and the 12 bit converted value the End Of Block EOB which contains the geographical address and the event counter Fig 3 5 Output buffer the Header 3130 29 287 26 25 24 21 201918 1716 E 13 ia 10 9 8 7 e s 41312 1 9 GEOIJ4 0 0 ofofo o 5 0 o o UNov ADC 11 0 31 30 29 28 27 26 25124123 02121120 19 18 17 Tenis a ta ra rn ro JE 7 efs 41312 10 Fig 3 6 Output buffer the data word format GEOJ4 0 1 0 0 EVENT COUNTER 23 0 Header NPO 00103 99 TAPSy MUTx 01 Fig 3 7 Output buffer the End Of Block content The bits 31 27 contains the GEO address The bits 2
30. signal generated at any time within the FAST CLEAR window i e between the leading edge of the COM signal and the end of the programmable time value set in the Fast Clear Window Register see 3 25 aborts the conversion Its minimum width must be 10 ns N B since a FAST CLEAR operation implies a CLEAR CONVERSION cycle a new trigger signal is accepted only if it occurs at least 600 ns after the leading edge of the FAST CLEAR signal NPO Filename Number of pages Page 00103 99 5 01 V874A 67 59 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 10 35 FAST CLEAR window 7 Fig 5 5 Fast Clear window NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 60 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 6 Operating modes 6 1 6 2 6 3 NPO Power on sequence To power on the board follow this procedure 1 insert the V874 A board into the crate as the board is inserted and the crate powered the OVC PWR green LED lights up indicating that the board is powered 2 after a short time the BUSY and DRDY LEDs will light off and the TERM LED will become either red or green or off according to the status of the termi
31. the Chained Block Transfer and the Multicast commands The V874 A module is not live insertable The V874 A board uses the VME P1 and P2 connectors and the auxiliary connector PAUX thus requiring the CERN V430 VMEbus crate NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 8 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 1 2 Block diagram Piggy back board IN 1 2 IN 3 IN 4 Iga THRESHOLD COMPARATOR scale J v LLI Ste deese urs apa LOGIC RST a DRDY RUIN DUAL PORT COM MEMORY BUSY START STOP VETO CONTROL FCLR VME INTERFACE HALT TP Front panel Fig 1 1 Model V874A Block Diagram NPO Filename Number of pages 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 Page 9 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 1 3 Functional description The board has 4 inputs one for each channel and one differential ECL common input COMM input The COMM input can be also sent in as NIM signal through a couple of 00 type LEMO connectors which allow easy daisy chaining of several mod
32. the digital conversion digitisation which starts about 500 ns settling time after the STOP signal and takes about 8 us After the digital conversion the clear phase takes place by a fast capacitor discharge about 500 ns which makes the conversion logic idle again The input signals which act as START and STOP are different according to the selected operating mode and to the type of channel For example in a peak sensing channel the START signal is the leading edge of the COM input and the STOP signal is its trailing edge conversely in the case of a TAC channel and the COMMON START mode selected the START signal is the leading edge of the COM input and the STOP signal is the leading edge of the input channel signal itself Filename Number of pages Page 00103 99 5 01 V874A 67 52 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 START trigger STOP CLEAR CONVERSION BUSY lt 34 WRITE __ MEM WE DRDY t CONVERSION LOGIC STATE LAN acguiring data l settling digitiza time tion Fig 5 1 Signal timing for signal conversion NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 53 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod
33. the module output buffer and on the type of piggy back plugged into the main board NPO Filename Number of pages Page 00103 99 5 01 V874A 67 39 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 BUFFER EMPTY BUFFER FULL RESERVED DSELO DSEL1 CSELO CSEL1 Fig 3 20 Status Register 2 BUFFER EMPTY Indicates if the output buffer is empty 0 buffer not empty 1 buffer empty BUFFER FULL Indicates if the output buffer is full 0 buffer not full 1 buffer full CSEL1 CSELO DSEL1 DSELO Indicate the type of piggy back plugged into the board 3 21 Event Counter_Low Register Base Address 0x1024 read only It contains the 16 LSBs of the event counter The event counter can work in two different ways see also 5 6 1 it counts all events 2 itcounts only the accepted events The two modes can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 8 3 26 EVENT CNT LOW 16 LSB of the 24 bit Event Counter Event Counter Low Fig 3 21 Event Counter Low Register This register is reset via the Event Counter Reset Register see 3 33 or via a software or hardware reset see 5 8 However if the event counter is set so as to work as relative counter i e it counts only the accepted events this register is reset also with a data res
34. the read address R Test Address Register must be different from the write address W Test Address Register 3 37 Clear Time Register Base Address 0x1066 read write This 16 bit register contains the ticar value expressed in clock cycles which allows to set the duration of the clear operation of the analog section The total time required for the clear operation is Tetear total 500 ns tciear It can be varied from 500 ns to 2 ms Default setting is 0x0000 3 38 SW Comm Register Base Address 0x1068 write only A write access to this dummy register causes a conversion for test purposes NPO Filename 00103 99 TAPSy MUTx 01 Number of pages Page V874A REVI DOC 67 46 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 39 Slide constant Register Base Address 0x106A read write only SLD CONSTANT Fig 3 30 Slide Constant Register This register contains a 8 bit value corresponding to the constant to which is set the sliding scale DAC when the sliding scale is disabled by means of the SLD_ENABLE bit of the Bit Set 2 Register refer to 3 26 3 40 BAD Register Base Address 0x1072 read only This register contains the value converted by the ADC CONVERTED VALUE 11 0 Fig 3 31 BAD Register 3 41 Thresholds Memory Base Address 0x1080 Ox10BE read write This register
35. to Fig 2 1 hosts the following LEDs DTACK BUSY DRDY TERM OVC PWR Colour green Function DATA ACKNOWLEDGE command it lights up each time a VME access is performed Colour red Function it lights up each time the module is performing a conversion or resetting the analog section or in MEMORY TEST mode or when the Multi Event Buffer is full it also lights up for a while at power on to indicate that the board is configuring Colour yellow Function it lights up when at least one event is present in the output buffer it also lights up for a while at power on to indicate that the board is configuring Colour orange green red Function it lights up green when all the lines of the control bus are terminated red when no line of the control bus is terminated If only some lines are terminated it is off It also lights up orange for a while at power on to indicate that the board is configuring Colour green orange Function it lights up green when the board is inserted into the crate and the crate is powered up when it is orange it indicates that there is an over current status in this case remove the overload source switch the module off and then switch it on again 2 5 Internal hardware components The V874 A board is constituted by a motherboard see also Fig 1 1 where the functional blocks hosted on the piggy back board are pointed out In the following some hardware setting components locat
36. 0x100E read only This register contains information on the status of the module TERM ON and TERM OFF refer to the terminations of the CONTROL bus lines the last module in a chain controlled via the front panel CONTROL connector must have these terminations ON while all the others must have them OFF The insertion or removal of the terminations is performed via internal DIP switches see Fig 2 3 The BUSY and DATA READY signals are available both for the individually addressed module and as a global readout of a system of many units connected together via the CONTROL bus NPO Filename Number of pages Page 00103 99 5 01 V874A 67 35 CAER Document type Title PRELIMINARY Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 DREADY GLOBAL DREADY DREADY GLOBAL DREADY BUSY GLOBAL BUSY not used PURGED TERM ON TERM OFF EVRDY Fig 3 15 Status Register 1 Indicates that there are data at least 1 event in the Output Buffer 0 No Data Ready 1 Data Ready Indicates that at least one module in the chain has data in the Output Buffer wired OR of the READY signal of each module in the chain 0 Module has Data Ready 1 At least one Module has Data Ready BUSY Busy status indicates that either a conversion is in progress or the board is resettin
37. 1 see 5 3 26 The fact that the converted value was under the threshold is also flagged in the datum stored in the memory where the bit 13 UNDERTHRESHOLD of the 16 bit data word is set to 1 see 3 5 NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 54 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 The Thresholds memory allows for the setting of one low threshold value for each channel Default setting corresponds to thresholds not defined The comparison is performed between the 8MSB of each 12 bit converted value and the 8 bit threshold value which is stored in the relevant register as illustrated in the figure ADC converted value from the channel n ADC CONVERTED VALUE sara ojo Threshold value THRESHOLD VALUE for the channel n Fig 5 3 Zero suppression The content of the Threshold Register includes also a KILL bit which allows to abort the memorisation of the datum even if it is higher than the threshold set in the register This bit can thus be used to disable some channels Refer to 3 41 for further details The threshold values are lost only after switching the board off a reset operation does not affect the threshold values 5 4 Overflow suppression The overflow suppression allows to abort the memorisation of data which originated an ADC overfl
38. 3 18 MCST Address Register LAST BOARD Last Board flag bit valid in CBLT and MCST modes only FIRST BOARD First Board flag bit valid in CBLT and MCST modes only Filename Number of pages Page 00103 99 5 01 V874A 67 38 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 The status of the boards according to the bit value is the following BOARD STATUS FIRST BOARD LAST BOARD bit bit Board disabled in CBLT or MCST chain 0 0 First board in CBLT MCST chain 1 0 Last board in CBLT or MCST chain 0 1 Active intermediate board in CBLT or MCST chain 1 1 Bits 2 to 15 are meaningless 3 18 SW Berr Register Base Address 0x101C write only A write access to this dummy register generates a bus error N B this register allows the user to perform a non standard CBLT access 3 19 Event Trigger Register Base Address 0x1020 read write This register contains a 5bit value set by the user when the number of events stored in the memory equals this value and EVTRDY 1 an interrupt request is generated Default setting is 0 in this case the interrupt generation is disabled See also 6 3 2 EV TRGI A 0 Fig 3 19 Event Trigger Register 3 20 Status Register 2 Base Address 0x1022 read only This register contains further information on the status of
39. 6 24 identify the type of word 010 header The bits 23 16 identify the crate number according to the content of the Crate Select Register see 6 3 31 The bits 13 8 contain the number of memorised channels Filename Number of pages Page V874A REVI DOC 67 30 CAER Document type User s Manual MUT PRELIMINARY Title Revision date Revision Mod V874A 4 channel General Purpose Converter 15 01 2004 1 Datum content The bits 31 27 contains the GEO address bits 26 24 identify the type of word 000 gt datum The bits 21 16 identify the number of the channel which the data are coming from The bit 13 is the UNDERTHRESHOLD bit 2 0 2 the datum is over the threshold fixed in the relevant register see 5 3 37 21 gt the datum is under the threshold fixed in the relevant register it is actually possible to make the datum be written in the buffer even if it is under the threshold by using the bits 3 and 4 of the Bit Set 2 Register see 3 26 The bit 12 is the OVERFLOW bit 0 gt ADC not in overflow condition 1 gt ADC in overflow The bits 11 0 contain the converted datum EOB content The bits 31 27 contains the GEO address The bits 26 24 identify the type of word 100 gt EOB The bits 23 0 contain the 24 bit event counter value see S 3 21 The bits 31 27 always contains the GEO address except for the not valid datum see Fig 3 8 The bits 26 24 ide
40. ARDWARE SET UP AND INSTALLATION eoocoooooooooooooooooooooooooooooooooooooooo 49 Z3 SAFETY INFORMATION beton nan anna NN tette dette drei ete deett detenta 49 4 1 1 General safety precautions eese eese tette tnnt nennt AE tenen nente enne 49 4 1 2 Terms and Symbols on the Product eee essere tenente tenente nennen nennen 50 NPO 00103 99 TAPSy MUTx 01 Filename V874A_REV1 DOC Number of pages Page 67 4 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 42 HARDWARESETTINGS rn nien ed d s deer D ee t dett bd 51 4 3 INSTAEDATION irai e eb EE C a Sih hee Sh Stt S eU i oce a 51 5 PRINCIPLES OF OPERATION eeooococooocoocoooooooooooooooooooooooooooooooooooooooooooocooo ooo 52 5 1 DATA CONVERSION TIMING see hah nb Ba BEN tee e lote 52 5 22 ANALOG TO DIGITALE CONVERSION ree DE RE De ede SRI an mann ana San 54 ZERO SUPPRESSION tee Peine deeper eap doe eee eerte desi de hangman aa asa 54 3 4 OVERFLOW SUPPRESSION 45 56 e duga naa nite e EEO EN E AERC EEE EE A 55 5 5 MULTIPLE EVENT BUFFER MEB ccsccsccsssssessenscececesensesensensensensessonscencencessnsensessssssnsensenssencencencensnes 55 5 65 EVENT COUNTER e eb E rh etta bs eo P be b bte ail 57 9572 BUSY LOGIC s te eee eet etude tet debe naa 58 2 82 RESET LO
41. BLT64 modes A standard readout in Block Transfer mode for example consists of a readout of the Header for the relevant event and a Hock Transfer readout of the number of data words relative to the event the number of data words referring to the event is the CNT number in the Header see 3 5 A more efficient readout in Block Transfer mode can be performed by using the BLOCK END and BERR ENABLE bits of the Control Register 1 see 3 14 Some examples of this type of readout in Block Transfer mode are as follows Example A BLOCK END 0 BERR_ENABLE 0 A Block Transfer readout of 32x34 words 32 events max each event 34 words max allows the readout of all data stored in the buffer as the buffer is empty the module will send only not valid data Example B BLOCK END 0 BERR ENABLE 1 A Block Transfer readout of 32x34 words 32 events max each event 34 words max allows the readout of all events stored in the buffer as the buffer is empty a BERR is generated Example C BLOCK END 1 BERR ENABLE 0 A Block Transfer readout of 34 words each event 34 words max allows the readout of one complete event after the readout of the EOB the module will send only not valid data Example D BLOCK END 1 ENABLE 1 A Block Transfer readout of 34 words each event 34 words max allows the readout of one complete event as the EOB is encountered is generated The use of the ENABLE bit
42. EAR DATA of the Bit Set 2 Register to 1 see 3 26 the Reset is released via the Bit Clear 2 Register see S 3 27 2 sending a RESET pulse from the front panel with the Bit 4 PROG RESET of the Control Register 1 set to 0 see 5 3 14 The Software RESET performs the same actions as the data RESET and moreover it resets the registers marked in the column SR Software Reset in Table 3 2 This type of RESET can be forwarded in three ways 1 setting the Bit 7 SOFTWARE RESET of the Bit Set 1 Register to 1 see 3 9 this sets the module to a permanent RESET status which is released only via write access with the relevant bit set to 1 to the Bit Clear Register 2 sending a RESET pulse from the front panel with the Bit 4 PROG RESET of the Control Register 1 set to 1 see 3 14 3 performing a write access to the Single Shot Reset Register see 3 16 the RESET lasts as long as the write access itself The Hardware RESET performs the same actions as the Software RESET and moreover it resets further registers All the registers reset by a Hardware RESET are marked in the column HR Hardware Reset in Table 3 2 This type of RESET is performed 1 at Power On of the module 2 viaa VME RESET SYS RES At power on or after a reset the module must thus be initialised 5 9 FAST CLEAR The FAST CLEAR of the module can be performed via the relevant front panel signal on the CONTROL connector see 2 3 2 FAST CLEAR
43. GIC eR ASA oA eA ends 58 5 0 BASTCEBAR secar eh hs eR n makanan 59 6 OPERATING MODES e ocoooooooooooooooooooooooooooooooooooooooooo 61 6 1 61 6 25 POWER ON STATUS n UR BREED BEN RERE BE Sia 61 6 3 OPERATION SEQUENCE tecti ee eiii Sent ite te ei e tede tite P i tee exit 61 64 XESTMODES 4 RABAT ERRARE ip 62 6 4 1 Random Memory Access Test Mode eee 63 0 42 ACQUISITION Test MOdE S S B d Eun 63 6 5 BLOCK TRANSFER MODE Mu Me OR UDINE anal 64 6 6 ADVANCED SETTING AND READOUT MODES esee nennen nennen eene eene nn nn ene tenente nennen eene 65 0 644 Chained Block Transfer RARI ARRA ARRA RAM 65 0 0 25 Multicast CORAlUs 66 7 REFERENCES o oocoococooooooooooooooooooooooooooooooooooooooooooooooo 67 LIST OF FIGURES Fic 1 1 MODEL V874A BLOCK DIAGRAM eerte nene entente ene 9 FG 2 1 MODEL V874 A FERONT PANEL 5 bete boe dy Pete Eco Det dod ete taints 14 Fic 2 2 CONTROL CONNECTOR PIN ASSIGNMENT ee eeeeeeeeetetntne tene tn ene tenens nennen 16 Fic 2 3 COMPONENT LOCATION COMPONENT 5 nn 19 Fic 3 1 BINARY HEXADECIMAL REPRESENTATION OF
44. MMON NIM input connector CONTROL connector gt Q oo romazoo Og o Rs to I z ic a O Revision date 15 01 2004 PRELIMINARY Revision 1 OG 4 BUSY status LED FCLR RST DRDY COM TP VETO BUSY HALT DRDY GENERAL PURPOSE CONVERTER 6 Fig 2 1 Model V874 A front panel Filename V874A REVI DOC Data Ready LED Number of pages Page 67 14 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 2 3 External connectors The location of the connectors is shown in Fig 2 1 Their function and electro mechanical specifications are listed in the following subsections 2 3 1 INPUT connectors Mechanical specifications LEMO 00 Electrical specifications To be defined by the user 2 3 2 CONTROL connector Mechanical specifications two 8 8 pin 3M 3408 5202 Header type connectors Electrical specifications differential ECL signals 110 impedance Pin assignment is shown in Fig 2 2 FCLR Electrical specifications active high diff ECL input signal min width 10 ns Function FAST CLEAR signal accepted if sent within the so called FAST CLEAR window see Fig 5 5 This window starts with the leading edge of the COM signal and ends with a programmable delay 10
45. NDOW REGISTER sis Mksh nir e ED Hebe Aa hahaa 41 3 26 BIT 5 2 REGISTER et tete ettet 42 3 27 BIT CLEAR 2 REGISTER Sh SA DS ABA SA 44 3 28 W MEMORY TEST ADDRESS REGISTER eese ettet 44 3 29 MEMORY TEST WORD HIGH REGISTER ette tte tet ied retia etae Dee tuae ees 44 3 30 MEMORY TEST WORD LOW REGISTER 22 00020000 45 3 31 CRATE SELECT REGISTER 5 S isn AGB nARASABARSBABAR ARRA RARABABRABARASRABARAS B ARAB AS 45 3 32 TESTEVENT WRITE REGISTER 45 3 33 EVENT COUNTER RESET REGISTER osi cei tisti eie dee o e Eb c od aan 46 3 34 VSET REGISTER delet ests NN Rod dote M deo RAER 46 3 35 MOEE REGISTER obe suas e Di i d dp t bd di hdi 46 3 36 R MEMORY TEST ADDRESS REGISTER eese nn eene nennen ene 46 3 37 CLEAR INSCR 46 3 38 SW COMM REGISTER bete iei ede eb ede ee ie abe Be ee ele i B ede Naaah 46 3 39 SLIDE CONSTANT REGISTER senin Ban bm Aam que cops cu ydgnan sos ani Pp an eare iea inpia e PE 47 3 40 BAD REGISTER REA 47 3 41 THRESHOLDS MEMORY pat er eti a Ee una Anna 47 3422 UK BUS dl eti ute ett edt d t editus 48 H
46. O inactive By default these bits are set to 0 the board is inactive Board status Board position in the chain F B bit L Bbit inactive gt active last 1 active first 1 0 active intermediate 1 1 Please note that in a chain there must be one and only one first board i e a board with F_B bit set to 1 and the L_B bit set to 0 and one and only one ast board i e a board with F_B bit set to 0 and the L_B bit set to 1 The complete address 2 mode is A 31 24 MCST CBLT Address A 23 16 don t care A 15 0 offset In MCST CBLT operation it is possible to define more chains in the same crate but each chain must have an address different from the other 3 1 5 MCST CBLT addressing examples The following is an example of MCST and CBLT addressing for four V874 A boards plugged into a VME crate To access the boards the steps to perform are as follows 1 Set the MCST address see 3 8 for all boards via VME Base Address or geographical addressing 2 Set the bits F B and L B of the MCST Control Register see S 3 17 according to the operational status active or inactive of each board and to its position in the chain first intermediate or last 3 Write or read the boards via MCST CBLT addressing An example of user procedures which can be used to perform a write access is NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 24 CAER D
47. ORD 31 16 Fig 3 25 Test Word High Register NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 44 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 30 Memory Test Word Low Register Base Address 4 0x103A write only This register allows to set the lower 16 bits of the Test Word see above TESTWORD 15 0 Fig 3 26 Test Word Low Register 3 31 Crate Select Register Base Address 0x103C read write This register contains the number of the crate which the board is plugged into This register must be filled at board initialisation and will be part of the data word see 3 5 CRATE NUMBERI7 0J Fig 3 27 Crate Select Register 3 32 Test Event Write Register Base Address 0x103E write only This register is used in Acquisition Test Mode and its content constitutes the test event to be written in the output buffer A write access to this register allows the user to write a set of data into a 32 word FIFO As the Bit 6 TEST ACA of the Bit Set 2 Register see 3 26 is set to 1 and the Acquisition Test Mode is consequently selected these data are directly written in the output buffer constituting an event which can be used to test the module and or the acquisition software Each 16 bit test word see the figure below contains a 12 bit value acting as the ADC con
48. R MEMORY TEST ADDRESS REGISTER i a etnea eatea KE EEC NEE EK EE nennen tenen S as 46 E1G 3 30 SHDECONSTANT REGISTER edge tete ete tee E A 47 FIGs 3 31 BAD REGISTR 4 rrr t t ERER E v haa tara Aik i i Aint 47 Fic 3 32 THRESHOLD REGISTER REO E re RE ree Eh REOR ead 47 Fic 5 1 SIGNAL TIMING FOR SIGNAL CONVERSION sssssessesesseseseeseescuseseseseeseecesseaeeceaseseaesscsaeseseeseseeaeeseaesesaeeeeeeeneeaes 53 Fic 5 2 BLOCK DIAGRAM OF THE SLIDING SCALE SECTION eeeeeeeeeteeee nennen nenne netten nennen enne 54 FIG 5 3 ZERO SUPPRESSION oe rrt terr rte ert rre rer nore Pp Pe EE gu e FU duds 55 Fic 5 4 MULTI EVENT BUFFER WRITE POINTER AND READ POINTER eren nennen nenne 56 FIG 3 5 FAST CLEAR WINDOW ee ehe ree e dena eder NN 60 LIST OF TABLES TABLE 1 1 MODEL V874 MAIN TECHNICAL SPECIFICATIONS sscssessesessesesceseseeeescseeeeseeeessenenseaeeseaeeeceseseeeeeeeeeaes 12 TABLE 3 1 MODULE RECOGNISED ADDRESS MODIFIER essent eene nennen netten 21 TABLE 3 2 ADDRESS MAP FOR THE MODEL V874 A nennen eren eterne nennen eene nennen 28 TABLE 3 3 ADDRESS MAP IN 2 2 2 2 2 000 1 1 ennt nennen teen nnt tenete
49. Set 1 Y Y 0x1006 Read Write D16 Bit Clear 1 v 0x1008 Read Write D16 Interrupt Level Y Y 0x100A Read Write D16 Interrupt Vector Y Y 0x100C Read Write D16 Status Register 1 Y Y 0x100E Read only D16 Control Register 1 v 0x1010 Read Write D16 ADER Y 0x1012 Read Write D16 Single Shot Reset 0x1016 Write only D16 MCST CBLT Ctrl Y 0x101A Read Write D16 SW Berr 0x101C Write only D16 Event Trigger Register Y Y 0x1020 Read Write D16 Status Register 2 Y Y 0x1022 Read only D16 Event Counter L 0 1024 Read only D16 Event Counter H v v v 0 1026 Read only D16 Increment Event 0x1028 Write only D16 Increment Offset 0x102A Write only D16 Load Test Register 0 102 Read Write D16 FCLR Window Y Y 0 102 Read Write D16 Bit Set 2 Y Y 0x1032 Read Write D16 Bit Clear 2 Y Y 0x1034 Write only D16 W Memory Test Address Y Y 0x1036 Write only D16 Memory Test Word High Y Y 0x1038 Write only D16 Memory Test Word Low 0x103A Write only D16 Crate Select Y Y 0x103C Read Write D16 Test Event Write 0x103E Write only D16 Event Counter Reset 0x1040 Write only D16 Vset 0x1060 Write only D16 Voff 0x1062 Write only D16 R Test Address Y Y 0x1064 Write only D16 Clear Time Y Y 0x1066 Read Write D16 SW Comm 0x1068 Write only D16 Slide Constant Y Y 0x106A Read Write D16 BAD 0x1072 Read only D16 Thresholds 0x1080 0x10BF Read Write D16 AUX Bus 0x1200 0x12FF Read Write D16 9 not all
50. User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 2 6 Performances and test results Packaging Number of channels Power on time Internal clock frequency Fast Clear intervention Conversion time Low Level Threshold NPO 00103 99 TAPSy MUTx 01 Filename V874A_REV1 DOC 6U high 1U wide VME unit V430 backplane required 4 inputs 140 ms 32 MHz lt 500 ns tolear 10 US trastclear for all channels from 0 to 99 of the full scale range for each ch Number of pages Page 67 20 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 VME interface 3 1 Addressing capability The modules can be addressed in three different ways specifically 1 via Base Address 2 via GEOgraphical address 3 Multicast Chained Block Transfer addressing mode 3 1 1 Addressing via Base Address The module works in A32 mode This implies that the module s address must be specified in a word of 32 bit The Address Modifier codes recognised by the module are summarised in Table 3 1 Table 3 1 Module recognised Address Modifier A M Description Ox2F GEO Address OxOD A32 supervisory data access 0xOC A32 supervisory 64 bit block transfer MBLT 0x0B A32 non privileged block transfer BLT 0 09 A32 non privileged data access 0x08 A32 non privileged 64 bit block transf
51. ant bit PURGED of the Status Register 1 is set to 1 This implies that the board will not be involved in the CBLT access any more since it has already sent all the required data At this point the IACKOUT line is asserted and the next board if not purged starts sending data As the last board receives the token and is purged it asserts a BERR which acts as a data readout completion flag In CBLT64 mode the accesses work as in the CBLT32 one except for the fact that the address is acknowledged during the first cycle and consequently a DTACK is asserted at least once In CBLT mode the Read Pointer must be incremented automatically if the AUTOINC ENABLE bit is set to 1 in the Bit Set 2 Register see 5 3 26 the Read Pointer is automatically incremented with the readout of the End Of Block word of each board if the AUTOINC ENABLE bit is set to 0 the Read Pointer is not automatically incremented and only the Header of the first word is read N B Please note that according to the VME standard a Chained Block Transfer readout can be performed with 256 read cycles maximum as a consequence a readout with a greater number of read cycles may require more CBLT operations This limit is not due to the board itself but only to the VME standard it is actually possible to performed a CBLT readout with more than 256 read cycles if the timeout of the BUS Timer is disabled or delayed If the latter action is not allowed and the CBLT readou
52. ct e DANGER indicates an injury hazard immediately accessible as you read the marking e WARNING indicates an injury hazard not immediately accessible as you read the marking e CAUTION indicates a hazard to property including the product The following symbols may appear on the product DANGER ATTENTION High Voltage Refer to Manual NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 50 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 4 2 Hardware settings Specific internal hardware components allow to perform the settings concerning the following e Selection of the VME Base Address of the board refer to 2 5 1 for details e insertion of 110 Q termination on one or more lines of the board refer to 2 5 1 for details e Selection of the board behaviour in response to a BUSY signal refer to 2 5 2 for details Details on these settings are given in the relevant sections mentioned above 4 3 Installation The V874 A board must be inserted in a VA30 VME 6U crate Please note that the board does not support live insertion extraction into from the crate i e it is not possible to insert or extract it from the crate without turning the crate off NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 51 CAER PRELIMINARY Document
53. ctions are cleared and the BUSY is removed and the module is ready for the next acquisition The input signal which acts as START signal is chosen on the basis of the channel type and selected operating mode COMMON START COMMON STOP COMMON GATE For example if the channel is a peak sensing one the START corresponds to the leading edge of the COM pulse which acts as a gate i e the leading edge is the START while the trailing edge is the STOP If he channel is a TAC section and the COMMON START operating was selected see bit 10 of the Bit Set 2 Register 3 26 the COM pulse leading edge acts as START and any input channel acts as STOP Test Modes Two different test modes can be enabled e Random Memory Access Test Mode e Acquisition Test Mode The first test mode operation is enabled via the Bit 0 of the Bit Set 2 Register and allows to write directly into the buffer The second test mode is enabled via the Bit 6 of the Bit Set 2 Register and allows to test the whole acquisition system by writing a set of 32 data in an internal FIFO which are then transferred to the output buffer at each COM pulse for the readout The test modes will be described in detail in the following subsections Filename Number of pages Page 00103 99 5 01 V874A 67 62 CAER Document type User s Manual MUT PRELIMINARY Title Revision date Revision Mod V874A 4 channel General Purpose Converter 15 01 2004
54. ctor Each slot of the VME crate is identified by the status of the SNB5 SN1 lines for example the slot 5 will have these lines respectively at 00101 and consequently the module inserted in the slot 5 will have a GEO address set to 00101 see Fig 3 1 The complete address geographical mode is A 31 24 don t care A 23 19 GEO A 18 16 0 A 15 0 offset The following two figures show the binary and the hexadecimal representation of respectively the board Address and a Register Address Bit Set 1 Register in GEO addressing mode Binary representation Hexadecimal representation 0 0 0 1 0 0 0 0 0 0 1 1 0 Binary representation 1006 offset Hexadecimal representation Fig 3 2 Binary Hexadecimal representation of Bit Set 1 Register Address in GEO mode The geographical addressing mode is suggested to perform module settings 3 1 3 Base GEO addressing examples The following is an example of Base GEO Addressing for two V874 A boards inserted in a VME crate NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 22 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 1 NPO BOARD 1 BOARD 2 Rotary Switches bits 31 24 of Slots Address in the crate EE cq E 2 3 4 5 6 7 8 epo fo pp s effe Fig 3 3 Bas
55. e GEO Addressing Example 1 If the board 1 and board 2 are respectively inserted in the slots 5 and 8 with the rotary switches for VME Base Addressing set as shown in the figure the complete address of the registers of the two boards will be as follows Board 1 Base addressing A32 0xEE000000 offset GEO addressing 0x280000 offset Output Buffer excluded Board 2 Base addressing A32 0xCC000000 offset GEO addressing 0x400000 offset Output Buffer excluded 4 MCST CBLT addressing When the Multicast Chained Block Transfer addressing mode is adopted the module works in A32 mode only The Address Modifiers codes recognised by the module are AM 0x0F A32 supervisory block transfer AM 0x0D A32 supervisory data access MCST AM 0x0B A32 user block transfer 0 09 A32 user data access MCST The boards can be accessed in Multicast Commands mode MCST mode see Ref 4 that allows to write in the registers of several boards at the same time by accessing the MCST Base Address in A32 only once The boards can be accessed in Chained Block Transfer mode CBLT mode see Ref 4 that allows to readout sequentially a certain number of contiguous boards in a VME crate This access is allowed in BLT32 and BLT64 modes only to the MCST Base Address N B The Base Address used for MCST and CBLT operations is the same i e throughout this User s Manual the MCST Base Address identifies the same Addres
56. ed on the boards are listed Refer to Fig 2 3 for their exact location on the PCB and their settings 2 5 1 Switches ROTARY SWITCHES TERM ON NPO 00103 99 TAPSy MUTx 01 Filename Type 2 rotary switches Function they allow the VME addressing of the module Please referto Fig 2 3 for their settings Type 14 DIP switches a couple positive and negative for each control signal Number of pages Page V874A REVI DOC 67 17 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 Function they allow the insertion of the Bus termination on the relevant line The 110 Q termination must be inserted on the lines of the last board of the chain In order to insert the termination on a given line both the positive and the negative DIP switches must be inserted If the termination is inserted on all the lines of the board the TERM LED is green if none of the terminations is inserted the TERM LED is red If only some terminations are inserted the LED is off Please refer to Fig 2 3 for their settings Right position dot visible the termination is inserted on the relevant line Left position dot not visible the termination is not inserted CAUTION IN ORDER TO INSERT A TERMINATION ON A LINE BOTH THE POSITIVE AND THE NEGATIVE DIP SWITCH MUST BE SET 2 5 2 Jumpers J9 Function it allows to select board b
57. ehaviour in response to a BUSY status Position A high INTBSY data acquisition is stopped as the board is BUSY independently from the status of the other boards on the CONTROL Bus Position B low EXTBSY data acquisition is stopped as soon as any of the boards on the CONTROL Bus is BUSY Refer to Fig 2 3 for the exact location of the jumper on the PCB and its setting NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 18 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 2x15 pin connector Pa to the piggy back Rotary switches for VME address selection Base address bit lt 27 24 gt Base address bit lt 31 28 gt 3X23 pin connector to the piggy back DIP switches for BUS termination insertion Jumper for TERM ON BUSY mode selection COM Position A INTBSY 1 49 acquisition is stopped as the NETO board is BUSY GATE not used Position B EXTBSY GATE not used J9 acquisition is stopped as any FCLR Right position board on the Bus is BUSY n RST termination ON BUSY Left position DEL Lo dot not visible IDRDY termination OFF Fig 2 3 Component Location component side NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 19 CAE PRELIMINARY Document type Title Revision date Revision
58. er MBLT The Base Address can be selected in the range 0x00000000 OxFF000000 The Base Address of the module can be fixed in two ways e by 2 rotary switches e by writing the Base Address in the ADER register The 2 rotary switches for Base Address selection are housed on the main printed circuit board see Fig 2 3 To use this addressing mode the bit 4 of the Bit Set 1 Register see 3 9 must be set to 0 This is also the default setting The module Base Address can be also fixed by using the Ader Register This register sets the A 31 24 VME address bits see 3 15 bits 2316 of Base Address are actually meaningless their value is neglected by the V874 A software in the examples they are set to 0 NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 21 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 To use this addressing mode bit 4 of the Bit Set 1 Register see 3 9 must be set to 1 This must be the last operation if the GEO is not used 3 1 2 Addressing via GEOgraphical address The Address Modifiers codes recognised by the module are AM 0x2F GEO access All registers except for the Output Buffer can be accessed via geographical addressing The geographical address is automatically read out at each RESET from the SN5 SN1 lines of the PAUX conne
59. et see S 5 8 NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 40 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 22 Event Counter High Register Base 0x1026 read only It contains the 8 MSB of the 24 bit event counter The event counter can work in two different ways see also 5 6 1 it counts all events 2 itcounts only the accepted events The two modes can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 3 26 EVENT CNT HIGH 8 MSB of the 24 bit Event Counter tshahsho a io o IE Event Counter High Fig 3 22 Event Counter High Register This register is reset via the Event Counter Reset Register see 3 33 or via a software or hardware reset see 5 8 However if the event counter is set so as to work as relative counter i e it counts only the accepted events this register is reset also with a data reset see 5 8 3 23 Increment Event Register Base Address 0x1028 write only A write access to this dummy register sets the readout pointer on the next event in the output buffer at the first address In particular f the bit 11 AUTO INCR of the Bit Set 2 Register is set to 0 see 53 26 the readout pointer is no more automatically incremented but it can be incremented via a write access to this register or to the I
60. et 2 Register set to 1 see 3 26 or via write access to one of two dummy registers Increment Event and Increment Offset Registers see 3 23 and 3 24 These allow to move the readout pointer to the next event in the output buffer or to the next word respectively WRITE POINTER READ POINTER BUFFER 0 gt BUFFER 1 m BUFFER 2 BUFFER 14 BUFFER 15 Fig 5 4 Multi Event Buffer Write pointer and Read pointer The MEB can be either in a Full a Not empty or an Empty status When the 5MSB of the Read pointer and the 5MSB of the Write pointer are different i e point to different events the MEB is in a Not empty status When the Read pointer and the Write pointer are equal the MEB can be either in a Full or an Empty status The MEB is full or empty according to the last increment pointer operation performed if the last increment is the one of the Write pointer the MEB is Full if the last increment is the one of the Read pointer the MEB is Empty The status of the MEB is monitored via two Registers the Status Register 1 and the Status Register 2 see 6 3 13 and 3 20 respectively After the conversion the accepted data i e the converted values above the programmed threshold not causing overflow and not killed are stored in the active event buffer i e the one pointed by the write pointer in subsequent 32 bit words These are organised in events Each event consists of a Header see Fi
61. et up and installation 4 1 Safety information This section contains the fundamental safety rules for the installation and operation of the module Read thoroughly this section before starting any procedure of installation or operation of the product 4 1 1 General safety precautions Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it To avoid potential hazards use the product only as specified Only qualified personnel should perform service procedures 4 1 1 1 Injury Precautions Avoid Electric Overload To avoid electric shock or fire hazard do not apply a voltage to a load that is outside the range specified for that load Avoid Electric Shock To avoid injury or loss of life do not connect or disconnect cables while they are connected to a voltage source Do Not Operate Without Covers To avoid electric shock or fire hazard do not operate this product with covers or panels removed Do Not Operate in Wet Damp Conditions To avoid electric shock do not operate this product in wet or damp conditions Do Not Operate in an Explosive Atmosphere To avoid injury or fire hazard do not operate this product in an explosive atmosphere 4 1 1 2 Product Damage Precautions Use Proper Power Source Do not operate this product from a power source that applies more than the voltage specified Provide Proper Ventilation To prevent product overheati
62. g 3 5 a block of data words Fig 3 6 and an End Of Block EOB word Fig 3 7 Each event contains thus from a minimum of 3 32 bit words Header one data word and EOB to a maximum of 34 32 bit words Header 32 data words and EOB In case there are no accepted data the user can choose to store anyway in the MEB the Header and the EOB relative to the event see EMPTY PROG bit of the Bit Set 2 Register see 8 3 26 in this case the event is constituted by 2 32 bit words only The Header content is as follows GEO address bits 31 27 Type of word bits 26 24 010 header Crate number bits 23 16 00 bits 15 14 NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 56 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 e Number of memorised channels bits 13 8 e Reserved bits 7 0 The Data Word content is as follows GEO address bits 31 27 Type of word bits 26 24 000 datum 00 bits 23 22 Number of the channel which the datum comes from bits 21 16 00 bits 15 14 UNDERTHRESHOLD flag bit 13 OVERFLOW flag bit 12 Converted datum bits 11 0 The End Of Block content is as follows e GEO address bits 31 27 e Type of word bits 26 24 100 gt EOB e Event Counter bits 23 0 The MEB may contain a not valid datum as well In a no
63. g or the Output Buffer is full or the board is in MEMORY TEST mode 0 Module not Busy 1 Module Busy GLOBAL BUSY Indicates that at least a module in a chain is BUSY wired OR of the BUSY signal of each module in the chain 0 No Module is Busy 1 At least a Module is Busy PURGED during a CBLT operation it indicates that the board is purged i e the board has finished to send data 0 the board is not purged 1 the board is purged TERM ON Termination ON bit 0 notall Control Bus Terminations are ON 1 all Control Bus Terminations are ON TERM OFF Termination OFF bit 0 notall Control Bus Terminations are OFF 1 allControl Bus Terminations are OFF EVRDY is a flag for the Event Trigger Register NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 36 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 0 default indicates that the number in the Event Trigger Register see 3 19 is smaller than the number of events stored in the memory 1 indicates that the number in the Event Trigger Register see 3 19 is greater than or equal to the number of events stored in the memory and an interrupt request has been generated with interrupt level different from 0 see 3 2 3 N B the condition in which both TERM ON and TERM OFF are equal to 0 means an uncommon termination status
64. ger If many units are connected via the COM and BUSY signals of the CONTROL bus after the trigger leading edge the GLOBAL BUSY signal is set to 1 and it is dropped only when all the modules in the chain have completed the conversion sequence and the system is ready to accept another trigger input The jumper J9 placed on the PCB see Fig 2 3 allows to select board behaviour in response to a BUSY GLOBAL BUSY status if this jumper is set to EXTBSY the acquisition is stopped as soon as any of the boards on the Control bus is BUSY if the jumper is set to INTBSY acquisition is stopped as the board is BUSY The GLOBAL BUSY condition is also flagged by the bit 3 GLOBAL BUSY of the Status Register 1 set to 1 see 8 3 13 Reset Logic Three different types of RESET operations can be distinguished according to the effects they have on the module and particularly on the registers These are e TypeA Data RESET e TypeB Software RESET e Type Hardware RESET Filename Number of pages Page 00103 99 5 01 V874A 67 58 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 The Data RESET clears the data in the output buffer resets the read and write pointers the event counter and the analog sections It does not affect the registers This type of RESET can be forwarded in two ways 1 setting the 2 CL
65. he COM signal it clears the analog sections of the unit and aborts completely the conversion in progress e RST clears the analog sections resets the Multi Event Buffer status stops pending ADC conversions and depending on the user s settings see 3 14 may reset the control registers e VETO common input signal that inhibits the conversions of the signals from all channels e HALT control input signal to the piggy back e input signal to the piggy back Two special signals BUSY and DRDY are also available on the CONTROL bus The BUSY is a differential ECL signal corresponding to the wired OR NAND Global Busy signal of the boards connected to the same CONTROL bus The Busy status indicates that the board is either full or converting or resetting or in MEMORY TEST mode The DRDY as well is a differential ECL signal corresponding to the wired OR NAND Global Data Ready signal of the boards connected to the same chain on the Control bus A Data Ready status indicates the presence of data at least one event see 5 5 in the output buffer of the board All the above described control lines can be terminated on board via internal DIP switches Terminations must be inserted only on the last board in the bus The status of the NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 10 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Pu
66. ical address vme write 0x180016 OxAA GEO D16 set MCST Address 0xAA for board 1 vme write 0x300016 OxAA GEO D16 set MCST Address 0xAA for board 2 vme write 0x480016 OxAA GEO D16 set MCST Address 0xAA for board 3 vme write 0x510016 OxAA GEO D16 set MCST Address 0xAA for board 4 vme write 0x180040 0x02 GEO D16 set board 1 First vme write 0x300040 0x03 GEO D16 set board 2 Active vme write 0x480040 0x00 GEO D16 set board 3 Inactive vme write 0x510040 0x01 GEO D16 set board 4 Last vme write 0 001006 0x80 A32 D16 set RESET MODE for all the boards NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 25 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 N B there must be always one and only one FIRST BOARD and one and only one LAST BOARD 3 2 Interrupter capability The Mod V874 A houses a RORA type VME INTERRUPTER which is generated when the number of events in the memory is equal to the value written in the Event Trigger Register at the VME address Base Address 0x1020 see 3 19 If the Event Trigger Register is set to the interrupt is disabled default setting The interrupt responds to 8 bit 16 bit and 32 bit interrupt acknowledge cycles providing an 8 bit STATUS ID on the VME da
67. increment of the readout pointer 0 the read pointer is not incremented automatically but only by a write access to the Increment Event or Increment Offset Registers see 3 23 and 3 24 1 the read pointer is incremented automatically default Allows to choose if writing the header and EOB when there are no accepted channels 0 when there no accepted channels nothing is written in the output buffer default 1 when there are no accepted channels the Header and the EOB are anyway written in the output buffer SLIDE SUB ENABLE Allows to change operation mode for the sliding scale 0 the sliding scale works normally default 1 the subtraction section of the sliding scale is disabled test purposes only ALL TRG Allows to choose how to increment the event counter 0 event counter incremented only accepted triggers 1 event counter incremented all triggers default DIGITAL OTD Allows to enable the Digital Overthreshold operation 0 no suppression 1 up to 3840 counts stored in memory the subsequent are neglected NPO Filename Number of pages Page 00103 99 5 01 V874A 67 43 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 27 Bit Clear 2 Register Base Address 0x1034 write only This register allows clearing the bits of the Bit Set 2 Register 3 26
68. le it is necessary to set a threshold value for each channel in the Threshold memory refer to 5 3 41 If the module is not BUSY a START signal causes the following Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 61 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 6 4 NPO starts the data conversion increments the event counter according to the user s settings see 5 6 sets the BUSY output signal to 1 If neither RESET nor FAST CLEAR occur refer to 5 8 5 9 to abort the conversion the control logic starts the following conversion sequence 1 outputs of the analog sections are multiplexed and sampled 2 The control logic checks if there are accepted data among the converted values according to the users settings zero suppression overflow suppression and KILL option see 5 3 and 5 4 a if there are accepted data these are stored in the active event buffer together with a Header and an EOB b if there are no accepted data and the EMPTY PROG bit of the Bit Set 2 Register is set to 0 default setting see 3 26 no data will be written in the output buffer C if there no accepted data and the EMPTY PROG bit of the Bit Set 2 Register is set to 1 see 5 3 26 the Header and EOB only will be written in the output buffer 3 The analog se
69. nations on the PCB of the board this indicates that the board is ready to acquire data N B if the OVC PWR LED becomes orange instead of being green there is an overload and the over current protection is now running In order to acquire data it is necessary to remove the overload source then turn the board off and switch it on again Sometimes it may happen that the OVC PWR LED is orange as soon as the board is inserted in the crate this is due to the fact that the board has been just misplaced into the crate In this case extract the board and insert it again into the crate Power on status At power on the module is in the following status e the Event Counter is set to 0 e the Output buffer is cleared e the Read and Write Pointer are cleared i e Buffer 0 is pointed e the Interrupt Level is set to 0 0 in this case interrupt generation is disabled and the Interrupt Vector is set to 0 0 e the values in the threshold memory are not defined see 3 41 e the MCST CBLT address is set to OxAA Moreover all other registers marked in the column HR Hardware RESET in Table 3 2 are cleared or set to the default value At power on or after a hardware reset see 5 8 the module must thus be initialised Operation sequence After the power on sequence the module is in the status described above Please note that the threshold values are not defined after power on and consequently before starting the operation of the modu
70. ncrement Offset Register see below 3 24 Increment Offset Register Base Address 0 102 write only A write access to this dummy register increments the readout pointer of one position next word same event if EOB is not encountered next event if EOB is encountered In particular if the bit 11 AUTO INCR of the Bit Set 2 Register is set to 0 see 3 26 the readout pointer is no more automatically incremented but it can be incremented via a write access to this register or to the Increment Event Register see above 3 25 Fast Clear Window Register Base Address 4 0x102E read write Sets the delay time expressed as number of 32 MHz clock cycles with respect to the trailing edge of COM signal in order to define the Fast Clear window the maximum allowed value is For the definition of the Fast Clear window refer to Fig 5 5 NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 41 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 26 Bit Set 2 Register Base Address 0x1032 read write This register allows to set the operation mode of the module A write access with a bit to 1 sets the relevant bit to 1 in the register A write access with the bit set to 0 does not clear the register content the Bit Clear 2 Register must be used see 3 27 A read access returns the sta
71. ng provide proper ventilation Do Not Operate With Suspected Failures If you suspect there is damage to this product have it inspected by qualified service personnel 4 1 1 3 Certifications and Compliance Use in conformity of the definition with fully equipped mainframe with fully closed slots by boards or dummy panels Sufficient cooling and mains connection must be secured NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 49 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 according to regulations Signal lines length during all tests was less than 3 m Admitted for powering by industrial mains only 4 1 1 4 Terms in this Manual The user is requested to pay particular attention to the parts of the document containing the following terms WARNING Warning statements identify conditions or practices that could result in injury or loss of life CAUTION Caution statements identify conditions or practices that could result in damage to this product or other property Please pay particular attention to the grey areas where warning and caution statements are emphasised as shown in the following examples A CAUTION PROVIDE PROPER VENTILATION WARNING DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE 4 1 2 Terms and Symbols on the Product These terms may appear on the produ
72. ntify the type of word according to the following 010 header 000 gt valid datum 100 end of block 110 5 not valid datum others reserved If a read access is performed to the buffer when it is empty the readout will provide a NOT VALID DATUM arranged as shown in Fig 3 8 29 29127 26 25 24 2322121 20 NPO 00103 99 TAPSy MUTx 01 Fig 3 8 Output buffer not valid datum Filename Number of pages Page V874A REVI DOC 67 31 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 Please note that some of the channel data may be missing in the sequence this is due either to overflow or underthreshold conditions which caused these data not to be stored or to user s settings to kill some channels 3 6 Firmware Revision Register Base Address 0x1000 read only This register contains a 16 bit value identifying the firmware revision The 16 bit value corresponds to 4 hexadecimal figures which give the firmware revision number For example in the figure is shown the register content for the firmware release Rev 04 06 which presently is the latest one Binary representation Hexadecimal representation Fig 3 9 Firmware Revision Register NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 32 CAE PRELIMINARY Document type Title Revision date
73. ock Transfer addressing modes are also supported Refer to 3 1 4 for further details on this subject NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 11 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 Data transfer occurs in D16 D32 BLT32 or MBLT64 The module supports also the Chained Block Transfer mechanism CBLT and the Multicast commands MCST A detailed description of functional blocks and principles of operation can be found in 5 1 4 Technical specification table Table 1 1 Model V874 A main technical specifications Packaging 6U high 1U wide VME unit V430 backplane required Number of channels Internal clock frequency 32 MHz Fast Clear intervention lt 500 ns tear Conversion time 10 US t fastclear for all channels Low Level Threshold from 0 to 99 of FSR for each channel active high diff ECL input signals 110 Q imp COM START STOP signal for data acquisition ECL NIM RST resets analog sections MEB status and control registers VETO inhibits the conversion of the input values FCLR FAST CLEAR of the analog sections and conversion HALT control signal to the piggy back TP control signal to the piggy back diff ECL output signals BUSY wired OR NAND Global Busy DRDY wired OR NAND Global Data Ready DTACK green LED lights up at each VME access BUSY
74. ocument type User s Manual MUT Title Mod V874A 4 channel General Purpose Converter PRELIMINARY Revision date Revision 15 01 2004 1 vme_write address data addr_mode data_mode which contain the following parameters Address Data Addr_mode Data_mode the complete address i e Base Address offset the data to be either written or read the addressing mode A32 the data mode D16 D32 or D64 BOARD 1 BOARD 2 BOARD3 BOARD 4 Rotary Switches bits 31 24 of Address S Fig 3 4 MCST CBLT Addressing Example lots m di in the crate In the following two software examples using the above mentioned procedures are listed Example of Access via Base Address vme write 0 001004 OxAA A32 D16 set MCST Address 0xAA for board 1 vme write 0xCC001004 OxAA A32 D16 set MCST Address 0xAA for board 2 vme write 0 001004 OxAA A32 D16 set MCST Address 0xAA for board 3 vme write 0xDD001004 OxAA A32 D16 set MCST Address 0xAA for board 4 vme write 0 00101 0x02 A32 D16 set board 1 First vme write 0xCC00101A 0x03 32 D16 set board 2 Active vme write 0 00101 0x00 A32 D16 set board 3 Inactive vme write OxDD00101A 0x01 32 D16 set board 4 Last vme write 0 001006 0x80 A32 D16 set RESET MODE for all the boards Example of Access via geograph
75. ow The control logic provides to check if the output of the ADC is in overflow and in the case the value is not stored in the memory The overflow suppression be disabled by means of the OVER RANGE PROG bit of the Bit Set 2 Register see 83 26 if this bit is set to 1 all the data independently from the fact that they caused ADC overflow or not are stored in the memory In this case the 16 bit word stored in the memory will have the bit 12 OVERFLOW set to 1 see 6 3 5 5 5 Multiple Event Buffer MEB After the conversion if there is at least one converted value above the programmed threshold not causing overflow and not killed the control logic stores it in the Multi Event Buffer MEB The Multi Event Buffer is a Dual Port Memory 34 Words event which can store up to 32 events It is available at the VME address Base Address 0x0000 0x07FF see dso 3 5 In order to trace the event flow two pointers Read and Write pointer are employed The Read Pointer points to the active read buffer NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 55 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 The Write pointer is incremented automatically via hardware at the end of the channels conversion while the Read pointer can be either incremented automatically AUTO INCR bit of the Bit S
76. rpose Converter 15 01 2004 1 terminations is available both on the front panel TERM LED and in an internal VME register Status Register 1 see 3 13 Five front panel LEDs show the status of the unit see Front Panel Fig 2 1 green lights up each time the module asserts the VME DTACK e BUSY red lights up each time the module is performing a conversion when resetting the analog section when the Multi Event Buffer is full or the module is in MEMORY TEST mode it also lights up for a while at power on to indicate that the board is configuring e DRDY yellow lights up when at least one event is present in the output buffer it also lights up for a while at power on to indicate that the board is configuring e TERM orange green red lights up green when all lines of the Control bus are terminated red when no line of the control bus is terminated and does not light up when only some lines are terminated it also lights up orange for a while at power on to indicate that the board is configuring e OVC PWR green orange lights up orange to indicate an over current situation and lights up green when the board is inserted into the crate and the crate is powered up Some of these LEDs light up at power on to indicate that the board is configuring after a little time these LEDs light off to indicate that the board is ready to operate For details please refer to the Power ON section 6 6 1 The board houses a 24 bit co
77. s used both for MCST commands in Write only and the CBLT Readout in Read only for the Output Buffer only Filename Number of pages Page 00103 99 5 01 V874A 67 23 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 The MCST Base Address must be set in a different way with respect to the ordinary Base Address lts most significant byte i e bits 31 through 24 must be written in the MCST CBLT Address Register see 3 8 and must be set in common to all boards belonging to the MCST CBLT chain i e all boards must have the same setting of the MCST CBLT Base Address on bits 31 through 24 The default setting is In CBLT and MCST operations the IACKIN and IACKOUT VME lines are used for the control transfer from one board to the following No empty slots must thus be left between the boards or in alternative empty slots can be left only in case VME crates with automatic IACKIN IACKOUT short circuiting are used Once the addresses have been set the first and last board in a chain must have respectively only the FIRST BOARD B and only the LAST BOARD L B bit set to 1 in the MCST Control Register see 3 17 On the contrary all intermediate boards must have both the FIRST BOARD and the LAST BOARD bits set to 1 active intermediate or both the FIRST BOARD and the LAST BOARD bits set to
78. t stops before having read all data the new CBLT cycle will start from where the token was left in the previous cycle this goes on until the last board is reached and all data read so that a BERR is generated 6 6 2 Multicast Commands NPO Once set the address of the boards as described 6 6 the boards be accessed in Multicast Commands MCST mode The MCST mode allows to write in the registers of several boards at the same time by accessing a dummy Address only once The latter is composed by the MCST Base Address plus the offset of the relevant register according to the list shown in Table 3 4 Refer to 3 1 4 for details on MCST addressing mode MCST access can be meaningless even if possible for the setting parameters depending on the individual channel characteristics N B the MCST CBLT Address Register must NEVER be accessed in MCST mode since this can affect the CBLT and MCST operations themselves Filename Number of pages Page 00103 99 5 01 V874A 67 66 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 7 References 1 2 3 4 C Cottini E Gatti V Svelto A new method of analog to digital conversion NIM vol 24 p 241 1963 C Cottini E Gatti V Svelto sliding scale analog to digital converter for pulse height analisys in Proc Int Symp
79. t valid datum only the bits 26 24 which mark it as not valid datum are meaningful The Not Valid Datum content is as follows e Type of word bits 26 24 110 gt not valid datum The meaning of the bits 26 24 to identify the type of word stored in the buffer is summarised in Table 5 1 Table 5 1 Word type in the multi event buffer Bit 26 Bit 25 Bit24 Header Datum End of Block 1 Not valid datum 1 Reserved Ooj oj o The converted data relative to each event are stored in the active write buffer However because of possible users settings e g Zero Overflow suppression some channels can be missing In any case each data word contains the converted datum together with its relevant channel number 5 6 Event Counter The module houses a 24 bit counter that counts the number of COM signals that the module has received The Event Counter can work in two different modes which can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 6 3 26 NPO Filename Number of pages Page 00103 99 5 01 V874A REVI DOC 67 57 CAER PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 5 7 5 8 NPO Mode A ALL TRG 1 it counts all events default Mode B ALL TRG 0 it counts only the accepted events In the first case Mode A
80. ta lines D00 D07 and removes its interrupt request when the condition mentioned above is FALSE 3 2 1 Interrupt Status ID The interrupt STATUS ID is amp bit wide and it is contained in the 8LSB of the Interrupt Vector Register see 5 3 12 The register is available at the VME address Base Address 0x100C 3 2 2 Interrupt Level The interrupt level corresponds to the value stored in the 3LSB of the Interrupt Level Register see 3 11 The register is available at the VME address Base Address 0x100A If the 3LSB of this register are set to 0 the Interrupt generation is disabled 3 2 3 Interrupt Generation The Interrupt Generation occurs as the number of events stored in the memory equals the value written in the Event Trigger Register see 3 19 This condition can be thus programmed via VME 3 2 4 Interrupt Request Release The INTERRUPTER removes its Interrupt request when a Read Access is performed to the Output Buffer so that the number of events stored in the memory decreases and becomes less than the value written in the Event Trigger Register NPO Filename Number of pages Page 00103 99 5 01 V874A 67 26 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod 874 4 channel General Purpose Converter 15 01 2004 1 3 3 Data transfer capability The internal registers are accessible in D16 mode unless otherwise specified Access in
81. tus of the register The register content is the following 15 1413 12 111 1019 8 17 6 51 4131 2 1 0 L MEM TEST OFFLINE CLEAR DATA OVER RANGE PROG LOW TRESHOLD PROG Not used TEST ACQ SLD ENABLE AUX BUS DIRECTION Not used COMM STOP AUTO INCR EMPTY PROG SLD SUB ENABLE ALL TRG DIGITAL OVERTHRESHOLD Fig 3 23 Bit set 2 register MEM TEST Test bit allows to select the Random Memory Access Test Mode see 6 4 1 0 normal mode default 1 Random Memory Access Test Mode selected it is possible to write directly into the memory OFFLINE Offline bit allows to select the ADC controller s status 0 ADC controller online default 1 ADC controller offline no conversion is performed CLEAR DATA Allows to generate a reset signal which clears the data the write and read pointers the event counter and the analog sections 0 no data reset is generated default 1 a data reset signal is generated OVER RANGE Allows to disable overflow suppression see also 5 4 0 over range check enabled only the data not causing the ADC overflow are written into the output buffer overflow suppression default 1 over range check disabled all the data are written into the output buffer no overflow suppression LOW THR Allows to disable zero suppression see also 5 3 NPO Filename Number of pages Page 00103 99 5 01 V874A
82. type Title Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 5 Principles of operation 5 1 NPO The board has 4 general purpose channel inputs and COM input common to all channels which is used to control the data acquisition timing according to the channel type and selected operating mode Each channel input value received within a temporal window determined by means of the COM input signal and according to the channel type and selected operating mode is converted into a voltage level by the analog sections The outputs of the analog sections are then processed by a fast 12 bit ADC module Only the values that are above a programmable threshold see 5 3 do not cause overflow see 5 4 and not killed see 8 5 3 will be stored in a dual port data memory accessible via VME In the following functional sections and operation principles of the module are described in some detail The block diagram of the module can be found in Fig 1 1 Data conversion timing The timing of the signals involved in the conversion of data is shown in Fig 5 1 The diagram includes four different temporal phases idle data acquisition settling time digitization and clear While the conversion logic is idle the occurrence of a trigger START signal starts the acquiring dala phase As the STOP signal occurs the acquired value is hold until the end of
83. ules The block diagram of the module is shown in Fig 1 1 Each value received from the channel inputs within a temporal window the definition of which depends on the selected operating mode and the channel type is converted into a voltage level by the relevant Analog to Digital Converter These output voltages from the analog sections are multiplexed and subsequently converted by a fast 12 bit ADC module The ADC adopts a sliding scale technique see Ref 1 2 to reduce the differential non linearity of the measurement Refer to 5 2 for further details The module features zero and overflow suppression i e only the values that are above a programmable level and do not cause overflow are stored in the dual port data memory accessible via VME It is also possible to disable some channels via the KILL option see 5 3 Board operation depends on the channel type TAC peak sensing etc and selected operating mode COMMON START COMMON STOP COMMON GATE Some test modes are also available and programmable via VME Refer to S 6 4 for further details The unit accepts the following CONTROL signals differential ECL 110 Q in common to all channels see Front Panel Fig 2 1 e input signal common to all channels acting as start stop gate signal for data acquisition e FAST CLEAR input signal sent after the leading edge of the COM signal within a programmable window ending 10 35 us after the trailing edge of t
84. unter Event Counter that allows to count either the accepted Triggers i e it is increased each time a pulse is sent through the COM input and accepted VETO FCLR and BUSY are not active or all incoming Triggers In the latter case the Event Counter acts also as an absolute time counter Via VME it is also possible to Set a low threshold for the Zero suppression for each channel Enable or disable the Zero Overflow suppression Disable some of the channels KILL option Increase the delay between the trailing edge of the COM signal and the start of conversion Fast Clear window The module may be addressed in 3 different ways 1 By Base Address 2 By GEOgraphical address 3 By Multicast Chained Block Transfer addressing In the first case the module s Base Address can be fixed either by 2 rotary switches or by writing it in the internal Address DEcoder Register ADER see 3 15 Refer to 3 1 1 for further details on addressing via Base Address Geographical addressing can be used thanks to the PAUX connector the geographical address is automatically read out at each RESET from the JAUX connector of the V430 VME crate and each slot is identified by a number GEO that is unique within the crate This addressing mode is performed with the Ox2F Address Modifier code This addressing mode is recommended to perform module settings Refer to 3 1 2 for further details on addressing via geographical address Multicast Chained Bl
85. verted value and an OV bit which indicates the possible overflow The test data corresponding to the data from the channels must be written in this FIFO in the same order as they are read from the output buffer For further details on the use of this register in Acquisition Test Mode please refer to 6 4 2 TEST ADC CONVERTED VALUE 11 0 Fig 3 28 Test Event Write Register NPO Filename Number of pages Page 00103 99 TAPSy MUTx 01 V874A REVI DOC 67 45 CAER Document type Title PRELIMINARY Revision date Revision User s Manual MUT Mod V874A 4 channel General Purpose Converter 15 01 2004 1 3 33 Event Counter Reset Register Base Address 0x1040 write only A VME write access to this dummy register clears the Event Counter 3 34 Vset Register Base Address 0x1060 write only This amp bit register contains the DAC value to set the slope of the ramp i e to select the range Default status is not defined 3 35 Voff Register Base Address 0x1062 write only This 8 bit register contains the DAC value to set the offset of the ramp Default status is defined 3 36 R Memory Test Address Register Base Address 0x1064 write only This register contains the address of the output buffer from which data can be read for the ao memory test TEST ADDRESS 10 0 Fig 3 29 R Memory Test Address Register N B The output buffer is a FIFO so

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