Home

USER`S MANUAL

Contents

1. 22 6 BCDYEAR Counter Register 22 7 KS32C65100 RISC MICROPROCESSOR xiii Table of Contents Concluded Chapter 23 Clock Save and PLL Control 23 1 Registers iei cdd 23 1 GEKSAVGON Registe P a 23 2 GON BegISEeE 23 2 Chapter 24 LSU Control ainn 24 1 SIQNAlS 3 M 24 2 Special a 24 3 ESU GON Gontrol RBeglster 24 3 V Window Start End Time Register 24 4 LD ON Pre Post Time 24 4 V Window Counter Observation 24 5 LSU Motor Clock Generation Counter 24 5 Chapter 25 Printer Interface Controller GI ERE ED 25 1 Page Image Data Fetch 25 2 LES 25 4 PIFC Special Registers Ee
2. 9 9 Chapter 10 Parallel Port Interface 10 1 KS32C65100 PPIC Operating 10 2 PPIC Special 10 5 Parallel Port Data Register 10 5 Parallel Port Status 10 6 Parallel Port ACK Width 10 9 Parallel Port Control Register 10 10 Parallel Port Interrupt Event Registers PPINTEN 10 14 Chapter 11 UART OVE IMIG Woo dt edd e E M M M a e M s ec Seu 11 1 E 11 2 UART Special 11 6 6 PC 11 15 Chapter 12 Tone Generator OVeIVIGW eh MUI I A D eU TD POUND i ve ea 12 1 Tone Generator Data Register 2200004 000 000 00 00 12 1 Chapter 13 Watchdog Timer NIE 13 1 Watchdog Timer Counter Register 13 2 Watchdog Timer Control Register 13 3 KS32C65100 RISC MICROPROCESSOR Table of Contents Continued Chapter 14 Ports OVOIVIGW xci Bana Wan a aua aaa Port Special Port M
3. 000 4001 4 COO CO QOooco 10 014 C00 Oo lt MOTOR PORT gt lt DATA PORT gt PRINT PORT gt Figure 29 8 Evaluation Board Schematic 5 26 12 ELECTRONICS
4. 4 13 4 12 SRAM Write 0 nennen nennen 4 13 4 13 DRAM Control Registers DRAMCONO 4 15 4 14 DRAM Bank Read Timing Page 4 16 4 15 DRAM Bank Write Timing Page 4 16 4 16 DRAM Refresh Control amp Memory Configuration Register DRAM Refresh Control 4 17 4 17 Self Refresh Mode Entry Process by 4 18 4 18 Self Refresh Mode Entry Process by 4 19 4 19 DRAM Refresh 4 20 4 20 Special I O Address 4 21 4 21 Extra Bank Control Registers ExtOntr 0 1 2 3 4 22 4 22 Extra Bank Read Timing tcoh 1 tacc 4 tcos 1 tacs 2 4 23 4 23 Extra Bank Write 0 4 23 4 24 An Example of System Manager Register 4 25 xviii KS17C80064 C80013 F80013 MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 5 1 Cache Memory 5 2 5 2 CS bit Status 5 3 5 3 Write Buffer 5 4 5 4 Non Cacheable Area
5. 25 5 and Engine Interface Status nene 25 5 Video Control 25 6 Pattern Control REGIStC M2 e E 25 8 Printer Control 25 11 Top Margin 25 13 Left Margin Register REM 25 14 Pixel Ma e OMM 25 14 Queue 0 1 Start Address 25 15 Queue 0 1 Transfer Count 25 16 F 0 Lens Compensation Control 25 17 F 0 Compensation Table Start 00 25 18 F 0 Compensation Table Data 25 19 Toner Counter Setting 25 19 Toner Count 25 20 517 80064 80013 80013 MICROCONTROLLER Table of Contents Concluded Chapter 26 Variable ImageScailing ecco teet t oaa Algorithms IS M LA ALI E EE M E E Example of VIS Operation sec LE I C MEM E MEE ES SpeciahbiSgistel s nodo attt ta Chapter 27 PWM Timer Control 0 oT a Main Input Output Signals Special Function Register Chapter 28 Mechanical D
6. 21 8 SRAM Data Register aa aa cei 21 8 Motor Term Control Register 21 9 Motor Phase Control 21 9 Black Shading Correction Factor Register 21 10 Reduction amp 21 12 Digital Shading 21 14 ett asd aad aia 21 15 2052 dudas d dada ced 21 15 ADC Controle tee a nca 21 16 Motor 21 17 Register Read Wirite 21 18 Ouiputi tances dd dac 21 20 Chapter 22 Real Time Clock eru 22 1 Leap Year CT T0 zuo RD 22 2 System Power Operation 5v 22 2 22 2 Real Time Clock Registers x tei cd empate icc et erus i c Ped 22 3 5 T 22 3 BODSEG Counter 22 4 BCDMIN Counter Register 22 4 BCDHOUR Counter 22 5 BCDDAY Counter 22 5 BCDDATE Counter F eglStOr sicci dic eene inccr ea deu ic e E e Ec aee 22 6 BCDMON Counter
7. 19 8 Dot Gounter Register oot eese pice dei deeds 19 9 Dot Counter Control Observation 19 9 Chapter 20 HDMA xii HDMA Source Match ADR Register Gc E 20 1 Special 20 1 HEAD Control 20 1 Source Address 20 4 Transfer Count Register 20 4 KS17C80064 C80013 F80013 MICROCONTROLLER Table of Contents Continued Chapter 21 Image Processor OVOeIVIGW at aaa E aa 21 1 Image Processor Special 21 2 Sensor Shift Clock Control Register 21 2 Sensor SI Clock Control Register 40 4 21 3 Sensor GB Led Control 21 4 IWIN Control Register 21 4 Changed IWIN Control 21 5 MAG RED Ratio Control 21 5 LAT Local Adaptive Threshold Control 21 6 Control Register aa dd aad daas dada 21 6 Operation Control 21 6 SRAM Control
8. 3 66 3 12 Summary of Format 5 5 3 68 3 13 Summary of PC Relative Load 58 3 71 3 36 Summary of Format 7 5 5 3 72 3 15 Summary of Format 8 5 3 74 3 16 Summary of Format 9 5 3 76 3 17 Halfword Data Transfer 3 78 3 18 SP Relative Load Store 3 79 3 19 Load 3 80 3 20 The ADD SP 3 82 3 21 PUSH and 5 3 83 3 22 The Multiple Load Store 3 85 3 23 The Conditional Branch 3 86 3 24 The SWI Instruction essen n nnne nnne nnn nnns 3 88 3 25 Summary of Branch 3 89 3 26 The BL Instruction 3 91 4 1 The Relations Between Physical Address and Address in Instructions 4 9 6 1 Set 1 Register Values after a 6 4 KS32C65100 RISC MICROPROCESSOR XXV List of Tables Continued Table Title Page Number Number 9 1 Difference Between and 9
9. pma ooma 1 oan ra ore orr i 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 1 0 Figure 3 1 ARM Instruction Set Format Some instruction codes are not defined but do not cause the undefined instruction trap to be taken for instance a multiply instruction with bit 6 changed to a 1 These instructions should not be used as their action may change in future ARM implementations ELECTRONICS 3 1 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set Mnemonic Instruction B 0045 Coprocessor specific Rd Rn and not Op2 or op2 and not Rn Coprocessor load Move CPU register to coprocessor register om o 1 3 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils the conditions encoded by the field the instruction is executed otherwise it is ignored There are sixteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a branch B in assembly
10. Er 52 TRANSFERS 5 53 TRANSFERS FROM 15 53 INSTRUCTION CYCLE 53 ASSEMBLER SYNTAX tenore oe oe ere 53 UNDEFINED 54 INSTRUCTION CYCLE 54 ASSEMBLER 54 INSTRUCTION SET 5 55 USING THE CONDITIONAL 55 PSEUDO RANDOM BINARY SEQUENCE 57 MULTIPLICATION BY CONSTANT USING THE BARREL 57 LOADING A WORD FROM AN UNKNOWN 59 THUMB INSTRUCTION SET 0 60 FORMAT 5 60 OPCODE 50 61 FORMAT 1 MOVE SHIFTED 63 OPERATION Ss e A M M M 63 INSTRUCTION CYCLE 63 FORMAT 2 64 OFERA TON 64 INSTRUCTION CYCLE TIMES 64 FORMAT 3 MOVE COMPARE ADD SUBTRACT 65 OPERA HONS cceli ul M M 65 INSTRUCTION CYCLE TIMES 65 FORMAT 4 ALU 66 66 ELECTRONICS 3 99 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR INSTR
11. Rw Description Reset Value Ports Controller Real Time Clock CLKSAVCON 0x1800 Clock save control register Clock Save PLLCON 0x1804 PLL control register 0x00000 ELECTRONICS 1 13 PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR Table 1 2 KS32C65100 Special Function Registers Continued UART Ch 0 line control register UART Ch 1 line control register UART Ch 2 line control register UART Ch 0 control register UART Ch 1 control register UART Ch 2 control register UART Ch 0 status register UART Ch 1 status register UART Ch 2 status register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0000 0x0000 0x0000 0x00 0x00000000 0x000000 0x00 0x0000 0x0000 0x0000 0x0000000 0x000000 0x0000000 0x000000 URXBUFO UART Ch 0 receive buffer register URXBUF1 Oxb810 R UART Ch 1 receive buffer register UART Ch 1 transmit buffer register UART Ch 2 transmit buffer register R UART EN UTXBUFO Oxb00c w UART Ch 0 transmit buffer register w Ww W UART Ch 2 receive buffer register R W Baud rate divisor register 0 Baud rate divisor register 1 Baud rate divisor register 2 Status register Video control register Pattern control register PDMA control register OP TOP margin register LEFT margin register Pixel count register start address register E 0 transfer address register
12. 3 14 aad 3 14 Using R15 As 3 14 TST and 3 14 6 3 14 Assembler Syntax od da a aae aa aa 3 15 PSR Transfer MRS MSR 3 16 Operand Restrictions eaa dau 3 16 Resetved Bits 22e ada dades 3 18 Instruction Cycle 3 18 Assembler Syntax dtd aaa addas 3 19 Multiply and Multiply Accumulate MUL 3 20 GPSHR Elags hina eed d dd dde 3 21 Instruction Gycle Titmbs adde dad dua 3 21 Assembler Syntax iiid edu eaa daas 3 21 Multiply Long and Multiply Accumulate Long 3 22 Restrictions ada da da d daa dd dus 3 22 CRSR Flags dni daa dd aec 3 23 Instruction Gycle Timas aida dada ada addita 3 23 Assembler Syntax e e a adu a aa ane 3 23 Single Data Transfer LDR 3 24 Offsets and Auto Indexing 3 25 Shifted Register Offset
13. 3 10 3 6 Logical Shift 3 10 3 7 Logical Shift 3 11 3 8 Arithmetic Shift Right 3 11 3 9 Rotate Matre o MM 3 12 3 10 Rotate Right Extended 3 12 3 11 PSR Transfer MM 3 17 3 12 Multiply 3 20 3 13 Multiply Long Instructions 3 22 3 14 Single Data Transfer 3 24 3 15 Little Endian Offset 3 26 3 16 Halfword and Signed Data Transfer with Register 3 30 3 17 Halfword and Signal Data Transfer with Immediate Offset and Auto Indexing 3 31 3 18 Block Data Transfer 3 36 3 19 Post Increment 5 3 37 3 20 Pro Increment Addressing 3 38 3 21 Post Decrement 3 38 3 22 Pre Decrement 3 39 3 23 Swap 3 43 3 24 Software Interrupt 3 45 3 25 Coprocessor Data Operation Instruction 000 3 47 3 26 Coprocessor Data Transfer 3 49 3 27 Coproces
14. x FIN p m value of 8 bit Main divider 0 lt lt 255 p value of 6 bit Pre divider 0 lt lt 63 s value of 2 bit Post scaler 0 lt 5 lt 3 1 Clock Input 10MHz 20MHz recommend condition 2 Fliter Input 820 pF 3 Clock output Main clock NOTE The setting of the PLLCON register can change only one time For example after power on the value of the PLLCON register is 0 0 this is PLL clock is not used After this you can set the PLLCON register only one time Also We recommend the s s value is greater than or equal to 1 and the FIN p 2 is greater than 1MHz ELECTRONICS 23 3 KS32C65100 RISC MICROPROCESSOR LSU CONTROL INTRODUCTION This module performs the following functions V Window and LD PreHeat pulse generation LSU ready state check VDO masking and software on off control LSU motor clock generation nHSYNC Filtering Printer Video Data InterFace Control LSU_CON Figure 24 1 LSU Control ELECTRONICS LSU CONTROL nHSYNC2 VDO2 nHSYNC1 nLREADY nVDI VDO1 LSU CLK 24 1 LSU CONTROL KS32C65100 RISC MICROPROCESSOR MAIN INPUT OUTPUT SIGNALS Input e nLREADY Signal activated when polygon motor is within the accurate speed nHSYNC1 Horizontal beam detect signal from LSU e nVDI Video data from PIFC block Output VDOt Laser diode on off output external output initial H active L nPSYNC Page sync signal set by S W for PIFC block LSU
15. Figure 15 2 Interrupt Pending Register 15 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR INTERRUPT CONTROLLER Interrupt Mask Register INTMSK 0x2008 Interrupt mask register 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 31 Global Mask If this bit is set to 0 all interrupts are disabled 30 0 Interrupt Mask Bit Each of the 31 bits in the interrupt masking register INTMSK corresponds to an interrupt source Interrupt mask bit is 1 the interrupt will be serviced normally The 30 interrupt sources are summarized in Table 15 1 Figure 15 3 Interrupt Mask Register ELECTRONICS 15 5 KS32C65100 RISC MICROPROCESSOR LF MOTOR LF MOTOR OVERVIEW This module performs the following functions e Step interrupt generation for driving line feed motor e 14 bit timer for step interrupt which controls the change of drive signal for line feed motor using selectable clock e Phase can be written by software or hardware NOTE 1 When the timer is enabled it begins to decrease from the base value 2 When the timer expires the associated interrupt is generated the base value is reloaded and the timer continues to decrease 3 If a new value is loaded in this register before the timer is expired the timer will keeping counting with the new value SPECIAL FUNCTION REGISTER LINE FEED MOTOR CONTROL REGISTER This register selects the phase written
16. 0 83 elem 83 INSTRUCTION CYCLE TIMES 84 FORMAT 15 MULTIPLE 5 85 OPERATION LM ML M LM 85 INSTRUCTION CYCLE 5 0 85 FORMAT 16 CONDITIONAL 86 OPERATIONS 86 INSTRUCTION CYCLE TIMES 87 FORMAT 17 SOFTWARE 88 INSTRUCTION CYCLE TIMES 88 FORMAT 18 UNCONDITIONAL 89 OPERA certe 89 FORMAT 19 LONG BRANCH WITH 90 OFERA TON 90 INSTRUCTION CYCLE 00 91 INSTRUCTION SET 5 nennen nnn 92 MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS meme 92 GENERAL PURPOSE SIGNED DIVIDE sese 93 DIVISION A CONSTANT RR 95 ELECTRONICS 3 101 KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER SYSTEM MANAGER OVERVIEW 532 65100 System Manager provides the following features tarbitrates the system bus access requests from a master block based on a fixed priority e t provides the appropriate memory control signals for an external memory access If a master block such as DMA or CPU generates an address that corresponds to a DRAM bank the System Mana
17. 3 25 Bytes d aae aa aaa 3 25 c oec Re dada 3 27 Restriction On The Use of Base 3 27 Data ADbOItS x end ada udi 3 27 lnstruction Gycle Times 3 27 Assembler 3 28 Halfword and Signed Data Transfer _ 3 30 Offsets and Auto Indexing 3 32 Halfword Load and Stores 3 32 Signed Byte and Halfword 3 32 Endianness and Byte Halfword 3 32 se ia Ra added 3 33 Data ADOITS edenda tasse 3 33 Instruction Oycle Timies 2 2 nra dada daas 3 33 Assembler Syntax dotada 3 34 vi KS32C65100 RISC MICROPROCESSOR Table of Contents Continued Table of Contents Continued Chapter 3 Instruction Set Continued Block Data Transfer LDM 5 E Addressing ModeS dais Address Alignment aaa cuu Use or Pie S eo done aa Use of R15 As The Inclusion of The Base In The Register Data Instruction Cycle TImies eias Assembler Syntex ed cede Single Data Swap Bytes and Word
18. 20 3 20 2 HDMA Source 20 4 20 3 HDMA Transfer Count 20 4 20 4 Source Match Address 20 5 21 1 Image Processor Block Diagram 21 1 21 2 Sensor Shift Clock Control Register 21 2 21 3 Sensor SI Clock Control Register 21 3 21 4 Sensor R GB LED Control 21 4 21 5 IWIN Control Register 21 4 21 6 CHANGED WIN Control 21 5 21 7 Mag Red Ratio Control 21 5 21 8 LAT Control 21 6 21 9 ADC Control 21 6 21 10 Operation Control 21 7 21 11 SRAM Control 21 8 21 12 SRAM Data 21 8 21 13 Motor Term Control Register 21 9 21 14 Motor Phase Control 21 9 21 15 Block Shading Correction Factor 21 10 21 16 Restart amp SCAN ON Timing 21 10 21 17 Reduction Pixel Clock Timing 21 12 21 18 Magnification Pixel Clock Timing 21 13 21 19 Shadi
19. During reverse data transfers software is responsible for data compression and writing data or command bytes in PPDATA to define the logic levels on PPD7 PPDO and BUSY pins in which the PPDATA 8 indicates whether the current data PPDATA 7 0 is a data byte or a command byte and outputs to the BUSY pin Responding to writing PPDATA PPIC automatically drives the nACK low waits for the nAUTOFD to go to high and then drives nACK high to conclude one reverse data transfer operation as shown in Figure 10 3 ELECTRONICS 10 3 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR ECP with RLE mode ECP with RLE hardware handshaking mode is enabled by setting the PPCON s mode selection bits as 11 i e PPCON 3 2 11 In this mode PPIC performs the same ECP mode handshaking as in ECP without RLE mode except that run length compression decompression is also carried out by hardware During forward data transfers PPIC automatically detects and intercepts run length counts and carries out data decompression Only the channel addresses will cause the command received bit in the PPINTPND register to be set and software responds by only performing operations associated with it Similarly PPIC automatically carries out the data compression in PPDATA during reverse data transfers PPD 7 0 Byte 0 T Byte 1 BUSY y Data byte X N Command byte nACK N N nAUTOFD N N Figure 10 3 ECP Hardware Handshaking
20. Figure 11 2 UART Block Diagram Loop back Mode The KS32C65100 UART provides a test mode referred to as the loop back mode to aid in isolating faults in the communications link In this mode data that is transmitted is immediately received This feature allows the processor to verify the internal transmit and receive data paths of each SIO channel This mode can be selected by setting the loop back bit in UART control register UCONn Interrupt DMA Request Generation Each SIO of KS32C65100 UART has seven status signals overrun error parity error frame error break receive buffer full transmit buffer register empty and transmitter empty all of which are indicated by the corresponding UART status register USTATn The overrun error parity error frame error and break condition are referred as the receive status each of which can cause the receive status interrupt request i e the error interrupt to be mentioned in Section 19 if the receive status interrupt enable bit is set in control register UCONn When a receive status interrupt request is detected you can determine which signal caused the request by reading the status register USTATn When the receiver transfers data from its shifter to its buffer it activates the receive buffer full status signal which will cause the receive interrupt If the receive mode in control register is selected as interrupt mode and when the transmitter transfers data from its transmit buffer
21. THUMB Assembler ARMEquivalent Aon 3 66 ELECTRONICS KS32C65100 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES ARM INSTRUCTION SET All instructions in this format have an equivalent ARM instruction as shown in Table 3 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples EOR ROR NEG CMP MUL ELECTRONICS R3 R4 R1 RO R5 R3 R2 R6 RO R7 EOR R4 and set condition codes Rotate Right R1 by the value in RO store the result in R1 and set condition codes Subtract the contents of R3 from zero store the result in R5 Set condition codes ie R5 Set the condition codes on the result of R2 R6 R7 RO and set condition codes 3 67 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 5 H REGISTER OPERATIONS BRANCH EXCHANGE 15 14 13 12 11 10 9 8 7 6 5 3 2 0 2 0 Destination Register 5 3 Source Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 3 34 Format 5 OPERATION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 3 12 NOTE In this group only Op 01 sets the CPSR condition co
22. Accessing Hi Registers in THUMB State In THUMB state registers R8 R15 the Hi registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range RO R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions For more information refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM7TDMI contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are Hold information about the most recently performed ALU operation e Control the enabling and disabling of interrupts e Set the processor operating mode The arrangement of bits is shown in Figure 2 6 condition code flags reserved control bits ai 31 30 29 28 27 26 25 24 23 Overflow b Mode bits Carry Borrow Extend State bit Zero FIQ disable Negative Less Than FRQ disable Figure 2 6 Program Status Register Format ELECTRONICS 2 7 PROGRAMMER S MODEL KS32C65100 RISC MICROPROCESSOR The Condition Code Flags The N Z C and V bits are the condition code flags These may be changed as a result of arithmetic and logical ope
23. CPU Writes CPU Writes SFR Bits SFR Bits DRAM Access Available DRAM Self Refresh Mode DRAM Access Available Figure 4 18 Self Refresh Mode Entry Process by Software NOTES 1 When DRAM does not work self refresh after system initialization Even though KS32C65100 activates self refresh mode when system power connected DRAM may not recognize self refresh mode correctly because of unstable state of control signals during system initialization Most of DRAM recognize the self refresh mode very well at power on When it happens KS32C65100 may fetch corrupted data from external memories because DRAM and ROM share OE Output Enable signal and they may generate data altogether KS32C65100 has a watch dog timer to cope with system malfunction problem When KS32C65100 initialized watchdog timer is enabled and makes external system reset signal unless MCU disables in the mid of operation Therefore it is recommended to put the watch dog ti mer disable code in the boot ROM area to disable watch dog timer If power on initial is not working correctly and KS32C65100 fetches corrupted data watch dog timer will make system reset signal and it will cause KS32C65100 reset once again The seco nd watch dog reset will cause DRAM self refresh mode because when it happens system power and other states are stable 2 DRAM access during self refresh mode If KS32C65100 accesses external DRAM for read or write data during self refresh mode nRAS
24. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 2 1 3 5 9 17 LSL Rt Rb zin ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb zin RSB Rb LSL zin SUB Ra Rt Rb 4 Multiplication by 2 n 2 4 8 LSL Ra Rb n MOV Ra Rb LSL n MVN Ra Ra RSB Ra Ra 0 5 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by any C 2 1 2 n 1 2 n or 2 n 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra n MOV Ra Ra LSL zin 3 92 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code Thumb code signed divide Signed divide of R1 by RO returns quotient in RO remaind
25. The data processing operations may be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected the C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the Z flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions emm AND EOR SUB RSB ADD ADC SBC TST ES CMP ORR 10 Operandt OR operand Operand2 is ignored BIC Operand1 AND NOT operand2 Bit clear MVN NOT operand2 is ignored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of a possible error if the operands were 2 s complement signed The C flag will be set to the carry out of bit 31 of the ALU the Z flag will be set if and only if the result was zero and the N flag will
26. Two 9 pin serial ports SERIAL 1 and SERIAL 2 are supplied for serial data communication between the host PC and the evaluation board You can control the SIO1 SIO2 by setting the jumper and JP5 One 14 pin JTAG port is supplied to connect with the Embedded ICE Unit Three 50 pin connectors U11 U12 U17 are supplied for system expansion They contain board data bus address bus external memory bank device control and external master control signals Five buttons are supplied on the board One button S5 is for system reset and the others S1 S4 S7 are reserved for external intervention during system running Depending on the setting of jumpers JP10 JP14 the S1 S4 S7 are optionally connected to four KS32C65100 s general purpose Input pins GIP3 GIP7 and the external intervention can be detected and handled by S W Five LEDs are supplied on the KS32C65100 board One LED LD9 adjacent to the power connector is for board power indication and the rest LD2 LD5 LD8 is reserved for other status indication LD2 LD5 LD8 are optionally connected with four KS32C65100 s general purpose Output pins GOPA5 GOPA7 GOPA10 Depending on the setting of jumpers JP4 JP6 JP9 their on off status can be controlled by S W ELECTRONICS KS32C65100 RISC MICROPROCESSOR EVALUATION BOARD PARALLEL PORT POWER CON POWER S W SERIAL1 SERIAL2 3 3V
27. half clock than normal fast page mode It is possible because EDO mode can make data valid even if CAS goes to high when RAS is low So it can give enough time to spare for CPU to access and latch the data so that it can reduce memory access cycle time eventually DRAM Bank Space KS32C65100 DRAM interface provides two DRAM banks and each of them are able to have different configuration Users can program the DRAM access cycles memory bank size and bank location by using two identical DRAM control registers DRAMCONO amp 1 DRAM control register has two 9 bits address pointers base and next pointer These two pointers which denote begin and end address of DRAM bank These 9 bits are mapped to the address 24 16 Therefore bank address offset value is 64K byte 16 bits The next pointer contents should be DRAM bank end address 1 Initially Two DRAM banks start and end addresses are 00000000h Therefore DRAM banks are disabled after system is initialized because next pointer and base pointer values are same Initialization When system is initialized two DRAM control register initial values are 00000000h and it specifies mode that the external DRAM is disabled 4 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER DRAM Bank Configuration The DRAM has different write methods from SRAM or other external memories Normally DRAM module has two CAS signals to separate data bus by byte order Therefore RAS signal is use
28. 1 Border data polarity When PCON 1 is 0 the border data which corresponds to the blank area on paper around the image to be printed including the top left right and bottom margins is inverted otherwise the border data is not inverted 3 2 Video clock selection When 21 is 01 the PIFC selects the external video clock 0 VCLKO as its video clock and when PCON 3 2 is 10 the PIFC doesn t selects any clock Otherwise it selects the internal system clock MCLK 6 4 Video clock divisor selection This 3 bit value determines the divisor for the selected video clock 9 7 Video data shrink pattern Using this 3 bit value you can create special effects in the printed image Depending on the video clock divisor n to achieve a fine print edge the size of the first pixel dot that is detected at the left edge of the image is shrunk by 1 n of the normal pixel size or by 2 n 3 n and so on The left edge of an image is defined as the pixel from which a string of consecutive 1 s is detected on a scan line In other words the size of the first pixel in the string of consecutive 1 s is reduced in order to achieve a sharper left edge of the printing area 17 10 Video data chopping Each bit of video data corresponds to a pixel dot in printing and the pixel dot consists of n sub pixels n is the video clock divisor defined by PCON 6 4 To save printer toner one or more sub pixels for each bit pixel can be chopped
29. 40 INSTRUCTION CYCLE TIMES 40 ASSEMBLER SYNTAX quu 41 SINGLE DATA SWAP SWP 43 8 22 222 43 LLLA LA LL M 43 44 INSTRUCTION CYCLE 5 44 ASSEMBLER SYNTAX MM 44 SOFTWARE INTERRUPT 45 RETURN FROM THE 45 COMMENT E ae ee E ee eee 45 INSTRUCTION CYCLE 5 45 ASSEMBLER SYNTAX 46 COPROCESSOR DATA OPERATIONS 47 COPROCESSOR INSTRUCTIONS 2 47 THE COPROCESSOR 5 48 INSTRUCTION CYCLE TIMES 48 ASSEMBLER SYNTAX 2 48 COPROCESSOR DATA TRANSFERS LDC 5 49 THE COPROCESSOR 5 49 ADDRESSING MODES 50 ADDRESS 50 OFRIS 50 B gpd edpcs4 50 INSTRUCTION CYCLE 5 50 3 98 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX eere err reae pea pena e e pe e ere e eere pe enar 51 COPROCESSOR REGISTER TRANSFERS MCR esee nennen 52 THE COPROCESSORH FIELDS rat e rennen nr un RR RE ERE
30. BUSY N nACK N Figure 10 1 Compatibility Hardware Handshaking Timing 10 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE ECP Without RLE Mode ECP without RLE hardware handshaking mode is enabled by setting the PPCON s mode selection bits as 10 i e PPCON 3 2 10 In this mode hardware generates handshaking signals needed to implement the ECP mode parallel port communication protocol When receiving data from host PPIC automatically responds to the high to low transition on nSTROBE by latching the logic levels on PPD7 PPDO and nAUTOFD in the PPDATA register in which the nAUTOFD logic level indicates the current data in PPD 7 0 is a data byte or a command byte and is latched to PPDATA 8 When the PPDATA is read the PPIC drives BUSY high waits for nSTROBE to go high and then drives BUSY low to conclude one forward data transfer operation as shown in Figure 10 2 Reception of a command byte indicated by PPDATA 8 0 causes the command received bit PPIC interrupt pending register to be set to 1 By examining the 7 software will interpret the command byte as a channel address if it is 1 and carry out corresponding operation or interpret the command byte as a run length count if it is 0 and then perform data decompression nAUTOFD y Data byte X N Command byte nSTROBE N N BUSY N N Figure 10 2 ECP Hardware Handshaking Timing Forward
31. Base Point It denotes the start address of extral bank x by word unit 31 23 End Point 1 of Extra Bank n Next Pointer It denotes the start address of next extra bank Figure 4 21 Extra Bank Control Registers ExtCntr O 1 2 3 4 22 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER Address Data fetch t coh Address Data fetch t Data fetch t 1 coh Figure 4 23 Extra Bank Write Timing ELECTRONICS 4 23 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR A C ELECTRICAL CHARACTERISTICS Ta 0 C to 70 3 00V to 3 60V Mim Mex Umi tADDRh Addesshodme dao ms tADDRd _ Address delaytime 251 fNRCS ROM bank chip select delay time 206 tNHOE ROMSSRAMExlObankoutenabledelay 285 INRWE SRAMorExlObankwrteenabledelay 182 Dh jReaddaahodtme Write data delay time SRAM EXIO 98 Write data hold time SRAM EXIO 63 n n n n n n n ns ns tNIOWR Special IO bank write signal delay time o 4 82 ns tWDDd DRAM write data delay time DRAM 2 ms tWDDh DRAM write data hold time DRAM 74 m 4 24 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER Memory mapping for external memory and I O is shown in Figure 4 24 Special Function ROMCON SR
32. If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted result will exactly match that of an instruction specified shift with the same value and shift operation If the value in the byte is 32 or more the result will be a logical extension of the shift described above 1 GE LSL by 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm ROR by n where n is greater than 32 will give the same result and carry out as ROR by n 32 therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 13 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value This value is zero extended to 3
33. In all cases had write back of the modified base not been required 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses do not affect the instruction However the bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 0 100 0x100C 0x1000 0x1000 OxOFF4 0x00 0x1000 OxOFF4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 37 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR 0 100 0x100C 0x1000 0x1000 Ox0FF4 O0x0FF4 0x100C 0x1000 OxOFF4 0x100C 0x100C 0x1000 0x1000 OxOFF4 OxOFF4 0x100C 0x1000 OxOFF4 Figure 3 21 Post Decrement Addressing 3 38 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET 0 100 0x100C 0x1000 0x1000 Ox0FF4 Ox0FF4 221 0x1000 OxOFF4 Figure 3 22 Pre Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruct
34. UART1 Mode Selection Figure 9 1 GDMA CDMA Unit Block Diagram ELECTRONICS 9 1 DMA KS32C65100 RISC MICROPROCESSOR DMA OPERATION The following sections describe the operation of the DMA DMA Transfers The transfers data directly between a requester and a target The requester and target are memory IP GDMA parallel port or external devices An external device requests service by activating an nXDREQ signal A channel is programmed by writing to registers which contain the requester address target address the amount of data and other control contents UART IP parallel port external I O or Software memory can request DMA service UART IP and parallel port are internally connected to the DMA In particular UART1 requests the DMA service to CDMA Bus Control Arbitration Because GDMA CDMA and DRAM controller DRAM refresh can all request bus control bus control priority must be arbitrated The priority of these bus masters is fixed as follows 1 GDMA 2 DRAM controller DRAM refresh 3 CDMA For very fast response of GDMA request GDMA has the highest priority As GDMA has higher priority than the DRAM controller GDMA is used very carefully not to disturb the DRAM controller refreshing the DRAM You may think that GDMA can t move the large amount of data for DRAM because of DRAM refresh but GDMA can transfer the large a amount of data DRAM if user don t use a c
35. zvdO9 VHd 9evdO9 1 viuo ev dO9 0gluo HO dane 8dl9 XHO 6dlO AHO SI vdOOPrTons1 SSA OLdIO LONASH dI9 IQA LdIO 10A aaae 1 oal SWL 8 409 1409 409 409 aaas ddd dd SSA 38ou1su 91 10 21918 103138 103 LL SC 102 SC CONPHA GOPA19 L vss 1 ADDR20 L 19 5 ADDR18 L 3 ADDR16 1 ADDR15 EF ADDR14 7 ADDR13 7 ADDR12 7 ADDRi1 L ADDR10 L 1 ADDR9 7 appre L 3 ADDR7 L 3 appre ADDR5 L 3 ADDR4 svpp L 3 ADDR3 L 1 ADDR2 ADDR F ADDRO L3 vss L 3 DATA15 DATAI4 2 DATA13 L DATA12 2 DATA L DATA10 L DATA9 L 3 DATAS E 5 1 DATA6 1 5 DATA4 L DATAS L 3 DATA2 L DATA DATAO vss nCAS L ncAso 1 nRAS1 C nwE 1 nOE 104 LL SC 100 1 ADDR21 101 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 KS32C65100
36. 26 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR EVALUATION BOARD P in p Re p NW DQ15 VSS1 9 551 552 VCC2 552 VCC2 vSS3 vSS3 VCC3 KM416C1200CT KM416C1200CT 018 H ao A2 5 9 A10 A11 A12 13 14 15 16 52 22 z 30 29 512 ng 24 ae WE Imm gt bot BE D ra eter etel KM681000C_55 32 Dip KM681000C_55 32 Dip lt MEMORY PART gt Figure 29 7 Evaluation Board Schematic 4 ELECTRONICS 26 11 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR nRCS1 GOPA7 nECS2 GOPA8 nlORD GOPA9 nlOWR GOPA10 nXDACK GOPA5 nEXWAIT GIP7 gt nEINT2 GIP5 gt nEINT1 GIP4 gt gt nXDREQ GIP6 IQ O 0i IQ A
37. 5 5 6 1 Shift Control Register 6 2 6 2 Rotation 6 2 7 1 Functional Block Diagram of General 7 1 7 2 ADC Control Register 7 4 7 3 ADC Data Register 7 5 8 1 16 Bit Timer Block Diagram 8 1 8 2 Timer Control Register 8 2 8 3 Timer Count Value Register 8 3 8 4 Timer Programming 8 3 9 1 GDMA CDMA Unit Block Diagram esses 9 1 9 2 External DMA Requests 9 Single 9 3 9 3 External DAM Requests Block 9 4 9 4 External DMA Requests Demand Mode ssss 9 4 9 5 Control 9 7 9 6 Source Destination Address 9 8 9 7 Transfer Count 9 8 9 8 CDMA Control 9 11 9 9 CDMA Source Destination Address 9 12 9 10 CDMA Transfer Count 9 12 10 1 Real Timer Block 10 1 10 2 Real Time Clock Control Register 10 2
38. Negate remainder if dividend sign 1 SUB R1 R2 MOV Ir ELECTRONICS 3 93 ARM INSTRUCTION SET ARM Code signed divide ANDS RSBMI EORS ip bit 31 2 sign of result bit 30 sign of a2 RSBCS a4 a1 amp 80000000 ai al 0 ip a4 a2 ASR 32 a2 a2 0 KS32C65100 RISC MICROPROCESSOR Effectively zero a4 as top bit will be shifted out later Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS BEQ just CMP MOVLS BLO div CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV 3 94 a3 a1 divide by zero a3 a2 LSR 1 a3 a3 LSL 1 S loop a2 a3 a4 a4 a4 a2 a2 a3 a3 a1 a3 a3 LSR 1 S loop2 al a4 ip ip ASL 1 a1 a1 0 a2 a2 0 pe Ir Justification stage shifts 1 bit at a time NB LSL 1 is always OK if LS succeeds ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code Thumb Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 MOV a2 al LSR a3 al 2 SUB a1 a3 LSR a3 al 4 ADD al a3 LSR a3 a1 8 ADD al LSR 16 ADD al LSR al 3 ASL a3 al 2 ADD a3 al ASL
39. PHASE 3 0 Initial value H 1 Normal mode1 LF Scan Mtr output OSC CLK PHASE 3 0 Initial value L 1 o jPscatestmde i O KERN Normal LF Scan Mtr Output 5 3 0 Initial value H OSC CLK 2 Normal mode1 LF Scan Mtr output PHASET 3 0 Initial value L OSC NAND tree test mode 07 14 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The KS32C65100 interrupt structure has a total of 30 interrupt sources which can be individually or globally enabled or disabled Interrupt requests can be generated by internal function blocks and at external pins The core recognizes two kinds of interrupts a normal interrupt request IRQ and a fast interrupt request FIQ Therefore all KS32C65100 interrupts can be categorized as either IRQ or FIQ The KS32C65100 interrupt controller extends the number of multiple interrupt sources that can be serviced by using three special registers INTMOD INTPND and INTMSK Interrupt mode register Defines the interrupt mode IRQ or FIQ for each interrupt source Interrupt pending register Indicates that an interrupt requests is pending that is when the I flag or F flag is set in the program status register PSR This status prevents any additional interrupts from being acknowledged When the pending bit is set the interrupt service routi
40. Roo EN 2 3 FREGISTCTS TEE 2 3 The Program Status Heglstets ine dec eee ii 2 7 2 10 2 11 RO 2 12 Interrupt LatencieS 2 14 pip 2 14 Chapter 3 Instruction Set Instruction Set Sumlmay itt RUE 3 1 Format Summary E 3 1 INSTRUCTION SUMMARY ec E 3 2 The Condition Field 3 3 Branch and Exchange 3 4 Instruction Cycle Times 3 4 Assembler ee i e 3 4 Using R15 As 3 4 Branch and Branch With Link B 8 3 6 MEE dic EE 3 6 Instruction Cycle Times 3 6 Assembler Syntax nc 3 7 KS32C65100 RISC MICROPROCESSOR Chapter 3 Instruction Set Continued Data Processing a eau waa 3 8 GBPSHEIags nnda ae d 3 9 SIUS PM A 3 10 Immediate Operand
41. SWINE 0 Conditionally call supervisor with O in comment field Supervisor code The previous examples assume that suitable supervisor code exists for instance 0x08 B Supervisor EntryTable DCD ZeroRtn DCD ReadCRin DCD WritelRtn Zero EQU 0 ReadC EQU 256 Writel EQU 512 Supervisor STMFD _ R13 RO R2 R14 LDR RO R14 4 BIC R0 R0 Z0xFF000000 MOV R1 RO LSR 8 ADR R2 EntryTable LDR R15 R2 R1 LSL 2 WritelRtn LDMFD R13 RO R2 R15 3 46 SWI entry point Addresses of supervisor routines SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13 svc points to a suitable stack Save work registers and return address Get SWI instruction Clear top 8 bits Get routine offset Get start address of entry table Branch to appropriate routine Enter with character in RO bits 0 7 Restore workspace and return restoring processor mode and flags ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 25 This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM7TDMI and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can
42. Tcsr 0 1 cycle 1 2 cycles 13 21 Refresh Interval Refresh Count Refresh interval 21 Value 1 Example If refresh interval is 15 6us 15 6us 211 value 1 33MHz Refresh conut value 10111111110b Figure 4 16 DRAM Refresh Control and Memory Configuration Register DRAM Refresh Control ELECTRONICS 4 17 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR DRAM Self refresh mode Every DRAM requires refresh operation periodically to keep correct data and JEDEC defines couple of refresh modes The self refresh mode is one of which has defined in JEDEC specification and it enables the DRAM to refresh memory cells internally once it has enabled without periodical external refresh control signals unless other refresh mode happens or power fails The self refresh operation is similar to that of CBR CAS before RAS Once after CPU generates CBR mode signals and it keeps CBR mode state more than 100us DRAMs recognize refresh mode as self refresh instead CBR DRAM Self refresh mode Entry 1 Self Refresh mode by Hardware When system reset pin nRESET is low the system manager block generates self refresh mode signals i e whenever KS32C65100 initialized it activates self refresh mode Hardware refresh feature enables the system to avoid DRAM data loss if system backup supplies power to DRAM while main power is disconnected When system main power is disconnected KS32C65100 will be disabled Meanwhile if DRAM ha
43. Timer 2 Figure 8 1 16 Bit Timer Block Diagram ELECTRONICS 8 1 TIMER KS32C65100 RISC MICROPROCESSOR TIMER CONTROL REGISTER Programmers can disable or enable the timer operation and can select a clock divider output from 4 divided signals by using the Timer Control Register TCON TCON 0x3000 System timer control register 0x000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Timer 0 Enable 0 Stop 1 Run 2 1 Clock Division Factor Selection for Timer 0 01 8 11232 3 Timer 1 Enable 0 Stop 1 Run 5 4 Clock Division Factor Selection for Timer 1 01 8 11232 6 Timer 2 Enable 0 Stop 1 Run 8 7 Clock Division Factor Selection for Timer 2 Figure 8 2 Timer Control Register 8 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR TIMER TIMER COUNT VALUE REGISTER The timer count value registers TBCNTn are used to specify the time out duration for each timers Counting value will be loaded or reloaded into down counter automatically when timer operation is enabled or timer out occurs i e the down counter is decreased to 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Timer 0 1 2 Count Value Figure 8 3 Timer Count Value Register If a programmer changes the contents of TBCNTn while the timer is enabled the new value will be written in this register and the counter continues to
44. boundaries Figure 25 12 Queue 0 1 Start Address Registers 5 QSAR1 ELECTRONICS 25 15 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR QUEUE 0 1 TRANSFER COUNT REGISTERS The values written to the two queue transfer count registers QTCRO and 1 define the transfer count in word 32 bit units when the DMA operation starts for the corresponding queue QTCRO 0xa020 queue 0 transfer count register 0x000000 1 028 PDMA queue 1 transfer count register 0x000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Queue transfer Count 27 0 Queue Transfer Count Value This 24 bits field contains the number of DMA transfers that have been completed in a gived PDMA operation for the respective queue The transfer count value is represented in word 32 bit units NOTE In image expanding operation a restriction is imposed on the queue transfer count value setting i e the count value setting should guarantee the queue boundary being aligned to the image line boundary and the word 32 bit boundary simultaneously In other words if assuming PXL_Q is the least common multiple of PXL value and 32 the queue transfer count should be specified as multiples of PXL_Q 32 Figure 25 13 Queue 0 1 Transfer Count Registers QTCR1 25 16 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER F 0 LENS
45. 0 INT_EOP Figure 25 3 Protocol Diagram PIFC and Printer Engine 25 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER PIFC SPECIAL REGISTERS PDMA AND ENGINE INTERFACE STATUS REGISTER The printer interface controller s PDMA and engine interface status register status contains read only status bits used to monitor the progress of print operations including power ready ready to print print synchronization PIFC status and currently active DMA queue STATUS 0xa000 R PDMA and engine interface status register 0x00 1 0 Reserved 2 Print Synchronization request When STATUS 2 is 1 a print synchronization request is being received from the laser printer engine When the engine issues this request it is ready to receive the synchronization pulse nPSYNC from the KS32C65100 4 3 Current PIFC status The value of this bit pair indicates the current operating status of the printer interface controller There are four states idle pick up counting top margin and active printing 5 Current DMA queue The KS32C65100 uses two DMA queues for dedicated printer DMA 0 and DMA 1 The STATUSJ 5 status bit indicates which queue is currently active during a PDMA operation When STATUSJ5 is 0 DMA queue 0 is active when it is 1 DMA queue 1 is active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 afte x 1 0 R
46. 06 05 04 03 02 01 00 DDT 3 0 Phase A AZ B BZ or 1 IBO 1 This 4 bit out signals control the motor phase 4 LF Motor Control 1 0 Low 1 High 5 LF Motor Control 2 0 Low 1 High 7 6 Default Phase 1 0 When Write 00 AB 01 AzB 10 AzBz 11 ABz 6 PHBZ_IB1 when read 0 low 1 high 7 PHB_IBO when read 0 low 1 high 8 PHAZ_IB1 Read Only 0 Low igh 9 PHA_IA Read Only 0 Low igh 10 LFPHASEB Read Only 0 Low igh 11 LFCON PHA Read Only 0 Low igh Figure 16 2 LF Motor Phase Control Register ELECTRONICS 16 3 LF MOTOR KS32C65100 RISC MICROPROCESSOR LINE FEED TIMER REGISTER This 14 bit timer is used to generate the Line feed motor s phase which is driven by software or hardware according to line feed motor control register LFTBR 0x5808 Line feed motor timer base register 0x00000000 LFTOR 0x580c R Line feed motor timer observation register 0x1e0d AN i LFTCBR 0x5810 R Line feed motor timer compare base 0x0000 register LFTCOR 0x5814 LF motor timer compare observation 0x0000 register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 13 0 Timer Value This time is used to generate line feed motor s phase to phase interval Figure 16 3 LF Motor Timer Register 16 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR LF MOTOR LFCON EACH CONTROL REGISTER This register is us
47. 11 1 UART Block 11 1 11 2 UART Block 11 2 11 3 UART Data Transmission 11 4 11 4 UART Data Reception 55 11 5 11 5 UART Line Control Register ULCONDO 1 2 11 7 11 6 UART Control Register 1 11 9 11 7 UART Status Register 05 0 1 000 11 11 11 8 UART Transmit Buffer Register 1 2 11 12 11 9 UART Receive Buffer Register URXBUFO 1 2 11 13 11 10 UART Baud Rate Divisor Register 1 2 11 14 11 11 Interrupt Based Serial I O Timing Diagram Tx and 11 15 KS32C65100 RISC MICROPROCESSOR xix List of Figures continued Figure Title Page Number Number 12 1 16 Bit Timer Block 12 2 12 2 Timer Control 12 5 12 3 Timer Data Registers TODATA T1DATA and 2 12 6 12 4 Timer Count Registers TOCNT T1CNT and 2 12 7 13 1 PWM Control Register 13 3 13 2 PWM Data Register PWMO 1 0004 13 4 13 3 Block Diagram of 14 bit PWM Output Unit 13 6 14 1 Bi
48. 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 19 0 Register Value Figure 24 3 V Window Time Start End Register LD_ON PRE POST TIME REGISTER LDON Pre Oxd00c LD ON Pre time register 0x00000 LDON Post 0 010 LD ON Post time register 0x00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 19 0 Register Value Figure 24 4 LDON Pre Post Time Register 24 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR LSU CONTROL V WINDOW COUNTER OBSERVATION REGISTER VONT OBS 0 014 V Window counter observation register 0x00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 19 0 Counter Observation Value Figure 24 5 V Window Counter Observation Register LSU MOTOR CLOCK GENERATION COUNTER REGISTER LSUCK_CNT 0xd018 150 Motor Clock counter base 0x00000000 observation register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 083 02 01 00 15 0 Counter Base Value 31 16 Counter Observation Value Figure 24 6 LSU CLK Counter Base Observation Register Caution The counter of the V Window time start end register and the LDON_ pre post time register should be run when the control register s run bit is stop L and the needed initial value is written The value written when the counter is being run is applied after the counting for the previous value is finished
49. 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IWIN START E IWIN END 28 16 IWIN START 12 0 IWIN END This register is to divide the necessary data from the unnecessary data that may be included in the sensor output data For example if IWIN START 20 and IWIN END 1748 it means that the 20th to the 1728th pixel of the ADC output will be handled and output Figure 21 5 IWIN Control Register 21 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR CHANGED IWIN CONTROL REGISTER CHANGED IWIN 0 9818 Mag Red pixels num control register 0x06b8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 0 CHANGED PIX NUM This register inputs the modified pixel values if the data is being magnified or reduced horizontally 13 12 NOR MAG RED 00 Normal 01 Magnification 10 Reduction Figure 21 6 CHANGED WIN Control Register MAG RED RATIO CONTROL REGISTER RATIO 0x981c Mag Red ratio control register 0x10080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 VER RATIO Vertical reduction ratio of 1 128 unit 16 8 RATIO Horizontal reduction magnification ratio of 1 256 unit Figure 21 7 Mag Red Ratio Control Register ELECTRONICS 21 5 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR LAT LOCAL ADAPTIVE THRESHOLD CONTROL REGISTER 0x9820 Local adaptive th
50. 3 12 1 Timer Control Register 12 3 12 2 Timer Data Registers 12 6 12 3 Timer Count Registers 12 7 13 1 PWMO PWM1 Control and Data 13 5 13 2 PWM Output Stretch Values for Extension Registers and PWM1 13 5 14 1 Port Mode Configuration and 14 1 15 1 Interrupt SOUICES RR 15 2 29 1 Jumper 29 7 29 2 Switch 29 7 xxvi 517 80064 80013 80013 MICROCONTROLLER KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW INTRODUCTION PRODUCT OVERVIEW Samsung s 532 65100 16 32 bit RISC micro controller is designed to provide a cost effective and high performance micro controller solution for ink jet laser jet printers and MFP An outstanding feature of the KS32C65100 is its CPU core 16 32 bit RISC processor ARM7TDMI designed by Advanced RISC Machines Ltd The ARM7TDMI core is a low power general purpose microprocessor macro cell that was developed for use in application specific and custom specific integrated circuits Its simple elegant and fully static design is particularly suitable for cost sensitive and power sensitive applications The KS32C65100 was developed using
51. 32 bit dot counter for mono e Fire strobe delay for horizontal alignment of dot 8 bit decrement timer for the width of the fire enable pulse of print head logic using MCLK e 10 bit decrement timer for the width of the fire group window of print head logic using MCLK e Four 12 bit timers for the fire strobe delay using selectable clock clock main clock 1 2 4 or 8 4 bit decrement counter for Td delay e 6 pre heat pulse timer e 6 bit pre heat delay timer Head Control Register Head Type Number of Data PHCR 8 PHCR T PHCR 1 1 DH mono head 208 nozzle 13 half word DH colour head 192 nozzle 12 half word o 1 o3 o 0 jSHmonohead S6nozzie 4halwod 1 _ 1 SH colour head 48 nozzle 3 half word SH mono head 56 nozzle 7 bytes SPECIAL FUNCTION REGISTER PRINT HEAD CONTROL REGISTER PHCR 0xa000 Print head control register 0x000000 ELECTRONICS 19 1 PRINT HEAD KS32C65100 RISC MICROPROCESSOR 19 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 m 3 0 Dither Count Bit 4 Decrement Through Enable Group 0 Up 1 Down 5 Black Dot Counter Select 0 Disable 1 Enable 6 Color Dot Counter Select 0 Disable 1 Enable 7 Color Head Select 0 Black 1 Color 8 Head Type Select 0 208 192 nozzle head 1 56 48 nozzle head 9 Cons
52. 5 m lt gt E e 14 DI GIP13 I lt nLREADY GIP11 HSYNC1 GIP10 ND 5 SU CLK GOPA15 nVDD1 GOPA14 nVDD2 GOPA29 PWMO2 GOPA13 PWMO1 GOPA12 PWMO0 GOPA11 2 D IP9 D INO IP8 D RIB1 PA28 papu eI 92 Al 4548 Sa sola GAAS ISO ON BE SSE R2 SC CONPHB GOPA20 Figure 29 4 Evaluation Board Schematic 1 00 ELECTRONICS KS32C65100 RISC MICROPROCESSOR EVALUATION BOARD W CAP SW sPDT POWER 3 3V gt D D zit nREST 1 c lt 45V 5V ai VDD VDD por swt POWER 3 3V 33 2 gt 3vpp J ON T lt POWER PART gt 7T C104 Ls NP 2 OSC L to lt RESET PART gt 3 C37 CAP NP 3 L EN 2 2 rr R92 6k l OSCO lt OSC 8 CRYSTAL PART gt 1 lt ADC PART g
53. AmA Normal output buffer with medium slew rate PHOT4SM AmA Tri State output buffer with medium slew rate 1 03 PHBLU50T8SM 50K 8mA TTL schmitt trigger level input with pull up resistor and Tri State output with medium slew rate 1 04 PHBLT4 AmA TTL schmitt trigger level input and Tri State output PHOB8SM 8mA Normal output buffer with medium slew rate 1 1 07 1 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW KS32C65100 SPECIAL FUNCTION REGISTERS Table 1 2 KS32C65100 Special Function Registers SYSCFG 0x0000 R W System register address configuration 0x1001 register System Manager ate Cach 0 0000000 0 0000000 OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX OXXXXX SFTCON 0x5004 Shift control register 0x04 DRASTO 0x4800 Derasterizer data register 0 OxXXXX DRAST1 0x4804 Derasterizer data register 1 OxXXXX Derasterizer i i 7 ELECTRONICS 1 11 PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR Table 1 2 KS32C65100 Special Function Registers Continued Group Register RW Description Reset Value TCON 0x3000 System timers control register 0x000 Ti TBCNTO 0x3004 Timer base count register 0 OxXXXX imer TBCNT1 0x3008 Timer base count register 1 OxXXXX TBCNT2 0 301 Timer base count register 2 OxXXXX DMACONO 0x8800 CDMA control register 0x00000 DMASRCO 0x8804 CDMA source address register Ox
54. B instructions is influenced by the BIGEND control signal of ARM7TDMI core The two possible configurations are described below NOTE The KS32C65100 is configured to the big endian format Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register Two shift operations are then required to clear or to sign extend the upper 16 bits A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 ELECTRONICS 3
55. Board Schematic 2 29 9 29 6 Evaluation Board Schematic 3 29 10 29 7 Evaluation Board Schematic 2 29 11 29 8 Evaluation Board Schematic 2 29 12 KS32C65100 RISC MICROPROCESSOR xxiii List of Tables Table Title Page Number Number 1 1 Pin 1 6 1 2 KS32C65100 Special Function Registers 1 11 2 1 PSR Mode bit Values 2 9 2 2 Exception 2 11 2 3 Exception Vectors ee eee ren 2 13 3 1 The ARM Instruction 3 2 3 2 Condition Code 3 3 3 3 ARM Data Processing 8 3 9 3 4 Incremental Cycle 8 3 14 3 5 Assembler Syntax 3 23 3 6 Addressing Mode 3 41 3 7 THUMB Instruction Set 3 61 3 7 THUMB Instruction Set Opcodes 3 62 3 8 Summary of Format 1 3 63 3 9 Summary of Format 2 3 64 3 10 Summary of Format 3 65 3 11 Summary of Format 4 5
56. C are defined as sequential S cycle internal I cycle and coprocessor register transfer C cycle respectively MCR instructions take 1S bl 1C incremental cycles to execute where bis the number of cycles spent in the coprocessor busy wait loop ASSEMBLER SYNTAX lt MCR MRC gt cond p lt expression1 gt Rd cn cm lt expression2 gt MRC Move from coprocessor to ARM7TDMI register L 1 MCR Move from ARM7TDMI register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field Rd An expression evaluating to a valid ARM7TDMI register number cn and cm Expressions evaluating to the valid coprocessor register numbers CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field Examples MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 c5 and transfer the single 32 bit word result back to R3 MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 R4 and place the result in MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and 6 and transfer the result back to R3 ELECTRONICS 3 53 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR UNDEFINED INSTRUCTION The instruction is only executed if the condition is true The various conditions are
57. COMPENSATION CONTROL REGISTER 0 F 0 Enable Disable if 0 Enable if 1 1 CPU Access Enable 0 F 0 compensation block accesses the F 0 table memory read write 1 CPU access To configure a table this bit must be set to 1 before CPU write 2 Clock Selection Select divided clock 0 MCLK 2 1 External video clock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 st 0 F gt Compensation Enable 0 Disable 1 Enable 1 F Compensation Table Access Mode 0 Normal mode 1 CPU access mode 2 F Compensation Clock Selection 0 MCLK 2 1 External video clock Figure 25 14 F Compensation Control Register FTCON ELECTRONICS 25 17 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR F 0 COMPENSATION TABLE START ADDRESS This is the start address for accessing the table read write normal access mode CPU access mode etc If you wish to access a different access during operation you must change this register value If you access after writing 00 the compensation block accesses from 00 in order If you write 20h to this register it accesses from 20h FSADDR 0xa030 Table start address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 6 0 F Compensation Table Start Address Holds the start address for accessing the table You need 7 bits for the access because the table is
58. Controller Q1 start address register Q1 transfer address register F 0 control register F 0 start register F 0 data register Toner counter set value register Tone count value register Test pattern period value register Test pattern on length register 0x00 Oxeffb 0x00000000 0x00000000 0x00 0x00 o lt 2 o 1 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 KS32C65100 Special Function Registers Continued Register R W Description Reset Value LSUCON 0 000 LSU control register 0x0000 VWIN STR 0xd004 V Window time start register 0x00000 VWIN END 0xd008 V Window time end register 0x00000 Pre 0 00 LDON Pre On time register 0x00000 LDPON Post 010 LDON Post On time register 0x00000 VONT OBS 0 014 V Window counter observation register 0x00000 LSUCK_CNT 0xd018 R W LSU Motor Clock counter base amp 0x00000000 observation register GADC ADCCON 0xd800 ADC control register 0xa0 ADCDATA Oxd804 R ADC data register OxXXX SEN_CLK 0x9800 Sensor shift signal period register 0x00818 SI TERM 0x9804 Sensor SI signal period register 0 09 4 RLED 0x9808 Sensor R led signal period register 0x00000960 GLED 0x980c Sensor G led signal period register 0x00000960 BLED 0x9810 Sensor B led signal period register 0x00000960 IWIN 0x9814 Image area register 0x000006b8 CHANGED_IWIN 0 9818 Magnified reduced pixels num register 0x06b8 Imag
59. ELECTRONICS 24 5 KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER PRINTER INTERFACE CONTROLLER OVERVIEW The PIFC performs direct memory accesses to fetch video data and then serializes the data and handshakes with the printer to transmit the video data after pattern procession It has the following important features It uses dedicated DMA to accelerate data transfers between page memory and the laser printer engine The dedicated DMA supports queued operations to facilitate the smooth switching between blocks of banded page memory The PIFC s DMA controller can transfer strings of consecutive zeros the 0 s in a given banded bit map or blank data without accessing external memory The length of a zeros string is determined by the value in the transfer count register of the PIFC s queue 0 or queue 1 The KS32C65100 PIFC employs pixel chopping to save printer toner It provides a fine edge to print images by shrinking the first pixel dot whenever there is a string of consecutive 1 s that is at the position where the left edge of the image starts It supports 2 to 4 times image expanding print It is able to control top margin left margin and image width for page layout ELECTRONICS 25 1 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR PAGE IMAGE DATA FETCH OPERATION Page images are stored in an area of memory known as the band buffer After a page image is rendered the PIFC can be programmed to fe
60. Format 10 Load Store Halfword 3 78 Format 11 SP Relative Load Store 3 79 12 Load Address sink denda a uda duds 3 80 Format 13 Add Offset To Stack Pointer 3 82 Format 14 Push Pop Registers 3 83 Format 15 Multiple 3 85 Format 16 Conditional Branch 3 86 Format 17 Software Interrupt 3 88 Format 18 Unconditional 3 89 Format 19 Long Branch With n nnn nnn niens sens 3 90 Instruction Set 3 92 Multiplication by A Constant Using Shifts and Adds 3 92 General Purpose Signed 3 93 Division DYA Consta aad adidas ie 3 95 viii KS32C65100 RISC MICROPROCESSOR Table of Contents Continued Chapter 4 System Manager OVeIVIGW cR RAE au audae 4 1 System Manager Registers 5 4 1 System Register Address Configuration Register 5 5 4 4 ROM Control 4 6 SRAM Control 4 11 DRAM Control 2 4 14 DRAM Refresh Control 4 17 Ext
61. INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 25 24 23 22 21 20 19 16 15 12 11 8765 43 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfwords 1 0 Signed byte 1 1 Signed halfwords 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Write address into base 21 Write Block 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset before transfer 31 28 Condition Field Figure 3 16 Halfword and Signed Data Transfer with Register Offset 3 30 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET 28 27 25 24 23 22 21 20 19 16 15 12 11 87 6 5 43 3 0 Immediate Offset low nibble 6 5 S H 0 0 SWP instr
62. It s important that the transfer width is not the size of a physical data bus The size of physical data bus is determined by SMR configurations 14 Continuous mode This bit specifies that CDMA operations hold the system bus until the count value is 0 Therefore this bit must be carefully used unless the whole operation time can not over appropriate interval 16 Byte swap mode When the transfer size is halfword or a word this bit specifies whether a byte swap operation has occurred or not For example if this bit is set to 1 11223344h read 44332211h write NOTE All control bits have to be configured independently and carefully 9 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR DMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMACONO 0 Run Enable 0 Disable CDMA operation 1 Enalbe CDMA operation 1 Busy Status 0 CDMA idle 1 CDMA active 3 2 Mode Selection 00 Software 01 External nXDREQ 10 Parallel port 11 UART1 port 4 Destination Address Direction 00 Increase address 1 Decrease address 5 Source AddressDirection 0 Increase address 1 Decrease address 6 Destination Address Fix 0 Increase decrease address 1 Do not change address fix 7 Source Address Fix 0 Increase decrease address 1 Do not change address fix 8 Stop Interrupt Enables 0 Do not generate stop interrupt when CDMA stops 1 Generate st
63. KS32C65100 RISC MICROPROCESSOR FORMAT 17 SOFTWARE INTERRUPT 15 14 13 12 11 10 9 8 7 0 Cep 7 0 Condition Figure 3 46 Format 17 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM state and enters Supervisor SVC mode The THUMB assembler syntax for this instruction is shown below Table 3 24 The SWI Instruction THUMB Assembler Equivalent Acton O SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 24 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples SWI 18 Take the software interrupt exception Enter supervisor mode with 18 as the requested SWI number 3 88 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 18 UNCONDITIONAL BRANCH 15 14 13 12 11 10 0 10 0 Immediate Value Figure 3 47 Format 18 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the
64. LSL 2 CMP Rb 5 ADDCS Rc Rc Ra ADDHI Rc Rc Ra Combining Discrete and Range Tests TEQ 127 Rc 7 1 MOVLS ELECTRONICS If Rn p OR Rm q THEN GOTO Label If condition not satisfied try other test Test sign and 2 s complement if necessary Multiply by 4 Test value Complete multiply by 5 Complete multiply by 6 Discrete test Range test IF Rc OR Re ASCII 127 THEN Re 3 55 ARM INSTRUCTION SET Division and Remainder KS32C65100 RISC MICROPROCESSOR A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM cross development Toolkit available from your supplier A short general purpose divide routine follows MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Div1 Div2 Rent 1 Rb 0x80000000 Rb Ra Rb Rb ASL 1 Rent Rent ASL 1 Div1 0 Ra Rb Ra Ra Rb Rc Rc Rent Rent Rent _SR 1 Rb Rb LSR 1 Div2 Overflow Detection in the ARM7TDMI 1 Overflow in unsigned multiply with a 32 bit result UMULL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 2 Overflow in signed multiply with a 32 bit result SMULL TEQ BNE Rd Rt Rm Rn Rt Rd ASR 31 overflow Enter with numbers in Ra and Rb Bit to control the division Move Rb until greater than Ra Test for possible subtraction Subtract if ok Put relevant bit into result Shift control bit Hal
65. Last DRAST15 is Written by S W DRASTO bitO At First 0 is Read 2 nd v1 15 is Read by S W Figure 6 2 Rotation Configuration 5 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR DERASTERIZER Example 1 Original 270 degree DRAST15 I DRASTO DRAST14 LLL Lt TT Tt DRAST1 DRAST13 DRAST2 DRAST12 DRAST3 DRAST11 DRAST4 DRAST10 DRAST5 DRAST9 L 1111 DRAST6 DRAST8 DRAST7 DRAST7 E E E323 E DRAST8 DRAST6 DRAST9 DRAST5 DRAST10 DRAST4 DRAST11 DRAST3 T T T T DRAST12 DRAST2 I DRAST13 DRAST1 EN DRAST14 DRASTO DRAST15 DRASTO DRAST1 DRAST2 DRAST3 DRAST4 DRAST5 DRAST6 DRAST7 DRAST8 DRAST9 DRAST10 DRAST11 DRAST12 DRAST13 DRAST14 DRAST15 SFTCON 3 0 90 degree ELECTRONICS 6 3 KS32C65100 RISC MICROPROCESSOR GENERAL ADC GENERAL ADC OVERVIEW The 10 bit CMOS A D converter consists of the 3 channel analog input multiplexer auto offset calibration comparator high resolution R string DAC clock generator 8 bit successive approximation register SAR ADC control register ADCCON and the tri state output register ADCDATA The CMOS comparator includes sample and hold functions without such a circuit and has high comparator gain in two stages This ADC provides software selection power down mode The device operates with a single 3 3V supply and its A D conversion rate is 500 KSPS
66. MOD 4 3 say C 2 n D 1 D odd n gt 1 D 1 RSB Rb Ra Ra LSL n D lt gt 1 Rb Ra D RSB Rb Ra Rb LSL n This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB Rb Ra Ra LSL 2 Multiply by 3 RSB Rb Ra Rb LSL 2 Multiply by 4 3 1 11 ADD Rb Ra Rb LSL 2 Multiply by 4 114 1 45 rather than by ADD ADD 3 58 Rb Ra Ra LSL 3 Rb Rb Rb LSL 2 Multiply by 9 Multiply by 5 9 45 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Rc Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Rc LSL Rb Enter with address in Ra 32 bits uses Rb Rc result in Rd Note d must be less than c e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes how in bits and test if aligned Produce bottom of result word if not aligned Get other shift amount Combine two halves to get result 3 59 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the A
67. REGURATOR POWER LED TEST S W ROM LOW ROM HIGH RTC BATTERY ICE PORT MOTOR PORT REST DATA PORT 55 O Figure 29 1 Evaluation Board ELECTRONICS 26 3 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR BOOTING SYSTEMT After power is turned on the Boot Code is activated automatically The Boot Code then performs system initialization and configuration Once this procedure is completed the four LEDs LD1 LD4 on the bottom of the board should light on together At the same time a message appears on the PC which shows that the system is waiting for program downloading If four LEDs fail to light on the board is either faulty or incorrectly powered If the LEDs light on but no message or some strange symbols appear on the communication window activated on the host PC you should check if the parameter setting for the communication window such as the Hyper Terminal is matched to the relative setting for board such as baud rate parity stop bit setting and so on Power Supply Application Board Debug Host RS232C Cable Figure 29 2 Connection to Host PC Power Supply Application Board Figure 29 3 Connection to Embedded ICE 26 4 EL
68. ROM control register is SYSCFG address Offset address of the ROM control register ROMCON 0x1000 ROM control register 0x02003002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 08 02 01 00 1 0 Bus Width DW 10 2 16 half word Others No use The ROM interface supports only 16 bits of external data bus width 8 7 Page Mode Configuration Pmc 00 Normal ROM 01 4 data page 10 8 data page 11 2 16 data page 10 9 Page Mode Access Cycles Tacp 00 5 cycles 01 2 cycles 10 2 3 cycles 11 4 cycles 13 11 Access Cycles for ROM Bank Tacc 000 Disable bank 100 5 cycles 001 2 cycles 101 6 cycles 010 3 cycles 110 7 cycles 011 4 cycles 111 Not used 22 14 Start Point of ROM Bank Base Pointer Indicates ROM bank start address 31 23 End Point 1 of ROM Next Pointer Indicates ROM bank end address 1 Next point value has to be bigger than base point value if base point and next point value are same ROM bank is not valid anymore Figure 4 4 ROM Control Register ROMCON 4 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER Page mode ROM Access Burst mode Access KS32C65100 ROM can be interfaced with simple ROM and page mode ROM Programmers can make burst mode enable or disable and can define the readable number of burst data by using ROMCON 8 0 ROM has two different access cycles for simple ROM and page mode ROM When a new bank ha
69. Ro Load sign extended halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to bit 15 3 74 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R3 RO Store the lower 16 bits of R4 at the address formed by adding RO R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding R1 R7 LDSH R3 R4 R2 Load into the sign extended halfword found at the address formed by adding R2 R4 ELECTRONICS 3 75 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 15 10 6 5 3 2 0 14 13 12 11 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Value 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity Figure 3 38 Format 9 OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 3 16 Table 3 16 Summary of Format 9 Instructions STR Rd Rb Imm STR Rd Rb Imm Calculate the target address b
70. The D A converter generates the digitized analog output DAOUT from data of SAR logic block as follows DAOUT AVREF AVSS 128 x D 9 0 where AVREF and AVSS are analog reference voltage and ground that are applied to the comparator and the D A converter block This 128 resolution DAOUT is supplied to the CMOS comparator XP1 Generator and Clock Generator CLKDIV and CKGEN The CLKDIV block of the A D converter in KS32C65100 can choose two clock sources x2 and x4 from system clock MCLK by setting the CLKSEL bit of the ADCCON register For the selected clock XP1 CKGEN block generates CLK1 CLK2 and DACLK CLK1 2 are used the comparator while DACLK is used to operate the SAR logic block Note that the maximum frequency of XP1 is 25MHz A D Conversion Time When we use the main oscillation frequency of 33MHz and select the A D converter clock to XPx4 then the total 10 bit conversion time is as follows 33MHZ 4 divide 4 frequency 45 at least 45 cycles by 10 bit operation 183 3kHz 5 45us This A D converter was designed to operate at 25MHz XP1 clock source and the maximum conversion rate goes up to 500 KSPS Power Down Mode When the power down mode is activated by setting the STBY bit of the ADCCON register to 1 the A D converter is kept in standby mode without A D conversion operation If STBY bit is set to 1 even at A D conversion mode flag bit goes high immediately When the DGET is activated by rea
71. The equivalence between the names and the values of the bits in the instruction are shown in the following table 3 6 Table 3 6 Addressing Mode Names Sek Fosicemmbai 9 Pre decrementioad omea twp 9 Post decrementioad imma 1 9 9 Pre incrementstore sme Fosmemmswe o 9 Pre decrementsre sm t 9 Fosseemersoe FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to a full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or descending If ascending a STM will go up and LDM down if descending vice versa IA IB DA DB allow control when LDM STM are not being used for stacks and simply mean increment after increment before decrement after decrement before ELECTRONICS 3 41 ARM INSTRUCTION SET Examples LDMFD SP RO R1 R2 STMIA RO RO R15 LDMFD SP R15 LDMFD SP R15 STMFD R 3 RO0 R14 KS32C65100 RISC MICROPROCESSOR Unstack 3 registers Save all registers R15 lt SP CPSR unchanged R15 SP CPSR SPSR mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged
72. The external clock XP1 is 25MHz The operating temperature range is 0 70 C according to commercial specifications FUNCTIONS AIN 2 0 CLKGEN OUTREG MODE8 ADEN STBY ADCCON ADCDATA CLKSEL Figure 7 1 Functional Block Diagram of General ADC ELECTRONICS 7 1 GENERAL ADC KS32C65100 RISC MICROPROCESSOR SAR SUCCESSIVE APPROXIMATION REGISTER A D CONVERTER OPERATION A SAR type A D converter basically consists of the comparator D A converter and SAR logic At the beginning of the conversion the MSB is switched on and the analog input signal is compared to the output signal of the D A converter When the input signal is larger than the output signal of the D A converter then the MSB remains on and the next bit is switched on and a comparison will be performed A bit by bit operation is performed in this system to bring the D A output signal within 1 LSB to the time discrete input signal COMPARATOR COMP AND DAC DIGITAL TO ANALOG CONVERTER The CMOS comparator produces digital output as the result of comparing selected analog input with reference voltage This comparator operates every CLK1 and CLK2 where the two clocks are non overlapping and have anti phase Note that the comparator has no sample and hold circuit for the reduction of the current consumption Especially the D A converter consists of 128 resistor strings and switches with 7 bit resolution So the comparator performs the comparison with 3 bit resolution
73. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The following table shows the exception vector addresses Table 2 3 Exception Vectors Mes Exe MedonEwy Foxoo000010 mox mox 000000010 Abort data 0100000014 000000018 0x0000001C ELECTRONICS 2 13 PROGRAMMER S MODEL KS32C65100 RISC MICROPROCESSOR Exception Priorities When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority Reset Data abort FIQ IRQ Prefetch abort Lowest priority 6 Undefined instruction software interrupt Not All Exceptions Can Occur at Once Undefined Instruction and software Interrupt are mutually exclusive since they each correspond to particular non overlapping decodings of the current instruction If a data abort occurs at the same time as a FIQ and FIQs are enabled i e the CPSR s F flag is clear enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing dat
74. WR CLK SW ADDR 11 0 RAM Write by Register SW RAM RD CLK SW ADDR 11 0 RAM DOUT 31 0 SD RAM Read by Register Figure 21 25 Timing Diagram SRAM Read Write by Register ELECTRONICS 21 19 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR The CONTROLLER has the following features so that it can read or write on the RAM using the register There is the RAM CTRL 14 12 s CHIP SELECT for selecting the internal SRAM The SRAM s first ADDRESS is received through the register This value is loaded using the value of the register called SW ADDR After setting the environment if you record the value to the register RAM DATA it is read or written to the SRAM The RAM ADDRESS increases by 1 for each READ WRITE from the original value from the register This process can be summarized as follows e Record first address of the SRAM area for read write and choose the SRAM RAM CS e Initialize the SRAM address Register SW RAM ADDR INIT e Record value on the register RAM_DATA during write e Read using the register RAM_DATA s address value during read NOTE When you read the register value the internal ram must not be selected Of course when you read the internal ram values the internal ram has to be selected DMA OUTPUT Binary Data Output The binary data output through the IP goes through the 32 bit cycle stealing DMA process In other words if the binary data for 32 pixels is
75. When 1 is set to 1 and the counter overflows before the generation of the next interrupt the DC motor interrupt is generated and the counter and pre step timer are cleared and restarted e The DC motor interrupt is generated in DC mode when the photo encoder sensor input s rising edge occurs for the number of times specified in the pre step timer Counting Result Register and Observation Register INTTIM 0x6028 R Interval counter observation register 0x0000 INTVAL 0 602 R Interrupt interval value register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Interrupt Interval Value Figure 17 7 Interrupt Interval Value Register 17 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR CONTROL SUGGESTIONS FOR CARRIER MOTOR DRIVE F W DESIGN When CR Motor is Stopped e The BASIC timer and PRESTEP timer s RUN bit must be reset to 0 Bits 0 1 of CMCR 0x6000 position block enable bit bit 0 of PFCR 0x6820 must be reset to When CR Motor is Restarted e Must write new or previous values in the BASIC timer base registers Must write new or previous values the PRESTEP timer base Register Must set the position block enable bit bit 0 of PFCR 0x6820 to 1 Must set BASIC timer and PRESTEP timer s RUN bit to 1 In other words before starting Re RUN after stopping the BASIC timer you must e Rewrite the B
76. a3 1 SUB a2 a3 CMP a2 110 BLT FTO ADD al 1 SUB a2 10 0 MOV Ir ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB al al Isr 2 ADD a1 a1 a1 Isr 4 ADD al a1 al Isr 8 ADD a1 a1 al Isr 16 MOV a1 a1 Isr 43 ADD a3 a1 a1 asl 42 SUBS a2 a2 asl 1 ADDPL al a1 1 ADDMI a2 a2 10 MOV Ir ELECTRONICS 3 95 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR INSTRUCTION SET SUMMAY 2 ei 1 FORMAT SUMMARY te eee rue e utu 1 INSTRUC MON SUMMARY em 2 CONDITION FIELD iriiri aeee EE NINN E ANE AEE NET ENEE ENNEN 3 EXCHANGE a a a ES 4 INSTRUCTION CYCLE TIMES Kiriri a KNEE 4 ASSEMBLER SYNTAX ee R T a R R RR eR ee sees 4 USING R15 AS AN OPERAND neret tentent emet KA AEE E E EE NEAN A ee ee e tana 4 BRANCH AND BRANCH WITH LINK B 6 zug M 6 INSTRUC HONG YGLE TIMES tesa egre saec edad sh aie eit einai eee eee ture 6 ASSEMBLER SYNTAX cree reete Pt tene eU e Eee UR RU uU Ue UL e eU E EUR 7 DATA PROCESSING 5 5 ela ele el tuta Sole ele ale tato Salo fede DoD fete So tubo 8 O PSR IN OA AAA II 9 10 IMMEDIATE OPERAN
77. an ARM7TDMI core 0 35um CMOS standard cells and a memory compiler Most of the on chip function blocks were designed using an HDL synthesiser The integrated on chip functions that are described in this document include 2KB Instruction data cache and controller PLL Phase Locked Loop Clock save control DMA control 3 channel Interrupt control UART 3 channel 16 bit Timer 3 channel PWM timer 3 channel Watch dog timer A D converter 8 10 bit 3 channel General I O port control Scan image control Scan motor control Tone generator Real time clock Parallel Port Interface control Print head control Carrier motor control Paper motor control Laser Printer Interface control Laser engine control S W assistant function rotator ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES Architecture 16 32 bit RISC architecture e Efficient and powerful ARM7TDMI CPU core Cost effective JTAG based debug solution System Manager e 16 bit external bus support for ROM 8 16 bit external bus support for SRAM DRAM Fast Page EDO and external I O e Programmable access cycle 2 7 wait cycles e Support idle mode for low power consumption Unified Instruction Data cache Two way set associative cache with 2KB e LRU Least Recently Used Four depth write buffer PLL Frequency Synthesiser Input freq range 10MHz 40MHz e Jitter 150 ps e External loop filter 820 pF DMA Direct Memory A
78. and nCAS signals are not working at all DRAM accessing during the self refresh mode may cause corrupted data read or writing ELECTRONICS 4 19 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR 3 Memory access is forbidden when the SMR is changed The external bus is disabled when MCU accesses any of SMR to change the system memory configurations It is for preventing the system malfunction which will be caused by memory address space overlaping during the new configuration To re activate external bus operation The VSF bit in refresh register need to be set to 1 by writing SMRs with STMIA ARM instruction While STMIA instruction writes 10 registers SRMs refresh reigster must be written at the last step with VSF bit has 1 so that external bus can be re activated right after system manager register has new configuration It is not recommended to change the SFRs after system initialization If SFR changed especially memory related areas users have to flush cache memory for the data coherency Address Figure 4 19 DRAM Refresh Timing 4 20 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER EXTRA BANK ACCESS CONTROL REGISTERS The KS32C65100 provides four extra banks and four Extra Bank Control registers EXTCONn controls timing bank size and bus width The extra bank 3 has the special features compared with other extra banks It has one special dedicated addresses refer to SRAMO control registers for providing the low co
79. can be found by the following formula yu KB x 256 W B Here the process of storing the value that will read the white pad W in memory is called white shading acquisition If you set the shading acquisition bit to 1 and scanning process is performed the value is immediately stored in the shading memory If you go into the scanning process after this step the shading corrected value for the actual value is generated using W and B as reference Real Scanned Value Black Pad Value 8 Bits 16 8 8 Bits Shift Shading Corrected Divider amp Clamping Value 8 Bits White Pad Value Black Pad Value 8 Bits Figure 21 19 Shading Correction Block Diagram 21 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR GAMMA CORRECTION This process uses a 256x8 bit SRAM to carry out gamma correction of the RGB value that was shading corrected in the previous step Gamma Table SRAM 256 8 Bits Gamma Corrected Value 8 Bits Data 7 0 Shading Corrected Value 8 Bits Address 7 0 Figure 21 20 Gamma Correction Block Diagram BINARIZATION Error Diffusion This process is for binarization in the image mode The algorithm used is in the FLOYD method and uses the mask given below 1 UC 5 U 3 UR 70 Input Pixel C pe 1 16 x Error UL 5 16 x Error U 8 16 x Error UR 7 16 x Error L Binary output decision and error calculation IF C 2 128 OUT White
80. coprocessor and a coprocessor will ignore any instruction which does not contain its number in the CP5 field The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field and possibly in the CP field on the contents of CRn and CRm and place the result in CRd INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where bis the number of cycles spent in the coprocessor busy wait loop S and are defined as sequential S cycle and internal I cycle ASSEMBLER SYNTAX CDP cond p lt expression1 gt cd cn cm lt expression2 gt cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field cd cn and cm Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field Examples CDP p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and CR3 and put the result in CR1 CDPEQ 2 5 1 2 3 2 If Z flag is set request coproc 2 to do operation 5 type 2 on CR2 and CR3 and put the result in CR1 3 48 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are
81. count with new value Example The timer programming sequence is shown below The count value and timer clock definition including the prescaling value and clock division factor should be specified before the timer enable bit setting Set prescaling value in TSTCON Select clock division factor in TCON Set count value in TBCNTn Set timer enable bit to start the timer operatio Figure 8 4 Timer Programming Sequence ELECTRONICS 8 3 KS32C65100 RISC MICROPROCESSOR DMA DMA OVERVIEW The KS32C65100 has two general direct memory access channels GDMA CDMA These DMA channels perform the data transfers between the following sources without CPU intervention e Memory and memory e P and memory GDMA Parallel port and memory CDMA Serial port and memory The on chip DMA controller can be started by software and or by an external DMA request DMA operation can also be stopped and restarted by software The CPU can recognize when a DMA operation has been completed by software polling and or by interrupt request The 532 65100 controller can increase or decrease source or destination address and conduct 8 bit byte 16 bit half word or 32 bit word data transfers Detailed information about the DMA block s operation is provided in the descriptions of each DMA register Mode Selection DMA Channel 1 nDREQ Disabled nXDACK nXDREQ DMA Channel 0 Parallel Port nDREQ S Y S T E M B U S
82. defined in Table 3 2 The instruction format is shown in Figure 3 28 31 28 27 25 24 543 0 011 XXXXXXXXXXXXXXXXXXXX XXXX Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 2S 11 1N cycles where S and are defined as sequential S cycle non sequential N cycle and internal I cycle ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 54 ELECTRONICS KS32C65100 RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES ARM INSTRUCTION SET The following examples show ways in which the basic ARM7TDMI instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some mostly they just save code USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Rn p BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q BEQ Label Absolute Value TEQ Rn 0 RSBMI Rn Rn 0 Multiplication by 4 5 or 6 Run Time MOV Rc Ra
83. directional Port Mode Register 14 3 14 2 Input Port Mode Register GIPMOD 14 3 14 3 Output Port Mode Register GOPAMOD 14 4 14 4 Output Port Mode Register 000070 14 4 14 5 Bi directional Port Data Register 14 5 14 6 Input Port Data Register 14 5 14 7 Output Port A Data Register GOPAD 14 6 14 8 Output Port B Data Register 0 14 6 14 9 Test Control Register 14 7 14 10 External Interrupt Control Register 14 8 15 1 Interrupt Mode 15 3 152 Interrupt Pending 15 4 15 3 Interrupt Mask 9 8 15 5 16 1 LF Motor Control Register sioan a aia 16 2 16 2 LF Motor Phase Control 16 3 16 3 EF Motor Timer REGISTER cocina teet E aa 16 4 16 4 LEGON REGISTE E 16 5 17 1 Carrier Motor Control 17 3 17 2 Basic Timer Base 17 4 17 3 Pre step Timer Base 17 4 17 4 CR State Control Register 17 5 17 5 CRSREG Re
84. format little endian format In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 n little endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte is the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 4 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER Byte swapping in word The byte swap is done by using following simple C code It changes the byte sequence in a word Unsigned int swap unsigned int data Make the sequence of bytes reverse in a word return 0 000000 amp data gt gt 24 0x00ff0000 amp data gt gt 8 Ox0000ff00 amp data lt lt 8 data lt lt 24 ROM writing BTU changes the sequence the byte in a word program codes are byte swapped To write the program to ROM do steps as follows 1 Compile the program by big endian mode 2 Byte swap the compiled code 3 Writes the code to ROM Little endian format code vs Byte swapped big endian format code if character strings doesn t exist in programs little endian format codes may be same as byte swapped big endian format codes But because the bytes in a string is not affected by
85. generates a I O read and write signals for the corresponding address area Fig 4 20 shows the diagram of special I O read write interface logic Address Bus Generation The address bus of KS32C65100 is some different from general MCUs When 8 bit data bus is selected the resolution of address bus is a byte When 16bit data bus is selected the resolution of address bus is a half word So although general MCUs don t use AO pins at 16bit data bus width KS32C65100 always uses 0 pins regardless of bus width Data Bus Width External Address Pins ADDR 21 0 A21 A0 internal 4M byte A22 A1 internal 4M half word Data Bus Width Configuration 8 bit 16 bit 22 bit A 21 0 External Address Pins ADDR 21 0 System Address Bus Y A 22 1 Figure 4 9 External Address Bus Generation ADDR 21 0 4 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER Address Figure 4 12 SRAM Write Timing ELECTRONICS 4 13 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR DRAM CONTROL REGISTERS 532 65100 DRAM interface has two banks of DRAM and each bank is able to control DRAM access timing as memory configurations The DRAM interface has two DRAM control registers DRAMCONO 1 and one DRAM refresh control register REFCON The initial addresses of each DRAM control registers are 0100101ch and 01001020h The refresh control register address is 01001024h The register address is re configurable and programmers can change the
86. in printing and the position of the sub pixel to be chopped is specified by PCON 17 10 Among the eight bits of PCON 17 10 the positions of zeros determines the positions of the sub pixels to be chopped For example PCON 6 4 is specified as 111 i e the is equal to 8 then each bit of video data one pixel dot corresponds to 8 sub pixels in printing If PCON 17 10 is specified as 10110010 the 1st 3rd 4th and 7th sub pixel for each pixel will be chopped in printing 25 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER 19 18 Image expanding ratio This 2 bit value determines the image expanding ratio When PCON 19 18 is not 00 the image to be sent to the printer engine is expanded first according to the defined ratio and then sent to the engine 20 HSYNC selection Selects the HSYNC signal to the used between HSYNC1 and HSYNC2 21 Test mode normal mode If 1 outputs the test pattern mode by the TPVAL register and TPON register ELECTRONICS 25 9 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T H V 054 0 Video Data Polarity 0 Invert the video data to be sent to print engine 1 Do not invert video data 1 Border Data Polarity 0 Invert border data 1 Do not invert border data 3 2 Video Clock Selection 00 Use MCLK a
87. mapped into the physical memory banks SC CONPHA 102 O1 Scan motor control Bi phase GOPA 19 SC CONPHB 105 O1 Scan motor control Bi phase GOPA 20 SC CUR S 0 103 104 O1 Scan motor bi current uni phase 106 107 PWMO 2 0 118 120 PWM out signal GOPA 13 11 VDO2 GOPA 9 121 Video out from PIFC VDO1 GOPA 14 Video out from LSU control LSU CLK Clock for LSU motor O1 AE Kd p VDI GIP 13 o 26 nHSYNC2 GIP 12 28 CIS LED signals Top reference voltage for general ADC Analog inputs for general ADC RTC VDD VCLK GIP 14 129 nEXTWAIT GIP 7 123 202 RTCXOUT SLED 2 0 196 198 GOPA 18 16 201 121 125 126 128 03 GAIN 2 0 206 208 ELECTRONICS 1 9 PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR Table 1 1 Pin Description Continued 3 3V internal power Externally connected to the 3 3V regulator 5V I O power Externally connected to the VCC board plane System ground Externally connected to the ground board plane Signal Pinno 3VDD 5VDD 48 67 89 141 195 VSS 11 25 39 58 76 101 108 124 150 172 181 TE de PICAlO w o m j 4 4 4 0 Master clock output 1 PHBTU50T4 50K 4mA TTL level with pull up resistor and Tri State output 2 PHBLU50T4SM 50K 4mA TTL schmitt trigger level input with pull up resistor and Tri State output with medium slew rate PHOB4SM
88. modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SP RO RS R14 BL somewhere LDMED SP RO R3 R15 3 42 Save to to use as workspace and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory manager is warned to treat them as inseparable This class of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swa
89. opcode will contain 123 as the Word8 value ELECTRONICS 3 79 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 12 LOAD ADDRESS 15 14 1 7 0 1 3 12 11 10 8 7 0 8 bit unsigned Constant 10 8 Destination Register 11 Source 0 1 SP Figure 3 41 Format 12 OPERATION These instructions calculate an address by adding an 10 bit constant to either the PC or the SP and load the resulting address into a register The THUMB assembler syntax is shown in the following table Table 3 19 Load Address SP THUMB Assembler ARM Equivalent Action ADD Rd PC ADD Rd R15 lmm Add to the current value of the program counter PC and load the result into Rd 1 ADD Rd SP ADD Rd R13 lmm Add to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by lmm is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places gt gt 2 in field Word 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to O The CPSR condition codes are unaffected by these instructions 3 80 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as show
90. register set is a subset of the ARM state set The programmer has direct access to eight general registers RO R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked Stack Pointers Link Registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State General Registers and Program Counter Supervisor THUMB State Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR fiq m SPSH SPSR abt SPSR irq SPSHR und banked register Figure 2 4 Register Organization in THUMB State ELECTRONICS 2 5 PROGRAMMER S MODEL KS32C65100 RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way e THUMB state RO R7 and ARM state RO R7 are identical e THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical e THUMB state SP maps onto ARM state R13 e THUMB state LR maps onto ARM state R14 e The THUMB state program counter maps onto the ARM state program counter R15 This relationship is shown in Figure 2 5 THUNB State ARM State o 2 2 T Hi registers Stack Pointer SP Link Register LR Program Counter PC Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PROGRAMMER S MODEL
91. register to its shifter it activates 11 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART the transmit buffer register empty status signal which will cause the transmit interrupt if the transmit mode in control register is selected as interrupt mode The receive buffer full and transmit buffer register empty status signals can also be connected to generate the DMA request signals if the receive transmit mode in control register is selected as DMA mode As mentioned before two DMA channels GDMA and CDMA are provided in KS32C65100 However each SIO can only be connected with a fixed DMA channel In other words the UARTO can only generate the GDMA request the can only generate the CDMA request and UART2 can not generate any DMA request Baud Rate Generation Each UART s baud rate generator provides the serial clock for transmitter and receiver The source clock for the baud rate generator is KS32C65100 s internal system clock MCLK The baud rate clock is generated by dividing the source clock by 16 and a 16 bit divisor specified by UART baud rate divisor register UBRDIVn UBRDIVn can be determined as follows UBRDIVn int source clock bps x 16 1 where the divisor should be a value from 1 to 2 16 1 For example if the baud rate is 56000bps and MCLK is 33Mhz use internal system clock UBRDIVn is calculated as follows UBRDIVn Data Transmission The data frame for transmissions is programm
92. shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the prefetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction Branches beyond 32Mbytes must use an offset or absolute destination which has been previously loaded into a register In this case the PC should be manually saved in R14 if a branch with link type operation is required THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and R14 1 0 are always cleared To return from a routine called by Branch with Link use MOV PC R14 if the link register is still valid LDM Rn PC if the link register has been saved onto a stack pointed to by Rn INSTRUCTION CYCLE TIMES Branch and branch with Link instructions take 2S 1N incremental cycles where S are defined as sequential S cycle and internal I cycle 3 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Items in are optional Items in must be present B L cond expression L Used to request the branch with link form of the instruction If absent R14 will not b
93. the force build button to build the application Click the Debug button to start the ARM Windows Debugger Click the YES button when you see the message box Are you sure that you want to start in remote debugging 6 After code downloading is completed type in the following command in the command window ob a XexampleWVCEdbg armsd in 7 Then you can run and debug the application using any functions provided by the Debugger 26 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR EVALUATION BOARD SWITCH AND JUMPERS DESCRIPTION Table 29 1 Jumper Description Suus JP1 5Vpp Main power and chip power 5 3 3V are separated JP2 3Vpp e Main power and chip power 5V 3 3V are connected JP3 SIO TXD SERIAL2 and TXD1 are connected SERIAL2 and TXD2 are connected JP5 SIO RXD SERIAL2 and RXD1 are connected SERIAL2 and RXD2 are connected JP17 CLOCK de MCLK and Crystal are connected cL MCLK and Oscillator are connected JP6 JP7 GOPA5 GOPA7 10 and LED LD2 LD5 8 are separated JP8 JP9 GOPA5 GOPA7 10 and LED LD2 LD5 8 are connected JP10 JP14 GIP3 7 and SWITCH 51 4 57 are separated GIP3 7 SWITCH 814 87 are connected JP19 JP20 Select EPROM 27512 on ROM sockets U13 amp U14 Select Flash memory 29EE512 on ROM sockets U13 amp U14 NOTE The grayed rows are the default settings of the evaluation board Table 29 2 Switch Descript
94. the address will be incremented by one word for each subsequent transfer ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system USE OF R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried INSTRUCTION CYCLE TIMES Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where n The number of words transferred B The number of cycles spent in the coprocessor busy wait loop 5 and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively 3 50 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC Load from memory to coprocessor STC Store from coprocessor to memory L When present perform long transfer N 1 otherwis
95. the operating system Abort mode abt Entered after a data or instruction prefetch abort e System sys A privileged user mode for the operating system Undefined und Entered when an undefined instruction is executed Mode changes may be made under software control or may be brought about by external interrupts or exception processing Most application programs will execute in user mode The non user modes known as privileged modes are entered in order to service interrupts or exceptions or to access protected resources REGISTERS has a total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode dictate which registers are available to the programmer The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non user modes mode specific banked registers are switched in Figure 2 3 shows which registers are available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers RO to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register used to store status information ELECTRONICS 2 3 PROGRAMMER S MODEL Register 14 Register 15 31 2 Regist
96. the registers specified by Rlist Update the stack pointer 1 1 Rlist PC LDMIA R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer ELECTRONICS 3 83 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 21 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine 3 84 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 1 12 11 10 8 7 0 Register List 10 8 Base Register 11 Load Store Bit 0 Store to memory 1 2 Load from memory Figure 3 44 Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 3 22 The Multiple Load Store Instructions STMIA Rb Rlist STMIA Rb Rlist Store the registers specified by Rlist starting at the ba
97. them are able to have different configuration Users can program the SRAM access cycles memory bank size and bank location by using two identical SRAM control registers SRAMCONO 1 SRAM control register has two 9 bits address pointers base and Next pointer These two pointers which denote the start and end address of SRAM bank These 9 bits are mapped to the address 24 16 Therefore bank address offset value is 64K byte 16 bits The next pointer contents should be SRAM bank end address 1 Initially Two SRAM banks start and end addresses are 00000000h Therefore SRAM banks are disabled after system initialization because the next pointer and base pointer have same values Initialization When system has been initialized two SRAM Control register initial values are 00000000h and it specifies the external SRAM is disabled Special I O Address The extra bank 3 of KS32C65100 has two special I O areas for making out the simple external latch control signal Two SRAM control registers have dedicated 9 bits for those special I O areas in the extra bank 3 Extra bank provides two special control signals nIOWRO When a user reads writes data from to external latch devices these signals doesn t need additional address decoding logic These signals are only available at the extra bank 3 When MCU accesses any of special I O address area 64kB 16 bit offset address specified by SRAM control registers extra bank interface logic
98. to 0 To control this bit only use the address 0x8810 By using 0xc810 the other values in the control register will not be affected 1 BUSY status When CDMA starts this read only status bit is automatically set 1 When it is 0 CDMA is in an idle status 3 2 CDMA mode selection Four sources can initiate a CDMA operation software an external CDMA request the parallel port and the UART block The CDMA mode selection bits determine which source can initiate a CDMA operation at any given time see Figure 9 8 4 Destination adr direction This bit determines whether the destination address will be decreased or increased during a CDMA operation 15 Source adr direction This bit determines whether the source address will be decreased or increased during a CDMA operation 6 Destination adr fix This bit determines whether the destination address will change or not during a CDMA operation This feature is used when transferring data from multiple sources to a single destination 7 Source adr fix This bit determines whether the source address will change or not during a CDMA operation This feature is used when transferring data from a single source to multiple destinations 8 Stop interrupt enable CDMA operation is started stopped by setting clearing the run enable disable bit This bit is set to 1 when operation starts stop interrupt is generated when CDMA operation stops If this bi
99. to 01 at the specified line which represents that only set 0 is valid When subsequent cache fills occurs CS will be 11 at the specified line which represents that contents of both set 0 and set 1 are valid When the contents of the two sets are valid and when it needs content replacement due to cache miss CS is changed to 10 at the specified line which represents that the content of set 0 was replaced When CS is 10 and when it needs another replacement due to cache miss the content of set 1 will be replaced by changing CS as 11 Summarizing at normal steady state CS will be changed from 11 10 to 10 11 which gives the information for the implementation of the 2 bit pseudo LRU Least Recently Used replacement policy NVALID 00 Not valid data Read miss 30 only 01 Set 0 valid set 1 invalid hit It doesn t change status on hit Read miss rmiss rmiss or hit1 AV 810 All valid and set 1 is dirty AV S1D 11 AV SOD 10 Dirty means to access just before Status does change on hit rmiss or hitO 4 se AV_SOD All valid and set 0 is dirty Figure 5 2 CS bit Status Diagram ELECTRONICS 5 3 CACHE CONTROLLER KS32C65100 RISC MICROPROCESSOR Cache Disable Operation The KS32C65100 Cache provides a programmable entire cache enable disable mode The cache can be enabled by setting the CE bit in SYSCFG to 1 and disabled by clearing SYSCFG 1 When the disable mode is specified instruc
100. to 511 MCLKs If you write a new value to the nACK width field near the end of a data transfer operation the new pulse width value does not take effect until the next cycle takes place Figure 10 6 Parallel Port ACK Width Register ELECTRONICS 10 9 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR PARALLEL PORT CONTROL REGISTER The parallel port control register PPCON is used to configure the operations such as handshaking digital filtering operating mode data bus output abort operations and DMA PPCON 15 13 are read only PPCON 0x800c Parallel port control register 0x0000 0 Software reset Setting the software reset bit causes the PPIC s handshaking control and compression decompression logic to immediately terminate the current operation and return to software Idle state When is set to 1 the run length decompression status bit PPCON 13 and the full status bit PPCON 14 are automatically cleared to 0 1 Digital filter enable Setting this bit enables digital filtering on all four host control signal inputs nSELECTIN nSTROBE nAUTOFD and nINIT 3 2 Mode selection This two bit value selects the current operating mode of the parallel port interface see Figure 14 4 Software mode disables all hardware handshaking so that handshaking can be performed by software Compatibility mode Compatibility mode hardware handshaking can be enabled during a forward data transfer You c
101. whether little endian format or big endian format the two codes are not same So the big endian format code byte swapped has to be used in KS32C65100 if little endian format code is used the strings are not displayed correctly byte swapped strings may be displayed Interfacing external peripherals Peripherals address is also byte swapped For example If users want to access address Oh in memory address 3h in MCU must be accessed This is because of word swapping of BTU The relation between physical address and the address used by instructions is as follows Table 4 1 The Relations Between Physical Address and Address in Instructions Physical Address Byte Wide Access Half Word Wide Access Address Used in Instructions Address Used in Instructions _ E Lo Ub 1 ELECTRONICS 4 9 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR Address Figure 4 7 Page Mode ROM Access Timing 4 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER SRAM CONTROL REGISTERS KS32C65100 SRAM interface has two banks of SRAM and each bank is able to set up own SRAM access configuration The SRAM Control Registers SRAMCONO SRAMCON 1 in SMR specifies not only the features for SRAM banks but also two Special I Os 1 00 1 in the external bank The initial addresses of SRAM control registers are 01001004h and 01001008h each The real address of each SRAM control register is S YSCFG address
102. you set the LFT with a value greater than four Figure 25 10 Left Margin Register LFT PIXEL COUNT REGISTER The value stored in the pixel count register PXL determines the total number of pixels per scan line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Pixel Count Value This 16 bits field contains the count value for the number of pixels per scan line NOTE image expanding operation the pixel count value contained in PXL should be set as the pixel number per scan line of original image rather than that of the expanded image Figure 25 11 Pixel Count Register PXL 25 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER QUEUE 0 1 START ADDRESS REGISTERS The values written to the two queue start address registers and QSAR1 respectively define the starting byte address for queues 0 and 1 QSARO queue 0 start address register 0x0000000 0xa024 PDMA queue 1 start address register 0x0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Queue Start Address 27 0 Queue Start Address for PDMA Operation This 28 bits field contains the start byte address for the respective DMA queue DMA queue 0 or DMA queue 1 NOTE Since performs 32 bit word data transfers the queue start addresses should be aligned to word 4 bytes
103. 0 Src Size i Frac Frac Dst_Size while Frac gt Src Size Frac Frac Src Size DstReg Dst Pixel IDx SrcReg Src Pixel IDx Dst Pixel IDx Src Pixel IDx Figure 26 1 VIS Algorithm Description 26 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR VARIABLE IMAGE SCALING EXAMPLE OF VIS OPERATION To carry out the VIS operation S W should run the following steps Set the control register FUNCON1 as zero to select the VIS operation Set the size registers SrcSize and DstSize to specify the scaling ratio Write source image data to source data register SrcReg Check the read request bit in status register VISSR 0 and read the scaled image data from destination data register DstReg once the read request bit is one repeat this step until all scaled data are read out If more data is to be processed check the write request bit in status register VISSR 1 and repeat steps 2 4 once the write request bit is one Inside the VIS unit hardware performs the image data replication automatically after obtaining the source image data from SrcReg according to the algorithm described above and outputs the scaled image data to DstReg Figure 26 2 shows some examples for VIS s internal image data replication process Example 1 SrcSize 4 8 bit SrcReg DstSize 5 Scaling ratio 5 4 16 bit DstReg LSB Example 2 SrcSize 4 8 bit SrcReg DstSize 6 Scaling ratio 6 4 16 bit
104. 0 AND Error C C 255 ELSE OUT Black 1 AND Error C This method is advantageous from the aspect of H W but if a certain brightness is maintained on the algorithm an optically displeasing stripe may be generated on the screen To compensate for this problem you can swing the outline values a little Local Adaptive Threshold This method is for binarization in text mode You don t need to use an edge emphasis algorithm when using this method and you can expect the ABC effect You need to select the values for the entire area as shown below Tmax decides if the pixels will have absolute white value Tmin decides if the pixels will have absolute black value Tdiff decides if the pixels have edge components ELECTRONICS 21 15 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR The algorithm using the above values is as follows MIN MAX Decision Decide MIN MAX gray value of 2x3 matrix Calculate the average of min max value AVE MIN 2 Edge Pixel Decision Pixel which is larger than Tdiff is edge pixel EXIT Hn Case of Edge Pixel Edge pixel which is larger than AVE is white EXIT Else is black EXIT Case of Non Edge Point Pixel which is larger than Tmin is white EXIT Else is black EXIT ADC CONTROL The ADC signal is for operating the internal ADC and the signal must always maintain a 5096 period For A D conversion of the analog signal you need a register that adjus
105. 0 GIOP mode 1 PHOE output mode Figure 14 1 Bi directional Port Mode Register GIOPMOD INPUT PORT MODE REGISTER GIPMOD 0x2804 Input port mode register 0x00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GIP 17 0 17 0 General In GIP Mode 0 Control signal 1 Intput mode Figure 14 2 Input Port Mode Register GIPMOD ELECTRONICS 14 3 PORT KS32C65100 RISC MICROPROCESSOR OUTPUT A PORT MODE REGISTER GOPAMOD 0x2808 Output port mode register 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ed ff et fff fff fa GOPA 29 0 29 0 General Output GOPA Mode 0 Control signal 1 Output mode Figure 14 3 Output Port Mode Register GOPAMOD OUTPUT B PORT MODE REGISTER GOPBMOD 0x280C Output port mode register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GOPB 12 0 12 0 General Output GOPB Mode 0 Control signal 1 Ouptut mode Figure 14 4 Output Port Mode Register GOPBMOD 14 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PORTS PORT DATA REGISTER The I O port data register GIOPD contains one bit values for I O ports that are configured to input mode and one bit write value for ports that are in output mode GIOPD 0x2810 Bi directional port data register 0x0000000 31 30 29 28 27
106. 0 parallel port is currently busy SELECT 156 O1 Parallel port select The SELECT output signal indicates whether the device connected to the KS32C65100 parallel port is on line or off line PERROR 157 O1 Parallel port paper error PERROR output indicates that a problem exists with the paper in the ink jet printer It could indicate that the printer has a paper jam or that the printer is out of paper nFAULT 155 O1 Not fault The nFAULT output indicates that an error condition exists with the printer This signal can be used to indicate that the printer is out of ink or to inform the user that the printer is not turned on PPD 7 0 142 149 2 Parallel port data bus This 8 bit tri state bus is used to exchange data between the KS32C65100 and an external host peripheral SAVRT 2 Top reference voltage for IP ADC SAIN ie Analog input for IP ADC SAVRB 4 Bottom reference voltage for IP ADC 1 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 Pin Description Continued Signal cissi _ Oo ICA Oo o 1686 motor control signalt O O o o o Oo o PinNo Sc 6 CIS SI 0 ADDR 21 0 Address bus The 22bit address bus ADDR 21 0 covers the full 4M half words address range of each ROM SRAM DRAM and external I O bank Not row address strobe for DRAM The KS32C65100 supports up to tw
107. 02 01 00 142 7 0 Test Pattern Duration Determines the test pattern duration Figure 25 19 Test Pattern Duration TPVAL 25 20 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER Test Pattern Width TPON 0xa044 Test pattern width register 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 142 7 0 Test Pattern Width Determines the test pattern width Decides how much width to print black in the duration decided by TPVAL Figure 25 20 Test Pattern Width TPON ELECTRONICS 25 21 KS32C65100 RISC MICROPROCESSOR VARIABLE IMAGE SCALING VARIABLE IMAGE SCALING OVERVIEW The VIS unit can support the variable ratio image scaling operation In other words the factor of image expansion can be in either integer or fraction For example it supports image scaling with ratios 3 2 5 4 2 13 5 and so on To implement this operation five registers are involved in this unit out of in which two size registers SrcSize and DstSize specify the scanline sizes of the source image and destination image two data registers SrcReg and DstReg are used to contain the scanline data of the input source image and the scaled scanline data of the output destination image and one status register VISSR indicates the operation status during VIS running The image scaling ratio can be determined by comparing the values in two data size registers For example if
108. 024 Encoder cycle value register 0x000000 UNTTIM 0x6028 Intervalcounterobservationregister 0000 UNTVAL 0x602c Intemuptintervalvalue register 0x0000 Fire Position control 0x6830 R W Position interrupt register FETOR Ox7008 R_ Fire enable timer observation register 0 00 FWTOR 0000 R_ Fire window timer observation register 0 000 FSDTOOR 0x7018 Fire delay strobe timer 0 observation 0x000 register FSDT1OR 0 701 Fire delay strobe timer 1 observation 0x000 register FSDT2OR 0x7020 R W delay strobe timer 2 observation 0x000 register FSDTSOR 0x7024 Fire delay strobe timer 3 observation 0x000 register 1 16 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 KS32C65100 Special Function Registers Continued Register Description Reset Value PHPTR 0x7028 R W Pre heat pulse timer register 0x00 PHPTOR 0x702c Pre heat pulse timer observation register 0x00 PHDTR 0x703 R W Pre heat delay timer register 0x00 2 PWM PRSC 0xe004 PWM 00 0xe010 0 014 0xe018 oxe01c RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 R W Print head data word 11 register 0x0000 R W Print head data word 12 register 0x0000 RW 000000000 RW 000000000 R W Dot counter yellow register 0x00000000 Dot counter control observation r
109. 1 100 0 0 33 0 a 66 0 1 0 KA 100 33 33 1 1 66 66 1 100 33 0 33 33 100 100 0 33 3396 33 100 0 33 3396 0 100 0 0 3396 33 100 0 33 33 100 100 0 33 3396 NN 100 33 0 33 33 100 0 0 33 0 1 66 3396 ELECTRONICS 17 7 CR CONTROL KS32C65100 RISC MICROPROCESSOR CR PWM TIMER Logic Configuration The PWM block is configured of the Cycle Time base register On Time base register counter observation register and 16 bit down counter Function The PWM output signal s period and the On Off time within it is decided by the Cycle Time base value and the On Time base value If the On Time base value is the same or larger than the Cycle Time base value the PWM output signal maintains On status The 16 bit down counter s RUN enable or STOP disable status is decided by the CMCR 6 The PWM block operation and the output according to CMCR s bits 4 5 and 7 are shown in the following table CMCR DC motor control signal output status CMCR A4 DC motor output enable Enables the PWM outputs CMCR T PWM mode selection CMCR 5 DC motor direction output selection x x DC CRIAO Pin PWM signal 0 PWM signal Counter Base Register and Observation Register Pwwoss PWM counter observation regser 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 PWM Cycle On Time Base Val
110. 1 00 3 0 Data State This indicates the printhead data state machine value 6 4 Fire State This indicates the printhead fire state machine value 10 7 HDMA State This indicates printhead HDMA state machine value 14 11 Dither Count 18 15 Number of Current Printhead Data from HDMA 22 19 Front Back end Delay Counter Value 27 23 Sum of the Number of Output Enable Signals Figure 19 7 PrintHead Observation Register 19 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR FRONT AND BACK END DELAY COUNTER REGISTER This 4 bit timer is used for the front back end delay duration counter value TDCR 0x703c Td delay counter register PRINT HEAD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ELECTRONICS 3 0 Counter 1 Value This data specifies the amount in the back end delay counter 7 4 Counter 2 Value This data specifies the amount in the front end delay counter Figure 19 8 Td Delay Counter Register 19 7 PRINT HEAD KS32C65100 RISC MICROPROCESSOR PRINT HEAD DATA WORD REGISTER PHDWOR 0x7040 Print head data word 0 register 0x0000 PHDW1R 0x7044 R Print head data word 1 register 0x0000 PHDW2R 0x7048 Print head data word 2 register 0x0000 PHDW3R 0x704c R PHDW4R 0x7050 R R R R RW RW RW RW RW Prntheaddataword4register 0x0000 PHDWSR 004 RW RW RW Pw RW RW 0 0000 PHDWER PHDW7R PHDW
111. 1 Branch if N clear positive or zero 0110 Branch if V set overflow 0111 Branch if V clear no overflow 1000 Branch if C set and Z clear unsigned higher 1001 Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Branch if N set and V set or N clear and V clear greater or equal 1011 BLT label BLT label Branch if N set and V clear or N clear and V set less than 1100 label BGT label Branch if Z clear and either N set and V set or N clear and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two 5 complement address this must always be halfword aligned i e with bit 0 set to 0 since the assembler actually places label gt gt 1 in field SOffset8 3 86 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 23 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples 45 Branch to over if RO 45 BGT over Note that the THUMB opcode will contain the number of halfwords to offset over Must be halfword aligned ELECTRONICS 3 87 ARM INSTRUCTION SET
112. 2 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 WRITING TO R15 When Rd is a register other than R15 the condition code flags in the CPSR may be updated from the ALU flags as described above When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state change which atomically restore both PC and CPSR This form of instruction should not be used in User mode USING R15 AS AN OPERAND If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TST AND CMN OPCODES NOTE TEQ TST CMP and CMN do not write the result of their operation but do set flags in the CPSR An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic The TEQP form of the TEQ instruction used in earlier ARM processors must not be used the PSR trans
113. 20 32 C65100 0599 USER S MANUAL KS32C65100 32 Bit RISC Microprocessor Revision 0 ELECTRONICS KS32C65100 32 BIT RISC MICROPROCESSORS USER S MANUAL Revision 0 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages KS32C65100 RISC Microprocessors User s Manual Revision O Publication Number 20 32 C65100 0599 1999 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters inclu
114. 208 QFP Top View O 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 x TESTO vss C 5 OPs C CJ 9 CJ GIOP10 CLKOUT GOPAe osci osco vDD nWDTO GOPA4 L vss C TONEOUT GOPA3 PHA LF_PH1 GOPA22 PHB IB1 nRESET L PLL FILTER C GAVSS 204 GAVRT 205 GAIN2 206 207 208 BUSY nACK C nlOWR GOPA10 CL TEST1 TESTA 5VDD CJ SLEDO GOPA16 RTCXIN 202 PERROR CJ PHA IA0 PHB Gi RTCXOUT 203 VDD 201 nlORD GOPA9 TXD2 GOPA2 RXD2 GIP2 TXD1 GOPA1 RXD1 GIP1 TXDO GOPA0 nXDREQ GIPe nXDACK GOPA5 200 LF 21 SLED2 GOPA18 SLED1 GOPA17 aaas 924019 9130 924019 813 vZdOIO rL3OHd 02dOI5 0 30Hd 6LdOl5 630Hd SSA 9LdOl9 e30Hd SLdOIO G30Hd aane z8dO9 tvoHdu 8dO9 PvOHdu SS
115. 21 20 19 18 17 16 1514 131211109 8 7 6 5 4 3 2 1 0 15 0 Baud Rate Divisor Value This field contains the baud rate divisor value for the corresponding SIO channel Baud ratecan be calculated as Baud rate source clock divisor 16 Figure 11 10 UART Baud Rate Divisor Register UBRDIVO 1 2 NOTE THE BAUD RATE DIVISOR SHOULD BE A VALUE FROM 1 TO 2 16 1 11 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART TIMING DIAGRAMS TRANSMITTER Data Bits 5 8 WR THR INT TXD RECEIVER Data Bits 5 8 Ws Start Data Bits Previous Receive Data Valid Receive Data Figure 11 11 Interrupt Based Serial I O Timing Diagram Tx and Rx ELECTRONICS 11 15 KS32C65100 RISC MICROPROCESSOR TONE GENERATOR TONE GENERATOR OVERVIEW The KS32C65100 Tone Generator provides a programmable tone signal which has 50 duty cycle and can be used to make a key click sound The tone Generator block has a tone counter which includes 8 bit programmable divider and a 1 2 divider for making the 5096 duty cycle and a Tone Data register TONDATA which has the tone enable or disable bit and tone count data bits The 8 bit programmable divider receives MCLK prescaler 1 128 clock signals and divides it depending on the count value in TONDATA 7 0 bits Also you can set the prescaler value Initial value OxC in TSTCON Figure 14 9 Enable Disable Clock TONDATAJ8 Divider 8 Bit Programable 1 2 Divider 8 Bit Prescaler 1 12
116. 25 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR Memory Register LDR from word aligned address LDR from word address offset by 2 Figure 3 15 Little Endian Offset Addressing Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register A shift operation is then required to move and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 A word store STR should generate a word aligned address The word present
117. 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GIOP 26 0 26 0 General In Out GIOP Data Figure 14 5 Bi directional Port Data Register GIOPD INPUT PORT DATA REGISTER GIPD 0x2814 Input port data register OxXXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GIP 17 0 17 0 General Input Data Figure 14 6 Input Port Data Register GIPD ELECTRONICS 14 5 O PORT KS32C65100 RISC MICROPROCESSOR OUTPUT A PORT DATA REGISTER GOPAD 0x2818 Output port data register 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 beet dete fff ef fff GOPA 29 0 29 0 General Output GOPA Data Figure 14 7 Output Port A Data Register GOPAD OUTPUT B PORT DATA REGISTER GOPBD 0x281C Output port data register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GOPB 12 0 12 0 General Output GOPB Data Figure 14 8 Output Port B Data Register GOPBD 14 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PORTS TEST CONTROL REGISTER The test control register TSTCON contains the 16 bits for testing the functions of CHORUS These bits for testing are only used during fabrication These bits are not specified in this manual The other bits which you can use are as follows CKOUT mode The C
118. 3 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 af a xf xf xf xf 0 External nFAULT Output Control Bit 0 nFAULT output low printer fault 1 2 nFAULT output high no printer fault 1 SELECT Output Control Bit 0 SELECT output low no response from printer 1 SELECT output high response received from printer 2 PERROR Output Control Bit 0 PERROR output low no paper error 1 PERROR output high paper error 3 BUSY Output Control Bit 0 BUSY output low not busy 1 BUSY output high busy 4 nACK Output Control Bit 0 nACK output low do not acknowledge handshake 1 nACK output high acknowledge handshake 5 BUSY Output Level This read only bit reflects the logic level on the external BUSY output After a system reset this bit is 1 6 nACK Output Level This read only bit reflects the logic level on the external nACK output After a system reset this bit is 1 7 nSLCTIN Input Level This read only bit reflects the logic level on the nSLCTIN input after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is 1 8 nSTROBE Input Level This read only bit reflects the logic level on the nSTROBE input after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is 17 9 nAUTOFD Input Level This read only bit reflects the logic level on the nAUTOFD input after synchronization and optional digit
119. 33 aM 1 33 66 ABz 0 100 100 33 33 1 1 66 66 ABz 0 1 100 33 33 33 aM 1 66 33 CW A Bz 0 1 1 100 0 33 0 a A B 1 66 0 AB 0 1 100 33 33 33 aM 1 66 33 G oi Ola O oi Ola oci Ola Ola 5 16 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR CONTROL CR CONTROL OVERVIEW This module is configured as follows Basic Timer using MCLK clock is 16 bit down counter Prestep timer using 19200 9600 PPI Pulse Per Inch clock is 10 bit down counter Phase and current control signal generation for step motor of bi polar type Filter for photo sensor input position counting strobe and direction generation for DC motor Encoder cycle counter of 20 bit up counter and latch with MCLK clock to calculate the cycle of photo sensor input in DC motor mode Interrupt interval counter of 16 bit up counter and latch with MCLK 32 clock to calculate the interval of carrier interrupt in DC motor mode This module performs the following functions in step motor mode Basic timer generates the basic pulse of 19200 9600 PPI to control the state and position of carrier step motor and to generate fire strobe to control the printhead Prestep timer is used to generate carrier step pulse to control the change of output state signals which are phase and current control signals for carrier motor driver and carrier step interrupt according to carrier motor step rate State c
120. 4 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Run Enable RE 0 Disable operation 1 Enalbe DMA operation 1 Busy Status Read Only BS 0 DMA idle 1 DMA active 3 2 Mode Selection MODE 00 Software 01 Reserved 10 Parallel port 11 Reserved 4 Destination Address Direction DD 00 Increase address 1 Decrease address 5 Source AddressDirection SD 0 Increase address 1 Decrease address 6 Destination Address Fix DF 0 Increase decrease destination address 1 Do not change destination address fix 7 Source Address Fix SF 0 Increase decrease source address 1 Do not change source address 8 Stop Interrupt Enables SI 0 Do not generate stop interrupt when DMA stops 1 Generate stop interrupt when DMA stops 9 Reset RS 0 Normal operation 1 Initialize control register 10 Transfer Direction for Parallel UART Only TD 0 IP to memory 1 Momory to IP 13 12 Transfer Width TW 00 Byte 8 bit 01 Halfword 16 bit 10 Word 32 bit 11 Not used 14 Continuous Mode CN 0 Normal operation 1 Hold system bus until the whole DMA operation stops 15 Demand Mode DM 0 Normal mode 1 Demand mode Figure 9 5 GDMA Control Register ELECTRONICS 9 7 DMA KS32C65100 RISC MICROPROCESSOR GDMA SOURCE DESTINATION ADDRESS REGISTER These registers contain the 25 bit source destination address for a DMA channel Depending on the setting of the DM
121. 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 fl fx RR RRN fff fff 30 0 Interrupt Mode Bit Each of the 31bits in the interrupt mode register INTMOD corresponds to an interrupt source When the source s interrupt mode bit is set to 1 the interrupt is processed by the ARM7TDMI core FIQ fast interrupt mode Otherwise it is processed in IRQ mode normal interrupt The 30 interrupt sourcess are summarized in Table 15 1 Figure 15 1 Interrupt Mode Register ELECTRONICS 15 3 INTERRUPT CONTROLLER KS32C65100 RISC MICROPROCESSOR Interrupt Pending Register The interrupt pending register INTPND contains interrupt pending bits for each interrupt source The INTPND has nothing to do with INTMSK Although INTMSK forbids an Interrupt request generated INTPND operates properly independent of INTMSK INTPND 0x2004 Interrupt pending register 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 fff fff fo 30 0 Interrupt Pending Bit Each of the 31bits in the interrupt pending register INTPND corresponds to an interrupt source When on interrupt request is generated it will be set by 1 The interrupt service routine must then clear the pending condition by writing 1 to the appropriate pending bit Only the bit written with 1 toggles from 1 0 The 30 interrupt sources are summarized in Table 15 1
122. 5 are defined as sequential S cycle and non sequencial N cycle respectively ASSEMBLER SYNTAX BX branch and exchange Items in are optional Items in must be present BX cond Rn cond Two character condition mnemonic See Table 3 2 Rn is an expression evaluating to a valid register number USING R15 AS AN OPERAND If R15 is used as an operand the behaviour is undefined 3 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR Examples ADR Into THUMB 1 BX RO CODE16 Into_THUMB ADR R5 Back ARM BX R5 ALIGN CODE32 Back to ARM ELECTRONICS ARM INSTRUCTION SET Generate branch target address and set bit 0 high hence arrive in THUMB state Branch and change to THUMB state Assemble subsequent code as THUNB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state Branch and change back to ARM state Word align Assemble subsequent code as ARM instructions 3 5 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instruction encoding is shown in Figure 3 3 below 31 28 27 25 24 23 0 24 Link Bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instructions contain a signed 2 s complement 24 bit offset This is
123. 7TDMI 1 Overwrites R14 svc and SPSR svc by copying the current values of the PC and CPSR into them value of the saved PC and SPSR is not defined 2 Forces M 4 0 to 10011 supervisor mode sets the and F bits in the CPSR and clears the CPSR s T bit 3 Forces the PC to fetch the next instruction from address 0x00 4 Execution resumes in ARM state 2 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core FORMAT SUMMARY The ARM instruction set formats are shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 1 0 cond owes oem pae ponsen Fs tay cos an Am Mutiny toro m aaa snep oo h p p EE anen and exchange re sja Am An re Sing cata ans Lem I D i s F U SIW E Broek oeta venster cms 9 gum cone 11111101 cP Ope om oma
124. 8 Divider p 5095 duty 1 1 Prescale value Reload TONDATA t Tone data Figure 12 1 Tone Generator Block Diagram The TONDATAQ 8 bit enables or disables the Tone generator operation When it is cleared to 0 the tone output is disabled stopped and the programmable divider is automatically cleared while the tone data register TONDATA retains its contents The initial value of the tone enable bit is O The input clock to the tone generator is MCLK prescaler 1 128 The division ratio of the tone counter is determined by the tone data register value and ranges from 0 to 255 A user has to load data into the tone data register TONDATA before enabling the tone generator to get the correct tone signal To make out the 50 duty cycle tone signal KS32C65100 tone generator has 1 2 divider with a programmable divider The output of the programmable divider is divided by the 1 2 divider The frequency of the tone is calculated as follows MCLK Prescaler 1 128 ToneData 2 ELECTRONICS 12 1 TONE GENERATOR KS32C65100 RISC MICROPROCESSOR Table 12 1 Tone Generator Data Value Setting MCLK 33 MHz Prescale OxC 4 958 kHz 99 159 Hz 3 305 kHz 255 38 886 Hz TONE GENERATOR DATA REGISTER TONDATA The tone generator data register TONDATA stores an 8 bit value which determines the frequency of the tone generator output The value in the TONDATA register determines the division ratio of the programmab
125. A vadOO SVOHaU 0 09 18dO9 8vOHdu 68dO9 0LvoHdu 0L8dOS LVOHdu LiBdOS zLvOHdu 8dOS L VOHdu 8vdO9 zsoau 18030 SSA SdlO z1NI3u dI5 01NI3u IS 810 80 SSAVS SUAVS NIVS lHAVS Figure 1 2 Pin Assignment 1 5 ELECTRONICS PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR PIN DESCRIPTION Table 1 1 Pin Description Semi Descripion nRESET 182 l4 Not reset nRESET is the global reset input for the KS32C65100 For a system reset nRESET must be held to low level for at least 65 machine cycles nSLCTIN GIP 16 152 11 Not select information This input signal is used by parallel port interface to request on line status information nSTROBE 151 11 Not strobe The nSTROBE input indicates when valid data is on parallel port data bus PPD 7 0 nAUTOFD GIP 17 154 l1 Not auto feed The nAUTOFD input indicates whether data on the parallel port data bus PPD 7 0 is an auto feed command Otherwise the bus signals are interpreted as data only nINIT GIP 15 153 l1 Not initialization The nINIT input signal initializes the parallel port s input control nACK 159 11 Not parallel port acknowledge The nACK output signal is issued whenever a transfer on the parallel port data bus is completed BUSY 158 O1 Parallel port busy The BUSY output signal indicates that the KS32C6510
126. A control register DMACON 1 these addresses will increase decrease or remain the same DMASRC 1 0x9004 GDMA source address register OxXXXXXXX DMADST1 0x9008 GDMA destination address register OxXXXXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMASRC1 DMADST1 EE Source Destination Address 24 0 Source Destination Address Figure 9 6 GDMA Source Destination Address Register GDMA TRANSFER COUNT REGISTER This register contains a 24 bit value which is the number of completed DMA transfers This value is decreased by 1 when one DMA operation is completed regardless of the width of the data that was transferred 0x900c GDMA transfer count register OxXXXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMACNT1 Number of Transfers 23 0 Number of Transfers Figure 9 7 GDMA Transfer Count Register 9 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR DMA CDMA CONTROL REGISTER CDMA C DMA is 2nd CDMA can transfer the data by byte swap mode can transfer data only through CDMA CDMA Compress Decompress DMA Control Register DMACONO 8800 control register 0x00000 CDMA Control Register Descriptions Note denotes a read only bit 0 Run enable disable CDMA operation starts When you set this bit 1 To stop CDMA you must clear this bit
127. A direction The PDMACON 5 control bit determines whether the bit map in a PDMA operation is printed from top to bottom down printing or from bottom to top up printing ELECTRONICS 25 11 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR 25 12 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Blank Mode for Queue 0 0 Normal access to external page memory 1 Blank mode send zeros as video data without memory access 1 Blank Mode for PDMA Queue 1 0 Normal access to external page memory 1 Blank mode send zeros as video data without memory access 2 PDMA Queue 0 Enable 0 Disable queue 0 clear automatically when queue 0 operation completed 1 Enable queue 0 start queue 0 operation 3 PDMA Queue 1 Enable 0 Disable queue 1 clear automatically when queue 1 operation completed 1 Enable queue 1 start queue 1 operation 4 Queued Operation Enable 0 Queued operation disable 1 Queued operation enable 5 Direction of PDMA Operation 0 Print page bitmap from bottom to top 1 Print page bitmap from top to bottom Figure 25 7 Printer DMA Control Register PDMACON ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER TOP MARGIN REGISTER The value written to the top margin register TOP controls the number of
128. AMCONO DRAMCON 1 EXTCONO EXTCON1 EXTCON2 Special I O 1 Start address SYSCFG 12 4 1FFh Next pointer 004h Base pointer 000h Next pointer 184h Base pointer 180h Next pointer 000h Base pointer 000h Next pointer 160h Base pointer 120h Next pointer 000h Base pointer 000h Next pointer 000h Base pointer 000h Next pointer OA1h Base pointer Next pointer 100h Base pointer OBOh Next pointer 000h Base pointer 000h Start address SRAMCON 1 000h 32MB Memory Space 1FFFFFFh 183FFFFh 1800000h 15FFFFFh SFR SRAMO 1200000h OAOFFFFh 0A00000h OAFFFFFh BANK1 BANK2 OFFFFFFh OO3FFFFh 0000000h 2 Figure 4 24 Example of System Manager Register Settings ELECTRONICS KS32C65100 RISC MICROPROCESSOR CACHE CONTROLLER CACHE CONTROLLER OVERVIEW The KS32C65100 CPU has an internal 2K Bytes of unified instruction data cache The cache is two way set associative and the line size is four words 16 Bytes It has a write through policy When a miss occurs words of memory are sequentially fetched from external memory It has a LRU Least Recently Used replacing algorithm Typically the RISC CPU uses instruction and data caches to improve performance Without caches the bottleneck that occurs during the instruction and data fetches from external memory may seriou
129. AR are matched the match pend status bit is set If you would like ELECTRONICS 20 1 HDMA 7 Match interrupt 8 HDMA Interrupt enable 9 Auto Load 10 Alternate Enable 11 Current queuing 16 Queuing 0 enable 24 Queuing 1 enable 20 2 KS32C65100 RISC MICROPROCESSOR to clear the status bit write zero This bit determines whether the interrupt pending by match of source match pending enable address register occurs or not In the case of a match HDMA operates until the source address is the match address An HDMA operation is started stopped by setting clearing the run enable disable bit If this bit is set to 1 when DMA starts a stop interrupt is generated when HDMA operation stops If this bit is 0 an interrupt and match interrupt are not generated This bit should be enabled for source address register s parallel load This bit determines to alternate register banks This bit indicates whether the current queuing bank is 0 or 1 You can bank selection set clear the queuing bit selection If this bit is set and HDCON 10 is set HDMA alternates bank 0 If this bit is set and HDCON 10 is set HDMA alternates bank 1 ELECTRONICS KS32C65100 RISC MICROPROCESSOR HDMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Run Enable 0 Disable HDMA operation 1 Enable HDMA operation 1 Busy Status 0 HDMA idle 1 HDMA a
130. ART status register USTATn is read This bit is automatically set to 1 whenever a frame error occurs during a serial data receive operation If the receive status interrupt enable bit UCONn 2 is 1 a receive status interrupt will be generated if a frame error occurs The frame error bit is automatically cleared to 0 whenever the UART status register USTATn is read This bit is automatically set to 1 to indicate that a break signal has been received If the receive status interrupt enable bit UCONn 2 is 1 a receive status interrupt will be generated if a break occurs The break interrupt bit is automatically cleared to 0 when you read the UART status register This bit is automatically set to 1 whenever the receive data buffer register RBR contains valid data received over the serial port The receive data can then be read from the RBR When this bit is 0 the RBR does not contain valid data Depending on the current setting of the UART receive mode bits UCONn 1 0 an interrupt or a DMA request is generated when this bit is 1 This bit is automatically set to 1 when the transmit buffer register TBR does not contain valid data In this case the TBR can be written with the data to be transmitted When this bit is 0 the TBR contains valid Tx data that has not yet been copied to the transmit shift register In this case the TBR cannot be written with new Tx data Depending on the current setting of the UAR
131. ASIC timer base register and PRESTEP timer base register values and Reset the position block enable bit before setting to reduce the error in carrier motor position To reduce location errors you should fix the position amp fire control register s bit 6 position counter clock to 1 adjust the position and fire Pre Scaler values and set the fire DPI e The value of position amp fire control register s bit 6 should not be changed during system operation ELECTRONICS 17 11 KS32C65100 RISC MICROPROCESSOR CR FIRE CR FIRE OVERVIEW This module performs the following functions Count and control the position of carrier motor e Fire strobe and start signal generation 16 bit counter for the position of carrier motor e 16 bit print slice counter for counting fire strobe e 6 bit prescaler for the clock of carrier position 8 bit prescaler for the clock of fire strobe NOTES 1 This block is responsible for positioning the printhead and regulating the printhead fire strobe timing 2 Two conditions must be met before the fire strobe logic can be activated First the print slice count must be greater than zero Second the position counter must be equal to the print start position 3 When the start position is reached the fire logic is enabled and the first fire strobe is generated Each fire strobe decrease the slice count by one When the slice count reaches to zero the fire logic is disabled 4 For step mot
132. All instructions in this format have an equivalent ARM instruction as shown in Table 3 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R3 R2 R6 Store word in R3 at the address formed by adding R6 R2 LDRB R2 RO R7 Load into R2 the byte found at the address formed by adding R7 RO ELECTRONICS 3 73 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALFWORD 2 0 Destination Register 5 3 Base Register 8 6 Offset Register 10 Sign Extended Flag 0 Operand not sign extended 1 sign extended 11 H Flag Figure 3 37 Format 8 OPERATION These instructions load optionally sign extended bytes or halfwords and store halfwords The THUMB assembler syntax is shown below Table 3 15 Summary of Format 8 Instructions S H THUMB Assembler ARMEquivalent Action STRH Rd Rb Ro STRH Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rd Rb Ro LDRH Rd Rb Ro Load halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 LDSB Rd Rb Ro LDRSB Rd Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rd Rb Ro LDRSH Rd Rb
133. B7 nPHGA7 GOPB6 nPHGA6 GOPB5 nPHGA5 GOPB4 VSS nPHGA4 GOPB3 nPHGA3 GOPB2 nPHGA2 GOPB1 nPHGA1 GOPBO 3VDD PHOET GIOP11 PHOE2 GIOP12 PHOES GIOP13 PHOE4 GIOP14 PHOES GIOP15 PHOE6 GIOP16 PHOE7 GIOP17 PHOE8 GIOP18 VSS PHOES GIOP19 PHOE10 GIOP20 PHOE11 GIOP21 PHOE12 GIOP22 PHOE13 GIOP23 PHOE14 GIOP24 PHOE15 GIOP25 PHOE16 GIOP26 5VDD nRCSO nRCS1 GOPA7 nRCS2 nRASO OLY OLY IX ada IVdO9 LOX L 2dIb cQXd VdOD LNO_ANOL vVdOO 1nO K532C65100 Ouuad 2 SELECT nFAULT nAUTOFD GIP17 nINIT GIP15 nSLCTIN GIP16 nSTROBE VS LZYdO9 0Hd 41 6vdob5 quoiu OLVdO9 HMOIU 3 nEXWAIT GIP7 nVCLK GIP14 nVDI GIP13 nHSYNC2 GIP12 nLREADY GIP11 nHSYNC1 GIP10 VS LSU_CLK GOPA15 nVDD1 GOPA14 nVDD2 GOPA29 PWMO2 GOPA13 PWMO1 GOPA12 PWMOO GOPA1 1 DC_SIN1 GIP9 DC_SINO GIP8 3VDD CRIB1 GOPA28 CR PHB GOPA24 CRIBO GOPA27 CRIA1 GOPA26 CR PHB GOPA23 CRIAO GOPA25 VSS 2 o pe GOPA20 OS D gt E m 2 I UOU oT OI B I2 5 e e JO I I
134. BR PHDW9R 0x0000 0x0000 0x0000 0x0000 Print head data word 3 register 0x0000 PHDW10R 0x7068 Print head data word 10 register 0x0000 PHDW11R 0x706c Print head data word 11 register 0x0000 PHDW12R 07070 R W head data word 12 register 0x0000 AN R W AN R W AN R W AN R W AN R W AN R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Printhead Data Word Figure 19 9 Print Head Data Word Register 19 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINT HEAD DOT COUNTER REGISTER R W DCCR 0700 R W Dotcountercyanregister 0x00000000 DCMR 0x7080 000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Dot Counter Value 31 0 Dot Counter Value This data specifies the amount in the counter of black for mono head and yellow cyan and megenta for color head Figure 19 10 Dot Counter Register DOT COUNTER CONTROL OBSERVATION REGISTER DCCOR 0x7084 Dot counter control observation register 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Sm Yee 2 0 Yellow Dots This data specifies the amout of yellow dots per fire pulse 5 3 Cyan Dots This data specifies the amout of cyan dots per fire pulse 8 6 Magenta Dots This data specifies the amout of magenta dots per fire pulse Figure 19 11
135. BUSY high level 6 PPD 7 0 Output Enable 0 Disable PPD 7 0 output 1 Enable PPD 7 0 output 7 Abort Bit 0 Normal operation 1 Disable data bus output and tri state PPD 7 0 drivers 8 DMA Selection 0 DMA 1 CDMA codec DMA 9 Request Mode 0 Generate interrupt request for data transfer 1 Send DMA request to DMA CDMA for data transfer 10 Flush Data 0 No operation 1 Remaining data to be transmitted to PPIC 12 Zero Insert Reverse ECP with RLE 0 When run length is 0 only data to be transmitted 1 When run length is 0 nCMD and data are transmitted 13 Decompress Status 0 Finished 1 Decompression is operating 14 Data Latch Status 0 No data 1 Data is latched if this bit is read automatically cleared 15 Data Empty Reverse ECP Mode 0 Data is processed 1 PPDATA buffer is empty it is automatically cleared when write operation occurs Figure10 7 Parallel Port Control Register 10 13 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERRUPT EVENT REGISTERS PPINTEN PPINTPND The two parallel port interrupt event registers PPINTEN and PPINTPND control interrupt related events for the input signal originating from the host as well as data reception command reception and invalid events Enable register PPINTEN contains the interrupt enable bits for each interrupt event that is indicated by the PPINTPND status bits If its PPINT
136. CESSOR LEAP YEAR GENERATOR This generator calculates if the last date of each month is 28 29 30 or 31 based on data from BCDDAY BCDMON and BCDYEAR It also considers leap years in deciding the last date An 8 bit counter can just represent 2 BCD digits so it cannot decide whether 00 year is a leap year or not We know year 2000 is a leap year therefore the leap year generator is hard wired to work up to 2 29 00 SYSTEM POWER OPERATION 5V It is required to set bit 0 of the RTCCON register for interfacing between CPU RTC logic 1 second error can occur when the CPU reads or writes data into BCD counters and this can cause the change of the higher time units When the CPU reads writes data to from the BCD counters another time unit may be changed if BCDSEC register is overflowed To avoid this problem the CPU should reset the BCDSEC register to 00 reading sequence of the BCD counters is BCDYEAR BCDMON BCDDATE BCDDAY BCDHOUR BCDMIN and BCDSEC It is required to read it again from BCDYEAR to BCDSEC if BCDSEC is zero BACKUP BATTERY OPERATION The RTC logic is driven by a backup battery if the system power is off The interfaces of the CPU and RTC logic are blocked and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation 22 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR REAL TIME CLOCK REAL TIME CLOCK REGISTERS RTCCON REGISTER The RTCCON register is co
137. CONTROL REGISTERS The KS32C65100 Cache provides two non cacheable areas It has four Cache Control registers to specify two non cacheable areas Basically cache stores any data within the whole system memory area but sometimes it needs non cacheable operation to keep the data consistency between the external memory and cache memory KS32C65100 provides two non cacheable areas and each of them requires two cache control registers to indicate the start and stop address of the non cacheable area If a non cacheable area is specified that area won t be cached while read miss occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 24 9 Non Cacheable Start End Address This 16 bit address becomes the upper address of the area 24 9 minimum non cacheable area is 512 byte because offset address is 9 bit 1ffffffh Cacheable Area CACHNAEO Non Cacheable Area 0 CACHNABO CACHNAE1 Non Cacheable Area 1 minimum 512 bytes CACHNAB1 Cacheable Area Memory Map Figure 5 4 Non Cacheable Area Register ELECTRONICS 5 5 KS32C65100 RISC MICROPROCESSOR DERASTERIZER DERASTERIZER OVERVIEW The KS65100 derasterizer provides the 16 x 16 bit image data rotation feature The derasterizer consists of 16 registers which has a 16 bit data width This 16 x 16 bits of register array is used to rotate raster image data 90 or 270 degrees DRASTO 0x4800 R W 16 bits of derasterizer data reg
138. Clock signal for LSU Motor MCLK ESUCK value 1 x2 24 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR LSU CONTROL SPECIAL REGISTER LSU CON CONTROL REGISTER LSUCON 0 000 LSU control register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 fx af x xf 0 VDO SW On Off Control 0 Disable 1 Enable 1 Enable VDI from PIFC 0 Disable 1 Enable 2 RUN Video Window amp Idpon Counter 0 Stop 1 Run 3 LD Pre_ON Function Enable 0 Disable 1 Enable 4 VDO Polarity Control 0 Same level as VDI 1 Inverted level of VDI 5 LSU_CLK Output Enable 0 Disable 1 Enable 6 Page Sync Control 0 Negate nPsync lt 1 1 Active nPsync lt 0 7 Load nHSYNC Filter Clock Value 0 Disable 1 Enable 9 8 nHSYNC Filter Clock Value Filter clock MCLK value 1 10 External VDI Enable 0 Disable 1 Enable 11 Internal nLREADY Status Check and Clear Read 0 Negate 1 Active Write 0 No clear 1 Clear 12 nLREADY Port Status Read Only 13 Not Used 15 14 nHSYNC Filter Counter Observation Read Only Figure 24 2 LSU_CON Control Register ELECTRONICS 24 3 LSU CONTROL KS32C65100 RISC MICROPROCESSOR V WINDOW START END TIME REGISTER VWIN STR 0xd004 V Window time start register 0x00000 VWIN_END 0xd008 V Window time end register 0x00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18
139. D ROTATES 14 WRITING TORI eiue Soto detto fefe Soo fefe Soto iue Soto eta Soto fuf Soto Sot et 14 USING R15 AS AN 14 TST CMP AND OPCODES 14 INSTRUC MON CYCLE lIMES neret eet teet tet eet tete teet eue tete e ree e ret v Ue eu e a 14 ASSEMBEER SYNTAX defe etu dv fu tatu lean 15 PSR TRANSFER MRS i e eee 16 OPERAND RESTRICTIONS odore caius 16 RESERVED A E 18 INSTRUC HON GY CLE TIMES e iat en ti esos ete 18 ASSEMBLER SYNTAX rete eee dives siete vd betes ce ee 19 MULTIPLY AND MULTIPLY ACCUMULATE MUL 20 CPSR 21 3 96 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES 0 0 enn eee enn 0 21 ASSEMBLER SYNTAX qu 21 MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL eee 22 OPERAND RESTRICTIONS 22 CRSA FIA O 23 INSTRUCTION CYCLE 5 23 ASSEMBLER SYNTAX iecore a a rrr
140. Dot Counter Control Observation Register ELECTRONICS 19 9 PRINT HEAD KS32C65100 RISC MICROPROCESSOR Caution e print head logic is responsible for receiving image data conditioning the data for print and routing the data to the print head in the proper sequence The nature of the print head design is the primary motivation behind the structure of the print head firing logic The print head contains 208 nozzles arranged in two columns that are divided into sixteen groups containing 13 nozzles each The print head is configured so that only one nozzle from each group may be fired at any time This necessitates a sequential firing scheme passing through each of the 13 nozzle group one at a time firing a maximum of sixteen nozzles e Many of the critical timing relationships for the print head firing are controlled by carrier motor logic It is imperative that print head motion and nozzle firing be directly linked to produce the desired print output characteristics Additional software control is provided to aid print alignment e Data for the print head logic is received from memory via the HDMA pair or directly from the KS32C65100 During a print fire cycle the logic will issue a data request for 7 byte 3 4 12 or 13 half words of data transferred per print slice 19 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR HDMA HDMA OVERVIEW This module is used to transfer head data from memory to the head data register by DMA
141. DstReg LSB Example 3 8 bit SrcReg SrcSize 4 DstSize 8 16 bit DstReg Scaling ratio 8 4 2 Figure 26 2 Examples of VISs Internal Operation ELECTRONICS 26 3 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR HALFTONING The halftoning unit performs the operation to convert the gray level image into a bi value halftone image To support the PCL6 0 protocol the input gray level image in which the pixel s gray level is 8 bit scaled and each pixel corresponds 8 bit scale data should be converted to halftone image suitable to be printed For halftone image the image gray level is represented by the density of the black pixels i e each pixel in this kind of image only corresponds one bit and may represent as white zero or black one only In this unit the conversion from gray level image to halftone image is implemented by hardware based on a comparison algorithm To generate the halftone image each pixel data 8 bit of the gray level image is compared with an 8 bit reference data i e the threshold value and a one bit halftone image pixel value is output according to the comparison result To support this operation four registers are provided in this unit in which three 16 bit data register Refln and HftReg are used to contain the source image gray level image pixels data reference data threshold values and the halftone data and a control register VISCON is used to initialize enable the half
142. ECTRONICS KS32C65100 RISC MICROPROCESSOR EVALUATION BOARD EMBEDDEDICE UNIT INSTALLATION EMBEDDEDICE UNIT The Embedded ICE Unit can also be connected with the KS32C65100 evaluation board as a debugging system for software applications development Embedded ICE is a JTAG based non intrusive debugging system for ARM based controllers or processors Embedded ICE provides the interface between a debugger and the ARM based controller development board To use the Embedded ICE the following additional equipment are required e Embedded ICE Interface Unit e 14 way ribbon cable 9 pin RS232 cable e 25 parallel cable optional e 7 9 V at 500mA DC power supply CONNECTING KS32C65100 EVALUATION BOARD AND PC The Embedded ICE Unit should be connected to the KS32C65100 evaluation board s JTAG Port CN1 via a 14 way cable and to the host PC via a 9 pin RS232 serial cable A parallel cable can optionally be connected between the 25 pin parallel port connector on the Embedded ICE interface and the printer port on the host PC Using the parallel cable can speed up the code download To power on the Embedded ICE interface 7 9 V DC power supply is required The system connection with Embedded ICE is shown in Figure 29 3 ELECTRONICS 26 5 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR POWERING UP THE BOARD AND EMBEDDEDICE We recommend that you power on the evaluation board before the Embedded ICE is powered on In this wa
143. ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 6 PC RELATIVE LOAD 15 14 13 10 8 7 0 12 11 7 0 Immediate Value 10 8 Destination Register Figure 3 35 Format 6 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The THUMB assembler syntax is shown below Table 3 13 Summary of PC Relative Load Instruction THUMB Assembler Equivalent Acton O LDR Rd PC lmm LDR Rd R15 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by lmm is a full 10 bit address but must always be word aligned i e with bits 1 0 set to 0 since the assembler places gt gt 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value ELECTRONICS 3 71 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR F
144. EN enable bit is 1 the corresponding event causes the KS32C65100 CPU to generate an interrupt request Otherwise no interrupt request is issued PPINTEN 0x8010 Parallel port enable interrupt event register 0x000 PPINTPND 0x8014 Parallel port interrupt pending register 0x000 0 nSLCTIN Low to High The bit of PPINTPND is set when a Low to High transition on nSLCTIN is detected If the corresponding enable bit is set the PPINTEN register an interrupt request is generated 1 nSLCTIN High to Low The bit of PPINTPND is set when a High to Low transition on nSLCTIN is detected If the corresponding enable bit is set in the PPINTEN register an interrupt request is generated 2 nSTROBE Low to High The bit of PPINTPND is set when a Low to High transition on nSTROBE is detected If the corresponding enable bit is set in the PPINTEN register an interrupt request is generated 3 nSTROBE High to Low The bit of PPINTPND is set when a High to Low transition on nSTROBE is detected If the corresponding enable bit is set in the PPINTEN register an interrupt request is generated 4 nAUTOFD Low to High The bit of PPINTPND is set when a Low to High transition on nAUTOFD is detected If the corresponding enable bit is set in the PPINTEN register an interrupt request is generated 5 nAUTOFD High to Low The bit of PPINTPND is set when a High to Low transition on nAUTOFD is detected If the corresponding enable bit is set in the PPI
145. ET KS32C65100 RISC MICROPROCESSOR SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 0 15 12 Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write Back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 25 Immediate Offset Offset is an immediate value 11 0 Offset 11 0 Immediate offset 11 0 Unsigned 12 bit immedite offset 11 4 3 0 3 0 Offset register 11 4 shift applied to Rm 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 24 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO INDEXING The offset from the base may be e
146. GIStCR 17 6 17 5 PWM Counter Base 17 8 17 6 Encoder Cycle 17 9 17 7 Interrupt Interval Value 17 10 18 1 Position Fire Control 18 2 18 2 GR Gount REGISTER ER i E E RR Ud uud 18 3 XX 517 80064 80013 80013 MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 19 1 Print Head Control 19 2 19 2 Fire Enable Timer Observation 19 3 19 3 Fire Window Timer Observation 19 3 19 4 Fire Strobe Delay Timer Observation 19 4 19 5 Pre Heat Pulse Timer Observation 19 5 19 6 Pre Heat Delay Timer Observation 19 5 19 7 PrintHead Observation 19 6 19 8 Td Delay Counter 19 7 19 9 Print Head Data Word nennen nnn 19 8 19 10 Dot Counter 19 9 19 11 Dot Counter Control Observation 19 9 20 1 Control
147. IC to control hardware handshaking 5 BUSY status This read only bit reflects the logic level on the external BUSY output pin After a system reset PPSTAT 3 is 1 which results in PPSTAT 5 being 1 So for compatibility mode operation you must clear the PPSTAT S3 by software beforehand so as to enable the hardware handshaking 6 nACK status This read only bit reflects the inverted logic level on the external nACK output pin After a system reset PPSTAT 6 is 1 7 nSLCTIN status This read only bit reflects the level read on the nSLCTIN input pin after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is set 10 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE 8 nSTROBE status This read only bit reflects the level read on the nSTROBE input pin after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is set 9 nAUTOFD status This read only bit reflects the level read on the nAUTOFD input pin after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is set 10 nINIT status This read only bit reflects the level read on the input pin after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is set ELECTRONICS 10 7 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR 31 30 29 28 27 26 25 24 2
148. ICROPROCESSOR vii Table of Contents Continued Chapter 3 Instruction Set Continued Undefined INStruction ARR 3 54 Instruction Cycle 3 54 Assembler Syntax ot oa aaa 3 54 Instruction Set Examples 3 55 Using The Conditional 5 3 55 Pseudo Random Binary Sequence 1 3 57 Multiplication by Constant Using The Barrel 3 57 Loading A Word From An Unknown 3 59 Thumb Instruction Set 3 60 Format SUmlmaryx 53 de ud ada dades 3 60 OP code SUMMALY x i ead ad ud ad adus 3 61 Format 1 Move Shifted Register 3 63 Format 1 Move Shifted Register 3 63 Format 2 Add Subtfract 5 cdd dea add dee 3 64 Format 3 Move Compare Add Subtract Immediate 3 65 Format 4 ALU Operations 3 66 Format 5 Hi Register Operations Branch 3 68 Format 6 PC Relative 0 3 71 Format 7 Load Store With Register 3 72 Format 8 Load Store Sign Extended 3 74 Format 9 Load Store With Immediate 3 76
149. KOUT mode bit determines whether CKOUT output is divided by 2 or not 0 1 MCLK 2 Prescaler value 0 Timer2 watchdog timer tone generator and line feed motor timer use this prescaler value to divide MCLK e Bidirectional control pin 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Chip Test Mode 1 Fire Test Mode 2 Out CLK Mode 3 Phfire Test Mode 4 Test FSTB Mode 5 Clock Output Mode 0 MCLK 12 MCLK 2 6 HOE Direction 14 7 Prescaler Value 6 1 15 IP Test Output Mode 1 GPIO 10 0 IP test out 16 IP Test Input Mode 1 GIOP 10 0 IP test in Figure 14 9 Test Control Register TSTCON ELECTRONICS 14 7 PORT KS32C65100 RISC MICROPROCESSOR EXTERNAL INTERRUPT CONTROL REGISTER The external interrupt control register INTCON is used for external interrupt signal filter mode control INTCON 0x2824 External interrupt control register 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 INTCON 8 0 2 0 EXT INTO Control Mode 5 3 EXT INTO Control Mode 8 6 EXT INTO Control Mode 000 Low level sensitive mode 001 High level sensitive mode 01X Falling edge trigger mode 11X Rising edge trigger mode Figure 14 10 External Interrupt Control Register INTCON TEST PIN SETTING Normal LF Scan Mtr output
150. M next pointer and base pointer values are same then ROM bank will be disabled Initialization When system has been initialized the initial value of ROM control register is 80003002h and it specifies that the external bus width is 16 bit half word normal ROM mode is enabled and the longest page mode access cycles are selected ELECTRONICS 4 7 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR MCU Core Physical Memory Compiled Code ROM Writing Figure 4 5 The Byte Swap Operation of BTU and the Positions of Data in Memory ROM Programming Big endian supporting core and little endian supporting physical memory KS32C65100 core and the internal peripherals support Big endian configuration while external memories like ROM SRAM and DRAM can have Little endian configuration Instead of having Big endian physical memory configuration there is BTU Byte twist unit in KS32C65100 internally The main role of BTU is to swap the bytes in word as shown in Fig 4 5 In other word when core access 11 byte it can get the 00 byte from physical memory To put the Big endian data in Little endian memory Compiled code with the option of Big endian has to put in memory by swapping byte in a word as shown in Fig 4 5 due to the double swapping BTU and compiled code swapping KS32C65100 can support Big endian mode without any problem The reason why we have double swapping is due to internal H W implementation issue endian
151. MA request for UCON1 Not used for UCON2 11 Not used 6 Send Break 0 Do not send break 1 Send break 7 Loopback Enable 0 Normal operationg mode 1 Enable loopback mode for testing only Figure 11 6 UART Control Register UCONO 1 2 UART Status Register There are two identical UART status registers USTATO 1 in the UART block for each SIO channel The USTAT is a read only register that is used to monitor the status of SIO USTATO 0xb008 UART ch 0 status register USTAT 1 Oxb808 UART ch 1 status register USTAT 2 0xc008 UART ch 2 status register 0 Overrun error This bit is automatically set to 1 whenever an overrun error occurs during a serial data receive operation If the receive status interrupt enable bit UCONn 2 is 1 a receive status interrupt will be generated if an overrun error occurs This bit is automatically cleared to 0 whenever the UART status register USTATn is read ELECTRONICS 11 9 UART 1 2 3 5 6 7 11 10 Parity error Frame error Break interrupt Receive data ready Tx buffer register empty Transmitter empty KS32C65100 RISC MICROPROCESSOR This bit is automatically set to 1 whenever a parity error occurs during a serial data receive operation If the receive status interrupt enable bit UCONn 2 is 1 a receive status interrupt will be generated if a parity error occurs This bit is automatically cleared to 0 whenever the U
152. MB assembler syntax is shown in Table 3 10 NOTE All instructions in this group set the CPSR condition codes Table 3 10 Summary of Format 3 Instructions 00 MOV Ra Offset8 MOVS Offset8 Move 8 bit immediate value into Rd CMP Rd Offset8 CMP Rd Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Rad Offset8 ADDS Rd Rd Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rad Offset8 SUBS Rad Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples MOV RO 128 RO 128 and set condition codes CMP R2 62 Set condition codes on R2 62 ADD R1 255 255 and set condition codes SUB R6 145 R6 145 and set condition codes ELECTRONICS 3 65 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 4 ALU OPERATIONS 15 14 13 12 11 10 9 6 5 3 2 0 2 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 3 33 Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair NOTE All instructions in this group set the CPSR condition codes Table 3 11 Summary of Format 4 Instructions
153. NTEN register an interrupt request is generated 6 nINIT Low to High The bit of PPINTPND is set when a Low to High transition on nINIT is detected If the corresponding enable bit is set in the PPINTEN register an interrupt request is generated 7 nINIT High to Low The bit of PPINTPND is set when a High to Low transition on nINIT is detected If the corresponding enable bit is set in the PPINTEN register an interrupt request is generated 10 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR 8 Data received 9 Command received 10 Invalid transition 11 Transmit data empty ELECTRONICS PARALLEL PORT INTERFACE The bit of PPINTPND is set when data is latched into the PPDATA register s data field This occurs on every High to Low transition nSTROBE when the parallel port data bus enable bit PPCON 6 is 0 An interrupt is also generated if ECP with RLE mode is enabled and if a data decompression is in progress The bit of PPINTPND is set when a command byte is latched into the PPDATA register data field If ECP without RLE mode is enabled a command received interrupt is issued whenever a run length or channel address is received If ECP with RLE mode is enabled a command received interrupt is issued only when a channel address is received This event can be posted only when ECP mode is enabled The corresponding enable bit in the PPINTEN register determines whether an interrupt request will be generated wh
154. ORMAT 7 LOAD STORE WITH REGISTER OFFSET 15 14 13 12 11 10 09 8 6 5 3 2 0 IS ee 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quanity 11 Load Store Flag 0 Store to memory 1 2 Load from memory Figure 3 36 Format 7 OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 3 14 Table 3 36 Summary of Format 7 Instructions STR Rd Rb Ro STR Rd Rb Ro Pre indexed word store Calculate the target address by adding together the value in Rb and the value in Ro store the contents of Rd at the address STRB Rd Rb Ro STRB Rd Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rd Rb Ro LDR Rd Rb Ro Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into Rd LDRB Rd Rb Ro LDRB Rd Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro load the byte value at the resulting address 3 72 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES
155. Offset address of each SRAM control register The register address is re configurable and programmers can change the SRAM control register address by changing the contents of SYSCFG SRAMCONO 0x1004 SRAM control register 0 0 0000071 SRAMCON1 0x1008 SRAM control register 1 0 0000071 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SRAMCONO 1 Next Pointer 0 Baseoiner 0 Special I O Address 1 0 Bus Width DW 00 Disable bank 01 8 Byte mode 10 16 half word 11 No use 9 2 Special I O Address Seiting Value It denotes the start address of special I O address in extra bank 3 Extra bank has two special I O areas for cost effective solution See extra I O control register bank explanation for more information 13 11 Access Cycles for SRAM Bank Tacc 000 Disable bank 100 5 cycles 001 2 cycles 101 6 cycles 010 cycles 110 7 cycles 011 2 4 cycles 111 2 Not used 22 14 Start Point of SRAM Bank Base Pointer Indicates SRAM bank end address 1 31 23 End Point 1 of SRAM Bank Next Pointer Indicates SRAM bank end address 1 Next point value has to be bigger than base point value if base point and next point value are same SRAM bank is not valid anymore Figure 4 8 SRAM Control Registers ELECTRONICS 4 11 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR SRAM Bank Space 532 65100 SRAM interface provides two SRAM banks each of
156. On rien 23 SINGLE DATA TRANSFER LDR 6 24 OFFSETS AND AUTO INDEXING 25 SHIFTED REGISTER OFFSET 25 BYTES AND WV OPS ia 25 IS EOP Rae P Id IE 27 RESTRICTION ON THE USE OF BASE REGISTER 1 0 0 27 RR 27 INSTRUCTION CYCLE 5 27 ASSEMBLER SYNTAX 28 HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH 30 OFFSETS AND AUTO INDEXING 32 HALFWORD LOAD AND STORES 32 SIGNED BYTE AND HALFWORD 5 32 ENDIANNESS AND BYTE HALFWORD 32 OFRIS ee eae eo ca aces M 33 DATAABORTSZ reed ariete ue e re EE RENE 33 INSTRUCTION CYCLE 33 ASSEMBLER SYNTAX nene trae eran a e ee 34 BLOCK DATA TRANSFER LDM 36 THE REGISTER 36 ADDRESSING 5 07 37 ADDRESS 37 ELECTRONICS 3 97 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR ae re s 39 USE OF R15 AS THE 39 INCLUSION OF THE BASE IN THE REGISTER 1 40 m
157. PC to be 1 word 4 bytes ahead of the current instruction Table 3 25 Summary of Branch Instruction THUMB Assembler Equivalent Acton O B label BAL label halfword Branch PC relative Offset11 lt lt 1 where label is PC offset 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be halfword aligned i e bit 0 set to 0 since the assembler places label gt gt 1 in the Offset11 field Examples here B here Branch onto itself Assembles to OXE7FE Note effect of PC offset B jimmy Branch to jimmy Note that the THUMB opcode will contain the number half word to offset jimmy m Must be halfword aligned ELECTRONICS 3 89 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 19 LONG BRANCH WITH LINK 15 14 1 10 0 1 3 12 11 10 0 Long Branch and Link Offset High low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 3 48 Format 19 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit 0 which must be 0 and creates two THUMB instructions Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is pla
158. R FORMAT 10 LOAD STORE HALFWORD 15 14 13 10 6 5 3 2 0 1 12 11 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 39 Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory Addresses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 3 17 Table 3 17 Halfword Data Transfer Instructions THUMB Assembler ARM Equivalent Acton STRH Rd Rb STRH Rd Rb Add to base address Rb and store bits 0 15 of Rd at the resulting address LDRH Rd Rb LDRH Rd Rb Add lmm to base address Rb Load bits 0 15 from the resulting address into Rd and set bits 16 31 to zero NOTE is a full 6 bit address but must be halfword aligned ie with bit 0 set to 0 since the assembler places lmm gt gt 1 in the Offset5 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 17 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R6 R1 56 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28asthe Offset5 value LDRH R7 4 Load into R4 the halfword found at the address formed by
159. RM7TDMI core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restrictions by 16 bit format is fully notified for using the Thumb instructions FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure 15 14 1312 11109 8 7 6 5 4 3 2 1 0 ojojo Op Rs Rd Moveshftedregisier ep ten Rc odds Se I te EE ALU operations 911191919111 Op T Y esee operations 011 01111 8 0 Ro Rb Load store with register offset 0 1 0 1 H S 1 Ro Rb Rd Load store sign extened byte halfword 0 1 1 B L Offsets Rb Rd Load store with immediate offset 0 O O L Offsets Rb Rd Loadistore hattword Rd Words SP eltvoloan siore Word8 Load address Oo OUO N Rd tolelo o s Add offset to stack pointer Push pop registers NE NN Multiple load store a Conditional branch Software interrupt E Offset11 Unconfitional branch Long branch with link 15 141312 11109 8 7 6 5 4 3 2 Figure 3 29 THUMB Instruction Set Formats 3 60 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET OPCODE SUMMARY The following table summaries the THUMB instruction set For further information about a particular i
160. Register There are two basic timers BTB1R and BTB2R At first the timer starts with the value of BTB1R but after down count stops the timer starts with the value of BTB2R and only BTB2R is written to a new value Otherwise the timer starts with the current base timer value repeat mode BTB1R 0x6004 Basic timer base register 1 OxXXXX BTB2R 0x6008 Basic timer base register 2 OxXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Base Timer 1 2 Count Value Figure 17 2 Basic Timer Base Register Prestep Timer Base Register PSTBR 0x600c R W CR Step INT counter amp prestep 0x000 counter base register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 10 CR Step Interrupt Count Value 9 0 Prestep Count Value Figure 17 3 Pre step Timer Base Register 17 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR CONTROL CR State Control Register This register can generate two phase lines and four current control lines to drive a bipolar stepping motor Eight output combinations are sequentially presented on these six lines CRSCR 0x6010 CR state control register 0x603f 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rx messes 5 0 Phase Status Read Only 0 IBO 1 IB1 2 IAO 4 PHASE B 5 PHASE 6 Write Strobe Write Only a
161. SB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A halfword load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and data bus inputs 31 through to 16 if it is a halfword boundary A 1 21 The supplied address should always be on a halfword boundary If bit O of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit O of the address is HIGH this will cause unpredictable behaviour 3 32 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET Big Endian Configuration A signed byte load LDRSB e
162. SWI vector address is suitably protected by external memory management hardware from modification by the user a fully protected operating system may be constructed RETURN FROM THE SUPERVISOR The PC is saved in R14 svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14 svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and are defined as sequential S cycle and non sequential N cycle ELECTRONICS 3 45 ARM INSTRUCTION SET ASSEMBLER SYNTAX SWI cond expression KS32C65100 RISC MICROPROCESSOR cond Two character condition mnemonic Table 3 2 lt expression gt Evaluated and placed in the comment field which is ignored by ARM7TDMI Examples SWI ReadC Getnext character from read stream SWI Writel k Output a the write stream
163. Source Address 27 0 Source Address Figure 20 2 HDMA Source Address HDMA TRANSFER COUNT REGISTER This register contains the 24 bit current count value of the number of HDMA transfers completed for HDMA This count value is decreased by 1 while one DMA operation is completed regardless of transfer width HDTCR 0x780c HDMA transfer count register 0x000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 23 0 Transfer Count Figure 20 3 HDMA Transfer Count Register 20 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR HDMA HDMA SOURCE MATCH ADR REGISTER These registers contain the 28 bit source destination address for the HDMA channel Depending on the settings you make to the HDMA control register HDCON theses adr will be fixed increased or decreased R W HDMAR1 0 7820 match address register 1 0x0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Source Match Address 27 0 Source Match Address Figure 20 4 HDMA Source Match Address Examples of setting registers to use the match and queuing function of HDMA 1 Case 1 BankO Bank1 Bank1 gt Banko 1 Set HDSARO HDMARO HDSAR1 HDMAR1 HDTCR 2 Set HDCON with 0x1010781 match interrupt pending enable HDMA interrupt enable auto load enable alternate enable select bankO for current queuing bank enable qu
164. Suggestions For Carrier Motor Drive F W KS32C65100 RISC MICROPROCESSOR xi Table of Contents Continued Chapter 18 CRFire 18 1 Special Function sensn 18 2 Position amp Fire Control 18 2 CR Position and Fire Control 18 3 Suggestions For F W Design 18 4 Chapter 19 Print Head eu 19 1 Special Functiori Reglster fcc sais dece de Dresd dec eu Peto etu uus 19 1 Print Head Control 19 1 Fire Enable Timer Observation 19 3 Fire Window Timer Observation Register 19 3 Fire Strobe Delay Timer Observation 19 4 Pre Heat Pulse Timer Observation Register 19 5 Pre Heat Delay Timer Observation 19 5 Printhead Observation 19 6 Front and Back End Delay Counter 19 7 Print Head Data Word Register
165. T internally If nWDTO is connected to nRESET by an external logic the KS32C65100 initialization routine will be executed by the nWDTO signal ELECTRONICS 13 3 KS32C65100 RISC MICROPROCESSOR PORTS PORTS OVERVIEW The KS32C65100 has 18 input 43 output and 27 input output ports PORT SPECIAL REGISTERS Two registers control the I O port configuration IOPMOD and IOP Table 14 1 shows the possible values for the port mode registers The IOP register contains one bit for each port which reflects the signal level at the respective port pin NOTE O port muxed pin configuration Table 14 1 I O Port Mode Configuration and Settings Function fort fumtonfor XDI GIF VOLK MINIT ELECTRONICS 14 1 O PORT KS32C65100 RISC MICROPROCESSOR Table14 1 Port Mode Configuration and Settings Continued SN CON SM PHB SM FHA LFU CONIO LF PHB PHA CR PHI CR PHB CR PHA 14 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PORTS PORT MODE REGISTER The I O port mode register GIOPMOD is used to configure the GIOP general in out port GIOPMOD 0x2800 Bi directional port mode register Oxffff800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GIOP 27 0 26 0 General In Out GIOP Mode 0 Input mode 1 Ouptut mode 27 GIOP PHOE Out Mode
166. T transmit mode bits UCONn 4 3 an interrupt or DMA request will be generated whenever this bit is 1 This bit is automatically set to 1 when the transmit buffer register has no valid data to transmit and the Tx shift register is empty When the transmitter empty bit is 1 it indicates to software that it can now disable the transmitter function block ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211109 87 6 5 4 3 2 1 0 Overrun Error 0 No overrun error during receive 1 Overrun error generate receive status interrupt if UCON 2 is 1 1 Parity Error 0 No parity error during receive 1 Parity error generate receive status interrupt if UCON 2 is 1 2 Frame Error 0 No frame error during receive 1 Frame error generate receive status interrupt if UCON 2 is 1 3 Break Detect 0 No break receive 1 Break received generate receive status interrupt if UCON 2 is 1 5 Receive Data Ready 0 No valid data in the receive buffer register 1 Valid data present in the receive buffer register issue interrupt or DMA request if UCON 1 0 set 6 Transmit Buffer Register Empty 0 Valid data in transmit buffer register 1 No data transmit buffer register issue interrupt or DMA request if UCON 1 0 set 7 Transmitter Empty 0 Transmitter not empty Tx in progress 1 Transmitter empty no data for Tx F
167. TER INTERFACE CONTROLLER Current State Printing Idle Queue 0 is INT_EOP Enabled Here Next Queue is Enabled Here INT_PUR 74 22 ACA Queued Operation Control PDMACR 4 Queued 0 Enable PDMACR 2 Enabled O Enabled 11 Queued 1 Enable El Enabled Enabled Current Queue Auto Reset Figure 25 2 Queued Operation for Page Under run PUR ELECTRONICS 25 3 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR PRINT OPERATION The print job is started by PIFC issuing an active print command signal nPRINT setting VCON 1 to 1 which means that the 532 65100 PIFC is ready to start a print job The PIFC then begins waiting for the nPSYNCRQ from LSU CON After nPSYNCRQ arrives the PIFC activates nPSYNC signal by setting VCON 2 to 1 and in the meantime the top margin counting operation begins The top margin counter is decreased until the count reaches O and then the PIFC begins to transmit video data The nPRINT signal must be held active until becomes inactive By using interrupts the nPSYNC time interval can be controlled As shown in Figure 25 3 the transitions on nPSYNCRQ signal level cause the occurrences of SYNC1 interrupts So the nPSYNC can be activated and inactivated the ISR interrupt service routine of INT SYNC1 Current State Idle Pick up Counting Top Margin Printing nPSYNC INT EVENT nPSYNC Active Top Margin
168. Timing Reverse Digital Filtering KS32C65100 provides the digital filtering function on host control signal inputs nSELECTIN nSTROBE nAUTOFD and nINIT to improve noise immunity and make the PPIC more impervious to inductive switching noise The digital filtering function can be enabled regardless of whether hardware handshaking or software handshaking is enabled If this function is enabled the host control signal can be detected only when its input level keeps stable during two sampling periods Digital filtering can be disabled to avoid signal missing in some specialized applications with the high bandwidth requirement Otherwise it is recommended that digital filtering be enabled 10 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE PPIC SPECIAL REGISTERS PARALLEL PORT DATA REGISTER The parallel port data register PPDATA contains an 8 bit data field PPDATA 7 0 that defines the logic level on the parallel port data pins PPD 7 0 It also contains a status bit PPDATA 8 which is used to indicate when a command byte RLE count or channel address is received during forward data transfers in ECP mode PPDATA 0x8000 Parallel port data register 0x100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 Data for Parallel Port Data Bus PPD 7 0 This is an 8 bit read write field When read this field provides the latched logic leveis on the paralle
169. UCTION CYCLE TIMES 67 FORMAT 5 HI REGISTER OPERATIONS BRANCH 68 68 INSTRUCTION CYCLE 5 69 THE 69 USING R15 AS AN 70 FORMAT 6 PC RELATIVE 71 OPERATIONS oe I a teats 71 INSTRUCTION CYCLE 5 71 FORMAT 7 LOAD STORE WITH REGISTER 72 ore 72 INSTRUCTION CYCLE 5 73 FORMAT 8 LOAD STORE SIGN EXTENDED 74 OPERATION E 74 INSTRUCTION CYCLE 5 75 FORMAT 9 LOAD STORE WITH IMMEDIATE 76 cac A ML LU LA 76 INSTRUCTION CYCLE 5 77 FORMAT 10 LOAD STORE 78 INSTRUCTION CYCLE 5 78 FORMAT 11 SP RELATIVE 5 79 OPERATION cR 79 INSTRUCTION CYCLE 79 FORMAT 12 LOAD ADDRESS 80 OPERATIONS LEAL A AM LM LE 80 INSTRUCTION CYCLE 5 81 FORMAT 13 ADD OFFSET TO STACK 82 OPERATION ws ence III MID IM PAIR 82 INSTRUCTION CYCLE 5 82 3 100 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 14 PUSH POP 5 5
170. XD2 GOPA 2 El External interrupt request input nEINT2 External DMA request channel s output for transmitting serial data channel s output for transmitting serial data generated whenever a DMA transfer is completed 187 TDI nTRST JTAG nTRST interface in MDS mode JTAG TDO interface in MDS mode GIOP 10 0 137 140 1 04 General I O port 173 179 TESTO 169 12 Test 0 pin At normal operation this pin must be connected to GND TEST1 170 12 Test 1 pin At normal operation this pin must be connected to GND TEST2 Test 2 pin At normal operation this pin must be connected to GND External interrupt request input nEINT1 nXDACK GOPA S TONEOUT GOPA 3 Transmit data output for the UARTO TXDO is the UARTO channel s output for transmitting serial data l1 l1 I3 I3 I3 I3 O1 O1 O1 O1 O1 P3 O1 1 1 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 Pin Description Continued nECS 1 0 12 13 O1 Not external chip select Three I O banks are provided for external memory mapped I O operations Each I O bank contains up to 4M half word The nECS signals indicate that an external I O bank is selected nRCS 2 Not ROM SRAM chip select The KS32C65100 can access up to three external ROM SRAM banks nRCS 0 corresponds to RCS 1 PA 7 50 O1 Jos ROM SRAM bank 0 nRCS 1 to bank 1 and nRCS 2 to bank nRCS O0 49 O1 2 By controlling the nRCS signals CPU addresses can be
171. XXXXXXX DMADSTO 0x8808 CDMA destination address register OxXXXXXXX oa 0 880 transfer count register OxXXXXXXX DMACON 1 0x9000 GDMA control register 0x0000 DMASRC1 0x9004 GDMA source address register OxXXXXXXX DMADST1 0x9008 GDMA destination address register OxXXXXXXX DMACNT1 0x900c GDMA transfer count register OxXXXXXXX PPDATA 0x8000 Parallel port data register 0x100 PPSTAT 0x8004 Parallel port status register 0x7e8 PPACKWTH 0x8008 Parallel port acknowledge width register OxXXX arallel por 0x800c Parallel port control register 0x0000 PPINTEN 0x8010 Parallel port enable interrupt event register 0x000 PPINTPND 0x8014 Parallel port interrupt pending register 0x000 HDCON 0x7800 HDMA control register 0x0000000 HDSAR 0x7804 HDMA source address register 0x0000000 HDTCR 0x780c HDMA transfer count register 0x000000 HDSARO 0x7814 HDMA source address register 0 0x0000000 HDMARO 0x7818 HDMA match address register 0 0x0000000 0x781c HDMA source address register 1 0x0000001 HDMAR1 0x7820 HDMA match address register 1 0x0000000 Tone TONDATA 0x3804 R W Tone generator data amp control register OxOff Generator Watchdog WTCON 0x4000 Watch dog timer control register 0x21 Timer WTCNT 0x4004 Watch dog timer count register 0x0003 1 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 KS32C65100 Special Function Registers Continued Group Register
172. a abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The time for this exception entry should be added to worst case FIQ latency calculations INTERRUPT LATENCIES The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchroniser Tsyncmax if asynchronous plus the time for the longest instruction to complete Tldm the longest instruction is an LDM which loads all the registers including the PC plus the time for the data abort entry Texc plus the time for FIQ entry Tfiq At the end of this time ARM7TDMI will be executing the instruction at Ox1C Tsyncmax is 3 processor cycles Tldm is 20 cycles Texc is 3 cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser Tsyncmin plus Tfiq This is 4 processor cycles RESET When the nRESET signal goes LOW ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again ARM
173. able It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits which can be specified in the line control register ULCONn The transmitter can also produce break conditions The break condition forces the serial output to logic 0 state for a duration longer than one frame transmission time On the receiving end a break condition sets an error flag as mentioned above The data transmission process is shown in Figure 11 3 in which the transmitter transfers data through such a path data source transmit buffer register transmit shift register TXDn pin and completes parallel to serial data conversions Two flags status signals transmit buffer register empty and transmitter empty are used to indicate the status of the transmit buffer register and transmitter which includes both the buffer register and transmit shifter Data Reception Like the transmissions the data frame for receptions is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits as the settings in the line control register ULCONn The receiver can detect overrun error parity error frame error and break condition each of which can set an error flag The overrun error indicates that new data has overwritten old data before the old data has been read The parity error indicates the receiver has detected a parity condition other than what it was programmed for The frame error indicate
174. able Interrupt 4 3 Clock Division Factor Selection 00 16 10 64 5 Watch Dog Timer Enable Disable 0 Disable timer 1 Enable timer Figure 13 3 Watchdog Timer Control Register WTCON WATCHDOG TIMER OPERATION Before loading or reading a count value of the Watchdog Timer Count Register WTCNT users have to disable the watchdog timer by setting the WTCON 5 bit to zero When WTCON S bit is set to 1 the watchdog timer is enabled and the counter starts down count The watchdog counter register value is accessible at any time while the watchdog timer is enabled because it provides read and write features The watchdog timer provides general timer interrupt as well as system reset features To enable a timer interrupt WTCON 2 bit has to be set to 1 When a timer interrupt is enabled the interrupt signal generates one pulse of a request signal to CPU to compare it to the long watchdog reset signal The interrupt pending bit bit2 INTPNDR is automatically set to 1 when an underflow occurs When WTCON O bit is 1 the nWDTO pin is enabled and the watchdog reset signal comes through the nWDTO pin If the watchdog counter reaches to zero the nWDTO signal is activated during for 128 MCLK cycles for some reason and WTCON will be 0x0 To avoid the watchdog timer activating the nWDTO signal MPU has to periodically reload the counter value into the watchdog counter register WTCNT The nWDTO signal is not connected to nRESE
175. ables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program Chapter 4 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 5 Special Function Regsiters contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the KS17 series RISC Microprocessor family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 and 5 Later you can reference the information in Part as necessary Part I hardware Descriptions has detailed information about specific hardware components of the KS17C80064 C80013 F80013 RISC Microprocessor Also included in Part Il are electrical mechanical and MTP It has 14 chapters Chapter 6 System Reset and Power Mode Chapter 13 PWM Chapter 7 Clock Circuits Chapte
176. ad Timing Page Mode Address Figure 4 15 DRAM Bank Write Timing Page Mode 07 4 16 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER DRAM REFRESH CONTROL REGISTER The KS32C65100 DRAM interface provides the CAS before RAS CBR refresh and self refresh mode The refresh control register REFCON determines refresh mode refresh timings refresh intervals as well as external bus enable REFCON 0x00001024 R W DRAM refresh control 0x00000001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Validity of Special Register Field VSF 0 Not accessable to memory bank 1 Accessable to memory bank Whenever MCU access of system manager registers SMR VSF bit is auto activate external bus VSF bit should be set to 1 by using STMIA instruction in the last Programmer should write into 10 system manager registers altogether with STMIA instruction while VSF bit set instruction is in the last 15 Reserved 0 16 Refresh Enable REN 0 Self refresh mode or disable DRAM refresh When this bit is set 0 DRAM enters the self refresh mode and cannot be accessed 1 Enable DRAM refresh When this bit is cleared MCU refreshs DRAM periodically and can read write the DRAM 19 17 CAS Hold Time Tcs 000 1 cycle 100 5 cycles 001 2 cycles 101 Not used 010 cycles 110 Not used 011 4 cycles 111 Not used 20 CAS Set up Time
177. adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value 3 78 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 11 SP RELATIVE LOAD STORE 15 14 13 7 0 1 12 11 10 8 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 40 Format 11 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in the following table Table 3 18 SP Relative Load Store Instructions STR Rd SP STR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR Rd lmm LDR Rd R13 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied in is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places gt gt 2 in the Word8 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB
178. address of DRAM control register by changing the contents SYSCFG DRAMCONO 0x0000101c DRAM 0 control register 0x00000000 0x00001020 DRAM 1 control register 0x00000000 The KS32C65100 provides fully programmable external DRAM interface features Programmers can easily modify the interface modes such as external data bus width number of access cycles for fast page or EDO access cycles for each DRAM bank and row address strobe nRAS pre charge timing by changing the contents of corresponding DRAM control register The refresh control register controls DRAM refresh operation and KS32C65100 supports CAS before RAS CBR refresh mode amp self refresh mode KS32C65100 can generate row amp column address and supports symmetric Asymmetric address DRAM by changing the number of address line from 8 to 11 It can support various size of DRAM by varying column address size If the number of a column address or a row addresses is bigger than 11 the accessible DRAM memory size is smaller than the original size of the DRAM For example if 16M bit DRAM with 4Mx4 row address 12bit amp column address 10bit is connected to KS32C65100 the maximum accessible size of the memory is 8Mbit 11bit x 10bit and the other 8Mbit will be obsolete EDO mode DRAM Accessing Even If users specify DRAM as EDO mode KS32C65100 gives same timing diagram compared with normal fast page mode However KS32C65100 CPU fetches data when read later by
179. after system reset The SYSCFG should not overlap with any other bank If a start address of SYSCFG has changed other control registers in the SFRs will have a new start address which is its offset address the new address of SYSCFG For example after the system reset the initial address of SYSCFG is 1000000h and ROM control register has initial address 1001000h because the ROM control register has the offset address value 1000h and its initial address is the sum of 1000000h 1000h If the SYSCFG address is changed to 1800000h the ROM control register address becomes 1801000h Cache Disable Enable KS32C65100 Cache memory provides the programmable Cache disable and enable feature It also provides a non cacheable area feature to maintain data coherency for specific memory areas Programmers can disable or enable the cache by setting the CE bit to O or 1 Programmers should be cautious about data coherency when cache memory is re enabled because cache memory doesn t have an auto flushing mode Programmers also have to be cautious about changes the memory data Usually the access memory area must be non cacheable to keep data coherency To keep the data coherency between the cache and external memory KS32C65100 uses a write through policy To compensate for the performance degradation due to the write through policy there is internal 4 depth write buffer A detailed description will be given in Chapter 5 Write Buffer Disa
180. al filtering when the digital filtering enable bit PPCON 1 is 17 10 nINIT Input Level This read only bit reflects the logic level on the nINIT input after synchronization and optional digital filtering when the digital filtering enable bit PPCON 1 is 1 Figure 10 5 Parallel Port Status Register 10 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE PARALLEL PORT ACK WIDTH REGISTER This register contains the 9 bit nACK pulse width field This value defines the nACK pulse width whenever the parallel port interface controller enters compatibility mode that is when the parallel port control register mode bits PPCON 3 2 are 01 The nACK pulse width can be selected from 0 to 511 MCLK periods The nACK pulse width can be modified at any time and with any PPIC operation mode selected but it can only be used during a compatibility handshaking cycle If you change the nACK width near the end of a data transfer when nACK is already low the new pulse width value does not affect the current cycle The new pulse width value would be used at the start of the next cycle PPACKWTH 0x8008 Parallel port acknowledge width register OxXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8 0 nACK Pulse Width The value in this 9 bit field defines the nACK pulse width when compatibility mode is enabled PPCON 3 2 1017 The period of the nACK pulse can range from 0
181. all one PON gt In all other cases ASSEMBLER SYNTAX MUL cond S Rd Rm Rs MLA cond S Rd Rm Rs Rn cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 Examples MUL R1 R2 R3 R1 R2 R3 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 R3 R4 Setting condition codes ELECTRONICS 3 21 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results signed and unsigned multiplication each with optional accumulate give rise to four variations 23 22 21 20 19 16 15 12 11 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the uppe
182. aluation board is a platform that is suitable for code development and exploration of KS32C65100 It supports various memory devices such as DRAM SRAM EPROM and Flash Using the embedded ICE interface you can debug the KS32C65100 directly SYSTEM REQUIREMENTS Host computer IBM compatible PC Evaluation board of KS32C65100 DC power supply with the following outputs 5V at 0 5 Parallel Cable 25 pin Serial cable 9 pin ELECTRONICS 26 1 VARIABLE IMAGE SCALING BOARD COMPONENTS KS32C65100 RISC MICROPROCESSOR The arrangement of major components on the board is shown in Figure 29 1 The major components include EPROM Flash Memory SRAM DRAM Parallel Port Serial Ports JTAG Port Expansion Connectors Buttons LED Indicators 26 2 There are two sockets U13 and U14 which will accept 8 bit FLASH or EPROM with 64 K size for lower byte U13 and upper byte U14 data access respectively The two sockets finally form 64 K x 16 bit ROM bank You can control the memory type by setting the jumper JP15 and JP16 Two sockets U18 and U19 are supplied for SRAM memory bank with 128 K x 16 bit size The U18 and the U19 will accept the 128 K 8 bit SRAM for lower byte data and upper byte data respectively Two sockets U15 and U16 are supplied for DRAM memory bank with 1M x 16 bit size One parallel port PRINT is supplied to support parallel data communication between the host PC and the evaluation board
183. alue 1 PWM Counter Clock time pulse width On time value 1 PWM Counter Clock MAIN INPUT OUTPUT SIGNALS Output PWM OUTO PWMO timer output signal PWM_OUT1 PWM timer output signal PWM OUT2 PWM2 timer output signal ELECTRONICS 27 1 PWM TIMER CONTROL KS32C65100 RISC MICROPROCESSOR SPECIAL FUNCTION REGISTER PWM Control Register PWMCONR 0 000 PWM control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Counter 0 Stop 1 Run PWM1 Counter 0 Stop 2 Run PWM2 Counter 0 Stop Figure 27 1 PWM_CON Control Register PWM Counter Pre Scaler PWM_PRSC 0 004 RW PWM Pre Scaler counter base value register 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Observation Observation Observation Counter Counter Counter Value2 Value1 ValueO Base2 Base1 0 7 0 Pre ScalerO Counter Base Value 11 8 Pre Scaler1 Counter Base Value 15 12 Pre Scaler2 Counter Base Value 23 16 Pre ScalerO Counter Observation Value 27 24 Pre Scaler1 Counter Observation Value 31 28 Pre Scaler2 Counter Observation Value Figure 27 2 PWM Pre Scaler Counter Base Observation Register 27 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PWM TIMER CONTROL PWM Cycle On Time Base amp Observation Register i i PWM ONT2 PWM
184. an change the mode selection at any time but if a compatibility mode operation is currently in progress it will be completed as normal Mode should be changed from compatibility mode only when BUSY is high level This ensures that there is no parallel port activity during the time when the parallel port is being re configured ECP without RLE mode ECP mode hardware handshaking without RLE support can be enabled during forward or reverse data transfers You can change the mode selection at any time but if an ECP cycle is currently in progress it will be completed as normal ECP with RLE mode ECP mode hardware handshaking with RLE support can be enabled during forward or reverse data transfers Change on the mode selection doesn t affect current data transfer operation including compression decompression until it completes To immediately abort an operation you can set the software reset bit PPCON O to 1 4 ECP direction This bit determines the direction of ECP is forward or reverse If this bit is set to 1 then the ECP is operated in reverse direction 10 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR 5 Error cycle 6 Data bus output enable 7 Abort 8 DMA selection ELECTRONICS PARALLEL PORT INTERFACE The error cycle bit is used to execute an error cycle when in compatibility mode When PPCON 5 is set to 1 the BUSY status bit in the parallel port interface register PPSTAT 5 is set to 1 Th
185. and byte mode data transfers and termination cycles must be carried out by software The IEEE 1284 EPP communications mode is not supported NOTE Here we assume that you are familiar with the parallel port communication protocols specified in IEEE 1284 parallel port standard If not we strongly recommend you to read this standard beforehand It will help you to understand the contents described in this section A detailed technical introduction to IEEE 1284 parallel port standard can be found in the web site http www fapo com ieee1284 htm ELECTRONICS 10 1 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR KS32C65100 PPIC OPERATING MODES The KS32C65100 PPIC supports four kinds of handshaking modes for data transfers e Software handshaking mode for forward and reverse data transfers Compatibility hardware handshaking mode for forward data transfers ECP hardware handshaking without RLE support ECP without RLE mode for forward and reverse data transfers ECP hardware handshaking with RLE support ECP with RLE mode for forward and reverse data transfers Mode selection is specified in PPIC control register PPCON By setting the PPCON S 2 one of these four modes can be enabled Software Handshaking Mode This mode is enabled by setting the PPCON s mode selection bits as 00 i e PPCON 3 2 00 In this mode by using PPIC interrupt event registers PPINTEN amp PPINTPND and reading writing PPIC status reg
186. arded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 3 27 26 1 0 Contents of Rm carry out Value of Operand 2 00000 Figure 3 6 Logical Shift Left NOTE LSL 0 is a special case where the shifter carry out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A logical shift right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET 31 0 Contents of Rm 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 82 to be specified An arithmetic shift right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 31 30 5 4 0 Contents of R
187. ase second or later in the transfer order will store the modified value A LDM will always overwrite the updated base if the base is in the list DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH This can happen on any transfer during a multiple register load or store and must be recoverable if ARM7TDMI is to be used in a virtual memory system Aborts during STM Instructions If the abort occurs during a store multiple instruction ARM7TDMI takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When ARM7TDMI detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible e Overwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved e The base register is restored to its modified value if wri
188. ata Package Dimensions Chapter 29 Evaluation Board HITFOG Pre ol REOR NE System Requirements Board Booting EmbeddedlCE Unit Installation EmbeddedlCE Connecting KS32C65100 Evaluation Board and Powering Up The Board and Debug Application With EmbeddedICE Switch and Jumpers Description KS32C65100 RISC MICROPROCESSOR XV List of Figures Figure Title Page Number Number 1 1 KS32C65100 Block Diagram 1 4 1 2 Pin WAS To Ttt RM 1 5 2 1 Big Endian Addresses of Bytes within Words 2 2 2 2 Little Endian Addresses of Bytes within Words 2 2 2 3 Register Organization ARM 1 2 4 2 4 Register Organization in THUMB 2 5 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 2 6 Program Status Register Format 2 7 3 1 ARM Instruction Set Format 3 1 3 2 Branch and Exchange 3 4 3 3 Branch 5 5 3 6 3 4 Data Processing Instructions 3 8 3 5 ARM Shift
189. be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 9 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted register the operation of the barrel shifter is controlled by the Shift field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may be contained in an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 6 5 Shift Type 6 5 Shift Type 00 Logic left 01 Logical right 00 Logic left 01 Logical right 10 Arithmetic right 11 Rotate right 10 Arithmetic right 11 Rotate right 11 7 Shift Amount 11 8 Shift Register 5 Bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations Instruction Specified Shift Amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left 151 takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map into the result are disc
190. bit is redundant and is always set to zero since the old base value can be retained if necessary by setting the offset to zero Therefore post indexed data transfers always write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected HALFWORD LOAD AND STORES Setting S 0 and H 1 may be used to transfer unsigned Half words between ARM7TDMI register and memory The action of LDRH and STRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below SIGNED BYTE AND HALFWORD LOADS The S bit controls the loading of sign extended data When S 1 the H bit selects between Bytes H 0 and Half words H 1 The L bit should not be set low Store when signed S 1 operations have been selected The LDRSB instruction loads the selected Byte into bits 7 to O of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit The LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section ENDIANNESS AND BYTE HALFWORD SELECTION Little Endian Configuration A signed byte load LDR
191. ble Enable KS32C65100 has four Write Buffer Registers to enhance the memory writing performance It s operation mode is programmable When Write buffer mode is enabled CPU writes data into write buffer first instead of an external memory which requires longer memory write cycles The write buffer has 4 registers and each register includes 32 bits of data field 25 bits of address field and 2 bit of status field Stall Disable Enable When the stall option is enabled the MCU core logic inserts a wait when non sequential memory accesses occur So the MCU core has more time margin during memory access When the stall option is disabled the logic doesn t insert a wait so that s faster than when the stall option is enabled ELECTRONICS 4 5 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR ROM CONTROL REGISTER The KS32C65100 ROM interface has one ROM bank for program memory it provides configurable features such as access timing access size and page mode support etc The ROM Control Register ROMCON in SMR supplies the control mode such as normal mode access page mode access and wait cycles of each mode for the external ROM bank The initial address of ROMCON is 01001000h and it is the sum of the initial address of SYSCFG 01000000h and the ROM control register offset address 00001000h The register address is re configurable that programmers can change the ROM control register by changing the contents of SYSCFG The real address of
192. bler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm lt shift gt offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes Rn Rm lt shift gt offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR Examples STR STR LDR LDR LDREQB STR PLACE ELECTRONICS R1 R2 R4 R1 R2 R4 R1 R2 16 R1 R2 R3 LSL 2 R1 R6 5 R1 PLACE Store R1 at R2 R4 both of which are registers and write back address to R2 Store at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load R1 from contents of R2 R3 4 Conditionally load byte at R6 5 into R1 bits O to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 29 ARM
193. by software or hardware direction interrupt request generation and clock select LFCR 0x5800 Line feed motor control register 0x0800 ELECTRONICS 16 1 LF MOTOR KS32C65100 RISC MICROPROCESSOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 4 0 Timer Start 0 Stop timer 1 Start timer 2 1 Clock Select 00 MCLK prescaler 1 8 01 MCLK prescaler 1 16 10 MCLK prescaler 1 32 11 MCLK prescaler 1 64 3 Interrupt Request at Each Step 0 Disable 1 Enable 4 Write Strobe Write Only async clk 0 No operation 1 Write strobe 5 Step Write Enable 0 Disable 1 Enable 6 Phase Hold 0 Disable 1 Enable 7 Direction 0 Up 8 Chop Enable 0 Disable 1 Enable 9 Phase Write Mode 0 Phase written by software 1 Phase written by hardware 10 Motor Selection 0 Bi polar 1 Uni polar 11 Initialize Drive State Write Only 0 Initialize 1 Normal 12 Software Latch Strobe Write Only 0 No operation 1 Latch strobe 13 Interrupt Latch Enable 0 Disable 1 Enable 15 14 Phase 00 Full step 01 Half step 1x Quarter step Figure 16 1 LF Motor Control Register 16 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR LF MOTOR LINE FEED MOTOR PHASE CONTROL REGISTER LFPCR 0x5804 Line feed motor phase control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07
194. ccess Controller 3 DMA Controller e Memory to print block with decompression e Memory to memory memory to parallel port parallel to memory UART to memory memory to UART IP to memory memory to IP data memory to I O data transfers without CPU intervention e Initiated by software or external DMA request e Increments or decrements source or 8 bit 16 bit or 32 bit data transfer Interrupts 31 interrupt sources external 3 e Normal or fast interrupt modes IRQ FIQ e Level or edge selectable 3 external interrupt 1 2 KS32C65100 RISC MICROPROCESSOR UART SIO e Three channel UART Serial I O with DMA based or interrupt based operation supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive Programmable baud rate Tx Rx support IrDA General Timers e Three programmable 16 bit timers Watch Dog Timer e 16 bit timer useful for periodic reset or interrupts PWM Timers e Three programmable 16 bit PWM timers with each prescaler General ADC e Three input 8 10 bit ADC with analog MUX Max conversion rate 650KSPS 25MHz e ADC clock MCLK 2 or MCLK 4 Scan Image Control e Minimum scan line time up to 2 ms e Supports 200dpi or 300dpi include 8 bit ADC 25 200 reduction magnification e White shading amp gamma correction LAT EDF 2X3 Binarization 256 Gray Scan Motor Control Programmable 16 bit int
195. ce if the register value is 9 H100 and for any value below it reduction is carried out according to the formula given below This feature is used when sending an image to a 203DPI level fax when using a 300DPI level sensor This feature uses sampling by an adder You only need to set the reduction bit and you can adjust in units less than 196 Register Value Reduction Ratio x 256 To find the number of reduced pixels compared to the input pixels use the following formula Re vae x Number of input pixels number of reduced pixels Except if the value behind the decimal point of the formula s result is larger than Register Value Re ister Value add 1 to the result If not the value found is the actual number of reduced pixels For example when reducing a 300DPI image to 203DPI the register setting value is Register Value 203 x 256 137 23 so you should set 137 to the register The number of reduced pixels can be found in the following manner x 2557 1727 9 in 0 97 is larger than lt 0 67 so the number of pixels actually reduced is 1728 PIX CLK RED BAN reduction ban CLK INNER PIX CLK reduction PIX CLK Figure 21 17 Reduction Pixel Clock Timing Diagram Reduction Vertical The feature described above allows vertical reduction in units of 1 128 using a 3 bit register The basic algorithm is the same as that in the horizontal direction but the unit of reduction is 8 bits and the reductio
196. ced in LR Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address is placed in PC the address of the instruction following the BL is placed in LR and bit 0 of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction 3 90 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 3 26 The BL Instruction THUMB Assembler Equivalent Acton 0 BL label LR PC OffsetHigh lt lt 12 Temp next instruction address PC LR OffsetLow lt lt 1 LR temp 1 Examples BL faraway Unconditionally branch to next m and place following instruction address i e next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned ELECTRONICS 3 91 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared
197. composed of 128 lines Figure 25 15 F 9 Compensation Table Start Address FSADDR 25 18 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER F 0 COMPENSATION TABLE DATA REGISTER The CPU reads writes this register when accessing the compensation Table FDATA 0xa034 F 0 compensation data register Oxeffb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 Divide Value Decides how to divide clock 15 8 Repetition Count Decides how many divided clocks to send out Figure 25 16 F 9 Compensation Table Data Register FDATA TONER COUNTER SETTING REGISTER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Toner Counter Setting Value 31 0 Toner Counter Setting Value Holds the toner counter setting value If you write in this register the toner counter counts from the value written Figure 25 17 Toner Counter Setting Register TCVAL ELECTRONICS 25 19 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR TONER COUNT REGISTER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 31 0 Toner Count Holds the toner count value Figure 25 18 Toner Count Register TNCNT Test Pattern Duration TPVAL 0xa040 Test pattern duration value register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03
198. cond Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 lt psr gt CPSR CPSR all SPSR or SPSR all CPSR and CPSR all are synonyms as are SPSR and SPSR all lt psrf gt CPSR flg or SPSR_flg lt gt Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error Examples In user mode the instructions behave as follows MSR CPSR all Rm 31 28 lt Rm 31 28 MSR CPSR flg Rm CPSR 31 28 lt Rm 31 28 MSR CPSR flg amp 0xA0000000 CPSR 81 28 lt set C clear Z MRS Rd CPSR 31 0 lt 1 0 In privileged modes the instructions behave as follows MSR CPSR all Rm CPSR 31 0 Rm 31 0 MSR CPSR flg Rm CPSR 31 28 Rm 31 28 MSR CPSR_flg 0x50000000 CPSR 31 28 lt 0x5 set Z V clear C MSR SPSR all Rm SPSR_ lt mode gt 31 0 Rm 31 0 MSR SPSR flg Rm SPSR_ lt mode gt 31 28 Rm 31 28 MSR SPSH 19 0 0000000 SPSR_ lt mode gt 31 28 lt OxC set Z clear C V MRS Rd SPSR Rd 31 0 SPSR mode 31 0 ELECTRONICS 3 19 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown
199. ctive 2 Source Address Direction 0 Increase source address 1 Decrease source address 3 Source Address Fix 0 Increase decrease source address 1 Do not change source address fix 4 Reset 0 Normal operation 1 Initialize control register 5 Not Used 6 Match Pend Status 0 Not match 1 Match 7 Match Interrupt Pending Enable 0 Match Interrupt disable 1 Match interrupt enable 8 HDMA Interrupt Enable 0 Do not generate stop interrupt and match interrupt 1 Generate stop interrupt and match interrupt when HDMA stops 9 Auto Load 0 Do not load parallel load 1 Load parallel load of counter register 10 Alternate Enable 0 Cannot operates alternation 1 Can operation alternation between bank 0 and bank 1 11 Current Queuing Bank Selection 0 Bank 0 1 Bank 1 16 Queuing Enable Bit 0 0 Queuing 0 disable 1 Queuing 0 enable 24 Queuing Enable Bit 1 0 Queuing 1 disable 1 Queuing 1 enable Figure 20 1 HDMA Control Register ELECTRONICS 20 3 HDMA KS32C65100 RISC MICROPROCESSOR HDMA SOURCE ADDRESS REGISTER These registers contain the 28 bit source destination address for the HDMA channel Depending on the settings you make to the control register HDCON theses adr will be fixed increased or decreased HDSAR 0x7804 HDMA source address register 0x0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
200. d as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 should not be specified as the register offset Rm When R15 is the source register Rd of Half word store STRH instruction the stored address will be address of the instruction plus 12 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 1S 1N 11 LDR H SH SB PC take 2S 2N 11 incremental cycles S N are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STRH instructions take 2N incremental cycles to execute ELECTRONICS 3 33 ARM INSTRUCTION SET ASSEMBLER SYNTAX KS32C65100 RISC MICROPROCESSOR lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR STR cond H SB SH Rd lt address gt can be 1 3 34 Load from memory into a register Store from a register into memory Two character con
201. d for bank selection and CAS signal is used for byte selection mode Example Settings for 60 5 EDO DRAM KM416V1204 Memory map 1000000h 11fffffh 0x9040101a DRAM 10bit row x 10bit column x 16bit data 60ns EDO MCLK 33MHz 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 E 1 0 Bus Width DW 00 Disable bank 01 8 Byte 10 16 Half word 11 2 No use 3 2 Column Address Number CAN 00 8 bits 01 9 bits 10 10 bits 11 11 bits 4 EDO DRAM or Ordinary DRAM EDO 0 Ordinary 1 EDO DRAM 6 5 CAS Strobe Time Page Mode Tpgm 00 1 cycle 01 2 cycles 10 3 cycles 11 4 cycles 7 CAS Pre Charge Tcp 0 z 1 cycle 1 2 cycles 10 8 CAS Strobe Time Single Mode Tcs 000 1 cycle 100 5 cycles 001 2 cycles 101 2 Not used 010 cycles 110 2 Not used 011 4 cycles 111 2 Not used 11 RAS to CAS Delay Trc 0 1 cycle 1 2 cycles 13 12 RAS Pre Charge Time 00 1 cycle 01 2 cycles 10 2 3 cycles 11 4 cycles 22 14 Base Point of DRAM x Base Pointer DRAM bank start address 31 23 End Point 1 of DRAM x Next Pointer DRAM bank end address 1 Figure 4 13 DRAM Control Registers DRAMCONO DRAMCON 1 ELECTRONICS 4 15 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR Column Address Address Address Row Address Fetch Time E 58 Fetch Time Normal DRAM EDO DRAM Figure 4 14 DRAM Bank Re
202. d operation during power down mode the previous A D conversion data are produced 7 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR GENERAL ADC SPECIAL REGISTER ADC Control Register The A D converter control register ADCCON is used to control the operation of the 10 bit A D converter as follows ADCCON 0xd800 ADC control register 0 A D conversion enable This bit is A D conversion start bit This bit is auto cleared after A D conversion start up 2 1 Analog input Select the analog input to be converted from AIN 2 0 Select AIN O for 00 AIN 1 for 01 AIN 2 for 10 and none if 11 3 Reserved This bit must be 0 4 Clock select Select between MCLK divided by 2 and MCLK divided by 4 as the XP1 clock Select 2 for 0 and 4 for 1 5 Stand by mode This bit is used for keeping standby without A D conversion operation For A D conversion its state must be changed from 1 to 0 for at least one XP1 period 6 8 bit mode It switches the ADC function between 8 bit and 10 bit The Low state is maintained in 10 bit operation and high state in 8 bit operation 7 Flag Its state goes 0 during A D conversion and goes 1 after the A D conversion If STBY signal is applied even at A D conversion mode its state goes 1 immediately ELECTRONICS 7 3 GENERAL ADC KS32C65100 RISC MICROPROCESSOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 A D Conve
203. data before the VIS process and the output destination image data after the VIS process The SrcReg is an 8 bit register and the DstReg is a 16 bit register 0xa810 Source image data register Destination image data register OxXXXX 0xa814 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SrcReg Source Image Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DstReg Destination Image Data SrcReg 7 0 Source Image Data This 8 bit field contains the input source image data to be processed by VIS DstReg 15 0 Destination Image Data This 16 bit field contains the output destination image data after VIS procession Figure 26 7 VIS Data Registers SrcReg DstReg ELECTRONICS 26 7 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR Half toner Data Registers Three half toner data registers and HftReg respectively contain the input reference source pixel data before the half toning process and the output the halftone data after the half toning process oaeo mage data register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Refln Reference Data n 1 Reference Data n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Source Pixel Data n 1 Source Pixe
204. data that was transferred DMACNTO 0x880c CDMA transfer count register OxXXXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMACNTO Number of Transfers 23 0 Number of Transfers Figure 9 10 CDMA Transfer Count Register 9 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE PARALLEL PORT INTERFACE OVERVIEW The KS32C65100 s parallel port interface controller PPIC supports four IEEE 1284 standard communication modes e Compatibility mode Centronics TM e Nibble mode e Byte mode e Enhanced Capabilities Port ECP mode The PPIC also supports all variants of these communication modes including device ID requests and Run Length Encoded RLE data compression The PPIC contains specific hardware to support the following operations e Automatic hardware handshaking between host and peripheral in compatible and ECP modes e Run length detection and compression decompression of host to peripheral or peripheral to host data during ECP mode transfers These features can substantially improve data rates when operating the parallel port in compatibility or ECP mode In addition hardware handshaking over the parallel port can be enabled or disabled by software This gives the programmer direct control of PPIC signals as well as the eventual use of future protocols Other operations defined in IEEE 1284 Standard such as negotiation nibble mode
205. defined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC or store STC a subset of a coprocessors s registers directly to memory ARM7TDMI is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 28 27 25 24 23 22 21 20 19 16 15 12 11 0 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write Back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtrack offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions THE COPROCESSOR FIELDS The field is used to identify the coprocessor which is required to supply or accept the data and a coprocessor will only respond if its number matches the contents of this field The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors but by convention CRd is the register to be transferred or the first register where more than one is to be transferred and the N bit is used to choose one of two tra
206. des The action of 0 H2 0 for Op 00 ADD Op 01 and Op 10 MOV is undefined and should not be used 3 68 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3 12 Summary of Format 5 Instructions ADD Rd Hs ADD Rd Rd Hs Add a register in the range 8 15 to a register in the range 0 7 ADD Hd Rs ADD Hd Hd Rs Add a register in the range 0 7 to a register in the range 8 15 1 1 ADD Hd Hs ADD Hd Hd Hs Add two registers in the range 8 15 01 1 Rd Hs CMP Rd Hs Compare a register in the range 0 7 with a register in the range 8 15 Set the condition code flags on the result CMP Hd Rs CMP Hd Rs Compare a register in the range 8 15 with a register in the range 0 7 Set the condition code flags on the result ER d Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition code flags on the result Rd Hs MOV Rd Hs Move a value from a register in the range 8 15 to a register in the range 0 7 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 EE Hd Hs MOV Hd Hs Move value between two registers in the range 8 15 Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equ
207. ding Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Microprocessor business has been awarded full ISO 14001 certification BSI Certificate No FW24653 All semiconductor products are designed and manufactured in accordance w
208. dition mnemonic See Table 3 2 Transfer halfword quantity Load sign extended byte only valid for LDR Load sign extended halfword only valid for LDR An expression evaluating to a valid register number An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register Rn and Rm are expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining In this case base write back should not be specified Writes back the base register set the W bit if is present ELECTRONICS KS32C65100 RISC MICROPROCESSOR Examples LDRH STRH LDRSB LDRNESH HERE STRH FRED ELECTRONICS R1 R2 R3 R3 R4 4H 4 R8 R2 4 223 R11 RO R5 PC FRED HERE 8 ARM INSTRUCTION SET Load R1 from the contents of the halfword address contained in R2 R3 both of w
209. e affected by the instruction cond A two character mnemonic as shown in Table 3 2 If absent then AL ALways will be used lt expression gt The destination The assembler calculates the offset Examples here BAL here Assembles to OXEAFFFFFE note effect of PC offset B there Always condition used as default CMP R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue BEQ fred Continue to next instruction BL sub ROM Call subroutine at computed address ADDS R1 1 Add 1 to register 1 setting CPSR flags onthe result then call subroutine if BLCC sub the C flag is clear which will be the case unless R1 held OxFFFFFFFF ELECTRONICS 3 7 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 4 28 27 26 25 24 21 20 19 1615 12 11 10 0 15 12 Destination Register 0 Branch 1 Branch with link 19 16 1st Operand Register 0 Branch 1 Branch with link 20 Set Condition Codes 0 Do not after condition codes 1 Set condition codes 24 21 Operation Code 0000 AND Op1 AND 0001 EOR Rd Op1 EOR 0010 SUB Rd Op1 0011 RSB Rd Opt 0100 ADD Rd Op1 0101 ADC Rd Op1 Op2 0110 SBC Rd Op1 Op2 C 1 0111 RSC Rd O
210. e IP block The mode selection bits determine which source can initiate a DMA operation at any given time see Figure 9 5 4 Destination adr direction This bit determines whether the destination address will be decreased or increased during a DMA operation 5 Source address direction This bit determines whether the source address will be decreased or increased during a DMA operation 6 Destination address fix This bit determines whether the destination address will be changed or not during a DMA operation This feature is used when transferring data from multiple sources to a single destination 7 Source adr fix This bit determines whether the source address will be changed or not during a DMA operation This feature is used when transferring data from a single source to multiple destinations 8 Stop interrupt enable DMA operation is started stopped by setting clearing the run enable disable bit If this bit is set to 1 and DMA is running a stop interrupt is generated when DMA operation forced to stop on purpose If this bit is 0 the stop interrupt is not generated The interrupt which is generated when the DMA counter is expired cannot be masked by this bit 9 Reset If this bit is set to 1 then the DMA control register value will refer to default values When this bit is cleared to 0 you can specify other control values 10 Peripheral direction This mode bit specifies the direction of the DMA operation I
211. e RATIO 0x981c Magnified reduced ratio register 0x10080 Processing 0x9820 Local adaptive register Oxdc7140 0x9824 IP ADC control register 0x005 OPERATION 0x9828 Operation control register 0x000 RAM CTRL 0x982c IP inner SRAM control register 0x70000 RAM DATA 0x9830 IP inner SRAM data register MOTOR TERM 0x9834 Motor signal period register 0x0000 MOTOR PHASE 0x9838 Motor signal phase register 0 001 BLACK 0x983c Black shading correction value register LFCR 0x5800 Line feed motor control register 0x0800 LFPCR 0x5804 Line feed motor phase control register LFTBR 0x5808 Line feed motor timer base register 0x0000 LFTOR 0x580c Line feed motor timer observation register 0x1e0d LF Motor L 0x5810 R W Line feed motor timer compare base 0x0000 register LFTCOR 0x5814 LF motor timer compare observation 0x0000 register LFCON 0x5818 LF step each control register 0x0000 ELECTRONICS 1 15 PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR Table 1 2 KS32C65100 Special Function Registers Continued Register R W Description Reset Value CMCR 0x6000 Carrier motor control register 0x204 BTB1R 0x6004 R W Basic timer base register 1 OxXXXX BTB2R 0x6008 R W Basic timer base register 2 OxXXXX PSTBR 0x600c R W CR Step INT counter amp pre step counter 0x000 base register camer PWMOBS oxeo14 PWMcounterobservationregister 0 0000 dis ECDTIM 0x6020 PWMontimebaseregister 0020292 ECDVAL 0x6
212. e added to or subtracted from a Lo register The THUMB assembler syntax is shown in Table 3 9 NOTE All instructions in this group set the CPSR condition codes Table 3 9 Summary of Format 2 Instructions op THUMB Assembler ARM Equivalent ADD Rd Rs Rn ADDS Rd Rs Rn contents of Rn to contents of Rs Place result in Rd 1 ADD Rd Rs Offset3 ADDS Rd Rs Add 3 bit immediate value to contents of Offset3 Rs Place result in Rd 1 SUB Rd Rs Rn SUBS Rd Rs Rn Subtract contents of Rn from contents of Rs Place result in Rd 1 1 SUB Rd Rs Offset3 SUBS Rd Rs Subtract 3 bit immediate value from Offset3 contents of Rs Place result in Rd INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 9 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD RO R3 R4 RO R4 and set condition codes on the result SUB R6 R2 6 6 R2 6 and set condition codes 3 64 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 12 11 10 8 7 0 1 7 0 ImmediateValue 10 8 Source DestinatiomRegister 12 11 Opcode 0 2 MOV 1 2 ADD 3 SUB Figure 3 32 Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8 bit immediate value The THU
213. e of the sensor The period of the SEN varies for different brands such as DYNA and CANON You need a 50 period for a CANON product and 25 period for a DYNA product The SEN CLK 15 8 adjusts the SEN signal s high period and the SEN CLK 7 0 adjust the SEN CLK s low period in system clock units It takes at least 10 system clocks to handle an actual pixel NOTE The phase of the SI and SEN CLK signal can change according to the different brands For example for a 200DPI DYNA or 300DPI CANON the two signals are high active but for a 300DPI DYNA it is low active Also a CANON product uses the 2 channel method which reads values from SEN CLK s both high and low level For that the register RATIO 17 SEN CLK LOW ACTIVE and RATIO 18 PHASE1 PHASE2 are prepared RLED GLED BLED This signal is for controlling the sensor s brightness The lamp s operational range is decided using the values of registers RLED GLED And BLED The SEN CLK period as the unit reference Generally only one of three signals is needed for normal mono CIS but the canon color CIS uses all three signals ELECTRONICS 21 11 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR REDUCTION amp MAGNIFICATION This feature uses the register value to magnify up to 20096 or reduce horizontally to a unit less than 196 and to reduce vertically Reduction Horizontal A 9 bit register be used for reduction in 256 steps Reduction can t take pla
214. e perform short transfer N 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor cd Ma evaluating to a valid coprocessor register number that is placed in the ie Address can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn xexpression offset of expression bytes 3 A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes write back the base register set the W bit if is present Rn is an expression evaluating to a valid register number NOTE If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining Examples LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2 c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from R5 write this address back to R5 and use long transfer option probably to store multiple words NOTE Although the address offset is expressed in bytes the instruction offset field is in words The assembler will adjus
215. e sensor turned off Figure 21 15 Block Shading Correction Factor Register SENSOR CIS The sensor is influenced by the 300DPI Canon DYNA S CIS The signal output from the controller to the sensor include the Sl SEN CLK RLED GLED and bled The reset values for all registers related to the sensor are set with the DYNA 200DPI as reference SI The SI signal is for latching the electrical charge the sensor The period is in units according to the value of register SI 12 0 This signal is adjusted during operation by S W so that it is synchronous to the motor The SI signal is automatically operated once the power is on but an interrupt occurs every time an SI signal is generated so you can change the SI period if you change the value according to this signal One thing to remember is that if you change the register SI value according to the interrupt it influences the period of the next SI If you give the restart signal by S W for synchronicity a new SI signal is generated from that signal Shading and binarization are carried out only when the SI signal and the SCAN ON are both high s l Restart Recount Start SI TERM SI TERM SI TERM J i Image Handing Figure 21 16 Restart amp SCAN_ON Timing Diagram 21 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR SEN CLK The SEN CLK is a clock for shifting the values latched by the SI signal to the outsid
216. e the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed Instructions SMULL SMLAL e f bits 31 8 of the multiplier operand are all zero or all one e f bits 31 16 of the multiplier operand are all zero or all one e f bits 31 24 of the multiplier operand are all zero or all one other cases For Unsigned Instructions UMULL UMLAL e f bits 31 8 of the multiplier operand are all zero e If bits 31 16 of the multiplier operand are all zero e If bits 31 24 of the multiplier operand are all zero e In all other cases S and are defined as sequential S cycle and internal respectively ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions Mnemonic Deswpion UMULL cond S RdLo RdHi Rm Rs Unsigned multiply long 32 x 32 64 UMLAL cond S RdLo RdHi Rm Rs Unsigned multiply amp accumulate long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed multiply long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed multiply amp accumulate long 32 x 32 64 64 cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 Examples UMULL R1 R4 R2 R3 R4 R1 R2 R3 UMLALS R1 R5 R2 R3 R5 R1 R2 R3 R5 R1 also setting condition codes ELECTRONICS 3 23 ARM INSTRUCTION S
217. ecutive Dot Eliminator 0 Disable 1 Enable 10 Top Nozzle Group Select 0 Right 1 Left 11 Vertical 300DPI Mode 0 Half word 1 Byte 12 Horizontal 300DPI Mode 0 Disable 1 Enable 13 Decompression Mode 0 Disable 1 Enable 14 Data Select 0 By H W 1 S W 15 Simulation Test Control HDMA Request Generation 0 Disable 1 Enable 16 Perform a Fire Cycle Write Only 0 Disable 1 Enable 17 Perform a Data Cycle Write Only 0 Disable 1 Enable 19 18 Clock Select 00 MCLK 1 10 MCLK 4 01 MCLK 2 11 2 MCLK 8 23 20 Address Line for the Nozzle 24 Address Line by S W 0 Disable 1 Enable 25 Current Mode 0 Printing 1 Scanning Figure 19 1 Print Head Control Register ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINT HEAD FIRE ENABLE TIMER OBSERVATION REGISTER This 8 bit timer is used for fire enable duration counter value The observation register is read only which is of the current value FETR 0x7004 Fire enable timer register FETOR 0x7008 amp Fire enable timer observation register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 Counter Value This data specifies the amount in the counter Figure 19 2 Fire Enable Timer Observation Register FIRE WINDOW TIMER OBSERVATION REGISTER This 10 bit timer is used for the fire window enable duration counter value The observation regist
218. ed 8 bits each for the extra bank 3 for providing the low cost system solution Bank has special signals nlORDO nIOWRO When a user reads writes data from to external latch devices these signals prevent extra address decoding logic ICs These signals are only available at the extra bank 3 When CPU access any of special I O address area 64KB 16 bit offset address specified by SRAM control registers extra bank interface generates a I O read and write signals for the corresponding address area Figure 4 22 23 shows the timing diagram of special I O read write cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1 0 Programmable Bus Width DW 00 Disable bank 10 Half word 01 Byte 11 2 No use 4 2 Chip Selection Set up on nOE Tcos 000 0 cycle 100 4 cycles 001 1 cycles 101 5 cycles 010 2 cycles 110 6 cycles 011 3 cycles 111 7 cycles 7 5 Address Set up Before nECS Tacs 000 0 cycle 100 4 cycles 001 1 cycles 101 5 cycles 010 2 cycles 110 6 cycles 011 cycles 111 7 cycles 10 8 Chip Selection Hold on nOE Tcoh 000 0 cycles 100 4 cycles 001 1 cycles 101 5 cycles 010 2 cycles 110 6 cycles 011 cycles 111 7 cycles 13 11 Access Cycles nOE Low Time Tacc 000 Not used 100 5 cycles 001 2 cycles 101 6 cycles 010 cycles 110 7 cycles 011 4 cycles 111 8 cycles 22 14 Start Address of Extra Bank n
219. ed Mode Selection 0 Normal mode operation 1 Infra red Tx Rx mode Figure 11 5 UART Line Control Register ULCONO 1 2 UART Control Register There are two identical UART control registers UCONO 1 2 in the UART block each for a UART channel UCONn has to be configured after ULCONnh is configured UCONO Oxb004 UART ch 0 control register UCON1 0xb804 UART ch 1 control register UCON2 0 004 UART ch 2 control register 1 0 Receive mode RxM This two bit value determines which function is currently able to read data from the UART receive buffer register RBR The difference between UCONO and UCON 1 should be noted UARTO can only generate GDMA requests can only generate CDMA requests and UART2 cannot generate any DMA requests ELECTRONICS 11 7 UART 2 Rx status interrupt enable 4 3 Transmit mode TxM 6 Send break 7 Loop back bit KS32C65100 RISC MICROPROCESSOR This bit enables the UART to generate an interrupt if an exception break frame error parity error or overrun error occurs during a receive operation 0 Do not generate receive status interrupt 1 Generate receive status interrupt This two bit value determines which function is currently able to write Tx data to the UART transmit buffer registers TBR The difference between UCONO and UCON 1 should be noted UARTO can only generate GDMA requests UART1 can only generate CDMA requests UART2 cannot generate any DMA
220. ed to set current level of each steps in bi polar mode LFCON 0x5818 LF step each control register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 LFCON Each Control Register Figure 16 4 LFCON Register CAUTION When the timer is enabled it begins to decrease from the base value 2 When the timer expires the associated interrupt is generated the base value is reloaded and the timer continues to decrease 3 If anew value is loaded in this register before the timer is expired the timer will keeping counting with the new value 4 In bi polar mode Ifcr 12 and lfpcr 5 0 should all be set to 0 ELECTRONICS 16 5 LF MOTOR KS32C65100 RISC MICROPROCESSOR PHASE STATE AND CURRENT TABLE FOR FULL HALF QUARTER STEP MODE Phase Current State amp Level Each Control Holding State 1 1 IA IB Register Register 1 AB 0 100 100 0 33 33 mE 1 1 66 66 AB 1 33 0095 33 33 1 33 66 cw AB 1 1 0 0 100 0 33 mE A2B 1 0 66 AzB 1 33 0095 33 33 mE 1 33 66 AzB 0 100 100 33 33 1 1 66 66 AzB 0 1 100 33 33 33 1 66 33 CW Az B 0 1 1 100 0 33 0 Az Bz 1 66 0 AzBz 0 1 100 33 33 33 1 66 33 AzBz 0 100 100 33 33 EN 1 1 66 66 1 0 33 0095 33 33 1 1 33 66 2 2 1 0 0 100 0 33 EE A Bz 1 0 66 ABz 1 33 0095 33
221. ed to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 3 26 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write back must not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When R15 is the source register Rd of a register store STR instruction the stored value will be address of the instruction plus 12 RESTRICTION ON THE USE OF BASE REGISTER When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value Example LDR RO R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from main memory The memory manager can signal a proble
222. egister 0x000 R W PWM CON control register 0x0 R W PWM Pre Scaler counter base value 0x00000000 register RIW_ PWIMO cycle time amp observation register_ 000000000 RW PWMO on time amp observation register 0x00000000 RW PWM cycle time amp observation register_ 000000000 R W on time amp observation register 0x00000000 R W Dot counter black register 0x00000000 R W PWM2 cycle time amp observation register 0x00000000 R W PWM on time amp observation register 0x00000000 up ELECTRONICS 1 17 PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR Table 1 2 KS32C65100 Special Function Registers Continued ep m Value VISSR 0Oxa800 ViSStatusregister 00 0x0 vis DstReg OxaB14 image data register 00000 image data register OXXXXX_ 1 18 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PROGRAMMER S MODEL PROGRAMMER S MODEL OVERVIEW KS32C65100 was developed using the advanced ARM7TDMI core designed by advanced RISC machines Ltd PROCESSOR OPERATING STATES From the programmer s point of view the ARM7TDMI can be in one of two states e ARM state which executes 32 bit word aligned ARM instructions THUMB state which operates with 16 bit halfword aligned THUMB instructions In this state the PC uses bit 1 to select between alternate halfword NOTE Transition between these
223. en a command byte is received The bit of PPINTPND is set when nSLCTIN transitions from High to Low in the middle of an ECP forward data transfer handshaking sequence This interrupt is issued if nSLCTIN is Low when nSTROBE is Low or when BUSY is High This event can only be detected when ECP mode is enabled The PPINTPND bit is set when the transmit data register PPDATA can be written in the middle of an ECP reverse data transfer handshake sequence 10 15 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 fff eff cf 0 nSELECTIN Low to High Transition 0 Disable interrupt 1 Enable interrupt 1 nSELECTIN High to Low Transition 0 Disable interrupt 1 Enable interrupt 2 nSTROBE Low to High Transition 0 Disable interrupt 1 Enable interrupt 3 nSTROBE High to Low Transition 0 Disable interrupt 1 Enable interrupt 4 nAUTOFD Low to High Transition 0 Disable interrupt 1 Enable interrupt 5 nAUTOFD High to Low Transition 0 Disable interrupt 1 Enable interrupt 6 nINITIAL Low to High Transition 0 Disable interrupt 1 Enable interrupt 7 nINITIAL High to Low Transition 0 Disable interrupt 1 Enable interrupt 8 Data Received Latched to PPDATA Data Field 0 Disable interrupt 1 Enable interrupt 9 Command Byte Received In PPDATA Data Field 0 Disable interrupt 1 Enable inter
224. er 16 and KS32C65100 RISC MICROPROCESSOR is used as the subroutine link register This receives a copy of R15 when a branch and link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14 svc R14 R14 R14 abt and R14 und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when branch and link instructions are executed within interrupt or exception routines holds the Program Counter PC In ARM state bits 1 0 of R15 are zero and bits contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC is the CPSR Current Program Status Register This contains condition code flags the current mode bits FIQ mode has seven banked registers mapped to R8 14 R8 fig R14 In ARM state many FIQ handlers do not need to save any registers User IRQ Supervisor abort and undefined each have two banked registers mapped to and R14 allowing each of these modes to have a private stack pointer and link registers ARM State General Registers and Program Counter Supervisor ARM State Program Status Register CPSR CPSR CPSR CPSR CPSR M SPSR NSPSH m SPSH abt SPSR A banked register 2 4 Figure 2 3 Register Organization in ARM State 07 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PROGRAMMER S MODEL The THUMB State Register Set The THUMB state
225. er in R1 abs value of RO into ASR R2 RO 31 Get 0 or 1 in R2 depending on sign of RO EOR RO R2 EOR with 1 OxFFFFFFFF if negative SUB R3 RO R2 and ADD 1 SUB 1 to get abs value SUB always sets flag so go amp report division by 0 if necessary BEQ divide by zero abs value of R1 by xoring with OxFFFFFFFF and adding 1 if negative ASR RO R1 31 Get 0 or 1 in depending on sign of R1 EOR R1 RO EOR with 1 OXFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value Save signs 0 1 RO amp R2 for later use in determining sign of quotient amp remainder PUSH RO R2 Justification shift 1 bit at a time until divisor RO value is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes LSR RO R1 1 MOV R2 R3 B FTO just_l LSL R2 1 0 CMP R2 RO BLS just_l MOV RO 0 Set accumulator to 0 B FTO Branch into division loop div_ LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 If successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 R3 Terminate when R2 R3 i e we have just BNE div_ tested subtracting the ones value Now fixup the signs of the quotient RO and remainder R1 POP R2 R3 Get dividend divisor signs back EOR R3 R2 Result sign EOR RO R3 Negate if result sign 1 SUB RO R3 EOR R1 R2
226. er influences the next motor phase interval This feature operates as described above if the bit of register OPERATION 9 MOTOR PHASE LAT OR NOT is set If the bit is reset the value immediately influences the operation You can synchronize the motor and SI using this feature and the SI period adjusting feature When the value of register OPERAION 8 MOTOR HIGH becomes high down counting is carried out from the MOTOR TERM value When the value reaches 1 the MOTOR PHASE 5 0 value used by the previous interrupt is output to each phase The reference counting clock is the one selected by the OPERATION 11 10 SEPARATE SEL value MOTOR INTERRUPT 1 MOTOR PHASEO Figure 21 23 Motor Interrupt Phase Timing Diagram ELECTRONICS 21 17 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR REGISTER READ WRITE NRW 0 MPU Read 1 MPU Write Figure 21 24 Register Read Write Timing Diagram Register Read Write When you want to write the register value from the MPU to the IP you receive the input as shown in Figure 21 24 When writing or reading the value to the register in the sections shown in the diagram the register read write is carried out within 2 cycles 21 18 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR RAM Initialization by Register Read Write SA 5 0 NRW 0 MPU Read 1 MPU Write SD 31 0 MAS 1 0 SW RAM ADDR INIT SA LAT 5 0 SD LAT 31 0 RAM DIN SW RAM
227. er is read only which is of the current value FWTR 0 700 0x000 FWTOR 0x7010 R Fire window timer observation register 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 9 0 Counter Value This data specifies the amount in the counter Figure 19 3 Fire Window Timer Observation Register ELECTRONICS 19 3 PRINT HEAD KS32C65100 RISC MICROPROCESSOR FIRE STROBE DELAY TIMER OBSERVATION REGISTER This 12 bit timer is used for the fire strobe delay duration counter value The phisetvedibitogigietmt srredoborlg taihitim ssftrtaearerrexdd tudelay the fire strobes from the carrier motor logic before sending them to the print head drivers The timers alternate for each fire strobe heces oye pefleo jt tig ek ne f exttbf re terreat lob i generated and the timer will be forced to reload This will prevent the loss of data from excessive delays Registers Offset R W Description Reset Value Address FSDTOOR 0708 strobe delay timer 0 observation register 0 000_ FSDTIOR 006 strobe delay timer 1 observation register Ox000 FSDT2OR 0020 Firestrobedelaytimer2 observation register 0 000_ FSDTSOR Fire strobe delay timer 3 observation register 0 000_ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 0 Counter Value This da
228. eration 1 Data received issue interrupt if enabled in PPINTEN 9 Command Byte Received In PPDATA Data Field 0 Normal operation 1 Command byte received issue interrupt if enabled in PPINTEN 10 Invalid nSELECTIN Transition During ECP 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 11 Transmit Data PPDATA Empty 0 Normal operation 1 PPDATA empty issue interrupt if enabled in PPINTEN Figure 10 9 Parallel Port Event Interrupt Pending Register PPINTPND ELECTRONICS 10 17 KS32C65100 RISC MICROPROCESSOR UART 11 OVERVIEW The KS32C65100 UART Universal Asynchronous Receiver and Transmitter unit provides two independent asynchronous serial I O SIO ports each of which can operate in interrupt based or DMA based mode For example SIO can generate an interrupt or a DMA request for data transfers between CPU and SIO Main features of the 532 65100 UART include programmable baudrates infra red IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data transfers and parity checking Each SIO contains a baud rate generator transmitter receiver a control unit as shown in Figure11 1 The baud rate generator can be clocked by the internal system clock MCLK The transmitter and receiver contain data buffer registers and data shifters Data to be transmitted is written to the transmit buffer register and then copied to the transmit shifter a
229. error shift lt Shiftname gt register or shiftname expression or RRX rotate right one bit with extend lt shiftname gt s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code Examples ADDEQ R2 R4 R5 Ifthe Z flag is set make R2 R5 TEQS R4 3 Test R4 for equality with 3 The S is in fact redundant as the assembler inserts it automatically SUB R4 R5 R7 LSR R2 Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into R4 MOV PC R14 Return from subroutine MOVS PC R14 Return from exception and restore CPSR from SPSR mode ELECTRONICS 3 15 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ TST CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the or SPSR mode to be moved to a general register The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR mode register The MSR instruction also allows an immediate value or register contents to be transferred t
230. erval counter with interrupt Output phase and control signals at same time with counter interrupt RTC Real Time Clock Unit 32 768kHz clock e The data includes second minute hour date day month and year ELECTRONICS KS32C65100 RISC MICROPROCESSOR Parallel Port Interface Controller DMA based or interrupt based operation e Supports IEEE 1284 standard communication modes compatibility mode nibble mode bytes mode and ECP mode Supports ECP protocol with or without Run Length Encoding RLE e Automatic handshaking mode for any forward or reverse protocol with software DMA Ink Head Control Supports both daVinci and Babbage print head e Printing data and fire control Carrier Motor Control Supports two kind of Motor DC and stepper e Motor speed calculation and compensation Support Full Half Quarter step mode for stepper Carrier Position and Fire Control e Fire control up to 2400 dpi and position control by 600 dpi in DC motor mode Fire and position control up to 9600 dpi in step motor mode e Carrier position interrupt for easy position control Paper Motor Control Support two kind of motor driver Uni Bi polar Support Full Half Quarter step mode Derasterizer e 16x16 bit block rotates by 90 270 degree e Rotates 13 half words with selectable direction ELECTRONICS PRODUCT OVERVIEW Laser Printer Video Data Control Cost effective high performance DMA ba
231. eserved 2 Print Synchronization Request 0 Active nPSYNCRQ not received nPSYNCRQ is high 1 Active received is low 4 3 Current PIFC Status 00 Idle 01 Pick up 10 Counting top margin 11 Active printing 5 Currently Selected DMA Queue 0 DMA queue 0 is selected 1 DMA queue 1 is selected Figure 25 4 PDMA and Engine Interface Status Register STATUS ELECTRONICS 25 5 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR VIDEO CONTROL REGISTER Settings in the PIFC video control register VCON control activities of the KS32C65100 printer interface controller during a printing operation including video clock selection and the shift direction of video data VCON 0xa004 Video control register 0 Reserved 1 nPRINT output When VCON 1 is 1 it signals the printer engine that the KS32C65100 is ready to start a print job 2 Print synchronization This bit activates or inactivates nPSYNC signal 3 Video clock inversion When using external a video clock VCLK VCON 3 is 1 the PIFC uses a non inverted external video clock VCLK as its clock Otherwise it uses the inverted external VCLK The VCLK selection VCLK depends on the setting in PCON 3 2 4 Video data shift direction In video data transmission if VCON 4 is 1 the shift direction of video data in the shift register is L SB first Otherwise the shift direction is MSB first 5 S
232. ess 31 Word Address Lower Address Most significant byte is at lowest address Word is addressed by byte address of most signficant byte Figure 2 1 Big Endian Addresses of Bytes within Words The data locations in the external memory are different with Figure 2 1 in the KS32C6200 Please refer to the chapter 4 system manager LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 Higher Address 31 Word Address Lower Address Most significant byte is at lowest address Word is addressed by byte address of least signficant byte Figure 2 2 Little Endian Addresses of Bytes within Words 2 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PROGRAMMER S MODEL INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state Data Types supports byte 8 bit half word 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries OPERATING MODES ARM7TDMI supports seven modes of operation e User usr The normal ARM program execution state e FIQ fiq Designed to support a data transfer or channel process e irq Used for general purpose interrupt handling e Supervisor svc Protected mode for
233. euing enable bit 0 1 run 2 Case 2 Banki Bank0 gt Bank1 Bank0 Bank1 1 Set HDSAR1 HDTCR 2 Set HDCON with 0x1010f81 match interrupt pending enable HDMA interrupt enable auto load enable alternate enable select bank1 for current queuing bank enable queuing enable bit 0 1 run HDMA 3 Case 2 Bank 1 1 Set HDSARO HDMARO HDSAR1 HDTCR 2 Set HDCON with 0x1000781 match interrupt pending enable HDMA interrupt enable auto load enable alternate enable select bankO for current queuing bank enable queuing enable bit 1 run ELECTRONICS 20 5 KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR 2 1 IMAGE PROCESSOR OVERVIEW Sensor In ADC Module CPU I F Module Register ADC Value 7 0 AD lock ee Shading Factor 7 0 SRAM 2 56K SI Shading Correction CLK Module RLED Shade Corrected Value 7 0 GLED BLED SI Interrupt Gamma Correction SRAM 0 256K SEN SO R Module CTRL Gamma Corrected Value 7 0 Nor Mag Red Reduction Magnification Module R M Value 7 0 LAT EDF Binarization Module SRAM 2 56K LAT EDF Binary Value 7 0 Motor Interrupt Motor Phase 5 0 DMA ACK DMA REQ Data 31 0 DMA Interface Module Figure 21 1 Image Processor Block Diagram ELECTRONICS 21 1 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR These modules adjust and convert the input data into data that can be outpu
234. f this bit is set to 1 DMA operates from memory to peripheral IP If this bit is cleared to 0 DMA operates from peripheral to memory 13 12 Transfer width This determines the transfer data width to be byte 8 bit halfword 16 bit or word 32 bit If transfer length is a byte source destination address will be increased decreased by 1 If it is halfword then the address will change by 2 If it is a word the address will increase decrease by 4 It s important that the transfer width is not the size of a physical data bus The size of a physical data bus is determined by SMR configurations ELECTRONICS 9 5 DMA KS32C65100 RISC MICROPROCESSOR 14 Continuous mode This bit specifies whether the operation will hold the system bus or not until the count value is 0 Therefore this bit must be carefully used for the whole operation time not to exceed the appropriate interval ex DRAM Refresh 15 Demand mode If this bit is set during the DMA operation DMA never goes to the idle state Altogether the external device transfers receives the amount of data which it wants to transfer receive The amount of data depends on how long the REQ signal is active NOTE All control bits have to be configured independently and carefully External I O related bits have no effect because nXDREQ is not connected to 9 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR DMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1
235. f whether the exception was entered from ARM or Thumb state an IRQ handler should return from the interrupt by executing SUBS PC R14 4 Abort An abort indicates that the current memory access cannot be completed It can be signalled by the external abort input ARM7TDMI checks for the abort exception during memory access cycles There are two types of abort e Prefetch abort occurs during an instruction prefetch e Data abort occurs during a data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken until the instruction reaches the head of the pipeline If the instruction is not executed for example because a branch occurs while it is in the pipeline the abort does not take place If a data abort occurs the action taken depends on the instruction type e Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this e The swap instruction SWP is aborted as though it had not been executed e Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data i e it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM ins
236. fer operations should be used instead The action of TEQP in the ARM7TDMI is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode INSTRUCTION CYCLE TIMES Data processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Normal data processing Data processing with register specified shift 15 1I Data processing with PC written 25 1 Data processing with register specified shift and written 25 1 1 NOTE 5 are defined sequential S cycle non sequencial N cycle and internal I cycle respectively 07 3 14 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX MOV MVN single operand instructions lt opcode gt cond S Rd lt Op2 gt CMP CMN TEQ TST instructions which do not produce a result lt opcode gt cond Rn lt Op2 gt AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt Op2 gt lt Op2 gt Rm lt shift gt or lt expression gt cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number lt gt If this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an
237. ger s DRAM control block generates appropriate DRAM control signals such as nRAS nCAS Address and Data e compensates for differences in bus width for data flowing between the external memory bus and the internal data bus Supports big endian mode with efficiency for most graphic device drivers refer to Figure 4 5 SYSTEM MANAGER REGISTERS SMR The KS32C65100 microcontroller has register files named Special Function Register SFR for keeping the system control information for the system manager cache Internal RAM DMA UART blocks and so on The SFR has System Manager Register files SMR for the configuration of external memory maps such as DRAM SRAM ROM and extra I O control Programmers can specify the memory type external bus width access cycles necessary control signal s timing eg nRAS and nCAS etc memory bank location and memory bank size of each bank which has a very configurable address spacing by utilizing the SMR The SMR also provide or accept the features such as control signals address and data that are required by external I O devices during normal system operation The SMR is constituted of 11 registers to control one ROM bank two SRAM banks two DRAM banks four extra I O banks and a DRAM Refresh Control Register system configuration register The KS32C65100 provides up to 32M bytes of address space and each bank provides up to 4M half word of memory space because the KS32C65100 has 22 add
238. gnal may be de asserted after checking nXDACK to be asserted ELECTRONICS 9 3 DMA KS32C65100 RISC MICROPROCESSOR Block Mode nDACK Figure 9 3 External DAM Requests 2 Block Mode The assertion of only one DMA request nXDREQ or internal request causes the entire data which is set in control registers to be transmitted DMA transfer will be completed when the counter reaches zero The nXDREQ signal may be de asserted after checking nXDACK to be asserted Demand Mode nXDREQ A nXDACK Figure 9 4 External DMA Requests 2 Demand Mode The amount of data that DMA transfers depends on how long the DMA request input nXDREQ is held active In the demand mode the DMA GDMA only continues to transfer data while the DMA request input nXDREQ is held active 9 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR DMA GENERAL DMA CONTROL REGISTER DMACON 1 0x9000 GDMA control register 0x0000 GDMA Control Register Description 0 Run enable disable The DMA operation starts When you set this bit to 1 To stop DMA you must clear this bit to 0 To control only this bit use the address 0x9020 By using 0x9020 the other values in the control register will not be affected 1 BUSY status When starts this read only status bit is automatically set to 1 When DMA is in an idle state this bit is 0 3 2 GDMA mode selection Four sources can initiate a DMA operation software memory to memory th
239. gnals the image processor operates and the image handling shading binarization etc starts If you want to stop the image processor while it is working clear the VER RATIO s value to 0 For restarting the image processor writing the VER RATIO s value 1 RESTART This register bit can be used for synchronization during automatic operation If there isn t a bit that fulfills this purpose the SI signal can be triggered without regard to the KS32C65100 s internal operations when power is on and the brightness of Line 1 s first pixel can be irregular To prevent this problem this register bit is set to 1 after the power is turned on so that the counting restarts from this point for synchronicity 2 SHAD ACQ Shading acquisition 3 SW MODE When initializing or reading the internal SRAM this value must be set to 1 The register s read write signal can be applied as the RAM read write signal only when this value is high 4 SWING If the same value is maintained for a long time during error diffusion the same pattern is repeated and can have an optically unsatisfactory result To prevent this problem it is necessary to swing the pixel values a little bit at the outline An algorithm is applied when this bit is set to 1 5 LAT EDF 0 Local adaptive threshold for text mode 1 Error diffusion for photo mode 6 PAGE CLK This signal is for resetting the horizontal reduction counter It carries out trigge
240. he System Register Address Configuration Register SYSCFG and its contents indicate the start base point address of SFR If the initial value is 1001h SYSCFG is mapped to the virtual address 01000000h SYSCFG 0x0000 Special function register start address 0x1001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 W C S 0 Stall Enable ST 0 Disable It s recommended for faster operation 1 Enable Insert an internal wait inside the core logic when non sequential memory accesses occur 1 Cache Enabl CE 0 Cache operation disable 1 Cache operation enable 2 Write Buffer Enable WE 0 Write buffer operation disable 1 Write buffer operation enable 12 04 SYSCFG Address SFRs Start Address The resolution is 64KB if you want to place the start address at 1800000h Setting Value 1800000h 10000h 15 13 Reserved Bits User should fix 000 Figure 4 3 Special Function Register Address Configuration Register 4 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER Start Address The SYSCFG 12 04 bits indicate the start address 24 16 SFRs As SYSCFG is locating at the bottom of the Special Function Register SFR files SYSCFG s location is same as the start address SFRs Programmers can allocate SFRs to arbitrary locations by using the SYSCFG You are recommended not to change the SYSCFG in mid operation once it has been configured
241. hich are registers and write back address to R2 Store the halfword in at R14 14 but don t write back Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 Conditionally load R11 with the sign extended contents of the halfword address contained in RO Generate PC relative offset to address FRED Store the halfword in R5 at address FRED 3 35 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load LDM or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data around main memory THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can also transfer to and from the user bank see below The register list is a 16 bit field in the instruction with each bit corresponding to a register 1 in bit O of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the regi
242. ided by 40 is cnt 40 and RSTCLK the frequency divided logic in the CLKSAV unit is the reset filtering logic SMCLK is MCLK in normal mode or cnt 40 in sleeping mode RSTCLK reset filtering logic Enable Figure 23 1 Clock Save Block Diagram REGISTERS CLKSAVCON 0x1800 CLKSAV control register W PLLCON ox1804 w control register 0x00000 ELECTRONICS 23 1 CLOCK SAVE amp PLL CONTROL KS32C65100 RISC MICROPROCESSOR CLKSAVCON REGISTER The CLKSAVCON register is comprised of the CLKSAVE CLKSAV Enable bit 0 which decides whether or not to enable clock saving for the peripherals 0 CLKSAVE CLKSAVE Enable Bit 0 Disble 1 Enable 1 31 Reserved Figure 23 2 CLKSAVCON PLLCON REGISTER PLLCON controls PLL and decides whether to use the PLL generated clock or the external clock as the system clock 1 0 S Post Scaler 9 2 M Main Divider 15 10 P Pre Divider 16 CLKSEL 0 Use external clock as MCLK 1 Use PLL clock out as MCLK Figure 23 3 PLLCON The frequency of the PLL generated clock is found by the following formula PLL clock out MHz M 8 external clock P 2 2 S If the external clock is 20MHz and 0 P 0 and S 0 the PLL clock out is 8 20 2 1 80MHz 23 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CLOCK SAVE amp PLL CONTROL System Clock Calculation Method when using the Frequency Synthesizer PLL Output Frequency Equation Fout
243. ied Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero 2 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR 10001 10010 10011 10111 11011 11111 System R7 RO R14 RO LR SP PC CPSR PC CPSR Table 2 1 PSR Mode bit Values PROGRAMMER S MODEL Visible THUMB State Registers Visible ARM State Registers 10000 User R7 RO 14 0 LR SP PC CPSR PC CPSR Undefined ELECTRONICS R7 RO LR fiq PC CPSR SPSR fiq R7 RO LR irq SP irq PC CPSR SPSR irq R7 RO LR svc SP svc PC CPSR SPSR svc R7 RO LR abt SP PC CPSR SPSR abt R7 RO LR und SP und PC CPSR SPSR und R7 RO 14 fiq R8 PC CPSR SPSR fiq 12 0 R14 irq R13 irq PC CPSR SPSR irq 12 0 R14 svc R13 PC CPSR SPSR svc 12 0 R14 abt R13 abt PC CPSR SPSR abt R12 RO R14 und R13 und PC CPSR 2 9 PROGRAMMER S MODEL KS32C65100 RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be handled the current processor state must be preserved so that the original
244. igure 11 7 UART Status Register USTATO 1 2 ELECTRONICS 11 11 UART KS32C65100 RISC MICROPROCESSOR UART Transmit Buffer Register There are two identical UART transmit buffer registers TBR in the UART block for the two SIO channels each of which contains an 8 bit data value to be transmitted over the SIO channel In DMA based transmit mode the address of the transmit buffer register should be set into the DMA destination address register as the destination of the DMA channel UTXBUFO Oxb00c UART ch 0 transmit buffer register UTXBUF1 Oxb80c UART ch 1 transmit buffer register UTXBUF2 UART ch 2 transmit buffer register 7 0 Transmit data This field contains the data to be transmitted by the corresponding SIO channel When this register is written the transmit buffer register empty bit in the status register USTAT 6 should be 0 This prevents overwriting transmit data that may already be present in the TBR Whenever the TBR is written with new value the transmit register emptybit USTAT 6 is automatically cleared to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514 131211109 8 7 6 5 4 3 2 1 0 UTXBUFO 1 2 Transmit Data 7 0 Transmit Data for UART Figure 11 8 UART Transmit Buffer Register UTXBUFO 1 2 11 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART UART Receive Buffer Register There are two identical UART receive buffer registers RBR in the UART block for the two SIO channels each of which co
245. in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 28 27 22 21 20 19 16 15 12 11 15 12 11 8 3 0 Operand Register 19 16 Destination Register 21 Set Condition Set 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs Rn is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 s complement or unsigned integers The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplication of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38 If the Operands Are Interpreted as Signed Operand A has the value 10 operand B has the value 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands Are Inter
246. ing sequence performs a mode change MRS RO CPSR Take a copy of the CPSR BIC RO RO 0x1F Clear the mode bits ORR RO RO new_mode Select new mode MSR CPSR RO Write back the modified CPSR When the aim is simply to change the condition code flags in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR_flg 0xFO000000 Set all the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as sequential S cycle 3 18 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX e MRS transfer PSR contents to a register MRS conq Rd lt psr gt e MSR transfer register contents to PSR MSR cond lt psr gt Rm e MSR transfer register contents to PSR flag bits only MSR cond lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp V flags respectively MSR transfer immediate value to PSR flag bits only lt psrf gt lt expression gt The expression should symbolise 32 bit value of which the most significant four bits are written to the N Z C and V flags respectively Key
247. ion power 5V switch Pint 3 is TESTO 1 ground Pin 4 ICE TDI ground When ICE non connection Pin1 3 is TESTO 1 VDD Pin 4 ICE TDI open When ICE connection NOTE The grayed rows are the default settings of the evaluation board ELECTRONICS 26 7 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR GND GAINO 802 900 S0c 704 HIC XO VDD nXDREQ GIPG 02 002 PLLFILTER 61 881 vst ESL nlORD GOPA9 EOL 291 R KS32C65100 Em 40301 nPHGA13 GOPB12 nPHGA12 GOPB1 1 nPHGA11 GOPB10 nPHGA10 GOPB9 COO NO GOPBG nPHGA6 GOPB5 PHG 4 n GND GOPB3 nPHGA3 GOPB2 nPHGA2 GOPB1 nPHGA1 GOPBO PHOET GIOP11 PHOES GIOP13 PHOEA GIOP14 PHOES GIOP15 7 GND PHOE10 GIOP20 t et Rs H LSS 26 8 ONVO INVO 2NVO lHA9 SSAVO OX 218 CI nEINTO GIP3 nEINT1 GIP4 nEINT2 GIP5 VSS nECSO nECS1 nECS2 GOPA8 3VDD nPHGA13 GOPB12 nPHGA12 GOPB11 nPHGA11 GOPB10 nPHGA10 GOPB9 nPHGA9 GOPB8 nPHGA8 GOP
248. ion Interrupt Register PIR CPCR The carrier position is updated based on the carrier movement of 1 600 inch PSPR The fire strobe control logic requires two conditions to be met before it will generate fire strobe to print logic A non zero value must be loaded into the print slice counter register The carrier position must match the value in the print start position register Once the two requirements have been met the logic will begin producing fire strobes after 1 75 inch PSCR This value is decreased once for each fire strobe that is generated PIR When outputs of carrier position counter become same as the value of this register position interrupt request occurs PSCR 0x682c RW Print slice counter register 0x0000 PIR 0 680 Position interrupt register Oxfftt R W R W R W R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Count Value of Each Register Figure 18 2 CR Count Register ELECTRONICS 18 3 CR FIRE KS32C65100 RISC MICROPROCESSOR SUGGESTIONS FOR F W DESIGN When CR Motor is Stopped Mustreset BASIC timer and PRESTEP timer s RUN bit to O e Must reset the position block enable bit bit 0 of PFCR 0x6820 to 0 When Restarting the CR Motor Must write new or previous values in the BASIC timer base registers Must write new or previous values in the PRESTEP timer base register Must set the posit
249. ion block enable bit bit 0 of PFCR 0x6820 to 1 e Must set the BASIC timer and PRESTEP timer s RUN bit to 1 In other words before starting Re RUN after stopping the BASIC timer you must Rewrite the BASIC timer base register and PRESTEP timer base register values and Reset the position block enable bit before setting to reduce the error in carrier motor position To reduce location errors you should fix the position amp fire control register s bit 6 position counter clock to 1 adjust the position and fire pre scaler values and set the fire DPI The value of position amp fire control register s bit 6 should not be changed during system operation Example of Position DPI Setting for Step Motor Mode Position DPI Pre scaler Value PFCR 20 15 300 DPI 64 19200 300 600 DPI 32 19200 600 1200 DPI 16 19200 1200 Example of Fire DPI Setting DC Motor Mode Step Motor Mode Prescaler value PFCR 14 7 DPI mode setting value Prescaler value PFCR 14 7 150 DPI 16 2400 150 000 other case 128 19200 150 300 DPI 8 2400 300 001 64 19200 300 1200 DPI 2 2400 1200 16 19200 1200 2400 DPI 1 2400 2400 8 19200 2400 600 DPI 4 2400 600 32 19200 600 18 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINT HEAD PRINT HEAD OVERVIEW This module performs the following functions e Fire pulse generation e DMA request for reading data e Three 32 bit dot counters for color e One
250. ion is a LDM then SPSR mode is transferred to CPSR at the same time as R15 is loaded STM with R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the user bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the user bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked register during the following cycle inserting a dummy instruction such as MOV RO after the LDM will ensure safety USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 39 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is written back at the end of the second cycle of the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the b
251. ions move a shifted value between Lo registers The THUMB assembler syntax is shown in Table 3 8 NOTE All instructions in this group set the CPSR condition codes Table 3 8 Summary of Format 1 Instructions OP THUMB Assembler _ ARM Equivalent Action LSL Rd Rs Offset5 MOVS Rd Rs LSL Shift Rs left by a 5 bit immediate value and Offset5 store the result in Rd 01 LSR Rad Rs Offset5 MOVS Rd Rs LSR Perform logical shift right on Rs by a 5 bit Offset5 immediate value and store the result in Rd 10 ASR Rd Rs Offset5 MOVS Rd Rs ASR Perform arithmetic shift right on Rs by a 5 bit Offset5 immediate value and store the result in Rd INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Setcondition codes on the result ELECTRONICS 3 63 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 2 ADD SUBTRACT 65 3 2 0 14 11 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Value 9 Opcode 0 Add 1 SUB 10 Immediate 0 Register operand 1 Immediate operand Figure 3 31 Format 2 OPERATION These instructions allow the contents of a Lo register or a 3 bit immediate value to b
252. is immediately causes the KS32C65100 to drive the BUSY level high If you set the error cycle bit when a compatibility mode handshaking sequence is in progress PPSTAT 5 will remain set to 1 beyond the end of the current cycle The error cycle bit does not affect the nACK pulse if it is already active but it will prevent an nACK pulse if it is about to be generated When PPCON 5 is 1 software set or clear the parallel port status register control bits PPSTATR 0 nFAULT control PPSTAT 1 SELECT control and PPSTAT 2 PERROR control When PPCON 5 is cleared to 0 the parallel port interface controller generates an nACK pulse and negates BUSY to conclude the error cycle The parallel port data bus output enable bit performs two functions 1 It controls the state of the tri state output drivers and 2 It qualifies the latching of data from the output drivers into the parallel port interface register O s data field PPDATA 7 0 When PPCON 6 is 0 parallel port data bus output are disabled This allows data to be latched into the PPDATA data field When PPCONJ6 is 1 PPD output are enabled and data is prevented from being latched into the PPDATA data field In this frozen state the data field is unaffected by transitions of nSTROBE The setting of the abort bit PPCON 7 affects the operation of the data bus output enable bit PPCON 6 If PPCON 7 is 1 nSELECTIN must remain high to allov PPCON 6 to be set o
253. ister PPSTAT to detect and control the logic levels on all parallel port signal pins software can control all parallel port operations including all four kinds of parallel port communications protocols supported by KS32C65100 refer to IEEE 1284 standard for operation control In addition it also gives software the flexibility to adapt to new and revised protocols Compatibility Hardware Handshaking Mode Compatibility hardware handshaking mode is enabled by setting the PPCON s mode selection bits as 01 i e PPCON 3 2 01 In this mode hardware generates all handshaking signals needed to implement compatibility mode parallel port communication protocol When this mode is enabled the PPIC automatically generates a BUSY signal on receiving the leading edge of nSTROBE from the host and latches the logic levels on PPD7 PPDO pins into PPDATA register The PPIC then waits for nSTROBE to negate and the PPDATA s data field to be read After the PPDATA is read the PPIC asserts nACK for the duration specified in the Ack Width Register PPACKWTH and then negates the nACK and BUSY signal to conclude the data transfer as shown in Figure 10 1 NOTE Since the initial value of the BUSY control bit in the PPSTAT register PPSTAT 3 is 1 after system reset the BUSY output has a high logic level and handshaking is disabled To enable hardware handshaking in this mode the BUSY control bit PPSTAT 3 must be cleared by software beforehand nSTROBE
254. ister 0 OxXXXX DRAST1 0x4804 R W 16 bits of derasterizer data register 1 OxXXXX DRAST14 0x4838 R W 16 bits of derasterizer data register 14 OxXXXX DRAST15 0x483c R W 16 bits of derasterizer data register 15 OxXXXX NOTE When h 15 0 is written and v 15 0 is read the address DRASTO DRAST15 is used ROTATION To rotate image data programmers should fill image data into the 16 x 16 bit register array from DRASTO to DRAST15 horizontally The image data made by reading the 16x16 has rotated the image The rotation direction depends on the shift control register SFTCON 3 When 5 is 0 read image data is 90 degrees rotated and when 5 is set to 1 it is rotated 270 degrees e Write h15 DRASTO DRAST15 e Read 90 degrees horizontal direction vO gt v15 vertical direction MSB gt h15 LSB ho 270 degrees horizontal direction v15 vO vertical direction MSB LSB gt h15 ELECTRONICS 6 1 DERASTERIZER KS32C65100 RISC MICROPROCESSOR SHIFT CONTROL REGISTER SFTCON Shift Control Register SFTCON specifies the rotation degree of the derasterizer data SFTCON 0x5004 Shift control register 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 NN 3 Direction of Derasterizer 0 90 degree 1 270 degree Figure 6 1 Shift Control Register At First DRASTO is Written 2 DRAST1 is Written
255. ith the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Lee Kiheung Eup Yongin City Kyungi Do Korea Box 37 Suwon 449 900 TEL 02 760 6530 0331 209 6530 FAX 02 760 6547 Home Page URL Http AWwww samsungsemi com Printed in the Republic of Korea Preface The KS32C65100 RISC Microprocessor User s Manual is designed for application designers and programmers who are using the KS32C65100 RISC Microprocessor for application development It is organized in two main parts Programming Model Part II Hardware Descriptions Part contains software related information to familiarize you with the RISC Microprocessor s architecture programming model instruction set memory structure and special function registers It has five chapters Chapter 1 Product Overview Chapter 4 Address Spaces Chapter 2 Programmer s Model Chapter 5 Special Function Registers Chapter 3 Instruction Set Chapter 1 Product Overview is a high level introduction to KS17C80064 C8001 3 F80013 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Programmer s Model describes the important feature of the KS17C80064 C8001 3 F80013 programming environment Chapter 3 Instruction Set describes the features and conventions of the instruction set used for all KS17 series RISC Microprocessors Several summary t
256. ither a 12 bit unsigned binary immediate value in the instruction or a second register possibly shifted in some way The offset may be added to U 1 or subtracted from 0 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base 1 or the old base value may be 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed data transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word B 0 between an ARM7TDMI register and memory The action of LDR B and STR
257. ivalent ARM instruction as shown in Table 3 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction THE BX INSTRUCTION BX performs a branch to a routine whose start address is specified in a Lo or Hi register 0 of the address determines the processor state on entry to the routine Bit02 0 Causes the processor to enter ARM state Bit 0 1 Causes the processor to enter THUMB state NOTE The action of 1 for this instruction is undefined and should be used ELECTRONICS 3 69 ARM INSTRUCTION SET Examples Hi Register Operations ADD PC R5 CMP R4 R12 MOV R15 R14 Branch and Exchange ADR R1 outof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outof THUMB USING R15 AS AN OPERAND KS32C65100 RISC MICROPROCESSOR PC PC R5 but don t set the condition codes Set the condition codes on the result of R4 R12 Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outofTHUMB into R1 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUMB state is entered ie ARM state here Now processing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit 0 cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution 3 70
258. l Data n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 HftReg Halftone Image Data Refln 15 0 Reference Data This 16 bit field contains two 8 bit reference data to be compared with corresponding source pixels data PixIn 15 0 Source Image Pixel Data This 16 bit field contains two 8 bit source image pixel data to be processed HftReg 15 0 Halftone Image Data This 16 bit field contains 16 halftone image pixel data generated by the halftoning operation Figure 26 7 VIS Data Registers SrcReg DstReg 26 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PWM TIMER CONTROL PWM TIMER CONTROL INTRODUCTION The PWM control is composed of the following one 8 bit pre scaler one 16 bit down counter two 4 bit pre scalers and 16 bit down counter e The 16 bit counter is either enabled RUN or disabled STOP according to the each control register s bit selection The PWM output signal and the on off time within its period are decided according to the Cycle Time base value and On Time base value If the On Time base value is the same or larger than the Cycle Time base value when the counter is enabled the PWM output signal maintains On status e If anew cycle time or on time value is written the PWM output is generated according to the modified value starting from the next cycle PWM Counter Clock MCLK pre scaler value 1 Cycle time pulse width Cycle time v
259. l port data bus PPD 7 0 when the strobe input from the host nSTROBE transitions from high to low with the PPCON 6 clear The PPCON 6 bit determines the forward or reverse dataflow direction of the parallel port When written the value in this field determines the logic level on the parallel port bus lines PPD 7 0 when the PPCON 6 is set 8 ECP Mode Command Byte Indicator During ECP forward data transfers reading this bit gives the logic level of nAUTOFD which indicates the data in PPDATA 7 0 is a data byte or a command byte when the following two conditions are met 1 nSTROBE has transitioned from high level to low level 2 the data bus output enable bit in the parallel port control register PPCON 6 is 0 During ECP reverse data transfers writing this bit defines the logic level of the BUSY pin which indicates whether the data written to PPDATA 7 0 is a data byte or a command byte when the data bus output enable bit in the parallel port control register PPCON 6 is 1 0 Command byte in PPDATA 7 0 1 Data byte in PPDATA 7 0 Figure 10 4 Parallel Port Data Register ELECTRONICS 10 5 PARALLEL PORT INTERFACE KS32C65100 RISC MICROPROCESSOR PARALLEL PORT STATUS REGISTER The parallel port status register PPSTAT contains eleven bits to control the parallel port interface signals These eleven bits consist of four read only bits that are used to read the logic level of the host input pins two read
260. language becomes BEQ for Branch if Equal which means the branch will only be taken if the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary Coe Fas ignored ELECTRONICS 3 3 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the program counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or instructions 3 0 Operand Register If bit 0 of Rn 1 subsequenct instructions decoded as THUMB instructions If bit 0 of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute where
261. lculated using the magnification ratio For a 12596 magnification the magnification ratio is 0 25 and the register value is found in the following manner Register Value Magnification Ratio x 256 To find the number of magnified pixels use the following formula Re ale x Total number of line input pixels number of added pixels Except if the value behind the decimal point of the formula s result is truncated The sum of this value and the number of originally input pixels give the number of actually magnified pixels For example for a 13796 magnification the magnification ratio register setting value for 1720 pixels line is Magnification Register Value 0 37 x 256 94 72 SO you can set 94 to the register The number of magnified pixels is the sum of the original value 1720 and the number of added pixels 631 Since in x x 1720 631 56 0 56 is truncated the number of added pixels from the magnification is 631 ELECTRONICS 21 13 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR DIGITAL SHADING CORRECTION This feature is for adjusting the sensor s non uniform illumination characteristics using the 16x8 divider In this controller the ratio between the value with 8 bit steps and the actual value of white is found and the ratio is used for conversion during scanning For example if we call the value from white pad W the value from black pad B and the actual value from scanning X the digital shading corrected value Y
262. le divider The divided by value therefore ranges from 0 to 255 Then the output value of the tone counter is divided by two producing 50 duty tone output signal A reset clears the TONDATA value to 00h The tone frequency is therefore calculated based on the tone data value as follows MCLK Prescaler 1 128 ToneData 2 TONDATA 0x3804 Tone generator data register OxOff 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211109 8 7 6 5 4 3 2 1 0 7 0 Tone Counter Data 8 bit tone counter data value 8 tone Generator Control 0 Clear counters and reset tone output 1 Generate tone Figure 12 2 Tone Data Register TONDATA 12 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR WATCH DOG TIMER WATCHDOG TIMER OVERVIEW The KS32C65100 Watchdog Timer is used to resume controller operation when it is disturbed due to noise or other kinds of system errors or malfunctions It can be used as a normal interval timer to request interrupt services also you can set the prescaler value initial value in TCR Figure 13 3 Clock Divider Interrupt 1 16 1 32 8 Bit Prescaler a nRSTO Pin 1 64 down counter 1 1 Prescale value 1 128 Enable Enable Enable Disable Disable Disable WTCON 4 3 WTCON 5 WTCON 2 0 WTCON O0 Figure 13 1 Watchdog Timer ELECTRONICS 13 1 WATCH DOG TIMER KS32C65100 RISC MICROPROCESSOR WATCHDOG TIMER COUNTER REGISTERS The watchdog timer counter registe
263. m carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 32 Bit 31 of Rm is again used as the carry output and each bit of operand 2 is also equal to bit 31 of Rm The result is therefore all ones or all zeros according to the value of bit 31 of Rm ELECTRONICS 3 11 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR Rotate right ROR operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example ROR 5 is shown in Figure 3 9 The form of the shift field which might be expected to give ROR 0 is used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right 31 1 0 Contents of Rm C carry out n Value of Operand 2 Figure 3 10 Rotate Right Extended 3 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount Rs can be any general register other than R15
264. m by taking the processor ABORT input HIGH whereupon the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S 1N 11 and LDR PC take 25 2N 11 incremental cycles where S and I are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 27 ARM INSTRUCTION SET ASSEMBLER SYNTAX KS32C65100 RISC MICROPROCESSOR LDR STR cond Rd lt Address gt where LDR STR Rd Rn and Rm Address can be 1 shift 3 28 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 If B is present then byte transfer otherwise word transfer If T is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is not allowed when a pre indexed addressing mode is specified or implied An expression evaluating to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining In this case base write back should not be specified An expression which generates an address The assem
265. mmdiate value to PSR flag bits only 2827 262524 2322 21 12 11 22 Destination PSR 0 CPSR 12 SPSR current mode 25 Immediate Operand 0 Source operand is a register 12 SPSR current mode 11 0 Source Operand 00000000 3 Source register 11 4 Source operand is an immediate value 00000000 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Confition Field Figure 3 11 PSR Transfer ELECTRONICS 3 17 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM7TDMI N Z C V I F T amp M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM7TDMI programs and future processors the following rules should be observed e reserved bits should be preserved when changing the value in PSR Programs should not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the appropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction Examples The follow
266. mprised of Enable bit 0 which controls the write disable of the BCD registers RCLK RTC Clock bit1 CNTSEL Counter Select bit 2 and CLKRST Clock Reset bit 3 for testing Bit RTCE controls all interfaces between the CPU and the RTC so it should be set to 1 in an initialization routine to enable data transfer after a system reset Instead of working BCD with 1Hz bit RCLK enables the operation of BCD counters with an external clock which is entered through the pin RXI to the test BCD counters Bit CNTSEL converts the dependent operation of BCD counters into independent counters for testing CLKRST resets the frequency divided logic in the RTC unit RTCCON 0 840 RTC control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 44 0 RTCE RTC R W Enable Bit 0 Disable 1 Enable 1 RCLK BCD Clock Selection Bit 0 RXI 215 Divied CLK 1 2 CNTSEL BCD Count Selection 0 Merge BCD Counters 1 Seperate BCD Counters 3 CLKRST RTC Clock Counter Reset Bit 0 No reset 1 Reset Figure 22 2 RTCCON Register ELECTRONICS 22 3 REAL TIME CLOCK KS32C65100 RISC MICROPROCESSOR BCDSEC COUNTER REGISTER BCD count register for seconds BCDSEC 0xc870 RTC second register 6 0 Second Counting Value 0 59 Figure 22 3 BCDSEC Counter Register BCDMIN COUNTER REGISTER BCD count register for minutes BCDMIN 0xc874 RTC minute regi
267. n in Table 3 19 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD R2 PC 572 R2 PC 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212 SP R13 212 but don t set the condition codes Note that the THUMB opcode will contain 53 as the Word 8 value ELECTRONICS 3 81 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 13 ADD OFFSET TO STACK POINTER 10 15 14 13 12 9 8 7 6 0 6 0 7 bit Immediate Value 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 3 42 Format 13 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 3 20 The ADD SP Instructions S THUMB Assembler __ARM Equivalent Acn 0 ADD SP ADD R13 R13 imm Add Imm to the stack pointer SP ADD SP Imm SUB R13 R13 Imm Add Imm to the stack pointer SP NOTE The offset specified by zzlmm can be up to 508 but must be word aligned i e with bits 1 0 set to 0 since the assembler converts lmm to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM ins
268. n ratio is not as dense During reduction all signals transmitted to the sensor and ADC are generated but the data isn t accepted You need to use the reduction ratio register for vertical reduction You can find the register value using the following formula Register Value Reduction Ratio x 128 The register s initialization value is 8 H80 and the value signifies a mode that does not carry out reduction 21 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR Magnification The design of this product is such that the reduction feature described above is also used for image magnification This feature is to magnify and print a 300DPI image using a 200DPI level sensor do so first increase the pixel clock PIX CLK speed to twice the original Since the internal PIX CLK INNER PIX CLK is made using the reduction feature you can have a maximum velocity MSLT of approximately 2ms for 33MHz in magnification In other words you are guaranteeing the time for one PIX CLK to be generated between the PIX CLKs and allowing a new PIX CLK to be generated there according to the register value The timing diagram is given below Whin SUM 8 0 40 h100 h040 h080 hoCo h100 h040 MAG PIX CLK INNER PIX CLK magnified PIX Figure 21 18 Magnification Pixel Clock Timing Diagram To carry out magnification you must select the magnification bit MAG 1 and record the actual number of pixels ca
269. n the PC is loaded with the exception vector address Action on Leaving an Exception On completion the exception handler 1 Moves the link register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTE An explicit switch back to THUMB state is never needed since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception 2 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PROGRAMMER S MODEL Exception Entry Exit Summary Table 2 2 summarises the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14 x yom FIO SUBS PC fi 4 PC 4 PC 2 2 IRQ SUBSPCRI4 ig 4 4 1 PC 2 2 SUBS PC R14_abt 4 PC 2 1 SUBSPO 8 8 2 RESET 4 n A NOTES 1 Where is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority 3 Where PC is the address of the Load or Store instruction
270. n the PPIC s buffer while reverse ECP mode is operating When the run length count is 0 this bit specifies whether to send the RLE count to PPIC during ECP with RLE reverse data transfers If this bit is set to 1 then the count will be sent but if otherwise it is not sent This bit indicates the run length decompression is taking place during forward data transfers in ECP with RLE mode It is set when a run length count is received and loaded into the internal counter and cleared when the last read of the PPD s data field takes place If a data is latched to PPDATA then this bit is set 1 It is automatically cleared while PPDATA is read When reverse ECP mode this bit specifies the PPDATA is empty It is automatically cleared while PPDATA is written with a new data ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ELECTRONICS 0 Software Reset Control 0 No effect 1 Terminate current PPIC operation and enter idle status 1 Digital Filter Enable 0 Disable 1 Enable 3 2 Operating Mode 00 Software mode 01 Compatibility mode 10 ECP mode without RLE 11 ECP mode with RLE 4 ECP Direction 0 Forward 1 Reverse 5 Error Cycle Control Compatibility Mode Only 0 Generate nACK and negate BUSY end error cycle 1 Execute an error cycle drive
271. nd Register 24 4 24 4 LDON Pre Post Time 24 4 24 5 V Window Counter Observation Register 24 5 24 6 LSU CLK Counter Base Observation 24 5 25 1 Queued Operation for End of Page 25 2 25 2 Queued Operation for Page Under run 25 3 25 3 Protocol Diagram PIFC and Printer Engine 25 4 25 4 and Engine Interface Status Register 5 25 5 25 5 Video Control Register VCON 25 7 25 6 Pattern Control Register 25 10 25 7 Printer DMA Control Register 25 12 25 8 Top Margin Register 25 13 25 9 Page 25 13 25 10 Left Margin Register 25 14 25 12 Queue 0 1 Start Address Registers QSARO 1 25 15 25 13 Queue 0 1 Transfer Count Registers QTCRO 25 16 25 14 F 0 Compensation Control Register 25 17 25 15 F 0 Compensation Table Start Address 0 25 18 25 16 F 0 Compensation Table Data Register FDATA 25 19 25 17 Toner Counte
272. nd shifted out by the transmit data pin TXDn Data received is shifted in by the receive data pin RXDn and then copied from shifter to receive buffer register once one data byte has been received The control unit will provide controls for mode selection and status interrupt generation Transmit Buffer Register Transmit Shifter Baud rate clock Control Baud rate Clock Source Unit Generator MCLK Baud rate clock i Receive Shifter Receive Buffer Register Receiver Figure 11 1 UART Block Diagram ELECTRONICS 11 1 UART KS32C65100 RISC MICROPROCESSOR UART OPERATION The following sections describe the UART operations that include infra red mode loop back mode interrupt generation baud rate generation data transmission data reception and so on Infra Red Mode The KS32C65100 UART block supports infra red IR transmit and receive which can be selected by setting the infra red mode bit in the line control register ULCONn The implementation on the mode is shown in Figure 11 2 In IR mode the transmit period is pulsed at a rate of 3 16 the of the normal serial transmit rate when the transmit data value in the TBR register is zero and in IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value in the receive buffer register RBR as the IR receive data refer to the frame timing diagrams shown in Figure 11 15 and 11 16 Em 1 F p IR Tx i IR Rx Encoder Decoder
273. ne starts whenever the I flag or F flag is cleared to 0 The service routine must clear the pending condition by writing 1 to the corresponding pending bit Interrupt mask register Indicates that the current interrupt has been disabled if the corresponding mask bit is 0 If an interrupt mask bit is 1 the interrupt will be serviced normally And if a global mask bit bit 31 is cleared all interrupts are not serviced However the source s pending bit is set when the interrupt is generated even if the corresponding mask bit is 0 After the global mask bit is set the interrupt will be serviced ELECTRONICS 15 1 INTERRUPT CONTROLLER KS32C65100 RISC MICROPROCESSOR INTERRUPT SOURCES The 30 interrupt sources in the KS32C65100 interrupt structure are described in brief in Table 15 1 Table 15 1 Interrupt Sources No SourceName Desrlon NETR External interrupt 2 comes from general input port 5 External interrupt 1 comes from general input port 4 External interrupt 0 comes from general input port 3 10 11 Image processor interrupt 1 Motor interrupt Image processor interrupt 0 SI interrupt 2 15 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR INTERRUPT CONTROLLER SPECIAL REGISTER Interrupt Mode Register Bits in the interrupt mode register INTMOD specify if an interrupt is to be serviced as a fast or normal interrupt INTMOD 0x2000 Interrupt mode register 0x00000000 31 30 29 28 27 26 25 2
274. ng Correction Block 21 14 21 20 Gamma Correction Block 21 15 21 21 ADC Control Timing Diagram 21 16 21 22 ADC Control Timing Diagram 21 17 21 23 Motor Interrupt Phase Timing 21 17 21 24 Register Read Write Timing 21 18 21 25 Timing Diagram SRAM Read Write by 21 19 KS32C65100 RISC MICROPROCESSOR xxi List of Figures continued Figure Title Page Number Number 22 1 Real Time Clock Block 22 1 22 2 RTCCON 22 3 22 3 BCDSEC Counter 22 4 22 4 Counter Register nnne nnne nennen 22 4 22 5 BCDHOUR Counter 22 5 22 6 BCDDAY Counter 22 5 22 7 BCDDATE Counter 22 6 22 8 BCDMON Counter 22 6 22 9 BCDYEAR Counter 22 7 23 1 Clock Save Block 23 1 23 2 RM 23 2 23 3 INNO O REM 23 2 24 1 IBSIURO v ui o REM 24 1 24 2 LSU CON Control 24 3 24 3 V Window Time Start E
275. nsfer length options For instance 0 could select the transfer of a single register and 1 could select the transfer of all the registers for context switching ELECTRONICS 3 49 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR ADDRESSING MODES is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to U 1 or subtracted from U 0 the base register Rn this calculation may be performed either before P 1 or after P 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and
276. nstruction please refer to the sections listed in the right most column Table 3 7 THUMB Instruction Set Opcodes Lo Register Hi Register Condition Codes Operand Operand Set Add with carry NE gt NN ADD Add 4 1 AND AND 4 4 4 Load multiple Load byte 5 2 207 gt Load sign extended byte Load sign extended halfword n r rir D olio Pop registers Push registers Rotate right Subtract with carry Store multiple Ala ALA A ajala ELECTRONICS 3 61 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR Table 3 7 THUMB Instruction Set Opcodes Continued Lo Register Hi Register Condition Codes Operand Operand Set STR Storewod 4 STRB Stmebye 4 SW Software interrupt f c SUB Subtract 4 t TST Test s 4 NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this instruction STRH Store halt word pou msc 3 62 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 1 MOVE SHIFTED REGISTER 15 14 13 12 11 10 6 5 3 2 0 2 0 Destination Register 5 3 Source Register 10 6 Immediate Value 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 3 30 Format 1 OPERATION These instruct
277. ntains an 8 bit data value for received serial data In DMA based receive mode the address of the receive buffer register should be set into the DMA source address register as the source of the DMA channel URXBUFO 0xb010 R UART ch 0 receive buffer register URXBUF1 0xb810 R UART ch 1 receive buffer register URXBUF2 oxc010 UART ch 2 receive buffer register 7 0 Receive data This field contains the data received from the corresponding SIO channel When UART finishes receiving a data frame the receive data ready bit in the UART status register USTAT 5 should be 1 This prevents reading invalid receive data that may already be present in the RBR Whenever the RBR is read the receive data ready bit USTAT 5 is automatically cleared to 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514 131211109 8 7 6 5 4 3 2 1 0 7 0 Receive Data for UART Figure 11 9 UART Receive Buffer Register URXBUFO 1 2 ELECTRONICS 11 13 UART KS32C65100 RISC MICROPROCESSOR UART Baud Rate Divisor Registers The value stored in the baud rate divisor register UBRDIV is used to determine the serial Tx Rx clock rate baud rate as follows UBRDIVn int source clock bps x 16 1 where the source clock is either MCLK the internal master clock or UCLK the external UART clock input as determined by the setting of the serial clock selection bit in the line control register ULCON 6 31 30 29 28 27 26 25 24 23 22
278. o DRAM banks One nRAS output is provided for each nRAS 1 0 52 53 bank DATA 15 0 59 66 1 03 External bi directional 16 bit data bus 68 75 Not column address strobe for DRAM The two nCAS outputs indicate the byte selections whenever a DRAM bank is accessed nCAS 1 0 54 55 mE Not output enable Whenever a memory access occurs the nOE output controls the output enable port of the specific nOE 5 memory device nWE 5 Not write enable Whenever a memory access occurs the nWE output controls the write enable port of the specific memory device Gate control line for print head O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 I3 I3 O5 O1 O1 O1 O1 LK nPHGA 13 1 16 24 GOPB 12 26 29 PHOE 16 1 31 38 1 Drain control line for print head GIOP 26 11 40 47 6 7 up ELECTRONICS 1 7 PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR Table 1 1 Pin Description Continued RXDO GIP 0 194 Receive data input for the UARTO RXDO is the UARTO channel s input signal for receiving serial data Receive data input for the UART1 RXD1 is the UART1 channel s input signal for receiving serial data RXD1 GIP 1 RXD2 GIP 2 190 Receive data input for the UART2 RXD2 is the UART2 channel s input signal for receiving serial data nEINTO GIP 3 08 External interrupt request input nEINTO nEINT1 GIP 4 9 nEINT2 GIP 5 193 191 189 188 nXDREQ GIP 6 199 TXD0 GOPA 0 TXD1 GOPA 1 EN T
279. o the condition code flags N Z C and V of CPSR or SPSR mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RESTRICTIONS e user mode the control bits of the CPSR are protected from change so only the condition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed e Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state e The SPSR register which is accessed depends on the mode at the time of execution For example only SPSR fiq is accessible when the processor is in FIQ mode e You must not specify R15 as the source or destination register Also do not attempt to access SPSR in User mode since no such register exists 3 16 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET MRS Transfer PSR Contents to a Register 28 27 23 22 21 16 15 12 11 0 00010 001111 000000000000 15 12 Destination Register 22 Source PSR 0 CPSR 12 SPSR current mode 31 28 Condition Field MRS Transfer Register Contents to PSR 31 28 27 23 22 21 12 11 4 3 00010 1010011111 00000000 3 0 Source Register 22 Destination PSR 0 CPSR 12 SPSR current mode 31 28 Condition Field MRS transfer register contents or i
280. ode Input Port Mode Output A Port Mode Register Output B Port Mode Register Data Registel eesti a d ae ae aua Input Port Data Output A Port Data Register Output B Port Data Test Control dd aa daas ida aiiud External Interrupt Control Register dd addas Chapter 15 Interrupt Controller Tull 5 M REGISter Chapter 16 LF Motor II I S Special Function Line Feed Motor Control Line Feed Motor Phase Control Register Line Feed Timer LFCON Each Control Phase State and Current Table For Full Half Quarter Step Mode Chapter 17 CR Control VS IVS WY xs ares a cet aa a a ec ett aa ea a ce Special Function 2000000000000000 44 Encoder Interrupt Interval Counter
281. ol Register SRAM DATA REGISTER RAM DATA 0x9830 SRAM data register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 RAM_DATA Records the value when MPU is writes on the internal SRAM Figure 21 12 SRAM Data Register 21 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR MOTOR TERM CONTROL REGISTER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 MOTOR TERM This register records the interval between the motor phase Its unit clock is selected by the register SEPARATE CLK SEL Figure 21 13 Motor Term Control Register MOTOR PHASE CONTROL REGISTER MOTOR PHASE 0x9838 Motor phase control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 BASE VALUEO 1 BASE VALUE1 2 BASE VALUE2 3 BASE VALUE3 4 BASE VALUE4 5 BASE VALUE5 Records next phase value for motor operation Figure 21 14 Motor Phase Control Register ELECTRONICS 21 9 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR BLACK SHADING CORRECTION FACTOR REGISTER BLACK 0x983c Black shading correction value register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 BLACK This value is for carrying out black shading correction It is found and recorded in this register by averaging the values found with th
282. on time amp observation register 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Counter Base Value 31 16 Counter Observation Value Figure 27 3 PWM Cycle Time Base Observation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Counter Base Value 31 16 Counter Observation Value Figure 27 4 PWM On Time Base Observation Register ELECTRONICS 27 3 PWM TIMER CONTROL KS32C65100 RISC MICROPROCESSOR Caution PWM Counter Clock MCLK pre scaler value 1 e Cycle time pulse width cycle time value 1 PNM Counter Clock e Ontime pulse width on time value 1 Counter Clock PWM Timer Setting Process e Write PWM Counter Pre Scaler value e Write PWM Cycle time value e Write PWM On time value e RUN Timer e Write Next PWM Cycle time value or PWM On time value When you change the PWM Cycle time or the PWM On time value 27 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSIONS 30 60 BSC 28 80 BSC 208 QFP 2828B EE 220 08 MAX 30 60 BSC antt 050850 a 0 08 MAX 3 40 0 20 NOTE Typical dimensions are in millimeters Figure 28 1 208 QFP 2828 Package Dimensions ELECTRONICS 28 1 KS32C65100 RISC MICROPROCESSOR EVALUATION BOARD EVALUATION BOARD INTRODUCTION KS32C65100 ev
283. only bits to read the logic level on the BUSY and nACK output pins and five read write bits control the logic levels on the printer output pins which can be used by software for handshaking control PPSTAT 0x8004 Parallel port status register 0 nFAULT control Setting this bit drives the nFAULT output to low level clearing it drives the signal High on the external nFAULT pin nFAULT is used to indicate to the host that there is a fault condition in the printer engine 1 SELECT control Setting this bit drives SELECT output to High level clearing it drives the signal low on the external SELECT pin SELECT indicates to the host that there has been a response from the printer engine 2 PERROR control Setting this bit drives PERROR output to high level clearing it drives the signal low on the external PERROR pin PERROR indicates to the host that a paper error has occurred in the engine 3 BUSY control Setting this bit drives the external BUSY output to high level This is generally done to disable hardware handshaking The PPSTATT 3 bit value is logically ORed with the internal busy signal that is provided by the PPIC to control hardware handshaking operations 4 nACK control Setting this bit to 1 forces the external nACK output to be driven low This is generally done when hardware handshaking is disabled The inverted logic of the PPSTAT 4 bit value is logically ANDed with the internal ACK signal that is provided by the PP
284. ontinuous mode of GDMA The GDMA which doesn t use the continuous mode releases the internal bus request in a short time after one unit of data 1 word 1 half word 16 bit or 1 byte When the bus is just released the DRAM controller may have the bus and can refresh DRAMs If CDMA which has the lower priority than the DRAM controller holds bus by continuous mode the DRAM refresh controller can not have the bus control until CDMA frees the bus control Starting Ending DMA transfers DMA starts to transfer data after the DMA receives service request from then XDREQ signal UART parallel port or Software When the entire buffer of data has been transferred the DMA becomes idle If you want to perform another buffer transfer the DMA must be reprogrammed Although the same buffer transfer will be performed again the DMA must be reprogrammed 9 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR DMA The Major Difference Between GDMA and CDMA GDMA and CDMA has differences as shown in table 9 1 Table 9 1 Difference Between GDMA and CDMA Functions GMA CDMA Single mode 0 0 Block mode Lo 0 0 2 Demadmode 0 Byte swap mode poe DATA TRANSFERS MODE Single Mode nXDREQ nXDACK Figure 9 2 External DMA Requests 2 Single Mode The DMA request nXDREQ or internal request causes one byte one half word or one word to be transmitted The single mode requires the DMA request for every data transfer The nXDREQ si
285. ontrol block is used to generate two phases and four current control signals for every step interrupt according to setting of motor direction and state mode This module performs the following functions in DC motor mode Filter block is used to protect from false information by noise onto input signals from photo sensor Encoder counter is used to calculate and store the cycle time of preceding input from photo sensor This cycle time is used for base value of basic timer which generates the basic pulse of 2400 PPI for fire strobe control in DC motor mode and this time value can be read by CPU Interrupt counter is used to calculate and store the interval time of DC motor interrupt If this counter overflows before the next interrupt has been observed an interrupt will be issued and the counter will go back to zero In DC motor mode prestep timer is used to set the number of rising edge on preceding input from photo sensor to issue an interrupt for DC motor position control ELECTRONICS 17 1 CR CONTROL KS32C65100 RISC MICROPROCESSOR NOTES 1 17 2 Writing the value of basic timer base register 1 must be preceded by that of basi c timer base register 2 after the reset is done If the next base value is written to the other base register when the basic timer based on one of the base registers is running the counter will keep counting with next value If the next base value is not written to the other register the counter
286. op interrupt when CDMA stops 9 Reset RS 0 Normal operation 1 Initialize control register 10 Transfer Direction for Parallel UART1 Only 0 Parallel UART1 to memory 1 Momory to parallel UART1 11 Single Block Mode 0 Single mode 1 Block mode 13 12 Transfer Width 00 Byte 8 bit 01 Halfword 16 bit 10 Word 32 bit 11 Not used 14 Continuous Mode 0 Normal operation 1 Hold system bus until the whole CDMA operation stops 16 Demand Mode 0 Normal operation 1 Byte swap operation Figure 9 8 CDMA Control Register ELECTRONICS 9 11 DMA KS32C65100 RISC MICROPROCESSOR CDMA Source Destination Address Register These registers contain the 25 bit source destination address for a CDMA channel Depending on the setting of the CDMA control register DMACONO these addresses will increase decrease or remain the same DMASRCO 0x8804 CDMA source address register OxXXXXXXX DMADSTO 0x8808 CDMA destination address register OxXXXXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMASRCO nan DMADSTO Source Destination Address 24 0 Source Destination Address Figure 9 9 CDMA Source Destination Address Register CDMA Transfer Count Register This register contains a 24 bit value which is the number of CDMA transfers completed for CDMA This value is decreased by 1 when one DMA operation is completed regardless of the width of the
287. operation and select the algorithm for half toning operation VISCON 0xa804 VIS control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Enable VIS Halftoning 0 Enable VIS operation 1 Enable Halftoning operation 1 Dot Mode Selection for Halftoning Operation 0 Dot mode 0 1 Dot mode 1 Refer to the halftoning algorithm description in Figure 26 3 Figure 26 5 VIS Control Register VISCON VIS Data Size Registers Two VIS data size registers SrcSize and DstSize are used to define the image data length before and after the VIS process i e the input source image data length and the output destination image data length The image scaling ratio can be determined by these two registers contents i e image scaling ratio DstSize value SrcSize value 0xa808 Destination image data size register OxXXXX Source image data size register OxXXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 mese 15 0 Data Size This 16 bit field contains the length value of the source image data to be written to SrcReg of the destination image data to be read from DstReg Figure 26 6 VIS Data Size Registers DstSize SrcSize 26 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR VARIABLE IMAGE SCALING VIS Data Registers Two VIS data registers SrcReg and DstReg respectively contain the input source image
288. or mode the cycle of fire strobe is decided by setting only the base value of the fire prescaler Fire 19200 Fire prescaler For DC motor mode the cycle of fire strobe is decided by the setting base value of the fire prescaler and DPI mode setting bit of PFCR ELECTRONICS 18 1 CR FIRE KS32C65100 RISC MICROPROCESSOR SPECIAL FUNCTION REGISTER POSITION amp FIRE CONTROL REGISTER PFCR 0x6820 Position amp fire control register 0x0080d0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 _ restr mee x 0 Position Prescaler Enable 0 Disable 1 Enable 3 1 DPI Mode Only for DC Mode 000 150 DPI 001 300 DPI 010 600 DPI 011 1200 DPI 011 2400 Other case 150 DPI 4 Position Count Reset Write Only 0 Reset 1 Normal operation 5 Window Time Base Select 0 Time base is written by S W 1 Time base is written by H W 6 PPI Clock Selection Only for Test 0 9600 1 19200 PPI default 14 7 Prescaler This 8 bit prescaler is for the fire strobe 20 15 Prescaler This 6 bit prescaler is for carrier position Figure 18 1 Position amp Fire Control Register 18 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR FIRE CR POSITION AND FIRE CONTROL REGISTER There are four registers in this block Carrier Position Count Register CPCR Print Start Position Register PSPR Print Slice Counter Register PSCR and Posit
289. output one request is output And if each line s last DMA is not 32 bits the remaining parts are filled with 0 for output To signify the location of the last pixel you must set the value of the register CHANGED_PIX_NUM If you do not magnify or reduce the image you can use the number of value pixels line for the last value but if you do magnify or reduce you must use a modified value NOTE If the number of magnified pixels exceeds 2560 during magnification the DMA operates fixed to 2560 regardless of the CHANGED_PIX_NUM value GRAY Data Output If you set the BINARY GRAY register bit to 1 the gamma corrected value 8 bits is immediately output through DMA Since the DMA must maintain 32 bits DMA request is output once for each time 4 pixels are handled so you must select the CHANGED PIX NUM accordingly 21 20 ELECTRONICS KS32C65100 RISC MICROPROCESSOR REAL TIME CLOCK REAL TIME CLOCK OVERVIEW The Real Time Clock RTC unit is operated by the system power 5V or the backup battery if the system power is turned off The RTC transmits 8 bit data to the CPU as BCD Binary Coded Decimal values using STRB LDRB ARM operation The data include second minute hour date day month and year The RTC unit works with an external 32 768kHz crystal OSC amp Frequency Leapyear Generator Division Logic System Bus Figure 22 1 Real Time Clock Block Diagram ELECTRONICS 22 1 REAL TIME CLOCK KS32C65100 RISC MICROPRO
290. overlap other activity allowing the coprocessor and ARM7TDMI to perform independent tasks in parallel COPROCESSOR INSTRUCTIONS The KS32C65100 unlike some other ARM based processors does not have an external coprocessor interface It does not have a on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the KS32C65100 These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor can not be connected to the 532 65100 the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 28 27 24 23 20 19 16 15 12 11 7 54 3 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Unmber 15 12 Coprocessor Destination Register 19 16 Coprocessor Operand Register 23 20 Coprocessor Operand Code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction ELECTRONICS 3 47 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR THE COPROCESSOR FIELDS Only bit 4 and bits 24 to 31 are significant to ARM7TDMI The remaining bits are used by coprocessors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP5 field is used to contain an identifying number in the range 0 to 15 for each
291. p address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation BYTES AND WORDS This instruction class may be used to swap a byte B 1 or a word B 0 between an ARM7TDMI register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers In particular the description of Big and little Endian configuration applies to the SWP instruction USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction ELECTRONICS 3 43 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR DATA ABORTS If the address used for the swap is unacceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the data abort trap will be taken It is up to the system software to resolve the cause of
292. p2 Op1 C 1 1000 TST set condition codes in Op1 AND Op2 1001 TEO set condition codes in Op1 EOR Op2 1010 CMP set condition codes in Op1 Op2 1011 SMN set condition codes in Op1 Op2 1100 ORR or 1101 MOV Rd Op2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd 25 Immediate Operand 0 Operand 2 is a register 1 2 is an Immediate value 11 0 Operand 2 Type Selection 11 4 3 Shift Rm 3 0 2nd operand register 11 4 Shift applied to Rm 11 8 7 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Confition Field Figure 3 4 Data Processing Instructions 3 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands The first operand is always a register Rn The second operand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in Table 3 3 CPSR FLAGS
293. preted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represented as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register 3 20 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET All other register combinations will give correct results and Rd Rn and Rs may use the same register when required CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V oVerflow flag is unaffected INSTRUCTION CYCLE TIMES MUL takes 15 and MLA 15 m 1 I cycles to execute where S and are defined as sequential S cycle and internal I cycle respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows If bits 32 8 of the multiplier operand are all zero or all one If bits 32 16 of the multiplier operand are all zero or all one If bits 32 24 of the multiplier operand are all zero or
294. printer DMA queue 0 sends a stream of zeros to the laser printer engine as video data No external memory access is required during this PDMA operation Blank mode is useful for sending a blank image if the bit map of a certain banded image consists of all zeros blank When this bit is O all PDMA accesses are in normal mode That is external page memory must be accessed to fetch the page bit map 1 Blank mode DMA queue 1 When PDMACON 1 is 1 the shift register of DMA queue 1 sends a stream of zeros to the laser printer engine as video data This control bit has the same effect for queue1 as PDMACON 0 does for queue 0 2 DMA queue 0 enable When PDMACON 2 is set to 1 queue 0 is enabled and a printer 0 operation can start When the queue 0 operation is completed this bit is automatically cleared to 0 3 DMA queue 1 enable When PDMACON S is set to 1 queue 1 is enabled and printer DMA 1 operation can start When the queue 1 operation is completed this bit is automatically cleared to 0 141 Queued operation enable The value of this bit determines whether PDMA uses queued operation to transfer banded bit mapped data to the laser engine If PDMACON 4 is 0 queue 0 or queue 1 transfers data over one queue or the other without alternating between the two If PDMACON 4 is 1 banded bit mapped data is transferred in an alternating queue operation using both queues 5 PDM
295. program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a fixed order See exception priorities on page 2 14 Action on Entering an Exception When handling an exception the ARM7TDMI 1 Preserves the address of the next instruction in the appropriate link register If the exception has been entered from ARM state then the address of the next instruction is copied into the link register that is current PC 4 or PC 8 depending the exception See Table 2 2 on for details If the exception has been entered from THUMB state then the value written into the link register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14 svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions If the processor is in THUMB state when an exception occurs it will automatically switch into ARM state whe
296. r 14 Remocon Receive Chapter 8 Interrupts Chapter 15 4 Bit Analog to Digital Converter Chapter 9 Ports Chapter 16 On Screen Display OSD Chapter 10 Real Timer Chapter 17 Electrical Data Chapter 11 Basic Timer amp Watchdog Timer Chapter 18 Mechanical Data Chapter 12 16 Bit Timers Chapter 19 KS17F80013 MTP Two order forms are included at the back of this manual to facilitate customer order for KS17C80064 C80013 F80013 RISC Microprocessors the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative KS32C65100 RISC MICROPROCESSOR iii Table of Contents Chapter 1 Product Overview nitro LOT n a e auc aua EA 1 1 3 ea e oS 1 2 BloekCIDIAgEatmi c aaa a aaa 1 4 oodd du 1 5 BI Tre o REM 1 6 KS32C65100 Special Function 1 11 Chapter 2 Programmers Model eT ul 2 1 Processor Operating States eie 2 1 SWITCHING State 2 1 Memory eo Luz 2 1 Big Endian 2 2 ede i e so E eor iaaa 2 2 INSTRUCTION Rm 2 3
297. r 32 bits of the result are written to The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce 64 bit result of the form RdLo Rm Rs RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write a two s complement signed 64 bit result OPERAND RESTRICTIONS e R15 must not be used as an operand or as a destination register RdLo Rm must all specify different registers 3 22 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N is equal to bit 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values INSTRUCTION CYCLE TIMES MULL takes 15 m 1 l MLAL 15 m 2 I cycles to execute where mis the number of 8 bit multiplier array cycles required to complet
298. r Setting Register 25 19 25 18 Toner Count Register 99 25 20 25 19 Test Pattern Duration TPVAL 25 20 25 20 Test Pattern Width TPON 25 21 xxii KS17C80064 C80013 F80013 MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 26 1 VIS Algorithm Description 26 2 26 2 Examples of VIS s Internal 26 3 26 4 VIS Status Register VISSR 26 5 26 5 VIS Control Register 5 26 6 26 6 VIS Data Size Registers DstSize 26 6 26 7 VIS Data Registers SrcReg DstReg 26 7 26 7 VIS Data Registers SrcReg DstReg 26 8 27 1 CON Control 27 2 27 2 PWM Pre Scaler Counter Base Observation 27 2 27 3 PWM Cycle Time Base Observation Register 27 3 27 4 PWM On Time Base Observation Register 27 3 28 1 208 QFP 2828 Package Dimensions sss 28 1 29 1 Evaluation dA e dct ee edd 29 3 29 3 Connection to Embedded ICE 29 4 29 4 Evaluation Board Schematic 1 29 8 29 5 Evaluation
299. r WTCNT is used to specify the time out duration The watchdog timer enable bit bits WTCON must be 0 before loading a value to this register Watchdog Timer clock MCLK prescale value 1 division factor Watchdog Timer duration count val Watchdog Timer clock Table 13 1 Watchdog Timer Counter Setting MCLK 33MHz Prescale WTCNT 16 bit count MCLK prescale 1 16 MCLK prescale 1 32 12 28us MCLK prescale 1 64 24 96us MCLK prescale 1 128 49 92us WTCNT 0x4004 Watchdog timer count register 0x0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Watch Dog Timer Count Register This specifies the time out duration Figure 13 2 Watchdog Timer Count Register WTCNT 13 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR WATCH DOG TIMER WATCHDOG TIMER CONTROL REGISTER The Watchdog Timer Control register WTCON provides the control bits for the enable disable of the watchdog timer selects the clock signal from 4 different sources enables disables interrupts and enables disables the watchdog timer reset output signal nWDTO pin If the watchdog timer is set to 0 WTCON is cleared to 0 0 WTCON 0x4000 Watchdog timer control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Reset Mode 0 Disable nWDTO pin 1 Enable nWDTO pin 2 Interrupt Mode 0 Disable Interrupt 1 En
300. r block receives its own clock signals signal name is Timer Clock from the clock divider which receives the clock from the 8 bit prescaler The 8 bit prescaler is programmable and it divides the MCLK signal depending on the loading value which is stored in TSTCON 14 7 bits The timer count value register TBCNTn stores initial count value and its data is loaded into the down counter when the timer is enabled Each timer has its own 16 bit down counter that is driven by the timer clock When one of the down counters reaches zero the timer counter interrupt request is generated to inform the CPU that one of the timer operations is completed When it reaches zero the corresponding TBCNTn content is automatically loaded into the down counter to continue the next operation However if a timer is stopped for example if you clear the timer enable bit in TCON during the timer running mode the count value in TBCNTn will not be reloaded into counter The timer count value register is used to define the duration for timer operation and contains the number of timer clock periods needed for one operation duration The timer duration can be calculated as follows Timer clock MCLK prescale value 1 division factor Hz Timer duration value Timer clock m Reload count value when down counter reaches to 0 TBCNTO 15 0 8 Bit Prescaler _ 0 mum Timer 1 interrupt Timer 1 Timer 2 interrupt TCON 8 7
301. r to remain set If PPCON 6 is 1 and nSELECTIN goes low PPCON 6 is cleared and setting this bit will have no effect The external PPD 7 0 outputs reflect the current state of PPCON 6 The abort bit causes the parallel port interface controller to use nSELECTIN to detect when the host suddenly aborts a reverse transfer and returns to compatibility mode If PPCON T is 1 a low level on nSELECTIN causes the parallel port data bus output enable bit PPCON 6 to be cleared and the output drivers for the data bus lines PPD 7 0 to be tri stated The PPIC can issue a DMA request during a forward data transfer in compatibility mode ECP without RLE mode or in ECP with RLE mode if the DMA request enable bit PPCON T is set The DMA selection bit determines which DMA channel is used for forward data transfer When PPCON S is 0 DMA channel 0 is used when it is 1 DMA channel 1 is used 10 11 PARALLEL PORT INTERFACE 9 10 12 13 14 15 10 12 DMA request enable Flush request Zero insert RLE status Data latch status Write status KS32C65100 RISC MICROPROCESSOR When this bit is set to 1 the PPIC issues a DMA request to DMA channel 0 or 1 during a forward data transfer otherwise an interrupt is requested for the data transfer When this bit is set to 1 the PPIC issues a DMA request to send the remaining data to parallel port The remaining data means run length code and data i
302. ra Bank Access Control 4 21 Electrical 4 24 Chapter 5 Cache Controller lal e 5 1 2 54 5 3 Cache Control REGISTENS E Qus 5 5 Chapter 6 Derasterizer TII PE 6 1 gie M RE D E 6 1 Shift Control Register SFTCON 6 2 Chapter 7 General ADC Qr ERREEN ENES NEE 7 1 SE oieee oon 7 1 SAR Successive Approximation Register A D Converter 7 2 Comparator COMP and DAC Digital To Analog 7 2 Special n ales noun e e e Pe x tee ce eae 7 3 Chapter 8 Timer OVeIVIGW2 xx 8 1 Timer Control Register 8 2 Timer Count Value 8 3 KS32C65100 RISC MICROPROCESSOR Table of Contents Continued Chapter 9 DMA OVGIVIOW 9 1 Op ration ed daa dadas 9 2 Data Transfers Mode REM 9 3 General Control Register 12 0 000 9 5 GDMA Source Destination Address Register 9 8 CDMA Control
303. rations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally see Table 3 2 for details In THUMB state only the Branch instruction is capable of conditional execution see Figure 3 46 for details The Control Bits The bottom 8 bits of a PSR incorporating F T and M 4 0 are known collectively as the control bits These will change when an exception arises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits The and F bits are the interrupt disable bits When set these disable the IRQ and FIQ interrupts respectively The mode bits The M4 M3 M2 M1 MO bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode bits define a valid processor mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be appl
304. register ULCON1 800 R W UART ch 1 line control register ULCON2 0 000 UART ch 2 line control register 1 0 Word length WL The two bit word length value indicates the number of data bits to be transmitted or received per frame 00 5bits 01 6bits 10 7bits 11 8bits 2 No of stop bit ULCON 2 specifies how many stop bits are used to signal end of frame EOF 0 One stop bit per frame 1 Two stop bit per frame 5 3 Parity mode PM The 3 bit parity mode value specifies how parity generation and checking are to be performed during UART transmit and receive operations No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 6 Reserved This bit must be O 7 Infra red mode This bit determines whether to use the infra red mode 0 Normal mode operation 1 Infra red Tx Rx mode NOTE ULCONn has to be configured before UCONn is configured 11 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 1514131211109 8 7 6 5 4 3 2 1 1 0 Word Length Per Frame 00 5 bits 01 6 bits 10 7 bits 11 8 bits 2 Number of Stop Bit at the end of Frame 0 One stop bit per frame 1 Two stop bit per frame 5 3 Parity Mode Oxx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced as 0 6 Reserved This bit must 0 7 Infra r
305. requests Setting causes the UART to send a break Break is defined as a continuous Low level signal on the transmit data output with a duration of more than one frame transmission time By setting this bit when the transmitter is empty transmitter empty bit USTAT 7 1 you can use the transmitter to time the frame When is 1 write the transmit buffer register TBR with the data to be transmitted then poll the USTAT 7 value When it returns to 1 clear reset the send break bit UCON 6 0 Do not send break 1 Send break Setting this bit causes the UART to enter loop back mode In loop back mode the transmit data output is sent to high level and the transmit buffer register TBR is internally connected to the receive buffer register RBR This mode is provided for test purposes only 0 Normal SIO operation mode 1 Enable SIO loop back mode for testing only ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211109 87 6 5 4 3 2 1 L S 1 0 SIO Receive Mode Selection RxM 00 Disable 10 Interrupt Request 10 GDMA rquest for UCONO CDMA request for UCON1 Not used for UCON2 11 Not used 2 Receive Status Interrupt Enable 0 Do not generate receive status interrupt 1 Generate receive status interrupt 4 3 UART Transmit Mode Selection TxM 00 Disable 10 Interrupt Request 10 GDMA rquest for UCONO CD
306. reshold control register Oxdc7f40 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 TDIFF 15 8 TMIN 23 16 TMAX Figure 21 8 LAT Control Register ADC CONTROL REGISTER 0x9824 ADC clock control register 0x005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 ADC_START This signal allows the analog signal output from the sensor to be A D converted by the internal ADC By adjusting this value the ADC clock location can be adjusted in system clock units for the optimum A D conversion This value can be found by outputting the signal output to the sensor and the ADC clock in IP test mode to the oscilloscope simultaneously and comparing the values 8 BINARY_GRAY 0 Output binary data 1 Output 8 bit data Figure 21 9 ADC Control Register OPERATION CONTROL REGISTER OPERATION 0x9828 Operation control register 0x000 207 21 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 SCAN ON After power on the KS32C65100 provides the SI signal and other various sensor signals Therefore you need a signal that tells you from which line you will get useful data The SCAN on provides that service The line triggering signals that follow after this bit is set to 1 are recognized as meaningful si
307. ress pins 16 bit data width for each bank ELECTRONICS 4 1 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR Undefined Region 32M Bytes SA 24 0 0x01010000 Special Function Register 0x01000000 ROM Region Non Accessible Region ROM Region 0x00800000 gt 16MB Accessible Region da 0x00000000 Figure 4 1 System Memory Map Default Map After Reset 4 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER DRAM Refresh Control Register REFCON DRAM Control Register 0 DRAMCON 0 Extra Bank 3 Control Register EXTCON 3 Extra Bank 2 Control Register EXTCON 2 Extra Bank 1 Control Register EXTCON 1 Extra Bank 0 Control Register EXTCON 0 SRAM Control Register 1 SRAMCON 1 Special Function REG SRAM Control Register 0 SRAMCON 0 ROM Regi ROMCON DRAM Bank 1 OM Control Register ROMCON System Register Configuration Register DRAM Bank 0 EXTRA Bank 3 Extra Bank 3 32M Bytes SA 24 0 EXTRA Bank 2 Tr SP IO EXTRA Bank 1 Extra Bank 3 EXTRA Bank 0 SRAM Bank 1 SRAM Bank 0 i ROM Bank 0 Max 4M half word 22 bit per bank A Each bank can be located anywhere in 32MB address space Figure 4 2 System Memory Map The KS32C65100 uses an internal 25 bit system address bus and it can provide 32M bytes the size of memory space The bank allocation methodology is very configurable and you can use any address area within 0000000h 1FEFFFFh b
308. ring at the beginning of a page 0 8 MOTOR ON 0 Motor off 1 Motor on 9 MOTOR PHASE LAT OR NOT 0 The motor phase value used in the register is used by the MPU with immediate effects 1 The motor phase value used the register is latched to the SI signal and manifested in the next phase 11 10 SEPARATE CLK SEL This register is for selecting the unit clock of the counter that adjusts the motor phase interval 00 System 2 01 System 4 02 System 8 03 System clock 16 Figure 21 10 Operation Control Register ELECTRONICS 21 7 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR SRAM CONTROL REGISTER RAM CTRL 0x982c IP Inner SRAM control register 0x70000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 0 SW_FIRST_RAM_ADDR You can select the first address through this register when MPU is writing data on the internal SRAM 16 GAMMA_RAM_CS 0 RAM chip select for gamma correction SRAM 17 SHAD RAM CS 0 RAM chip select for shading SRAM 18 RAM CS 0 Chip select for binarization SRAM 19 SW ADDR INIT This register is for initializing the internal RAM s address When this is triggered once 0 1 0 the S W FIRST RAM ADDR value becomes the first address value that MPU records in the SRAM it must be initialized before writing on the internal SRAM Figure 21 11 SRAM Contr
309. rsion Enable 0 A D conversion disable 1 A D conversion start This bit auto cleared after A D conversion start up 2 1 Analog Input Selection 00 AINO 01 AIN1 10 AIN2 11 2 Not defined 3 Reserved This bit must be O 4 Clock Selection 0 MCLK 2 clock 1 MCLK 4 clock 5 Stand by Mode 0 Normal mode 1 Stand by mode power down No A D conversion operation For A D conversion its state must be changed from 1 0 for at least one XP1 period 6 8 bit Mode 0 10 bit resolution 1 8 bit resolution 7 Flag 0 A D conversion in process 1 End of A D conversion Figure 7 2 ADC Control Register ADCCON 7 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR GENERAL ADC ADC Data Register ADCDATA loads the A D conversion data during read operation after the conversion process is completed and flag goes 1 Internally DGET signal is activated by read operation of ADCDATA and A D converted data are produced by applying DGET ADCDATA 804 R data register OxXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 9 0 ADC A D Conversion Value A D converted data Figure 7 3 ADC Data Register ADCDATA ELECTRONICS 7 5 KS32C65100 RISC MICROPROCESSOR TIMER TIMER OVERVIEW Timer Block has three 16 bit timers Three timer blocks share an 8 bit prescaler and a clock divider which has 4 different divided signals Each time
310. rupt 10 Invalid nSELECTIN Transition During ECP 0 Disable interrupt 1 Enable interrupt 11 Transmit Data PPDATA Empty 0 Disable interrupt 1 Enable interrupt Figure 10 8 Parallel Port Event Interrupt Enable Register PPINTEN 10 16 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PARALLEL PORT INTERFACE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 fff eff cfc 0 nSELECTIN Low to High Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 1 nSELECTIN High to Low Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 2 nSTROBE Low to High Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 3 nSTROBE High to Low Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 4 nAUTOFD Low to High Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 5 nAUTOFD High to Low Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 6 nINITIAL Low to High Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 7 nINITIAL High to Low Transition 0 Normal operation 1 Transition occured issue interrupt if enabled in PPINTEN 8 Data Received Latched to PPDATA Data Field 0 Normal op
311. s ondas se Ob e I e Data ADOrte Instruction Cycle Times insi AASI EAE O eed dieu Software Interrupt Return From The 5 Comment FICE 4 adero adds Instruction Cycle TIMES dadas Asseimbler Syntax vo ae cdd aded didi Coprocessor Data Operations Coprocessor Coprocessor Data Transfers LDC 5 Coprocessor Fieldsi 5 232 cid dad dde Addressing Modes Address Alignment 5 5 d T Use Ob Hb ooo den Data 2 9 cnet Instruction Gycle Times iade Assembler Syntax nasce dede Coprocessor Register Transfers The Coprocessor Fields 3 edd Transfers Lo Instruction Cycle Tires 3 iini Assembler Syntex i tee added deu KS32C65100 RISC M
312. s power back up circuitry it still requires periodical refresh signals from KS32C65100 Therefore it won t be able to keep valid DRAM data in a short time if KS32C65100 does not make DRAM self refresh mode For this reason when main power is disconnected and nRESET goes low KS32C65100 s system manager block makes self refresh signals The system user can make memory back up system easily by utilizing this feature if only DRAM is used for system memory Main Power Reset Filter 65 Cycle nRST s KXXXXXXXXXXXXXXXXX Internal Reset 256 Cycle 0 0 9 0 0 0 0 0 0 0 0 0 0 09 0 9 9 DRAM will enter self refresh mode after 100us ncas KKK KKK KK KKK KKK KKK nOE DATA Figure 4 17 Self Refresh Mode Entry Process bynRESET 4 18 ELECTRONICS KS32C65100 RISC MICROPROCESSOR SYSTEM MANAGER 2 Self Refresh mode by Software After system reset KS32C65100 is in DRAM self refresh mode By programming the REN bit of DRAM refresh control register to 1 system manager block works as normal DRAM access mode To enable the self refresh mode during normal system operation programmer needs to change the REN bit to 0 system manager detects the REN bit content change from 1 to 0 it activates the self refresh mode If programmer wants change mode from self refresh mode to normal DRAM access mode programmer just needs to write 1 to REN bit once again
313. s selected first data access time will be different from the access time of the following data of the same bank Tacc access cycles for ROM bank is defined as the access cycles after the ROM bank changes This cycle time is also used for simple ROM access mode When CPU reads consecutive data within same bank page mode ROM supplies data read cycles shorter than reading the simple ROM or new bank access mode The Tacp bit in ROM ROM control register defines consecutive data read cycles in page mode ROM Writes to the ROM space KS32C65100 ROM interface provides write feature Users can write data into ROM bank area Physically the internal program in ROM is not to be changed So if a user puts external memory instead ROM such as SRAM flash memory etc it is possible to write data ROM Bank Space One of good features of KS32C65100 is to have the configurable memory space Users can program the memory bank size and bank location by modifying the contents of the ROM control register ROMCON ROM control register has two 9 bits address pointers base and Next pointer These two pointers denote the beginning and ending address of ROM bank These 9 bits are mapped to the address 24 16 which means that bank address can be configured by 64KB range The next pointer contents should be ROM bank end address 1 Initially ROM bank start address is 00000000h and end address is OOFFFFFFh Therefore Next pointer values must be OOFFh 1h 0100h If RO
314. s that the received data did not have a valid stop bit The break condition indicates that the received data input is held in the logic 0 state for a duration longer than one frame transmission time The data reception process is shown in Figure 11 4 in which the receiver transfers data through such a path RXDn pin receive shift register receive buffer register destination and completes serial to parallel data conversions In addition to receive error status flags a receive buffer full flag is used to indicate the status of the receive buffer register ELECTRONICS 11 3 UART KS32C65100 RISC MICROPROCESSOR UBRDIV ULCON UCON is configured ransmit Y Transfer the data to transmit shifter Set the transmit buffer register empty flag After shift out last stop bit set the transmitter empty flag Figure 11 3 UART Data Transmission Process 11 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR UART UBRDIV ULCON UCON is configured Receive data into receive shifter from RXDn pin Parity overrun frame error or break detected N Transfer the data to receive buffer Set receive buffer full flag Figure 11 4 UART Data Reception Process ELECTRONICS 11 5 UART KS32C65100 RISC MICROPROCESSOR UART SPECIAL REGISTERS UART Line Control Register There are three identical UART line control registers ULCONO 1 2 in the UART block one for each UART channel ULCONO 0xb000 UART ch 0 line control
315. s the video clock 01 Use external VCLK as the video clock 10 No clock selected 11 Use MCLK as the video clock 6 4 Video Clock Divisor Selection 00021 00122 01023 011 24 10025 10126 11027 11128 9 7 Shrink Pattern for Video Data 000 No shrinking 001 1 n dot shrunk at left edge of image 010 2 n dot shrunk 011 dot shrunk 100 4 n dot shrunk 101 5 n dot shrunk 110 6 n dot shrunk 111 7 n dot shrunk 17 10 Video Data Chopping Pattern 0 Chop 1st sub pixel of each dot Chop 2nd sub pixel of each dot Chop 3rd sub pixel of each dot Chop 4th sub pixel of each dot Chop 5th sub pixel of each dot xxOxxxxx 2 Chop 6th sub pixel of each dot Chop 7th sub pixel of each dot Chop 8th sub pixel of each dot 19 18 Image Expanding Ratio 00 Normal 01 2 times expanding 10 3 times expanding 11 4 times expanding 20 Hsync Selection 0 HSYNC1 1 HSYNC2 21 Test Mode 0 Normal mode 1 Test pattern generation Figure 25 6 Pattern Control Register PCON 25 10 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER PRINTER DMA CONTROL REGISTER The printer DMA control register PDMACON is used to control the operation of the printer DMA queues PDMACON PDMA control register 0x00 0 Blank mode DMA queue 0 When PDMACON O is 1 the shift register of
316. scan lines to be skipped when printing starts An internal counter records the number of NRENGHSYNC pulses to determine the beginning of the effective printing area 0xa010 Top margin register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Top Margin Count Value This 16 bits field contains the top margin count value This value specifles how many scan lines are to be skipped in the top margin area of a page in order to reach the start of the effective print area Figure 25 8 Top Margin Register TOP Paper Image Border Figure 25 9 Page Layout ELECTRONICS 25 13 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR LEFT MARGIN REGISTER The PIFC left margin register LFT controls the number of pixels that are skipped when a scan line operation starts in synchronization with nENGHSYNC An internal counter records the number of pixels skipped in order to determine the starting pixel of the scan line operation 0xa014 Left margin register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 Left Margin Count Value This 16 bits field contains the left margin count value This value specifles how many pixels are to be skipped in the left margin area of a page in order to determine the starting pixel on which the scan line begins NOTE For correct printing operation it is recommended that
317. se address in Rb Write back the new base address Rb Rlist Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 22 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STMIA RO R3 R7 Store the contents of registers R3 R7 starting at the address specified in incrementing the addresses for each word Write back the updated value of RO ELECTRONICS 3 85 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR FORMAT 16 CONDITIONAL BRANCH 15 14 13 11 8 7 0 1 12 7 0 8 bit signed Immediate 11 8 Condition Figure 3 45 Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 3 23 The Conditional Branch Instructions Code THUMB Assembler ARMEquivalent Adi Branch if Z set equal Branch if Z clear not equal 0010 Branch if C set unsigned higher or same 001 1 Branch if C clear unsigned lower 0100 Branch if N set negative 010
318. sed Laser printer engine interface e Dedicated DMA for fast data transfer between page memory and the printer engine e Consecutive zero string blank data output for banded bit maps no memory access required Queuing operation to facilitate smooth switching between data blocks of banded page memory Pixel chopping mode for fine edged image printing e Video data boundary polarity definition e Support for 2x or 4x image expansion e Dot counter to accumulate printing dot e Generates test pattern for laser engine Laser Engine Control e Controls LSU on off data and motor clock e Controls LSU interface signals e Programmable external clock for LSU motor Operating Voltage Range e Internal logic to 3 6 Volts e PAD 4 75 to 5 25 Volts Operating Frequency e Up to 33MHz Package Type e 208 pin QFP 1 3 PRODUCT OVERVIEW BLOCK DIAGRAM Scan Image amp Scan Motor Controller Ink Head Controller Parallel Port Interface Video Data Controller UART Serial I O 1 4 KS32C65100 RISC MICROPROCESSOR PLL amp Clock Save Interrupt Controller Converter gt Carrier Motor Control Position amp Fire Control Paper Motor Control Real Time Clock Watch Dog Timer Figure 1 1 KS32C65100 Block Diagram CPU ARM7TDMI I D Cache 2 KB ELECTRONICS PRODUCT OVERVIEW KS32C65100 RISC MICROPROCESSOR PIN ASSIGNMENT 02vdO9 8HdNOO 08 os os SSA SevdO9 0viuo
319. sensor latch clock s period The count unit uses the SEN CLK s period as reference The 1 channel s sensor counts one period but the 2 channel sensor outputs one pixel value in a half period of SEN CLK so you must adjust as needed Example To get an A pixel with a DYNA sensor gt 51 To get an A pixel with a CANON sensor gt SI 2 When the appropriate SI signal for each period is being output an interrupt is generated The S W uses this signal to modify the value The value modified at this time influences the SI output next Figure 21 3 Sensor SI Clock Control Register ELECTRONICS 21 3 IMAGE PROCESSOR KS32C65100 RISC MICROPROCESSOR SENSOR R GB LED CONTROL REGISTER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 28 16 RLED START 12 0 RLED END 28 16 GLED_START 12 0 GLED END 28 16 BLED START 12 0 BLED END A signal for operating the sensor s light source It is counted using SEN CLK as reference This signal latches the register value each time the SI is turned on and operates automatically according to that value Generally a normal mono CIS uses only one out of three signals but the canon color CIS uses all three refer to color canon CIS spec Figure 21 4 Sensor R GB LED Control Register IWIN CONTROL REGISTER IWIN 0x9814 Effective pixels num control register 0x000006b8 31 30 29 28 27 26 25 24 23 22 21 20
320. sly degrade performance The unified cache deals with instruction and data in the same way ELECTRONICS 5 1 CACHE CONTROLLER KS32C65100 RISC MICROPROCESSOR 31 30 29 28 27 26 25 24 10 43 21 9 0 15 2 6 bit 15 15 Seti 0 Tag Height 64 Decoder 6 bit Tag RAM 32 bit Set 1 Icache line 4 instruction data 128 Set 0 line 4 instruction data 128 a Height 64 Ooo Oooo o E Set 0 Hit Set 1 Hit Figure 5 1 Cache Memory Configuration 5 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CACHE CONTROLLER CACHE OPERATION Cache Organization The KS32C65100 Cache has two sets of 2KB cache memory and one small Tag RAM The Tag RAM has two bits of CS Cache Status and two sets of Tag memory set 0 and 1 Each Tag set has 15 bits of address field 24 10 which is being stored in the cache memory The CS has two bits and it indicates the validity of cached data for corresponding cache memory line It is also used for the cache replacement algorithm and for selecting a data coming from Set 0 and 1 Cache memory has two sets Set 0 and Set 1 Each set has 64 lines and each line has four words of memory space 128 bits Cache Replace Operation After system is initialized CS is 00 which represents that the contents of set 0 and set 1 cache memory are invalid When first cache fill occurs CS is changed
321. sor Register Transfer Instructions 3 52 3 28 Undefined Instruction 3 54 3 29 THUMB Instruction Set nennen 3 60 KS32C65100 RISC MICROPROCESSOR xvii List of Figures Continued Figure Title Page Number Number 3 30 Format RR 3 63 3 31 REM 3 64 3 32 Format c REM 3 65 3 33 p RM 3 66 3 34 Format d c RM 3 68 3 35 Format RR 3 71 3 36 Format REM 3 72 3 37 Format RM 3 74 3 38 RR 3 76 3 39 ae uz un RR 3 78 3 40 Format b 3 79 3 41 Format REM 3 80 3 42 Format 13 Rm 3 82 3 43 Format PEE 3 83 3 44 Format RM 3 85 3 45 Format RR 3 86 3 46 ae tub AREE 3 88 3 47 lao tub RR 3 89 3 48 ae tub I RR 3 90 4 1 System Memory Map Default Map After 4 2 4 2 System Memory 4 3 4 3 Special Function Register Address Configuration Register 4 4 4 4 ROM Control Register ROMCON 4 6 4 5 The Byte Swap Operation of BTU and the Positions of Data in Memory 4 8 4 6 Simple ROM Access 4 10 4 7 Page Mode ROM Access 4 10 4 8 SRAM Control 4 11 4 9 External Address Bus Generation ADDR 21 0 sse 4 12 4 11 SRAM Read
322. ssor 23 21 Coprocessor Operation Mode 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP field is used as for all coprocessor instructions to specify which coprocessor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 52 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When coprocessor register transfer to ARM7TDMI has R15 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of the transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer TRANSFERS FROM R15 A coprocessor register transfer from ARM7TDMI with R15 as the source register will store the PC 12 INSTRUCTION CYCLE TIMES MRC instructions take 15 b 1 l 1C incremental cycles to execute where S and
323. st external I O control solution Extra bank has special signals such as nlIOWRO When a user reads writes data from to external latch devices these signals prevent extra address decoding logic ICs These signals are available at only the extra bank 3 Basically they have same timing diagram as the extra bank 3 has The initial address of each I O control registers are plus of its own offset address with initial SYSCFG register address 01000000h End Address of Extra Bank 3 Special I O 0 Address Specified by SRAM o Control 0 Reg P nlORD 0 Start Address of Extra Bank 3 End Address of nlOWR 0 End Address of End Address of Extra Bank 0 Start Address of Start Address of Start Address of Extra Bank 0 Figure 4 20 Special I O Address When fetching data the point of data reading is the last down edge of MCLK within nECS active region Users may be curious about the figure 4 22 nOE s de asserting before the point of data reading If nOE has to be de asserted after the point of data reading use tcoh 0 which defines the time between nOE s de asserting and nECS s de asserting Setting tcoh as 0 nOE is de asserted after the point of data reading as the user wants In reality extra bank can t be configured It is an imaginary bank for planning the special I O ELECTRONICS 4 21 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR Special I O Address One SRAM control registers have dedicat
324. ster 6 0 Minute Counting Value 0 59 Figure 22 4 BCDMIN Counter Register 22 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR REAL TIME CLOCK BCDHOUR COUNTER REGISTER BCD count register for hours BCDHOUR 0xc878 RTC hour register 5 0 Hour Counting Value 0 23 Figure 22 5 BCDHOUR Counter Register BCDDAY COUNTER REGISTER BCD count register for days 5 0 Day Counting Value 1 28 29 30 31 Figure 22 6 BCDDAY Counter Register ELECTRONICS 22 5 REAL TIME CLOCK KS32C65100 RISC MICROPROCESSOR BCDDATE COUNTER REGISTER BCD count register for the date BCDDATE 0xc880 RTC date register 7 6 5 4 3 2 1 0 2 0 Date Counting Value 1 7 Figure 22 7 BCDDATE Counter Register BCDMON COUNTER REGISTER BCD count register for months BCDMON 0xc884 RTC month register 4 0 Month Counting Value 1 12 Figure 22 8 BCDMON Counter Register 22 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR REAL TIME CLOCK BCDYEAR COUNTER REGISTER BCD count register for years BCDYEAR 0xc888 RTC year register 7 0 Year Counting Value 0 99 Figure 22 9 BCDYEAR Counter Register ELECTRONICS 22 7 KS32C65100 RISC MICROPROCESSOR CLOCK SAVE amp PLL CONTROL CLOCK SAVE amp PLL CONTROL OVERVIEW PLL is used to generate a higher internal clock from a low external clock source Clock saving provides that power dissipation of the periphery decreases in sleeping mode SYSTEM CLOCK div
325. ster which is used to monitor the status of VIS operation VISSR 0xa800 R VIS status register 0 Read request VISSR 0 is automatically set to 1 whenever the scaled image data has been prepared in DstReg When it is 1 it indicates that you can read the scaled results from DstReg 1 Write request VISSR 1 is automatically set to 1 whenever the VIS operation for all the data in SrcReg has been completed When it is 1 it indicates that you can write the next source data to SrcReg a 2 Busy flag VISSR 2 is automatically set to 1 whenever VIS operation starts and when it is 0 VIS is in an idle state 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 sd 0 Read Request 0 No request to read DstReg 1 Request to read DstReg 1 Write Request 0 No request to write SrcReg 1 Request to write SrcReg 2 Busy Flag 0 VIS be in an idle state 1 VIS be in progress NOTE During VIS operation if read request and write request occur simultaneously i e the VISSR s content is 1112 the S W should read the DstReg first and then write the next source data to SrcReg Figure 26 4 VIS Status Register VISSR ELECTRONICS 26 5 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR VIS Control Register The VIS control register VISCON controls the VIS half toning operation Two bits in this register are used to respectively enable the VIS half toning
326. sters or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 28 27 25 24 23 22 21 20 19 16 15 0 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write Back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or force user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtrack offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 36 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre post bit P and the up down bit U The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lowest register also gets transferred to from the lowest memory address By way of illustration consider the transfer of R1 R5 and R7 in the case where Rn 0x1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed
327. syn clk 0 No operation 1 Write strobe 7 Write Enable Asyn Enable 0 Disable 1 Enable 9 8 Default Phase 00 AB 01 AzB 10 AzBz 11 ABz 11 10 Phase A Current Control IAO 1 A1 00 Full step 01 Half step 1x Quarter step 12 Direction 0 Up 1 Down 13 Holding Enable 0 Normal state 1 Holding state 14 Phase Change Enable 0 Disable 1 Enable 15 Initial Drive State Control Write Only 0 Initialize 1 Normal Figure 17 4 CR State Control Register ELECTRONICS 17 5 CR CONTROL KS32C65100 RISC MICROPROCESSOR CRSREG Each Control Register This register is used to set the active current level for each step in bi polar mode You can refer to the phase state and current table the next page for detailed current level of each step CRSREG 0x6030 CR step each control register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 0 CRSREG Each Control Register Figure 17 5 CRSREG Register 17 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR CONTROL Phase State and Current Table for Full Half Quarter Step Mode Phase Current State amp Level Each Holding State Control Register 1 1 Register AB 1 33 100 0 33 3396 1 33 66 1 CW A B 1 1 0 0 100 0 0 33 CCW AJB 1 0 66 1 AzB 1 33 100 0 33 3396 1 33 66 1 AzB 0 0 100 100 0 33 33 1 1 66 66 1 AzB 0 100 33 0 33 33 66 33
328. t oe RTC_XIN 1N4148B 1N4148B R845 R85 R86 R87 88 A 10k 10k 10K 33 32 7 6BKHz Bn BATTERY AS C14 10UF 16V lt RTC PART gt R89 4 7k C ES R90 4 7k H ESTE R91 4 7k lt ICE INTERFACE PART gt lt TEST S W PART gt lt _1 RTC_XOUT Figure 29 5 Evaluation Board Schematic 2 ELECTRONICS 26 9 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR TXD1 GOPA1 TXD2 GOPA2 C4 3 3UF 10k NE H2 L11XD0 GOPA0 T RXDO GIPO ie R2in R2out RXD1 GIP1 C8 330H RXD2 GIP2 R39 R49 R31 R38 54K 57 120 PPO O 7 R58 R66 39 Y PERROR CT FD GIP17 R70 200 nSLCTIN GIP16 R71 200 LT IP15 R73 200 uon qOQO OO0 OuRONLAO 151 C16 C17 C108 C18 C19 C20 C22 C23 C24 C25 1108 220 220 2209 2204 220d 2208 220 220 2208 220d lt PARALLEL PORT gt Figure 29 6 Evaluation Board Schematic 3
329. t is 0 the stop interrupt is not generated the interrupt which is generated when the DMA counter is expired cannot be masked by this bit 9 Reset If this bit is set to 1 the CDMA control register value will be initialized When this bit is cleared to 0 you can specify other control values 10 Peripheral direction When the mode bit is set to 10 parallel port from to memory 11 UART from to memory this direction bit specifies the direction of the CDMA operation If this bit is set to 1 then CDMA operates from memory to peripheral parallel port UART If this bit is cleared to 0 CDMA operates from peripheral to memory ELECTRONICS 9 9 DMA KS32C65100 RISC MICROPROCESSOR 11 Single Block mode This bit determines the number of external CDMA requests nXDREQ that are required for CDMA operation At single mode this bit is set to 0 the KS32C65100 requires an external DMA request for every CDMA operation At block mode this bit is set to 1 the KS32C65100 requires only DMA request during the entire CDMA operation An entire CDMA operation is defined as the operation of CDMA until the counter is O 13 12 Transfer width This determines the width of the data being transferred to be a byte a halfword or a word If byte operation is set then source destination address will be increased decreased by 1 If it is a halfword then the address is changed by 2 If it is a word the address is changed by 4
330. t the offset appropriately ELECTRONICS 3 51 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS MRC MCR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between ARM7TDMI and a coprocessor An example of coprocessor to ARM7TDMI register transfer MRC instruction would be a FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM7TDMI register A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the CPSR flags As an example the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution 28 27 24 23 21 20 19 16 15 12 11 8 7 543 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Uumber 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to Co Processor 1 Load from Co Proce
331. t to the printer CIS sensor control Digital shading correction GAMMA correction Magnification reduction Photo text mode binarization IMAGE PROCESSOR SPECIAL REGISTERS SENSOR SHIFT CLOCK CONTROL REGISTER SEN CLK 0x9800 Sensor shift clock control register 0x00818 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 7 0 SEN CLK LOW Indicates the sensor shift clock s low period in system clock units 15 8 SEN CLK HIGH Indicates the sensor shift clock s high period in system clock units NOTE The SEN CLK s and periods are chosen according to the type of sensor being used For example for a DYNA with a 25 period you should input the values HIGH 08H and LOW 18H reset value and for a CANON with 5096 period each value should be set to 10H 16 Sensor CLK LOW ACTICE The SI signal and sensor shift signal s phase can be changed according to the sensor characteristics 0 High Active 1 Low Active 17 PHASE1 PHASE2 0 DYNA 1 channel CIS 1 CANON 2 channel CIS Figure 21 2 Sensor Shift Clock Control Register 21 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR SENSOR SI CLOCK CONTROL REGISTER SI TERM 0x9804 Sensor SI clock control register 0x09c4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 12 0 51 TERM This register decides on the
332. ta specifies the amount in the counter Figure 19 4 Fire Strobe Delay Timer Observation Register 19 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINT HEAD PRE HEAT PULSE TIMER OBSERVATION REGISTER This 6 bit timer is used for the pre heat pulse enable duration counter value The observation register is read only which is of the current value PHPTR 0x7028 Pre heat pulse timer register PHPTOR 0x702c R Pre heat pulse timer observation register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 5 0 Counter Value This data specifies the amount in the counter Figure 19 5 Pre Heat Pulse Timer Observation Register PRE HEAT DELAY TIMER OBSERVATION REGISTER This 6 bit timer is used for the pre heat delay enable duration counter value The observation register is read only which is of the current value PHDTR 0x7030 Pre heat delay timer register PHDTOR 0x7034 R Pre heat delay timer observation register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 5 0 Counter Value This data specifies the amount in the counter Figure 19 6 Pre Heat Delay Timer Observation Register ELECTRONICS 19 5 PRINT HEAD KS32C65100 RISC MICROPROCESSOR PRINTHEAD OBSERVATION REGISTER PHOR 0x7038 R Print Head observation register 0x0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 0
333. tch the contents of the band buffer to fill its FIFO The data fetch operation is performed by PDMA and queued PDMA operations are supported by PIFC specially for the print task with a large amount of video data The principle of queued operation is that to divide the whole video data into several data blocks The first block of data is transferred by DMA queue 0 and the second block is transferred by DMA queue 1 and during one queue operation the other DMA queue can be set to prepare for next block transfer so that the next block transfer operation can start as soon as the previous block transfer operation is completed The switching between two DMA queues is implemented automatically by a data fetch controller so as to guarantee the continuity of data transfer Normally an EOP End of Page interrupt is posted when a whole page video data transmission is completed and then the PIFC returns to idle However an abnormal interrupt PUR Page Under run may be generated if one DMA queue is not been ready when another DMA queue operation is completed Current State Printing Queue 0 is Next Queue is INT EOP Enabled Here Enabled Here ZZ INT_SOD 2 1 Queued Operation CNN URN Control PDMACR A4 M 5 Queued 0 Enable Enabled Enabled 5 PDMACR 2 Queued 1 Enable E PDMACR S 2 Enabled 9 Current Queue Auto Reset Figure 25 1 Queued Operation for End of Page EOP 25 2 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRIN
334. te back was requested This ensures recoverability in the case where the base register is also in the transfer list and may have been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 11 and LDM PC takes 1 5 2N 11 incremental cycles where 5 and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STM instructions take n 1 S 2N incremental cycles to execute where nis the number of words transferred 3 40 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDM STM gt cond lt FD ED FA EAIIA IB DA DB gt Rn lt Rlist gt where cond Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 1 If present requests write back W 1 otherwise 0 If present set S bit to load the CPSR along with the PC or force transfer of user bank when in privileged mode Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes
335. th i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 or bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles Enter with seed in Ra 32 bits Rb 1 bit in Rb Isb uses Rc TST Rb Rb LSR 1 Top bit into carry MOVS Rc Ra RRX 33 bit rotate right ADC Rb Rb Rb Carry into Isb of Rb EOR Rc Rc 5 12 involved EOR Ra Rc Rc LSR 20 similarly involved new seed in Ra Rb as before MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 24n 1 2 4 8 16 32 MOV Ra Rb LSL n Multiplication by 24n 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 24n 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS 3 57 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR Multiplication by 6 ADD Ra Ra Ra LSL 1 Multiply by 3 MOV Ra Ra LSL 1 and then by 2 Multiply by 10 and add in extra number ADD Ra Ra Ra LSL 2 Multiply by 5 ADD Ra Rc Ra LSL 1 Multiply by 2 and add in next digit General recursive method for Rb Ra C C a constant 1 If C even say C 2 n D D odd D 1 MOV Rb Ra LSL n D lt gt 1 Rb Ra D MOV Rb Rb LSL n 2 If C MOD 4 1 say 2 n D 1 D D 1 ADD Rb Ra Ra LSL n D lt gt 1 Rb Ra D ADD Rb Ra Rb LSL n 3 If C
336. the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 11 incremental cycles to execute where S are defined as sequential S cycle non sequential and internal I cycle respectively ASSEMBLER SYNTAX lt SWP gt cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B If B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers Examples SWP RO R1 R2 Load RO with the word addressed by R2 and store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and store bits 0 to 7 of R3 at R4 SWPEQ RO RO R 1 Conditionally swap the contents of the word addressed by R1 with RO 3 44 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 24 23 1111 Comment Field ignored by processor 32 28 Condition Field Figure 3 24 Software Interrupt Instruction The software interrupt instruction is used to enter supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR_sve If the
337. the source size register is set to 4 and the destination size register is set to 5 then the image scaling ratio is 5 4 For integral ratio image scaling each pixel of input source image scanline is replicated by hardware according to the specified scaling ratio to generate the destination image scanline output This operation is the same as the image expander s operation mentioned before except that in this unit the expanding factor can be an arbitrary integer However for fractional ratio image scaling hardware performs the pixel replication following a particular algorithm The hardware has to decide which pixel in input source image scanline should be replicated or how many times it should be replicated with specified fractional scaling ratio ELECTRONICS 26 1 VARIABLE IMAGE SCALING KS32C65100 RISC MICROPROCESSOR ALGORITHM The VIS algorithm is given out in the form of a C program as shown in Figure 26 1 CORO CORO Variable Descriptions Y Pixel IDx Pixel position in destination data register 7 Pixel IDx Pixel position in source data register Dst_Size Destination size register s setting value Src Size Source size register s setting value DstReg Destination data register SrcReg Source data register ARERR VIS Operation Frac 0 Dst Pixel 0 Src Pixel IDx 0 for i
338. tions and data are always fetched from external memory 532 65100 can also provide non cacheable areas in cache enable mode for some particular memory access operations such as the DMA operation The two non cacheable areas are specified by four special registers to be introduced later Programmers have to be cautious about data coherency when cache memory is enabled again because cache memory does not have auto flush mode Programmers also have to be cautious if DMA changes memory data The DMA access memory area must be non cacheable for keeping the data coherency To keep the data coherency between the cache and external memory KS32C65100 uses the write though method Write Buffer Operation KS32C65100 has four write buffer registers to enhance the memory writing performance When write buffer mode is enabled CPU writes data into the write buffer instead an external memory when the external bus was already occupied by other bus masters like DMA The write buffer has 4 registers and each register includes 32 bits of data field 25 bits of address field and 2 bits of status field 02 01 00 01 00 31 30 02 01 00 31 0 Write Buffer Data Data to be written into external memory 1 0 MAS 00 8 bit data mode 01 16 bit data mode 10 32 bit data mode 11 Not used 24 0 Address Indicates the address of write data Figure 5 3 Write Buffer Configuration 5 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CACHE CONTROLLER CACHE
339. toning operation and select the dot mode to be introduced below Since the data register is 16 bit while the input image pixel data is 8 bit two pixels are input and processed at the same time To carry out the half toning operation S W runs in the following steps control register s 0 bit VISCON O as one to enable the VIS operation and set the VISCON 1 to select dot mode e Write two pixel thresholds to Refln register s lower 8 bit and upper 8 bit to provide two pixel reference data e Write two pixel data of source image to register s lower 8 bit and upper 8 bit to compare with reference e Repeat steps 2 3 seven times and then read the HftReg to obtain the 16 bit output i e the 16 pixels s data of halftone image e Repeat steps 2 4 until all pixels of source image are processed The half toning algorithm is described in Figure 26 3 in which two kinds of dot modes are included The dot mode selection in half toning operation depends on the setting of VISCON 1 Dot mode 0 if source pixel data gt reference data halftone pixel data 0 else halftone pixel data 1 Dot mode 1 if source pixel data reference data halftone pixel data 1 else halftone pixel data 0 Figure 26 3 Half toning Algorithm Description 26 4 ELECTRONICS KS32C65100 RISC MICROPROCESSOR VARIABLE IMAGE SCALING SPECIAL REGISTER VIS Status Register The VIS status register VISSR is a read only regi
340. top printing When VCON 5 is set to 1 PIFC stops printing and generates the End of Page interrupt INT EOP and then VCON 5 is auto cleared to 0 and all of PIFC state is reset 25 6 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PRINTER INTERFACE CONTROLLER ELECTRONICS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 Reserved 1 nPRINT Signal 0 nPRINT signal with high level 1 2 nPRINT signal with low level 2 Print Synchronization Signal 0 nPSYNC signal with high level 1 2 nPSYNC signal with low level 3 Video Clock Inversion 0 Invert video clock VCLK 1 Don t invert video clock normal 4 Shift Direction of Video Data Transmission 0 MSB first 1 LSB first 5 Stop Printing 0 Normal operation 1 Stop printing and generate interrupt Figure 25 5 Video Control Register VCON 25 7 PRINTER INTERFACE CONTROLLER KS32C65100 RISC MICROPROCESSOR PATTERN CONTROL REGISTER Settings in the printer interface controller s pattern control register PCON control various video data functions including video data polarity border data polarity video clock selection clock divisor shrink pattern data chopping selection for toner savings and image expanding 0 Video data polarity When PCON O0 is 0 the video data that the KS32C65100 sends to the printer engine is inverted Otherwise the video data sent in a non inverted stream
341. truction The abort mechanism allows the implementation of a demand paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 for a prefetch abort or SUBS PC R14_abt 8 for a data abort This restores both the PC and the CPSR and retries the aborted instruction 2 12 ELECTRONICS KS32C65100 RISC MICROPROCESSOR PROGRAMMER S MODEL Software Interrupt The software interrupt instruction SWI is used for entering supervisor mode usually to request a particular supervisor function A SWI handler should return by executing the following irrespective of the state ARM or Thumb MOV 14 This restores the PC and CPSR and returns to the instruction following the SWI NOTE nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM7TDMI CPU core Undefined Instruction When ARM7TDMI comes across an instruction which it cannot handle it takes the undefined instruction trap
342. truction as shown in Table 3 20 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD SP 268 SP R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the Word7 value and S 0 ADD SP 44 104 SP R13 SP 104 but don t set the condition codes Note that the THUMB opcode will contain 26 Word7 value and S 1 3 82 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 14 PUSH POP REGISTERS 7 0 Register List 8 PC LR Bit 0 Do not store LR Load PC 1 Store LR Load PC 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 43 Format 14 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 3 21 NOTE The stack is always assumed to be full descending Table 3 21 PUSH and POP Instructions S H THUMB Assembler Equivalent PUSH Rlist STMDB R13 Rlist Push the registers specified by Rlist onto the stack Update the stack pointer PUSH Rlist LR STMDB R13 Rlist Push the Link Register and the registers R14 specified by Rlist if any onto the stack Update the stack pointer 1 POP Rlist LDMIA R13 Rlist Pop values off the stack into
343. ts the ADC signal s starting point in units of system clock for the register value The figure below shows the ADC controlling diagram for a product using the 2 channel method such as CANON SEN CLK BASIS CNT 7 0 ADC CLK 0 ADC Clock Sample Figure 21 21 ADC Control Timing Diagram CANON As shown in the figure above the range of the ADC STAR 7 0 value that adjusts the ADC signal location becomes 1 2 of the SEN CLK s LOW period from 1 and the ADC signal s high period B becomes LOW 2 For product using the 1 channel method such as DYNA CIS refer to the diagram below 21 16 ELECTRONICS KS32C65100 RISC MICROPROCESSOR IMAGE PROCESSOR SEN CLK SEN CLK LOW SEN CLK HIGH ws M i B i 7 0 ADC Clock Sample Figure 21 22 ADC Control Timing Diagram DYNA In this case you need a 25 DUTY so the SEN CLK s HIGH period and low period are added to make the ADC signal s high period Therefore the width of B in the figure above is SEN LOW SEN 2 MOTOR CONTROL There are 6 port phase outputs for motor control Each output signal can be adjusted by S W In other words the register MOTOR TERM 15 0J s value can change the interval value for the changing motor phase An interrupt occurs every time a signal signifying the interval is generated so the S W changes the register value using that signal which lat
344. two states does not affect the processor mode or the contents of the registers SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state Entering ARM State Entry into ARM state happens e execution of the BX instruction with the state bit clear in the operand register processor taking an exception IRQ FIQ RESET UNDEF ABORT SWI etc In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address MEMORY FORMATS ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to hold the first stored word bytes 4 to 7 the second and so on ARM7TDMI can treat words in memory as being stored either in Big Endian or Little Endian format NOTE The KS32C65100 is configured to the big endian format ELECTRONICS 2 1 PROGRAMMER S MODEL KS32C65100 RISC MICROPROCESSOR BIG ENDIAN FORMAT In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher Addr
345. uction 0 1 Unsigned halfwords 1 0 Signed byte 1 1 Signed byte 11 8 Immediate Offset high nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write Back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset before transfer 31 28 Condition Field Figure3 17 Halfword and Signal Data Transfer with Immediate Offset and Auto Indexing ELECTRONICS 3 31 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSOR OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be 0 In the case post indexed addressing the write back
346. ue Figure 17 5 PWM Counter Base Register Caution Real cycle time base value 1 x 1 MCLK Real on time base value 1 x 1 MCLK This block only operates in DC mode 17 8 ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR CONTROL ENCODER COUNTER Logic Configuration This block is configured of a 20 bit up counter and a 20 bit register for storing the counting results Function e tcounts the period of the photo sensor encoder sensor input and stores the value in the register e The period is used as a base value for calculating the fire strobe and fire window time according to the setting of the fire Countering Result Register and Observation Register ECDTIM 0x6020 O R Encoder counter observation register 0x20292 ECDVAL 0 6024 R Encoder cycle value register 0x00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 19 0 Encoder Cycle Register Figure 17 6 Encoder Cycle Register Caution This block only operates in DC mode ELECTRONICS 17 9 CR CONTROL KS32C65100 RISC MICROPROCESSOR INTERRUPT INTERVAL COUNTER Logic Configuration This block is composed of a 16 bit up counter and a 16 bit register for storing the counting results Function e This logic starts operating after the first DC motor interrupt is generated e counts the interval between each DC motor interrupt and the next and stores the value in the register e
347. ve unless finished Divide result in Rc remainder in Ra 3 to 6 cycles 1 cycle and a register 3 to 6 cycles 1 cycle and a register 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 4 to 7 cycles 1 cycle and a register 4 Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE 3 56 Rd Rt Rm Rn Rt Rd ASR 31 overflow 4 to 7 cycles 1 cycle and a register ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL RI Rh Rm Rn 3to6 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BCS overflow 1 cycle and 2 registers 6 Overflow in signed multiply accumulate with a 64 bit result SMULL RI Rh Rm Rn 3to6 cycles ADDS Lower accumulate ADC Rh Rh Ra2 Upper accumulate BVS overflow 1 cycle and 2 registers NOTE Overflow checking is not applicable to unsigned and signed multiplies with a 64 bit result since overflow does not occur in such calculations PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo random numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal leng
348. which generated the data abort 4 The value saved in R14 svc upon reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimising the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending on the state of the ISYNC input signal When ISYNC is LOW nFIQ and nIRQ are considered asynchronous and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14_fig 4 FIQ may be disabled by setting the CPSR s F flag but note that this is not possible from user mode If the F flag is clear ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction ELECTRONICS 2 11 PROGRAMMER S MODEL KS32C65100 RISC MICROPROCESSOR IRQ The IRQ Interrupt Request exception is a normal interrupt caused by a low level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting the bit in the CPSR though this can only be done from a privileged non User mode Irrespective o
349. will the repeat counting with current base value until the timer is disabled In order to set DC motor mode bit 9 of CMCR has to be set 1 For the step motor mode CMCR 1 1 4 has to be set zero ELECTRONICS KS32C65100 RISC MICROPROCESSOR CR CONTROL SPECIAL FUNCTION REGISTER Carrier Motor Control Register This register determines whether the interrupt request is generated or not and enables or disables the prestep timer and basic timer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ff ef 0 Basic Timer Enable 0 Disable 1 Enable 1 Preset Timer Enable 0 Disable 1 Enable 2 Carrier Step Interrupt Enable 0 Disable 1 Enable 3 Only for Test Initial 1 4 DC Motor Output Enable 0 Disable 1 Enable 5 DC Motor Output Selection Direction 0 DCOUT1 is enabled DIR 0 1 DCOUT2 is enabled DIR 1 6 PWM Timer Run 0 Stop 7 PWM Mode Selection 0 2 PWM signal mode 1 1 PWM and direction signal mode 8 Preceding Encoder Input Selection 0 CHX 1 9 Motor Type Selection 0 Step motor 1 DC motor 10 Head Type Selection in DC Mode 0 208 nozzle head 1 56 nozzle head 11 Overflow Interrupt Enable 0 Disable 1 Enable DC interrupt causing overflow of interrupt interval counter Figure 17 1 Carrier Motor Control Register ELECTRONICS 17 3 CR CONTROL KS32C65100 RISC MICROPROCESSOR Basic Timer Base
350. with match function HDMA SPECIAL REGISTERS HEAD DMA CONTROL REGISTER This DMA has a kind of DMA operation under the control of the print module HDMA reads from memory and writes to head HDMA can transfer data by bytes half words The transfer size is decided by setting the head control register HDCON 0x7800 Head DMA control register 0x0000000 0 Run enable disable When you set this bit to 1 operation starts To stop you must clear this bit to 0 If you control this bit only 0x7810 address will be used if 0x7810 address is used other value will not be changed 1 BUSY status When HDMA starts this read only status bit is automatically set 1 When it is 0 is in idle status 2 Source address direction Only one source can initiate an HDMA operation If this bit is set the source address will be decreased If this bit is cleared the source address will be increased 3 Source address fix This bit determines whether the source address will be changed or not during an HDMA operation This feature is used when transferring data from a single source to multiple destinations 4 Reset If this bit is set to 1 then the control register value will be initialized after this bit is cleared to 0 you can specify other control values 5 Not Used 6 Match pend status If the value of the source address register HDSAR and the value of the match address register HDM
351. xpects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary on data bus inputs 23 through to 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A halfword load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary on data bus inputs 15 through to 0 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit O of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour NOTE The KS32C651000 is configured to the big endian format USE OF R15 Write back should not be specified if R15 is specifie
352. y the system initialization and memory configuration for KS32C65100 evaluation board performed by the Boot Code can be completed first Otherwise it may cause the failure of code download via Embedded ICE DEBUG APPLICATION WITH EMBEDDEDICE Install ARM Tool kit for Windows Run the Hyper Terminal in host PC 1 2 3 Configure the serial port settings of the Hyper Terminal as 38400bps 8 bit data no parity and 1 stop bit 4 Install the evaluation board and Embedded ICE interface as Figure 29 3 5 Power on the board and Embedded ICE Configuring the ARM Windows Debugger 1 the ARM Windows Debugger 2 Select Options configure Debugger Debugger menu to set Big for Endian item 3 Select Options configure Debugger Target menu to set Remote A for Target Environment item 4 Click Configure button in Options configure Debugger Target menu to open the Angel Remote Configuration window In this configuration window you select serial or serial parallel for Remote Connection item select an appropriate COM port select an appropriate baud rate for serial line speed and then click the OK button to end the configuration Click the OK button in Options configure Debugger to conclude the debugger configuration Select File Exit menu to quit the ARM Windows Debugger Debugging the application with Embedded ICE 1 Run the ARM Project Manager Open Hello apj in directory example ICEdbg Click
353. y 64K byte address steps The last 64K bytes area cannot be allocated as memory banks except SFR Because the last 64KB bank is 1FFxxxxh the next pointer of the last bank should have 1 200xxxxh but it has 000xxxxh because the next pointer is 9 bit If a user needs to utilize the full 32M bytes of memory space you are recommended to allocate the SFRs to the last 64k byte area 1FF0000h 1FFFFFFh and other banks for the rest of the area For programming convenience programmers want to get rid of scattered memory area and want to have consecutively connected memory space without any blank areas KS32C65100 s configurable memory allocation methodology provides a very adaptive solution for this type of requirements You can move the memory area easily by only changing the SMR ELECTRONICS 4 3 SYSTEM MANAGER KS32C65100 RISC MICROPROCESSOR When you try to change physical DRAM memory size for example from 1MB to 2MB user can easily change memory configuration by modifying the system manager register SMR in the KS32C65100 microcontroller KS32C65100 provides two DRAM banks and changeable memory space that has configurable DRAM size to 2M word So then you can enlarge memory space just by changing the end point of the DRAM bank SYSTEM REGISTER ADDRESS CONFIGURATION REGISTER SYSCFG The KS32C65100 System Manager Registers SMR have a register which determines the start Base point address of the Special Function Register SFR files It is t
354. y adding together the value in Rb and Imm Store the contents of Rd at the address LDR Rd Rb lmm LDR Rd Rb lmm Calculate the source address by adding together the value in Rb and Imm Load Rd from the address STRB Rd Rb lmm STRB Rd Rb lmm Calculate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address LDRB Rd Rb LDRB Rd Rb lmm Calculate source address by adding together the value in Rb and Imm Load the byte value at the address into Rd NOTE For word accesses B 0 the value specified by is a full 7 bit address but must be word aligned ie with bits 1 0 set to 0 since the assembler places gt gt 2 in the Offset5 field 3 76 ELECTRONICS KS32C65100 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 16 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 0 131 Store the lower 8 bits of R1 at the address formed by adding 13 RO Note that the THUMB opcode will contain 13 as the Offset5 value ELECTRONICS 3 77 ARM INSTRUCTION SET KS32C65100 RISC MICROPROCESSO

Download Pdf Manuals

Related Search

Related Contents

User manual S Class series  インフラストラクチャーモード  1 仕様書 基本仕様に徹した低価格ISAボード  User manual for PIR Video Camera  BFC-E Manuel d`utilisation - CNRS  Supermicro SYS-7047A-T server barebone  Exceleram 12GB PC3-10666  Anhang  SE615 and SE675 User Manual – English  Severin EK 3157  

Copyright © All rights reserved. Failed to retrieve file