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CPU87-Manual

1. 5 2 SCC 1 SMC 1 2 Page 80 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Appendix B Layout Component Side Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 81 of 84 2000 2007 MicroSys Electronics GmbH ys MicroS Made for Professionals OOOO 000000 6 00 O O 0 000000000 00 0000150 9 QO QOO 0 O0 OO OOO 0 0 QUO Q Q OFC 050900100 O66 40 OO OOOO OO 0000000000 000000000 000002200 gt _ 71111111 0000000500 00000000000000000000000001 5TB eh MCHI MCH2 MCH3 DLLE RSRV
2. extshare acces disabled x x 9 s on The following AM Codes are necessary for the shared SRAM access AMS AN ANG AMD AMI Aes TT L logical low H logical high Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 33 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 3 The Bus The bus onboard the CPU87 is controlled via the SDA port D15 and SCL port D14 pins of the MPC8270 and contains a real time clock EEPROM and a system hardware monitor device 6 3 1 The EEPROM The CPU87 offers a 16KBit serial EEPROM for storing system or board parameters The X24C164 device is internally organized to 2048 x 8 bit and allows for at least 100000 write cycles with a typical cycle time of 5ms The 24C164 device responds on the bus at the odd addresses from B1 to BF for read and on the even addresses from to BE for write accesses E For detailed programming information and chip description please refer to X24C164 Data Sheet 6 3 2 The Real Time Clock The PCF8563 RTC features a clock function with a calendar and an universal timer with alarm and interrupt function The RTC is protected against data loss by a backup circuitry The backup feature supplied from a service free gold capacitor cannot be disabled For long time applications the VMEbus standby line on ST1B pin 31 can be used to
3. 5 5 Is 3 ammo I ls ps IRO Ins mann x x NEC imei sive Page 52 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 3 The VMEbus Interface The VMEbus interface of the CPU87 is designed according to the VMEbus specification ANSVIEEE STD1014 1987 IEC 821 amp 297 The VMEbus connector 571 rows A B and C and ST2 row B contain all standard VMEbus lines necessary for A16 A24 A32 D8 D16 D32 mas ter slave boards All unused daisy chain lines are linked through i e no external bypass links are necessary The address modifier signals AMO to AMS are part of the VMEbus specification and serve to differentiate between certain memory areas All address modifier lines are necessary for the mailbox and the shared access decoding logic The CPU87 accepts only slave data accesses within the VMEbus short I O range the VMEbus standard access area and the VMEbus extended access range The following AM Codes are accepted by the CPU87 ane ano n ae aman __ Standard User Data 39 Short I O Supervisory Data 2D Short I O User Data 29 Extended Supervisory Data OD Extended User Data 09 logical low H logical high The CPUS7 is able to generate user or supervisor data or program
4. mon EA HE o 0000000000000 0000000000 _ 0000 00000 0000003 00600 1111111 11011711711 00 010 00 00 00606 L0 0E C B 5 f 1 20000 04 ae o me WBS ree e7 00000 fm OD m ID 80009 8 124 20000 ini 5 i c mr B mmm m rti no Ass 00000000000000000000000000000 00000000000000000000000000000 00000000000000000000000000000 00000000000000000000000000000 00000000000000000000000000000 00000 RM32 bL 00000 00000 RM38
5. C14 ANG 00000 05C2 CPU874AB DOC 2000 2007 MicroSys Electronics GmbH i Date 5 ivierung Arch EW285MA 04AB P C I OL 1 00 U 0 2 amt 138 O p 00000000 00000000 1 N D3u i E ce DO gn 0000 58885 b m HHH AIB RIS R28 R21 RS RIO RIZ 513 7 0000 OOOO 0000 0000 0000 0000 OOOO 0000 Page 82 of 84 VS oo GH n Wz o O Lg gt D e e O 0 000 00x o gt 9 gt gt O Oo OOO OO 82000 0 00 0000 0 DD css enn Edles ess 00 57 wenn OOe7 00 es sa DO A 00 ess OD ess 5 o 000000 oo o mieten ne AM a
6. 00 0000 zz DO pa 5133 1 Res R4 SD TE lt 5 00 GE ces DESDE pp a cnz DO 7 Ee sies 00 Dns 00 128 SS 0000000 DU ces ID co De Ge gg 2 DOD ca s 09 ewe Gg cw OO a ol cn 80 o G 6 OU QU Co 00 ces 00 ce de 5 1 LL EB n GO DD mas 00 cse DO cse BD an 10 DO DD 09 Dre 73 R75 65 R74 00 17 00 ivierung lt 00 pp ug ey Cate pes Layout Solder S da 80 00 89 O e200 DOr 00 DO UU 7 ED n d 00 6 DD eve CM sel EDU pm a d w00 00 OO 2400D OO 7 9 ED an me ne mm III e ms tn RS Rss lt DU 5 0000 Hg 00 ED 59 Gor DD 00 a d Ss o 4 nm no 950800 969 EDED oo bi dd EN EDED ED DED CD Der en 0g 00 gt 00 o as oo Mer an D 4200 20 00 r5 DO o M
7. X ___ 13MHz 33 133MH 165MHz X X 10MH 128MHz 450MHz __ X 132MH po X 66MHz 198mH h Resulting clock rates with 50 MHz Oscillator OSC1 link installed link not installed The MPC8270 of the CPU87 is configured for the MPC8270 stand alone mode i e not for the 603e bus mode If the link RCFG is not installed the power up configuration is set to the internal default mode Otherwise the reset configuration word is taken out of the memory device con nected to the CS0 line of the 8270 The 64 bit flash area or the 8 bit ROM socket can be con figured as boot memory by jumper BTMD BTMD RCFG 50 connected to 8 bit socket CS1 connected to 64 bit Flash 50 connected to 64 bit Flash CSI connected to 8 bit socket Because of a special BCTLO BCTLI buffer control the configuration word must be always read from the boot device Only during the use ofthe BDM port the internal configuration word can be used Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 15 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 1 1 The Debug Port The JTAG COP interface of the CPU87 can be used via the 16 pin standard wrap connector JTAG according to following table Pin 1 TDO GND Pin 2 Pin 3 TDI TRST Pin 4
8. MicroSys User s Manual CPUS7 Rev 4 2 edition Declaration of Conformity We Manufacturer MicroSys Electronics GmbH M hlweg 1 D 82054 Sauerlach Germany declare that the product CPU87 is in conformity with EN 50081 1 Generic emission standard EN 50082 1 Generic immunity standard in accordance with 89 336 EEC EMC Directive We also declare the conformity of the above mentioned product with the actual required safety standards in accordance with Low Voltage Directive 73 23 EEC Date Signature Position General Manager The information in this document has been carefully checked and is believed to be entirely reliable However no responsibility is assumed for inaccuracies Furthermore MicroSys reserves the right to make changes to any product herein to improve reliability function or design MicroSys does not assume any responsibility arising out the application or use of any product or circuit described herein neither does it convey any license under its patent rights or the rights of others All rights reserved MicroSys Electronics GmbH 2001 MicroSys Made for Professionals Edition Date Ident Nr Released Manual 10 06 2002 EW285MA 04AA 13 12 2007 EW285MA 04AB Schematics 17 02 2003 EW285SL 04AA Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 3 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals MicroSys GmbH M hlweg 1 82054 Sauerla
9. 1 9 A A DO 00 5 YY SG oo S I oo a O de lt C NI 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Appendix D Schematics CPU87 on request Page 84 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH
10. connected to DiskOnChip connected to 413 VCC 413 PWEOH A16 A14 19 417 A24 418 A25 A23 A26 22 27 20 A28 POE A29 A21 A30 CS11 A31 D7 DI D6 D2 D5 D3 GND D4 The signals within brackets are not used by the DiskOnChip device but the socket might also be used for other pin compatible devices with a larger address range e g FLASH memory Page 30 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 4 1 Socket Pin out Please check for correct pin compatibility before mounting any device All 32 pin packages must be inserted into socket as shown below only during power down Any insertion of other types or not as directed may cause permanent damage to the device and or the board A18 O 32 16 WR 15 A17 12 Al4 O A13 48 AS TOP A9 A4 O All OE A2 VIEW 10 Al O O AO D7 O O D6 DI O O D5 D2 O O D4 GND O O D3 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 31 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 5 The Static RAM Area The CPU87 contains a static ram area consisting of two SRAM devices with 512Kx8 capacity which allows for a total capacity of IMBytes at a 16 bit wide data bu
11. 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of the L ocal Dnterrupt M ask R egister DI os os 4 CS6 82 7 PMC VSYF ISCM IRTC IFDC IMBX IABO read write reset ABORT key IRQ disable x ABORT key IRQ enable x Mailbox IRQ disable Mailbox IRQ enable FDC IRQ disable FDC IRQ enable RTC IRQ disable RTC IRQ enable LM81 IRQ disable LM81 IRQ enable VME SYS Fail disable VME SYS Fail enable PMC IRQ disable PMC IRQ enable VME AC Fail disable VME AC Fail enable 1 X X X X 1 X X X X X X X X X X X X X X X X X X X X X X E X X BEE EARE Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 51 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals The current state of each local interrupt source can be checked within the local interrupt status register at location CS6 83 The high active status of each interrupt line is valid at any time no matter ifthe according interrupt line is enabled or not Bit map of the L ocal Dnterrupt S tatus R egister nisi sessi o I pe www C aee me mx x x x x x x L7 MEE KE RI RT a FDC IRQ inactive x 0 x x x 0 x x FDC IRQ active x 0 x x x 1 x x ee
12. 24 Bit map of the V ME S tandard A ddress C ompare Register IE ee std shared access disabled fest amp eae ee std shared access enabled 0 1 0 1 ext shared access disabled 0 1 0 1 ext shared access enabled 0 1 compared with VME short I O access disabled short I O access enabled Requester RWDN mode Requester ROR mode suci sucus SHCRS sucus sucia sucia we ee compared with VME Al5 Al4 A13 A12 All 10 Page 62 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of the B oard C ontrol R e g ister Lace m lo vete uam us awr pun ee FT ee C N and 3 _ s s ps pels MEC ila Peck va eee eci Bit map of the B oard S tatus R e g ister case a Ts Tepe sw ame o emo a x ELI omoes x x 0 x a LE wud x x x x E E Loose x of x x x E E I 0 x x Lo E E I Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 63 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of the W atch D og R etrigger P ort Bit map of the C lear M ailbox Dnterr
13. The flash memory area of the CPU87 consists of four devices with a total capacity of 8MBytes as standard The 64 bit wide flash bank can be controlled via the CSO or the CS1 line on the 603 bus of the MPC8270 and no parity check is performed The selection between both CS lines is per formed via jumper BTMD If the links are set to BTMD 1 3 and BTMD 2 4 the main flash memory is connected to the CSO line while the boot flash memory is controlled via the CS1 line of the MPC8270 The data lanes of all devices are swapped according to the necessary endian conversion The WAIT pin is not connected and left floating The flash memory works in normal mode if the soldering link FA is set to position 2 3 The ADV pin is connected to ground by fac tory and must not be changed The pins of the Flash devices are controlled by the MPC8270 ac cording to following table CLK BENE TE enable vn we ie prote vi ps If the 64 bit wide main flash memory is used as boot memory it must contain the 4 bytes of the hard reset configuration word for the MPC8270 at its base address locations 00 08 10 and 18 0 EARB 0 8 I2CPC 0 16 BMS 0 CSIOPC 0 CSIOPC APPC ISPS 0 15 ISB APPC 0 MODCK 0 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 27 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 3 1 The FLASH Memory Write Protection The B oard C ontrol R e g ister at
14. FF93 FFFF FF94 0000 FF97 FFFF FF98 0000 FF9B FFFF FF9C 0000 FF9F FFFF FFAO 0000 FFA3 FFFF 4 0000 FFA7 FFFF FFAS 0000 FFAB FFFF FFAC 0000 FFAF FFFF FFBO 0000 FFB3 FFFF FFB4 0000 FFB7 FFFF 8 0000 FFBB FFFF 256 Kbytes FFBC 0000 FFBF FFFF 0000 FFFF 4 0000 FFC7 FFFF 8 0000 FFCB FFFF 0000 FFDO 0000 FFD3 FFD4 0000 FFD7 FFD8 0000 FFDB FFDC 0000 FFDF FFEO 0000 FFFF 4 0000 7 8 0000 FFEB FFFF FFEC 0000 FFEF 256 KBytes FFF0 0000 FFF3 FFFF 36 256 KBytes FFFA0000 FFF7FFFF 37 256 KBytes FFF80000 FFFBFFFF address 0100 Sector 0 7 32KBytes organized 4K x 64Bit 4 Flash Devices Sector 8 38 256K Bytes organized 32K x 64Bit 4 Flash Devices 7 10 11 12 13 14 15 16 17 18 19 20 21 N 23 24 25 26 27 28 29 30 31 32 33 34 35 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 29 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 4 The DiskOnChip Socket The CPU87 offers a 32 pin socket for mounting a 5 volt DiskOnChip device The selec tion of this device is handled via the CS4 line on the 603 bus side of the MPC8270 Its control data and address lines are connected according to the following table
15. VIMR CS6 80 DO D1 D2 D3 D4 DS D6 D7 VIM X X E x x ee BE WEH 5 48 Hr Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 47 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals The current state of each VMEbus interrupt line can be checked within the VMEbus interrupt status register at location CS6 81 The low active status of each interrupt line is valid at any time no matter ifthe according interrupt line is enabled or not Bit map of the V MEbus Dnterrupt S tatus R egister sma m D1 m or noe var x x x x x x x x Mengo nawe x x x weno x x x x x a x o x x x x x Page 48 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 7 2 1 The VMEbus Interrupt Acknowledge The necessary VMEbus acknowledge procedure must be performed by a read access within the address range from xxx80000 to xxx8FFFF of 59 decoded area This range works as a 16 bit device with an external acknowledge The data byte transferred on the data line D7 to DO during the acknowledge cycle can be used to distinguish between different interrupt sources on the same VMEbus interrupt level The
16. from Flash Rom address 00 08 10 and 18 or if a processor internal configuration is used Only with external configuration some settings like various clock rates can be used by repro gramming the Flash Note Internal configuration RCFG removed must only be set when the BDM port is used and no external hard reset configuration word is available 3 1 3 1 5 0 4 2 4 2 Boot from 8 bit socket Boot from 64 bit Flash Jumper RCFG must be installed Jumper RCFG must be installed and Hard Reset Config Word and Hard Reset Config Word must exist at address 00 must exist at address 00 If the 8 bit socket is used as boot memory it must contain the 4 bytes of the hard reset configura tion word for the MPC8270 at its base address locations 00 08 10 and 18 16 BMS 0 24 CSIOPC 0 2 CDIS O EOE DERG EO O 26 27 3 EBM 0 11 DPPC 0 0 4 BPS 0 2 0 20 LBPC 0 28 0 13 ISB O 21 LBPC 0 29 MODCK 0 6 0 14 ISB 0 130 MODCK 0 7 ISPS 0 15 ISB 0 23 0 31 MODCK 0 E For detailed information about the Hard Reset Configuration Word please refer to the MPC8270 User s Manual Page 26 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 3 The Flash Memory
17. 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 9 3 The Local Bus and PMC VO Connector Pin out ST2 ST9 ST2 Page 72 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 9 4 The PMC Module Slot The PMC module slot uses the connectors ST7 518 and ST9 The PCI configuration space 15 de coded by AD13 for this slot The PMC VO lines are connected via ST9 to the rows D amp E of the VG160 connector ST2 Attention Standard PMC modules work ONLY with processors offering PCI bus i e MPC8250 MPC8265 MPC8266 MPC8270 and MPC8280 The MPC8260 however does not support standard PMC PCI support Using PMC cards on a system with MPC8260 may cause per manent damage to the board and or the whole system Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 73 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 9 5 The PMC PCI Connector Pin out GND 3 4 INTA INTBH 5 6 INTCH ED 9 10 GND H 12 GND 39 40 LOCK SDONE 41 42 SBO PAR 43 44 GND VCC 45 46 ADIS 47 48 ADI AD9 49 50 59 6 ADI GND 63 64 REQ64 EE TENEO SAI RESET 13 14 VDD 15 16 17 18 GND GND 33 34 PERR
18. FFFF SFFOO 0000 FFTF FFFF Boot ROM Socket FF00 0000 FFOF FFFF gt Flash Memory Bank FF80 0000 SFFFF FFFF 2 BTMD Jumpers set to 1 2 and 3 4 2 BTMD Jumpers set to 1 3 and 2 4 Note The address map shown above reflects the standard MicroSys initialization Due to the flexibility of the MPC8270 memory controller nearly any customized address map may be defined Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 13 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 5 2 The I C Bus Address Map Te Tra Ti 24C164 EEPROM B0 BE B1 BF LM81 System Hardware Monitor 58 59 PCF8563 Real Time Clock A2 A3 Page 14 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 Functional Description 6 1 The PowerQUICC Processor The CPU87 uses the MPC8270 Power QUICC II RISC microprocessor from Motorola It can be configured for different CPU core and bus speed versions The MPC8270 contains a 603e com patible core with 16 Kbytes data cache and 16 Kbytes instruction cache It uses a 3 3 volt bus sup plyanda 1 8 volts core supply voltage The processor works with CPU clock rates up to 450 MHz and the according system clock rate varies from 50 to 100 MHz The desired clock configuration can be adjusted via the soldering link area MDCK according to the following table LX
19. MicroSys Made for Professionals 3 Installation 3 1 Items required for CPU87 installation For installation of the CPU87 the following items are required Card cage or housing VMEbus motherboard Adequate rated power supply 3 2 Points to be observed Before the unit is inserted into the card cage the following points should be observed Unit requires 5V 5 95 2 5 Unit requires 12V 5 2 5 90 for PMC extension Unit requires 12V 5 2 5 for PMC extension Be sure voltage is of correct polarity Check default jumper or switch setting The card cage must be well ventilated The operating temperature must never exceed its specified range GUARANTEE IS VOID IF UNIT IS OPERATED OUT OF IT S SPECIFICATIONS Page 10 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 4 Board Overview 4 1 Features CPU87 Board Format Main Processor Dynamic RAM Flash Memory Boot ROM Area Static DPRAM EEPROM DiskOnChip FD Interface Real Time Clock Serial Interfaces System Control Data Backup double euro card format MPC8270 with PowerPC 603e Core 64 Bit 603e bus 32 Bit local bus 16 Kbytes instruction cache 16 Kbytes data cache up to 450 MHz CPU core clock rate CPM interface with four SCCs amp one SMC four SDRAM devices 32 Mbytes ca
20. Pin 5 QREQ 2K2pullup Pin Pin 11 SRSTH Pin 12 Pin 13 HRST neo Pin 14 TG Pil Pin Pins Ping Pis ae Pins Pino Pin 13 Pis cKsrPO Page 16 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 1 2 The Processor Pin Configuration The MPC8270 offers a wide variety of pin functional swapping The CPU87 uses the multi func tional processor pins according to following table DPIIRQUEXT 2 A22 ABOIR interrupt DP2 ZIRQZ TLBISYNC EXT DBG2 221 SCMIR interrupt DPA IRQ4 CORE SRST EXT C21 RTCIR __ interrupt 5 IRQS TBEN EXT_DBG3 B21 CNAIR interrupt DP6 IRQ6 CSEO 21 CNBIR interrupt DP7 IRQZ CSEI E20 CNCIR interrupt RQUNMI OUT T1 NMIO amp interrupt pulup IRQUGBL WI notused IRQ2 BADDR29 C1 02 BADDR29 notused pulup IRQ3 BADDR30 WT 03 ATMIR interrupt IRQ4 L2 HIT YA I2HIT fnotused I 2 U4 BADDR3 notused pulup I DI INTO pulup E __ notused pulp IRQ3 DBB V2 DBB amp ___ notused pulp PBS7 PSDDQM7 PWE7 RQS BADDR3I CPU BG RQ7 INT OUT APE PGLPSIPSDAMUX D22 Inotused notconnected used functionality is shown in bold characters E2
21. VMEbus BTO feature offers a time out sequence of 27us starting at the falling edge of one or both VMEbus data strobes It will be automatically activated if the system controller function is enabled by jumper ARBE If the board is not system controller the bus monitor function of the VMEbus side is not disabled but the time out sequence is set to about 60 5 6 8 6 Preparations for VMEbus Multiprocessing In case a VMEbus system should be configured for more than one VMEbus master the user must verify that only one system controller is enabled in the whole system The system controller is usually located in the leftmost slot and drives the bus grant in lines of slot 1 It supplies the system with the system clock the system reset and optionally the bus error and the bus clear information All these lines with the exception of the system reset and the bus error signal are totem pole out puts and must be controlled only by the system controller within the VMEbus system The system reset and the bus error lines are driven by open collector circuits and might be driven by more than one board Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 61 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 7 Register Overview Bit map of the V ME E xtended A ddress C ompare Register EXCR7 EXCR6 5 4 EXCR3 EXCR2 EXCRI ic se Eee compared with VME A31 A30 29 28 27 26 25
22. bits wide and no parity check is performed The SDRAM contains 4 banks and supports auto refresh and self refresh with 4096 cycles during 64ms The pins of the SDRAM device are controlled by the MPC8270 according to following table E For detailed information about the SDRAM chip specification please refer to the according SDRAM data sheet Page 22 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 2 The Boot Socket The boot socket of the CPU87 is able to handle 32 pin JEDEC compatible 600mil standard 5V 8 bit wide ROM PROM EPROM or Flash device The device type selection is made by the 3 soldering links BA BB and BC The socket can be controlled via the CS0 or the CS1 line on the 603 bus of the MPC8270 The selection between both CS lines is performed via jumper BTMD If the links are set to BTMD 1 2 and BTMD 3 4 the 8 bit socket is connected to the CSO line while the 64 bit wide flash memory is controlled via the CS1 line of the MPC8270 The data lanes are swapped according to the necessary endian conversion The pins of the socket are controlled by the MPC8270 according to following table endian swapped data lanes Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 23 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 2 1 Type Selection for Boot ROM Socket by link 512Kbit 1Mbit 2Mbit
23. eiecti ame au 71 9 3 The Local Bus and PMC Connector Pin out sese 72 Od The PMC Module Slot sense 73 9 5 The PMC PCI Connector ccce Re est genas 74 10 The ispLSI Programming Port ei 75 11 Summa ob UIDES er 76 Lid JumpersComponent Sides uiii ete u de au 77 11 2 Jumpers solder cat alah anise tens Mee e unu aa 78 ApPpendices RES 79 Appendix VO Connector Overview 80 Appendix B Layout Component Side 81 Appendix C Layout Solder Side ee en su 83 Appendix D Schematics CPU87 request sse 84 Page 6 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 1 Introduction 1 1 Short Description The Double Euro sized board CPUS is based on the Motorola PowerPC MPC8270 It features a 64 bit wide data bus for the 32 64 128 Mbytes SDRAM area and the 8 Mbytes Flash memory bank Additionally it offers two 8 bit wide 32 pin JEDEC sockets for a boot ROM and a DiskOnChip device An additional 16 bit wide SRAM area with battery backup is shareable with any other VMEbus master The PC Interface of the MPC8270 controls a 2KBytes EEPROM a RTC with battery backup and a System Monitor for supply voltage supervision The Module of the MPC8270 handles two 10 100Mbit Ethernet ports three RS232 com munication ports and two special RS422 and
24. generates a low active interrupt to the MPC8270 on the IRQI line Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 69 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 9 The Mezzanine Slot The CPU87 supports an extension slot for mezzanine boards with PMC form factor The interface to this extension depends on the type of processor mounted on the CPU87 With the standard MPC8260 CPU only the Local Bus signals are available To use the PCI interface for PMC modules 8250 CPU type is necessary Page 70 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 9 1 The Local Bus Module Slot The Local Bus module slot uses the connectors ST9 and ST10 The bus signals and power pins are available on ST10 The mezzanine I O lines are connected via ST9 to the rows D amp E of VG160 connector ST2 9 2 The Local Bus Connector Pin out GND 12V 5V GND 3 3V GND PBXCLK LGPLO LGPL2 INTA LGPL3 REQ2 LGPL4 LA31 LGPLS5 GN IRDY AD STOP ADI DVSL AD 31 32 IDSL 33 34 PERR AD SERR AD REQO 39 40 cs m AD LSDQMO GND 43 44 LSDQMI ADS 45 46 LSDQM2 AD9 47 48 LSDQM3 ADIO 49 50 LWR AD11 CBE0 AD12 CBEI AD13 CBE2 CBE3 ADIS 59 60 GND GND 3 3V 5V 63 64 GND Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 71 of 84
25. location CS6 offset 03 allows for a complete protection against all write accesses to the flash devices The BCRG contains two protection bits one for the device write line WE and one for the write protect pin WP of the 64bit flash bank The BCRG can be read back for verification After a reset these bits are set to low and the write protect mode is activated Bit map of the B oard C ontrol R e g ister cadente ues ee reset Poo Po e oe II flash write disable x x x x x x 0 X In addition the flash area can be hardware protected against unintended write cycles by jumper FWRE If jumper FWRE is installed the flash devices are protected independent of the contents of the BCR For detailed chip information see Technical manual of Intel 28F160C3B Page 28 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 3 2 Flash Address Map for 64 Bit Boot Option 64 Bit Flash Jumper BTMD 1 3 and 2 4 Sector Comment 0 32 KBytes FF80 0000 FF80 7FFF Hard Reset Configuration Word address 0x0000 0000 0x00 address 0x0000 0008 0x00 address 0x0000 0010 0x00 address 0x0000 0018 0x40 32 KBytes 4 32 KBytes FF82 0000 FF82 7FFF FF82 8000 FF82 FFFF FF83 0000 FF83 7FFF FF83 8000 FF83 FF84 0000 FF87 FFFF FF88 0000 FF8B FFFF FF8C 0000 FF8F FFFF FF90 0000
26. upper byte from D15 to D8 does not contain valid data during the byte sized acknowledge read cycle on odd VMEbus addresses In order to meet the VMEbus specifications the necessary acknowledge cycles must be performed according to following table VMEbus Interrupt Acknowledge Access Address Overview IACK for level VA3 VA2 VAI 0 s wem 0 1 0 wem 0 1 end _ 1 1 _ 9 Byerei _ VERO Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 49 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 7 3 The Onboard Interrupt Handler There are seven low active interrupt sources onboard the CPU87 Each source can be enabled or disabled individually by software and its current status can be checked within a status register After a hardware reset all bits of the enable register are set to zero and all local interrupt sources are disabled To enable an interrupt source the according bit must be set to high The register contents can be read back for verification The sources are distributed to the seven interrupt input lines of the MPC8270 according to following table o IRQUNMLOUTAPE 0 4 monxes TMCIRQABCD Page 50 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC
27. 0 Tl WI 2 U3 Y4 U4 DI E2 V2 26 25 25 23 24 24 23 23 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 17 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals LDO31 ADOS LDO31 ____ local bus PMC PCI LDPO CO CBEO 128 jused bus PMC PCI LDP1 C1 CBE1 54 local bus PMC PCI LDPZ C2ICBE __ T28 Jused local bus PMC PCI LDP3 C3 CBE3 W28 Jused local bus PMC PCI PARILAI4 N27 54 local bus PMC PCI 15 31 LAQS31 usd local bus PMC PCI used functionality is shown in bold characters Page 18 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals PA0 input LAN Channel 1 input LAN Channel 2 PA3 output LAN Channel 1 output LAN Channel 2 5 output Channel 1 output output LAN Channel 1 output LAN Channel 1 output LAN Channel 2 output LAN Channel 2 input LAN Channel 1 input LAN Channel 1 input LAN Channel 1 input LAN Channel 1 output LAN Channel 1 output LAN Channel 1 output LAN Channel 1 output LAN Channel 1 output LAN Channel 1 PA23 output LAN Channel 1 output LAN Channel 2 output LAN Channel 2 input LAN Channel 1 input LAN Channel 1 output LAN Channel 1 output LAN Channel 1 input LAN Channel 1 inp
28. 00Mbps LAN Interface Connector ST3 A 43 6 5 2 2 10 100Mbps LAN Interface Connector 3 43 6 5 2 3 The Network Status Beds a edes t soe eret itte a iaia 44 6 6 The Floppy Disk Controller Option iii 45 6 6 1 1 The Floppy Interface Connector S ea es 46 6 7 EEEE eb 47 6 7 1 The Interr pt Handler Ecaca els 47 6 7 2 The VMEbus Interrupt Handler us s aan kan 47 6 7 2 1 VMEbus Interrupt Acknowledge sass 49 6 7 3 The Onboard Interrupt Handler sss 50 6 8 The VMEbus aues ei RI nu 53 6 8 1 Pin Assignment of the VMEbus Connector ST2 57 6 8 2 The VMEBUS Mailbox nn naar 58 6 8 3 The VYMEBUS Regwester a RR ari 60 6 8 4 The VMEbus Arbiter 60 6 8 5 The VMEbus Tine eat 61 6 8 6 Preparations for VMEbus Multiprocessing 61 Tes a dI si ah 62 8 Bront Panel Deschplion u en Rei use 68 8 1 Front Bed MH E ER 69 8 1 1 1 The User Programmable EGds an 69 8 1 1 2 gt The Network Status Weds 325 eco ope bh ton ea nie TG 69 8 1 2 Front Switches u en 69 9 TheMezzanine Sloane ie pita euere 70 9 1 The Local Bus Module Slot aerei 71 92 The Local Bus Connector Pin Qut
29. 19 Opvo DO 20 D2 Opo 21 D3 22 GD 23 OplO 24 DS Opo 25 D6 pt 226 cole Opt VO CIKHP Opt VO Page 46 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 7 Interrupt Structure 6 7 1 The Interrupt Handler The CPU87 offers a bit maskable 7 level VMEbus and a 7 level onboard interrupt handler The 7 VMEbus interrupt levels work in vector controlled mode only The interrupt priority structure of the VMEbus must be realized by software i e by the use of mask and status register bits for each VMEbus interrupt level The interrupt priorisation of all local interrupt sources can be freely han dled according to the users demands 6 7 2 The VMEbus Interrupt Handler Each VMEbus interrupt level can be enabled or disabled by software via the VMEbus interrupt mask register at location CS6 80 After a hardware reset all bits of this register are set to zero and all VMEbus interrupt levels are disabled To enable a VMEbus interrupt level the according bit must be set to high The register contents can be read back for verification All VMEbus inter rupt lines share the MPC8270 interrupt line IRQ3 Bit map of the V MEbus Dnterrupt M ask R egister
30. 39 40 GND CBEI 43 44 GND ADI4 4 46 ADIS GND 47 48 ADI0 ADS 9 50 VDD 51 5 53 54 55 56 GND pce eae uem T GND 5 60 62 wp GND 63 64 marked pins not connected Page 74 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 10 The ispLSI Programming Port The programmable logic onboard the CPU87 can be modified or updated via a PC controlled pro gramming interface The ISP programming port contains the necessary lines for serial a program ming of all ispLSI devices Besides the programming option also a JTAG mode is available for the ispLSI devices in hardware or emulation mode The pin assignment of the ISP port is shown in the following table Connector ISP Description DD Attention Please contact MicroSys before attaching this interface Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 75 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 11 Summary of Jumpers Described function is valid when jumper is set or link is intact System Controller Function Disable 15 BA 12 BootROMPinltoVec 23 BootROMPinitoA9_ suli 4 Boot ROM Pilo ATS BB 12 BootROMPin30toVec 1 23 BootROM Pin 30to
31. 4AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 6 The Floppy Disk Controller Option The CPU87 provides the FDC37C78 floppy disk controller interface from SMsC It uses the CSS select line of the MPC8270 as an 8 bit device The DMA function works in memory to memory mode with external request and no address increment on the FDC access address CS5 80 This feature allows the DMA read write timing parameters to be equivalent to the nor mal read write operation low active read line high active terminal count all signals fed through the ispLSI are changed if necessary to their respective logical active state Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 45 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 6 1 1 The Floppy Interface Connector ST2 The FDC interface signals are linked to the VMEbus connector ST2 on its row C as show in the following table 1 owo 2 GND 3 Opt I O Opt I O 4 Index 5 5 MotorOn2 6 A26 __ DriveSelecti 7 7 Drive Select2 8 MotorOni 9 9 DirectionIn 13 Opvo 5 Trako GND 16 DI8 SideSelet 18 Ovo D0
32. 4Mbit 8Mbit EEPROM 1Mbit Flash 1Mbit 4Mbit don t care Default soldering links setting for 4Mbit Flash types A BA BB BC Page 24 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH 6 2 2 2 Socket Pin out MicroSys Made for Professionals Please check for correct pin compatibility before mounting any device 28 pin and 32 pin pack ages must be inserted into socket as shown below only during power down Any insertion of other types or not as directed may cause permanent damage to the device and or the board VPP A18 A19 16 15 12 AT A6 AS A4 A3 A2 Al AO DO DI D2 O O O O O O O O O GND O 0 O oO Vec Vcc A18 WR Vcc A17 14 A13 9 11 10 D7 D6 D5 D4 D3 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 25 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 2 3 Boot Options The CPU87 can be configured to boot either from the 8 bit ROM socket or from the 64 bit Flash Rom bank after Reset The selection is done by jumper BTMD When set to 1 2 and 3 4 the fac tory default setting the MPC8270 boots from the 8 bit device when BTMD is set to 1 3 and 2 4 the MPC8270 boots from 64 bit Flash The jumper RCFG defines if the MPC8270 Hard Reset Configuration Word is read external
33. 5485 interfaces The local bus of the MPC8270 is accessible via 64 pin extension connector A PMC slot is con nected to the PCI interface replacing the local bus lines The VMEbus interface contains a single level arbiter a requester with a four level ROR option and a 7 level interrupt handler The short I O decoded mailbox with interrupt capability allow for process synchronization For background debug purposes the JTAG COP interface of the MPC8270 is accessible via a 16 pin standard wrap connector The complete board is implemented in CMOS technology which allows for a power consump tion as low as 5V 9W 450 MHz CPU speed The 5 volt board supply voltage is protected by a transient suppresser diode against over voltage or wrong polarity The CPU87 conforms to the VMEbus specification ANSVIEEE STD1014 1987 IEC 821 amp 297 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 7 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 1 2 Specifications The power requirements for the CPU87 board are shown in the following table Power Requirements SV 5 2 5 t b d typ 450 MHz 12V 5 2 5 for PMC slot only 12V 5 2 5 for PMC slot only Environmental Requirements Operating Temperature 0 Cto 70 C 40 C to 85 C optional Relative Humidity 0 to 95 non condensing Storage Temperature 40 C to 859 1 3 Related Documentation The fo
34. A 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of the L ocal Dnterrupt M ask R egister gt a LISR CS6 83 we E oc box Oma x x a Bit map of the C lear M ailbox Dnterrupt P ort Do bi D2 ps os 1 write clear mailbox IRQ Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 59 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 8 3 The VMEbus Requester The CPUS7 contains a single level 2 1 pass requester with R elease W hen D one or a four level R elease O n R equest mode The RWD requester releases the VMEbus mastership after the completion of each bus cycle and it has to request for it for every following VMEbus cycle The ROR method releases the VMEbus only if the current VMEbus cycles have been completed and any other device in the VMEbus system requests for the bus mastership If there are no other requests the ROR requester remains being bus master even if it does not access the VMEbus The RWDN method is enabled within the VME standard access compare at location CS6 01 If this bit is set to low the release when done mode is active otherwise the requester work
35. AIZ 2 3 4 5 12 Lithium battery connected tum banery discomeeed HERES 56 wmmmMobciskw internal default configuration MPC8270 gt N usable only when booting from 64Bit Flash 10 100BaseT Channel A TX CT voltage set 10 100BaseT Channel B TX CT voltage set 1x2 Factory setting dependent on Flash types mounted Must not be changed Page 76 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH 11 1 Jumpers Component Side 918 e e e e e e e e e 1 e e e e e e ee e ee e ee e e e n n 994 2 go ARBE STI Bee Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH Archivierung 5 5 omw 15 3 e o N EW285MA 04AA MicroSys Made for Professionals Page 77 of 84 MicroSys Made for P
36. DV RXDV T T T T 8 RX E RX RXDI P 16 P B20 RX 3 RX RX RX RX 4 ile amp ASIE N Page 42 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 5 2 1 The 10 100Mbps LAN Interface Connector ST3 A af 10 100Mbps TP transmit line 2 TxD 10 100Mbps TP transmit line 3 RxD 10 100Mbps TP receive line 4 center 75R terminated center 75R terminated 8 center 75R terminated 6 5 2 2 The 10 100Mbps LAN Interface Connector ST3 B ue emm i mee 1 ne OMT aniline mb 6 s em e RD Dr Tem seme Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 43 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 5 2 3 The Network Status Leds There are two network front panel status LEDs for each channel which can be programmed via the management data port within the LED configuration register of each LXT971 according to following table link status duplex status i festmodeted si TI festmode ed fash on i fink and receive sans 1 link and activity status 1 duplex and collision status Default setting in VxWorks BSP for LED 2 Y Default setting in VxWorks BSP for LED Page 44 of 84 EW285MA 04AB Archivierung 5 Datei CPU87
37. Data 09 L logical low H logical high E Page 54 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals The CPU87 generates the following VMEbus cycles within the standard extended and interrupt acknowledge address ranges cycle read byte read word read lword write byte write byte write word write lword read byte read byte read word read word read lword read lword The BYMD function is contained within the VMEbus interrupt mask register It is used to gener ate byte sized read cycles on the VMEbus because all normal read cycles from the VMEbus are by default word or longword sized The shadowed area can be used but care must be taken be cause of invalid data paths or unallowed VMEbus cycle combinations Any write cycle to the VMEbus is always performed with the CPU requested size Bit map of the V MEbus Dnterrupt M ask R egister Im res ____ fe Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 55 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Pin Assignment of the VMEbus Connector STI BBSY BCLR ACFAIL BGOIN Hu BGOOUT ie BGIIN BGIOUT BG2IN E x GND BERR SYSRESET LWORD AMS Ace Tee Inm signals enclosed in brackets are not use
38. Type Selection for Boot ROM purea 24 lt Sanieren 25 9223 26 6 2 3 The Flashi Memory grace em een 27 6 2 3 1 The FLASH Memory Write Protection ahnen 28 6 2 3 2 Flash Address for 64 Bit Boot Option nennen 29 6 2 4 The DiskOnChip 30 92 4 1 2 Socket eco on a 31 6 2 5 The Static RAM Area na 32 6 2 5 1 Low Battery 32 6 2 5 2 DPRAM Shared Address Decoding essere 33 TRG TG BUS et noL EE Ie E 34 6 3 1 The EEPROM eek 34 6 3 2 TheReal Time Clock Bee step user 34 6 3 2 1 The PCE8563T Address Maps ann 35 6 3 3 The System Hardware Monitor east 36 od Miscellanous saa nn tata ideali 37 6 4 1 Th Backup Beati eru ede ie rive a 37 6 4 2 The Board Reset Function uses i erento etre nase 37 6 4 3 Hardware Watchdog e DO e 38 6 4 4 Board Control Register 39 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 5 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 4 5 Board Revision Re sister Ei 40 6 5 The C PST Inte Eae e reelle 41 6 5 1 The Serial VOS arri ee ua eu 41 6 5 2 Pott ar 42 6 5 2 1 10 1
39. access cycles on the VMEbus The according address modifier combination is handled by different address ranges and the board control register Bit map of the B oard C ontrol R e g ister acc css To To To To Pos To p Esra Basar ee Ns Ci Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 53 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals The address modifier lines AM5 and are address decoded according to the following table The data size represents the maximum allowed data width i e the longword signal is only driven active within the A32 D32 address range never within the other address ranges Any longword access within the non D32 ranges is automatically split into several byte or word sized cycles VMEbus Extended Access Range 8000 0000 80FF FFFF A32 D32 VMEbus Standard Access Range H H FE00 0000 FEFF FFFF A24 D16 VMEbus Short I O Access Range FDOO 0000 FD07 FFFF A24 D16 VMEbus Int Ackn Access Range X 008 0000 SFDOFFFFF A24 D16 L logical low H logical high X don t care The following AM Codes are generated by the CPU87 ama awa AMI AMO Standard Supervisory Data 3D Standard User Prog 3A Standard User Data 39 Short I O Supervisory Data 2D Short I O User Data 29 Extended Supervisory Prog OE Extended Supervisory Data OD Extended User Prog OA Extended User
40. ch Germany ISDN Hotline 08104 801 130 Phone 08104 801 0 Fax 08104 801 110 Internet http www MicroSys de MicroSys Electronics GmbH December 2007 Page 4 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Table of Contents s aee tef es gen d 1 1 Short Descriptions esce oio eau 7 1 2 Specifications eucarioti aa 8 1 3 Related Docimentatnori ansie ale 8 2a 5 1 CIA IRA AIR Seat 9 2 1 Items shipped with this ieri eee e eo Edo reto tope qu doe de 9 2 2 Hints for unpacking handling and storing ui o een dee ee eet eder aeta 9 3 an see ali aaa 10 3 1 Items required tor CPU87 installation ann ana 10 3 2 Bots io Be ODSeLVe eine 10 4 Board OVERVIEW aD ler 11 4 1 Features CPUS Aa i 11 Se Address Map Cice pote idee deve cea hie 13 5 1 The 6036 Bus Address Map au ae 13 52 The PC Bus Address 14 6 F nctional Description o ose ilaele pm qu 15 6 1 The PowerQ UICC II Processor s scies veo ee Sese vete m Ee tero is 15 6 1 1 The Debug POE 16 6 1 2 The Processor Pin Configuration sa 17 6 2 Memory seien ieh 22 6 2 1 The SER NEA TO ce e an ta dass aui S tes ees 22 6 2 2 The Boot Socket meti ee les 23 6 2 2 1
41. croSys Made for Professionals two IEEE compliant Fast Ethernet PHY Transceivers full duplex operation for 100BASE TX and 10BASE T four network status LEDs four user programmable LEDs ABORT key with level 1 interrupt capability RESET key for complete hardware reset hardware watchdog timer with system reset programmable time out rate via external parts 16 pin JTAG COP Interface 7 level onboard interrupt handler 7 level VMEbus interrupt handler software programmable interrupt mask full VMEbus slot 1 functions single level arbiter single jumper function enable according to ANSVIEEE STD1014 1987 DTB A16 A24 A32 D8 D16 D32 VMEbus address modifier support standard extended and short I O addressing dynamic bus sizing feature DTB A24 A32 D8 D16 programmable VMEbus access base address programmable VMEbus access window size DTB A16 D8 D16 programmable VMEbus access base address short decoded with interrupt capability single level arbiter on level 3 single level 2 1 pass requester release when done or 4 level release on request modes PMC form factor Local Bus Interface for MPC8260 Processor type 3 3V PCI Interface for MPC8250 and MPC8270 Processor type Page 12 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 5 Address Map CPU87 5 1 The 603e Bus Address Map faa Sana se pes pei VMEbus Int Ackn Access Range FDOF
42. d and left open 5 a ow EC HN 10 Ou Ep hee 14 5 5 ii Bm CANI 20 2 23 24 25 261 27 2 ED ud 30 Page 56 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 8 1 Pin Assignment of the VMEbus Connector ST2 GD Opt pt VO pt VO Drive Select 1 pt VO pt VO Opt YO ND ND pt VO GND pt VO pt VO GND pt VO GND iD D2 pa pt D2 pt D3 E 5 5 Q 4 pt JO Q Z pt VO N N Din gt EE Rc p NEWER SM Din SM Clk SM4 pt I Ld SM pt VO DataHP Opt JO CIKHP N pt I RR 2 2 2 12 2 2 Ix SIS i218 8181 5 IEEE Ix O O O O O O Be NI DN E NA 10 Ln y ESSET Be 18 E We Eo 22225 4 HE CA 2 26 27 28 1 2307 ME EE Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 57 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 8 2 The VMEbus Mailbox The mailbox feature of the CPU87 is realized by a programmable location monitor funct
43. ines and can be disconnected by removing the OR links R101 and R102 Frontpanel Connector ST4 RJ45 RS232 1 m Frontpanel Connector ST3 D RJ45 RS232 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 41 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 5 2 The Fast Ethernet Ports The CPU87 offers two 100 10Mbit Ethernet channels with twisted pair interface Both ports are accessible via two 8 pin RJ45 connectors on the front panel Each channel is handled by an LXT971 controller with MII Interface connected to the and FCC2 ports of the MPC8270 The device address for the channel A controller is set by hardware to 1 The controller for chan nel B uses the device address 2 Channel A FCC1 Channel B FCC2 LXT971 8270 8270 MDINT A MDINT P 0 P AI B MDINT MDINT P A24 MDIO P A23 P A25 PWRDN P P 4 PAUSE P 5 P A6 TXSLEWO TXSLO P AIO P 12 MID TXSLO TXSLEWO TXSLEWI P_AII P_A13 TXD3 P A21 P B25 TXD2 P A20 P B24 MID TXD2 TXD2 TXDI P A19 P B23 TXDO P_A18 P_B22 N P_A28 P B29 MID TXEN TXEN R P_A29 P_B31 MID TXER K P C20 P CI8 RXD3 14 P BI8 RXD XD2 XEN XER K 3 D3 RX 15 P 19 D2 DI 0 DO V DV ER OL CRS RXDV P A27 P B30 RXER P A26 P B28 RXCLK P C21 P CI9 CLK COL P A3I P B27 MIDCOL COL CRS P A30 P B26 MID CRS CRS DO RXDO 17 21 MID RXDO RX
44. ion within the VMEbus short I O range The programmable base address decodes the VMEbus address lines from A15 down to A8 and all VMEbus address modifier lines The mailbox issues an interrupt on level 7 if a byte or word sized write cycle is performed within the programmed address range The mailbox decoding function must be enabled within the VSAC at location CS6 01 If the VSHTE bit is set to high the mailbox decoding is enabled and in case the according interrupt mask bit within LIMR is set a mailbox interrupt can be generated The interrupt will be held active until a mailbox clear command by a single write access to location CS6 06 is performed The actual state of the mailbox interrupt can be detected within the local IRQ status register at location CS6 83 After a reset the according mask and enable bits are set to zero and the mailbox decod ing and interrupt are disabled Bit map of the V ME M ailbox A ddress C ompare Register __ bo m 0 e fo Bit map of the V ME S tandard A ddress C ompare Register bo ma o sf O ces ibi 5 The following AM Codes are necessary for the mailbox access AMS ANG AWE AMT L logical low H logical high Page 58 of 84 EW285M
45. ivierung 5 EW285MA 04AA Page 67 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 8 Front Panel Description e 2 1 NV 1 Pd Page 68 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 8 1 Front Leds There are three user programmable leds processor RUN indicating led and four LAN status leds located on the front panel of the CPU87 8 1 1 1 The User Programmable Leds These leds can be controlled via the B oard C ontrol R e g ister at location CS6 offset 03 The BCR contains three high active bits for the led control two VME address modifier control bits and two protection bits used for the 64bit flash bank The BCRG can be read back for verifica tion After a reset all bits are set to low and all leds are deactivated Bit map of the B oard C ontrol R e g ister Junens ouem user led 1 switch off user led 1 switch on user led 2 switch on user led 4 switch off user led 2 switch off user led 4 switch on 8 1 1 2 The Network Status Leds There are two network front panel status LEDs for each channel which can be programmed via the management data port within the LED configuration register of each LXT971 8 1 2 Front Switches The RESET switch performs a hardware reset to the CPU87 The ABORT switch
46. line will be continu ously low Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 37 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 4 3 Hardware Watchdog Timer The CPUS7 features a fixed rate hardware timer for watchdog purposes which can be enabled by software The time out rate is set to 1 6 seconds by default Within that time at least one write ac cess must be performed to the W atchdog R etrigger P ort located at CS6 05 to retrigger the timer Once retriggered i e enabled it only can be disabled by a hardware reset The time out se quence can be modified by an additional hardware component on the SMD 1206 location C35 according to following equation Watchdog Time out Period in ms 2 1 x capacitor C35 value in nF allowed values are 4 7nF to 100nF The modified time out sequence will only be activated if the 0 R SMD Resistor R42 is removed If R42 15 installed the time out rate 15 set to 1 6 seconds independent of the value of C35 The watchdog timer must be reset within the given time out period by a write access to the W atch D og R etrigger P ort located at CS6 05 WDRP CS6 05 write Page 38 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 4 4 Board Control Register The board control register located at CS6 03 handles the user programmable leds the VMEbus address
47. llowing manuals are applicable to the CPU87 MPC8270 Power QUICC II Microprocessor User s Manual HY57V651620B TC7 4x1Mx16 SDRAM Data Sheet Note DRAM may actually vary depending on the specific version and availability 28F160C3B Intel Boot Block Flash Memory Data Sheet Note Flash may actually vary depending on the specific version and availability LM8I System Hardware Monitor Data Sheet PCF8563 Real Time Clock User s Manual X24C164 EEPROM Data Sheet DiskOnChip 2000 User s Manual VMEbus Specification Manual ANSI IEEE STD1014 1987 Page 8 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys 2 Delivery 2 1 Items shipped with this unit User s Manual CPU87 Hardware MicroSys shipping carton ATTENTION STATIC DISCHARGE CAN DESTROY UNIT 2 2 Hints for unpacking handling and storing Avoid touching areas of integrated circuitry Unit should only be placed on a static free conductive surface Unit must only be transported using anti static bags or MicroSys shipping carton Packing should be saved if unit needs to be reshipped or returned When the unit needs to be stored it should be placed in a moist free dust free environment The storage temperatures and humidity specifications are shown in chapter 1 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 9 of 84 2000 2007 MicroSys Electronics GmbH
48. modifier lines and the Flash write protect switches A logical high enables the according function After reset the register is cleared all leds are switched off and the 64 bit Flash memory area is write protected Bit map of the B oard C ontrol R e g ister Di rena amon FWRE wed a RECEN RC Pei et a Fo AME X X X X X X X X X X X X X X X X X X x Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 39 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 4 5 Board Revision Register For identification purposes and user defined demands the CPU87 features an 8 bit read only regis ter at location CS6 07 Bit map of the B oard R evision R e g ister Revsison 4 BRRG CS6 07 Page 40 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 5 The CPUS7 Interfaces 6 5 1 The Serial 1 5 Four RS232 serial interfaces are accessible via three RJ45 connectors on the front panel of the CPU87 The SCCI and SCC2 ports use a standard pin out with two handshake lines on their con nectors while both SMC ports share a single RJ45 connector according to the following table The SMC2 port uses the standard RTS CTS l
49. ofessionals 6 4 Miscellaneous 6 4 1 The Backup Feature The backup feature of the CPU87 is used to protect the RTC as well as the SRAM area Both de vices are connected to the MAX 791A which controls the backup supply and the power up and down sequences to avoid unintended write pulses The backup power is supplied by a service free gold capacitor as well as by a 260mAh lithium cell CR2430 In case the cell must be replaced the goldcap will avoid data loss of the connected devices The RTC as well as the SRAM area cannot be disconnected from the backup power The gold capacitor allows for a service free short time backup without any battery or other time or temperature degrading parts If the backup time should be extended the backup power can be sup plied via the onboard lithium cell or via the VMEbus standby line on connector ST1A pin 31 The external supply voltage should not exceed 5 25 volts and not fall below 2 5 volts to ensure correct data retention The power consumption table of all backup connected devices device max current total MAX791A 5uA 5uA PCF8563 0 5uA Svolts 0 5 KM684000ALG 5L 50 3volts 100pA 6 4 2 The Board Reset Function During power up or power down sequences the board supervisory circuit MAX 791A activates the board reset line and holds the CPU87 in a defined state The reset line will be low for at least 200ms if the supply voltage reaches 4 65 volts Below that voltage the reset
50. pacity optional 64MB or 128MB 64 bit data bus width 8 Mbytes capacity 64 bit data bus width single 3 3 volt programmable devices one 32 pin socket according to JEDEC standard max Mbytes capacity 512Kbytes for FLASH types device type selection by soldering links 8 bit data bus width 5 volt supply ROM PROM EPROM EEPROM FLASH support 64 Kbytes max 1 Mbytes SRAM capacity 16 bit data bus width data backup with onboard supply accessible by other VMEbus masters serial access device 2KBytes capacity MD 2800 D08 5V device optional 32 pin socket with standard JEDEC pin out FDC37C78 Floppy Disk Controller optional serial access device PCF8563 with time amp date function backup function with onboard supply 2 SMCs with RS232 interface 2 SCCs with configurable buffers via I O modules serial access device LM81 hardware monitor for temperature and voltage control short time backup via service free gold cap extended backup via 260mAh lithium cell CR2430 external backup via VMEbus standby line Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 11 of 84 2000 2007 MicroSys Electronics GmbH features CPU87 continued Network Capabilities Front Panel LEDs Front Panel Keys Watchdog Debug Features Interrupt Handler System Controller VMEbus Interface VMEbus Master VMEbus Slave VMEbus Mailbox VMEbus Arbiter VMEbus Requester Mezzanine Slot Mi
51. rofessionals 11 2 Jumpers Solder Side e e 1 Bra 4 3 a e 1 1 e Ala a a eo p Bj ale e on e e e e e e 1 e e e e B e e e e e Page 78 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Appendices Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 79 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Appendix A I O Connector Overview Uo Connector Local Bus Connector PCI Connectors DiskOnChip Socket Boot ROM Socket lo OT 79999 55 1 T m 00 Do E LAN 1 E 8 2 2
52. roprocessor sys tem hardware monitor LM81 It offers the monitoring of the board ambient temperature all board supply voltages and the voltage range of an external battery The VIDO 4 inputs can be used for a user configurable 5 bit identification A maskable interrupt can be generated on the MPC8270 IRQ level 2 if the according enable bit within the L ocal Dnterrupt M ask R egister at location CS6 82 is set to high The LIMR contents is cleared after reset and can be read back for verifica tion The current status of the LM81 interrupt line can be detected within the LISR register at loca tion CS6 83 The LM81 device responds on bus at address 59 for read and 58 for write accesses The pins of the LM81 are connected according to following table CI CPU IRQ 12V VMEbus supply VMEbus 5V standby line not used and left open FANI via R63 to GND or pulled up The voltage detection of the 12V VMEbus supply is handled by a resistor divider against the 5V VMEbus supply The used division factor formats the 12V to 1 25V according to the formula 141 R2 40K 5V 12V R2 R2 Vcc x 1 y x EIE 3 895V 12V x 0 221 E For detailed programming information and chip description please refer to National LM81 Data Sheet Page 36 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Pr
53. s The SRAM is accessed on the 603 bus side of the MPC8270 by the CS3 select line and no parity check is performed The SRAM bank can be shared with other VMEbus masters but any access from an alternate VMEbus master to this area cannot be snooped because no CPU bus arbitration is performed i e this area must not be configured as cacheable The contents of the SRAM area is protected against data loss by a backup circuitry The backup power is supplied by a service free gold capacitor or a lithium cell An extended backup time can be reached if the VMEbus standby line on ST1B pin 31 is used to supply the necessary backup power In any case the backup time mainly depends on the used SRAM devices and their standby power consumption The backup feature of the CPU87 cannot be disabled The backup power is supplied to the SRAM area as well as to the onboard real time clock 6 2 5 1 Low Battery Monitor The MAX791 backup battery controller features a monitor function to detect a low battery volt age The low backup supply GoldCap and Lithium cell is monitored only during the reset period If the voltage is below 2 0V 0 15V the second chip select pulse to the SRAM devices is inhib ited If the voltage is above 2 0V all CS pulses are allowed To use this feature you may write 0x00 to a SRAM location and OxFF to the same location directly after Reset The contents of the SRAM then indicates a good battery if OxFF can be read If you read 0x00 the ba
54. s in re lease on request mode Bit map of the V ME S tandard A ddress C ompare Register m pr os Ion est o lo su BN 2117 0 x Requester ROR mode Requester ROR mode 6 8 4 The VMEbus Arbiter The CPUS7 is equipped with a single level VMEbus arbiter on request level 3 This allows the board to work as VMEbus controller as well as a bus slave in any combination The VMEbus arbiter function can be enabled if jumper ARBE is installed This link enables also all other system controller functions according to following table VMEbus Signal Slot 1 Function Driver Type not Slot 1 Function Bus Error Input Output Input Bus Grant In 3 Input Output Input Please make sure that only one system controller is enabled within a VMEbus system at a time usually located in the leftmost slot The use of more than one system controller will lead to im proper operation and may cause permanent damage Page 60 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 8 5 The VMEbus Timer The CPU87 offers a bus monitor to supervise all VMEbus accesses This time out counter termi nates any cycle with the bus error signal if the access exceeds a certain time because non exist ing device has been addressed or a defect device does not respond The
55. supply the necessary backup power The low active RTC interrupt signal is connected on the MPC8270 IRQ line 5 The RTC device responds on the bus at address A3 for read and A2 for write accesses E For detailed programming information and chip description please refer to Philips PCF8563 Data Sheet Page 34 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 3 2 1 The PCF8563T Address Map us seme wr os s DA DI LL rn o femsas pepe TE ae ne CLKOUT frequency 0E Timer control fran DI TT IE EI mw or rime com e ume me D7 s amare ile CB oat nisi lt hours 00 to 23 coded in BCD gt s sw wma ES E TOT sone 508 lt years 00 to 99 coded in BCD gt lt minute alarm 00 to 59 coded in BCD gt sos tian pwa Ce Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 35 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 3 3 The System Hardware Monitor The board ambient and supply conditions of the CPU87 can be sensed by the mic
56. the L ocal Dnterrupt M ask R egister LIMR CS6 82 read write reset ABORT key IRQ disable ABORT key IRQ enable Mailbox IRQ disable Mailbox IRQ enable FDC IRQ disable FDC IRQ enable RTC IRQ disable RTC IRQ enable LM81 IRQ disable LM81 IRQ enable VME SYS Fail disable VME SYS Fail enable PMC IRQ disable PMC IRQ enable VME AC Fail disable VME AC Fail enable Z gt IS Io Io Po ISCM IRTC IFDC IMBX VSYF REC x ERE x x x x x x x x X X Page 66 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of the L ocal Dnterrupt S tatus R egister Abort Key inactive x x x x Abort Key active Mailbox IRQ inactive Mailbox IRQ active FDC IRQ inactive FDC IRQ active RTC IRQ inactive RTC IRQ active LM81 IRQ inactive LM81 IRQ active VME Sys Fail inactive VME Sys Fail active VME AC Fail inactive VME AC Fail active Bit map of the P MC Dnterrupt S tatus R egister INTD INTC INTB INTA PMC IRQ A inactive x PISR CS6 84 read only MC IRQ A active x MC IRQ B inactive x MC IRQ B active x PMC IRQ C active x PMC IRQ D inactive X X X X X X X X EE e PMC IRQ C inactive x x PMC IRQ D active 1 Datei CPU874AB DOC Arch
57. ttery is below 2 0V Note This feature cannot be disabled With a low battery voltage and no check routine implemented the second access to the SRAM fails after Reset Page 32 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 5 2 The DPRAM Shared Address Decoding The 16bit SRAM area onboard the CPU87 can be accessed by other VMEbus masters The neces sary access address from the VMEbus side is decoded and enabled by two internal registers of the VME ispLSI Any shared ram access from the VMEbus side must be performed with the proper address modifier combination for a standard or extended access and the state of the according compare bit must match with the state of the desired VMEbus address line The address decoding for the extended or standard access range is automatically activated by the according address modifier combination The enable bits for standard and extended access allow the SRAM area to be shareable or not within one or both address ranges After reset both registers are cleared and the shared access is disabled at all Bit map of the V ME E xtended A ddress C ompare Register wacacws bo pi pz OT ew fo Bit map of the V ME S tandard A ddress C ompare Register wecacws DO ps o7 rest
58. upt P ort races Im Bit map of the B oard R evision R e g ister moon i a lele Bit map of the V MEbus Dnterrupt M ask R egister Tm To Io To Im ssa a fe fo 0 x x x x a ver se x x e o x a so x x e o x a fa x fo a x fo e a a VME IRQ6 disable ES ERE fa fa fa ao arme 1 x 5 x a aa VME IRQ7 disable Page 64 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of the V MEbus Dnterrupt S tatus R egister Ts Ts VIRGI vios veer vas menan a x x i pL meno x 0 x x x 9 a x x 23 o x pL KE 1 x a x 2 menu x menan a x x x pL 1 x x x pL menan 1 x x Lo do Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 65 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals Bit map of
59. ut LAN Channel 1 Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 19 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals input LAN Channel 2 input LAN Channel 2 input LAN Channel 2 input LAN Channel 2 output Channel 2 output Channel 2 output Channel 2 output Channel 2 input LAN Channel 2 input LAN Channel 2 input LAN Channel 2 output Channel 2 input output LAN Channel 2 used functionality is shown in bold characters FDC37C78 5 5 ext baud rate H14 LAN Channel 2 LAN Channel 2 HI2 LAN Channel 1 LAN Channel 1 AGIO FDC37C78 FDC37C78 AF9 SCC3 SCC3 SCC4 SCC4 RS232 on 513 RS232 on ST3 D used functionality is shown in bold characters Page 20 of 84 EW285MA 04AB Archivierung 5 Datei CPU874AB DOC 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals used functionality is shown in bold characters Datei CPU874AB DOC Archivierung 5 EW285MA 04AA Page 21 of 84 2000 2007 MicroSys Electronics GmbH MicroSys Made for Professionals 6 2 Memory 6 2 1 The SDRAM Area The CPUS7 is fitted out with four synchronous dynamic ram devices which allows for total ca pacity of 32 MBytes 64 MBytes or 128 MBytes depending on the used chip sizes The RAM bank is directly controlled by the CS2 select line of the MPC8270 The DRAM data port is 64

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