SH69P23 - SinoWealth！
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1. PF1OUT PFOOUT TOS TOE Legend x unknown u unchanged unimplemented read as O Others After any Reset Program Counter PC 000 Undefined Undefined Undefined Accumulator AC Data Memory 5 69 23 4 Low Power Detection LPD The LPD function is used to monitor the supply voltage and applies an internal reset in the micro controller at the time of battery replacement If the applied circuit satisfies the following conditions the LPD can be incorporated using software control Power supply voltage Vpp 2 4 to 6 0 V 4 1 Functions of the LPD Circuit The LPD function is selected by OTP option The LPD circuit has the following functions It generates an internal reset signal when x VLPD and t 2 tLPD It cancels the internal reset signal when gt VLPD or x VLPD and t lt tLPD Here VDD power supply voltage LPD detect voltage There are two level selected by OTP option Low level 2 3 2 7V typical 2 5V High level 3 8 4 2V typical 4 0V tLPD 100us 500us typical 300us LPD can be enabled or disabled permanently by OTP option SH69P23 5 O Ports The SH69P23 provides 14 I O pins When every I O is used as an input port the port control register controls ON OFF of the output buffer Sections below show the circuit configuration of I O ports Every I O pin has a internal pull up2. 0 175 4 45 0 010 Min 0 25 Min Symbol Dimensions in inches Dimensions in mm A in A2 1 026 Typ 1 046 Max 26 06 Typ 26 57 Max 1 0 130 0 010 3 30 0 25 B 0 018 0 004 0 46 0 10 0 002 0 05 1 0 060 0 004 1 52 0 10 0 002 0 05 0 010 0 004 0 25 0 10 0 002 0 05 1 1046 26 57 00 000 2545025 3 30 025 _ 48 0345 0055 8765090 1 98 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E1 does not include resin fins 3 Dimension S includes end flash 27 5 69 23 SOP 20L W B Outline Dimensions unit inches mm Symbol Dimensions in inches Dimensions in mm 0 106 Max 2 69 Max 0 004 Min 0 10 Min A2 0 092 0 005 2 33 0 13 b 0 016 0 004 0 41 40 10 0 002 0 05 0 010 0 004 0 25 0 10 0 002 0 05 0 500 0 02 12 80 0 51 0 295 0 010 7 49 0 25 1 27 0 050 0 006 7 0 15 0 376 NOM 9 50 NOM 0 406 0 012 10 31 0 31 L 0 032 0 008 0 81 0 20 L 0 055 0 008 1 40 0 20 S 0 042 Max 1 07 Max y 0 004 0 10 0 10 09 10 Notes 1 The maximum value of dim
3. Programming Clock input pin When the chip is being programmed the SCK SDA should be separated from other appliction circuits Function Description 1 CPU The CPU contains the following function blocks Program Counter Arithmetic Logic Unit ALU Flag Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and the Stack 1 1 PC Program Counter The Program Counter is used to address the 4K program ROM It consists of 12 bits the Page Register PC11 and the Ripple Carry Counter PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO The program counter normally increases by one 1 with every execution of an instruction except in the following cases 1 When executing a jump instruction such as JMP BAO BAC 2 When executing a subroutine call instruction CALL 3 When an interrupt occurs 4 When the chip is in the INITIAL RESET mode The program counter is loaded with data corresponding to each instruction The unconditional jump instruction JMP can be set at 1 bit page register for higher than 2K 1 2 ALU and CY ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI Decimal adjustment for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM 2 OTPROM SH69P23 Decision BAO BA1 BA2 BA3 BAZ BAC Logic Shift
4. PRELIMINARY Features SH6610C based single chip 4 bit micro controller OTPROM 4K X 16 bits RAM 160 X 4 bits data memory Operation voltage 2 4V 6 0V typical 3 0V or 5 0V 14 CMOS bi directional I O pins Built in pull up and pull low resistor for PortA PortF 4 level subroutine nesting including interrupts One 8 bit auto re load timer counter Warm up timer for power on reset Powerful interrupt sources Internal interrupt TimerO External interrupts PortB amp PortC rising falling edge General Description SINO WEALTH SH69P23 OTP 4 bit Microcontroller Oscillator OTP option Xtal oscillator 32 768KHz 2 Ceramic resonator 400K 4MHz RC oscillator 400K 4MHz External clock 30K 4MHz Instruction cycle time 4 32 768KHz 122us for 32 768KHz OSC clock 4 4MHz 1us for 4MHz OSC clock Two low power operation modes HALT and STOP Built in watch dog timer OTP option Built in power on reset Two LPD level OTP option High level 4 0 Lowlevel 2 5 OTP type amp Code protection SH69P23 is a 4 bit micro controller This chip integrates the SH6610C 4 bit CPU core with SRAM 4K OTPROM Timer and I O Ports Pin Configuration PF1 1 e 20 1 PFO PA2 2 19 11 PA1 3 18 1 nw SDA TO 4 17 OSCI SCK RESET VPP 5 2 16 osco GND 6 U 15 Voo PBO 7 N
5. 0 00 50 00 100 00 150 00 200 00 250 00 300 00 350 00 400 00 R k om Typical RC Oscillator Resistor vs Frequency Voo for reference only 3V RC Frequency 10000 00 N I 8 100000 LL 100 00 T T T T 1 000 50 00 100 00 150 00 200 00 250 00 300 00 350 00 400 00 R k am Application Circuit for reference only AP1 1 Operating voltage 5 0V 2 Oscillator Ceramic resonator 455KHz 3 TO input timer clock counter 4 PORTA F I O SH69P23 RESET AP2 1 Operating voltage 5 0V 2 Oscillator RC 420KHz 3 PORTA C F I O 69 25 OSCO RESET GND PORTF 24 OSCI P TOME 1000PF 4 PORTA SH69P23 1 PORTA as scan KEY BOARD 32 keys 2 PORTF I O 3 All input pin internal Pull up On gt SH69P23 PC1 PC2 PC3 PBO PB1 PB2 PB3 PAO PA1 PA2 PA3 P P P P P 4 AP4 a Operating voltage 3 0V b Oscillator Crystal 32 768KHz c PORTA C I O PULL UP 469 5 25 5 69 23 Ordering Information Part No Packages SH69P23 20L DIP SH69P23M 20L SOP 26 SH69P23 5 69 23 Package Information P DIP 20L Outline Dimensions unit inches mm Seating Plane d
6. OV Ta 25 C Fosc 4MHz unless otherwise specified Parameter in 2 Condition Operating Voltage All output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded All output pins unloaded Stand by Current STOP LPD off If LPD on IsB2x IsB2 2uA WDT off If WDT on IsB2x IsB2 15uA Input Low Voltage GND 0 2 X ports pins tri state Input Low Voltage GND 0 15 RESET TO Input Low Voltage GND 0 15 X OSCI Driven by external clock Input High Voltage 0 8 X VDD ports pins tri state Input High Voltage 0 85 X VDD RESET TO Input High Voltage 0 85 X OSCI Driven by external Clock Leakage Current 4 Pan 10 ors vie veo FinputLeakage Current ma amp wA Vmsr GNDsOzV us frf Was Yoo Input Leakage Current GND lt lt VDD meea a 177777 NN I O ports 10mA Output High Voltage 0 7mA ports loL 20mA OSCOrc lor 1 6mA Operating Current Output Low Voltage AC Electrical Characteristics 5 0V GND OV TA 25 unless otherwise specified Parameter Symbol in Condition Oscillator Start Time Tosci X tal osc 32 768KHz RESET pulse width low TRESET Vpb 5 0V WDT Peri
7. TIMERO service routine 003H NOP Reserved 004H JMP Instruction Jump to PBC service routine 3 RAM SH69P23 The built in RAM consists of general purpose data memory and the system register Direct addressing in one instruction can access both data memory and the system register The following is the memory allocation map 000 01F System register and I O 020 0BF Data memory 160 X 4 bits divided into 2 banks 020 07F bankO 080 0BF bank a The Configuration of the System Register Address Bit3 Bit2 Bit1 BitO R W Remarks 00 R W Interrupt enable flags 01 IRQTO IRQP R W Interrupt request flags 02 TMO 2 TMO 1 0 0 R W TimerO Mode register Prescaler 03 Reserved 04 TLO 3 TLO 2 TLO 1 TLO O R W TimerO load counter register low digit 05 THO 3 THO 2 THO 1 THO 0 R W TimerO load counter register high digit 06 07 Reserved 08 PA 3 PA 2 1 0 R W PORTA 09 PB 3 PB 2 PB 1 0 R W 0A PC 3 PC 2 PC 1 0 R W PORTC Bit0 3 is reserved Always keep it to 0 0B 0C in the User s program Refer to notice 0D PF 1 PF 0 R W PORTF 0E TBR 3 TBR 2 TBR 1 TBR O R W Table Branch Register 0F INX 3 INX 2 INX 1 0 R W Pseudo index register 10 DPL 3 DPL 2 DPL 1 DPL O R W Data poi
8. 2 768KHz 4MHz C1 Crystal 4MHz 2 2 Ceramic resonator 400KHz 4MHz C1 Ceramic 400K 4MHz C2 3 RC oscillator 400KHz 4MHz VDD R OSCI C1 1000 OSCO L 4 External input clock 30KHz 4MHz OSCI External clock source OSCO 15 5 69 23 9 OTP Program Notice 9 1 OTP option a Oscillator range 0 OSC 32K 2MHz default 1 OSC 2M 4MHz b LPD voltage range 0 High LPD voltage default 1 Low LPD Voltage c LPD on off control 0 LPD off default 1 LPD on d WDT on off control 0 WDT on default 1 WDT off e Oscillator select 000 External clock default 100 RC Oscillator 400k 4M 110 Crystal Ceramic Resonator 400k 4M 111 X tal 32768Hz 9 2 OTP Program circuit diagram If the SH69P23 need to be programed in circuit the program interface can be connect as the following diagram Application PCB OTP SH6XPXX Writer VPP VDD SCK SDA To application circuit When the chip is being programmed the VPP SCK SDA should be separated from other appliction circuits If more detail information is needed please see the OTP writer s user manual 16 5 69 23 Instruction Set All instructions are one cycle and one word instructions The characteristic is memory oriented operation Arithmetic and Logical Instruction Accumulator Type Mnemonic Instruction Code
9. 44 0 H 1 8 13 2 PB2 9 12 pci PB3 10 11 0 1 V1 0 5 69 23 Block Diagram RESET OSCO OSCI RC Y WATCHDOG PRESCLALER e a CTL REG 8 BITS TIMER Up counter TIMER INTERRUPT OTPROM 4096 16 BITS DATA RAM 160 4 BITS PORTA 4 BITS PORTB 4 BITS PORTC 4 BITS PORTD 4 BITS PORTA 0 3 PORTB 0 3 PORTC 0 3 0 1 5 69 23 Pin Description Normail mode Pin No Designation Descriptions 20 1 PF 0 1 Bit programmable I O 18 19 2 3 PA 0 3 Bit programmable TO Timer Clock Counter input pin Schmitt trigger input RESET Reset input active low Schmitt trigger input GND Ground pin Bit programmable I O Vector Interrupt Active rising or falling edge by system PB 0 3 register setup Bit programmable 1 Vector Interrupt Active rising or falling edge by system register setup VDD Power supply pin OSCO OSC output pin No output for RC mode OSCI OSC input pin connected to a crystal ceramic or external resistor Pin Description OTP program mode e RESET voltage Power supply 10 5V Ground
10. Function Flag Change 00000 Obbb xxx xxxx AC lt Mx AC CY CY 00000 1bbb xxx xxxx AC Mx AC CY CY 00001 Obbb xxx xxxx AC Mx AC 00001 1bbb AC Mx Mx AC CY 00010 Obbb xxx xxxx AC lt Mx AC CY CY 00010 1bbb xxx xxxx AC Mx AC CY CY 00011 Obbb xxx xxxx AC lt Mx 1 00011 1bbb xxx AC lt AC 1 00100 Obbb xxx xxxx AC lt Mx 6 AC 00100 1bbb xxx AC Mx Mx AC 00101 Obbb xxx xxxx AC lt Mx AC 00101 1bbb xxx xxxx AC Mx lt Mx AC 00110 Obbb xxx xxxx AC lt Mx amp AC 00110 1bbb xxx xxxx AC Mx Mx amp AC 0 gt AC 3 AC 0 2CY AC shift right one bit X vj vj SEIS xix XK X 11110 0000 000 0000 Immediate Type Fee comm xi xi ow xi 00 In the assembler ASM66 V1 0 the EORIM mnemonic is EORI However EORI has the identical operation to EORIM The same is true for the ORIM with respect to ORI and ANDIM with respect to ANDI Decimal Adjustment 11001 0110 xxx AC Decimal adjustment for add 11001 1010 xxx xxx AC Mx Decimal adjustment for sub 17 5 69 23 Transfer Instructions LDA X B 00111 Obbb xxx x
11. SHR The Carry Flag CY holds the ALU overflow which the arithmetic operation generates During an interrupt servicing or call instruction the carry flag is pushed into the stack and retrieved back from the stack by the RTNI instruction It is unaffected by the RTNW instruction 1 3 Accumulator The Accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with the ALU data transfer between the accumulator and system register or data memory can be performed 1 4 Stack A group of registers are used to save the contents of CY amp PC 10 0 sequentially with each subroutine call or interrupt It is organized into 13 bits X 4 levels The MSB is saved for CY 4 levels are the maximum allowed for subroutine calls and interrupts The contents of the Stack are returned sequentially to the PC with the return instructions RTNI RTNW The stack is operated on a first in last out basis This 4 level nesting includes both subroutine calls and interrupts requests Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4 and the bottom of the stack will be shifted out The SH69P23 can address up to 4096 X 16 bit words of program area from 000 to FFF Service routine as starting vector address Address Instruction Remarks 000H JMP Instruction Jump to RESET service routine 001H NOP Reserved 002H JMP Instruction Jump to
12. UT 2 o gt gt 2 PBOUT 1 1 PBOUT O 0 Pcourisi gt PC 3 2 2 PCOUT 1 PCOUT O gt PC O 10 SH69P23 6 TO amp WDT System Register 1C 1C TOS TOE TO signal edge Bit1 TO signal source TOE TO signal edge 0 Increment on low to high transition TO pin Power on initial 1 Increment on high to low transition TO pin TOS TO signal source 0 OSC 1 4 Power on initial 1 Transition on TO pin Tos osca 9 1 TIMERO 8015 TO 1 x x TOE EOR 3 Built in RC Oscillator TMO 2 0 v WDT Enable OTP option WDT amp Warm 3 WDTreset YP Counter 14 WDT Timeout System Register 1E ow em om AW emm sie wot wl Bit3 Watchdog timer reset write 1 to reset WDT The input clock of the watchdog timer is generated by a built in RC oscillator so that the WDT will always run even in the STOP mode SH69P23 generates a RESET condition when the watchdog times out The watchdog can be enabled or disabled permanently by using the OTP option To prevent it timing out and generating a device RESET condition you should write this bit as 1 before timing out The WDT has a time out period of more than 7ms typical 18ms If longer time out periods are desired a prescaler with a divis
13. al Clock Event TO as 0 Source When an external clock event input is used for the TMO it is synchronized with the CPU system clock Therefor the external source must follow certain constraints The output from the TOM multiplex is TOC It is sampled by the system clock in instruction frame cycle Therefore it is necessary for the TOC to be high at least 2 tosc and low at least 2 tosc When the prescaler ratio selects 2 the TOC is the same as the system clock input Therefore the requirement is as follows TOCH TO high time gt 2 tosc AT TOL TOCL TO low time gt 2 tosc AT Note AT 40ns When another prescaler ratio is selected the TMO is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical Then 2 N TO TOC high time TOC low time 2 Where TO TimerO input period prescaler value The requirement is therefore N TO 5 2 tosc AT or TO gt 210921241 The limitation is applied for the period time only pulse width is limited by this equation It is summarized as follows 4 tosc 2AT TO TimerO period gt N 14 5 69 23 8 System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock to the CPU and any peripherals Instruction cycle time 1 4 32 768 122us for 32 768KHz system clock 2 4 AMHz 1us for 4AMHz system clock 8 1 Oscillator 1 Crystal oscillator 3
14. ension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e is for PC Board surface mount pad pitch design reference only 4 Dimension S includes end flash 28 5 69 23 Product Spec Change Notice SH69P23 Specification Revision History Version Content Date Reduce operating current 10 Add RC Frequency Resistance diagram 0 1 Original Mar 2003 29
15. ent sunk by any I O port 25mA Max Output current sourced by any port 20mA Max Output current sunk by all ports A B C D E 2 50 Max Output current sourced by all ports A B C D E F 40mA AC Electrical Characteristics VDD 3 0V GND 0V 25 unless otherwise specified Parameter Symbol in Condition Oscillator Start Time 1 Crystal Osc 32 768KHz 3 0V RESET pulse width low TRESET VDD 3 0V WDT Period TWDT 7 Vpp 3 0V Frequency Stability RC A F F RC oscillator 1MHz F 3 0 F 2 7 F 3 0 Low Power Detect Electrical Characteristics VDD 2 4 6V GND TA 25 C Fosc 4MHz unless otherwise specified Parameter in i Condition LPD Voltage Low LPD enable 20 5 69 23 LPD Voltage High VLPD2 3 8 4 0 4 2 V LPD enable Low power detect ignore time tLPD 100 300 500 us LPD enable and lt 21 5 69 23 Characteristics Symbol Parameter Min Typ Max Unit Condition Tiw TO Input Width Tev 40yN m Prescaler divide ratio Timing Waveform TO Input Waveform TO Built in RC Oscillator Only use for Watch Dog 22 5 69 23 Typical RC oscillator Resistor vs Frequency Vpp 5V for reference only 5V RC Frequency 10000 00 N 1000 00 LL 100 00 1 1 1
16. hip reset please first write 1111B to 19 1A and write 0000 to 0B 0C Otherwise the halt current and stop current will be abnormal PAXOUT PBXOUT PCXOUT X 0 1 2 3 PFXOUT X 0 1 1 Use as an output buffer 0 Use as an input buffer Power on initial PBCFR 1 Rising Edge interrupt 0 Falling Edge interrupt PH PL 1 Port Pull up resister ON 0 Port Pull low resister ON PULLEN 1 Port Pull up Pull low enable 0 Port Pull up Pull low disable 5 69 23 PORTB amp PORTC interrupt The PORTB and PORTC are used as port interrupt sources Since PORT 1 is bit programmable I O so only the input port can generate an external interrupt When PBCFR set to 0 any one of the PORTB and PORTO input pin transitions from VDD to GND will generate an interrupt request And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD When PBCFR set to 1 any one of the PORTB and PORTO input pin transitions from GND to VDD will generate an interrupt request And further rising edge transition would not be able to make interrupt request until all of the pins return to GND Following is the port interrupt function block diagram PBOUT 3 PB 3 PBOUT 2 PB 2 PBOUT 1 PB 1 PBOUT O PB O PCOUTI 3 PC 3 2 21 PCOUT 1 PC 1 0 PC 0 1 E PORT INTERRUPT PBOUTISI o gt DETECT PORTINT PB 3 Ss PBO
17. ion ratio of up to 1 2048 can be assigned to the WDT under software controll by writing to the 0 register 11 SH69P23 Pre scaler divide ratio Prescaler Divide Ratio Timer out Period 1 1 7ms min 1 2 14ms min 1 4 1 8 28ms min 56ms min 1 32 224ms min 1 128 896ms min 1 512 3 584ms min 1 1 1 1 0 0 0 0 RC OSC 1 2048 Power on initial 14 336ms min WDT Time 0 875ms out Period 4 Internal 7ms mi SCALER 1 18 1 12 4 18 132 1128 1512 12048 Final WDT Time out period 12 7 0 5 69 23 SH69P23 has 8 bit timer The time counter has the following features 8 bit timer counter Readable and writeable Automatic reloadable counter 8 prescaler scale is available Internal and external clock select Interrupt on overflow from FF to 00 Edge select for external event Following is a simplified timer block diagram TOE TOS 7 1 Configuration and Operation TimerO consists of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH The counter and load register both have low order digits and high order digits Writing data into the timer load register TLOL TLOH can initialize the timer counter Load register programming Write the l
18. nter for INX low nibble 11 DPM 2 DPM 1 DPM 0 R W Data pointer for INX middle nibble 12 DPH 2 DPH 1 DPH O R W Data pointer for INX high nibble 13 14 Reserved Bit1 PBC interrupt rising failing edge set 15 PULLEN PH PL PBCFR R W Bit2 Port pull hi low set Bit3 Port pull up low enable control 16 2 PA1OUT PAOOUT R W PortA input output control 0 input 1 output 17 PB3OUT 2 PB1OUT PBOOUT R W PortB input output control 0 input 1 output 18 PC3OUT PC2OUT PC1OUT PCOOUT R W PortC input output control 0 input 1 output Bit0 3 is reserved Always keep it to 1 19 1A in the User s program Refer to notice 1B PF1OUT PFOOUT R W PortF input output control 0 input 1 output TO signal edge c 7 7 Tos ME i Bit1 TO 4 1D Reserved 1E WDT W WDT timer reset write 1 to reset WDT 1F Reserved System Register 00 12 except 07H refer to SH6610C User manual Power Reset Pin Reset Low Voltage Reset SH69P23 WDT Reset 0 0 0 0 0 0 0 0 000 000 1 1 1 1 2 1 2 1 DPL 2 DPL 1 DPM 2 DPM 1 DPH 2 DPH 1 PBCFR PB1OUT PBOOUT PC1OUT PCOOUT PULLEN PH PL PA3OUT 2 PB3OUT 2 PC3OUT 2
19. od Twdt 5 0V Frequency Stability RC F F RC Oscillator F 5 0 F 4 5 F 5 0 19 _ SH69P23 DC Electrical Characteristics 3 0V GND OV 25 C Fosc 4MHz unless otherwise specified Parameter in i Condition Operating Voltage All output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded All output pins unloaded Stand by Current STOP LPD off If LPD on IsB2x IsB2 2uA WDT off If WDT on IsB2x IsB2 5 Input Low Voltage GND 0 2 X I O ports pins tri state Operating Current Input Low Voltage GND 0 15 X VDD RESET Input Low Voltage GND 0 15 X VDD OSCI Driven by external clock Input High Voltage 0 8 X VDD VDD I O ports pins tri state Input High Voltage 0 85 X VDD VDD RESET TO Input High Voltage 0 85 X OSCI Driven by external Clock 3 meme ceci Curent 5 E npr saps Cone r a Var Von rou Curent 3 3 onov I O ports 7mA VDD 3V OSCOnrc 0 7mA VDD 3V I O ports lol 8mA VDD 3V 5 1 0mA 3V Output High Voltage Output Low Voltage User Notice Max Current into VDD 50mA Max Current out of Vss 150mA Max Output curr
20. ow order digit first and then the high order digit The timer counter is loaded with the contents of the load register automatically when the high order digit is written or the counter counts overflow from FF to 00 Timer Load Register Since the register H controls the physical READ and WRITE operation please follow these rules Write Operation First write Low nibble Then write High nibble to update the counter PRE SCALER TOM 8 BIT COUNTER Read Operation High nibble first Followed by Low nibble Load Reg L Load Reg H 8 bit timer counter Latch Reg L 13 5 69 23 7 2 0 Interrupt The timer overflow will generate an internal interrupt request when the counter counts overflow from FF to 00 If the interrupt enable flag is enabled then a timer interrupt service routine will proceed This can also be used to waken the CPU from HALT mode 7 3 0 Mode Register The timer can be programmed in several different prescaler ratios by setting the Timer Mode register TMO The 8 bit counter counts prescaler overflow output pulses The timer mode registers 0 3 bit registers used for timer control as shown in table1 These mode registers select the input pulse sources into the timer Table 1 Timer 0 Mode Register 02 Prescaler Divide Ratio Ratio N 12 2048 initial 512 128 32 8 4 2 7 4 Extern
21. pull low resister which is controled by PULLEN and PH PL of 15 Each of these ports contains 4 or 2 PF bits I O pins ON OFF of the output buffer for port can be controlled by the port control register Port I O mapping address is shown as follows 08 PA 3 PA 2 PA 1 PA 0 R W PORTA 1111 09 PB 3 PB 2 PB 1 0 R W PORTB 1111 0A PC 3 PC 2 1 0 R W PORTC 1111 0B 0C ents is reserved Aways keep it to 0 in the User s program 0D PF 1 R W PORTF 1111 Equivalent Circuit for a Single I O Pin VDD PULL EN AND PH PL AND 5o VDD DATA p WRITE RESET VO PIN DATAIN 4 gt CONTROL WRITE gt RESET RESET 21 GND PULL EN AND PH PL i V GND 5 69 23 CN 16 1B PBC interrupt rising failing edge set PULLEN PH PL PBCFR R W Bit2 Port pull hi low set Bit3 Port pull up low enable control 16 PA3OUT PA2OUT W PortA input output control 0 input 1 output PB3OUT PB2OUT PB1OUT w PortB input output control 0 input 1 output PC2OUT PC1OUT PCOOUT PortC input output control 0 input 1 output 19 1A Bit0 3 is reserved Always keep it to 1 in the User s program 18 PF1OUT PFOOUT PortF input output control 0 input 1 output For SH69P23 after the c
22. xxx AC lt Mx STA X B 00111 1bbb xxxx Mx lt AC LDI X 01111 xxx AC lt 1 Control Instructions 0 O Toros ST 1 lt X Not including p 11000 57 lt hhhh lt 1 pe No Operation Complement of accumulator Logical OR ST Carry flag amp Logical AND Mx Data memory bbb RAM bank RTNW H L 11010 000h hhh IIII Where Immediate data RAM bank Every 7F as one RAM bank Table Branch Register 18 SH69P23 Absolute Maximum Rating Comments DC Supply Voltage 0 3V to 7 0V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device Input 0 3V to VDD 0 3V These are stress ratings only Functional operation of this device under these or any other conditions above those Operating Ambient Temperature 40 C to 85 C indicated in the operational sections of this specification is not implied or intended Exposure to the absolute maximum Storage Temperature 55 C to 125 C rating conditions for extended periods may affect device reliability DC Electrical Characteristics 5 0V GND
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