NAR-5071 User`s Manual
Contents
1. PROMP TEST OK db lt PPAP 3714 RESET TO DEFAULT test OK gt gt 0dh 0ah PROMP_TEST_fail db lt lt PPAP 3714 RESET TO DEFAULT test FAIL gt gt Odh 0ah PROMP_Qkey db Odh 0ah Press Q key to stop test and return to DOS or other key to go on next test debugtesting db Odh Oah lt lt lt lt lt This is for debugging only gt gt gt gt gt Odh 0ah GP_INV_OFFSET db 2Ch The offset value from GPIOBASE GPEO STS OFFSET db 28h The offset value from PMBASE GH LVL OFFSET db OCh The offset value from GPIOBASE GD BLINK OFFSET db 18h Must let GPIO19 to be Blink disabled for normal GPIO function GPIO USE SEL OFFSET db 00h GPIO USE SEL Bit19P1 as GPIO function PMBASE dw GPIOBASE dw code programstart mov ax data mov ds ax lea dx PROMP_2 CR LF mov ah 09h Int 21h lea dx PROMP1 mov ah 09h Int 21h lea dx PROMP_2 CR LF mov ah 09h Int 21h lea dx PROMP1_1 mov ah 09h Int 21h lea dx PROMP_2 CR_LF mov ah 09h int 21h lea dx PROMP_ Str mov ah 09h Int 21h lea dx PROMP_ Str2 mov ah 09h Int 21h lea dx PROMP_ Str3 mov ah 09h Int 21h lea dx PROMP_ Str4 mov ah 09h Int 21h lea dx PROMP_ Str5 mov ah 09h Int 21h lea dx PROMP_ Str6 NAR 5100 User s Manual 21 mov ah 09h int 21h lea dx PROMP_ Str7 mov ah 09h Int 21h lea dx PROMP_ Str8 mov ah 09h Int 21h lea dx PROMP_ Str9 mov ah 09h Int 21h lea dx PROMP2. count in CX then return Gives a programmed software delay S FIXDELAY PROG near push cx push dx push ax pushf mov cx 02h mov dx 61h in al dx jmp 2 jmp 2 and al 00010000b mov ah al fixed delay 1 in al dx jmp 2 jmp 2 and al 00010000b cmp al ah jz shortfixed delay 1 mov ah al loop short fixed delay 1 popf pop ax pop dx pop CX ret FIXDELAY ENDP END programstart 2 18 WDT Information This is a test program for 32 bit protected mode memory access The compiler id DJGPP please refer http www delorie com digpp 7 This program is to test Intel 6300ESB ICH internal WDT C include lt dpmi h gt include lt sys types h gt include lt sys movedata h gt include lt go32 h gt include lt pc h gt include lt keys h gt include lt unistd h gt include lt dos h gt include lt conio h gt Constant define define VenderlD 0x8086 define DevicelD 0x25ab Intel 6300ESB ICH WDT D2 F4 define Mem_ Size 4096 NAR 5100 User s Manual 29 define KEY 1 0x31 define KEY 2 0x32 define KEY 3 0x33 define Preload Value 1 offset 0x00 define Preload Value 2 offset 0x04 define Int Sts offset 0x08 define Reload Reg offset OxOc Varriety define unsigned long Base Addr to save memory base address of four 878A int Sel LDT selector unsigned char time _out _ dpmi regs regs subprogram void Search PCI WDT voi
3. turn turn on blinking block cursor show turn on underline cursor scl scroll cursor one character left scr scroll cursor one character right R setdis set character generator address g Procedure 1 The program sets up the environment i e com port settings 2 The main function MUST call init twice to initialize EZIO before any communication 3 For executing any command the command prefix Cmd MUST be called be command So all command contains two parts eg to initialize the sequence of HEX number is OxFE 0x25 4 After clear screen and display welcome message ReadKey method must be call to advise EZIO for reading data 5 A pooling method is implemented to get input from EZIO while any button is pressed NOTE This program is a sample program provided AS IS with NO warranty Copyright c Portwell Inc All Rights Reserved a NAR 5100 User s Manual 47 include lt sys stat h gt include lt fcentl h gt include lt unistd h gt include lt stdlib h gt Static int fd void SetEnvironment system stty ispeed 2400 lt dev ttyS1 system stty raw lt dev ttyS1 int Cmd 254 EZIO Command int cls 1 Clear screen void Cls write fd amp Cmd 1 write fd amp cls 1 int init 0x28 void Init write fd amp Cmd 1 write fd amp init 1 int stopsend 0x37 void StopSend write fd amp Cmd 1 wri
4. Carn Direct to Come Direct to Corn Direct ta Cord TCP IP insack 4 Please make the port settings to Baud rate 19200 Parity None Data bits 8 Stop bits 1 Port Settings Bits per second 15200 lt Data bits Parity Stop bits i Elow control Hardware mf Advanced Restore Defaults a l 5 Turn on the power of NAR 5100 series after following screen was shown NAR 5100 User s Manual 13 g port HyperTerminal File Edit View Call Transfer Help Ta 4 K Connected 0 00 15 Auto detect Auto detect SCROLL CAPS NUM Captu 4 6 You can then see the boot up information of NAR 5100 series ep HyperTerminal File Edit View Cal Transfer Help Award Nodular BIOS v6 8H46PG An Energy Star Snas Copyright C 1984 2861 Award Software Inc Portwell Inc PPAP 288 BIOS Version R1 B1 U2 L 18172881 Nain Processor Intel Pentium III 888EB MHz 133x6 8 Memory Testing 261 128K OK 1824K Shared Memory Main Memory Clock is 188 MHz Primary Master PAI IDE DiskOnModule db 1 19a Primary Slave None Secondary Master None Secondary Slave None Connected 0 00 19 Auto detect 19200 R M 1 SCROLL CAPS NUM Capture E 7 When message Hit lt DEL gt if you want to run Setup appear during POST after turning on or rebooting the computer press lt Tab gt key immediately to enter BIOS setup program This is the end of this section If the terminal did not po
5. Fig 2 8 Compact Flash Card Fig 2 9 Insert Compact Flash Card into the CF NAR 5100 User s Manual 6 interface 2 The completed installation of Compact Flash Card is shown as Fig 2 10 Fig 2 10 Completion of Compact Flash Card connection 2 Remove and Install Battery 1 Press the metal clip back to eject the button battery Fig 2 11 2 Replace it with a new one by pressing the battery with fingertip to restore the battery Fig 2 12 oe i A T DHS TT E r Fig 2 11 Eject the battery 2 8 Install HDD The system has an internal drive bay for one 2 5 hard disk drive If the HDD is not pre installed you can install it by yourself Follow the steps below to install the HDD 1 Install HDD connector with HDD Fig 2 13a 2 13b NAR 5100 User s Manual T tet TR BE lt Fig 2 13a A 2 5 HDD and the HDD bracket 2 Fasten the six screws to lock HDD and bracket together Fig 2 14 3 Connect HDD to NAR 5100 Fig 2 15 Fig 2 13b Install HDD Connector to HDD Fig 2 14 Fix HDD to the bracket Fig 2 15 Connect IDE to PPAP 3714L 7 2 11 Ear Mount Kit Installation The NAR 5100 shipped with 2 ear mount kits The following is the installation instruction of these ear mounts 1 Take out the L shape ear mount kits One ear mount fits on one side of the chassis 2 Placing the side with three holes agonists the chassis and the side with two holes face outward Fig 2 2
6. RAM 3 0011 RAM 4 0100 RAM C a in PS mg 0111 RAM 1000 RAM CG 1001 RAM CG 1010 RAM CG 1011 RAM CG 1100 RAM CG 1101 RAM 1110 RAM 1111 RAM NAR 5100 User s Manual 2 20 10 Sample Codes aa kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk EZIO RS232 LCD Control Sample Program K kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kk k kkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Company Portwell Inc Date 4 16 2003 Program 02A c Version 1 02 Compile Linux GNU C Purpose Direct access to EZIO LCD the program will display messages according to the control button The current version only has the following function 1 display welcome message 2 display UP message if scroll up button is pressed 3 display ENTER message if ENTER button is pressed 4 display ESC message if ESC button is pressed 5 display DOWN message if scroll down button is pressed Program Overview R Parameters fd a file name for open method here represents the com port i Cmd command prefix cls clear command init initialize command blank display blank screen K stopsend stop input output ij home move cursor to initial position readkey set to read from EZIO hide hide cursor amp display blanked characters movel move cursor one character left mover move cursor one character right
7. Sel Preload Value 2 offset i Do reload to make sure active reload wdt set WDT Lock Reg NAR 5100 User s Manual 31 regs x ax 0xb10b set PCI Cfg Byte regs x di 0x0068 get CR Ox68 regs h cl 0x02 WDT is WDT mode WDT enable Unlock _ dpmi int Oxla amp regs int main int i j unsigned char k Search PCI WDT prepare access above 1mb Show Select do do i getkey while i lt KEY_1 amp amp i gt KEY_3 switch i case KEY_1 enable_wat break case KEY 2 reload wdt break case KEY 3 disable wdt return 0 break Show Select while 1 2 19 GPIO Information For PPAP 3714 GPIO testing By Frank Hsu 06 03 2004 GPIO on PPAP 3714 PPAP 3714 J11_Pin1 GPIO4 from HR _GPIO43 J11_Pin3 GPIO3 from HR_GPIO42 J11_Pin5 GPIO2 from HR_GPIO41 J11_Pin7 GPIO1 from HR_GPIO40 J11_Pin9 VCC J11_Pin10 GND Programming Guide ECX_Bit 31 16 How to program GPIO 40 41 42 43 Get GPIOBASE B0 D31 FO Offset 58 5Bh and let bito 0 GPIO_CNTL B0 D31 F0 Offset_5Ch_bit4P1 Enable ICH4 GPIO GPIO USE SEL2 GPIOBASE 30h Bit 11 8 P 1 1 1 1 GP_IO SEL2 GPIOBASE 34h Bit 11 8 1 gt Input 0 gt Output NAR 5100 User s Manual 32 PG_Step1 Enable GPIO IO function and get GPIOBASE then save to GP _LVL2 GPIOBASE 38h Bit 11 8 Input readback output 1 high O low GPIO40 gt bit8 G
8. WDT n printf 2 Retriggle WDT n printf 3 Disable WDT and Exit n printf n nPress 1 3 void reload_wat void _farpokeb Sel Reload Reg offset 0x80 _farpokeb Sel Reload Reg offset 0x86 _farpokeb Sel Reload Reg offset 1 0x01 void disable_wat void set WDT Lock Reg regs x ax 0xb10b set PCI Cfg Byte regs x di 0x0068 get CR 0x68 regs h cl 0x00 WDT is WDT mode WDT disable Unlock __dpmi_int Oxta amp regs void enable_wadt void unsigned long Get PCI Device s Addr info regs x ax 0xb102 find PCI device regs x dx VenderlD Vender ID regs x cx DevicelD Device ID regs x si i Device index __dpmi_int Oxla amp regs set WDT Configuration Reg regs x ax 0xb10b set PCI Cfg Byte regs x di 0x0060 get CR Ox60 regs h cl 0x03 WDT Out enable Clock is 1Khz Disable INT when first stage reached _ dpmi int Oxla amp regs printf n nPress number 1 1000 to select time out time second scanf d amp time_out Preload Value 1 Reg always set to about 1 Second _farpokeb Sel Reload Reg offset 0x80 _farpokeb Sel Reload Reg offset 0x86 i 0Ox000003e8 _farpokel Sel Preload_Value_1_ offset i Preload Value 2 Reg get by key press _farpokeb Sel Reload Reg offset 0x80 _farpokeb Sel Reload Reg offset 0x86 i time_out 1000 999 _farpokel
9. char mes4 Down is selected char mes5 Enter is selected char mes6 ESC is selected char nul int a b void ShowMessage char str1 char str2 a Strlen str1 b 40 a write fd str1 a write fd nul bi write fd str2 strlen str2 int main SetEnvironment Set RAW mode fd open dev ttyS1 O RDWR Open Serial port COM2 Init Initialize EZIO twice Init Cls Clear screen ShowMessage mes1 mes2 NAR 5100 User s Manual 49 while 1 int res char buf 255 SetDis ReadKey sub routine to send read key command res read fd buf 255 read response from EZIO switch buf 1 Switch the Read command case 0x4D Up Botton was received Cls ShowMessage mes1 mes3 display Portwell EZIO break display Up is selected case 0x47 Down Botton was received Cls ShowMessage mes1 mes4 display Portwell EZIO break display Down is selected case Ox4B Enter Botton was received Cls ShowMessage mes1 mes5 display Portwell EZIO break display Enter is selected case OX4E Escape Botton was received Cls ShowMessage mes1 mes6 display Portwell EZIO break display Escape is selected Chapter3 Operation Guide 3 1 Brief Guide of PPAP 3714L PPAP 3714L is an Intel Pentium 4 based board with Cavium Nitrox Lite CN
10. failed t3 Clear RST2DF status to 0 read GPI6 GPI6 0 if yes pass if no failed a t_start make sure GPO19 1 start RST2DF F F no cleared by GPO19 xor bx bx mov bl GP_LVL_OFFSET Write GPO19 1 mov dx GPIOBASE add dx bx add dx 02h point to GPIO 16 23 register in al dx read first call IODELAY io delay or al 08h bit3 gt GPO19 out dx al output GPO19 1 make sure GPO19 1 end GP INV bit6 MUST Program 0 for GPI6 state not inverted start xor bx bx mov bl GP_INV OFFSET Not invert GPI6 status mov dx GPIOBASE add dx bx in al dx read first call IODELAY io delay and al OBFh mask bit6 and write 0 out dx al GP INV bite MUST Program 0 for GPI6 state not inverted end t1 start GPI6 read its status initialization will be O NAR 5100 User s Manual 24 How to read GPI6 Get GPI6 status from GPEO STS PMBASE 28h bit22 O low 1 high level call READ GPI6 TO AL and al 40h mask bit6 cmp al 00h je next test1 okay go on test no error message display lea dx promp_err1 mov ah 09h int 21h lea dx promp erri 1 mov ah 09h int 21h ror edx 10h error falg EDX Bit16 1 gt Error happened or dl 01h rol edx 10h call KB Wait t1 end next test1 t2 start lea dx promp_rst2df mov ah 09h int 21h lea dx opromp_anykey mov ah 09h int 21h xor al al halt for ready Any key pressed to go on WAIT KB 0 mov ah 1
11. in Socket 478 to support Intel mPGA Celeron Pentium 4 processor 533 800MHz FSB for cost effective and high performance application The provides a completely integrated solution for the system controller and data path components in a Celeron Pentium 4 processor system It provides optimized 64 bit DDRAM NAR 5100 User s Manual 51 interface with one 184 pin 2 5V DIMM The provides a highly integrated multifunction for the best industry applications It supports 2 channel dedicated Ultra ATA 33 66 100 IDE master interface Universal Serial Bus USB controllers and two 32 bit PCI bus interfaces All detailed operating relations are shown in Fig 3 2 PPAP 3714L System Block Diagram VRM 10 0 K 478 PIN P4 PROCESSOR EEE DEEE CHANEL_ DDR Modules 875P a CHAMEL_ amp DDR Modules p TUE LNK EAK bh IDE Pri emee 6300ESB GDG USB PORT 1 2 USB2 0 a Hub Sariai WBIEZT PSfz K B MIS Figure 3 2 PPAP 3714L Block Diagram NAR 5100 User s Manual 52
12. int 21h cmp al 0 je WAIT KB 0 lea dx PROMP_2 CR LF mov ah 09h int 21h test RST2DF button pressed call READ GPI6 TO AL and al 40h mask bit6 cmp al 40h je next_test2 okay go on test no error message display NAR 5100 User s Manual 25 lea dx promp err2 mov ah 09h int 21h ror edx 10h error falg EDX Bit17 1 gt Error happened or dl O2h rol edx 10h call KB Wait t2 end next test2 t3 start Clear RST2DF F F GPO19 write 1 0 1 ii Write GPO19 1 0 1 start xor bx bx mov bl GP LVL OFFSET Write GPO19 1 mov dx GPIOBASE add dx bx add dx 02h point to GPIO 16 23 register in al dx read first call IODELAY io delay or al 08h out dx al output GPO19 1 first call FIXDELAY 30 us delay in al dx output GPO19 0 then call IODELAY and al OF h out dx al call FIXDELAY 30 us delay in al dx output GPO19 high finally call IODELAY or al 08h out dx al iid Write GPO19 1 0 1 end call READ GPI6 TO AL check RST2DF F F and al 40h mask Bit6 cmp al 0O0h je test end okay then end jz test end okay then end no error message display lea dx promp_err3 mov ah 09h NAR 5100 User s Manual 26 Int 21h ror edx 10h error falg EDX Bit18 1 gt Error happened or dl 04h rol edx 10h t3 end test end ror edx 10h check error flag cmp dl 00h je test_ok test_fail lea dx PROMP_2 CR LF mov ah O9h int 21h lea dx opromp_TEST
13. out dx al call IODELAY io delay in al dx and al 05h Mask bit 2 0 cmp al 00h je next_test2 okay go on test no error message display NAR 5100 User s Manual 36 lea dx promp err2 mov ah 09h int 21h ror edx 10h_ error falg EDX_Bit17 1 gt Error happened or dl O2h rol edx 10h call KB Wait next test2 t2 end for t3 and t4 define GPI43 41 GPO42 40 Define GPIO as input or output pin 1 input pin O output pin GP IO SEL2 GPIOBASE 34h _bit 11 8 P 1 0 1 0 mov bl GP IO SEL2 OFFSET Define GPO GPI pin mov dx cx add dx bx GP IO SEL inc dx in al dx Read First and al 0FOh GPI43 41 GPO42 40 or al 0Ah call IODELAY io delay out dx al D start GPO42 Write 1 to GPI43 GPI43 1 if yes pass if no failed GPO40 Write 1 to GPI41 GPI41 1 if yes pass if no failed Output value or read status GP_LVL2 GPIOBASE 38h _bit 11 8 Output value When output pin defined Read returned status when input pin defined mov bI GP_LVL2 OFFSET GPO42 Write 1 to GPI43 mov dx cx gt GPO40 write 1 to GPI41 add dx bx GP_LVL2 inc dx l in al dx Read First or al 05h call IODELAY io delay out dx al call IODELAY io delay in al dx and al Oah Mask bit3 1 GPI43 41 cmp al Qah je next test3 okay go on test no error message display lea dx promp_err3 mov ah O9h int 21h NAR 5100 User s Manual 3 ror edx 10h error falg ED
14. words the Serial Port is defined as DCE Therefore we can use a straight through cable to connect it to the Serial Port of most of the computers defined as DTE 1 Interface Pin Assignment PIN NO PIN OUT Description NC No connector Vss 2 Power PIN OUT Description GND Power GND GND Power GND 5V Power VCC 5V 2 20 Hardware installation The installation steps are e Connect the power connector to the power connector of this module Connect the straight through cable between Serial Port of this module and computer NAR 5100 User s Manual 42 2 20 8 EZIO Function Command First all versions OOA 01A 02A of EZIO can use those commands Only the 02A version of EZIO firmware that adds FE 28 amp FE 37 command can control start of HEX amp End of HEX EZIO is an intelligent device which will display those data received from RS 232 port and reply key pressing status to polling command from RS 232 port Both commands and data go thru RS 232 ports To distinguish between data and commands the LCD key pad module recognizes a command prefix 254 Hex OFE The byte following 254 will be processed as a command For example to clear the screen send the command prefix 254 followed by the LCD clear screen code 1 The valid data range is shown as the following table Valid daia rande Displayed characters Customized icon 0 7 48 57 30 39 Hex 0 9 65 90 41 5A Hex 97 12
15. 1010X supporting IPSec SSL The onboard Cavium security processor provides a cost advantage and the flexibility to implement various networking appliances The PPAP 3714L has the capability of processing up 1GB IPSec traffic or 7000 RSA operations per second PPAP 3714L is a Communication Appliance computing board based on Intel 875P chipset technology PPAP 3714L has ten on board LAN ports to serve communication appliances such as Firewall which needs sufficient ethernet ports to connect external network internet demilitarized zone and internal network Different I O management policies can be applied respectively to individual network to achieve the highest security level The target market segment is communication appliance including Virtual Private Network Load Balancing Quality of Service Intrusion Detection Virus Detection Firewall and Voice Over IP This PPAP 3714L system board is utilized with Intel mPGA Celeron and Intel mPGA Pentium 4 processors and 184 pin DIMM The enhanced on board PCI IDE interface supports 2 drives up to PIO mode 4 timing and Ultra DMA 100 synchronous mode feature The on board NAR 5100 User s Manual 50 Intel 6800ESB chipset integrates two serial ports driven by two high performance 16C550 compatible UARTs to provide 16 byte send receive FIFOs In addition the two Universal Serial Bus ports provide high speed data communication between peripherals and PC The on board flash ROM is used to make
16. 2 61 7A Hex To get the key pressing status a read key command can be issued to this module which will check the key pressing status and reply accordingly The following are the commands and corresponding Decimal Hex values Functions commands Decimal Hex Comment Start Of HEX 4028 Only for 02A End Of HEX 55 37 Only for 02A Clear screen Blank display taining gaa sw oo 7 Hide cursor amp display blanked characters 1200 Turon blinking block curso 10 9 Show underline cursor 14 0E 10 Move cursor 1 characterleft m Move cursor 1 oharacterright SOM 12 Sooltcharacterlet ee o 13 Scroll toharacterright sene S 14 Set display address position the cursor location 128 Hex080 Location 15 Set character generator address 64 Hex 040 address Note 1 Upon receiving the read key command from host computer the LCD keypad module will check the status of every key and reply with status command accordingly The replied message from LCD key pad module consists of a header and a status byte The header byte is 253 HexOFD The high nibble with the most significant bit of the status byte is always 4 and the low nibble with the least significant bit of the status byte is used to indicate key pressing status of the keypad module This nibble will be F of four 1s if no key pressed while the read key received O will be used to indicate key pressing st
17. 51QM 10 100 Fast Ethernet controllers Seven Intel 82551ER 10 100 Fast Ethernet with RJ 45 interface for NAR 5100 Support on board hardware monitor for Totally four for CPU and System fan System voltages Vcore 3 3V 5V and 12V On board power good interval 100ms 500ms Operating Temperature 5 C 40 C Storage Temperature 5 C 70 C Relative Humidity 5 95 non condensing 429 W x 330 D x 44 H mm 2 13 Hardware Configuration Setting This section gives the definitions and shows the positions of jumpers headers and connectors All of the configuration jumpers on PPAP 3714L are in the proper position The default settings NAR 5100 User s Manual 9 set by factory are marked with a star C Jumpers In general jumpers on PPAP 3714L system board are used to select options for certain features Some of the jumpers are configurable for system enhancement The others are for testing purpose only and should not be altered To select any option cover the jumper cap over Short or remove NC it from the jumper pins according to the following instructions Here NC stands for Not Connected Jumper Table Jumper Function Default Setting Watchdog function JP1 Short Reset Watchdog reset En Open NM1 SM1 CF Setup JP2 Short Master Master Open Slave CMOS Clear 1 2 CMOS normal CMOS normal 2 3 CMOS clear Figure 2 27 PPAP 3714L Jumper Table JP1 JP2 JP3 J11 6300E
18. 6 3 Fast three screws on each side Fig 2 26 gt O m m d E E E Rete aen T RE ME l Ch ri al 6001 fer FS Fig 2 26 Fasten the screws to the side NAR 5100 User s Manual 8 Model Main Processor BIOS Main Memory L2 Cache Memory Chipset PCI IDE Interface Serial Ports USB Interface Auxiliary I O Interfaces Power Input PCI Slot On board Ethernet Hardware Monitor Power Good Environmental Requirements Dimension 2 12 Product Specifications NAR 5100 Intel socket 478 Pentium 4 processors 533MHz or 800MHz system bus Award system BIOS with 512KB flash ROM to support DMI PnP APM function Totally four 333 400 MHz unregistered DDR on 184 pin DIMM socket supports up to 4GB of 2 5V DIMM with ECC 256KB 512KB PBSRAM built in Celeron Pentium 4 CPU module North Bridge Intel 875P South Bridge Intel 6300ESB One 40 IDE 1 interface for DMA 33 66 100 IDE hard disk Support two high speed 16550C compatible UARTs with 16 byte T R FIFOs Optional Support LCD Key pad module Portwell proprietary Support two USB2 0 ports for high speed I O peripheral devices System reset switch power okay LED and HDD LED interface Support one AC input jack power requirement 110V 220V auto switch One PCI slot for add on PCI card One Intel 82546EB 100 1000 Gigabit Fast Ethernet controllers with RJ 45 interface for NAR 5100 One Intel 825
19. 86 STACK 200h data PROMP1 DB PORTWELL PPAP 3714 3714RSTD exe V1 00 11 08 2004 All rights reserved PROMP1_ 1 DB For PPAP 3714 Reset to Default test 13 10 PROMP 2 CR LF db ODh 0Ah 0Dh OAh PROMP Str db Reset To Default status latched by a F F Odh 0ah NAR 5100 User s Manual 20 PROMP Str2 db This status bit 0 gt Normal Odh 0ah PROMP Str3 db This status bit 1 gt RST2DF button has been pressed Odh 0ah PROMP Str4 db This status bit can be read by ESB6300_GPI6 Odh 0ah PROMP_Str5 db and can be cleared by an ESB300 GPO19 High1 Low High2 pulse Odh 0ah PROMP Str6 db 0dh 0ah PROMP Str7 db Hight 30us High level 0dh 0ah PROMP Str8 db Low 30us Low level Odh Oah PROMP Str9 db High2 High level again and no level change from now on Odh 0ah PROMP_StrA db 0dh 0ah PROMP rst2df db Odh 0ah Press the Reset to Default button and then release it for the test NOW PROMP_anykey db Odh 0ah Ready If yes then Press any key to start test PROMP_err1 db Odh Oah Reset to Default F F Initialization Failed Odh 0ah PROMP err _1 db This may be a H W error or Reset to Default button has ever been pressed Odh 0ah PROMP err2 db Odh 0ah Reset to Default event latched by F F Failed Odh 0ah PROMP err3 db Odh Oah Clear Reset to Default F F status Failed Odh 0ah
20. Ch out dx eax mov dx 0OCFCh in eax dx or al 10h 5Ch Bit4P1 to Enable GPIO out dx eax mov dx 0CF8h Get GPIOBASE mov eax 8000F858h BO D31 FO Offset 58h NAR 5100 User s Manual 34 out dx eax mov dx 0CFCh in eax dx and al Ofeh bit O cleared to 0 rol eax 10h mov ecx eax Save GPIOBASE to ECX 31 16 Testing way t1 GPO43 Write 1 to GPI42 GPI42 1 if yes pass if no failed GPO41 Write 1 to GPI40 GPI40 1 if yes pass if no failed t2 GPO43 Write 0 to GPI42 GP142 0 if yes pass if no failed GPO41 Write 0 to GPI40 GPI40 0 if yes pass if no failed t3 GPO42 Write 1 to GPI43 GPI43 1 if yes pass if no failed GPO40 Write 1 to GPI41 GPI41 1 if yes pass if no failed 14 GPO42 Write 0 to GPI43 GPI43 0 if yes pass if no failed GPO40 Write 0 to GPI41 GPI41 0 if yes pass if no failed rol ecx 10h Restore GPIOBASE from ECX 31 16 to ECX 15 0 Let GPIO43 42 41 40 as GPIO pins by l GPIO USE SEL GPIOBASE 30h _bit 11 8 P 1 1 1 1 xor bh bh mov bl GPIO USE SEL2 OFFSET Define as GPIO pins mov dx cx GPIOBASE add dx bx GPIO USE SEL2 inc dx 3 in al dx Read first or al Ofh Set GPIO40 43 as GPIO pins out dx al for t1 and t2 define GPO43 41 GP142 40 E Define GPIO as input or output pin 1 input pin O output pin l GP IO SEL2 GPIOBASE 34h _bit 11 8 P 0 1 0 1 mov bl GP IO SEL2 OFFSET Defin
21. K PPAP 3714 GPIO test 3714GPIO EXE FAIL failed Odh Oah failed Odh Oah failed Odh Oah failed Odh Oah le Odh 0ah PO gt gt Odh 0ah PROMP_Qkey db Odh 0ah Press Q key to stop test and return to DOS or other key will go on next test GPIO USE SEL2 OFFSET db 30h The offset value from GPIOBASE GP IO SEL2 OFFSET db 34h The offset value from GPIOBASE GP_LVL2 OFFSET db 38h The offset value from GPIOBASE ECX_bit 31 16 save GPIOBASE B0 D31 F0 Offset 58 5Bh code programstart mov ax data mov ds ax lea dx PROMP_2 CR LF mov ah O9h int 21h lea dx PROMP 1 mov ah 09h int 21h lea dx PROMP_2 CR_LF mov ah O9h int 21h lea dx PROMP1_1 NAR 5100 User s Manual 33 mov ah 09h int 21h lea dx PROMP_2 CR LF mov ah O9h int 21h lea dx PROMP_ Str mov ah 09h Int 21h lea dx PROMP_ Str2 mov ah 09h Int 21h lea dx PROMP_ Str3 mov ah 09h Int 21h lea dx PROMP_ Str4 mov ah 09h Int 21h lea dx PROMP_ Str5 mov ah 09h Int 21h lea dx PROMP_ Str6 mov ah 09h Int 21h lea dx PROMP_anykey ready to go mov ah 09h int 21h xor al al WAIT KB 0 mov ah 1 Int 21h cmp al 0 je WAIT KB 0 lea dx PROMP 2 CR LF mov ah O9h int 21h mov edx 00000000h Error flag in EDX_BIT 16 19 O ok 1 failed PG_Step1 Enable GPIO IO function and get GPIOBASE then save to l ECX_Bit 31 16 mov dx 0CF8h mov eax 8000F85Ch BO D31 F0 Offset_5
22. NAR 5100 Series Communication Appliance User s Manual Revision 010 Portwell Inc 3F No 92 Sec 1 Nei Hu Rd Taipei 114 Taiwan R O C Headquarter 886 2 2799 2020 FAX 886 2 2799 1010 http www portwell com tw Email info mail portwell com tw ED ISO 9001 Table of Contents Chapter IN T Kele 151 e y T lt 7 1 nnn ended ee 2 1 1 ADOUE TINS MIN TTT 2 1 2 Manual ONG eT lee nele tee eieren tanden 2 1 3 Technical Suppor dieer rel svesne teen A ERNE EA EEEa 2 Chapter 2 Getting Started ssssssssssssssssssssess enesenn ennenen ennenen ennenen 4 2 1 siea CG AWWA Esya a a a a 4 2 2 Boole VOUS COUN erite REE EE E tenen E T blended 4 23 TTC E E eeen E E E 5 2 4 Oper ECI EN 5 2 Remove ANG IST DIMM isanne antennes EAER AE 6 2 6 Remove and Install Compact Flash Card eee ee 6 2 7 Remove ano INS SANO nummerde vetten eene 7 2 8 ere Ta TT 7 2 11 Ear WVIOUNE Terre erenn a a O hoes E ene Oaa 8 2 12 Product eT eel iee 9 2 13 Hardware CONMOUTATON SEUN erdee E E eae 9 2 14 NSt ll a Diflerent PIOCSSSON annen a REA E RA A ETDS 12 2 15 se CIE COMPU TT 12 2 16 BIOS SUP IMONMANON renster edeler eeen 14 2 17 FICSC 10 DOI INO MAU ON zena aie aeie 20 2 18 UV EDT IOM Onnette entier E A RUT O 29 2 19 GPO AMON AQUON wanna nea enh 32 2 20 ADOULEZIO WOO renden nnee eene enden 40 Chapter 2 Operation Guide ette cede cewase ve venen neat menin earneanden senden neni eenen eneen 50 3 1 Br f GOE Of PPAPSSLTAE wairere a A 50 3 2 Syst
23. PIO41 gt bit9 GPIO42 gt bit10 GPIO43 gt bit11 Let GPIO40 41 42 43 as GPIO pins by GPIO USE SEL2 GPIOBASE 30h _ bit 11 8 P 1 1 1 1 Define GPIO as input or output pin 1 input pin O output pin GP IO SEL2 GPIOBASE 34h _bit 11 8 P 0 1 0 1 0 1 0 1 Output value or read status GP LVL2 GPIOBASE 38h _bit 11 8 Output value When output pin defined Read returned status when input pin defined MODEL tiny 386 STACK 200h data PROMP1 DB PORTWELL PPAP 3714 GPIO 3714GPIO exe V1 00 06 03 2004 All rights reserved PROMP1 1 DB For PEB 3714 GPIO test 13 10 PROMP 2 CR LF db ODh 0Ah 0Dh OAh PROMP Str db PPAP 3714 J11_Pin1 GPIO4 from HR ICH GPIO43 Odh 0ah PROMP Str2 db J11_Pin3 GPIO3 from HR ICH_GPIO42 0dh 0ah PROMP Str3 db J11_Pin5 GPIO2 from HR ICH_GPIO41 Odh 0ah PROMP Str4 db J11_Pin7 GPIO1 from HR ICH_GPIO40 Odh 0ah PROMP Str5 db Odh Oah PROMP_Str6 db Put a jumper cap on J11 pin1 and 3 another jumper cap on pind and 7 Odh 0ah PROMP_anykey db Odh 0ah Ready If yes then Press any key to start test PROMP_err1 db Odh 0ah GPO43 41 write 1 1 to GP142 40 PROMP_err2 db Odh 0ah GPO43 41 write 0 0 to GP142 40 PROMP_err3 db Odh 0ah GPO42 40 write 1 1 to GP143 41 PROMP_err4 db Odh 0ah GPO42 40 write 0 0 to GPI43 41 PROMP_TEST_OKdb PROMP_TEST_fail db lt lt PPAP 3714 GPIO test 3714GPIO EXE O
24. SB 875P O oee GESS a ANIC T om lA CNN 10 YNN 10 oe T CN1010X fr me 19 Pe Pele ele elle T TE NAR 5100 User s Manual Connector Connector Function SYSTEM FAN SENSOR SYSTEM FAN CPU SYSTEM FAN 1 CPU SYSTEM FAN 2 CPU SYSTEM FAN 3 CPU SYSTEM FAN 4 IDE CNANNELO 44pin IDE CHANNEL 40pin IDE CHANNEL1 CF CARD FORNT PANEL FAN PS2 KEYBOARD MOUSE SYSTEM FAN 4 PCI COM2 USB i Reset to default LAN 10 LAN 9 LAN 8 LAN 7 LAN 6 LAN 5 LAN 4 LAN 3 LAN 2 LANH com Reset bottom PS2 KEYBOARD MOUSE ATX POWER CONNECTOR B EE En ml H T En en en en GN nl en EN nn EN a a fe a es aes En ae NAR 5100 User s Manual 11 2 14 Install a Different Processor Yh G Install CPU Lift the handling lever of CPU socket outwards and upwards to the other end 2 Align the processor pins with holes on the socket Make sure that the notched corner or dot mark pin 1 of the CPU corresponds to the socket s bevel end Then press the CPU gently until it fits into place If this operation is not easy or smooth don t do it forcibly You need to check and rebuild the CPU pin uniformly 3 Push down the lever to lock processor chip into the socket 4 Follow the installation guide of cooling fan or heat sink to mount it on CPU surface and lock it on the socket 478 5 Be sure to follow particular CPU speed and voltage type to
25. User can use the keyboard to choose among options or modify the system parameters to match the options with your system The table shown on next page will navigate through all of keystroke functions in BIOS Setup Keys to navigate within Setup menu Key Function Up Move to the previous item Down J Move to the next item Left gt Move to the item on the left menu bar Right lt Move to the item on the right menu bar Enter Enter the item you desired PgUp Increase the numeric value or make changes S Decrease the numeric value or make changes Increase the numeric value or make changes a Decrease the numeric value or make changes Main Menu Quit and not save changes into CMOS Status Page Setup Menu and Option Page Setup Menu Exit current page and return to Main Menu SE S22 eon SETUR mete Load previous values from CMOS O 5c a ae saus ron bosman FZ Load the optimized defaults EIO aa al te CMOS changes ande OO OOOO O C6 Main Menu Within NAR 5100series Award BIOS CMOS Setup utility user should start with the Main Menu The Main Menu allows to select from eleven setup functions and two exit choices Use arrow keys to switch among items and press lt Enter gt to accept or bring up the sub menu Phoenix Award BIOS CMOS Setup Utility CMOS Setup Utility NAR 5100 User s Manual 15 Standard CMOS Features Frequency Voltage Control Advanced BIOS Features Load Fail Safe Defa
26. X Bit18 1 gt Error happened or dl 04h rol edx 10h call KB Wait next_tests t3 end t4 start GPO42 Write 0 to GPI43 GPI43 0 if yes pass if no failed GPO40 Write 0 to GPI41 GPI41 0 if yes pass if no failed Output value or read status GP_LVL2 GPIOBASE 38h _bit 11 8 Output value When output pin defined Read returned status when input pin defined mov bl GP LVL2 OFFSET GPO42 Write 0 to GPI43 mov dx cx GPO40 write 0 to GPI41 add dx bx GP LVL2 Inc dx in al dx gt Read First and al OFAh i call IODELAY io delay out dx al call IODELAY io delay in al dx and al Oah Mask bit 3 1 cmp al 00h je test_end okay end of test no error message display lea dx promp_err4 mov ah 09h int 21h ror edx 10h error falg EDX Bit19 1 gt Error happened or dl 08h rol edx 10h t4 end test end ror edx 10h cmp dl 00h je test ok test fail lea dx PROMP 2 CR LF mov ah 09h int 21h lea dx promp_ TEST fail NAR 5100 User s Manual 38 mov ah 09h int 21h jmp return_to_dos test ok lea dx promp TEST OK mov ah 09h int 21h ror ecx 10h ECX 15 0 to ECX 31 16 Restore GPIOBASE to ECX 31 16 return_to dos mov ah 4ch Return to DOS Int 21h IODELAY PROC near push ax push dx mov dx 0edh in al dx jmp 2 mov dx 0edh in al dx pop dx pop ax ret IODELAY ENDP KB wait PROC near push ax push bx push cx push dx lea
27. _StrA mov ah 09h Int 21h mov edx 00000000h Error flag in EDX_BIT 16 18 O ok 1 failed PG_Step1 Enable ACPI IO port assignment and get PMBASE then save to First GPI ROUT bit 25 24 P 0 0 Let GPI6 not evoke SCI Write GPI Rout bit 25 24 to 0 0 for no effect on GPI6 BO D31 FO Offset_B8h Bit 25 24 P 0 0 no SCI event evoked Second Enabe ACPI IO port by setting ACPI CNTL bit4 BO D31 FO Offset_44h_bit4P1 Third Get PMBASE ACPI I O port BAR PMBASE B0 D31 F0 Offset 40 43h Let BitO 0 PCI BAR bit0 returns 1 for a IO BAR A 1_start Let GPI6 GPI ROUT to 0 0 i e not evoke SCI in SO mov dx 0CF8h PCI Config Read mov eax 8000F8B8h B0 D31 F0 Offset_B8h out dx eax mov dx 0CFCh in eax dx ror eax 10h l and ah OFCh bit 25 24 set to 0 0 to let GPI6 not rol eax 10h evoke SCI event out dx eax mov dx 0OCF8h PCI Config Read mov eax 8000F844h BO D31 F0 Offset_ 44h out dx eax mov dx 0CFCh in eax dx or al 10h bit 4 set to 1 to enable PMBASE out dx eax mov dx 0CF8h Get PMBASE mov eax 8000F840h BO D31 FO Offset 40h out dx eax mov dx 0CFCh in eax dx and al Ofeh bit0 cleared to 0 NAR 5100 User s Manual 22 mov PMBASE ax PG Step2 Enable GPIO IO function and get GPIOBASE How to program GPO19 Get GPIOBASE B0 D31 F0 Offset 58 5Bh and let bit0 0 GPIO_CNTL BO D31 FO Offset 5Ch bit4P1 Enable ICH4 GPIO GPIO_USE_SEL19 GPIOBASE 0 _bit19 P1
28. _fail mov ah 09h Int 21h jmp return_to_dos test ok lea dx promp_ TEST OK mov ah 09h int 21h return_to dos mov ah 4ch Return to DOS int 21h IODELAY PROC near push ax push dx mov dx 0edh in al dx jmp 2 mov dx 0edh in al dx pop dx pop ax ret IODELAY ENDP KB wait PROC near push ax push bx push cx push dx lea dx PROMP Okey mov ah 9 Display Q key prompt int 21h NAR 5100 User s Manual 27 xor al al WAIT KB mov ah 1 Int 21h cmp al 0 je WAIT_KB cmp al 51h Q pressed je test_fail cmp al 71h q pressed jne call_return jmp test fail call return lea dx PROMP 2 CR LF mov ah O9h int 21h pop dx Pop CX pop bx pop ax ret KB_wait ENDP READ GPI6 TO AL PROC near push bx push dx xor bx bx mov dx PMBASE mov bl GPEO STS OFFSET add bl 02 Point to Bit22 for GPI6 add dx bx in al dx call IODELAY io delay MUST to do write 1 to clear GPEO STS bit22 to 0 FIRST due to the access 0 1 This register is R WC and will be set at any time when GPI signal is high and al 40h mask bit6 or al 40h WC out dx al Write bit4 to 0 first call IODELAY io delay in al dx read GPI6 again pop dx pop bx ret READ GPI6 TO AL ENDP NAR 5100 User s Manual 28 l FIXED_DELAY E S Input CX count of 15 microseconds to wait STACK PRESENT l Output NONE s l CX 2 15us x 2 30 us l This routine is called to wait for 15 microseconds
29. adjust the jumper settings properly for all boards Remove CPU 1 Unlock the air funnel and heat sink first 2 Lift the lever of CPU socket outwards and upwards to the other end 3 Carefully lift up the existing CPU to remove it from the socket 4 Follow the steps of CPU installation to change to another one or place handling bar to close the opened socket Configure Processor Speed The system was designed to self detect its CPU speed So it does not require any system adjustment 2 15 Use a Client Computer Connection Using Hyper Terminal If users use a NAR 5100 series which has no mouse keyboard and VGA output connected to it the console may be used to communicate with NAR 5100 series To access NAR 5100 series via the console Hyper Terminal is one of many choices Follow the steps below for the setup Note Terminal software may need to update for correct console output 1 Execute HyperTerminal under C Program Files Accessories Hyper Terminal NAR 5100 User s Manual 12 2 Enter a name to create new dial Connection Description ST New Connection Enter a name and choose an icon for the connection Hame por leon ces 3 For the connection settings make it Direct to Com1 Connect To Ei I port Enter details for the phone number that you want to dial County code United States of America 1 Area code Phane number Connect using Direct to Cam Direct to
30. atus of corresponding key There are four keys in this module upper arrow down arrow enter ENT and escape ESC The relationship between the function key corresponding status bit and status byte is shown as the table below NAR 5100 User s Manual Function key Corresponding status bit L byte Escape The fourth bit of lower nibble the least significant bit 1110 up arrow The third bit of lower nibble 1101 Enter The second bit of lower nibble 1011 4B s Downarrow The first bit of lower nibble 0111 47 H More than one key can be pressed at the same time so that there may be more than one 0 s in the low nibble of status byte For example if Up and Down arrow keys are pressed at the same time while read key command received the replied status will be Hex045 Note 2 This command can be used to place the cursor at any location The corresponding address for each character on the screen is as follows For 16x2 Display Address Character Location Address The addresses of characters at the same row are continuous so moving cursor commands can be applied to shift the cursor position back and forth However the addresses of characters between upper and lower row are discontinuous To change cursor position between upper row and lower row this command will be applied Note 3 This command can be used to create customized icon The starting address is 64 and every character will ta
31. characters display support e Four key pads can be customized for different applications e Easy system installation and operation e Clearly display system status e Single interface to SBC or M B 2 20 2 Technical Support Information For further support users may also contact Portwell s headquarter in Taipei or your local distributors Taipei Office Phone Number 886 2 27992020 NAR 5100 User s Manual 40 2 20 3 Mechanical Specification Module Size mm 101 6 W x 26 0 H x 30 6 D max S J Display Format e 16 characters x 2 lines Character Size e 3 0 x 5 23 mm 2 20 4 General Specification General Specification Display Resolution e 16 characters x 2 lines Dimensional Outline mm e _101 6 W x 26 0 H x 30 6 D max Function Key e Four operation keys up down enter and ESC Display Icon e Eight self defined icons Interface e RS 232 Absolute Maximum Rating Normal Temperature Operating Storage Note 2 4 Note 3 5 2 20 5 Product Outlook 2 20 6 Interface Pin Assignment There are only two connectors in this module as shown in Figure C 2 1 power connector and Serial Port connector The power source into this module is 5 volt only There are only three pins used in the Serial Port interface Figure C 2 2 NAR 5100 User s Manual 41 Pin 2 TxD Pin 3 RxD Pin 5 Ground Fig C 2 1 Power connector and serial port Fig C 2 2 Pin assignment connector of EZIO 100 In other
32. d int i Search PCI Deviceo printf n nPortwell Inc 6300ESB ICH WDT TEST PROGRAM V1 00 n n printf nSearch 6300ESB ICH WDT Device Get PCI Device s Addr info regs x ax 0xb102 find PCI device regs x dx VenderlD Vender ID regs x cx DevicelD Device ID regs x si i Device index _ dpmi int Oxta amp regs if regs h ah 0 printf nWDT device is find i else printf nDevice d not find i _exit 1 get Base0 data regs x ax Oxb10a get PCI Cfg Dword regs x di 0x0010 get CR 0x10 _ dpmi int Oxla amp regs regs h cl 0 Base Addr regs d ecx if regs h ah 0 printf nPCI Base Address x Base_Add r else printf nRead PCI Cfg Reg fail _exit 1 void prepare_access_above_1mb void int j __dpmi_meminfo MemInfo Process for memory access above 1MB Map the physical device address to linear memory Memlnfo address Base Addr MemInfo size Mem _ Size MemInfo handle 1 MemInfo handle 01 __dpmi_physical_address_ mapping amp MemInfo Allocate LDT descriptor Sel lt dom allocate Idt descriptors 1 NAR 5100 User s Manual 30 Set Segment base addr amp segment limit _ dpmi set segment base address Sel Meminfo address _ dpmi set segment limit Sel Mem _ Size 1 void Show Select void elrser printf n n1 Set WDT Time out value and Enable
33. date Set the system time EGA VGA CGA Select the default video device 40CGA NAR 5100 User s Manual All Errors No Errors All but Keyboard All but Diskette All but Disk Key Display the amount of conventional memory Display the amount of extended memory Extended Memory detected during boot up Total Memory Display the total memory available in the system Select the situation in which you want the BIOS to stop the POST process and notify you lt BIOS Features Setup This section allows you to configure your system for basic operation You are able to select the system s default speed boot up sequence keyboard operation shadowing and security Screen Shot Phoenix Award BIOS CMOS Setup Utility Advanced BIOS Features CPU Feature Press Enter Hard Disk Boot Priority Press Enter Virus Warning Disable Console Redirection Enable CPU L1 amp L2 Cache Press Enter Agent connect via NULL Hyper Threading Technology Enabled _ Agent wait time min 1 Quick Power On Self Test Enabled _ Agent after boot Disabled First Boot Device USB Floppy Second Boot Device CD ROM L Third Boot Device Hard Disk ESC Quit Boot Other Device Enable Te gt Select Item Typematic Rate Setting Disabled _F1 Help Typematic Rate Chars Sec 6 Shift F2 Color Typematic Delay Msec 250 F5 Old Values Security Option Setup F6 Load BIOS Default OS Select for DRAM gt 64MB Non OS2 F7 L
34. dx PROMP Okey mov ah 9 Display Q key prompt int 21h xor al al WAIT KB mov ah 1 Int 21h cmp al 0 je WAIT_KB cmp al 51h Q pressed je test_fail cmp al 71h q pressed jne call_ return jmp test fail call return pop dx Pop CX pop bx pop ax ret NAR 5100 User s Manual 39 KB wait ENDP END programstart 2 20 About EZIO 100 Proprietary keypad and LCD display interfaces are implemented in traditional computing system design but they are usually different from system to system The main purpose to roll this module out is to provide an easier human machine interface for those computing systems regarding application friendly operation as a must The design goals of this interface are A single interface for those applications where both LCD display and keypad are required e This interface should be available in every computing system The communication implementation should be OS independent Our solution is to use Serial port as the interface for both LCD display and keypad A simple protocol is further defined so that applications can directly communicate with this module no matter what the Operating System is WARNING THE LCD DRIVER ICS ARE MADE OF CMOS PROCESS DAMAGED BY STATIC CHARGE VERY EASILY MAKE SURE THE USER IS GROUNDED WHEN HANDLING THE LCD 2 20 1 Features e Ideal user interface for communication appliance e No driver required OS independent e Alphanumeric
35. e GPO GPI pin mov dx cx GPIOBASE add dx bx GP IO SEL Inc dx in al dx Read First and al 0FOh GPO43 41 GPI42 40 or al 05h out dx al t1 start GPO43 Write 1 to GPI42 GPI42 1 if yes pass if no failed GPO41 Write 1 to GPI40 GPI40 1 if yes pass if no failed Output value or read status GP_LVL2 GPIOBASE 38h _bit 3 0 Output value When output pin defined Read returned status when input pin defined NAR 5100 User s Manual 35 mov bl GP LVL OFFSET GPO43 Write 1 to GPI42 mov dx cx gt GPO41 write 1 to GPI40 add dx bx GP LVL2 inc dx in al dx Read First or al 0Ah out dx al call IODELAY io delay in al dx and al 05h Mask bit2 0 GPI42 40 cmp al 05h je next_test1 okay go on test no error message display lea dx promp_err1 mov ah 09h int 21h ror edx 10h_ error falg EDX_Bit16 1 gt Error happened or dl Oih rol edx 10h call KB Wait next_test1 t1 end t2 start GPO43 Write 0 to GPI42 GPI42 0 if yes pass if no failed GPO41 Write 0 to GPI40 GPI40 0 if yes pass if no failed Output value or read status GP_LVL2 GPIOBASE 38h _bit 11 8 Output value When output pin defined Read returned status when input pin defined mov bI GP_LVL2 OFFSET GPO43 Write 0 to GPI42 mov dx cx gt GPO41 write 0 to GPI40 add dx bx GP_LVL2 inc dx in al dx gt Read First and al OF5h E call IODELAY io delay
36. em AI ele entente E T lacs 51 NAR 5100 User s Manual Chapter 1 Introduction 1 1 About This Manual This manual contains all required information for setting up and using the NAR 5100 series NAR 5100 is an Intel Pentium 4 based system with the Cavium NITROX IPSec SSL processor onboard The embedded Cavium s NITROX Lite CN1010X processor features cost benefit and flexibility by supporting IPSec SSL processing NAR 5100 provides the essential platform for delivering optimal performance and functionality in the value communications appliance market segment This manual should familiarize you with NAR 5100 series operations and functions NAR 5100 series has up to ten on board Ethernet ports to serve communication appliances like Firewall requiring Ethernet ports to connect external network internet demilitarized zone and internal network Feature of NAR 5100 series includes One On board Cavium Nitrox CN1010X Security Processor Versatile networking and I O capabilities 10 Ethernet ports Dual 64bit 133MHz Gigabits Ethernet Intel 82546 EB Up to 4GB 266 333 400MHz DDR on 4 x 184 pin DIMM sockets with ECC Unregistered One on board IDE channel to support one removable 2 5 HDD User friendly LCD control panel AA A AAA 1 2 Manual Organization This manual describes how to configure your NAR 5100 series system to meet various operating requirements It is divided into three chapters with each chapter addressing the ba
37. is guide is for technically qualified personnel who have experience installing and configuring system boards Disconnect the system board power supply from its power source before you connect disconnect cables or install remove any system board components Failure to do this can result in personnel injury or equipment damage 3 Avoid short circuiting the lithium battery this can cause it to superheat and cause burns if touched 4 Do not operate the processor without a thermal solution Damage to the processor can occur in seconds 5 Do not block air vents Minimum 1 2 inch clearance required NAR 5100 User s Manual 4 2 3 The Chassis The system is integrated in a customized 1U chassis Fig 2 1 Fig 2 2 On the front panel you will find a 4 push button LCD module EZIO totally ten LAN ports and a COM port NAR 5100 Fig 2 1 Front view of the chassis Fig 2 2 Rear view of the chassis 2 4 Open the Chassis 1 Loosen the four screws of the chassis two on each side and the rest two on the back to remove the top lead Fig 2 3 Fig 2 3 Take off screws 2 The top lead Fig 2 4 can be removed from the base stand Fig 2 5 NAR 5100 User s Manual 5 Fig 2 4 The top lead Fig 2 5 The base stand 2 5 Remove and Install DIMM Follow these steps to upgrade RAM module 1 Install the system memory by pulling the sockets arm and pressing it into the slot gently Fig 2 6 2 7 nnn
38. ke 8 bytes to create a 5 W x 7 H resolution picture as shown below CG RAM MAPPING Character Patterns 6G RAM data High w High 0 0 0 0 0 1 E ae Character Dd tk Pattern 1 0 U 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 oe Character 0 1 1 ka de 10 0 Pattern 1 0 1 1 1 0 1 1 1 lt Cursor 1 11 0 0 0 gt amp 0 0 1 E lt Character 0 1 1 4 0 0 Pattern 1 0 1 od 1 0 NAR 5100 User s Manual To show the customized icon simply send the data between 0 to 7 to this module For example this module will display the customized icon at location 64 to 71 upon receiving data 0 white it will display the customized icon at location 72 to 79 upon receiving data 1 Watchdog timer is also built in the module This module will reset itself and send out reset packet OFDH OEH thereafter The input must be a standard RS 232 or inverted TTL signal The RS 232 setting should be Baud rate 2400 bps Parity None Data bits 8 Stop bit 1 Z What follows is the default setup after LCD module initiated 2 line display mode every character is 5 x 8 dots Display on cursor off cursor blink off Display will be cleared Shift right for entry mode Set address counter to OO cursor position to 0 In entry mode 2 20 9 Character Generator ROM CGROM NAR 5100 User s Manual 45 CG 0010
39. oad Setup Default Small Logo EPA Show Disable _ PU PD Modify Console Redirection Set the UNIX Console redirect to the terminal from COM1 The choice Enabled Disabled C Baud Rate NAR 5100 User s Manual p R R amp set the RS 232 baud rate speed The choice 9600 19200 38400 57600 and 115200 Cache Setup CPU L1 amp L2 Cache Enabled or Disabled CPU L1 and L2 cache Enabled Enable cache Disabled Disable cache CPU L2 Cache ECC Checking Enabled or Disabled CPU L2 cache ECC checking Enabled Enable checking Disabled Disable checking Virus Warning Allows you to choose the VIRUS warning feature for IDE Hard Disk boot sector protection Enabled Disabled Enable VIRUS warning Disabled VIRUS warning Hyper Threading Technology For WindowsXP and Linux 2 4 x OS optimized for Hyper Threading Technology Enabled Disabled Enable Hyper Threading Technology Disabled Hyper Threading Technology Quick Power On Self Test This category speeds up Power On Self Test POST after you power up the computer If it is set to Enable BIOS will shorten or skip some check items during POST Enabled Disabled Enable quick POST Normal POST e Boot Up NumLock Status Select power on state for NumLock NAR 5100 User s Manual The choice Enabled Disabled _Typematic Rate Setting Keystrokes repeat at a rate determined by the keyboard controller When enabled the
40. rt correctly please check the previous steps 2 16 BIOS Setup Information NAR 5100 series is equipped with the Award BIOS within Flash ROM The BIOS has a built in setup program that allows users to modify the basic system configuration easily This type of information is stored in CMOS RAM so that it still retains during power off periods When system is turned on NAR 5100 series communicates with peripheral devices and checks its hardware resources against the configuration information stored in the CMOS memory Whenever an error is detected or the CMOS parameters need to be initially defined the diagnostic program will prompt the user to enter the Setup program Some errors are significant enough to abort the start up NAR 5100 User s Manual 14 C6 Entering Setup When message Hit lt DEL gt if you want to run Setup appear during POST after turning on or rebooting the computer press lt Del gt key immediately to enter BIOS setup program To enter Setup but fail to respond before the message disappears please restart the system either by first turning it off and followed by turning it on COLD START or simply press the RESET button WARM START press lt Ctrl gt lt Alt gt and lt Delete gt keys simultaneously will do as well When no setting is stored in BIOS or the setting is missing a message Press lt F1 gt to run Setup will appear Then press lt F1 gt to run Setup or resume HIFLEX BIOS Setup
41. settings should be done 2 1 Included Hardware The following hardware is included in package e PPAP 3714L Communication Appliance System Board e One null serial port cable 2 2 Before You Begin To prevent damage to any system board it is important to handle it with care The following measures are generally sufficient to protect your equipment from static electricity discharge When handling the board use a grounded wrist strap designed for static discharge elimination and touch a grounded metal object before removing the board from the antistatic bag Handle the board by its edges only do not touch its components peripheral chips memory modules or gold contacts When handling processor chips or memory modules avoid touching their pins or gold edge fingers Restore the communications appliance system board and peripherals back into the antistatic bag when they are not in use or not installed in the chassis some circuitry on the system board can continue operating even though the power is switched off Under no circumstances should the Lithium battery cell used to power the real time clock be allowed to be shorted The battery cell may heat up under these conditions and present a burn hazard WARNING CAUTION DANGER OF EXPLOSION IF BATTERY IS INCORRECTLY REPLACED REPLACE ONLY WITH SAME OR EQUIVALENT TYPE RECOMMENDED BY THE MANUFACTURER DISCARD USED BATTERIES ACCORDING TO THE MANUFACTURER S INSTRUCTIONS 2 Th
42. sic concept and operation of this system Chapter 1 Introduction This section describes how this document is organized It includes brief guidelines and overview to help find necessary information Chapter 2 Hardware Configuration Setting and Installation This chapter demonstrated the hardware assembly procedure including detailed information It shows the definitions and locations of Jumpers and Connectors that can be used to configure the system Descriptions on how to properly mount the CPU and main memory are also included to help perform a safe installation This chapter will provide detailed instruction on how to set up NAR 5100 series Chapter 3 Operation Information This section provides illustrations and information on the system architecture and how to optimize its performance Any updates to this manual technical clarification and answers to frequently asked questions would be posted on the web site http isc portwell com tw 1 3 Technical Support Information Users may find helpful tips or related information on Portwell s web site http www portwell com tw A direct contact to Portwell s technical person is also available For further support users may NAR 5100 User s Manual 2 also contact Portwell s headquarter in Taipei or local distributors Taipei Office Phone Number 886 2 27992020 NAR 5100 User s Manual 3 Chapter2 Getting Started This section describes how the hardware installation and system
43. te fd amp init 1 int home 2 Home cursor void Home write fd amp Cmd 1 write fd amp home 1 int readkey 6 Read key void ReadKey write fd amp Cmd 1 write fd amp readkey 1 int blank 8 Blank display void Blank write fd amp Cmd 1 write fd amp blank 1 int hide lt 12 Hide cursor amp display blanked characters void Hide write fd amp Cmd 1 write fd amp hide 1 int turn 13 Turn On blinking block cursor void TurnOn write fd amp Cmd 1 write fd amp turn 1 intshow 14 Show underline cursor void Show write fd amp Cmd 1 write fd amp show 1 NAR 5100 User s Manual 48 int movel 16 Move cursor 1 character left void MoveL write fd amp Cmd 1 write fd amp movel 1 int mover 20 Move cursor 1 character right void MoveR write fd amp Cmd 1 write fd amp mover 1 int scl 24 Scroll cursor 1 character left void ScrollL write fd amp Cmd 1 write fd amp scl 1 int scr 28 Scroll cursor 1 character right void ScrollR write fd amp Cmd 1 write fd amp scr 1 int setdis 64 Command void SetDis write fd amp Cmd 1 write fd amp setdis 1 Add or Change Show Message here char mes1 Portwell EZIO char mes2 erraren char mes3 Up is selected
44. the BIOS update easier The high precision Real Time Clock Calendar is built to support Y2K for accurate scheduling and storing configuration information All of these features make PPAP 3714L excellent in stand alone applications lf any of these items is damaged or missing please contact your vendor and save all packing materials for future replacement and maintenance TR a ARIE T l Fares 2 A pa OF Sie en a Y f ya T T gk T 2 BL oN L L r i Ke L L D R eit add v J l Z K CH CRK noe O Gals ES maa P LE IT f No y ah ZT 822 8 TT RON AOE MAN MY Sadi Ey ETRO en E rar on on ennn EW Gie D A M E U CA RE ra on ga pen a P Kd T r z 4 aie gan ms un R RUH 64 er es BEE Mo Men E a t Ap s lt aot 4 K K at a ae 4 Bes gt A RAR Bk PT A T ep j 9 aB a e Se re T Ga T r P dp er 7 2 s ZP Fa r ER c F Z A i Miz H ZE pa Ee a 4 rd at ts Aa al L Tr ae aoe 9 Krr 4 in x L han H 00H NRT Figure 3 1 PPAP 3714L Board 3 2 System Architecture The following illustration of block diagram illustrated basic design reference of PPAP 3714L a highly integrated system solution The most up to date system architecture of PPAP 3714L includes two main chips It contains and to support mPGA2 Pentium 4 processor DIMM PCI bus interface USB port SMBus communication and Ultra DMA 100 IDE Master PPAP 3714L has built
45. to define GPIO19 as GPIO function GP_BLINK19 GPIOBASE 18h _bit19 P0 to let GPIO19 function normally No Blink GPO19 GB LVL GPIOBASE OCh _bit1 9P 0 1 Write value 0 1 GPIO USE SEL6 bit must be set to 1 to make sure GPI6 as a GPIO function First GPI6 status must NOT be inverted then GPI_INV GPIOBASE 2Ch bit6P0 GPI6 not inverted Get GPI6 status from GPEO_STS PMBASE 28h bit22 O low 1 high level mov dx 0CF8h mov eax 8000F85Ch BO D31 F0 Offset_5Ch out dx eax mov dx 0OCFCh in eax dx or al 10h 5Ch Bit4P1 to Enable GPIO out dx eax mov dx 0CF8h Get GPIOBASE mov eax 8000F858h BO D31 FO Offset 58h out dx eax mov dx 0OCFCh in eax dx and al Ofeh bit O cleared to 0 mov GPIOBASE ax xor ax ax mov dx GPIOBASE mov al GPIO USE SEL OFFSET add dx ax in al dx or al 40h GPIO USE SEL6P1 out dx al xor ax ax mov dx GPIOBASE NAR 5100 User s Manual 23 mov al GPIO USE SEL OFFSET add dx ax add dx 2 Point to Bit 16 23 in al dx or al 08h Bitl9P1 GPIO USE SEL19P1 out dx al GPIO19 MUST be set as GPIO function xor ax ax mov dx GPIOBASE mov al GP_BLINK OFFSET add dx ax add dx 2 Point to Bit 16 23 in al dx and al OF h Bit19PO out dx al GPIO19 MUST be set as NO Blinking Write 0 Testing way t1 Read GPI6 first GPI6 0 if yes pass if no failed 2 RST2DF button pressed and released read GPI6 GPI6 1 if yes pass if no
46. to high 1 RST2DF register can be cleared by ESB6300 GPO19 Write a pulse timing Hight_low_high2 to clear RST2DF to 0 High1 output GPO19 high and keep 30 us Low output GPO19 low and keep 30 us High2 output GPO19 high again and keep high always Programming Guide PG_Step1 Enable ACPI IO port assignment and get PMBASE First GPI ROUT bit 25 24 P 0 0 Let GPI6 not evoke SCI Write GPI_ Rout bit 13 12 to 0 0 for no effect on GPI6 BO D31 FO Offset_B8h Bit 25 24 P 0 0 no SCI event evoked l Second Enabe ACPI IO port by setting ACPI CNTL bit4 l B0 D31 F0 Offset_44h_bit4P1 Third Get PMBASE ACPI I O port BAR PMBASE B0 D31 F0 Offset 40 43h S Let BitO 0 PCL_BAR bit0 returns 1 for a IO BAR PG Step2 Enable GPIO IO function and get GPIOBASE How to program GPIO19 Output only i e GPO19 Get GPIOBASE B0 D31 F0 Offset 58 5Bh and let bit0 0 GPIO_CNTL B0 D31 FO Offset 5Ch bit4P1 Enable GPIO GPIO_USE_SEL19 GPIOBASE 0 _bit19 P1 to define GPIO19 as GPIO function GP_BLINK19 GPIOBASE 18h _bit19 P0 to let GPIO19 function normally No Blink GPIO19 GP LVL GPIOBASE OCh bit19P 0 1 Write value 0 1 GPIO USE SEL6 GPIOBASE 0 bit6 P1 to define GPI6 as GPIO function GPI6 status MUST NOT be inverted First GPI INV GPIOBASE 2Ch bit6P0 GPI6 not inverted Get GPI6 status from GPEO STS PMBASE 28h bit22 O low 1 high level MODEL small 3
47. typematic rate and typematic delay can be selected The choice Enabled Disabled ow Typematic Rate Chars Sec set the how many number of times a second to repeat a keystroke when you hold the key down The choice 6 8 10 12 15 20 24 and 30 Ym Typematic Delay Msec set the delay time after the key is held down before it begins to repeat the keystroke The choice 250 500 750 and 1000 Security Option select whether the password is required every time the system boots or only when entering setup System The system will not boot and access to Setup will be denied if the correct y password is not entered at the prompt The system will boot and access to Setup will be denied if the correct password is not entered at the prompt g OS Select for DRAM gt 64MB Select the operating system that is running with more than 64MB of RAM on the system The choice Non OS2 OS2 NAR 5100 User s Manual 19 2 17 Reset to Default Information For PPAP 3714 RESET to Default testing By Frank Hsu 11 08 2004 Reset to default status can be read from ESB6300 GPI6 IF BIOS does not init GPIO USE SEL6 does not set to 1 then the initial level on GPI6 signal may be 0 8 0 98V This Signal level is no good for logical high or low Therefore this program will init GPIO USE SEL6 to 1 After Power On reset GPI6 low 0 If Reset to Default RST2DF Button pressed Triggered then GPI6 will be latch
48. ults Advanced Chipset Features Load Optimized Defaults Integrated Peripherals Set Supervisor Password Power Management Setup Set User Password PnP PCI Configurations Save amp Exit Setup PC Health Status Exit Without Saving ESC Quit TY amp gt Select Item F10 Save amp Exit Setup Shift F2 Change Color Time Date Hard Disk Type NOTE It is strongly recommended to reload the optimized default setting if CMOS is lost or BIOS is updated em Standard CMOS Setup Menu This setup page includes all the items within standard compatible BIOS Use the arrow keys to highlight the item and then use the lt PgUp gt lt PgDn gt or lt gt lt gt keys to select the value or number you want in each item and press lt Enter gt to certify it Follow command keys in CMOS Setup table to change Date Time Drive type and Boot Sector Virus Protection Status Screen Shot Phoenix Award BIOS CMOS Setup Utility Standard CMOS Setup Utility Date Wed Jan 17 2004 Time 16 51 13 IDE Primary Master None IDE Primary Slave None IDE Secondary Master None IDE Secondary Slave None Video EGA VGA Halt On All but Keyboard Base Memory 640K Extended Memory 512MB Total Memory 512MB ESC Quit TY lt gt Select Item F1 Help Shift F2 Change Color PU PD Modify Menu Selections Options i Description pan Set the system date Note that the Day RI automatically changes when you set the
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