MC9S12XEPB, MC9S12XE Family Product Brief
Contents
1. Freescale Semiconductor Product Brief Document Number MC9S12XEPB Rev 9 4 2015 MC9S12XE Family Product Brief 16 Bit Microcontroller Family with Enhanced System Integrity Features 1 Introduction The new MC9S12XE Family of microcontrollers takes the innovation of today s MC9S12XD Family a step further with the introduction of new features to deliver enhanced system integrity and greater functionality These new features include a Memory Protection Unit MPU and Error Correction Code ECC on the Flash memory together with enhanced EEPROM functionality EEE an enhanced XGATE a Frequency Modulated Phase Locked Loop IPLL and a faster ATD The E Family will extend the S12X product range up to 1MB of Flash memory with increased I O capability in the 208 pin version of the flagship MC9S12XEP100 Targeted at automotive multiplexing and generic auto body applications S12XE Family will deliver 32 bit performance with all the advantages and efficiencies of a 16 bit MCU It will retain the low cost power consumption EMC and code size efficiency advantages currently enjoyed by users of Freescale s existing 16 bit S12 and S12X MCU families There is a high level of compatibility between the 12XE and S12XD families Like members of other S12X families the S12XE Family will run 16 bit wide accesses without wait states for all peripherals and memories The S12XE Family features an enhanced version of the performance boosti2. Freescale reserves the right to make changes without further notice to any products herein Freescale makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursuant to standard terms and conditions of sale which can be found at the following address freescale com SalesTermsandConditions Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off All other product or service names are the property of their respective owners 2015 Freescale Semiconductor Inc Document Number MC9S12XEPB Revision 9 4 2015 e Po oe freescale
3. LIN 2 0 Master and Slave Drivers ProOSEK for S12X Volcano LIN Drivers For S12 available and compatible for S12X 5 Document Revision History Table 3 shows the revision history of this document Table 3 Revision History Rev 2 Replaced high level block diagram with detailed block diagram Added Table 1 Added Table 2 Rev 3 Replaced future tense with present tense Corrected corrupted footnote font in Table 1 Added dataflash column to Table 2 Changed CPU compatibility text following removal of fuzzy instructions Table continues on the next page MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc 13 Document Revision History Table 3 Revision History continued Rev 4 Merged device family option tables Rev 5 Added package mechanical information Rev 6 Changed D Flash size for S12XEG128 Rev 7 Corrected SCI IIC PIT counts in derivative table Rev 8 Table 1 updated TIM listing added 80QFP options MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc How to Reach Us Home Page freescale com Web Support freescale com support Information in this document is provided solely to enable system and software implementers to use Freescale products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document
4. MC9S12XE Family Product Brief Rev 9 4 2015 10 Freescale Semiconductor Inc Features 3 5 18 Serial Peripheral Interface SPI e Up to three SPI modules e Configurable 8 or 16 bit data size e Full duplex or single wire bidirectional e Double buffered transmit and receive Master or Slave mode e MSB first or LSB first shifting Serial clock phase and polarity options 3 5 19 Serial Communication Interfaces SCI e Up to eight SCI modules e Full duplex or single wire operation e Standard mark space non return to zero NRZ format Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse widths e 13 bit baud rate selection e Programmable character length e Programmable polarity for transmitter and receiver e Receive wake up on active edge e Break detect and transmit collision detect supporting LIN 3 5 20 Inter IC Module IIC Up to two IIC modules e Compatible with Inter IC Bus standard e Multi master operation e Software programmable for one of 256 different serial clock frequencies e Broadcast mode support e 10 bit address support 3 5 21 Background Debug BDM e Background debug module BDM with single wire interface e Non intrusive memory access commands e Supports in circuit programming of on chip non volatile memory e Supports security 3 5 22 Debugger xDBG e Four comparators A B C and D e Each can monitor CPU or XGATE buses e A and C compares 23 bit address bus and 16 bit
5. data bus with mask register e B and D compares 23 bit address bus only e Three comparator modes exact address match inside address range or outside address range MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc 11 Developer Environment e 64 x 64 bit circular trace buffer to capture change of flow addresses or address and data of every access e Tag type or force type hardware breakpoint requests 3 5 23 On Chip Voltage Regulator VREG e Two parallel linear voltage regulators with bandgap reference e Low voltage detect LVD with low voltage interrupt LVI e Power on reset POR circuit e 3V and 5V range operation e Low voltage reset LVR 3 5 24 Input Output e Up to 152 general purpose input output I O pins and 2 input only pins e Hysteresis and configurable pull up pull down device on all input pins e Configurable drive strength on all output pins 4 Developer Environment The S12XE Family of MCUs supports similar tools and third party developers as other Freescale S12X products offering a widespread established network of tools and software vendors Available support includes 12X Evaluation Board e Full standardized header ring for all pins except Oscillator and PLL e 6 LIN Interfaces 2 RS232 2 Interfaces e 3 CAN Interfaces e Power Supply Connector e Prototyping area es USB BDM and USB2BDM interface e Daughter boards with 144 112 and 80 pin devices e Canned Oscillator e Pierc
6. packages only e Each chip select output can be configured to complete transaction on either the time out of one of the two wait state generators or the deassertion of EWAIT signal e Supports glue less interface to popular asynchronous RAMs and Flash devices 3 5 10 Analog to Digital Converter ATD e Up to two independent ATD converters e 8 10 12 bit resolution e Multiplexer for 16 analog input channels e 3 s 10 bit single conversion time e Left right signed unsigned result data e External and internal conversion trigger capability e Internal oscillator for conversion in Stop modes e Wake up from low power modes on analog comparison gt or lt match 3 5 11 Enhanced Capture Timer ECT e 8 x 16 bit channels for input capture or output compare e 16 bit free running counter with 8 bit precision prescaler e 16 bit modulus down counter with 8 bit precision prescaler e Four 8 bit or two 16 bit pulse accumulators e Four channels have enhanced input capture capabilities e Delay counter for noise immunity e 16 bit capture buffer e 8 bit pulse accumulator buffer 3 5 12 Timer TIM e 8 x 16 bit channels for input capture or output compare e 16 bit free running counter with 8 bit precision prescaler e One 16 bit pulse accumulator MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc 9 Features 3 5 13 Periodic Interrupt Timer PIT e Up to 8 timers with independent time out periods e Time out p
7. 8ch 8ch 152 1M 64K 9S12XEP 208 2 32 4K 32K 100 MAPBGA 144LQFP 5 8 3 2 8ch 8ch ch 2 24 119 112LQFP 5 8 3 1 8ch 8ch 8ch 246 91 80QFP 4 2 3 1 8ch 8ch 8ch 1 8 59 9S12XEP 208 5 8 3 2 sch 8ch sch 2 32 152 768K 48K 768 MAPBGA 144LQFP 5 8 3 2 8ch 8ch ch 2 24 119 112LQFP 5 8 3 1 8ch 8ch sch 2 16 91 80QFP 4 2 3 1 8ch 8ch 8ch 1 8 59 9S12XEQ 144LQFP 4 6 3 2 sch o 4ch 2 24 119 512K 32K 512 112LQFP 4 6 3 1 8h o 4ch 146 91 80QFP 4 2 3 1 8ch o 4ch 1 8 59 9S12XEQ 144LQFP 4 6 3 2 sch o 4ch 2 24 119 384K 24K 281 112LQFP 4 6 3 1 sch o 4ch 246 oa 80QFP 4 2 3 1 shn o 4ch 1 8 59 9S12XET 144LQFP 3 4 3 1 8ch o 4ch 2 24 119 256K 16K 256 112LQFP 3 4 3 1 8h 0 4ch 216 a 80QFP 3 2 3 1 8ch o 4ch 1 8 59 9S12XEG 112LQFP Yes 2 2 2 1 8h o 2ch 216 91 128K 12K 2k 32K 128 s0QFP 2 2 2 1 8h o 2ch 18 59 1 CAN Options Versions with 5 CAN modules will have CANO CAN1 CAN2 CAN3 and CAN4 Versions with 4 CAN modules will have CANO CAN1 CAN2 and CAN4 Versions with 3 CAN modules will have CANO CAN1 and CAN4 Versions with 2 CAN modules will have CANO and CAN4 Versions with 1 CAN module will have CANO SCI Option
8. Analog Digital Converter 8 10 12 bit 16 channel ANI15 0 PAD 31 16 Analog Digital Converter 16 bit 8 channel lOC 7 0 PT 7 0 Enhanced Capture Timer TIM 16 bit 8 channel IOC 7 0 PR 7 0 Timer PWM 8 bit 8 channel PWM 7 0 gt o gt PPIZ 0 Pulse Width Modulator W aa Asmehronous Senile Gel Ee Asynchronous Serial IF TXD Sg PS1 SCH RXD EI PS2 Asynchronous Serial IF TXD D PS3 MISO pa E PS4 MOSI pa PS5 SCK lt PS6 Synchronous Serial IF ss GC PS7 we ki eat GI PH2 PH3 MISO pa PH4 MOSI WW PH5 SCK a gt E j gt PH6 Synchronous Serial IF ss wal D PH7 mecanzoe eat Es msCAN 2 0B TXCAN gt PM1 mecanz08 Tean gt er pms msCAN 2 0B TXCAN Sg PM3 mecanz0n Sean fe gt aeus msCAN 2 0B TXCAN pa PM5 Sien Selz kran msCAN 2 0B TXCAN Sei PM7 Genen boa Asynchronous Serial IF TXD PL1 Asynchronous Serial at Eclat Asynchronous Serial IF Te gt PL3 Pedii gar Gaz heri Asynchronous Serial IF TXD Se PL5 Asynchronous saat ac E Asynchronous Serial IF TXD GC PL7 SCH RXD fe fee Po Asynchronous Serial IF TXD PJ1 2 PJ2 H PJ3 ICH PJ4 Inter IC Module PJ5 CAN4 2 PJ6 msCAN 2 0B D PJ7 Figure 3 MC9S12XE Block Diagram MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc Features 3 2 Peripheral and Memory Options 12XE Family Table 1 Peripheral and Memory Options of S12XE Family Members Package XGA CANT SCI IIC ECT TIM PIT A D 1 07 8 TE Yes 5 8 3 2 8ch
9. I O ports are available with interrupt capability allowing wake up from STOP orWAIT mode The S12XE Family is available in 208 Pin MAPBGA 144 pin LQFP both with optional external bus 112 pin LQFP or 80 Pin QFP options 2 Application Examples The following sections describe target applications of the MC9S12XE 2 1 Body Controller Application Example In this example the MC9S12XE is implementing the features of a typical car body controller application The module interfaces with the main CAN buses distributed in the car using the on chip MSCAN module whereas the LIN bus communicates with functions local to the body controller In both cases the communication functions are managed by the XGATE independently of the CPU The MC9S12XE provides direct control of power drivers for lights and pumps and reading of sensors using the on chip PWM and ATD modules Finally the SPI interface to the RF receiver provides the interface to the car remote access system LS CAN Body CAN P I CAN P I HS CAN Diagnostic CAN P I LIN P I HS CAN Powertrain LIN P I Figure 1 Body Controller Application Example MC9S12XE Family Product Brief Rev 9 4 2015 2 Freescale Semiconductor Inc 2 2 Gateway Application Example Features In this application the MC9S12XE provides gateway functionality between its on chip CAN and LIN modules Much of the low level communications functionality is handled by the XGATE which frees th
10. ameters The following describes the critical operating parameters of the MCU 3 3 1 Operating Conditions e Wide single supply voltage range 3 3V 5 10 to 5 0V 10 at full performance e Separate supply for internal voltage regulator and I O allow optimized EMC filtering e 50MHz maximum CPU bus frequency e 100MHz maximum XGATE bus frequency e Ambient temperature range 40 C to 125 C e Temperature Options e 40 C to 85 C e 40 C to 105 C e 40 C to 125 C 3 3 2 Package Options e 208 pin MAPBGA 17mm x 17mm body size case no 1159A 01 issueB e 144 pin low profile quad flat pack LQFP 20x20mm body size 0 5mm pitch case no 918 03 e 112 pin low profile quad flat pack LQFP 20x20mm 0 65 pitch case no 987 e 80 pin quad flat pack QFP 14x14mm body 0 65mm pitch case no 841B 3 4 Chip Level Features On chip modules include the following features e Pin compatible family extends existing S12D Family e 16 bit CPU12X e Enables higher system integrity at the MCU level MPU ECC Supervisor Mode e Enhanced SPI allows 8 or 16 bit data size e ECC on flash MC9S12XE Family Product Brief Rev 9 4 2015 6 Freescale Semiconductor Inc Features e 1 bit fault correction e 2 bit fault detection e Improved EMC performance e Separate supply for internal voltage regulator and I O allow optimized EMC filtering e Enhanced current consumption e Extended API up to 5 sec 3 5 Module Features The following s
11. e CPU to manage higher level communications and other direct connections to the module LS CAN Body CAN P I Digital Inputs HS CAN Telematics Digital Outputs PWM or not SCI LIN LIN P I SCI LIN CAN P I LIN PI Frontighting S CAN PII HS LS CAN Chassis HS CAN Powertrain HS CAN Diagnostic _ mee LIN LIN Figure 2 Gateway Application Example 3 Features Features of the S12XE Family are described in this section 3 1 Block Diagram Figure 3 shows a top level block diagram of the S12XE Family MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc Features PEO MPU PE1 Memory Protection PE2 8 regions 128K 1M bytes Flash 12K 64K bytes RAM 2K 4K bytes EEPROM Voltage Regulator CPU12X Debug Module Single wire Background 4 address breakpoints Debug Module 2 data breakpoints 512 Byte Trace Buffer COP Watchdog Periodic Interrupt Async Periodic Int PIT 8ch 16 bit Timer Enhanced Multilevel Interrupt Module Amplitude Controlled Low Power Pierce or Full drive Pierce Oscillator PES MODA TAGLO RE PE6 MODB TAGHI PE7 XCLKS ECLKX2 PB 7 0 PC 7 0 EWAIT ADDR 22 16 ADDR 15 8 ADDRI7 0 DATAI15 8 Non Multiplexed External Bus Interface S Ol S 2 CS3 SCL Inter IC Module TXD Asynchronous Serial IF XGATE X ATDO 8 10 12 bit 16 channel AND DT PAD 15 0
12. e Oscillator provision e Reverse polarity protection e Configuration jumpers mode pins clock source vreg e 0 Ohm resistor going from test to ground e Ground points e Kit includes e USB cable e CodeWarrior CD e 9S12XDP512 Service Pack CD e EVB9S12X Evaluation Board User Manual e SofTec System Software CD e Status Available Now MC9S12 Code Warrior Development System gt S12X Service Pack contains e CodeWarrior for OSEK e Sophisticated project manager e Build system with optimizing C C compiler e Graphical source level debugger MC9S12XE Family Product Brief Rev 9 4 2015 12 Freescale Semiconductor Inc Document Revision History e Fast cycle accurate simulator e Code coverage and profile analysis e Flash programmer e Evaluation Kit for MC9S12DT256 e Evaluation board e BDI interface e Power supplies and cables e Metrowerks OSEK Real Time Operating System demo e Documentation package Table 2 Tools Suppliers Name Toot IDE Compiler Debugger Simulator Emulator BDM Conn Software CodeWarrior xX xX X Cosmic Software X Xx X IAR Systems X X X Hardware P amp E Microcomputer X Systems Inc iSystem X X X X Nohau X X Lauterbach X X xX Drivers Vector e LIN 1 3 Master Driver S12X LIN 2 0 Master Driver S12X including XGATE e CAN Driver S12X including XGATE This includes COM and NM for specific OEM configuration 3Soft I O HIS Drivers
13. ections provide more details of the modules implemented on the MC9S12XE 3 5 1 16 Bit CPU12X e 16 bit CPU12X e Compatible with MC9S12 instruction set with the exception of five fuzzy instructions MEM WAV WAVR REV REVW which have been removed e Enhanced indexed addressing e Access to large data segments independent of PPAGE 3 5 2 Enhanced Interrupt Module e Eight levels of nested interrupts e Flexible assignment of interrupt sources to each interrupt level e External non maskable high priority interrupt XIRQ e Internal non maskable high priority memory protection unit interrupt e Up to 24 pins on ports J H and P configurable as rising or falling edge sensitive 3 5 3 XGATE e Programmable high performance I O coprocessor module with up to 100 MIPS RISC performance Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states Performs logical shifts arithmetic and bit operations on data e Can interrupt the S12X CPU signalling transfer completion Triggers from any hardware module as well as from the CPU possible e Two interrupt levels to service high priority tasks Enables Full CAN capability when used in conjunction with MSCAN module e Full LIN master or slave capability when used in conjunction with the integrated LIN SCI modules 3 5 4 Memory Protection Unit MPU e 8 address regions definable per active program task e Address range granularity as low as 8 bytes e Protection Attr
14. eriods selectable between and 224 bus clock cycles e Time out interrupt and peripheral triggers 3 5 14 Real Time Interrupt RTI e Real time interrupt for task scheduling purposes or cyclic wake up e Can be active in Pseudo Stop mode for low power precision timing tasks 3 5 15 Asynchronous Periodic Interrupt API e Available in all modes including Full Stop mode e Trimmable to 10 accuracy e Time out periods range from 0 2ms to 13s with a 0 2ms resolution 3 5 16 Pulse Width Modulator PWM e 8 channel x 8 bit or 4 channel x 16 bit Pulse Width Modulator e Programmable period and duty cycle per channel e Center or left aligned outputs e Programmable clock select logic with a wide range of frequencies e Fast emergency shutdown input 3 5 17 Multi scalable Controller Area Networks MSCAN e Up to five MSCAN modules e CAN 2 0 A B software compatible e Standard and extended data frames e 0 8 bytes data length e Programmable bit rate up to 1 Mbps e Five receive buffers with FIFO storage scheme e Three transmit buffers with internal prioritization Flexible identifier acceptance filter programmable as e 2x 32 bit e 4x 16 bit e 8x 8 bit e Wake up with integrated low pass filter option Loop back for self test e Listen only mode to monitor CAN bus e Bus off recovery by software intervention or automatically e 16 bit time stamp of transmitted received messages e FULL CAN capability when used in conjunction with XGATE
15. ibutes e No write e No execute MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc 7 Features e Non maskable interrupt on access violation 3 5 5 System Integrity Support e Power on reset POR e Illegal address detection with reset e Low voltage detection with interrupt or reset e System can run in Supervisor or User state e using a new bit in the condition code register e peripheral space can only be accessed in user state if enabled by a descriptor e Computer Operating Properly COP watchdog e Configurable as window COP for enhanced failure detection e Can be initialized out of reset using option bits located in Flash e Clock monitor supervising the correct function of the oscillator 3 5 6 Memory Options e 128K 256K 384K 512K 768K and 1M byte Flash e 2K 4K byte Emulated EEPROM s 12K 16K 24K 32K 48K and 64K Byte RAM e Flash General Features e 64 data bits plus 8 syndrome ECC Error Correction Code bits allow single bit failure correction and double fault detection e Erase sector size 1024 bytes e Automated program and erase algorithm Security option to prevent unauthorized access e Sense amp margin level setting for reads e Data Flash General Features e 32 Kbytes of D Flash memory with 256 byte sectors for user access e Dedicated commands to access D Flash memory over EEE operation e Single bit fault correction and double fault detection within a word during read operations e Auto
16. mated program and erase algorithm with verify and generation of ECC parity bits e Fast sector erase and word program operation e Ability to program up to four words in a burst sequence e Emulated EEPROM General Features e Automatic EEE file handling using internal Memory Controller e Automatic transfer of valid EEE data from D Flash memory to buffer RAM on reset e Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D Flash memory Ability to disable EEE operation and allow priority access to the D Flash memory e Ability to cancel all pending EEE operations to allow priority access to the D Flash memory 3 5 7 Oscillator OSC_LCP e Loop Control Pierce oscillator utilizing a 4MHz to 16MHz crystal e Good noise immunity MC9S12XE Family Product Brief Rev 9 4 2015 8 Freescale Semiconductor Inc Features e Full swing Pierce option utilizing a 2MHz to 40MHz crystal e Transconductance sized for optimum start up margin for typical crystals 3 5 8 Clock and Reset Generator CRG e Phase locked loop IPLL clock frequency multiplier e Internally filtered No external components required e Configurable option to spread spectrum for reduced EMC radiation frequency modulation e Fast wake up from STOP in self clock mode for power saving and immediate program execution 3 5 9 Non Multiplexed External Bus 208 pin and 144 pin packages only e Non Multiplexed External Bus 208 pin and 144 pin
17. ng XGATE co processor which is programmable in C language and runs at twice the bus frequency of the S12X with an instruction set optimized for 2015 Freescale Semiconductor Inc Introduction Application Examples 2 1 Body Controller Application LTE 2 2 Gateway Application Bxample Gr EDN hc e eee tee re re gee eater rea reer E reer tree Dol Block Daa ceninin 3 2 Peripheral and Memory Options Pe ZAI Familya 3 3 Critical Performance Paramnetei S unnn a 34 Chip Level Features csrisiae ionsar 33 Mod le Pears assis cssiscsteeanssacaranstoncaaee Developer Environment Document Revision History Contents A d A K freescale Application Examples data movement logic and bit manipulation instructions and which can service any peripheral module on the device The new enhanced version has improved interrupt handling capability and is fully compatible with existing XGATE module As with the 12XD Family the S12XE Family features an enhanced MSCAN module which when used in conjunction with XGATE delivers FULL CAN performance with virtually unlimited number of mailboxes and retains backwards compatibility with the MSCAN module featured on existing S12 products The S12XE Family has full 16 bit data paths throughout The non multiplexed expanded bus interface available on the 144 pin versions allows an easy interface to external memories In addition to the I O ports available in each module up to 25 further
18. s Versions with 8 SCI modules will have SCIO GC SCI2 SCI3 SC14 SCI5 SCI6 and SCI7 Versions with 7 SCI modules will have SCIO SCI1 SCI2 SCI3 SCH SCI5 and SCI6 Versions with 6 SCI modules will have SCIO GC SCI2 SCI3 SCl4 and SCI5 Versions with 5 SCI modules will have SCIO GC SCI2 SCI3 and SC14 Versions with 4 SCI modules will have SCIO SCI1 SCI2 and SCH Versions with 3 SCI modules will have SCIO GCI and GC Versions with 2 SCI modules will have SCIO and SCI1 Versions with 1 SCI module will have SCIO 3 SPI Options MC9S12XE Family Product Brief Rev 9 4 2015 Freescale Semiconductor Inc 5 EE Features Versions with 3 SPI modules will have SPIO SPI1 and SPI2 Versions with 2 SPI modules will have SPIO and SPI1 Versions with 1 SPI modules will have SPIO 4 IIC Options Versions with 2 IIC modules will have IICO and IIC1 Versions with 1 IIC module will have IICO TIM available via rerouting on EP100 EP768 devices 80 112 144 pinout options A D is the number of modules total number of A D channels I O is the sum of ports capable to act as digital input or output For details see the Port Availability by Package Option table in the MCS12XE Data Sheet 8 I O is the sum of ports capable to act as digital input or output For details see the Port Availability by Package Option table in the MCS12XE Data Sheet 9 Can only execute code from RAM NDN 3 3 Critical Performance Par
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