Atlas™ User`s Manual
Contents
1. AE EE AE AH E MESA 1 CPWR_OK 51 GND 101 D3V3 151 SCK 2 JTGCPU 52 D5V 102 GND 152 CGPI4 3 CINTHIN 53 GND 103 GND 153 SDA 4 CORE_OK 54 CINTLON 104 GND 154 CGPO7 5 CGPI7 55 GND 105 D3V3 155 CGPO6 6 CD31 56 D5V 106 GND 156 CGPO5 7 CD30 57 GND 107 GND 157 CGPO4 8 CD29 58 GND 108 GND 158 INTNS 9 CD28 59 GND 109 D3V3 159 INTN4 10 CD27 60 D5V 110 GND 160 INTN3 11 CD26 61 GND 111 CGPIO 161 INTN2 12 CD25 62 GND 112 GND 162 INTN1 13 CD24 63 GND 113 D3V3 163 INTNO 14 CD23 64 D5V 114 CA6 164 NMIN 15 CD22 65 GND 115 GND 165 CA10 16 CD21 66 GND 116 GND 166 CA9 17 CD20 67 GND 117 CA5 167 CA8 18 CD19 68 D5V 118 GND 168 CA7 19 CD18 69 GND 119 GND 169 CGPI3 20 CD17 70 GND 120 CA4 170 D12V 21 CD16 71 GND 121 D3V3 171 D12V 22 CD15 72 D5V 122 GND 172 CGPI2 23 CD14 73 GND 123 CA3 173 CPRESN 24 CD13 74 GND 124 GND 174 APRESN 25 CD12 75 GND 125 D3V3 175 BIGEND 26 CD11 76 D5V 126 CA2 176 CGPO3 27 CD10 77 GND 127 GND 177 CGPO2 28 CD9 78 GND 128 GND 178 CGPO1 29 CD8 79 GND 129 CA24 179 CGPOO Page 46 of 52 Atlas User s Manual Table 40 J3 pinout CGPI1 EJTCK GND CREVO EJTMS CREV1 EJTDI CREV2 EJTDO CREV3 EJTRSTN CREV4 EJDINT CREV5 CREV6 CREV7 CA15 CA14 CA13 CA12 GA11 9 2 2 J4 Connector The following pin layout is used for J4 Table 41 J4 pinout 1 RSTN 51 GND 101 D5V 151 GND2. Error in programming or set block lock bits Low volt Low programming voltage detected Lock det Master lock bit Block lock bit or RP lock detected Atlas User s Manual Page 41 of 52 9 Core Card design This section details the external specification that all Core cards must comply with 9 1 Interfaces The following features shall be present on the interface to the Core card 9 1 1 Power Power supplies at 3 3V 5V and 12V are present on the interface These are positioned such that if a Core card is placed on the Atlas 180 degrees incorrect all rails are shorted out by a number of pins This should place the PSU in shutdown mode It is not guaranteed that the 5V rail will be present before the 3 3V rail 9 1 2 PCI Bus The interface to the core card includes a PCI bus All core cards shall be 5V tolerant on inputs but drive 3 3V on all outputs on the PCI bus 9 1 3 Clock The PCI bus clock is driven to the Core card from Atlas The Core card shall be able to run with this clock at any frequency from 0 33MHz 9 1 4 Revision number The Core card drives a processor readable revision number via pins CREV 7 0 down to the Atlas card where the CPU will be able to read them via the CBUS This revision number could for example be set via 8 fit not fit resistors 9 1 5 12C bus An 12C bus is present on the interface This will typically be used for interrogating SDRAM DIMMs See User Manual for the address
3. The signals DSR and RI can be seen on the SAA9730 s GPIO signals as follows GPIO 0 RI GPIO 1 DSR Atlas User s Manual Page 33 of 52 Note that both RI and DSR are active low signals at the GPIO x input meaning that Control line ON 12V on RS232 OV on GPIO X 0 Control line OFF 12V on RS232 3 3V on GPIO x 1 The following 5 wire symmetric wired cable must be used to guarantee the correct operation of the HW flow control with standard PC COM port e 2 to 3 RXD to TXD e 3 to 2 TXD to RXD 5 to 5 GND to GND e 7 to 8 RTS to CTS e 8 to 7 CTS to RTS A recommended data terminal program for PC s running Windows OS is Procomm Plus32 from Datastorm Technologies Basic setup to allow Motorola S record file download as described below Communication settings in the menu area e Options gt SystemOptions gt ModemConnection gt System From here select the com port and click on the Modem ConnectionProperties to set the baudrate 38400 parity none data bits 8 stop bits 1 and important select use hardware flow control Download protocol setting in the menu area e Options gt SystemOptions gt ModemConnection gt Data From here set current transfer protocol to ASCII set all delays to 0 and set the CR LF options to don t translate CR LF The file to be downloaded to Atlas is selected via the path Data gt SendFil
4. This section details the board design details at a reasonable user level The schematics Ref 13 are available if more detailed knowledge is required 6 1 Compact PCI interface The Atlas Board is suitable for a System slot in a Compact PCI system and provides the appropriate clock reset and arbitration functions to the other boards in the rack It can be fitted in a peripheral slot in which case the rack will merely provide power no Com pactPCl function is then supported Software can detect which slot type Atlas is fitted to by reading the value of the SYSENN signal 1 system slot from GPIO 1 on the 21150 bridge chip If it is identified that the board is not in a System slot then the clock drivers in the bridge must then be disabled or they will prevent the other devices in the rack from functioning The backplane interface is 3 3V 5V compatible and will therefore function in any rack envi ronment 6 2 Primary PCI bus The primary PCI bus is implemented as a 5V 32bit and 33MHz PCI standard version 2 1 compliant bus that connects the main components on the Atlas Board The five devices on the primary PCI bus are e Core Card connector for connection to the system controller on the Core Card e Philips SAA9730 lO controller that implements the VGA interface and Video RAM two USB interfaces Keyboard and PS2 Mouse interface 12C interface to serial EEPROM on the Atlas Board and on the Core Card serial presence detect o
5. Address 1FC0 0010 is special in the sense that when the software reads this address it is overridden and does NOT decode to an address in Flash but rather to register address REVISION This is done to ensure future compatibility all possible implementations of MIPS Technologies boards will be able to identify their hardware environment and configure them selves accordingly When programming address 1FC0 0000 it is the Flash selected by switch S1 1 that is being programmed and the only way to read the programmed value back is to read the dedicated System or Monitor Flash address Reads from address 1E00 0010 will decode to an address in Flash RAM is typically mapped at the bottom of memory so that the exception vectors are located in fast memory Atlas does not specify a mapping for addresses above 0x2000 0000 which cannot be addressed in kseg0 1 Page 10 of 52 Atlas User s Manual See the appropriate data sheets for the 21150AB the SAA9730 and the SYM53C810A PCI devices to see how to configure these The I2C bus is controlled by the SAA9730 its slave address map is configured as follows Table 2 12C slave address map for EEPROM devices 12C slave address Function 0x50 256 bytes Core Card PC 100 SDRAM Core Card optional PC 100 SDRAM Core Card optional PC 100 SDRAM Core Card optional PC 100 SDRAM 0x51 256 bytes 0x52 256 bytes 0x53 256 bytes 0x54 0x55 512 bytes Atlas EEPROM unused area
6. S4 to bring up the board Check that the green 3V3 and 5V LEDs also turn on to indicate good power NOTE some ATX power supplies are unable to maintain power when the load is light If you experience problems where the 3V3 or 5V LED turns off without cause or never turns on then check the power supply A dummy load can be added to 5V to solve the problem but the best solution is to get a good power supply If you on the other hand are drawing power via the CompactPCI connectors then the board will boot as soon as there is power to the backplane The green FPGA LED should be on this indicates that the board s FPGA has booted The red RST LED should be off if lit this indicates that something is holding the board in reset When the CPU initially boots the YAMON monitor signs on using the Dbg Ser serial port the upper one with information about the board configuration details e board revision SDRAM size etc Finally you should arrive at YAMON s prompt line Simultaneously you should see the word YAMON on the ASCII LED display If you do not see this check with the YAMON User s Manual for what the display messages mean Note that you will be running in big endian mode and that you can change this with a switch setting See the Atlas User s Manual for details The command help lists the available commands in the YAMON monitor and help lt com mand name gt gives more d
7. 2 PCI_AD31 52 GND 102 GND 152 NC 3 PCI_AD30 53 GND 103 D3V3 153 GND 4 PCI_AD29 54 GND 104 D3V3 154 NC 5 PCI_AD28 55 GND 105 GND 155 GND 6 GND 56 GND 106 D5V 156 NC 7 GND 57 GND 107 GND 157 GND 8 PCI_CLK 58 GND 108 D3V3 158 NC 9 GND 59 GND 109 D3V3 159 GND 10 GND 60 GND 110 GND 160 NC 11 PCI_PAR 61 GND 111 D5V 161 GND 12 PCILFRAMEN 62 GND 112 GND 162 NC 13 PCI_IRDYN 63 GND 113 D3V3 163 GND Atlas M User s Manual Page 47 of 52 Table 41 J4 pinout PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_CBEN3 PCI_CBEN2 PCI_CBEN1 PCI_CBENO PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_TRDYN PCI_STOPN PCI_LLOCKN PCI_IDSEL PCI_DEVSELN PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_REQN PCI_GNTN PCI_PERRN PCI_SERRN NC PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 Page 48 of 52 Atlas M User s Manual 9 3 Physical design The core card is 170mm x 100mm and is mounted by pillars at each corner plus 2 x 200 way 4 row x 25 pin 1 27mm pitch connectors of type Samtec MOLC 150 31 x Q See Figure 9 Pin numbering on these connectors is as follows Figure 8 J3 and J4 pin alignment view from top of Core card 50 2 1 200 Note that one corner pillar top left in diagram is placed offset from a symmetrical position which is to guarantee t
8. ASCII value to this reg ister updates ASCII display posi tion 2 ASCIIPOS3 0x0000 0030 Writing an ASCII value to this reg ister updates ASCII display posi tion 3 ASCIIPOS4 0x0000 0038 Writing an ASCII value to this reg ister updates ASCII display posi tion 4 ASCIIPOS5 0x0000 0040 Writing an ASCII value to this reg ister updates ASCII display posi tion 5 ASCIIPOS6 0x0000 0048 Writing an ASCII value to this reg ister updates ASCII display posi tion 6 ASCIIPOS7 0x0000 0050 Writing an ASCII value to this reg ister updates ASCII display posi tion 7 which is the right most positioned character Name LEDGREEN Address 0x1F00 0400 Access R W Reset value 0x01 Table 17 LEDGREEN register 31 1 reserved 0 ON Set GREEN LED ON 51 1 Atlas M User s Manual Page 19 of 52 Name LEDBAR Address 0x1F00 0408 Access R W Reset value 0x00 Table 18 LEDBAR register CES ee Field name Function Initial value value reserved BAR 8 bits each corresponding to 1 LED 1 Name ASCIIWORD Address 0x1F00 0410 Access WO Reset value n a Table 19 ASCIIWORD register NN TEA Field name Function Initial value value Writing a 32 bit word to this register will a 32 bit word to this register will cause it to be displayed in hex on the ASCII character display Name ASCIIPOSO Address 0x1
9. Atlas EEPROM contains MAC address and serial number 0x56 0x57 512 bytes 4 1 Devices Devices in the memory map above are listed below with their internal register maps and pro gramming details Note that all addresses listed below are physical addresses It is recom mended to use the macros available in the YAMON source deliverable See Ref 6 for accessing these registers and bitfields All registers shall be addressed as 32 bit words and lie on 64 bit word boundaries This con vention allows software to access all registers using the same word address in both little and in big endian mode Those registers that contain a single value are not described in bit field detail these values are aligned to the LSB of the word Atlas User s Manual Page 11 of 52 4 1 1 Revision info Name REVISION Address 0x1FC0 0010 Access RO Reset value n a Table 3 REVISION register 0 reserved FPGRV 8 bit binary number gives revision of CBUS n a FPGA CORID 6 bit Core Card ID CORRV 2 bit Core Card revision PROID 4 bit binary number gives product ID PRORV 4 bit binary number gives product revision A cryptic word can be read here which imparts information about the revision of the Atlas and Core Cards This information is for MIPS Technologies internal use 4 1 2 Interrupt controller All sources of interrupt except NMI on the Atlas Core card plus those from the CompactPCI bus are
10. June 1 1995 Microsoft Standard Development Board SDB Requirements for Windows CE Version 5 4 2 3 CompactPCI Specification Version 2 0 R2 1 Microsoft Harp enclosure requirements Version 1 0 5 MIPS YAMON User s Manual MD00008 MIPS YAMON M Reference Manual MD00009 7 EJTAG specification Version 2 5 Dallas DS1687 data sheet Available from http Awww dalsemi com Texas Instruments TI 16C550C datasheet Available from http Awww ti com 10 Intel ATX Power Supply Design Guide Version 0 9 11 Philips SAA9730 Data sheet 12 Quality Semiconductor QS6612 data sheet Available from http Awww qualitysemi com 13 MIPS Atlas Schematic MD00019 4 6 8 9 Atlas User s Manual Page 51 of 52 11 Revision history Table 43 Revision history CN a SSCSC Y 1999 12 15 Initial release 2000 01 03 Updated with Core card specification 2000 01 13 Slight modifications to CBUS timing CRDN pulse shorter T12 added Improved board layout diagram Section 5 Added Front panel layout Fixed erroneous table and figure numbering 2000 02 07 Fixed copyright date Made CLOSED an alias for ON w r t switch settings Fixed TOC references 2000 03 22 Removed Header Files section replaced with reference to YAMON Ref Man ual and source deliverables Allowed 5 wire serial cable Added details of Flash programming and protection and YAM
11. diagram Section 3 Memory map Section 4 e Hardware jumpers amp configuration options Section 5 1 It is probably also well worth getting acquainted with the literature in the References section Atlas User s Manual Page 5 of 52 2 Getting Started 2 1 Supplied hardware The basic Atlas hardware consists of Atlas Board 2 2 Required hardware In addition to the basic Atlas hardware you will need e Compact PCI rack system or suitable enclosure with ATX power supply e The Core Card that carries your choice of CPU e Serial cable for RS232 Debug connection The cable must be a Null Modem cable with 9 way D female connector in both ends 2 3 Optional hardware The following may also be useful depending on your application e Video cable for VGA monitor Ethernet cable e USB cable e PS2 Keyboard mouse e SCSI cable Narrow SCSI 2 50 pin connector In depth debugging requires the following LA probe connectors that match with the AMP Mictor headers if you have a HP Logic Analyser e PCI probe board if you want to be able to monitor activity on the internal PCI bus e g FuturePlus FS2000 e CompactPCI probe board for the backplane bus e g FuturePlus FS3020 e Parallel port download cable for programming of Flash memory 2 4 Wiring it up First if this is not already fitted connect the Core Card It is fairly obvious how to do this the connectors J3 and J4 have the same numbers
12. escape sequences being sent The file format is a sequence of ASCII encoded hex bytes as described below How to download Switch OFF both the Atlas and the PC or workstation that will be used to download e Connect the parallel cable between the PCs parallel port and J14 on the Atlas e Switch S5 1 on the Atlas to ON or CLOSED e Switch both PC and Atlas ON e Run the download script to dump the file to the parallel port on the PC or w s Disconnect the parallel cable e Switch S5 1 to OFF and reset Atlas Note when S5 1 is set to ON it overrides any other Flash protection that may have been set by S1 3 According to the memory map in Section 4 the Monitor Flash is programmed on base address 1E00 0000 and System Flash is programmed on base address 1C00 0000 Which physical Flash that is being programmed when programming address range 1FC0 0000 is dependent of the position of switch S1 1 see Section 5 2 If any address outside the Flash is addressed the attempt will be ignored If S1 1 is ON the Monitor Flash will be programmed on base address 1FC0 0000 and if the switch is OFF it is the upper 4 MBytes from offset 0x01C0 0000 of System Flash that is pro grammed on base address 1FC0 0000 Note When programming the address 1FC0 0010 it is the Flash selected by switch S1 1 that is being programmed but when reading the address it is overridden and does NOT decode to an address in Flash but rather to register address REVISI
13. handled in an interrupt controller located in the CBUS FPGA They are combined together to generate an interrupt on the Core Cards INTN O signal The interrupt signals INTN 5 1 are always inactive It is recommended to use the macros available in the YAMON source deliverable See Ref 6 for accessing these registers The various interrupt sources are listed below together with their bit positions in the interrupt controller registers NOTE The field bits may not correspond to the actual signal voltage as many of these are active low All the interrupt bits are active high sense Table 4 Interrupt controllers registers field positions sits Fieldname Function __ _ _ 19 SERR Primary PCI SERR signal 18 INTD Primary PCI INTD PCI slot only 17 INTC Primary PCI INTC includes SCSI 16 INTB Primary PCI INTB includes SAA9730 15 INTA Primary PCI INTA PCI slot only 14 ATXFAIL Indicates ATX PSU about to fail 13 DEG The DEG signal from the PCI backplane indicates power supply is about to fail 12 ENUM The ENUM signal from the PCI backplane 11 PCID Compact PCI INTD 10 PCIC Compact PCI INTC 9 PCIB Compact PCI INTB Page 12 of 52 Atlas User s Manual Table 4 Interrupt controllers registers field positions Bits Field mame Function PCIA Compact PCI INTA reserved CORELO Core Card low priority interrupt COREHI Core Card high priority interrupt RTC Real Time Cl
14. CI SERR signal ATXFAIL from powersupply e Real time clock e Timer 0 in CBUS FPGA e Four PCI interrupts that are wired or signals from the PCI connector and PCI interrupt from Philips SAA9730 lO controller e Four Compact PCI interrupts e Two interrupts from Core Card ENUM signal from Compact PCI backplane DEG signal from Compact PCI backplane e Auxiliary Serial port interrupt from the 16550 UART NMI push button The NMI interrupt to the Core Card is controlled by the NMI push button debounced and latched in the CBUS FPGA interrupt controller see 4 1 2 The INTNO interrupt to the Core Card is controlled by the CBUS FPGA interrupt controller see Section 4 1 2 Interrupt controller INTN 5 1 are always driven inactive 6 8 Serial ports There are 2 serial ports on Atlas which are taken out to the front panel to standard male DB9 connectors marked Dbg Ser short for Debug Serial and Pd Ser short for Product Serial Each port is electrically identical with the pinout shown in the table below allowing full hard ware handshaking although one of them the Pd Ser on front panel is driven by the SAA9730 s main serial port while the other is driven from a separate 16550 UART chip Table 35 Serial port pinouts PIN NO Name Direction Input Input Output Output Input Output Input OO OO NN OD oO A wo mM Input
15. F00 0418 Access WO Reset value n a Table 20 ASCIIPOSO register 31 8 lreserved ASCII Writing an ASCII value to this register updates ASCII display position 0 Position 0 is the left most positioned character Register descriptions for ASCIIPOS1 to ASCIIPOS7 are identical with the description above for ASCIIPOSO 4 1 9 Reset control There are two different reset functionalities that are controlled by software Writing a magic value to the SOFTRES register immediately triggers a reset of the Atlas Board and the BRKRES register controls how the break condition on the Debug Serial port is monitored Both reset functions generate a board reset with the exact same effect as if you had pressed the reset button Page 20 of 52 Atlas User s Manual Name SOFTRES Address 0x1F00 0500 Access WO Reset value 0x00 Table 21 SOFTRES register 31 8 reserved 7 0 RESET Writing the magic value GORESET 0x42 to this field will initiate a board reset Name BRKRES Address 0x1F00 0508 Access R W Reset value 0x00 Table 22 BRKRES register 0 31 8 reserved 7 0 WIDTH Writing a value to this address indicates the Ox0A number of milliseconds in length a Break must be on the Dbg Ser interface in order i e 10ms to trigger a reset Valid values are from 0 to 255 A value of zero prevents this reset ever occurring NOTE The initial value for WIDTH of 10
16. G debugging as the only device then present in the chain is the CPU 6 16 Debug access For those long late night debug sessions you have access to most if not all interesting sig nals found on the Atlas board via the debug connectors and test points See the schematics Ref 13 for details Page 36 of 52 Atlas User s Manual 6 17 Timer RTC The Real Time Clock is a Dallas DS1687 5 with internal battery It contains a timer running at a fixed frequency 32 kHz Some Core Cards may need to be able to determine their own clock frequency by software The RTC timer can be used to do this to sufficient accuracy Atlas User s Manual Page 37 of 52 7 SDB Revisions The following table lists the issued revisions of Atlas and Core Cards that make the released Harp SDB revisions Table 36 Harp revisions Harp SDB Atlas Core card Date revision revision revision released Description CPU Card with QED RM5261 Proces 1999 07 05 Initial release for approv approv sor 00 0 als CoreLV 01 0 2000 03 09 Page 38 of 52 Atlas User s Manual 8 1284 Flash download format Both System and Monitor Flash can be programmed and reprogrammed via a download cable that connects directly to a PC parallel port The CBUS FPGA can read data from this port and execute the appropriate erase write cycles in the Flash The PC must be configured so that its printer port is set to Generic text only to avoid unpredictable
17. I controller Self explanatory e Intel 21150 PCI PCI bridge chip Self explanatory A 5V PCI board slot e The Core Card Atlas User s Manual Page 9 of 52 4 Memory map The memory map as seen from the CPU is partly dependent on the Core Card and how the PCI bus is configured However the Atlas design places some requirements on how the CBUS is mapped and therefore this area will always appear as shown below Table 1 Atlas physical memory map Base address Sie 0000 0000 128Mbytes Typically SDRAM on Core Card 0800 0000 Typically PCI 1800 0000 62 Mbytes Typically PCI 1C00 0000 32 Mbytes System Flash 1E00 0000 1E40 0000 12 Mbytes reserved Interrupt controller Timer Switches LEDs 1F00 0000 ASCII display Soft reset FPGA revision number RTC UART 1F10 0000 11 Mbytes Typically System Controller specific S1 1 ON Base of Monitor Flash 0x1E00 0000 S1 1 OFF At base of upper 4 Mbyte of System Flash 0x1DC0 0000 1FD0 0000 3 Mbytes Typically System Controller specific 1FC0 0000 1 Mbyte Note The shaded area of the table indicates memory areas the mapping of which depends on the implementation of the Core Card and of software The indicated mappings shown would be suitable for a Harp SDB implemen tation Note Which physical Flash that is being programmed when programming address range 1FC0 0000 is dependent of the position of switch S1 1 Note
18. L shall be written with a special code to enable writing to the Flash by asserting its programming enable or equivalent pin Writing is disabled by default after reset e Switch S1 3 See Section 5 2 can be set to prevent any writing to the System Flash by always deasserting the programming enable The Monitor Flash can also be reprogrammed but by default the sectors which contain the YAMON monitor are locked Lock Bits cannot be cleared unless you fit JP8 MFWR This prevents you overwriting YAMON by accident YAMON stores its environment variables in a writable sector of the Monitor Flash which is referred to in the YAMON documentation as Environment Flash Note that while Flash is being reprogrammed by software the code that performs the pro gramming will have to be copied into RAM and executed there as the Flash will be inacces sible during this process The Flash fitted are Intel 64Mbit StrataFlash and FlashFile devices which are the densest devices available at the time of writing See Intel s web site for the documentation however you may find it easier to use the programming APIs included in YAMON Note that from a hardware viewpoint the Flash appears as a 32 bit wide block with Atlas User s Manual Page 35 of 52 no individual write control capability to allow writing to just 1 16 bit halfword However this function can be achieved through software by running a dummy e g read cycle on the half word th
19. Mis TECHNOLOGIES Atlas User s Manual Document no MD00005 Revision 01 10 October 12 2000 MIPS Technologies Inc 1225 Charleston Road Mountain View CA 94043 Atlas User s Manual Page 1 of 52 Notice Copyright c 1999 2000 MIPS Technologies Inc All rights reserved Unpublished rights reserved under the Copyright Laws of the United States of America This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying modifying or use of this information in whole or in part which is not expressly permitted in writing by MIPS Technologies or a contractually authorized third party is strictly prohibited At a minimum this information is protected under unfair competi tion laws and the expression of the information contained herein is protected under federal copyright laws Violations thereof may result in criminal penalties and fines MIPS Technologies or any contractually authorized third party reserves the right to change the information contained in this document to improve function design or otherwise MIPS Technologies does not assume any liability arising out of the application or use of this infor mation Any license under patent rights or any other intellectual property rights owned by MIPS Technologies or third parties shall be conveyed by MIPS Technologies or any contrac tually authorized third party in a separate license agreement between the parties The i
20. ON The only way to read the programmed value back is to read the dedicated System or Monitor Flash address i e address 1C00 0010 or 1E00 0010 see Section 4 Memory map The Flash devices are organised in sectors of 64 Kbyte Monitor Flash and 128Kbyte Sys tem Flash Erase and Set Lock Bit commands operate on exactly one sector this being the sector currently addressed After the last block of 16 words in a sector are written into flash the address counter has advanced to the next sector This implies that a Set Address O to the sector has to be executed before a Set Lock Bit command S can be issued The file to be loaded into the Flash via the 1284 port has the following format Type ASCII hex both small and large letters are accepted White space Any characters below or equal to 20h are ignored after the character 1Bh start of a printer initialization command it ignores any character until next Reset Command Word width 32 bits data has to be in blocks of 16 words starting on a 16 word boundary Atlas User s Manual Page 39 of 52 A number of codes are used to control code download and Flash memory handling Table 37 Download codes Sets current writing erasing address in Atlas Board physi cal memory map format Addresses must be on 16 word boundaries Reset download system Erase the current Flash sector 64 KB Clear all Flash lock bits Set current Flash sector lock bit
21. ON upgrading Added EJTAG routing Added PCI arbiter description Required all INT pins to be connected on Core Card STATUS register MFWR field indicates write enabled Removed Atlas amp Core revisions table Moved to Errata sheet Added full name for CPU Card in SDB revisions table Minor fixes throughout 2000 04 13 Fixed incorrect references to Pd Dbg Ser ports 2000 06 20 Updated CBUS timing with CCSN to read data valid timing Updated copyright notice 2000 06 30 Updated Getting Started section Renamed bitfields in Interrupt controller Fixed definition of MFWR in STATUS register Minor edits 2000 07 10 Added more detail to effect of S1 on memory mapping 2000 08 30 Added component height restrictions to Core card specification Added details to memory map including restriction of boot flash area to 1MB Updated definition of JP8 Added reservation of and in 1284 flash download format description 2000 10 12 Whole of EEPROM now write protected by JP4 Page 52 of 52 Atlas User s Manual
22. Print command shows next 8 characters in ASCII display the command needs exactly 8 non white space characters Any character except for and ff may be printed use of these in the print command is reserved IC IS Comment rest of line gt data data has to be in blocks of 16 words without interruption of any Comments and Print Commands gt Example of code download format Exampl IR 1C000000 IR B 12345678 23456789 3456789A 456789AB 56789ABC 6789ABCD 789ABCDE 89ABCDEF SABCDEFO ABCDEF01 BCDEF012 CDEF0123 DEF01234 EF012345 F0123456 01234567 always 16 words in a block After a Reset it will start at 1C00 0000 i e base of System Flash erase the base sector and then write the 16 words into offset 0 Page 40 of 52 Atlas User s Manual If an error should occurs during Flash download the ASCII display will show an error mes sage Table 38 Flash download error messages Message Meaning Ill cmd Illegal command received e g R is received not R Illegal command received e g lA is received Illegal hex received in data or addr e g ABCDEFGH both G and H is illegal characters Hex expected always data blocks of 16 words e g a com ment is received in the middle of a block of 16 words Block erase suspended Error in block erasure or clear lock bits
23. Table of contents INTO CUCUON cacon ate da A RS A A AA AA 5 1 1 Purpose of the Atlas platf0rM ooonnnicccnnnnnniccnnnnnccccnnnnnnnncnnnnnnnnn e nn nn e ha 5 1 2 Mital SOciONS cia ease eee Sea 5 Le QUO A a nace eee 6 21 Supplied Hardware vivia iaa 6 2 2 Required hardWar8 oooooocccnnninnccnnnnnocccccnnnnonccnnnnnnnccnnn nar Anan rr 6 2 39 Optional hardware x orcas ere 6 24 NIE e RET LE eked desea ca eee beets A Sele Rane adie beet E A DE A AEN 6 2 5 POWer Up SEQUENCE sonense iari iniiai aapa A ea ENEA ANNE iA aN NA 7 3 Design overview Block diagram ccceseeeeeeeeenseseeeeeeeeeeeensneeeeneneeseeeeeeeeesnenees 8 4 gt Memory AD ita alten oo aaa in ad 10 Ad E E E E wait A E E E A E EA E E E E 11 AAA Revision IMO canica iene 12 4 1 2 interrupt controletoren E A AAO a 12 4 1 3 Hardware acknowledge oococcoccccnonnoccccnnonocccccnonnonc cnn nan n cnn nana cnnnnnnnnn 13 4 1 4 NMI interrupt Controller ooooonnncccnnnnnoccccnnnncccccnnnnrrcccnnnnnrrn cnn rc 14 4 1 5 NMI acknowledge oooomocccccnnnnccccnnnnnoccccnnnncnnccnnnn nn c cnn nn rnrn nan 14 4 1 6 Switches StallS cetonas sit 14 AAA O aan 16 ATS DISPIyS 000 a da tee heat daca 18 4 19 Reset control cuina rotas 20 4 1 107 PSU Sta Oy sitio dia 21 4 1 11 Flash writing Cont Olesea e AE cnn nn cnn 22 4 1 12 RTC real time clock oooccccncncnnnnccnnncnnnccnnnccnn cra rccrn nana 22 AS UA a e e oa ott le ere i ete 23 4 1 14 General purpose W O on
24. at is not to be altered Both Flash areas can also be reprogrammed by download of an ASCII file to the 1284 parallel port See Section 8 for details The YAMON binary distribution contains ASCII files suitable for this download process which allows upgrade or re installation of the monitor software 6 14 EEPROM The EEPROM is a Fairchild or alternative NM24C09 device with a total of 1024 bytes of memory which can be write enabled by fitting jumper JP4 Its upper half contains on manu facture the board serial number and the Ethernet MAC address See Table 2 for details of the memory map The lower half is unused and is it possible to use this area This is NOT recommended as you risk losing valuable and supposedly permanent data Note that on some older cards the unused area was accessible without fitting JP4 6 15 JTAG scan chain The Atlas board provides an EJTAG interface for software debugging The JTAG scan chain on the board is topologically connected as described by Figure 4 below Figure 4 JTAG scan chain JTAGCPU Backpl JTAG Core Card ackplane connector NE A TDI 21150 Bridge TDO VA SYSEN TDI l l l l l l L JTAGATLAS The signals JTAGCPU controls the routing of the JTAG chain on the Core Card JTAGATLAS controls the routing on Atlas These are both controlled by the setting of jumper J5 Its default setting no jumpers fitted is suitable for EJTA
25. ccurate timing measurement a fast timer is implemented It run from the fixed 40 MHz clock associated with the SCSI controller so it is independent of CPU and bus speeds It generate an interrupt when the count value match a compare value This interrupt is latched until cleared by writing to TMINTACK Page 16 of 52 Atlas User s Manual The timer device provides the following registers to control of the timer resources Table 12 Timer Registers BASE 0x1F00 0300 0x0000 0000 Timer O current count value When written value is updated The count value are reset to zero when the compare value TMOCMP is updated 0x0000 0008 Timer 0 current compare value When the counter reaches this value it resets TMOCNT to zero and continues counting and an interrupt signal TIMO is gener ated This is a momentary event so the interrupt latches and must be acknowledged by writing to the TMINTACK register When the TMOCMP value is updated the TMOCNT is reset to zero TMINTACK 0x0000 0020 Bit 0 Write 1 to clear interrupt TIMO Atlas User s Manual Page 17 of 52 Name TMOCNT Address 0x1F00 0300 Access R W Reset value 0x0000 0000 Table 13 TMOCNT register Bits Field name Function Initial value reserved 0x00 COUNT Timer O current count value When written O0x00 0000 value is updated Name TMOCMP Address 0x1F00 0308 Access R W Reset value 0x0000 0000 Table 14 TMOCMP register Bi
26. ctive Address hold from CCSN inactive CRDN width CRDN active to read data valid CRDN inactive to data bus tristated Read data hold time after CRDN inactive Address valid to data bus driven Write data setup to CRWN active Write data hold time after CWRN inactive CWRN pulse width Address valid to read data valid CCSN active to read data valid 9 1 9 EJTAG The EJTAG signals from the basic EJTAG connector are taken to the interface from the front panel connector 9 1 10 Misc Various debug reserved and presence detect functions see Section 9 2 9 2 Signals These signals are carried on J3 and J4 which are 200 pin 4 row 1 27mm pitch connectors SAMTEC type MOLC 150 31 S Q male fitted to Core card The interface signal list is as follows Table 39 CBUS signals from Core Core Atlas Function INTN 5 0 Input up Interrupt signals to CPU NMIN Input up NMI signal to CPU CD 31 0 1 0 CBUS data bus CCSN Output CBUS chip select CA 25 2 Output CBUS Address CRDN Output CBUS read strobe CWRN Output CBUS write strobe SCK 1 0 IIC bus clock SDA 1 0 IIC bus data Page 44 of 52 Atlas M User s Manual from Core Core Atlas Function CINTHIN Output up ee interrupt signal down to Atlas high CINTLON Output up te a int
27. directly to WinCE kernel image on boot else use Monitor WinCE convention only This switch provides a value which can be read from the SWITCH register Reset button NMI Power ON button In a benchtop environment this button will bring the ATX power supply out of standby It can also be used to generate an NMI to the CPU for example to shut down the PSU again This button will also make a hardware shutdown if pressed for more than two seconds The shutdown is performed when the but ton is released Push button When ON enables Flash programming via parallel port When ON set operation mode to big endian If the endianess is changed Atlas must be reset again in order for the new endian mode to take effect If the board is not reset unpredictable operation can occur No default function When ON set YAMON in factory default mode e g communica tion on debug serial port is forced to 38 4 kbaud 8 bits char RTS CTS hardware handshaking and no parity DIP switches S1 and S2 are readable by software and the functions given for S1 2 and S1 4 are conventions applicable in the Windows CE environment However S1 1 and S1 3 have direct effects on the function of the hardware S5 2 S5 3 and S5 4 are also readable by software and S5 3 is available for user applica tions For the DIP switches S1 S2 amp S5 a dot marks the switch referred to as 1 this is the left hand one when l
28. e The Serial Debug port can be used to reset the Atlas Board By default a Break condition on the Serial Debug port for more than 10 ms will reset the board exactly as if the reset but ton had been pressed This functionality can be disabled or the time can be changed to a different value by programming the BRKRES register in the CBUS FPGA see Section 4 1 9 6 9 Ethernet The Ethernet supports the 10baseT standard on a twisted pair connection The interface is implemented in the Philips SAA9730 chip see Ref 11 The PHY is a Quality Semiconductor QS6612 10 100BaseTX MII Transceiver for Category 5 Twisted pair cable which supports auto negotiation of speed 10 100MB s and duplex mode half or full duplex see Ref 12 This autonegotiation is however disabled and the interface always runs at 10Mbit s half duplex See Section 5 3 for details of the Ethernet LEDs which are built in to the RJ45 connector and the on board LED Page 34 of 52 Atlas User s Manual 6 10 Video The video from the SAA9730 is output on a VGA connector on the front panel Again consult the manual for the device for all details here There are 2 Mbytes of DRAM attached to the video controller which allow for good if not fantastic video resolutions 6 11 USB keyboard mouse parallel port All these functions are also provided by the SAA9730 Two USB ports are available on a dou ble connector the PC keyboard and mouse are on a double mini DIN c
29. e Ref 10 for details of a suitable supply The 12V rail is only connected to the PCI connector 6 5 Reset A push button on the front panel is provided to reset the board Alternative sources of reset are The CBUS FPGA when a software reset register is written e A reset push button fitted to the rack system e The power fail signal FAL from the CompactPCI backplane This stops the system before the supply voltage falls too low e The EJTAG probe system reset signal e An incoming break on Dbg Ser UART This may be disabled by software All resets are the same there is no distinguishing between a warm or a cold reset 6 6 Clocks Both PCI clocks normally run at 33MHz generated from a 66MHz crystal oscillator plus divider module Jumper J23 allows the user to decrease this frequency by half This will not affect the clock frequency of a CPU mounted on its Core Card The Core Card generates its own clock The different clocks on the board are e PCI clock oscillator 66 MHz divided to 33MHz or 16 5 MHz Ethernet 25 MHz e SCSI CBUS FPGA and Timer 40 MHz e Philips lO Controller 27 MHZ e Real Time Clock 32 KHz 6 7 Interrupt All sources of interrupt on the Atlas Board are handled in an interrupt controller located in the CBUS FPGA They are combined together to generate interrupts on the Core Card Page 32 of 52 Atlas M User s Manual All interrupt sources are listed below e P
30. errupt signal down to Atlas low CREVI7 0 Output ee Core card revision as a 6 2 bit binary BIGEND Input Sets CPU Endianness EJTCK Input down EJTMS Input up EJTRSTN Input down EJTDI Input up EJTDO Output E EJDINT Input down Sets Core card s JTAG output to come direct JTGCPU Input down from the CPU rather than also via other cir cuits CGP I 7 0 Output E R Neo ea from Core which can CGPOT 7 0 Input i i es purpose input to Core which Atlas can nn wire wr r n CUU 15 0 i E U aa A CPRESN Output P up e to zero to indicate presence of Core APRESN Input up he ee to zero on Atlas to indicate presence of D12V Input Twelve volt power for possible fan D5V Input E 5 Volt power D3V3 Input z 5 3 3 Volt power CPWR_OK Input i i r that power on both 3V3 and 5V rails CORE_OK Output E up Nets that Core is ready to come out of RSTN Input Global reset signal PCI_ADI31 0 1 0 PCI bus PCI_DEVSELN 1 0 PCI bus PCI_CBEN 3 0 1 0 PCI bus PCI_REQN Output PCI bus PCI_GNTN Input PCI bus PCI_SERRN 1 0 PCI bus PCI_FRAMEN 1 0 PCI bus PCI_IRDYN 1 0 PCI bus PCI_IDSEL 1 0 PCI bus Atlas User s Manual Page 45 of 52 from Core Core Atlas Function PCI_PAR 1 0 PCI_STOPN PCI_CLK PCI_TRDYN PCI_LOCKN PCI_PERRN 9 2 1 J3 Connector The following pin layout is used for J3 Table 40 J3 pinout
31. eserved 7 0 ADR Writing to this address sets the RTC inter nal register address which will be used on subsequent accesses to RTCDAT Name RTCDAT Address 0x1F00 0808 Access R W Reset value n a Table 26 RTCDAT register 0 31 8 reserved 7 0 DATA Once RTCADR has been loaded with the n a RTC internal register address this pseudo register can be used to read and write the addressed register 4 1 13 UART For details on programming the UART a Tl 16C550C see the appropriate data sheet on their web site Ref 9 The clock frequency for baud rate calculations is 3 6864 MHz The registers of the UART which have a native width of 8 bit are all memory mapped on 64 bit aligned boundaries with the following layout Table 27 UART Registers BASE 0x1F00 0900 ame Offset Address 0x0000 0000 Receive Transmit char register 0x0000 0008 Interrupt enable register 0x0000 0010 Read Interrupt identification Write FIFO control 0x0000 0018 Line control register 0x0000 0020 Modem control register 0x0000 0028 Line status register 0x0000 0030 Modem status register 0x0000 0038 Scratch register 1 The Divisor Latch Registers are accessible through RXTX and INTEN registers when bit 7 Divisor Latch Access Bit of the Line Control Register is set Atlas User s Manual Page 23 of 52 4 1 14 General purpose I O Eight GP inputs and eight GP outputs connected to the Core Card a
32. etailed information about the specific command See the YAMON documentation for a full description of the functionality Atlas M User s Manual Page 7 of 52 3 Design overview Block diagram The diagram below gives an overview of the important features of the Atlas Board ASCII LED DIL switch LED x9 Figure 1 Block diagram Pd Dbg Ethernet Ser Ser KB mouse gt PHY eT a UART oe video SAA9730 10 chip 1284 Graphics RAM 2Mbyte x64 SCSI 2 PCI SCSI interface 53C810A PCI slot PCI PCI bridge Intel 21150 CompactPCI PCI RTC CBUS ON NMI FPGA EIA O 12C i timer l A el interrupt _ controller interrupts etc System Flash 32 Mbyte x32 Monitor Flash 4 Mbyte x32 Atlas Core interface INT PCI bridge amp SDRAM controller System RAM RAM Page 8 of 52 Eines Atlas User s Manual The Core Card design shown is only a typical implementation in fact most implementations will look like this until CPUs that have outlived the SysAD bus start arriving However all Core Cards will conform to the same interface specification Worth noting is that the Core Card has its own clock Nothing on Atlas is synchronized to this clock as it is most probably independent of the PCI clock and the CBUS protocol is asynchronous by nature The CBUS exists to allow the CPU to access peripherals which ei
33. he board cannot be inserted the wrong way around The connectors chosen are low insertion force ones however the intention is that the user should be able to lever the card up by placing a screwdriver between the mounting pillars and the card Therefore tracking is forbidden in the areas at the ends of the card The Harp enclosure provides for a 3 slot wide SDB therefore the maximum centre centre shall be 3 x 20 32mm or 61mm Allowing for some margin therefore the maximum compo nent height above the combined Atlas Core cards shall be 55mm The Core card is mounted at a height of 11mm over the motherboard when using the con nectors given above However the existing placement of high components on the Atlas and Malta motherboards gives the following restrictions when placing components on the Core board Table 42 Core card component height restrictions Height restrictions on underside Whole card default No underside SMDs thicker than 6 5mm No leaded components at all No underside SMDs thicker than 1 2mm No underside SMDs thicker than 4 4mm No underside SMDs thicker than 4 4mm Atlas User s Manual Page 49 of 52 Figure 9 Core card template layout 0 a ie connector et 3 6 TOP VIEW 170 TOWARDS BACKPLANE gt __ Shaded zone No tracks on outer layers Page 50 of 52 Atlas User s Manual 10 References 1 PCI Local Bus Specification Revision 2 1
34. it notfit Peripheral slot configuration When fitted enables cable download of code to FPGA U2 Do NOT fit this it is reserved for production use fit notfit notfit When fitted allows writing to the Monitor Flash Lock bits from software lt also allows writing to the Monitor Flash fit notfit notfit itself regardless of the state of the Lock bits The dis abling function when not fitted is overridden by S5 1 when parallel port download is used 5 2 Switches Switches all on the front panel are listed below together with their functions and default settings This is how you should receive the Atlas Board For those switches that are soft Page 28 of 52 Atlas M User s Manual ware readable a switch in position ON or CLOSED will give a 1 in the appropriate reg ister Table 32 Switches Ref Type Default Description If ON system boots from Monitor Flash else System Flash Note Which physical Flash that is being programmed when pro gramming address range 0x1FC0 0000 is also dependent of the position of this switch When ON 0x1FC0 0000 maps to the Mon itor Flash base address When OFF 0x1FC0 0000 maps to the upper 4 Mbytes of System Flash i e 0x1DC0 0000 If ON debug serial port is used for debug communication else the Ethernet port is used for debug WinCE convention only If ON the System Flash is write protected else it can be written If ON jump
35. map 9 1 6 Interrupts Six interrupt signals to the MIPS CPU on the Core card are present as is a single NMI inter rupt signal triggered by a front panel pushbutton Core cards must route all of these inter rupts to the CPU if the CPU chip has fewer external interrupt pins then they should be ORed together 9 1 7 Endian The endian control signal BIGEND driven by Atlas according to setting of S5 2 Page 42 of 52 Atlas M User s Manual 9 1 8 CBUS The Core bus is designed to interface to simple devices on the Atlas card which it is nec essary that the CPU can access either before the PCI is up and running or with a low latency e g interrupt controller and Flash All core cards shall decode CPU addresses from 0x1C00 0000 to Ox1FFF FFFF These address shall then translate into addresses 0x0000 0000 to OxO3FF FFFF on the CBUS Bus signals are e CA 25 2 Address bus e CD 81 0 Data bus e CCSN Chip select CWRN Write strobe CRDN Read strobe Figure 5 CBUS Read cycle CA 25 2 k ADDR Y CD 31 0 RD DATA Y PER T gt 7 To T5 Figure 6 CBUS Write cycle cAf25 2 A ADDR CD 31 0 WR DATA CCSN T CWRN E MEA Atlas M User s Manual Page 43 of 52 Table 7 CBUS AC timing parameters Description Tmin ns Address valid to CCSN active CCSN valid to strobe CRWN or CRDN valid strobe CRWN or CRDN inactive to CCSN ina
36. mcccnnncncnnncccnncccnonncccnnncc rancia rcc carr nrrnnn 24 5 Board layoU danita dali laca 25 5 1 Connectors and JUMPEIS oooococcccnccccononaconaccnonnnnnnnn co nonnnnnnnn nn nro r cnn rra nar ranma 27 522 ISWIICNS vi A aad ae A a dee eee eae 28 53 Displays WEDS oiea Ana E aaa A ees 30 6 Hardware description icono ninan ianan nananana eisai 31 6 1 Compact PCI interface naniii diii ii ai aa ii iis 31 6 2 Primary POI DU A a a vy ate td 31 63 POLANEN aiid aa Mite aries Maiti eed ated ad 32 GA CROWE olei e at a a Re cetacean tee 32 A ss a A A N E E 32 06 Clocks m raaa eae a a a tada arean 32 67 emip e aaa AEA T A AAT 32 6 87 Serial pOr e a ea a a ear tac As 33 A O dae tinue T 34 6 107 MIO etna tailed dave old wi nevada eal ag dae Ban eee 35 6 11 USB keyboard mouse parallel POFt ccceeccceeeeeeeeeeeeeeeeeeeeeaeeeeeeeeetaeeeseneees 35 A A acini ae ewan easiness 35 6 13 gt Flash Memo y ir 35 6 14 EEPROM acini caine a de 36 Atlas User s Manual Page 3 of 52 6 15 JTAG SCAN ii AA eld eesti ties evden 36 6 16 DEDU ACCESS cit ica 36 CAZ Time AC date 37 Te SDB Revisions innicisioi ita dci dada leia ld ddr 38 8 1284 Flash download forMat nccccononccconnoncnccnnonnnccnnonnncernonnnnrrnnannnrrnnannnrrnnanaannns 39 9 COTO Card ASIN A a eee 42 A a o 42 Qla POW Gi AAA A A A dd 42 Ole ee IPEUBUS A A E RT O rod 42 A A O O 42 9 1 4 Revision NUMDET cc cccccccscsccncccsscrectecuceuserccuueduacsse
37. ms will cause problems if the baud rate of the serial port is less than 2400 Baud If baud rates below 2400 Baud are used this register must be programmed to a larger value 4 1 10 PSU standby If and only if you are running from an ATX PSU you have the ability to shut down into a standby mode until the ON NMI button is pressed again Atlas User s Manual Page 21 of 52 Name PSUSTBY Address 0x1F00 0600 Access WO Reset value n a Table 23 PSUSTBY register Bits Field name Function Initial value 31 8 reserved 7 0 STBY Writing the magic value GOSTBY 0x4d to this address will shut down the ATX PSU 4 1 11 Flash writing control The following register provides access to enable for writing programming the System Flash devices Name SFWCTRL Address 0x1F00 0700 Access R W Reset value 0x00 Table 24 SFWCTRL register 0 31 8 reserved 7 0 WRENA Writing the magic value ENSFWRITE 0xC7 to this address will enable writing to the System Flash It will not however over ride switch S1 3 4 1 12 RTC real time clock For details on programming this device see the appropriate data sheet which is available from their web site Ref 8 The device is the Dallas DS1687 5 with internal battery Page 22 of 52 Atlas M User s Manual Name RTCADR Address 0x1F00 0800 Access WO Reset value n a Table 25 RTCADR register Bits Field name Function Initial value 31 8 r
38. n the SDRAM module Serial Debug RS232 Interface and the Ethernet interface e Intel 21150AB PCI to PCI bridge that implements the bridge between the PCI bus on the Atlas Board and the Compact PCI interface that connects to the back plane in the rack system Symbios SYM53C810A SCSI 2 controller with active termination e 5V 32 bit PCI connector that can be used for debug trace purposes or for installation of a PCI board For configuration purposes the IDSEL and INT signals to the PCI devices are connected as shown below shown below Table 34 IDSEL and INTA for PCI devices Device IDSEL PCI PCI Interrupts address line Bc INTAN PCI_INTBN PCI_INTCN PCI_INTDN 21150 PCI to PCI bridge PCI_ADP25 none SYM53C810A SCSI controller PCI_ADP26 SCSI_IRQ Core Card PCI_ADP27 Special interrupt see Table 4 PCI connector PCI_ADP28 INTA SAA9730 lO controller PCI_ADP29 Atlas M User s Manual Page 31 of 52 6 3 PCI Arbiter The PCI arbiter controls the request and grant scheduling to the PCI components and is implemented in an Altera MAX7064 EPLD The PCI arbiter implements a round robin scheme where each of the devices have equal pri ority 6 4 Power The board draws power from the Compact PCI backplane or with 3 3V 5V and 12V supplied from a standard PC ATX power supply connected to J12 This should comfortably be able to supply enough current for the board and conceivable Core Card options Se
39. nformation contained in this document constitutes one or more of the following com mercial computer software commercial computer software documentation or other commer cial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this infor mation from MIPS Technologies or any contractually authorized third party MIPS R3000 R4000 R5000 R8000 and R10000 are among the registered trademarks of MIPS Technologies Inc and R4300 R20K MIPS16 MIPS32 MIPS64 MIPS 3D MIPS MIPS II MIPS Ill MIPS IV MIPS V MDMX 4K 4Kc 4Km 4Kp 5K 5Kc 20K 20Kc EC MGB SOC it SEAD YAMON ATLAS JALGO CoreLV and MIPS based are among the trademarks of MIPS Technologies Inc All other trademarks referred to herein are the property of their respective owners Page 2 of 52 Atlas User s Manual
40. o used to program Flash devices under production 10 pin 0 1 header Download connector for Arbiter EPLD AMP 38 pin Mictor HP Logic Analyzer connector AMP 38 pin Mictor HP Logic Analyzer connector AMP 38 pin Mictor HP Logic Analyzer connector AMP 38 pin Mictor HP Logic Analyzer connector AMP 38 pin Mictor HP Logic Analyzer connector 3 pin 0 1 header Atlas User s Manual LED connector If a front panel mounted LED is to be used instead of D1 then this should be fitted to pins 3 cathode amp 2 anode Otherwise to use D1 fit a jumper between pins 1 and 2 Page 27 of 52 Table 31 Jumpers Silk Descrip screen tion term off Enables the onboard active Enables the onboard active SCSI terminations terminations tpwr off Enables power to external SCSI terminations Switches PCI clocking frequency both busses between 33MHz and 16 5MHz When fitted enables writing to the EEPROM Do NOT fit this it is reserved for production use When not fitted the Core Card routes JTAG through the CPU only When fitted allows routing of JTAG not fit notfit notfit Pin 3 4 EJTAG chain through Atlas backplane components 33 16 33 fit notfit nottfit notfit Pin 1 2 All other pins are reserved Do not fit jumpers to these ordinary JTAG TDI TDO connection Inverts JTAG TDI TDO connection System slot configuration f
41. ock reserved TIMO Timer 0 in CBUS FPGA SER Auxiliary serial port chip 8 7 6 5 4 3 1 0 The interrupt controller provides the following registers to enable control of interrupts Table 5 Interrupt Controller Registers BASE 0x1F00 0000 Offset Address Access Function Initial value 0x0000 0000 Raw value on external interrupt lines NOTE This may not corre spond to the actual signal voltage as many of these are active low All these INTRAW bits are active high sense INTSETEN 0x0000 0008 Writing a 1 in a given bit position sets the corresponding bit in the INTENABLE register INTRSTEN 0x0000 0010 Writing a 1 in a given bit position OxFFFF FFFF clears the corresponding bit in the INTENABLE register INTENABLE 0x0000 0018 Each bit that is a 1 indicates that the corresponding interrupt is enabled INTSTATUS 0x0000 0020 Shows the status of enabled inter rupts only i e INTRAW anded with INTENABLE Note that several interrupts can be enabled or disabled in the same operation but that it is impossible to both enable and disable interrupts in the same operation 4 1 3 Hardware acknowledge The DEG interrupt is by nature transient Therefore it is debounced and latched and thereaf ter treated as ordinary level based interrupt in the interrupt controller It can be cleared by writing to HWINTACK When the bit in this register is written a
42. ome spares in case you lose any A dot by a pin indicates which pin is pin 1 On all jumpers pin numbering goes crosswise i e the end pins are 1 and 2 this is not always the case on other connectors Table 30 Interface connectors a ve O esa OOOO O CompactPCI Carries conventional PCI signals to from the backplane CompactPCI Carries the extra CompactPCI signals required of a System Board to from the backplane 200way header Connects the Core Card Carries amongst other things the CBUS 200way header Connects the Core Card Carries amongst other things the pri mary PCI bus RJ45 Ethernet 15 pin DSUB VGA video connector Connects to a standard PC monitor Dual USB Two USB host ports Dual 6 pin miniDIN Connection to a PC keyboard lower and mouse upper Dual 9 pin DSUB Serial ports Dbg Ser upper and Pd Ser lower 14 pin 0 1 header EJTAG connector As per EJTAG specification see Ref 7 Pin 12 removed for keying PCI slot Connects to the primary PCI bus Allows insertion of probe board or PCI board with additional functionality ATX PSU This connects the power in a benchtop environment 50 pin 0 1 header SCSI interface Connects to e g HDD via IDC ribbon connectors 26 pin 0 1 header IEEE1284 Flash programming port This can either be used as a parallel port for communications and is als
43. on both boards if you are in doubt about the orientation One of the corner mounting pillars is also offset to prevent incorrect insertion When removing the Core Card be careful There will typically be BGA devices fitted which can take offence at having the board bent violently Under each corner of the Core Card is a mounting pillar with a gap where a screwdriver can be inserted to gently lever it up Only apply the screwdriver to the PCB area around the mounting holes you don t want to cut any tracks by accident You will most likely want to also have the following set up Page 6 of 52 Atlas User s Manual e Serial port The supplied PROM monitor YAMON by default signs on via the serial debug port using 38 4 kbaud 8 bits char RTS CTS hardware handshaking and no parity A 5 wire cable is sufficient The implemented signals must be RXD TXD RTS CTS and GND see Section 6 8 Serial ports for serial connector pinout Ethernet Twisted pair ethernet cable will plug into the front panel this will run at 10 Mbit s half duplex e Check that the 4 way DIP switches S1 and S5 are in the positions labelled as default in Table 32 2 5 Power up sequence If you are using an ATX PSU via J12 when you first connect the power supply and switch it on the only thing that happens is that the green 5VSB LED turns on because the ATX power supply comes up by default into standby mode Press the switch marked ON NMI
44. onnector both on the front panel The parallel port is not on the front panel for space reasons we also assume that most bulk data transfer will be done using Ethernet The parallel port also allows the user to reprogram the Flash memory although this will typ ically only be done under production See Section 6 13 6 12 SCSI The Narrow SCSI 2 connector J13 is mounted on the furthest edge of the board from the front panel It is not going to be easy to use this in a rack situation The SCSI controller is a SYM53C810A used to be Symbios now LSI Logic and unfortunately neither company seem willing to place their documentation on the Web You may need to order a paper copy by snail mail if you re going to be doing detailed SCSI work In this case a SCSI probe for exam ple the FuturePlus FS2230 31 may also be very useful 6 13 Flash memory Atlas is fitted with 36Mbytes of Flash memory divided up into two sections Monitor 4 Mbytes and System 32 Mbytes S1 1 selects which is used for boot i e which Flash area that is accessed on address 1FC0 000 Both Monitor Flash and System Flash are always visible See Section 4 for details of the Atlas Board memory map If S1 1 is set to ON the system will boot from the Monitor Flash Otherwise the system will boot from an address in the System Flash The System Flash can be reprogrammed by software There are two protection mechanisms e A software addressable register FW_CTR
45. ooking at Atlas on a bench Atlas User s Manual Page 29 of 52 5 3 Displays LEDs There are three displays near the front panel See Section 4 1 8 on how to control these and various LEDs placed on the Atlas board Table 33 LEDs on the Atlas Board Ret Tre 7 SSCSC C d ON after reset is then switched off by the boot software There is the option to have this replaced by a front panel mounted LED connected to J21 J21 must have a jumper fitted between pins 1 2 to enable use of the on board D1 Green LED 8 way bar LED Function undefined Can be written to by software Used by YAMON to display status during boot can be used afterwards 8 char ASCII display for any user purpose Indicate that power is applied to 3 3V 5V and 5VSTBY rails respec tively Green SMD LED Indicates that CBUS FPGA programming completed OK Red SMD LED Indicates that RSTN is active Yellow SMD LED Indicates TX Ethernet packets Green SMD LEDs The two LEDs which are built in to the RJ45 connector give the status as follows LNK SPD LED left LED Link status Speed LED Color Xx None off 10 Yellow 100 Green ACT DPLX LED right LED Activity Duplex LED Color None off Yellow Green Additionally the yellow LED D8 mounted on the PCB near the connector also gives indication of transmitted packets Page 30 of 52 Atlas M User s Manual 6 Hardware description
46. re implemented on the Atlas Board Read documentation for Core Card for the usage Name GPOUT Address 0x1F00 0A00 Access R W Reset value n a Table 28 GPOUT register Bits Field name Function Initial value 31 8 reserved 7 0 OUTVAL Writing to this address sets the 8 GP output 0x00 pins Reading gives the actual setting of the GP output pins Functionality is Core Card dependent Name GPINP Address 0x1F00 0A08 Access RO Reset value n a Table 29 GPINP register ae ie Ce 31 8 reserved 7 0 INPVAL Reading gives the actual state of the GP n a input pins Functionality is Core Card dependent Page 24 of 52 Atlas M User s Manual 5 Board layout The diagram in Figure 2 shows the basic layout of the Atlas Board Figure 2 Atlas board layout J14 oa oo oo oa oo oa ood oo oo oa oo oo BO J4 JPeEEHH JP3 D00 J10 merma dae AER gogg lecccocs U1 Atlas User s Manual Page 25 of 52 The layout of the front panel if fitted is as shown below Figure 3 Front panel layout Page 26 of 52 MIPS Technologies Inc Atlas SDB CPU REV Ethernet a 07 O6 S S 1284 03 02 01 Oo C Status Kbd Mouse a PS 2 0o 1 USB g S1 RESET ON NMI PdSer DbgSer i RS232 Atlas User s Manual 5 1 Connectors and Jumpers All jumpers and connectors are listed below All jumpers are standard 0 1 pitch It is worth getting s
47. s 1 the interrupt is cleared Atlas User s Manual Page 13 of 52 Name HWINTACK Address 0x1F00 0100 Access WO Reset value n a Table 6 HWINTACK register reserved DEG Write 1 to acknowledge DEG reserved 4 1 4 NMI interrupt controller When the ON NMI push button is activated the signal is debounced and latched in the NMI interrupt controller This signal then generates an interrupt on the MIPS core LV NMIN pin Name NMISTATUS Address 0x1F00 0024 Access RO Reset value n a Table 7 NMISTATUS register 31 1 reserved n a 0 ONNMI Pending NMI from ON NMI push button n a 4 1 5 NMI acknowledge The ON NMI interrupt is by nature transient Therefore it is debounced amp latched and there after treated as ordinary level based interrupt in the NMI interrupt controller The NMI inter rupt can be cleared by writing to NMIACK When the bit in this register is written as 1 the interrupt is cleared Name NMIACK Address 0x1F00 0104 Access WO Reset value n a Table 8 NMIACK register Bits Field name Function Initial value 31 1 reserved n a 0 ONNMI Write 1 to acknowledge NMI n a 4 1 6 Switches status The following registers allow software to monitor the state of various switches and jumpers on the Atlas board All DIP switches give a value of 1 for a switch in the ON or CLOSED position Page 14 of 52 Atlas M User s Manual There is no debo
48. secnauuacercnsctucetaerannacdess 42 Qe 1 2G e D nn nica 42 916 Inte ruplS sis tadas 42 A EMEA aches ects E E Sapa dee Dead pe Ee 42 9 18 CBU Se ia A A A a cl AT 43 91149 EJTAG E ET EE E A A E ala diia 44 AO MISC A a E a a a a 44 A A A E O O E E teases 44 21 JI COnne ClO fines acini A a ravi 46 A SONNE CIOR AAA o ctaniiad cvvbaanaghs desuteskea clyeidhavershanstea casera 47 93 Physical desig ecann a e a A e diene lene 48 10 References oia cai wiv wns BUG did dewey dare Nada 51 11 Revisi n Risto Miri 52 Page 4 of 52 Atlas User s Manual 1 Introduction This document is for the user of the Atlas platform It details how to use the board set it up and the software relevant information 1 1 Purpose of the Atlas platform The Atlas platform was designed in order to provide a standard platform for development work with MIPS32 and MIPS64 CPUs It is compatible with the Microsoft Harp SDB specification Ref 2 and as such can be used for Windows CE development work The design is composed of two parts the Atlas Board which is 6U CompactPCI form factor and holds the CPU independent parts of the circuitry and a Core Card which holds the CPU plus its System Controller and fast SDRAM memory It is intended for use in a suitable CompactPCl rack system 1 2 Vital sections To save you the trouble of looking in the Contents list the most immediately interesting sec tions are probably e Block
49. ther have to be available before the PCI bus has been configured for example the Flash memory it s booting from or those that require simple low latency access for example the interrupt controller the debug LEDs and so on The Flash is divided up into two areas known as Monitor and System In principle the Monitor area is inviolate it is there so you can easily recover if you should happen to corrupt the System Flash entirely It can be reprogrammed but only via a hardware download cable The System area can be reprogrammed at will Atlas can be configured by setting S1 1 to boot from either Flash area The primary PCI bus is 32 bit 33 MHz PCI standard version 2 1 compliant It connects to the backplane CompactPCI bus via the bridge chip and allows devices on the bus and back plane DMA access to the RAM on the Core Card A single 5V PCI slot is provided on the Atlas to allow insertion of optional peripherals and also provides a way of monitoring traffic on this bus On the primary PCI bus are e Philips SAA9730 lO controller This device provides a large number of interface functions the Pd Ser serial port Ethernet USB IEEE1284 keyboard and mouse plus it s a pow erful graphics controller Additionally it provides a 12C serial bus which gives access to the EEPROM containing non volatile data and any similar devices on the Core Card e g SDRAM modules e LSI Logic used to be Symbios SYM53C810A SCS
50. ts Field name Function Initial value reserved COMP Timer O current compare value When the 0x00 0000 counter reaches this value it resets to zero and continues counting and an interrupt signal TIMO is generated This is a momentary event so the interrupt latches and must be acknowledged by writing to the TMINTACK register Name TMINTACK Address 0x1F00 0320 Access WO Reset value n a Table 15 TMINTACK register Bits Field name Function Initial value 31 1 reserved n a 0 TMOACK Write 1 to acknowledge interrupt of TIMO n a 4 1 8 Displays There are 3 display devices on the front panel The single green LED an 8 LED array and an 8 character ASCII display HDSP 2532 These are controlled through the following reg isters Page 18 of 52 Atlas M User s Manual Table 16 Display Registers BASE 0x1F00 0400 LEDGREEN 0x0000 0000 Bit 0 Green LED is ON LEDBAR 0x0000 0008 8 bits each corresponding to 1 LED 1 ON ASCIIWORD 0x0000 0010 Writing a 32 bit word to this regis ter will cause it to be displayed in hex on the ASCII character dis play ASCIIPOSO 0x0000 0018 Writing an ASCII value to this reg ister updates ASCII display posi tion 0 which is the left most positioned character ASCIIPOS1 0x0000 0020 Writing an ASCII value to this reg ister updates ASCII display posi tion 1 ASCIIPOS2 0x0000 0028 Writing an
51. uncing on these registers so if software wants to monitor a value while it changes allowance for this must be made by waiting for the new value to become stable Name SWITCH Address 0x1F00 0200 Access RO Reset value n a Table 9 SWITCH register 0 reserved DIP switch S1 bit 4 DIP switch S1 bit 3 Flash write protection DIP switch S1 bit 2 DIP switch S1 bit 1 Flash address mapping 8 bit value of the setting of DIP switch S2 LSB is set by the lefthand switch See Section 5 2 for description of switch S1 functionality Atlas M User s Manual Page 15 of 52 Name STATUS Address 0x1F00 0208 Access RO Reset value n a Table 10 STATUS register PO E e e 31 5 reserved 4 MFWR 0 indicates Monitor Flash lock bits are n a write enabled JP8 fitted S54 1 will set YAMON in factory default mode n a communication on serial debug port etc as controlled by switch S5 4 DIP switch S5 3 1 indicates big endian mode as controlled by switch S5 2 1 indicates that Atlas is plugged in to a System Slot of a Compact PCI backplane SYSENN signal Name JMPRS Address 0x1F00 0210 Access RO Reset value n a Table 11 JMPRS register A A O ee 31 2 reserved 1 EELOCK State of JP4 Not fitted 1 EEPROM n a write protected PCI33M State of JP3 PCI freq 1 33MHz 0 n a 16 5MHz 4 1 7 Timer To allow a
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