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Tram-rac 4A Housing Service Kits

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2. 6 28 Tram rac 4 Housing Revision A 2002029 021 2004289 001 iagram D ic Schemat Tram rac 4A Processor Acquisition PCB 6 40 6 1335 A05 S 580112 4 2 11 77 SGYHY 308 NI 100 682700 39v 11 151003 805533084 S4190 TONHIIL NOLLVPGIOANI M91 1 SWHO NI SINIYA 3ONVISIS3U 11 Z W3HJS YSIH3LSY NY SWHISAS 49 031412395 351 10 553140 9 of 9 FE T INT 198 2 09 pasnun A9 03 01104 TYNDIS 11 1 L 8 1 20 1538183 00 7 9133 390001 1 OND 4348 3 283 OT EE 440001 199 9 083 T ED 1 OND 100A NIA LOZSJIW 910 1 AEE sanddns PUD 100A NIA 02531 4080790 4080790 SZESLIL 100 2855007 00 0 507 8 208 415421 L00L13H7L 9SZZ9WH 200 625507 87251208 SNId 123 02 ON 1138 1138 1901 PUNOJD puo 6 29 Housi
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5. Housing Service Manual Two Board 2002029 021 GE Medical Systems Information Technologies gemedics Due to continuing product innovation specifications in this manual are subject to change without notice Trademarks Listed below are GE Medical Systems Information Technologies trademarks All other trademarks contained herein are the property of their respective owners 900 SC ACCUSKETCH AccuVision APEX AOUA KNOT ARCHIVIST Autoseg BABY MAC Qwik Connect CardioServ CardioSmart CardioSys CardioWindow CASE CD TELEMETRY CENTRA CHART GUARD CINE 35 CORO COROLAN COROMETRICS Corometrics Sensor Tip CRG PLUS DASH Digistore Digital DATAQ E for M EAGLE Event Link FMS 101B FMS 111 HELLIGE IMAGE STORE INTELLIMOTION LASER SXP MAC LAB MACTRODE MANAGED USE MARQUETTE MARQUETTE MAC MARQUETTE MEDICAL SYSTEMS MARQUETTE UNITY NETWORK MARS MAX MEDITEL MEI MEI in the circle logo MEMOPORT MINISTORE MINNOWS Monarch 8000 MULTI LINK MULTISCRIPTOR MUSE MUSE CV Neo Trak NEUROSCRIPT OnlineABG OXYMONITOR Pres R Cuff PRESSURE SCRIBE QMI QS Quantitative M edicine Quantitative Sentinel RAC RAMS RSVP SAM SEER SILVERTRACE SOLAR SOLARVIEW Spectra 400 Spectra Overview Spectra Tel ST GUARD TRAM TRAM NET TRAM RAC TRAMSCOPE TRIM KNOB Trimline UNION STATION UNITY logo UNITY NETWORK Vari X Cardiomat
6. 4 Housing Input and Output Connectors Table 2 1 4 30 Connectors to Parameter Module Slots Pin Signal Name Signal Level 10 Signal Description B9 123KHZ Drain O 123 kHz Clock Signal provided to the modules for the purpose 1K 5V pull up of modulating signals for transfer across the module s isolation barrier using an inductive coupling mechanism 10 CALIRATE Open Drain O Module Calibrate Signal is an active low calibrate control 1K 5V pull up provided to the modules NOTE This function is not currently implemented B101 34 0 Blank Signal is asserted when spike is 1K 5V pull up detected and provided to a discrete parameter module to indicate that spike should be rejected NOTE This function is not currently implemented B102 WF 5 Waveform Output no 5 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the 4 signal 11 11 GND OV O Ground Logic reference and 5V return 1214 SLOT1 4 Tram net Enable Determines whether the module is capable of Tram net communication and also indicates to the module thatthe Tram Rac 4 housing is capable of supporting Tram net
7. 5 1 Theory of 5 3 OVEIVIEW AR ek hee dy AR YD A anes 5 3 Top Level Block 5 3 Block Diagram of Control Signals 5 6 Indicators and Controls 5 7 Interconnection Diagram PN 900081 5 8 Input and Output Connectors 5 10 Exploded View PN 900031 005 006 5 15 Parts List PN 900031 005N 006N 5 20 Tram rac 4A Processor Acquisition PCB 6 1 Theory of 6 3 OVEIVIOW 2 u 6 3 Block Diagram bae uu po del dq 6 4 Microprocessor 6 4 Microprocessor Memory i 6 5 Reset Generator and Watchdog 6 5 PCB Clock tres tete ees prendere es 6 6 Analog Multiplexers 6 6 Noise Filter and Buffer Amplifier 6 6 Analog to Digital Converter 6 6 RAC Field Programmable Gate Array FPGA 013
8. 3 6 Receptacle ence ayau 3 7 Ground nacti 3 7 Ground Earth Wire Leakage Current Tests 3 8 Enclosure Leakage 5 3 10 Tram rac 4A Housing Service 3 12 PN 2006853200 Wd ew A 3 12 20068545001 detti 3 12 2006855 001 Repair Kit 3 to 2 Board Conversion 3 12 5 5 3 13 Log 245 3 14 Troubleshooting 4 1 Controlling Electrostatic Discharge Damage 4 3 Guidelines melee e d 4 3 Wall Receptacle Check 4 4 Measure 5 scie oed eene a ae 4 4 Ground Neutral Loop Resistance 4 4 Check PowenCord 3 on Penn Ra 4 5 General Fault Isolation 4 6 Pirst THINGS tQ ASK dm ttr rv A A c eto eie A en t 4 6 4 7 Tram rac LED Troubleshooting Chart 4 8 ii Tram rac 4A Revision A 2002029 021 Housing
9. Pin Signal Name Signal Level 10 Signal Description B9 123KHZ Drain O 123 kHz Clock Signal provided to the modules for the purpose 1K 5V pull up of modulating signals for transfer across the module s isolation barrier using an inductive coupling mechanism 10 CALIRATE Open Drain O Module Calibrate Signal is an active low calibrate control 1K 5V pull up provided to the modules NOTE This function is not currently implemented B101 34 0 Blank Signal is asserted when spike is 1K 5V pull up detected and provided to a discrete parameter module to indicate that spike should be rejected NOTE This function is not currently implemented B102 WF 5 Waveform Output no 5 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the 4 signal 11 11 GND OV O Ground Logic reference and 5V return A1214 SLOT1 4 Tram net Enable Determines whether the module is capable of Tram net communication and also indicates to the module thatthe Tram Rac 4 housing is capable of supporting Tram net communication low logic level indicates Tram net capability a high logic level indicates synchronous serial shift register co
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12. ECG A4 SYNC ECG 24 DACD3 24 14 WF OUT11 MOD DATA CLOCK MOD DATA CLOCK 25 DAC D4 25 15 OUT13 SLOT2 A6 51074 26 DAC D5 26 MDO SLOT2 SLOTA 27 DAC D6 27 J11 MOD DATA LATCH MOD DATA LATCH 28 DAC D7 28 OUT4 LAGND 29 GND 29 LCALIBRATE LCALIBRATE 5V 30 PSI J8 AC SOURCE GND A41 SND 31 DAC D8 31 LINE A12 LIN ENA SLOT2 A12 LIN ENA SLOT4 32 DAC 09 32 NEUTRAL A13 D10 33 GROUND 15 15 14 14 34 DAC D11 34 A15 AGND A15 AGND 35 OUT SEL2 35 W1P1 W1 W1P1 36 OUT SEL1 36 gr WF CH3 gr WF CH7 37 OUTSELO 37 a MOD EN CH3 25 MOD EN CH7 ANA OUT 38 WF CH4 WF CH8 39 39 1654 165 40 5V 40 gs gs NC 41 GND 41 WF OUT WF OUT 42 5 42 OUT2 OUT2 43 GND 43 OUT3 WF OUT3 44 5 44 123 2 123 2 45 GND 45 WF OUT5 PACER BLANK 46 5 46 B10 GND B10 GND 47 AGND 47 B11 45V B11 35V 48 15V 48 B12 15V B12 15V 49 AGND 49 B13 B13 15 15 50 15V 50 14 AGND B14 AGND 51 AGND 51 B15 B15 52 15 52 53 AGND 2 2 2 4 54 15 54 55 55 56 WF OUT1 56 57 WF OUT2 57 58 WF OUT3 58 59 WF OUT4 59 60 WF OUT5 60 2 45 45 Revision 4 Housing 5 9 2002029 021 Tram ra
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14. INNDIS HOLOSNNOO SINO ILnO 4M AST AST AST AST anow AS AS AS INO VNV 07557100 1185 100 2185 rno Tid 6a ova AS La ova 9a ova lt ova 0a ova N30 1X3 LX3 dn OS 1X8 an qxw dn Nad NG OS LXH AS 91 9T ano 9 9T ano 9T D T D an n a 1 Doran ana ooo 1 1 nn an an an hhhh s m 1 i 0 an an an an 2555555555 un m hhhh n an nan an 555 nor dame ee mm o0 nan 2555555 2555 o ood 1 1 oan 5 Housing 7 24 2002029 021 9 4 Supply evision Tram rac 4 Housing 2002029 021 your notes 8 2 Tram rac 4 Housing Revision A 2002029 021 Tram rac 4A Power Supply Theory of Operation Theory of Operation Overview The AC to DC power supply pn 6123 211 is manufactured for
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16. s DN_RX x EXT_RXD_DN fmi Dp DN RX f EXT SQ EXT gt ml IL r Blinding Timer TRAM net downward data to the auxiliary external port Driver TRAM net downward data from host Carrier transformer and external J10 Driver transformer and external J9 are Sense located on the Interface PCB located on the Interface PCB Blinding Timer TNC_TXD Carrier Data TNC_RXD Receive data and carrier TNC_DEN Sense Select TNC detect signals to the gt 80 152 U3 TRAM net node FIGURE 3 Downward TRAM net Path and Serial Shift Register Data Modules The RAC FPGA U13 uses the PCLK signal as a global clock input PCLK is a 14 7456M Hz clock signal output from the U17 single gate inverter Logic divides the PCLK signal down to 122880Hz and outputs the 123K HZ signal to the four module slots Revision A Tram rac 4A Housing 2002029 021 6 9 Tram rac 4 Processor Acquisition PCB Indicators Controls Indicators Controls The TRAM RAC Processor Acquisition does not contain switches jumpers or adjustable circuits The watch dog circuit may be disabled by removing the 1K ohm resistor R23 connected to the 705 05 The TRAM RAC Processor Acquisition PCB contains six LEDs The functionality of each L E
17. 100 9 016 INO AS 9T Revision A Tram rac 4A Housing 7 20 2002029 021 Schematic Diagram SD800516 001D 4 Interface 4 of 7 SOINONLOHIH 11500 2414 NMVHG TINO 21007 100 4M sino qSH 100 8100 4M 6100 am OTINO am 2 110074 2 2110074 T TINO 4M 7 21 Tram rac 4A Housing 2002029 021 Revision 50800516 0010 ic Schemat Tram rac 4 Interface SOINONLOHIH 11500 HLVd NMVHG IVIINHQTANON san Nd dXI LXS txdN OS LX8 OS IXH ian axa Nad LX3 INLWC3M IXS TLDO 4M FXIUNG IILDO aM IId 0IInO 91n074M 16100 p1n074M 1n0 4M c1no am dsa AST ILDnO ASI xi an Le 2100 AS 91 E an 2 027 679 2185 100 1115 100 5 18 28 6 SHuLVNIGGWOOO IHGV I SHLVNIGHOOD HEYT SHLVNIGHOOD SHLVNIGHOOD 5 of 7 Revision A Tram rac
18. D o 0 d 255555 DATE DRAWN BY ANALOG OUTPUT CIRCUITRY CONFIDENTIAL DB9 BIPOFF DB11 DB10 a _SELI OUT_SELO OUT AAAA AAAAAAA 0 oea 1 wan an an an an 2555555555555 Revision A Tram rac 4A Housing 7 19 2002029 021 Schematic Diagram SD800516 001D 4 Interface PCB 3 of 7 5 uLLWOOGuVNW AULINOYIO 20 47AS 20447AS ANDY sva se 1540 Woo 10064 110061 NI INOST NI ANOD ANOD AS 91 L 01D ON In0 dN55 eru eur LNO ISN WVHI 8 010 2 5 2 5 601297 NI 6 8 6 lt lt NI See
19. 3 THE FOLLOWING COMPONENT S APPEAR ON THE SILKSCREEN BUT ARE NOT USED ON THIS ASSEMBLY C12 C14 C49 C52 C85 C86 C99 C101 CR14 CR40 R16 R32 R55 R79 R86 AND R92 4 INSTALL STANDOFFS ITEM 46 ON SOLDER SIDE OF BOARD 5 J6 LEADS NOT PROTRUDING THROUGH THE CIRCUIT BOARD 15 ACCEPTABLE 3 of 3 Tram rac 4A Housing Revision A 2002029 021 Tram rac 4 Processor Acquisition PCB arts List PN 2004288 001 Parts List PN 2004288 001A Reference Designation Description Number Qty C1 4 22 23 70 97 98 CAP SM TANT 100UF 20 16V LESR 412662 006 8 119 C2 6 8 10 15 25 27 30 SM X7R 0603 1UF 10 411575 002 31 33 42 44 46 51 54 64 65 69 74 75 77 78 81 88 95 103 109 112 114 C3 7 9 11 13 16 17 19 CAP SM X7R 0603 0 01UF 5 50V 411575 012 39 31 35 36 47 48 50 53 55 56 61 63 66 67 71 79 83 84 87 89 90 92 96 100 102 104 105 108 110 113 118 C5 20 21 24 80 82 107 SM X7R 0603 1000PF 5 50V 411575 003 10 111 115 117 18 32 37 41 57 60 72 CAP SM 55 0 1UF 20 50 404370 001 15 91 106 116 26 43 76 SM TANT 3 3UF 10 16V 406883 005 3 34 SM NPO 0603 470 5 50V 411576 018 1 C73 CAP SM TANT 10UF 10 35V 406884 013 1 93 94 5 0603 22 5 50 411576 002 2 CR 13 815 39 841 77 DIODE DUAL SERIES 99 507323 411605 001 75 DS1 2 5 LED SM 1206 R
20. 6 16 Housing Revision 2002029 021 Tram rac 4A Processor Acquisition PCB Part Location Diagram PN 2004288 001A 2 of 3 SOLDER SIDE ASSEMBLY VIEW 92 4 SEE NOTE 4 O O BB amaa o o 0 oo ooo 6609009 00 mn ag 12117 Ui Fn mi 5 ona 988 E 8g C ao Boose 5 e LI LI ses 5 88 m BBB m B 500 9990 28 an B acaraca 5 oy 16600 BBC 88 23636 6 42 4 CEN SEE NOTE 4 ar m B 050811 49 8 88888888 Das lt SEE NOTE 4 lt 000000000000000000000000000000 O0000000000000000000000000000O 2T 18 i QUO C2 C2 C2 C2 C2 C2 C3 C3 CJ ot 4 Revision Housing 6 17 2002029 021 Tram rac 4A Processor Acquisition PCB Part Location Diagram PN 2004288 001A NOTES UNLESS OTHERWISE SPECIFIED ALL RESISTANCE VALUES ARE IN OHMS ALL CAPACITANCE VALUES ARE MICROF ARADS 2 THE BAR SHOWN ON ALL POLARIZED CAPACITORS DENOTES POSITIVE TERMINAL
21. Ground The Tram rac chassis power supply requires a 120 V 50 60 Hz main supply 240 V may be required for international systems Using a multimeter confirm that the AC outlet is wired properly This consists of two steps 1 Measure the voltage between the three connections in the outlet and 2 Measurethe ground neutral loop resistance A standard 120 VAC 240 VAC outlet consists of three connections m Line m Neutral and m Ground Line and neutral are the rectangular openings with neutral being the wider of the two Ground is the third opening and is either round or horseshoe shaped Select the AC voltage scale on the multimeter easure the voltage from line to neutral line to ground and neutral to ground A correctly wired should have these readings m Lineto neutral 120 VAC or 240 VAC m Lineto ground 120 VAC 240 VAC m Neutral to ground 3 VAC Readings other than these indicate improper wiring Have the outlet checked by a qualified electrician Ground Neutral Loop Resistance Check After you have confirmed that the wiring is correct measure the ground neutral loop resistance CAUTION DoNOT check the ground neutral loop resistance unless the outlet is wired correctly 1 Select the milli ohms scale on the multimeter 2 Measure across the power cord neutral and ground 3 Measure from the ground lug at the rear of the Tramscope or Remote Display and any exposed metal fan guard
22. sent to all slots so take care that only one module sources these signals All invasive blood pressure signals are produced at a 24 415mV mm Hg scale regardless of whether they are acquired by the Tram or discrete parameter module Scaling and zero level offset is accomplished by the data acquisition microprocessor software When you use a discrete parameter blood pressure input module the blood pressure zero level offset has a range of 150 mm Hg The 6 dB bandwidth of the analog output circuitry in the Tram rac 4 housing is 120Hz 5 4 Tram rac 4 Housing Revision 2002029 021 Tram rac Housing Theory of Operation Data Communication Optional Power Supply Communication of patient data to other devices within the bedside care area occurs with a patient monitor using the Tram net communication network The Tram rac 4 housing contains an intermediate internal Tram net hub that gives access to the Tram rac 4 processor each of the four module slots and one external Tram net device such as a remote control Tram net interface adapter or another Tram rac housing You can havethe Tram rac 4 housing equipped with a power supply for applications where one or more of the following conditions apply m TheTram rac 4A housing is located more than 20 feet from the monitor m TheTram rac 4A housing is operating an environment with high electrical noise m Another Tram rac housing without a power supply is
23. The resistance between the ground and neutral connections must be less than 100 milli ohms If not have the outlet checked by a qualified electrician 4 4 Tram rac 4A Housing Revision A 2002029 021 Troubleshooting Wall Receptacle Check Check Power Cord Make sure the power cords being are good A failure the power cord caused by pulling on the cord to disconnect it from the wall outlet is very common If in doubt test for continuity through each wire of the cord Check to see that the line neutral and ground wires are all connected firmly to the plug and that they are not shorted together Rewire the plug to correct this problem Revision A Tram rac 4A Housing 4 5 2002029 021 Troubleshooting General Fault Isolation General Fault Isolation First Things to Ask If the unit is not working properly save yourself some time troubleshooting by asking yourself these basic questions m s the power cord connected Istheunitturned ON m Does the display LED illuminate m the communication cables firmly connected m Were there any changes in the use location or environment of the equipment that could cause the failure m Hastheunit been modified any way either in software hardware m s operator error the cause of the problem Try to repeat the user s scenario exactly and compare that to the proper operation of the equipment Check the operator s manual as necessary
24. 6 7 Indicators and 6 10 Input and Output Connectors 6 11 Module Interface 1 4 6 11 Interface CRUS 6 14 ISP Serial EEPROM Interface 6 6 15 Part Location Diagram PN 2004288 001 6 16 Parts List PN 2004288 001 6 19 Schematic Diagram PN 2004289 001 6 21 Revision A Tram rac 4A iii 2002029 021 Tram rac 4A Interface 7 1 Theory of Operation 7 3 eM MM E IP LM M E 7 3 Block Diagrali atq kalpaqa babi hamoq osa ae 7 3 Indicators and Controls 7 8 Input and Output Connectors 7 9 Part Location Diagram PN 800516 001J 002J 7 13 Parts List PN 800516 001 7 14 Parts List 800516 002 7 16 Schematic Diagram PN SD800516 001D 7 18 Tram rac Power Supply 8 1 Theory of Operation 8 3 OVelVIeW
25. 6583 T NO 0X1 1x3 66AVd 7183 dn 05 1 3 66 0983 1x3 66 1 5182 30 1X3 1985 dn 0X1 1X3 66AYd 1 9182 T NO OS 1X3 66 1 2983 1 VV AA V NO OXU 1X3 i66 AVE z LLU T VIVO 1 1835 20 5 r 1010 2 0 LT 4 tna 2 0 ILT 4 2 ZLI 4 1610 2 0 ELT 4 1710 2 0 691 4 OLT 1910 2 0 191 lt 110 2 0 891 4 1810 2 0 791 1630 2 0 991 10110 2 0 291 1700 2 0 9 lt lt NO N30 1X3 611 lt NU OXL 1X3 LLT d N30 1X3 681 d 0X1 1X3 181 135 1 2 2 135 jM 2 0135 1135 NL 213 3u 950 7 N3389 950 40443 404 48011 404 UD yr 001 00TH 9018 X0 uonisinby 404 45014 AS 100112971 900M 5 0 59 r SV0 2 INI ONL 221 4 INL IL A H 5 0 911 Herr lt ZHHEZT d 52 2 XNV18 2 d EET d ilvugrvo d LS 4 HJ1 Vivo GOW d6TT I 31 VIVO 00 d LE 1n0 VLVO GOW 271 211015 10 d 9 5 sin LOOLLIHYL sees IL S xD NL gr NL 321015 TON d 7 L00LL2H7L sin 11015 106 d 72101510474 61075 IOW d EI0IS TON d 8 6 sin LO0LLIHYL 7101 IOW d Fr IH 00 d 71015 10 d or stn 3 ZH N3 d 55 lt EHO 00H d 77 c 2H3 N3 00H d OE c SH
26. your notes 3 2 Tram rac 4 Housing Revision A 2002029 021 Maintenance Controlling Electrostatic Discharge Damage Controlling Electrostatic Discharge Damage Guidelines All components of the Tram Critical Care Monitoring System make extensive use of CMOS components CM OS components are used because they are more immune to noise and consume less power than standard TTL NMOS components H owever by their nature CM OS components are more vulnerable to electrostatic discharge ESD damage than other semiconductors ESD damages usually a subtle weakening of semiconductor junctions can range from corruption of digital memory to catastrophic failure rendering a component or a number of components permanently unusable Although it is more common for CMOS components to fail from ESD damage no semiconductor device is completely safe from ESD damage The inputs and outputs of all of the components are protected from ESD damage so they are no more susceptible to ESD damage during normal operation than any other device However when you service components you expose the components to several sources of static electricity ranging from human hands to improperly grounded test equipment F or this reason it is recommended that all service workstations be as static free as possible The following guidelines can help make your workstation more resistant to the damage that can be caused by static electricity m Discharge any
27. April and so on manufactured Hellige to marketing specification E May R refurbished equipment F June S special product G July documented under H August Specials part numbers J September U upgraded unit K October L November M December Warranty 1 year 1 8 TRAM RAC 4A Revision A 2002029 021 2 General Information evision Tram rac 4A Housing 2002029 021 your notes 2 2 Tram rac 4 Housing Revision A 2002029 021 General Information Equipment Overview Equipment Overview Tram rac Theory The Tram rac housing remote acquisition case acquires the patient data for the patient monitor It provides an interface between the patient monitor and a Tram module or discrete parameter module An interface cable provides the communications media between the Tram rac 4 and the host monitor If the Tram rac 4 is an unpowered pn 900031 005 the cable provides 16 5V power If a Tram rac housing is located more than 20 feet from the patient monitor the Tram rac housing needs its own power supply NOTE For an equipment overview of other products used in the Tram Critical Care Monitoring system refer to Table 2 Service Documents on page 1 4 Communication options and Tram net communication are explained in Tram net Communication on page 2 4 There are three Tram rac housings available for the patient monitor m Tram rac 2 housing which houses
28. C16 C26 C30 C34 C42 and C49 with a 249 ohm current limiting resistor R7 R11 R18 R23 R29 R35 R39 and R48 at the input and a voltage follower operational amplifier U4A U5A U8A U11A circuit at the output The operational amplifier circuit provides a high impedance to the hold capacitor so that it has a negligible effect on the capacitor s charge between refresh samples by the DAC The series resistor along with the on resistance of the multiplexer U 10 limit the charge discharge current of the hold capacitor to damp its response to step changes in voltages due to the DAC The dwell time for each sample as determined by the DAS control processor on the Tram rac4A Processor Acquisition PCB must be at least ten times longer than the R C time constant of 3 8 us maximum A two pole Butterworth low pass filter using U4B U5B U8B and U11B is employed to remove the high frequency steps caused by the DAC as it produces successive samples of the analog waveform The low pass cut off frequency of the filter is 120 Hz which is half the sample rate of the analog waveform The offset error attributable to the low pass filter is typically 4 mV 10 mV maximum The maximum gain error is 2 due to the use of 1 tolerance resistors to set the gain Five analog signals which typically are produced by a Tram module inserted the Tram rac 4A housing are included with the analog outputs generated by the Tram rac 4A housing on t
29. Safety Information Equipment Symbols Bem lt The following symbols appear the equipment NOTE Some symbols may not appear on all equipment ATTENTION Consult accompanying documents before using the equipment In Europe this symbol means dangerous or high voltage In the United States this symbol represents the caution notice below To reduce the risk of electric shock do NOT remove cover or back R efer servicing to qualified personnel Defibrillator proof type CF equipment type CF equipment is specifically designed for applications where a conductive connection directly to the heart is established The paddles indicate the equipment is defibrillator proof Defibrillator proof type BF equipment type BF equipment is specifically designed for applications intentional external and internal application to the patient excluding direct cardiac application Type BF equipment is type B equipment with an F type isolated floating part The paddles indicate the equipment is defibrillator proof B equipment type B equipment is suitable for intentional external and internal application to the patient excluding direct cardiac application Equipotentiality Alternating current AC Power 1 ON O 0FF Fuse Indicates where to press to open the door on the Series 7160 Direct Digital Writer Revision TRAM RAC 4A 1 7 2002029 021 Introduction Serv
30. Tram rac 4 housings with the gold plate below the module slots Three Board version A service kit is available to repair existing Tram rac 4As with the gold plate See Tram rac 4 Housing Service Kits page 3 12 for the available kit Users of this manual are expected to have a strong background in electronics including analog and digital circuity with microprocessor and micro controller architecture Revision A TRAM RAC 4A 1 3 2002029 021 Introduction Related Manuals Related Manuals Check these documents if you need additional information about related producets Table 2 Service Documents Part Number Name 404183 006 Tram rac Chassis Service Manual For Tram rac 3 and Tram rac 4 Housing 404183 048 Tramscope 12C Monitor Service Manual 404183 094 Tramscope 12 Monitor Service Manual 404183 096 Tram rac Housing Service Manual 404183 150 Modular Patient Monitor Accessories Manual 404422 001 Tram 100 600 Modules Service Manual 404422 065 Tram 100 850 A amp SL Modules Service Manual 405040 002 Centralscope 12 Central Station Service Manual 405040 018 Centralscope 12C Central Station Service Manual 405040 117 Modular Centralscope Central Station Service Manual 414993 001 Solar 7000 8000Niew P atient Monitor Service Manual 414993 007 Solar 7000 Patient Monitor Data Manual 2000701 001 Solar 8000M Patient Monitor Service Manual 421669 001 Solar 9500 I
31. of this chapter These instructions are intended for for Tram rac 4A units with the optional power supply Listed below arethe safety tests m Wall receptacle test m Ground Earth integrity m Ground Earth leakage current tests and m Enclosure leakage current tests Checkout procedures safety tests and leakage tests are described in the Maintenance chapter of the appropriate patient monitor See Table 2 Service Documents on page 1 4 for the appropriate manual NOTE Perform the safety tests for the Tram modules or discrete parameter modules used in the Tram rac 4A according to the directions in their respective service manuals If a Tram rac 4A under test fails the leakage tests call Tech Support for assistance See How to Reach Us 3 6 Tram rac 4A Housing Revision A 2002029 021 Maintenance Electrical Safety Tests Test Conditions Test Equipment Wall Receptacle Test All electrical safety tests may be performed under normal ambient temperature humidity and pressure conditions A Leakage Current T ester is needed Before starting the tests the wall receptacle from which the device will get electrical power must be checked T his test checks the condition of the wall receptacle to ensure correct results from leakage tests For international wall receptades refer to the internal standards agencies of that particular country U se a digital multimeter to ensure the wall recepta
32. single Tram module two discrete modules m 2A housing which houses a single Tram module or two discrete modules m 4A housing which houses a Tram module two discrete parameter modules or no Tram module and four discrete parameter modules NOTE If your system contains Tram rac 4 4A housing it houses only two discrete parameter modules and Tram module in the top slot This manual addresses only the Tram rac 4 Revision Tram rac 4A Housing 2 3 2002029 021 General Information Equipment Overview Tram net Communication Tram rac 4 Housing Tram net communication permits connection to the Tram rac housing and other bedside peripherals The Tram net communication is one form of local area network that provides a data and power link from the monitor to peripheral devices The connector makes a communication processor available for the peripheral devices The Tram net controller processor is built into the communication PCB assembly which frees up the main processor in the monitor To avoid confusion consider Tram net communication as a small area network SAN contained in one room or at the patient bedside more details about communication networks refer to the appropriate monitor service manual Shown below is Tram rac 4A housing with a Tram module and one and one BP Dual Temperature module inserted The Tram rac 4 housing has thr
33. 001 This kit can be ordered as an aid to troubleshooting a Tram rac 4 chassis without a power supply Table 7 Tram rac 4 Service Kit Description Part Number Qty 4 Processor Acquisition P CB 2004288 001 1 4 Interface P CB 800516 001 1 PN 2006854 001 This kit can be ordered as an aid to troubleshooting 4A chassis with a power supply Table 8 4 Supply Service Kit Description Part Number Qty 4 Processor Acquisition P CB 2004288 001 1 4 Interface P CB 800516 002 1 Tram rac 4 Power Supply 6123 211 1 PN 2006855 001 Repair Kit 3 to 2 Board Conversion This kit can be ordered to repair an older Tram rac 4A with the gold plate below the module slots Use this kit to repair an older Tram rac 4A if the 800514 or the 800518 PCBs are damaged The 2004288 PCB replaces the functions on the two older PCB assemblies The new light pipe and silver bottom plate allow for the front bezel LED to be visible Table 9 Tram rac Repair Kit 3 to 2 Board Conversion Description Part Number Qty 4 Processor Acquisition P CB 2004288 001 1 Tram rac4A Power Light Pipe 2004496 001 1 Tram rac 4 Bottom Cover 400766 004 1 Grommet Non metallic 3 16 inch ID 2006427 001 1 CD Service Manual 2002029 025 1 3 12 Tram rac 4A Housing Revision 2002029 021
34. 006 4 of 5 PCD ASSEMBLY ROTATED 180 FOR CLARITY FD DETAIL SCALE _2 J 5 18 Tram rac 4 Housing 2002029 021 Revision A Tram rac 4A Housing Exploded View 900031 005 006 5 5 REAR VIEW REAR VIEW W Q POWER SUPPLY W POWER SUPPLY 4 ge quU fo S REF REMOVE KNOCK OUT PLATE PRIOR TO ATTACHING FIND NUMBER 83 POWER SUPPLY 4 PLACES POWER SUPPLY ASSEMBLY ROTATED 180 FOR CLARITY Revision A Tram rac 4A Housing 5 19 2002029 021 Tram rac 4A Housing Parts List PN 900031 005 006 Parts List PN 900031 005N 006N Description Number Qty Designation 19 LABEL BLANK 2 6IN X 4IN 404525 006 1 22 SCREW 100 FLH 4 40 X 25 GRAY For PN 900031 005 Only 4716 833 6 SCREW 100 FLH 4 40 X 25 GRAY For PN 900031 006 Only 4716 833 10 24 SCREW BDGH 4 40 X 1 4 45074 408 4 25 SCREW SEMS PH 10 32X3 8 For PN 900031 006 45018 906 1 33 GASKET EMITRAMRAC 404874 001 4 34 CLAMP CABLE CUSH 31 ID For PN 900031 006 Only 4528 106 1 45 LABEL SYMBOL EQUIPOTENTIAL 70437 002 1 46 WASHER LOCK SERRATED F M 6 400041 001 1 47 PLUG EQUIPOTENTIAL 400040 001 1 51 LABEL UL LISTED MEDICAL 408230 011 1 52 LABEL UL LISTED M
35. 200 OHM 1 1 16W 410334 044 1 R107 RES SM 0603 750 1 410334 099 1 R 26 28 RES SM CER 0603 24 9K 1 1 16W 410334 147 3 01 SM CMOS 62256F LP 3202 256 1 02 SM PROC 405329 002 1 U3 IC COMM CONTROL 80C152J B PLCC 400368 001 1 U4 IC SM OR GATE TC7S 32F 3047 032 1 U5 IC SM PWR SPLY MON MAX705 410066 001 1 U6 IC REG SM LM78L05ACD 400726 001 1 U7 IC SM REFERENCE 2 5V 1 50PPM 420084 001 1 U8 IC SM 12 BIT ADC AD7895 419736 001 1 U9 IC SM OP AMP MIC6211 SOT 23 420995 001 1 U10 IC SM LDO REG 3 3V MIC520 420140 003 1 011 12 IC SM 8CH MUX LOW PWR 06408 402024 001 2 913 IC FPGA SM 00 208 3 2 5 3 3 208PQFP 2005003 001 1 014 EEPROM SM TRAM RAC FPGA VIA 2005582 001 1 015 HCT SM BUFFER 74HCT7007 5014 2006707 001 1 016 IC SM LDO REG 2 5V 180MA 5207 422635 002 1 017 IC SM 5 S TRIG INV 7514 416170 001 1 018 IC PQFP MICROCOMPUTER 80C31BH 402610 002 1 U19 PEPROM RAC DAS PROC 405330 003 1 Y1 XTAL SM 14 7456MHZ 100P PM 414847 002 1 STANDOFF PCB MT 143DIA 75L 411134 001 4 SCHEM TRAM RAC 4A PROCESSOR ACQUISITION 2004289 001 See Schematic Diagram PN 2004289 001 on page 6 21 CKT BD TRAM RAC 4A PROCESSOR ACQUISITION 2004287 001 See Part Location Diagram PN 2004288 001A on page 6 16 6 20 Tram rac 4A Housing Revision A 2002029 021 2004289 001 D ic Schemat Tram rac 4 Processor Acquisition P
36. 4 6 Tram rac 4 Housing Revision A 2002029 021 Troubleshooting General Fault Isolation Visual Inspection A thorough visual inspection of the equipment can save time Small things disconnected cables foreign debris on circuit boards missing hardware loose components can frequently cause symptoms and equipment failures that may appear to be unrelated and difficult to track Taketime to make all the recommended visual checks listed in the visual inspection chart below before starting any detailed troubleshooting procedures Table 1 Visual Inspection Chart Area Look for the following problems 10 Connectors and Cables m Fraying or other damage m Bent prongs or pins m Cracked housing m Loose screws in plugs Fuses m Type and rating Replace as necessary Interface Cables m Excessive tension or wear m Loose connection m Strain reliefs out of place Circuit Boards m Moisture dust or debris top and bottom m Loose or missing components m Burn damage or smell of over heated components m Socketed components not firmly seated m PCB not seated properly in edge connectors m Solder problems cracks splashes on board incomplete feedthrough prior modifications or repairs Ground Wires Wiring m Loose wires or ground strap connections m Faulty wiring m Wires pinched or in vulnerable position Mounting Hardware m Loose or missing screws or other hardware especially faste
37. 4 waveform A 8 AGND 0v O ANALOG GROUND Signal return for WF OUT6 through WF 00113 9 WF Analog 10V O OUTPUT NO 1 Analog waveform output number 1 typically waveform Tram ECG 10 WF OUT3 Analog 10V O OUTPUT NO 3 Analog waveform output number 3 typically waveform Tram ECG V 11 WF 0UT51 Analog 10V O WAVEFORM OUTPUT 5 Analog waveform output 1 number 5 slot 2 waveform or Tram BP4 or RESP 12 WF 0017 Analog 10V O WAVEFORM OUTPUT NO 7 Analog waveform output 1 number 7 slot 1 waveform 13 WF Analog 10V O OUTPUT NO 9 Analog waveform output B number 9 slot 2 waveform B or Tram BP2 or SPO2 14 WF OUT112 Analog 10V O WAVEFORM OUTPUT 11 Analog waveform output 1 number 11 slot 3 waveform 15 WF 007132 Analog 10V O WAVEFORM OUTPUT 13 Analog waveform output number 13 slot 4 waveform B Shell CGND 0v O CHASSIS GROUND Chassis shield ground 7 12 Tram rac 4A Housing Revision A 2002029 021 4 Interface PCB P art Location Diagram 800516 001 002 Part Location Diagram PN 800516 001J 002J Le O
38. 4A Housing 2002029 021 7 22 Tram rac 4A Interface PCB Schematic Diagram 50800516 0010 SOINONLOHIH ALLENOUVN 2414 NMVHG IVIINHQTANON LO P La T 52 6 SAIVNIQHOO SWddawd SHLVNIGHOOD 540484 SHLVNIGHOOD 54484 SHLVNIGHOOD 540484 6 of 7 7 23 Tram rac 4A Housing 2002029 021 Revision 50800516 0010 0 ic Schemat Tram rac 4 Interface 7 of 7 SOINONLOHIH 11500 2414 TIWNOIS HOLOSNNOO TIWNOIS HOLIOSNNOO qN52 TINO ILLnO 4M 6100 4M LINO 4M SInO 100 4M 1100 4M crino a OTINO a 810074 910074 100 am 07 NIN qN52 qN52 XIUNd 1007 679 XIUNd In07A8 91 x an qN52 qN52 NI GN9 AS 91 x 91 NI GN2 XITan AS 9T AS 9T 91 AS ASI AST ANOO AS AST AST PLICITID ST TIC T TIL 0T IID 16 110 8 11 e 9 112 6 IID IID I IID trotar 6 01 8 016 29 012 5 0 2 22 012 0 6 6 6 6 8 6 6r 18 60 6
39. 6 Tram rac 4A Housing Revision A 2002029 021 Tram rac 4A Power Supply Parts List PN 6123 211 Parts List PN 6123 211A NOTE Table 5 Main PCB GE Medical Systems Information Technologies part numbers not given because this is manufactured by a vendor Reference Designation Description Part Number Qty C1 0 8 250V 1 C2 0 33uF 250V 1 4 15 680 20 250 3 5 6 Cap Cer 470g F 200V 2 C7 Cap Cer 25V 1 C8 Cap 0 47UF 20 50V 1 C10 11 12 Cap Cer 1000UF 25V 1 C13 10uF 25V 1 14 0 11 20 50V 1 C16 Cap LOOpF 10 1KV 1 17 Cap 0 001UF 10 1 1 01 Bridge Rectifier Diode 600V 1 D2 3 Diode 1A 600V BYV26C 1 D4 Diode 1A 100V MUR110 1 D6 Diode 15 200V MUR1520 1 D7 Diode Zener 18V 1 2W 1N5248B 1 1 2 Fuse Assembly 2 1 NOTE m This is not a field serviceable component J1 20 AWG 1 11 Inductor 28mH 1 L2 3 Inductor 2881 H 2 L4 Inductor Transformer 75W 1 L5 Inductor 4 1 L6 Inductor Transformer Gate 1 23mH 1 1 Circuit Board P CB 1 See Part Location Diagram PN 6123 211 M3 4 5 6 Switch Assembly Not Shown 4 M7 8 Sleeve Teflon 1 M9 Screw PNH Phillips 6 32 x 3 8 1 10 Nut
40. GE Medical Systems Information T echnologies by a vendor T he parts list does not supply part numbers but a description is provided for each vendor part NOTE The fuse assembly is not a field serviceable component Revision 4A Housing 8 3 2002029 021 Tram rac 4 Power Supply Indicators and Controls Indicators and Controls Listed below is the function of any indicators switches jumpers or controls located on the power supply There are no calibration procedures because the power supply is not field repairable Table 1 Adjustments LED Color Signal Name Function Normal Condition R112 16 5 Voltage 16 5 DC Voltage Setin Factory Table 2 Switches Symbol Signal Name Function Normal Condition SW1 Power Power ON OFF ON for normal operation 8 4 Tram rac 4A Housing Revision A 2002029 021 Tram rac Power Supply Input and Output Connectors Input Output 5 The following tables contain all connections to the Tram rac4 Interface PCB Each signal includes such information as whether it is an input or output the nominal voltage range for each signal the type of signal and the maximum frequency the signal may have This is organized by connector Table 3 Connector P1 15 Pin Connector to Tram rac4 Interface PCB Pin Signal Name Signal Level Signal Descrip
41. GROUND Power return for 16 5V supply 2 4 6 8 10 12 16 5V 16 5V 0 16 5 POWER 16 5V power input for the module slots 13 EXT RXD DN TTL O EXTERNAL TRAM NET DOWNWARD PATH RECEIVE DATA This signal is the receive data for the external downward path Tram net channel 14 EXT SQ DN TTL 0 EXTERNAL TRAM NET DOWNWARD PATH SQUELCH DATA This signal is the squelch data for the external downward path Tram net channel 15 EXT TXD UP TTL EXTERNAL UPWARD PATH TRANSMIT DATA This signal is the transmit data for the external upward path Tram net channel 16 EXT DEN UP TTL EXTERNAL TRAM NET UPWARD PATH DRIVER ENABLE This signal is the active low driver enable for the external upward path Tram net channel 17 EXT RXD UP TTL O EXTERNAL TRAM NET UPWARD PATH RECEIVE DATA This signal is the receive data for the external upward path Tram net channel 18 EXT SQ UP TTL O EXTERNAL TRAM NET UPWARD PATH SQUELCH DATA This signal is the squelch data for the external upward path Tram net channel 19 EXT TXD DN TTL EXTERNAL DOWNWARD PATH TRANSMIT DATA This signal is the transmit data for the external downward path Tram net channel 20 EXT DEN DN TTL EXTERNAL DOWNWARD PATH DRIVER ENABLE This signal is the active low driver enable for the external downward path Tram net channel 21 DAC TTL D A CONVERTER DATA The 12 bit data for the analog 22 DAC D1 25 DAC D4 26 DAC D
42. INVERTED TRANSMIT Inverting transmitter output to the lower level device or hub 7 Not Used 9 DN_TX Differential DOWNWARD PATH NON INVERTED TRANSMIT Non inverting transmitter output to the lower level device or hub Shell CGND_OUT OV CHASSIS GROUND OUT Shield ground from the Tram rac 4A housing to the lower level device or hub Revision Tram rac 4A Housing 5 13 2002029 021 Tram rac 4 Housing Input and Output Connectors Table 6 Connector J11 15 Pin Analog Output Connector NOTE The Tram module must be in the top slot to receive Tram signals listed below dual BP discrete parameter modules waveform is from the right connector and waveform is from the left connector NOTE The superscript number 1 indicates that this signal remains unchanged after entering the Tram rac 4A housing and is controlled by Tram module software NOTE The superscript number 2 indicates that this signal is generated by the DAC on the interface PCB assembly Pin Signal Name Signal Level Type Signal Description 1 WF OV O WAVEFORM RETURN Signal return for WF_OUT1 through WF_0UT5 2 WF 01121 Analog 10V O OUTPUT 2 Analog waveform output 7 number 2 typically waveform Tram Trace 1 3 WF_0UT4 Analog 4 10V O WAVEFORM OUTPUT 4 Analog waveform output number 4 typ
43. Keps Hex 6 12 x 1 4 1 Revision Tram rac 4A Housing 8 7 2002029 021 Tram rac 4A Power Supply Parts List PN 6123 211 Table 5 PCB Medical Systems Information T echnologies part numbers not given because this part is manufactured by a vendor Reference inti Designation Description Part Number Qty M21 Ferrite Bead on D2 1 22 23 Insulator 1 24 Plastic 1 1 51 7 Assembly 16 5 7 1 See Connector P1 15 Connector to 4 Interface P2 51 8 Assembly Input 3 1 See Connector P2 3 Pin Connector to AC Power Source Q1 2 Transistor FET 8A 500V IRF840 2 Q3 SCR 8A 50V MCR72 2 1 81 180 5 1 2W 1 12 3 47 5 2 2 R4 Res 20 Ohm 5 1 4W 1 R5 Res 47K 5 1 4W 1 R6 Res 0 24 Ohm 2 2W 1 R7 Res 100 5 1 2W 1 R8 Res 10 Ohm 5 1 2W 1 R9 Res 44 2K 1 1 4 1 1 Thermistor 1 T2 Thermistor 100 C 1 X1 Daughter P CB Details listed below 1 See Part Location Diagram 6123 2114 21 Varistor Metal 280 22 1 Inductor 20 18 1 Inductor 20 18 1 8 8 Housing Revision 2002029 021 Tram rac 4A Power Supply Parts List P
44. Schemat Tram rac 4A Processor Acquisition PCB 3 of 9 6 30 E _ 13365 AOS 75 38V 58012 4 2 11 77 100 6827002 M38WDN WALI SOVUVIOUIIN NI SANIVA 32NVIDVdV2 11 01151003 805532084 S3HID0 1ONHO31 541545 TYOIGHN HD 145 UO yDdJ0EMT 445 UO 251208 OL lt 1SH INL 0311V1SNI LON M9T T AT SWHO NI SINIYA 32NVISIS3H 11 Z 3 112 3 V YSIW3LSY 03 01104 TYNDIS TV 031312345 351 83 10 SS31Nn 2 2 puo WONd33 vDd3 A TON gy A0v3u EZEON 7114 25929 lt vivo ovivo 100 2855002 N3 YIS 4 E x N3 U3s 5204 XN3 HIS 304 3800 11180 osa 5 m 758 4 3130 lt gt 1084 39 0 558 AEE E ZZEJN TZEJN OZEIN lt 913SW 3003402 T13SW 4 snivis 3 3d0001 oviva 914N02 53271 30 d 540 0307 508551 lt NET 3084 INT gt lt gt gt SUV 570 3137030 ISU 35 3138 158 3SV313H 001 1581 Sul Ovi or
45. Signal Signal Level Signal Description 1 7 8 Shell GND OV GROUND Power return for 16 5V supply and chassis ground reference 2 9 15V 15V 15V POWER 15 power 3 10 15V 15V 15V POWER 15 power 4 11 AGND 0v ANALOG GROUND 5 V 15 V and 15 V power return 5 12 5V 5V 45V POWER 5 V power 6 GND_CONV OV CONVERTER GROUND 16 5 V power return for DC DC converter 13 16 5V_CONV 16 5V CONVERTER 16 5V POWER 16 5 power for DC DC converter 14 15 16 5V 16 5V 16 5V POWER 16 5 V power 7 10 Tram rac 4A Housing Revision A 2002029 021 Tram rac 4 Interface PCB Input and Output Connectors Table 4 Connector J9 9 Pin Tram net Connector to Patient Monitor Pin Signal Name Signal Level 10 Signal Description 1 UP_TX Differential 0 UPWARD PATH NON INVERTED TRANSMIT Non inverting driver output to the upper level hub 2 8 GND_IN OV GROUND IN Power return for 16 5V supply into the Tram rac housing from the upper level hub 3 UP_TX Differential 0 UPWARD PATH INVERTED TRANSMIT Inverting driver output to the upper level hub 4 6 16 5V_IN 116 5 16 6V POWER 16 5 V power supply into the Tram rac housing from the upper level hub 5 DN_RX Differential DOWNWARD INVERTED RECEIVE Inverting receiver input from
46. When TNC_PROM is low during FLASH memory reprogramming code is executed from the 32K byte SRAM The FPGA multiplexes the correct memory control signals based on the state of the DAS PROM_DELAY and TNC_PROM _DELAY signals Revision A Tram rac 4A Housing 6 7 2002029 021 Tram rac 4 Processor Acquisition PCB Theory of Operation Processor Memory Map Decode The RAC FPGA provides memory map decoding logic for the 80C31 and 80C 152 processors Each processor address bus is latched the FPGA andSRAM FLASH and dual port memory control signals are generated Several registers and the associated decode logic are present in the FPGA for use by the 80C31 The 80C31 processor can access the ADC result DAC output value control registers 1 and 2 analog 1 0 select and three status registers And Shift Register Communication The RAC FPGA U 13 implements a six port TRAM net hub and Serial Shift Register communication logic Figures 2 and 3 show the RAC 4A TRAM net upward and downward data paths Six TRAM net upward data paths are combined into one port that transfers TRAM net data to the host monitor SOLAR 8000 8000M 9000 9500 T he six upward bound ports originate from the four RAC 4A module slots J 1 J 4 the 80C152 communications processor and the external TRAM RAC 4A auxiliary connector J 10 Each of the 4 module slots are enabled when the associated TRAM net enable signal input TN_ENA_SL
47. a satisfactory maintenance schedule may cause undue equipment failure and possible health hazards Inspection Inspect the Tram rac 4A on a regular basis F ollow these guideline when you inspect the equipment m Inspect the equipment for obvious physical damage and replace damaged items m Inspect all connectors for bent pins or prongs Replace or repair any bad cables or connectors NOTE Only qualified service personnel should replace the connectors m Inspect all cable insulation Qualified service personnel should repair or replace damaged or deteriorated cables m Inspect fuses 3 4 Tram rac 4A Housing Revision A 2002029 021 Maintenance Maintenance Schedule General Cleaning Exterior Cleaning Clean the Respiratory Mechanics Module on a regular basis Clean the exterior surfaces of the device with a dampened lint free cloth Use one of the following approved solutions m ammonia diluted m Cidex m sodium hypochlorite bleach diluted or m mild soap diluted To avoid damage the equipment follow these rules CAUTION Failuretofollow these rules may melt distort or dull the finish of the case blur lettering on the labels or cause equipment failures Always dilute the solutions according to the manufacturer s suggestions Always wipe off all the cleaning solutions with a dry cloth after cleaning Never use wax containing a deaning substance Never pour water or any deaning solution on the
48. already connected to the monitor or m The power supply capability has been exceeded for another reason Revision Tram rac 4 Housing 5 5 2002029 021 Tram rac 4 Housing Theory of Operation Diagram Control Signals This block diagram presents the signals paths between the two circuit boards inside the Tram rac 4 housing F or more detailed information refer to the theory of operation for each PCB presented below 30 Pin Module Connectors J1 J4 Analog Interface Digital Interface DAS DAS TRAM net Hub and Slot 1 Microprocessor EEPROM Serial Shift Register aM 80C31 U18 32Kx8 U19 Communication Slot2 EN IHR DAS_ADDRESS Dip Switch DAS ID and Bootfail Logic 013 Analog Multiplexers 011 012 14 7456 2 Crystal amp Buffer 1 017 Control Logic fo Two Status Status Register Read Reset Watchdog Most PCB Registers 9 05 Functions 013 Buffer Offset Correction 2s Comp To Unsigned ADC State Dual Port RAM 2Kx8 Machine Control zu State Machine Control DAC Data Register Write 12 bits U13 2 5V Reference U7 6 Diagnostic LEDs Tram Net Comm TNC TNC SRAM 051 056 iciti Microprocessor EEPROM 32Kx8 U1 nn FOB 80 152 03 32Kx8 U2 DC to DC Converter U1 Buffer Amplifier U9 FPGA Reset
49. and Configuration U13 FPGA Configuration EEPROM U14 FPGA Configuration Download Header 10 TNC_ADDRESS 16 5V 15 5V TNC_DATA TRAM RAC 4A Processor Acquisition PCB 2004288 001 D A Converter U7 Analog Multiplexer TRAM net U10 Isolation and Buffers Analog Buffer and Filters U5 U4 U8 Turn On Circuits TRAM RAC 4A Interface PCB 800516 001 un powered 800516 002 powered J8 populated Power Supply TRAM netOut TRAM net In Analog Out 15 pin Opt Aux 9 pin 9 pin Host 15 pin J8 J10 J9 J11 5 6 Tram rac 4 Housing Revision A 2002029 021 Tram rac 4 Housing Indicators and Controls Indicators and Controls Listed below is the function of the LE D located on the Tram rac 4 housing T here are no other controls or switches and no calibration procedures F or details on indicator functions see Tram rac 4A LED Troubleshooting Chart on page 4 8 or Indicators and Controls on page 6 10 Table 1 LED Function LED Color Signal Name Function Normal Condition Green Power Indicator Indicator of proper operation ON when power applied Revision A Tram rac 4A Housing 5 7 2002029 021 Tram rac 4 Housing Interconnection Diagram 900031 Interconnection Diagram 900031 lot 2 INTERFACE PCB MODULE PROCESS
50. communication low logic level indicates Tram net capability a high logic level indicates synchronous serial shift register communication support only B12 5V 5V O 5 digital power 13 B13 15V 15V O 15 analog power 14 15 15V 15V O 15 analog power 15 B15 AGND OV O Analog power return Table 3 Connector J8 15 Connector to Optional Power Supply Pin Signal Name Signal Level Signal Description 1 7 8 Shell GND OV GROUND Power return for 16 5V supply and chassis ground reference 2 9 15V 15V 15V POWER 15 power 3 10 15V 15V 15V POWER 5 V power 4 11 AGND OV ANALOG GROUND 5 V 15 V and 15 V power return 5 12 45V POWER V power 6 GND_CONV OV CONVERTER GROUND 16 5 V power return for DC DC converter 13 16 5V_CONV 16 5V CONVERTER 16 5V POWER 16 5 power for DC DC converter 14 15 16 5V 16 5V 16 5V POWER 16 5 V power 5 12 Tram rac 4A Housing Revision A 2002029 021 Tram rac 4 Housing Input and Output Connectors Table 4 Connector J9 9 Pin Tram net Connector to Patient Monitor Pin Signal Name Signal Level 10 Signal Description 1 UP_TX Differential 0 UPWARD NON INVERTED TRANSMIT Non inverting driver output to the upp
51. eccl Menor Wd 8 3 Indicators and Controls 8 4 Input and Output Connectors 8 5 Part Location Diagram PN 6123 211 8 6 Parts List PN 6123 211 8 7 Schematic DiagramPN 506123 211 8 10 iv Tram rac 4 Revision A 2002029 021 1 Introduction evision TRAM RAC 4A 2002029 021 your notes 1 2 TRAM RAC 4 Revision 2002029 021 Introduction Manual Information Manual Information Revision History Each page of the document has the document part number and revision letter at the bottom of the page revision letter changes whenever the document is updated Revision Date Table 1 Revision History Comment A 23 February 2001 Initial release of this manual for the 4 Two Board version Manual Purpose Silver or gold This manual supplies technical information for service representative and technical personnel so they may maintain the equipment to the assembly level U se it as a guide for maintenance and electrical repair considered field repairable m This manual applies only tothe Tram rac 4A with the silver plate below the module slots Two Board version m TheTram rac Housing Service Manual PN404183 096 is for
52. equipment or permit fluids to run behind switches into the connectors or into any ventilation openings in the equipment Never use these cleaning agents m abrasive cleaners or solvents of any kind acetone m alcohol based cleaning agents except for cleaning the thermal print head or m Betadine Interior Cleaning On a regular basis qualified service personnel should open the RM M or RM module and blow dust from unit with compressed air Revision A Tram rac 4A Housing 3 5 2002029 021 Maintenance Electrical Safety Tests Electrical Safety Tests General Recommendations Required Tests Electrical safety tests provide method of determining if potential electrical health hazards to the patient or operator of the device exist These tests are Tram rac 4A units with the optional power supply If your Tram rac 4A does NOT havea power supply see the test procedure in the service manual of the host monitor i e Solar 8000 Solar 9500 etc GE Medical Systems Information Technologies recommends electrical safety tests be performed m upon receipt of the module m every twelve months thereafter and m each time the module is opened or repaired m Tosafety test Tram rac 4A without a power supply leave it connected to a monitor during the safety tests m Safety test a Tram rac 4A with a power supply separately Record the date and results on the Repair Log on page 3 14 at the end
53. for cables and cable part numbers WARNING Equipment damage Connect the Octanet and Tram rac housing to the Solar 8000M patient monitor BEFORE plugging the power cord into AC outlet Connecting these devices to a powered Solar 8000M patient monitor could damage the connectors Revision Tram rac 4 Housing 2 7 2002029 021 General Information Equipment Overview Tramscope Monitor Connection Thelevel of software used in the connected patient monitor determines how the two Tram net connectors on the Tram rac 4 may be used Tramscope V6 V7 Software If your Tramscope monitor uses V6 or V7 software the monitor may only support one Tram rac housing The right Tram net connector may be connected to the following m themonitor or m aTram ne hub The center Tram net connector may be connected a remote control but NOT toanother Tram rac housing See Accessories on page 3 13 for cables and cable part numbers 2 8 Tram rac 4A Housing Revision A 2002029 021 General Information Equipment Overview Tramscope V17 Software If your Tramscope monitor uses V17 software the monitor may support two Tram rac housings The right Tram net connector may be connected to the following m amoni
54. rac 4 is more the 20 feet from the monitor The Tram rac 4 operates in an environment with high electrical noise One Tram rac without a power supply is already connected to the monitor or Tram net hub or Y ou exceeded the monitor power supply capability e 55 55 2 12 4 Housing Revision 2002029 021 General Information Technical Specifications Technical Sp ecifications Table 2 Performance Specifications for Analog Output Description ECG From Tram or Discrete Parameter Module Trace and ll gain 1 V mV 10 Range 5 mV Frequency response 0 05 Hz to 100 Hz Respiration From Tram module only Lead Displayed lead Gain 1 V ohm 0 4 ohm to 10 ohms Frequency response 0 05 Hz to 2 2 Hz Blood Pressure From Tram or Discrete Parameter Module Outputs Tram Arterial BP BP 2 BP 3 BP 4 Discrete Parameter Module Up to 3 additional signals for slots 5 6 and 8 Dependent on Tram rac housing size Gain 10 mV mm Hg 5 Frequency response 0 to 50 Hz Range 25 mm Hg to 300 mm Hg 0 mm Hg 0 0V 0 005V Table 3 Communication Specifications Description Communications to monitor provi ded by Tram net communication Data acquisition Intel 80 31 8 bit 14 7 MHz Communication to display Intel 80 152 8 bit 14 7 MH
55. the TRAM RAC 4A front bezel and sliding the cover out the front Table 4 J6 10 Header to In System Programmer Pin S Signal Name Signal Level 1 0 Signal Description 1 DATAO TTL I O Data stream input from the In System Programming equipment when programming serial EEPROM SER EN active low Data stream output from the AT17LV512A when configuring the Altera 1K30 FPGA 013 2 4 5 6 9 Noconnection Pins are unused and not connected to the Processor Acquisition PCB 3 DCLK TTL 10 Clock signal input from the ISP equipment when programming serial EEPROM SER EN active low 1 67MHz to 16 7MHz clock signal supplied by the AT17LV512A when configuring the Altera 1K30 FP GA 113 7 GND 0v O Ground supplied to the ISP equipment 8 3 3 3 3 3 3V power supplied to the ISP equipment 10 SER_EN TTL Signal driven low by ISP equipment when programming the AT17LV512A serial EEPROM Revision Tram rac 4A Housing 6 15 2002029 021 Tram rac 4A Processor Acquisition PCB Part Location Diagram PN 2004288 001A Part Location Diagram PN 2004288 001A 1 of 3 COMPONENT SIDE ASSEMBLY VIEW Q O O NNNNNNNANANNNNANNANNNNNNNANNNANNNANNNA
56. the upper level hub 7 Not Used 9 DN_RX Differential TRAM NET DOWNWARD PATH NON INVERTED RECEIVE Non inverting receiver input from the upper level hub Shell CGND_IN OV CHASSIS GROUND IN Shield ground into the Tram rac 4 housing from the upper level hub Table 5 Connector J10 9 Pin Tram net Connector to Another Tram net Device Pin Signal Name Signal Level 10 Signal Description 1 UP_RX Differential 0 UPWARD PATH NON INVERTED RECEIVE Non inverting receiver input from the lower level device or hub 2 8 GND_OUT OV GROUND OUT Power return for 16 5V supply from the Tram rac housing to the lower level device or hub 3 UP RX Differential 0 UPWARD PATH INVERTED RECEIVE Inverting receiver input from the lower level device or hub 4 6 16 5 OUT 16 5V 16 5 POWER OUT 16 5V power supply from the Tram housing to the lower level device or hub 5 DN_TX Differential DOWNWARD PATH INVERTED TRANSMIT Inverting transmitter output to the lower level device or hub 7 Not Used 9 DN_TX Differential DOWNWARD PATH NON INVERTED TRANSMIT Non inverting transmitter output to the lower level device or hub Shell CGND_OUT OV CHASSIS GROUND OUT Shield ground from the Tram rac 4A housing to the lower level device or hub Revision Tram rac 4A Housing 7 11 2002029 021 Tram rac 4 Interface PCB Input and Output Connectors Table 6 C
57. 1 4 on the Processor Acquisition PCB interface to parameter modules inserted in the RAC 4A Revision A Tram rac 4A Housing 6 3 2002029 021 Tram rac 4 Processor Acquisition PCB Theory of Operation Block Diagram 4A Processor Acquisition PCB architecture is illustrated this block diagram 30 Pin Module Connectors J1 J4 Digital Interface DAS DAS TRAM net Hub and gt sura A YFY Microprocessor EEPROM Serial Shift Register Slat 80031 U18 32Kx8 U19 Communication a Dip Switch D AS ID and Bootfail Logic U13 Analog Multiplexers 0411 and 112 Status Register Read Analog Interface DAS ADDRESS 14 7456MHz Crystal amp Buffer Y1 017 C ontrol Logic for Two Status Reset Watchdog MostPCB Control US Functions U 13 INIHI D ata Buffer Offset Suner Registers U13 Correction 2 s Comp To Amplifier 09 PERA Deta Unsigned ADC Stat e eee Machine Control Serial Dual Port RAM 29 State Machine ontrol Converter FPGA AD7895 US 2 5V Reference 07 DAC Data Register Configuration Write 12 bits 013 114 Configuration Download Header 10 pin J6 165 154 45V 6 Diagnostic LEDs TNC TNC SRAM 051 056 Processor Acquisition PCB to Interface Microprocessor EEPROM 32 8 U1 60 pin connector
58. 10 which is configured as a 1 to 8 demultiplexer under control of the DAS control processor on the Tram rac4A Processor Acquisition PCB The demultiplexer circuit feeds eight analog hold circuits which hold the analog samples until they are refreshed by the DAC with the next samples Finally the analog signals are filtered to remove the high frequencies introduced by the digital sampling process The signals are supplied to external devices through a 15 pin subminiature D type connector Digital to Analog Converter Analog Demultiplexer A12 bit DAC U 7 with built in voltage reference and output amplifier It produces a voltage output with 1 LSB maximum linearity error It is configured for bipolar 10 V operation The gain error is 0 2 maximum andthetypical zero error is 10 mV 220 mV maximum The data bus and control signals for U 7 come from the Tram rac4 Processor Acquisition PCB The analog multiplexer U 10 is configured as 1 to 8 demultiplexer It consists of eight bi directional switches with one side of each switch common with all switches The maximum switch on resistance is 550 ohms T he switches guarantee break before make action to avoid interference between channels 7 4 Tram rac 4A Housing Revision 2002029 021 4 Interface PCB Theory Operation Analog Hold Circuit Low Pass Filter Tram Analog Outputs The analog hold circuit consists of a 4700 pF hold capacitor C5 C13
59. 14 19 23 250 1UF 80 20 50V 1287 104 20 27 33 35 37 40 41 43 48 3 38 39 AL 470 20 50 1264 471 3 C5 7 8 11 13 15 18 25 CAP CER X7R 0047UF 10 50V 1282 472 24 26 28 32 34 42 44 47 49 C24 CAP CER COG 22PF 10 50V 1281 220 1 C50 CAP TANT 1 0UF 10 35V 1224 105 1 CR1 DIODE 100V 2401 410 1 CR2 5 DIODE RECT 1A 50V 1N4001 2401 001 2 CR3 4 DIODE 5515 2002 515 2 DS1 4 DIODE VSBL RED RTANG PC MT 5V 2498 002 4 Fl CURRENT PROT PTC 250MA 1913 025 1 5 BOARD SPACER 75IN 2 30 1 410676 001 1 See Table 2 15 60 Connector to Processor Acquisition PCB on 7 9 9 CONN D VERT 9M PC MT W FFS 410573 001 1 See Table 4 Connector J 9 9 Pin Tram net Connector to Patient Monitor on page 7 11 10 CONN D VERT 9F PC W FFS 1747 509 1 See Table 5 Connector J 10 9 Tram net Connector to Another Tram net Device on page 7 11 111 CONN D VERT 15F MT W FFS 1747 516 1 See Table 6 Connector 11 15 Pin Analog Output Connector on page 7 12 Q1 TRANSISTOR MFET P CHAN IRF9531 2706 101 1 R1 4 5 7 11 15 18 23 RES MINI MF 249 1 1 4W 1023 133 12 29 35 39 48 R2 3 13 14 RES MINI 4 99 1 1 4W 1023 258 4 R6 8 10 17 19 20 22 RES MINI MF 280K 1 1 4W 1023 426 17 28 30 32 34 36 38 40 47 49 50 R9 12 16 21 24 27 31 RESISTOR MINI MF 1 1 4W 110 1023 100 10 33 45 46 R25 26 RES MINI MF 49 9 1 1 4W 1023 067 2
60. 3 00 d LE cL 942 NI 00H d c H2 NI 0OW 8HJ N3 GOW d AAAA 1010 100 VNV tz 180 01387100 1510 135 1 0 1910 21387100 0 pag 810 1610 91 05713 tra NO 0S 1x3 LM NO 1X3 N30 1X3 NT OXL 1X3 N30 1X3 dn 0XI 1X3 ASn8_0 v 135 1 2 N02 20v 13574 13 20 9135 7135 517207 2135 vivo 1 1 35720 20 3u 950 E 00 150 3004 vi 900 570 AQuU ONI SVO NLLY LNI ONI t Sv 02 294001 Sv0DDV SVO ZHXEZI d 9 ANVIS 4 d H211 V1V0 d XX V1Y0 00M d 20127 1 0 00H 100 V1V0 00H 31V8911V3 _ _ 93294 1 15 0 NI V1V0 0V01 00W 02 2NL _ 11015 IW d N3072NL 21015 10W d NL 101 10 d 71015 I0 d T101S7 VN3 NL d Z101S VN3 NI d ELOTS VN3 NL d T1015 NL d 00H d 2H2 N3 00k d H27N3 00k d 7H2 N3 ON d SHO N3 00k d 9827N37 00k d LH2 N3 00k d 8H3 N3 0DN d 11015 00 9 1015 0084 101S_00W_d 71015 0084 AAAA AAAA L T 8ST 110 191 1735 1n gt 991 2135 100 L C PM d
61. 5 27 DAC D6 28 DAC D7 31 DAC D8 32 DAC D9 33 DAC D10 34 DAC 011 35 36 OUT SEL2 TTL ANALOG OUTPUT CHANNEL SELECT The analog output 38 ANA OUT TTL ANALOG OUTPUT DEMULTIPLEXER SELECT The enable signal for the analog output demultiplexer 39 DAC TTE DIGITAL TO ANALOG CONVERTER DEVICE SELECT This active low signal selects the DAC device during DAC write operations Revision A Tram rac 4A Housing 7 9 2002029 021 Tram rac 4 Interface PCB Input and Output Connectors Table 2 J5 60 Pin Connector to Processor Acquisition PCB Pin Signal Name Signal Level Signal Description 29 41 43 45 GND OV O 5 GROUND The return signal for the 5V power supply 30 40 42 44 46 5V 5V 0 5V POWER power supply 47 49 51 53 AGND OV O ANALOG GROUND The return signal for the 15V power supplies 48 50 15V 15V O 15V POWER 15V power supply 52 54 15V 15V 0 15V POWER 15V power supply 55 WF_RTN 0v WAVEFORM OUTPUT RETURN NUMBERS 1 THROUGH 5 This signal is the reference for waveform outputs 1 5 56 WF OUTI Analog WAVEFORM OUTPUTS NUMBERS 1 THROUGH 5 57 WF 0012 10V Programmable waveform outputs unbuffered typically from a 58 WF_0UT3 Tram or discrete parameter module 59 WF_OUT4 60 WF 5 Table 3 8 15 to Power Supply
62. 50V 1281 220 1 CR3 4 DIODE TVS515 2002 515 2 DS1 4 DIODE VSBL RED RTANG PC MT 5V 2498 002 4 Fl CURRENT PROT PTC 250MA 1913 025 1 5 BOARD SPACER 75IN 2X30 1 410676 001 1 See Table 2 5 60 Pin Connector to Processor Acquisition on 7 9 8 CONN D PLUG 15 PIN 402452 001 1 See Table 3 Connector J 8 15 Connector to Optional Power Supply on page 7 10 9 CONN D VERT 9M W FFS 410573 001 1 See Table 4 Connector 9 9 Pin Tram net Connector to Patient Monitor on page 7 11 10 CONN D VERT 9F W FFS 1747 509 1 See Table 5 Connector J 10 9 Tram net Connector to Another Tram net Device on page 7 11 111 CONN D VERT 15F W FFS 1747 516 1 See Table 6 Connector 11 15 Pin Analog Output Connector on 7 12 R1 4 5 7 11 15 18 23 RES MINI MF 249 1 1 4W 1023 133 12 29 35 39 48 82 3 13 14 RES MINI 4 99 1 1 4W 1023 258 4 R6 8 10 17 19 20 22 5 MINI MF 280K 1 1 4W 1023 426 16 28 30 32 34 36 38 40 47 49 R9 12 16 21 24 27 31 RESISTOR MINI MF 1 1 4W 110 1023 100 10 33 45 46 R25 26 RES MINI MF 49 9 1 1 4W 1023 067 2 T2 TRANSFORMER QUAD ISO STARLAN 404053 001 1 7 16 Housing Revision 2002029 021 4 Interface PCB P arts List 800516 002 Table 8 Parts List 800516 002 Ref Des Description Number Qty T3
63. 7 14 Tram rac 4A Housing Revision A 2002029 021 4 Interface PCB List 800516 001 Table 7 Parts List 800516 001 Reference Designation Description Number Qty T1 3 CHOKE 20UH 407418 001 2 T2 TRANSFORMER QUAD ISO STARLAN 404053 001 1 01 CONVERTER DC DC 25W 5 15V 409028 001 1 U2 3 IC DIP DIFF XCVR DUAL DS8923 410461 001 2 U4 5 8 11 IC DIP AMPL QUAD MC34184 403321 001 4 U6 9 IC DIP ESD OVP ARRAY 14 PAIR 411120 001 2 U7 12 BIT D A CONVERTER AD767 400643 001 1 U10 IC MUX 8CH MOS 508 3304 508 1 W1 2 RES 0 OHM 1001 000 2 CKT BD TRAM RAC 4A INTERFACE 800517 001 See Part Location Diagram 800516 001 002 page 7 13 SCHEM TRAM RAC 4A INTER SD800516 001 1 See Schematic Diagram PN 50800516 0010 on page 7 18 SCREW 4 40 X 1 4 45074 408 6 Revision A Tram rac 4A Housing 7 15 2002029 021 4 Interface PCB P arts List 800516 002 Parts List PN 800516 002 Table 8 Parts List PN 800516 002 Ref Des Description Number Qty C1 CAP AL 100UF 20 35V 1265 101 1 C2 4 6 C9 10 14 19 23 750 1UF 80 20 50V 1287 104 19 27 33 36 37 40 41 43 48 3 38 39 CAP AL 470uF 20 50V 1264 471 3 C5 7 8 11 13 15 C18 CAP CER X7R 0047UF 10 50V 1282 472 24 25 26 28 32 34 42 44 47 49 C24 CAP CER COG 22PF 10
64. 8 TOUV NI 19 ISTIV NL 93 1 90EN 4 5 L 8 325621 900M 570 900M JNL 6 23 Housing 2002029 021 2004289 001 iagram D ic Schemat Tram rac 4A Processor Acquisition PCB 4 of 9 6 30 7 _ 13365 100 6829002 saan alt 1 510039 8055330 4 JVW Wvul W3HJS S4190 TONHIIL NOLLVN3OSNI SRALSAS TVO9ISN A05 5 38V 580112 8 2 11 S0VuV308JIN NI SANIVA 32NVIDVdV2 11 M9T T SWHO NI SINIYA 32 151538 11 Z 3 112 3 V NY A9 03 01104 19 91 11 031412345 351 83 10 SS31Nn 834 10 85 LUISA mE 100 1585 T 2 0135 110 66 9983 1 1 713 Ind GAVE 2583 z 7135 100 z T 1983 T tig LUTXE 4 z T Tor 66 AVE 2 8983 16107770 T 7587 T z 1810 390 66AV z 985 H 150 2vd 66 AV 2 5583 1910 390 T 9287 1510 30 66 2 9583 70 290 T 1 tela 390 S6 AVE 7 1587 T 0 3vd 66 8 7182 T Tmo 250 66 z 8583 1 1010 3 0 66 z ELU N30 1X3 66 2
65. CB PN 2004289 001A 10 9 Schematic Diagram TYNIDIHO 0V2 6 JO T 13355 3190 033 15830038 38 TIM ONY SH3H10 10076829002 10 50 70 35 3138 035 38 LON LI LVHL ONIONVLSHAONN 030551 338 SVH 1102140442813 1151003 805533084 LS3U31NI SLI OL 19143418130 H3NNYW ANY NI 1350 38 LON AVW ONY S3I9010NH231 V W3HJS MVANOW JAILS 5 431545 1VJIO3N 39 40 41439034 387 031N3S3Hd3H NIJH3HI NOIS30 ONY INIHd SIHL SYULX3A0S WVUS 8 x 3085 JNI HS ON SUV ONI 3107 95229 ONL INL WONd33 8 X 3MBd ONI ISTIV ONL olv ow a nv n 5 2N Hu 299 62650 N zn NL 00000000 m YYVYY EE SERE E JN 16 v NI ONI 50 INL 2N1 TVILNSGIJNOO 219093 TA 6EN 90TH or 950 4483 6112 0350 108 035 15 1 530 338 423420 7 0113 50
66. CHOKE 20UH 407418 001 1 01 CONVERTER DC DC 25W 5 4 15V 409028 001 1 02 3 IC DIP DIFF XCVR DUAL 058923 410461 001 2 U4 5 8 11 IC DIP AMPL QUAD MC34184 403321 001 4 U6 9 IC DIP ESD OVP ARRAY 14 PAIR 411120 001 2 U7 12 BIT D A CONVERTER AD767 400643 001 1 U10 IC MUX 8CH MOS 508 3304 508 1 BD TRAM RAC 4A INTERFACE 800517 001 1 See Part Location Diagram 800516 001 002 page 7 13 5 TRAM RAC INTER SD800516 001 1 See Schematic Diagram PN SD800516 001D on page 7 18 SCREW BDGH 4 40 X 1 4 45074 408 6 Revision A Tram rac 4A Housing 7 17 2002029 021 Tram rac 4A Interface PCB Schematic Diagram 50800516 0010 Schematic Diagram 1 of 7 PN SD800516 001D m MARQUETTE FLECTRONICS INC TRAM NET IN TRAM NET OUT DATE DRAWN BY TRAM NET INTERFACE CIRCUITRY CONFIDENTIAL DS8923AN DS8923AN 02 DS8923AN DS8923AN 02 D UP EXT DEN EXT DEN UP 75 20 EXT DN RXD EXT_TXD_DN 175 25 DAS BOARD 7 18 Tram rac 4A Housing Revision 2002029 021 Tram rac 4A Interface PCB Schematic Diagram 50800516 0010 2 of 7 J11 6 OUT1 WF OUT13 WF_OUT10 Ov 1 MARQUETTE ELECTRONICS INC
67. D is defined in Table 1 Indicators Table 1 Indicators LED Color Signal Name Function Condition DS6 Green Power Indicator Proper Operation m On Continuous normal operation m Visible Tram rac 4A front Flashing Quickly 2Hz ADC Error bezel lower left m Flashing Slowly 0 5Hz watchdog timeouts m LED Off power off supply fault RAC FPGA configuration fault DS5 Red Network Activity hear talking on TRAM net m On mostly steady TRAM RAC connected m Flickers low TRAM net not hear myself talk 054 TransmitEnable am talking on TRAM net m Flickers occasionally when talking m On continuous while graphing DS3 Yellow Error Detect I detect an error on this PCB m Off normal operation DS2 Red RAC COMM 80 152 COMM Processor is m Flashes with 051 twice per second normal operation DS1 Red RAC DAS 80C31 DAS Processor is OK m Flashes with 052 per second normal operation NOTE 14 hear talking on my TRAM net LED flashes with the 1 am talking TRAM net LED alone when someone else is talking 6 10 Tram rac 4A Housing Revision 2002029 021 Tram rac Processor Acquisition PCB Input and Output Connectors Input and Output Connectors This section defines all signal connections with the Processor Acquisition PCB Pin number signal name signal level input or output and a description i
68. ED 414417 002 3 053 LED SM 1206 YELLOW 414417 003 1 DS4 LED SM 1206 GREEN 414417 004 1 DS6 LED GRN SUBMN SRFMNTPRFMD CON 405033 002 1 11 4 CONN M VER 1866 030 4 See Module Interface J 1 4 on page 6 11 1 4 30 Pin Connectors to Parameter Module Slots on page 5 10 5 2ROW 10CRT PASS THR 410333 001 1 See Interface PCB 5 on page 6 14 5 60 Pin Connector to Processor Acquisition PCB on page 7 9 16 HEADER VERT 2 5 10 230H 1778 210 1 See ISP Serial EEPROM Interface J 6 on page 6 15 03 TRANSISTOR SM NPN MMBT3904WT1 421106 001 1 R1 10 12 14 18 25 38 RES SM 0603 100 1 1 16W 410334 003 27 40 42 48 51 56 59 62 65 67 68 77 81 85 88 93 96 98 106 Revision A Tram rac 4A Housing 6 19 2002029 021 Tram rac 4 Processor Acquisition PCB arts List PN 2004288 001 Reference Designation Description Number Qty R2 7 13 17 20 23 24 5 SM 0603 1 1 16W 410334 008 41 30 31 34 35 39 41 43 46 47 50 53 55 57 66 72 14 16 80 87 89 91 97 99 104 R8 19 21 22 29 49 58 RES SM CER 0603 10K 1 1 16W 410334 013 11 61 71 73 78 R9 R37 R83 R 94 RES SM 0603 100K 1 1 16W 410334 019 4 R11 36 82 90 95 RES SM CER 0603 0 OHM 410334 027 5 R15 52 60 84 RES SM 0603 4 75 1 1 16W 410334 010 4 44 45 69 70 RES SM 0603 49 9 1 1 16W 410334 040 4 R105 RES SM 0603
69. EDICAL 408230 002 1 54 HOUSING ASSEMBLY TRAM RAC 4A 404773 003 0 70 BEZEL TRAM RAC 4A 404479 003 1 71 MOUNT SIDE RAIL RIGHT HAND TRAMRAC 4A 400764 004 1 72 MOUNT SIDE RAIL LEFT HAND TRAMRAC 4A 400764 005 1 75 COVER BOTTOM TRAM RAC 4 400766 004 0 76 COVER PL RAC 4 404685 003 0 78 COVER BACK 4 404673 007 0 80 LIGHT PIPE 4 POWER 2004496 001 1 81 A2 PCB TRAM RAC 4A PROCESSOR ACQUISITION 2004288 001 1 See Chapter Tram rac 4A Processor Acquisition 82 PCB TRAM RAC INTERFACE W PS For PN 900031 005 Only 800516 001 1 PCB TRAM RAC INTERFACE W PS For PN 900031 006 Only 800516 002 1 See Chapter 7 Tram rac 4A Interface 83 IPSI POWER SUPPLY PAC 4A UNIVERSAL For PN 900031 006 Only 6123 211 1 See Chapter 8 Tram rac 4 Power Supply 85 SCR 6 32 X 1 12 STL COAT 405318 002 4 86 SPRING COMPRESSION 410529 001 4 87 LABEL TRAM RAC 4A DIA W O PWR For PN 900031 005 Only 411224 004 1 88 LABEL TRAM RAC 4A PORTS For PN 900031 005 Only 411224 002 1 93 LABEL CE MARK 408230 008 1 94 SCR 4 24X3 8 PH PHIL BLT POINT 408217 001 6 95 SCR THRD FORMING HI LOW 4 24 X 3 8 GREY 2001015 001 18 98 KIT SNAP COVER TRAM RAC 2002421 002 1 99 GROM NON MTLC 3 16 ID NEOPRENE BLACK 2006427 001 1 5 20 Tram rac 4A Housing Revision A 2002029 021 6 4 Processor Acquisition P CB evision Tram rac 4A Housing 2002029 021 yo
70. J5 2800 152 U3 32Kx8 U2 Microprocessors The two eight bit microprocessors on the board run at an external clock input frequency of 14 7456M HZ The 80 31 U 18 is referred to as the data acquisition system DAS processor while the 80C152 U3 is referred to as the communications COMM processor The 80C31 provides serial shift register digital communications with each module slot controls a twelve bit analog to digital converter ADC and controls a digital to analog converter DAC the Interface PCB Patient parameter data acquired by the 80C31 is passed to the 80C152 through a dual port random access memory RAM contained in the RAC field programmable gate array RAC FPGA U13 The 80C152 collects the parameter data from dual port memory and transmits the data on the TRAM net communications network The 80C152 receives TRAM net data intended for the TRAM RAC 4A housing and may pass the data to the 80C31 through dual port memory 6 4 Tram rac 4A Housing Revision 2002029 021 Tram rac 4 Processor Acquisition PCB Theory of Operation Microprocessor Memory 80C31 DAS processor U18 80C152 COMM processor The 80C31 DAS processor U 18 executes software code from a 32K byte FLASH memory device U 19 The 80C31 exchanges data with the 80C152 through the 2K byte dual port memory contained in the RAC FPGA U13 The 80C31 uses a portion of the dual port memory for local data storage and has the ability to
71. Maintenance Accessories Accessories You can order the following accessories from GE M edical Systems Information Technologies see Solar 7000 8000 Monitor Connection on page 2 6 Solar 8000M Monitor Connection on page 2 7 or T ramscope Monitor Connection on page 2 8 for cable placement Table 10 Tram rac Accessories Description Part Number Cables for Tram rac 4 without HU B 1 2 meter 4 foot cable CPU to Tram rac 700520 001 interconnects Solar 8000 9 to 9 3 meter 10 foot cable CPU to Tram rac 700520 002 4 5 meter 15 foot cable to Tram rac 700520 003 7 5 meter 25 foot cable CPU to 700520 004 Cables for Tram rac without HUB 1 meter 3 5 foot cable CPU to Tram rac 409753 001 interconnects Solar 7000 8000 Tramscope 2 4 meter 8 foot cable CPU to Tram rac 409753 002 6 meter 20 foot cable CPU to Tram rac 409753 003 9 1 meter 30 foot cable CPU to Tram rac 409753 004 NOTE Cable lengths less than 6 meters 20 feet do not require a Tram rac with a power supply Cables 4 with HUB interconnects 1 2 meter 4 foot cable HUB to Tram rac 409752 001 B connects Tram rac 4A to hub 3 meter 10 foot cable HUB to Tram rac 409752 002 4 5 meter 15 foot cable HUB to Tram rac 409752 003 Daisy chain Cables to connect a Tram rac 4Ato 0 3 m
72. N 6123 211 NOTE Table 6 Daughter PCB GE Medical Systems Information T echnologies part numbers not given because this is manufactured by a vendor Reference Designation Description Part Number Qty C101 Cap 220pF 100V 1 C102 0 22uF 10 50V 1 C103 0 01uF 10 100V 1 104 0 002UF 10 100V 1 105 Cap O 1g F 50V 1 1 Circuit Board Daughter PCB 1 See Part Location Diagram PN 6123 211 R101 Res 20 5 1 4W 1 R102 Res 47 5 1 4W 1 R103 Res 680 Ohm 5 1 4W 1 R104 Res 1 33K 1 1 4W 1 R105 111 Res 1 0K 1 1 4W 1 R106 Res 909 Ohm 1 1 4W 1 R107 Res 5 23K 1 1 4W 1 R108 Res 255 Ohm 1 1 4 1 R109 Res 31 6 1 1 4W 1 R110 Res 5 11K 1 1 4W 1 R112 Res Variable 1K 1 U101 Monostable Multivibrator UC 2842 1 U102 Isolator Optically Coupled MOC81011 1 9103 Volt Ref Programmable TL431CLP 1 Revision A Tram rac 4A Housing 8 9 2002029 021 Tram rac 4A Power Supply Schematic Diagram PN 506123 211 t lt 2 N tc L cN Q 2 E Schematic Diagram 8 10 2002029 021
73. N RX A8 FAGND MOD LATCH 15 9 AGND 10 10 SHELL CGND IN CALIBRATE A9 11 AGND 11 A10 CALIBRATE 12 5V 12 A11 FIN ENA SLOTT A11 FOND 43 165 CONV 43 12 412 LIN ENA SLOT3 165 14 J10 A13 15V 16 5V ma A13 Hey 15 he 1 14 SHEL SHELL 2 GND OUT A15 A15 LAGND A3J8 PS1J7 UP RX WE CHI 4 165VOUT B1 FMOD EN gi EAE CHS A2 J5 A3 J5 5 DNTX B2 go MOD EN CHS 1 GND 1 6 16 5V OUT B3 65 Ba OF CHG 2 165V 2 7 He 165 3 OUT B5 FWEOUH gs 4 165 4 DNTX BU WE OUT2 5 GND 5 OUT 87 Fours WF OUT2 6 1654 6 B8 WF OUT3 123KHZ B8 7 GND 7 123 2 16 5V 8 B10 FGND LPACER BLANK 9 GND 9 B11 GND J11 5V B11 10 16 5V 10 B12 isy pio LV 11 GND 7 4 B13 LV 12 16 5V 12 2 EWEOUT2 B14 15 B14 13 EXT RXD DN 43 LWFOUT4 LAGND AGND 44 EXT SQ DN 44 4 WF OUT6 15 EXT TXD UP 45 5 WFOUT8 85 WEF OUT10 A248 16 EXT DEN 16 6 17 EXT UP 17 WFOUT12 18 EXT SQ UP 18 19 EXT TXD DN 19 9 WFOUT1 242 20 EXT DEN DN 20 10 WE A1 END A1 OND 21 DAC DO 21 11 WF OUT5 CH4 A2 MOD EN CH8 22 DACD1 22 12 OUT7 23 DAC D2 23 13 OUT9 A4
74. OR ACQUISITION PCB 2 SCHEMATIC DETAIL 5 8 Tram rac 4 Housing Revision A 2002029 021 Tram rac 4 Housing Interconnection Diagram 900031 9 J8 PS1 J7 A2 J1 A2 J3 1 GND 1 1 GND 2 LCIV 2 2 GNDIN A1 MODENCH2 A1 COND 3 15V 3 3 UP A2 AGND A2 MOD EN CH6 4 AGND 4 16 5V IN A3 4 SYNC ECG SYNC ECG s 5 5 DNRX MOD DATA CLOCK 4 5 6 GND 6 6 16 5V 5 MD1SLOT1 A5 MOD DATA CLOCK 7 GND 7 NC MD1 SLOT3 7 SLOT1 A6 Do SLOTS GND 8 GNDIN AT MOD DATA LATCH 9 15V 9 9 D
75. OTX is asserted low The four TN ENA SLOTX signals are inputs to the RAC 4A and contain a 100K ohm pull down resistors The logic performs carrier sense on each of the six upward path and downward path TRAM net ports Collisions are detected when more than one upward path port transmits simultaneously When a collision is detected the collision presence reporting signal is substituted for the colliding signals The collision reporting signal contains Manchester code violations and enables all network nodes to detect the collision logic enforces a 26 bit blinding time after all upward or downward path transmissions to remove spurious transitions Spurious transitions may occur after a valid packet transmission due to magnetic field collapse in isolation transformers L oopback headhub carrier sense and blinding timer functions for the 80C152 TRAM net node are implemented as shown in Figures 2 and 3 The FPGA provides logic for the synchronous serial shift register communication protocol that allows the 7000 series parameter acquisition modules to communicate with the 80C31 DAS processor 7000 series modules are identified by a logic high the TN_ENA_SLOTX signal input to the 4 TheMOD LOAD DATA andthe MOD_DATA_OUT signals are multiplexed with the TRAM net receive data and transmit data signals respectively for each module slot 6 8 Tram rac 4A Housing Revision 2002029 021 Tram rac 4 Processo
76. Revision Maintenance Log Unit Serial Number Institution Name bate Maintenance Repair Revision Tram rac 4A Housing 2002029 021 Maintenance Log For your notes 3 16 Tram rac 4 Housing Revision A 2002029 021 4 Troubleshooting evision Tram rac 4 Housing 2002029 021 your notes Tram rac 4 Housing 2002029 021 Revision A Troubleshooting Controlling Electrostatic Discharge Damage Controlling Electrostatic Discharge Damage Guidelines components of the Tram Critical Care Monitoring System make extensive use of CMOS components CMOS components are used because they are more immune to noise and consume less power than standard TTL NMOS components H owever by their nature CM OS components are more vulnerable to electrostatic discharge ESD damage than other semiconductors ESD damage usually a subtle weakening of semiconductor junctions can range from corruption of digital memory to catastrophic failure rendering a component or a number of components permanently unusable Although it is more common for CMOS components to fail from ESD damage no semiconductor device is completely safe from ESD damage The inputs and outputs of all of the components are protected from ESD damage so they no more susceptible to ESD damage during normal operation than
77. THI 2 T MNV18 d aivusnva lt 1 d lt ZHNEZT d H21v1 VLVO 00H HDL vivo dew 11015 00W 6AVI E 482 110157104 pousse gan 66AVG 4882 2 T101S ION d 12 viv0 004 THJ N3700W THO N3 00W d a GOW 6 of 9 Se GOW d A ision Rev Tram rac 4A Housing 6 26 2002029 021 2004289 001 iagram D ic Schemat Tram rac 4A Processor Acquisition PCB 6 30 4 1335 5 58012 4 2 11 7 50 NI xd 100 6827002 38v 3 viDvavo mw 7 of 9 51003 805533084 9 SWHO 38 SINIYA 151538 11 W3HJS sun 35183159 NY SHIDOTONHOSI NOLLYNHOANI 03 01104 TYNDIS 545 031 12345 351 83 10 SS31Nn 71015 YNI NI 66AV8 2782 216361 XNV18 43294 PASGAVB G 49282 2 31Vu8I1v3 4 2 ZHNEZT El 2 1 H21V1 VLVO 00W 66 8 6 E 4 5782 2 t EIOS WNI NL 71015 004 PASGAVE g E 2752 2 T X7101S 004 a 7101S I0
78. Tram net receive data to the module for slots 1 4 The module load function is used in the synchronous serial shift register protocol to pre load the module s output shift register prior to transferring data out of the module to the Tram Rac 4A housing When the shift register communication protocol is used active low binary input data is transferred to the module s input shift register on this signal with the falling edge of the MOD DATA CLOCK signal When Tram net communication is used input data on this signal is Manchester encoded and does not require a separate clock 86 WF_0UT1 Analog I O Waveform Output no 1 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the ECG lead II signal 114 MDO_SLOT1 4 TTL Module Data Out Signal is the module data output for slots 1 4 When the discrete parameter synchronous serial shift register communication protocol is used active low binary output data is transferred from the module s output shift register on this signal with the falling edge of the module data clock signal Otherwise when the Tram net communication is used output data on this signal is Manchester encoded and requires no separate clock 87 WF 0012 I O Waveform Output no 2 Th
79. VS and observe the same meter readings as in the previous step Set the GND switch on the leakage tester to CLOSED Read the current leakage indicated DMM If the reading is greater than the appropriate specification below and the device under test is powered from 100 240 V 50 60 Hz the device under test fails and should be repaired and tested again 100 microamperes 0 1 volts on the DMM and the device under test is powered from 100 240 V 50 60 Hz Set the polarity switch to RVS and observe the same meter readings as in the previous step Set the leakage tester power switch to OFF and remove the meter lead connected in step 2 LEAKAGE TESTER PARTIAL SCHEMATIC 9 HIGH SINORM POWER CORD LOW x o s GND DEVICE F TEST s GND M D MEASURING Probe to exposed conductive chassis DEVICE Revision A Tram rac 4A Housing 3 11 2002029 021 Maintenance Housing 5 Kits Housing Service Kits The following part lists are given for ordering purposes T hese kits are available to aid troubleshooting by swapping a suspect component NOTE When ordering these kits note that each kit contains only the latest revision of the PCB assemblies Contact Service T ech Support to verify if the latest revision is compatible with your system PN 2006853
80. any other device However when you service components you expose the components to several sources of static electricity ranging from human hands to improperly grounded test equipment F or this reason it is recommended that all service workstations be as static free as possible The following guidelines can help make your workstation more resistant to the damage that can be caused by static electricity m Discharge any static charge you may have built up before handling semiconductors or assemblies containing semiconductors m A grounded antistatic wristband or heelstrap should be worn at all times when repairing assemblies containing semiconductors Use only properly grounded soldering and test equipment m Usea staticfree surface when working on assemblies containing semiconductors m remove semiconductors or assemblies containing semiconductors from antistatic containers bags until needed m Make sure power to an assembly is turned off before removing inserting a semiconductor m Do NOT slide semiconductors or assemblies containing semiconductors across any surface Do NOT touch semiconductor leads unless absolutely necessary Semiconductors and assemblies containing semiconductors should be stored only in antistatic bags or boxes Revision A Tram rac 4A Housing 4 3 2002029 021 Troubleshooting Wall Receptacle Check Wall Receptacle Check Measure Voltages Neutral
81. c 4 Housing Input and Output Connectors Input and Output Connectors The following tables contain all connections to the Tram rac 4 housing Each signal includes such information as whether it is an input or output the nominal voltage range for each signal the type of signal and the maximum frequency the signal may have This is organized by connector The Tram rac 4 provides connectors J 1 J 4 that correspond to module slots 1 4 The superscript number after the pin number indicates which slot s provide the given signal s Signal names containing slot numbers 1 4 indicate that the signals to each slot or module connector are independent Pin numbers listed without a superscript indicate the signal is common to all four module connectors or slots Table 2 J1 J4 30 Pin Connectors to Parameter Module Slots Pin Signal Name Signal Level 10 Signal Description A1 GND 0v O Ground m Analog discrete parameter modules reference for the output m Tram series modules 16 5V power return 8114 WF A14 Analog Waveform Channels A1 4 Analog waveforms from channel 10V slots 1 4 Art or BP 1 signal for TRAM series modules A214 MOD EN B14 Open Drain O Module Channels B1 4 enable This signal is the module 1K 5V pull up enable for channel B slot 1 4 ofthe discrete parameter modules Signal is asserted high to enable the module to communicate via the synchronous serial shift r
82. cle is wired properly If other than normal polarity and ground is indicated corrective action must betaken before proceeding The results of the following tests will be meaningless unless a properly wired wall receptacle is used Ground Earth Integrity Ground Continuity Test Listed below are two methods for checking the ground earth integrity Ground Continuity Test Impedance of Protective arth Connection These tests determine whether the device s exposed metal and power inlet s earth ground connection has a power ground fault condition Perform the test method below that is required by your Country L ocal governing safety organization Completion of this test is checked by the following steps Disconnect the DU T device under test from the wall receptacle 2 Connect the negative lead of the ohm meter to the protective earth terminal ground pin in power in let connector or the protective earth pin inthe MAINS PLUG ground pin in power cord Refer to the US 120Vac power cord figure on the left Set the Ohm meter to the milliohm range Connect the positive lead of the Ohm meter to all exposed metal surfaces on the DU T If the metal surfaces are anodized or painted scrape off a small area in a inconspicuous area for the probe to make contact with the metal Revision Tram rac 4 Housing 3 7 2002029 021 Maintenance Electrical Safety Tests 5 Resistance should r
83. crete parameter modules This signal is asserted high to enable the module to communicate via the synchronous serial shift register protocol A3 AGND OV O Analog Ground m Analog discrete parameter modules reference for WR output m Tram series modules reference for the SYNC_ECG signal 831 WF 1 4 Waveform Channels B1 4 Analog waveform from channel B 4 10 V slots 1 4 This pin is the BP2 signal Tram series modules A4 SYNC_ECG Analog JO Sync ECG Tram series modules provide this 10mV V signal 4 10 V for use by other modules B4 16 5V 16 5V O 16 5V power output to the modules 5 MOD DATA CLOCK Open Drain O Module Data Clock Signal is the discrete parameter modules 1K 5V pull up data clock used in the synchronous serial shift register protocol The falling edge is used to shift serial data both into and out of the selected module 8514 Connection Revision 4 Housing 6 11 2002029 021 Tram rac Processor Acquisition PCB Input and Output Connectors Table 2 1 44 30 Connectors to Parameter Module Slots Pin Signal Name Signal Level 10 Signal Description A614 510 1 4 5V CMOS 0 Module load Module Data In Signal functions as discrete no tri state module load module data input and Tram net receive data to the module for slots 1 4 The module load function is used in the synchronous serial shift register protocol to pre load
84. d Rott kenn Fa IO tdg a epe 1 5 Definitions of Warnings Cautions and Notes 1 6 Equipment Symbol iaria escena t WAN EMA 1 7 Service Information 1 8 Service Requirements 1 8 Equipment Identification 1 8 VIP ANE 1 8 General Information 2 1 Equipment Overview 2 3 6 Sea Meet Run me 2 3 Tram net Communication 2 4 Tram rac 4 HOUSING 1 oet es ete COR 2 4 Power Supply Connection 2 12 Technical Specifications 2 13 Revision Tram rac 4A 2002029 021 Maintenance 3 1 Controlling Electrostatic Discharge Damage 3 3 Guidelines y 3 3 Maintenance Schedule 3 4 General ct et E eaae A se ad MR DA NG AN ON 3 4 Inspection was 20 55 DO 3 4 G n ral Cleaning ie tee WD Rd ete 3 5 Electrical Safety 5 3 6 General os en 3 6 Recommendations
85. e Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the first displayed trace on the Tramscope monitor A8 MOD DATA LATCH Open Drain O Module Data Latch Signal is the discrete parameter module 1K 5V pull up data latch strobe used in the synchronous serial shift register protocol After eight bits of input data have been shifted into the module using the module data clock this signal strobes the input data into the module s data latch B8 WF OUT3 Analog I O Waveform Output no 3 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the ECG lead V signal A9134 AGND 0v O Analog Shield Ground Discrete parameter modules may use this pin to terminate their shield ground A9 WF 0014 Analog Waveform Output no 4 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the signal Revision A Tram rac 4A Housing 5 11 2002029 021
86. e following m amonitor m aTram ne hub or m another Tram rac housing if this Tram rac housing has a power supply The center Tram net connector may be connected tothe following m aremote control or m toanother Tram rac 4A housing with a power supply NOTE The housing furthest from the monitor must have a power supply Shown below are examples of how to connect dual Tram rac housing to a Solar 7000 or 8000 monitor Note that the Solar 8000 has a horizontal orientation See Accessories on page 3 13 for cables and cable part numbers 2 6 Tram rac 4A Housing Revision A 2002029 021 General Information Equipment Overview Solar 8000M Monitor Connection The Solar patient monitor can support two Tram rac housings The right Tram net connector may be connected to the following m amonitor m aTram ne hub or m another Tram rac housing if this Tram rac housing has a power supply The center Tram net connector may be connected tothe following m aremote control or m toanother Tram rac 4A housing with a power supply NOTE Tram rac housing furthest from the monitor must have a power supply See below to connect dual Tram rac housing to a Solar 8000M monitor TRAM NET 2 RS 232 2 ETHERNET TRAM NET 1 VGA VID 2 See Accessories on page 3 13
87. e standard for measuring leakage current The measuring devices defined by various standard organizations UL etc produce almost identical test measurement results Enclosure Leakage Current Test Perform this test to measure current leakagethrough exposed conductive surfaces on the device under test during normal operation 1 Settheleakage tester switches as follows GND switch OPEN Polarity switch NORM 2 Connect meter lead between the CHAS connector the rear of the leakagetester and an unpainted non anodized chassis ground on the unit under test Set the leakage tester power switch to ON Read the current leakage indicated DMM If the reading is greater than the appropriate specification below the device under test fails and should be repaired and tested again uA 0 3 volts on the DMM and the device under test is powered from 100 120 V 50 60 Hz uA 0 3 volts on the DMM and the device under test is powered from a centered tapped 200 240 V 50 60 Hz single phase circuit 500 0 5 volts on the DMM and the device under test is powered from non center tapped 200 240 V 50 60 Hz single phase circuit NOTE Center tapped and non center tapped circuits produce different leakage currents and the UL and IEC limits are different 3 10 Tram rac 4A Housing Revision A 2002029 021 Maintenance Electrical Safety Tests Set the polarity switch to R
88. ead to pass 0 1 ohm or less without power cord 0 2 ohms or less with power cord Impedance of Protective Earth Connection This test unlike a ground continuity test will also stress the ground system by using special ground bond testers i e Kikusui model 872 TOS 6100 or Associated Research model HYAMP amp J r Model 30300 This test normally is only required as a manufacturing production test to receive safety agency compliance i e IEC601 1 Some country agency s do require this test after field equipment repairs i e Germany s DIN VDE 0751 standards Consult your country local safety agency if in question Compliance is checked by the following steps 1 current not less than 10 and not exceeding 25 A from a current source with a frequency of 50 or 60 Hz with a no load voltage not exceeding V is passed for at least 5 s through the PROTECTIVE EARTH TERMINAL or the protective earth pin intheMAINS PLUG andeach ACCESSIBLE METAL PART which could become LIVE in case of failure in BASIC INSULATION 2 The voltage drop between the parts described is measured and the impedance determined from the current and voltage drop It shall not exceed the values indicated For EQUIPMENT without a POWER SUPPLY CORD the impedance between the PROTECTIVE EARTH TERMINAL and any ACCESSIBLE METAL PART whichis PROTECTIVELY EARTHED shall not exceed 0 1 ohms For EQUIPMENT with a POWER SUPPLY CORD the impedance between the protect
89. ee communication connectors m The 15 yellow color coded connector is used for analog output m Thetwo 9 pin blue color coded connectors are Tram net communication with a patient monitor Tram net hub remote control or anadditional Tram rac housing The number of peripheral devices is dependent upon the software version of the host monitor When you use an optional power supply thereis an additional hidden connector on the back panel for the power supply connection 2 4 Tram rac 4A Housing Revision A 2002029 021 General Information Equipment Overview k Below are examples of the rear label of the Tram rac 4 housing with and without a power supply Further explanation about connection and labeling of the male and female Tram net connectors is found on the following pages 4 200000 ANALOG TRAM Ports without Power Supply ae 00000 ANALOG A TRAM TRAM OUT NET NET Tram rac with Power Supply Revision Tram rac 4 Housing 2002029 021 General Information Equipment Overview Solar 7000 8000 Monitor Connection The Solar patient monitor can support two Tram rac housings The right Tram net connector may be connected to th
90. egister protocol 8214 1 4 Open Drain O Module Channels A1 4 enable Signal is the module enable 1K 5V pullup for channel slots 1 4 ofthe discrete parameter modules This signal is asserted high to enable the module to communicate via the synchronous serial shift register protocol A3 AGND OV O Analog Ground m Analog discrete parameter modules reference for WR_B output m Tram series modules reference for the SYNC_ECG signal 8314 WF_B1 4 Analog Waveform Channels B1 4 Analog waveform from channel 4 10 V Slots 1 4 This pin is the 2 signal Tram series modules A4 SYNC_ECG Analog JO Sync ECG Tram series modules provide this 10mV V signal 4 10 V for use by other modules B4 16 5V 16 5V O 16 5V power output to the modules 5 MOD DATA CLOCK Open Drain Module Data Clock Signal is the discrete parameter modules 1K 5V pull up data clock used in the synchronous serial shift register protocol The falling edge is used to shift serial data both into and out of the selected module B514 No Connection EE jes 5 10 Tram rac 4A Housing 2002029 021 Revision A Tram rac 4 Housing Input and Output Connectors Pin Table 2 1 4 30 Connectors to Parameter Module Slots Signal Name Signal Level 10 Signal Description 614 MDI_SLOT1 4 5V CMOS O Module load Module Data In Signal functions as discrete no tri state module load module data input and
91. enerated in the EEPROM FPGA configuration continues 30ms to 300ms before the F P GA enters user mode The logic programmed into the FPGA during configuration becomes active in user mode Once the FPGA enters user mode the RELEASE RST output drives low and the TNC RST signal transitions high The 80C152 exits the reset state and begins to execute code from FLASH memory U2 The 80C 152 negates the DAS_RST signal by driving the DAS RST signal low allowing the 80C31 018 to begin code execution The MAX 705 U5 contains a watchdog timer circuit that times out in the range of 1 0 to 2 25 seconds The MAX705 circuit forces a board reset nCONFIG node low when the internal watchdog timer expires The 80C 152 and 80C31 strobe the watchdog through a single gate OR device U4 Revision A Tram rac 4A Housing 6 5 2002029 021 Tram rac 4 Processor Acquisition PCB Theory of Operation PCB Clock Generation Analog Multiplexers The Processor Acquisition PCB 80C31 processor uses 14 7456 2 crystal Y 1 to generate the board clock source T he crystal is connected directly to the 80C31 U 18 that contains an internal inverter The output of the 80C31 inverter drives an external single gate inverter U17 U17 drives the clock signal tothe RAC FPGA U13 andthe 80C152 03 Eight analog waveforms can be acquired from the four module slots for analog to digital conversion Discrete parameter modules output analog paramete
92. er level hub 2 8 GND IN 0 GROUND IN Power return 16 5V supply into the Tram rac housing from the upper level hub 3 UP_TX Differential 0 UPWARD TRANSMIT Inverting driver output to the upper level hub 4 6 16 5V_IN 16 5V 16 6V POWER IN 16 5 V power supply into the Tram rac housing from the upper level hub 5 DN_RX Differential DOWNWARD INVERTED RECEIVE Inverting receiver input from the upper level hub 7 Not Used 9 DN_RX Differential TRAM NET DOWNWARD PATH NON INVERTED RECEIVE Non inverting receiver input from the upper level hub Shell CGND_IN OV CHASSIS GROUND IN Shield ground into the Tram rac 4 housing from the upper level hub Table 5 Connector J10 9 Pin Tram net Connector to Another Tram net Device Pin Signal Name Signal Level 10 Signal Description 1 UP_RX Differential 0 UPWARD PATH NON INVERTED RECEIVE Non inverting receiver input from the lower level device or hub 2 8 GND_OUT OV GROUND OUT Power return for 16 5V supply from the Tram rac housing to the lower level device or hub 3 UP RX Differential 0 UPWARD PATH INVERTED RECEIVE Inverting receiver input from the lower level device or hub 4 6 16 5 OUT 16 5V 16 5 POWER OUT 16 5V power supply from the Tram housing to the lower level device or hub 5 DN_TX Differential DOWNWARD PATH
93. eter 1 foot 411090 001 Tram rac 4A 9 pin to 9 pin 0 5 meter 1 5 foot 411090 002 0 8 meter 2 5 foot 411090 003 Tram net HUB Connects the patient monitor to multiple peripheral 409754 001 D Notused with Solar 8000M devices Hub only Tram net HUB Connects the patient monitor to multiple peripheral 410217 001 Not used with Solar 8000M devices Hub with mounting hardware Analog Output Cable for Tram rac 4A Includes instruction sheet 411170 001 Un terminated Defib Sync Cable 4 5 meter 15 foot cable 403936 001 Extension Cables for Tram rac 4A withoutHUB 30 4 meter 100 foot cable CPU to 409753 001 cable 700164 001 60 9 meter 200 foot cable CPU to 409753 001 cable 700164 002 Extension Cables for Tram rac 4A with HUB 30 4 meter 100 foot cable CPU to 409753 001 cable 700159 001 60 9 meter 200 foot cable CPU to 409753 001 cable 700159 002 m Can pulled through conduit end must be terminated the field Requires pn409753 001 cable to connect to the to the power supply m Cost of labor is extra if the cables are not included with the original equipment purchase Revision A Tram rac 4A Housing 3 13 2002029 021 Maintenance Log Repair Log Maintenance Repair Unit Serial Number Institution Name 3 14 4 Housing 2002029 021
94. execute code from dual port when reprogramming FLASH memory The 80C31 maps dual port memory into executable code space by assertingthe DAS_PROM signal low 03 The 80C152 COMM processor 03 executes code from another 32Kx8 FLASH memory device U 2 80C152 exchanges data with the 80C31 through the 2K byte dual port memory contained in the RAC FPGA The 80C152 uses a 32K byte static random access memory SRAM U 1 for local data storage The 80C152 communications processor has the ability to execute code from SRAM when reprogramming FLASH memory The 80C152 maps SRAM into code space by assertingthe TNC_PROM signal low Reset Generator and Watchdog Circuit The main reset generator and watchdog timer functions are performed by the MAX705 device U5 The MAX705 asserts the nCONFIG signal active low 140ms to 280ms after the 5V supply rises above 4 65V The 705 reset output nCONFIG node remains active low while the supply is below 4 65V and is guaranteed to hold the low state down toa supply voltage of 1 2V An active low nCONFIG signal holds the EP1K 30 RAC FPGA U13 in reset with all pins tri stated The FPGA pins have weak internal pull up resistors in the range of 20K to 50K ohms when the nCONFIG signal is low and during FPGA configuration FPGA configuration occurs when the nCONFIG signal is in the high state Serial data is clocked from the Atmel AT17LV512A serial EEPROM U14 into the FPGA using the DCLK signal g
95. he same output connector These signals are not filtered or buffered They are however protected from over voltage and electrostatic discharge by the diode array U9 Electrostatic Discharge Protection Tram net Interfaces A single diode array U6 is used to protect all of the analog output signals from excessive voltages typically caused by electrostatic discharge E SD The signals are damped to the 15 V power supplies if they exceed that voltage range The Tram rac 4 housing appears as six port intermediate hub on the Tram net communication network Two Tram net interfaces are provided on the Tram rac4 Interface PCB One interface is the upward path toward the header hub contained within the patient monitor of the Tram net network The second interface the auxiliary channel is one of the six ports available to the next device downward along the network path from the Tram rac 4A housing Revision A Tram rac 4A Housing 7 5 2002029 021 4 Interface PCB Theory Operation Transceiver Circuit Media Interface Both Tram net interfaces use identical transceiver circuits dual differential line driver receiver U2 and U3 is used for each interface This device contains two driver receiver pairs One pair is used to perform the TTL to differential signal level conversion between the digital logic and isolation transformers which couple to the Tram net media The other receiver is used to imp
96. iature D connector T he two configurations account for the two versions of the PCB assembly which are available the 001 and 002 respectively A DC DC converter U 1 is used to generate 5 V 15 V power from the 16 5 V source Since 5 V output is limited to considerably less than its maximum capability the 15 V outputs are capable of delivering a greater maximum current than specified in the data sheets The output of the DC DC converter 15 limited to 25 W total The DC DC converter has a soft start circuit at its input to limit the current surge when a 4 housing is connected while the patient monitor is powered 7 6 Tram rac 4 Housing Revision 2002029 021 4 Interface PCB Theory of Operation Signal Conditioning The 001 version provides signal conditioning with choke T1 and MOS FET Q1 NOTE The Tram net IN connector has a plastic shell when the power supply 15 installed to isolate chassis ground Otherwise it has metal shell to connect the chassis ground of the monitor Use plastic screws to secure the plastic connector to avoid making the chassis ground connection Revision Tram rac 4 Housing 7 7 2002029 021 4 Interface PCB Indicators and Controls Indicators and Controls Listed below is the function of any indicators switches jumpers or controls located on the Tram rac4 Interface PCB There are no calibration procedure
97. ic VariCath VARIDEX VAS and Vision Care Filter are trademarks of GE Medical Systems nformation Technologies registered in the United States Patent and Trademark Office 1251 1551 Access AccuSpeak ADVANTAGE BAM BODYTRODE Cardiomatic CardioSpeak CD TELEMETRY LAN CENTRALSCOPE Corolation EDIC EK Pro Event Link Cirrus Event Link Cumulus Event Link Nimbus HI RES ICMMS IMAGE VAULT IMPACT wf INTER LEAD IQA LIFEWATCH Managed Use MARQUETTE PRISM MARQU RESPON MicroSmart MMS MRT MUSE CardioWindow NST PRO NAUTILUS O SENSOR Octanet OMRS PHi Res Premium Prism QUIK CONNECT V QUICK CONNECT QT Guard SMART PAC SMARTLOOK Spiral Lok Sweetheart UNITY Universal Waterfall Walkmom are trademarks of GE Medical Systems Information Technologies Medical Systems Information Technologies 2001 All rights reserved T 2 Tram rac 4A Housing Revision A 2002029 021 21 February 2001 Introduction 1 1 Manual Information 1 3 REVISION 1 3 Manual 5 et A By dp 1 3 Related Manuals 14 Tech MEMOS nosse 14 Safety Information 1 5 Responsibility ofthe e 1 5 Intende
98. ically waveform Tram or SP 02 4 WF OUT62 Analog 10V O WAVEFORM OUTPUT 6 Analog waveform output number 6 slot 1 waveform A 5 WF_0UT82 Analog 10V O OUTPUT NO 8 Analog waveform output number 8 slot 2 waveform or Tram ART 1 or BP 1 6 WF 0UT102 Analog 4 10V 0 OUTPUT NO 10 Analog waveform output 1 number 10 5101 3 waveform 7 WF 001122 Analog 10V O WAVEFORM OUTPUT NO 12 Analog waveform output number 12 slot 4 waveform A 8 AGND 0v O ANALOG GROUND Signal return for WF OUT6 through WF 00113 9 WF Analog 10V O OUTPUT NO 1 Analog waveform output number 1 typically waveform Tram ECG 10 WF OUT3 Analog 10V O OUTPUT NO 3 Analog waveform output number 3 typically waveform Tram ECG V 11 WF 0UT51 Analog 10V O WAVEFORM OUTPUT 5 Analog waveform output 1 number 5 slot 2 waveform or Tram BP4 or RESP 12 WF 0017 Analog 10V O WAVEFORM OUTPUT NO 7 Analog waveform output 1 number 7 slot 1 waveform 13 WF Analog 10V O OUTPUT NO 9 Analog waveform output B number 9 slot 2 waveform B or Tram BP2 or SPO2 14 WF OUT112 Analog 10V O WAVEFORM OUTPUT 11 Analog waveform output 1 number 11 slot 3 waveform 15 WF 007132 Analog 10V O WAVEFORM OUTPUT 13 Analog waveform output number 13 slot 4 waveform B Shell CGND 0v O CHASSIS GROUND Chass
99. ice Information Service Information Service Requirements Follow the service requirements listed below m Refer equipment servicing to GE Medical Systems Information Technologies authorized service personnel only m Any unauthorized attempt to repair equipment under warranty voids that warranty m tistheuser sresponsibility to report the need for service to GE Medical Systems Information Technologies or to one of their authorized agents m Failureon the part of the responsible individual hospital or institution using this equipment to implement a satisfactory maintenance schedule may cause undue equipment failure and possible health hazards m Regular maintenance irrespective of usage is essential to ensure that the equipment will always be functional when required Equipment Identification Every GE Medical Systems Information Technologies device has unique serial number for identification The serial number appears on the product label on the base of each unit under the Trim knob control D 1 XX 0005 G Product Sequence Manufactured Manufactured Product Code Number Division Device Characteristics A January 1 2001 Two character Manufacturing F Diagnostic One or 2 letters that further B February 2 2002 product descriptor number of total G Monitoring describe the unit for example C March 3 2003 ST Tram rac 4A units Freiburg P prototype not conforming D
100. ing on TRAM net m On mostly steady TRAM RAC connected m Flickers low TRAM net not connected l hear myself talk DS4 Green Transmit Enable I am talking on TRAM net m Flickers occasionally when talking m continuous while graphing DS 3 Yellow Error Detect detect an error on this PCB m Off normal operation DS2 Red RAC COMM 80C152 COMM Processor is OK m Flashes with DS 1 twice per second normal operation DS1 Red RAC DAS 80 31 DAS Processor is OK m Flashes with DS2 twice per second normal operation NOTE 14 hear talking on my TRAM net LED flashes withthe 1 amtalking on TRAM net LED and alone when someone else is talking 4 8 Tram rac 4A Housing Revision A 2002029 021 5 Housing evision Tram rac 4A Housing 2002029 021 your notes 5 2 Tram rac 4 Housing Revision A 2002029 021 Tram rac 4A Housing Theory of Operation Theory of Operation Overview Tram rac 4A housing is a housing for a Tram module and two additional discrete parameter modules or no Tram module and four discrete parameter modules It connects the modules with the patient monitor via the Tram net communication network Thelight emitting diode ED on the front bezel is used as an indicator of proper operation It normally illuminates to indicate power is applied but it may be disabled under microprocessor control TheTram net hub connector at the rear of the Tram rac 4A ho
101. is shield ground 5 14 Tram rac 4A Housing Revision A 2002029 021 Tram rac 4A Housing Exploded View 900031 005 006 Exploded View 900031 005 006 1 of 5 2 PLACES ORIENT AS SHOWN PLACE BAGGED ITEMS INTO VOID OF ASSEMBLED PRODUCT o PLACES ORIENT AS SHOWN 97 PLACE ASSEMBLED UNIT INTO BAG PACKAGING DETAIL W O POWER SUPPLY SCALE 1 4 900031 005 PLACE BAGGED ITEMS INTO VOID OF o ASSEMBLED PRODUCT PACKAGING DETAIL W POWER SUPPLY SCALE 1 4 900031 006 Revision A Tram rac 4A Housing 5 15 2002029 021 Tram rac 4A Housing Exploded View 900031 005 006 205 lt SEE DETAIL 6 PLACES TORQUE TO 9 Z 3 54 5 2 2 Z SEE DETAIL 7 28 2 2 22 oF Zi 2 2 7 12 2 22 6 PLACES 2 5 16 4 Housing Revision 2002029 021 Tram rac 4A Housing Exploded View 900031 005 006 3 of 5 ANN p di 7 L LZ 2 2 229 2 2 27 TSN Ze M 953 NEAR SIDE 2 9 FAR SIDE Z TORQUE TO 7 3 54 5 IN LBS NOTES 1 FOR 005 UNITS MARK LABEL WITH DESCRIPTION RAC4A W O SERIAL NUMBER AND BAR CODE FOR 006 UNITS MARK LABEL WITH DESCRIPTION RAC4A SERIAL NUMBER AND BAR CODE 2 LOOSE ITEMS MAY BE SHIPPED WITH THE UNIT IF SPACE PERMITS OR PACKAGED AND SHIPPED SEPARATELY Revision Tram rac 4 Housing 5 17 2002029 021 Tram rac 4A Housing Exploded View 900031 005
102. ive earth pin in the MAINS PLUG and any ACCESSIBLE METAL PART whichis PROTECTIVELY EARTHED shall not exceed 0 2 ohms When taking this measurement move the customer s power cord around no fluctuations in resistance should be observed Ground Earth Wire Leakage Current Tests Perform this test to measure current leakage through the ground earth wire of the equipment during normal operation 1 Set the leakage tester switches as follows GND switch OPEN Polarity switch Power switch OFF 3 8 Tram rac 4 Housing Revision 2002029 021 Maintenance Electrical Safety Tests 2 ConnecttheDMM tothe METER jacks the leakage tester Set the DMM tomeasure AC millivolts 3 Connect the power cord of the device under test to the power receptacle on the rear of the leakage tester NOTE The device under test is to be tested at its normal operating voltage Set the leakage tester power switch to ON Set the power switch of the device under test to ON Read the current leakage indicated DMM If the reading is greater than the appropriate specification below the device under test fails and should be repaired and tested again 300 0 3 volts on the DMM and the device under test is powered from 100 120 V 50 60 Hz uA 0 3 volts on the DMM and the device under test is powered from a centered tapped 200 240 V 50 60 Hz single phase circuit 500 0 5 volts o
103. lement a squelch receiver The squelch receiver biases its input away from the idle line voltage level to reject noise received on the data lines This makes the receiver less sensitive to noise but also distorts the shape of the waveform received by the squelch receiver The waveshape is not important since the squelch receiver is only used by the hub circuit to detect activity Once the hub circuit detects activity the normal receiver interprets the signals The squelch receiver is biased negatively by 250 mV minimum using an external resistor divider network Thetransceiver circuit is isolated from the media twisted pair wire by a pulse transformer T2 The receive channel is terminated in 110 ohms the characteristic impedance of the media The 4 housing attaches to the media 9 pin subminiature D type connector male connector on the Tram rac 4 housing interfaces to the upper level hub a female connector interfaces to the lower level device or hub Power Generation and Distribution DC DC Converter The Interface PCB receives 16 5 V power into the Tram rac housing converts it to 5 V 15 V and then distributes all four voltages to other parts of the Tram rac 4 housing T he 16 5 V power is received either from the patient monitor via the upper level hub Tram net connector or from the Tram rac power supply which connects directly tothe interface PCB via a 15 pin submin
104. llected it is packaged and sent to other devices using the Tram net communication network The Tram module does not use discrete parameter synchronous serial communication but communicates directly on the Tram net communication network without intervention by any of the Tram rac processors Two channels of analog data from each of the module slots are sampled 240 times a second The analog data is converted to digital data with an input range of 10 0 and a resolution of 12 bits 4 9 mV The offset of the analog acquisition circuitry is adjusted continuously by RAC 4A hardware The data acquisition bandwidth and system accuracy is determined by the specific module used A total of 13 software dependent analog output signals are provided Eight analog outputs are generated by the data acquisition microprocessor which typically reproduces the eight analog data input channels from the modules slot T he eight analog outputs are buffered so that cables up to 6000 feet long may be driven The maximum analog output gain error is 2 and the offset error zero level error is typically less than 18 mV 40 mV maximum Five of the analog outputs are generated by the Tram module used in the Tram rac 4 housing Two special analog outputs typically and BP4 signals are provided from the second slot to accommodate a Tram module otherwise all slots are equivalent Three more analog signals typically ECG II and ECG V signals
105. ls of the Tram net network Each of these functions is discussed next in detail Block Diagram The architecture of the Tram rac 4A Interface PCB is illustrated in the block diagram below Analog Analog Demultiplexer Morg WF OUT6 13 DAC_D0 11 P 8 Circuit WF OUT6 13 U10 U4 U5 05 To 08 911 Analog AnalogOutput Control Output Signal Connector Conditioning From amp Protection WF OUT1 5 gt Processor Acquisition PCB Driver Tram net Tram net Communicaton Receive Signal Signals U3 Conditioning Out amp Protection Driver Tram net External Tram net Communicaton Channel Auxiliary M Receive Signals U2 In Revision Tram rac 4A Housing 7 3 2002029 021 4 Interface PCB Theory Operation Analog Waveform Generation In addition to five analog waveforms provided by the Processor Acquisition PCB the Interface PCB produces eight analog waveform outputs These waveforms are generated using an 12 bit digital to analog converter DAC U 7 The DAS control processor on the Tram rac Processor Acquisition PCB controls DAC U 7 to produce sequential samples of the eight analog signals Each analog signal consists of 240 samples per second so a total of 1920 samples are output each second The individual analog signals are demultiplexed from the output of the DAC by analog multiplexer U
106. mmunication support only B12 5V 5V O 5 digital power 13 B13 15V 15V O 15 analog power 14 15 15V 15V O 15 analog power 15 B15 AGND OV O Analog power return Revision Tram rac 4A Housing 6 13 2002029 021 Tram rac Processor Acquisition PCB Input and Output Connectors Interface PCB J5 The TRAM RAC 4A Processor Acquisition P CB 2004288 001 interfaces tothe TRAM RAC 4A Interface PCB 800516 001 through a 60 pin connector J 5 internal tothe TRAM RAC 4A The connector pin out is defined below The J 5 connector used on the Processor Acquisition P CB is a 60 pin 0 1 inch center two row header 410333 001 Table 3 J5 60 Pin Connector to TRAM RAC 4A Interface PCB Pin S Signal Signal Level 1 0 Signal Description 1 3 5 7 9 11 GND OV Ground Power return for 16 5V supply 2 4 6 8 10 12 16 5V 16 5V 16 5 power 16 5v power input for module use 13 EXT_RXD_DN TTL External NET downward path receiver data sourced from the host 8000 9500 14 EXT_SQ_DN TTL External TRAM NET downward path squelch data 15 EXT_TXD_UP TTL O External TRAM NET upward path transmit data generally routed to the host 8000M 9500 16 EXT_DEN_UP TTL O External TRAM NET upward path driver enable 17 EXT_RXD_UP TTL External TRAM NET upward path receiver data sourced from the Interface PCBJ9 18 EXT SQ UP TTL External TRAM NET
107. n 05 1 34 dn 0 8 1X3 4 NO 05 1X3 ter NU 05 1X3 4 NO OXE 1x3 er r ASNA Q v 5 17 AND 20 5 ES 31 20 4 97 2518 5 20 4 Vivo 1VIH3S 20 3004 VIT k 96 2vl 05 16 9NH v3H 9 DY 4 STT SVO TT 33917 0083 E6 3lvusrv 4 89 XXNVIS 832994 V1V0 0v01 GOW N30 JNI 707 INL 99 11015 YN3 421 861 21015 YNI Ni dc ST 015 Ni dci zT 71015 YNI Nl d 95 11015 00 d 62 _ 018 0 94 2 E101S_OOW 42 8 71075 OOW d 8 20 1538183 00 7 9T43W ision Rev Tram rac 4A Housing 6 24 2002029 021 2004289 001 iagram D ic Schemat Tram rac 4A Processor Acquisition PCB VNISIBO 0 2 6 30 13365 100 6827002 nur 01151003 805532084 SHID0 1ONHO31 NOLLYROIOANT 581545 TYOIGHF HD Sf AOS 01 580112 4 2 11 SOYMV308JIN NI S301VA 32 112 4 2 11 M9T T SWHO NI SINIYA 32NVISIS3H 11 3 112 3 V NY 031312345 351 83 10 SS31Nn 7 z 03 01104 lVN9IS puo M66AV8 98 2 4 M66AV8 0182 DM S1n0 3M 66A v8 4 7992 z T 6AY8 z T TINO JA66AYG
108. n the DM and the device under test is powered from a non center tapped 200 240 V 50 60 Hz single phase circuit NOTE Center tapped and non center tapped circuits produce different leakage currents and the UL and limits are different Set the polarity switch on the leakage tester to RVS reverse Read the current leakage indicated on DMM If thereading is greater than the appropriate specification below the device under test fails and should be repaired and tested again 300 0 3 volts on the DM and the device under test is powered from 100 120 V 50 60 Hz 300 uA 0 3 volts on the DM and the device under test is powered from a centered tapped 200 240 V 50 60 Hz single phase circuit 500 0 5 volts on the DM and the device under test is powered from a non center tapped 200 240 V 50 60 Hz single phase circuit Center tapped and non center tapped circuits produce different leakage currents and the UL and IEC limits are different Revision A Tram rac 4A Housing 3 9 2002029 021 Maintenance Electrical Safety Tests 9 Set the leakage tester power switch to OFF LEAKAGE TESTER PARTIAL SCHEMATIC HIGH 5 POWER CORD 5 LOW GND M amp DEVICE UNDER RVS TEST GND M D MEASURING DEVICE NOTE The MD measuring device is the circuitry defined by the appropriat
109. ners used as connections to ground panes on PCBs Power Source m Faulty wiring especially AC outlet m Circuit not dedicated to system Power source problems can cause static discharge resetting problems and noise WARNING Solder multilayer and surface mount PCB assemblies at your own risk I mproper repair methods can damage the PCB assemblies even further Only qualified service personnel with the proper laboratory equi pment should attempt to repair PCB assemblies Revision A Tram rac 4A Housing 4 7 2002029 021 Troubleshooting LED Troubleshooting Chart Tram rac 4A LED Troubleshooting Chart Use the following chart to determine if the Tram rac 4A is functioning properly This chart refers to LEDs on the Processor Acquisition PCB For problems refer to the appropriate manual for more information about troubleshooting a patient monitor and Tram rac housing together Service manuals are listed in Table 2 Service Documents on page 1 4 Table 1 Processor Acquisition PCB Indicators LED Color Signal Name Function Condition DS6 Green Power Indicator Proper Operation m On Continuous normal operation m Visible on Tram rac 4A front bezel m Flashing Quickly 2Hz ADC Error lower left m Flashing Slowly 0 5Hz watchdog timeouts m LED Off power off supply fault RAC FPGA configuration fault DS5 Red Network Activity hear talk
110. nformation Monitor Service Manual Table 3 Operator Documents Name Tram Critical Care Monitor Operator s Manual Centralscope Central Station and CD Telemetry LAN Monitoring System Operator s Manual Solar 7000 8000 Patient Monitor Operator s Manual Solar 8000M Patient Monitor Operator s Manual Solar 9500 Information Monitor Operator s Manual Tech Memos GE Medical Systems Information Technologies Service issues technical memos that aid service personnel in servicing and maintaining the equipment Tech Memos supply important information about changes to the equipment typical problems and how to solve those problems Tech Memos are also written to describe hardware and software upgrades Tech Memos are automatically distributed to all GE Medical Systems Information Technologies Field Service personnel and available to customers by subscription Contact Technical Support for more information or to subscribe F or the address or telephone number see How to Reach Us TRAM RAC 4A Revision A 2002029 021 Introduction Safety Information Safety Information Responsibility of the Manufacturer GE Medical Systems Information T echnologies is responsible for the effects of safety reliability and performance only if m Assembly operations extensions readjustments modifications or repairs are carried out by persons authorized by Information Technologi es m The elec
111. ng 2002029 021 Tram rac 4 Processor Acquisition PCB Schematic Diagram 2004289 001 your notes 6 30 Tram rac 4 Housing Revision A 2002029 021 1 Interface evision Tram rac 4A Housing 2002029 021 your notes 7 2 Tram rac 4 Housing Revision A 2002029 021 4 Interface PCB Theory Operation Theory of Operation Overview Several functions are performed by the Tram rac 4 Interface PCB Two Tram net connections and interfaces are provided one for the patient monitor data and one for an auxiliary device The analog output circuitry to generate eight analog waveforms and output connector are provided Five additional analog outputs are supplied from the data acquisition PCB tothe analog output connector The PCB may be configured either to take input power from a patient monitor or to accept the AC power supply 002 version A DC DC converter residing on this PCB produces V 15 V power for the Tram rac 4 housing and discrete parameter modules This PCB is connected to the Processor Acquisition PCB within the Tram rac 4A housing and is connected tothe AC power supply if it is the 002 version The functions of the Tram rac 4A Interface PCB include generation of analog waveform outputs conversion of DC power for the Tram rac 4A housing and providing interfaces to the upper and lower leve
112. onnector J11 15 Pin Analog Output Connector NOTE The Tram module must be in the top slot to receive the Tram signals listed below For dual BP discrete parameter modules waveform is from the right connector and waveform is from the left connector NOTE The superscript number 1 indicates that this signal remains unchanged after entering the Tram rac 4A housing and is controlled by Tram module software NOTE The superscript number 2 indicates that this signal is generated by the DAC on the interface PCB assembly Pin Signal Name Signal Level Type Signal Description 1 WF OV O WAVEFORM RETURN Signal return for WF_OUT1 through WF_0UT5 2 WF 01121 Analog 10V O OUTPUT 2 Analog waveform output 7 number 2 typically waveform Tram Trace 1 3 WF_0UT4 Analog 4 10V O WAVEFORM OUTPUT 4 Analog waveform output number 4 typically waveform Tram or SP 02 4 WF OUT62 Analog 10V O WAVEFORM OUTPUT 6 Analog waveform output number 6 slot 1 waveform A 5 WF_0UT82 Analog 10V O OUTPUT NO 8 Analog waveform output number 8 slot 2 waveform or Tram ART 1 or BP 1 6 WF 0UT102 Analog 4 10V 0 OUTPUT NO 10 Analog waveform output 1 number 10 5101 3 waveform 7 WF 001122 Analog 10V O WAVEFORM OUTPUT NO 12 Analog waveform output number 12 slot
113. ontrol of the Tram module Typically this waveform is the first displayed trace on the Tramscope monitor A8 MOD DATA LATCH Open Drain O Module Data Latch Signal is the discrete parameter module 1K 5V pull up data latch strobe used in the synchronous serial shift register protocol After eight bits of input data have been shifted into the module using the module data clock this signal strobes the input data into the module s data latch B8 WF OUT3 Analog I O Waveform Output no 3 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the ECG lead V signal A9134 AGND 0v O Analog Shield Ground Discrete parameter modules may use this pin to terminate their shield ground A92 WF_OUT4 Analog Waveform Output no 4 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the signal 6 12 Tram rac 4A Housing Revision A 2002029 021 Tram rac Processor Acquisition PCB Input and Output Connectors Table 2 1 4 30 Pin Connectors to Parameter Module Slots
114. owing describes the logic functions in the RAC FPGA that have not been included in other sections Connector J 6 can be used to reprogram the contents of the serial configuration EEPROM when the RAC 4A is powered up COMM and DAS Processor Handshake Signals The RAC FPGA logic implements the communication latches between the COMM 80C152 and DAS 80C31 processors When one of the processors has data to pass to the other processor the data is written to the 2k byte dual port memory The processor sending data generates an interrupt signal DAS ATTNCK inform the receiving processor that data is available The interrupt signals are latched in the FPGA and the latched signals DAS RDY ATTN_DAS or TNC_RDY are output to both processors The processor receiving the data asserts the ACK_TNC or DAS_TNC signal to clear the interrupt latch allowing the sending processor to send more data if required DAS_PROM and TNC_PROM Delay Logic The RAC FPGA delays the DAS PROM and TNC_PROM signals from the DAS and COMM processors The delayed DAS PROM DELAY and TNC_PROM _DELAY signals determine the code execution memory device for each processor When DAS_PROM_DELAY is high the 80C31 executes code from the 32K byte FLASH device Code is executed from dual port memory when DAS PROM is low during FLASH memory reprogramming When TNC_PROM_DELAY is high the 80C152 executes code from the 32K byte FLASH device
115. r Acquisition PCB Theory of Operation Clock Generation TRAM net or Serial Shift Register data and enable from each module MDO_SLOT4 1 RAC FPGA Data MOD DATA OUT Serial data from TN SLOTA 1 TRAM net upward data from auxiliary external port Driver transformer and external J10 located on the Interface PCB Select EXT RXD UP UP RX f EXT SQ UP m r L RAC_TXD Carrier Sense Blinding Timer ollision Detect RAC FPGA Loopback and Headhub Functions gt Collision rrier Pattern Generation Transmit data and transmit enable signals from the 80C152 U3 TRAM net node modules to 80C31 _ EXT _ UP_TX EXT DEN TRAM net upward data to host Driver transformer and external J9 are located on the Interface PCB FIGURE 2 Upward TRAM net Path and Serial Shift Register Data From Register data to each module slot DN TX Modules Two active high Serial Shift Register enable signals to each module slot MOD EN CHE Active low TRAM net enables from RAC FPGA each module slot Serial Shift Register data from the 80C31 U18 U13 TRAM net or Serial Shift SLOTA 1 Data MOD_LOADIDATA_IN Select
116. r data on the signals Two analog signals from each module slot are routed to the U11 DG408 multiplexer second DG408 multiplexer U 12 has ground and 5V connected to the inputs Multiplexer signal selection is controlled by the 80C31 and logic the RAC FPGA The analog waveform signals have a range of 10V Noise Filter and Buffer Amplifier The U11 and U12 DG408 multiplexer outputs are connected to 24 9K ohm resistors T he resistors connect to 470 C34 to form low pass filter and OR the multiplexer outputs together T he resistor capacitor filter removes high frequency noise from the selected input signal before the buffer amplifier 09 stage The MI C6211 unity gain buffer amplifier U 9 drives the analog to digital converter ADC input signal with the filtered analog waveform ground or 5V Analog to Digital Converter The Processor Acquisition PCB contains an AD7895 analog to digital converter 08 The serial 12 bit analog to digital converter ADC has bipolar input range of U 7 is 2 5V precision external reference for the ADC that provides a 0 29 maximum gain error The U 6 linear regulator generates 5V for use by the ADC and the 2 5V reference An analog to digital conversion is initiated when the RAC F PGA receives an ADC convert command from the 80C31 processor The RAC FPGA generates an active low pulse on the ADC_CONV signal to start the conversion that requi
117. res 3 8us The RAC FPGA clocks serial data from the ADC and converts it to parallel form for read access by the 80C31 The 80C31 controls the conversion process timing by switching the multitiplexers commanding conversions and reading the conversion result The 5V supply from the Interface PCB is converted to verify the conversion process is operating properly Conversions are to performed on ground through the U12 multiplexer to allow the conversion offset correction in the FPGA Offset errors in the circuit are removed from all waveform conversion results read by the 80C31 Software checks ground conversion results to verify offset remains within reasonable limits 6 6 Tram rac 4A Housing Revision A 2002029 021 Tram rac 4 Processor Acquisition PCB Theory of Operation When the ground or 5V conversion results are out of tolerance the stops operation and rapidly flashes the green front panel LED RAC Field Programmable Gate Array FPGA U13 The FPGA 013 is an Altera static random access memory type with logic configured by the contents of a 512K bit serial EEPROM 014 The EEPROM clocks a serial bit stream into the FPGA immediately after power up The configured FPGA contains miscellaneous glue logic a 2K byte dual port a six port TRAM net communications hub shift register communications logic memory decode analog output control logic and analog to digital conversion control logic The foll
118. s due to the complexity of the circuitry Table 1 Interface PCB Indicators LED Color Signal Name Function Normal Condition DS1 Red Network Activity from I hear talking on Tram net m Flickers ON only if auxiliary device Auxiliary Device connected m ON steady while graphing DS2 Red Transmit Enable to I am talking on Tram net m Flickers ON only if auxiliary device Auxiliary Device connected m ON steady while graphing DS3 Red Network Activity from hear talking on Tram net m Flickers ON Monitor m ON steady while graphing DS4 Red Transmit Enable to I am talking on Tram net m Flickers ON Monitor m ON steady while graphing NOTE 1Because I hear when am talking the talking LED flashes with the hearing LED but the hearing LED also flashes alone when it hears someone else talking 7 8 Tram rac 4A Housing 2002029 021 Revision A Tram rac 4 Interface PCB Input and Output Connectors Input and Output Connectors The following tables are organized by connector for all connections to the Tram rac4 Interface PCB Each signal includes information such as symbol name pin number function and whether it is an input or output Table 2 J5 60 Pin Connector to Processor Acquisition PCB Pin Signal Name Signal Level Signal Description 1 3 5 7 9 11 GND 0 0
119. s given for each signal Module Interface 41 44 The 4A Processor Acquisition PCB provides four 30 pin module connectors 1866 030 that interface with up to four modules in the Tram rac 4A The connector numbers J 1 J 4 correspond to slots 1 4 m The superscript number after the pin number indicates which slot s provide the given 5 5 Signal names containing numbers 1 4 indicate that the signals to each slot listed are independent m Signals listed with a single pin number without a superscript indicate the signal is common to all four slots Table 2 J1 J4 30 Connectors to Parameter Module Slots Pin Signal Name Signal Level 10 Signal Description A1 GND OV 0 Ground m Analog discrete parameter modules reference for the output m Tram series modules 16 5V power return 8114 WF_A1 4 Analog Waveform Channels A1 4 Analog waveforms from channel 10V slots 1 4 Art or BP 1 signal for TRAM series modules 214 1 4 Open Drain 0 Module Channels 1 4 enable This signal is the module 1K 5V pullup enable for channel slot 1 4 of the discrete parameter modules Signal is asserted high to enable the module to communicate via the synchronous serial shift register protocol B214 MOD_EN_A1 4 Open Drain 0 Module Channels A1 4 enable Signal is the module enable 1K 5V pull up for channel A slots 1 4 of the dis
120. static charge you may have built up before handling semiconductors or assemblies containing semiconductors m grounded antistatic wristband or heelstrap should be worn at all times when repairing assemblies containing semiconductors Use only properly grounded soldering and test equipment m Usea staticfree surface when working on assemblies containing semiconductors m remove semiconductors or assemblies containing semiconductors from antistatic containers bags until needed m Make sure power to an assembly is turned off before removing inserting a semiconductor m Do NOT slide semiconductors or assemblies containing semi conductors across any surface DoNOT touch semiconductor leads unless absolutely necessary Semi conductors and assemblies containing semiconductors should be stored only in antistatic bags or boxes Revision A Tram rac 4A Housing 3 3 2002029 021 Maintenance Maintenance Schedule Maintenance Schedule General An effective maintenance schedule should be established for the Tram 4 The schedule should include inspection general cleaning performance testing and safety testing on a regular basis Safety tests are recommended to be performed every twelve months or if any internal components have been altered WARNING A failure on the part of the responsible individual hospital or institution employing the uses of this monitoring equipment to implement
121. the module s output shift register prior to transferring data out of the module to the Tram Rac 4A housing When the shift register communication protocol is used active low binary input data is transferred to the module s input shift register on this signal with the falling edge ofthe MOD DATA CLOCK signal When Tram net communication is used input data on this signal is Manchester encoded and does not require a separate clock B6 WF OUTI Analog I O Waveform Output no 1 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software control of the Tram module Typically this waveform is the ECG lead II signal 71 4 MDO_SLOT1 4 TTL Module Data Out Signal is the module data output for slots 1 4 When the discrete parameter synchronous serial shift register communication protocol is used active low binary output data is transferred from the module s output shift register on this signal with the falling edge of the module data clock signal Otherwise when the Tram net communication is used output data on this signal is Manchester encoded and requires no separate clock 87 WF 0012 I O Waveform Output no 2 The Tram series modules generate 10V this signal for use by other modules This signal is also output to the analog output connector The waveform signal generated is under software c
122. tion 1 7 8 Shell GND OV O GROUND Power return for 16 5V supply and chassis ground reference 2 9 15V 15V O 15V POWER 15 V power 3 10 15V 15V O 415 POWER 15 V power 4 11 AGND OV O ANALOG GROUND 15 V and 15 V power return 5 12 HV HV 0 5V POWER 5 V power 6 GND_CONV 0v O CONVERTER GROUND 16 5 V power return for DC DC converter 13 16 5 CONV 16 5V 0 CONVERTER 16 5V POWER 16 5 V power for DC DC converter 14 15 16 5V 16 5V 0 16 5V POWER 16 5 V power Table 4 Connector P2 3 Pin Connector to AC Power Source Pin Signal Name Signal Level Signal Description L L 0 280 VAC LINE 0 to 280V AC from wall receptacle N N 0 3 NEUTRAL 0 to AC from wall receptacle G G OV CHASSIS GROUND OV DC from wall receptacle Revision A Tram rac 4A Housing 8 5 2002029 021 Tram rac 4A Power Supply P art Location Diagram 6123 211 Part Location Diagram PN 6123 211A 2 og de m 2 8 8 2 TNR or M5 29 c1 ae ONE x R1 C14 F1 C D1 L G N C8 gt 21 PCB Assembly SESS aO C105C 9 01047 E R101 R102 Daughter PCB Assembly 8
123. tor m aTram ne hub m another Tram rac housing if this Tram rac housing has a power supply The center Tram net connector may be connected to the following m aremote control or m toanother Tram rac 4A housing with a power supply NOTE The Tram rac housing furthest from the monitor must have a power supply If older models of Tram rac housing are used Tram net hub is necessary Shown below are examples of how to connect dual Tram rac housing toa monitor dip es gt d ___ See Accessories 3 13 for cables cable part numbers Revision 4 Housing 2 9 2002029 021 General Information Equipment Overview Analog Output Connection The analog out connector is provided for customized uses for other peripheral devices The yellow color coded 15 pin connector provides an analog output waveform signal 45 T 13 12 D ooocccoeoc Note the parameter numbers indicated on the front of the Tram rac 4A housing 2 10 Tram rac 4A Housing Revision A 2002029 021 General Information Equipment Overview When a Tram or discrete parameter module is inserted into the housing the slot n
124. trical installation of the relevant room complies with the requirements of the appropriate regulations m The equipment is used in accordance with the instructions for use Intended Use This device is intended for use under the direct supervision of a licensed health care practitioner To ensure patient safety use only parts and accessories manufactured recommended by GE Medical Systems Information Technologies Contact I nformation Technologies for information before connecting any devices to this eguipment that are not recommended in this manual Revision A TRAM RAC 4A 1 5 2002029 021 Introduction Safety Information Definitions Warnings Cautions Notes Warnings cautions and notes are used throughout this manual to designate a degree or level of hazardous situations Hazard is defined as a source of potential injury to a person NOTE DANGER indicates an imminent hazard which if not avoided will result in death or serious injury WARNING indicates a potential hazard or unsafe practice which if not avoided could result in death or serious injury CAUTION indicates a potential hazard or unsafe practice which if not avoided could result in minor personal injury or product property damage provides application tips or other useful information to assure that you get the most from your equipment TRAM RAC 4 Revision 2002029 021 Introduction
125. umber of the parameter and its analog output waveform is available at a designated pin of the analog out connector Refer to the list below NOTE The Tram module must the top slot in order to receive the Tram signals listed below Table 1 Analog Output Signals et cos Signal Name m Pin1 Signal Ground for Tram Waveforms gt Pin2 Trace 1 Tram Pin Tram BP3 or SPO Value Tram Pin 42 Slot 1 Discrete Module Waveform A 1 Pin 5 Tram ART 1 or BP1 Tram Pin 6 Slot 3 Discrete Module Waveform A 6 Pin 7 Slot 4 Discrete Module Waveform A 8 Pin 8 Signal Ground for Discrete Module Waveforms Pin 9 Tram ECG Il Tram Pin 10 Tram ECG V Tram Pin 11 Tram BP4 or RESP Tram Pin 122 Slot 1 Discrete Module Waveform B 2 Pin 13 Tram BP2 or SPO Waveform Tram Pin 14 Slot 3 Discrete Module Waveform B 5 Pin 15 Slot 4 Discrete Module Waveform B 7 NOTE The superscript number 1 indicates that this signal remains unchanged after entering the Tram rac 4A housing and is controlled by Tram module software All other signals are generated by the DAC digital to analog converter on the Tram rac 4 interface PCB assembly The asterisk indicates reserved for future use Revision A Tram rac 4A Housing 2002029 021 General Information Equipment Overview Power Supply Connection The power supply is required where one or more of the following conditions apply The Tram
126. upward squelch data 19 EXT TXD DN TTL O External TRAM NET downward path transmit data generally routed to the Interface PCB J 10 20 EXT DEN DN TTL O downward path driver 21 22 23 24 25 DAC 00 12 TTL O D A converter data from 80C 31 to the DAC on the Interface PCB 26 27 28 31 32 33 34 35 36 37 OUT SEL2 0 TTL O Analog output channel select 38 ANA OUT TTL O Analog output demultiplexer select 39 DAC TTL Digital To Analog converter device select 29 41 43 45 GND OV 5V Ground 30 40 42 44 46 5V Power 47 49 51 53 AGND OV Analog Ground 48 50 15V 15V 15V Power 52 54 15V 15V 15V Power 55 WF_RTN 0V O Waveform output return numbers 1 through 5 56 57 58 59 60 WF 1 5 O These signals are waveform outputs numbers 1 through 5 Signals are 10 V generated modules routed through the this board to the Interface Board 6 14 Tram rac 4 Housing Revision A 2002029 021 Processor Acquisition PCB Input Output Connectors ISP Serial EEPROM Interface J6 The Processor Acquisition PCB provides a 10 pin header to interface with in system programming ISP equipment This equipment be used to reprogram the AT17LV512A serial EEPROM device that is used to configure the Altera EP1K 30 FPGA 013 The 10 pin header be accessed by removing
127. ur notes 6 2 Tram rac 4 Housing Revision A 2002029 021 Tram rac 4 Processor Acquisition PCB Theory of Operation Theory of Operation Overview The Processor Acquisition PCB pn 2004288 001 provides digital and analog circuits that acquire parameter data from modules inserted into the TRAM RAC 4 Parameter data from each module slot is obtained using TRAM net communications serial shift register communications and analog to digital conversion The Processor Acquisition PCB contains an 80C31 U 18 and an 80C152 03 eight bit processor m The 80C31is referred to as the data acquisition system DAS processor m The 80C152 is referred to as the communications COMM processor TRAM net communications hub in the RAC FPGA 013 combines four module slot TRAM net nodes the 80C152 node and an external auxiliary TRAM net node into one TRAM net port connection located on the back of the TRAM RAC 4A Static protection circuitry on the Processor Acquisition PCB prevents electro static discharge damage through module and external RAC connectors The Processor Acquisition PCB Architecture is shown in Figure 1 Functions shown in shaded blocks are contained in the RAC FPGA U13 The Processor Acquisition PCB interfaces to the TRAM RAC Interface PCB 800516 001 through a 60 pin connector Power required by the Processor Acquisition PCB is supplied by the TRAM RAC 4A Interface PCB 800516 Four module slot connectors J
128. using is for daisy chaining multiple Tram rac housings The analog output connector provided at the rear of the Tram rac 4A housing allows access to analog outputs from all modules Top Level Block Diagram Below is thetop level block diagram for the Tram rac 4A housing with and without the optional power supply PN 900031 006 uses a different Tram rac4A interface PCB assembly and has a connection for an additional power supply PN 900031 005 does not have a connection for a power supply TRAM PAC 4A 900031 005 006 1 TRAM MODULE TRAM RAC 4A i PROCESSOR TO FROM ACQUISITION SERIES 7000 MODULES 2004288 001 TO FROM SERIES 7000 MODULES 1 1 1 1 1 1 1 TRAM RAC4 1 INTERFACE i 800516 001 For 005 Only 800516 002 For 006 Only TO FROM TO FROM TO FROM HEL ANALOG TRAM NET TRAM NET OUTPUT COMMUNICATION COMMUNICATION With 006 Only Revision A Tram rac 4A Housing 5 3 2002029 021 Tram rac 4 Housing Theory of Operation Patient Data Acquisition Analog Output Signals Thefollowing paragraphs describe the basic functions of the Tram rac housing From each of the four discrete parameter module slots two channels of analog patient signals are acquired Digital patient data is acquired using the discrete parameter synchronous serial shift register communication interface As analog and digital data is co
129. z Revision Tram rac 4A Housing 2002029 021 General Information Technical Specifications Table 4 Environmental Specifications Description Tram rac housing 4 with power supply Power requirements 220 40 VAC 50 60 Hz single phase Power consumption 120 watts Low voltage shutdown 90 VAC 180 VAC Cooling Convection Heat dissipation 238 Btu hr 70 watts Tram rac housing 4A without power supply Maximum distance from monitor 3 67 20 ft Power requirements from monitor 16 5 35A housing Operation conditions m Ambient temperature m Relative humidity 10 to 35 50 F to 95 F 40 to 95 noncondensing Storage conditions m Temperature m Relative humidity 10 C to 50 C 14 F to 122 F 0 to 95 noncondensing Table 5 Physical Specifications Item Description Height 22 9 cm 9 0 in Width 14 5 cm 5 7 in Depth 33 5 cm 13 2 in Depth w power supply 38 4 cm 15 1 in Weight 2 9 kg 6 4 10 Weight w power supply 3 5 kg 7 9 Ib Table 6 Certification Item Description Safety standards UL544 listed IEC 601 certified Meets current ANSI AAMI safety and performance standards Complies with CSA No 125 2 14 Tram rac 4A Housing Revision A 2002029 021 3 Maintenance Revision Tram rac 4 Housing 2002029 021 3 1

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