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Service Manual - National Service Alliance

1. 9 Separate the MAIN BD and the IO BKT 2 W7 10 11 ig 16 14 18 16 Oe 14 23
2. y 4 Pe 2 POWER BD ASS Y REMOVAL 1 Remove the connector 9 CN2 of the AC Power cable 2 Remove the connector 2 CN4 of the main bd cable 3 Remove the connector 8 CN3 CN1 of the inverter cable 4 Remove one screw 1 from chassis 5 Remove two screws 2 from Power BD Ass y 6 Separate the Power BD Ass y 2 LJ Eh 41 P 10 3 MAIN BD ASS Y REMOVAL 1 Remove the connector 3 W7 of the LVDS signal cable 2 Remove the connector 49 W2 of the speaker cable 3 Remove the connector W3 of the Main BD cable 4 Remove the connector W10 of the keypad cable 5 Remove the connector 7 W9 of the IR cable 6 Remove four small screws 69 Four hexagon screws 0 Two screws 02 and one screw 63 from IO BKT 1 7 Separate the IO BKT 1 8 Remove eight screws 8 and three screws 9 from MAIN BD o Lj oum 5
3. EE RENE DT PE TORT UOCE E DET E 2 00 V 1001315 chi f EE 12 49 20 010 62 Tek itid Y TI XA He ATE rA uu pee ee Er AEE EEE T SE S E A TAT ES E LET EN E E EN LEN EE MM M ME NER RE AR RR ARE RR RR ARE RE NR 1 00 V 40 015 Ch f PITT 12 50 20 SCL 010 pin 13 CH2 SDA V 013 pin 14 Tek SSP Y 00V 1 00 100345 Ch2 T 0 19 40 CONFIDENTIAL DO COPY Chi 4 76 V Freq 15 74 2 29 Sep 2004 23 34 11 Chi 3 22 V Freq 20 31MH2 27 Sep 2004 00 46 06 1 Chi 2 78 V Freq 45 87kH2 Ch2 Freq 32 78kH2 1 Ch2Pk Pk 2 86 V 27 Sep 2004 01 00 00 Page 9 12 File No SG 0156 CHI VID VS U10 pin 57 CH2 VID HS U10 pin 56 Tek Run Trig d AT TTL RN Y NF NR RE 2 00 Ch2 2 00V 100 5 Chi f TEE 0240 20 CH1 VID DATA 010 pin 53 WU 2 00V 77778140 ons Chl 7 136 50 00 3 CH1 VID CLK2 010 pin 28 Tekstop 3 EWENENEETENEENWENRTENTCEEMERENNENEMEENRETEWERNTtUUCENENTEM 2 00 V M40 0ms chi f CONFIDENTIAL DO NOT COPY Ch1 3 68 V Freq He No pe
4. 5 U V ITEM PART NO DESCRIPTION QTY 1 1801 0117 2020 BEZEL V inc 30 ASS Y 1 2 1701 0414 7010 FUNCTION KEY Gateway 30 3 1947 1500 1910 FUNCTION KEY CR t 1 0 Gateway 5 5010 4 3830 0032 0156 DISPLAY BD ASS Y Gateway SHD 3010 5 1947 1500 1920 SPEAKER CR t 0 5 Gateway 5 3010 4 6 0335 5080 0170 SPEAKER 8ohm 5w 7 1947 1200 0820 ACETATE CLOTH TAPE 60 45 mm 8 1947 1200 0310 ACETATE CLOTH TAPE 27 75mm 1 9 1721 4103 0810 TAP SCREW TRFZ3 0 8 0L Zn Cc 8 10 1701 1500 0450 WIRE SADDLE CH 01B 16 11 1947 1500 0990 CR 328 5 1 mm 4 13 12 1947 1500 1010 CR 390 5 1 mm 2 15 1947 1700 0050 SHIELDING AL TAPE 50 0 40 0 2 14 0211 0300 0977 LCD MODULE 30 TFT T296XWO1 V 3 AU 1 15 1947 1200 0400 ACETATE CLOTH TAPE 20 45mm 3 16 0460 3430 0150 WH DF14 30S DF19G 20S 1571430 80mm 1 4 17 1947 2000 0690 AU PANEL RUBBER BLACK GW30 4 18 1701 0900 1440 AU INVERTER MYLAR Gateway 5 3010 1 19 1701 1500 0690 WIRE SADDLE CH 1 4 1 20 1947 2000 0750 RUBBER PAD 16 0 12 0 18 0t 2 21 1947 1500 1190 CMO PANEL SUPPOR 30 0 20 0 15 0 LM 30C 5 22 1712 0100 6650 CHASSIS FOR AUO Gateway 30 1 43 23 1947 1800 0090 GASKET BLOCK 17 25 25mm 10 24 1701 1500 0790 CABLE PROTECTOR BLACK UST 02 25 3830 0062 0157 POWER BD ASS YV30 1 V296W1 L14 1 26 1712 0100 4880 POWER SHIELDING TM 30A 1 27 3830 0042 0189 IR BD ASS Y Gateway SHD
5. Chi Pk Pk 5 16 V Ch1 A NO oi found 2 00 V 7M 00115 Chi 7 30 Sep 2004 12 50 00 18 57 41 CONFIDENTIAL DO NOT COPY Page 9 24 File No SG 0156 CHI F3 V50DC OFF Tek 4 40 V 600mV 4 325 3 985 Ch1 4 80 V chi d NO found i 290 Ni 1 00 5 Chi X 2 32 V 30 Sep 2004 50 00 19 03 23 CHI F2 V33DC ON Tek 3 20V 1 3 48V 1 46 5 9401 Chi 3 42 V Ch1 d No period found 2 00 V MU 00ms Chi 2 T 56 V 30 Sep 2004 12 49 40 19 06 55 CHI F2 V33DC OFF Ten i 2 60 je 720mV JA 1 165 j 1 06 s Chi 3 16 V 1 Freq Hz No period found DN 1 200 1 00 5 chi X IE 30 Sep 2004 12 49 40 19 10 24 CONFIDENTIAL DO NOT COPY Page 9 25 File No SG 0156 CHI LCD VOL ON Tek Prevu 1207 10 12 2 4 32 8us 18 31 645 Chi Pk Pk 13 2 i Ch1 deo No period found 5 00 V arto one chi 7 EXT 30 Sep 2004 0 50 20 19 41 22 Bes Prevu Chi Pk Pk 11 7 V Ch1 m NO period found 5000 MTO Oms Chl X ATE 30 Sep 2004 20 40 19 46 13 Tek Prevu lA 2 72V 10 520 208345 1 44 015 Chi Pk Pk 3 20 V Ch1 Freq Hs No period found 2909 cht 7 PRIM 30 Sep 2004 49 80 20 05 04 CONFIDENTIAL DO NOT COPY Page 9 26 File No SG 0156
6. 2 9 m m m NU m IGPH AI2D 54 LU gt L j 2 T A132 0 m ICLK A33 m DO 4 TROY ALA A42 Cp VBI DATA SLICER ALAS A144 ADUT POWER ON CONTROL POWER SUPPLY Yoga seo Vpp xmn LLC XTAU XRDY XcLK XRH X TRI AMXCLK ALRCLK TOO TRST Ths Vesixtaly poo LLC RTS1 XTALO XTOUT 7 0 HPDL T 0 ASCLK TDI TCK Analog input processing The 7118 offers sixteen analog signal inputs four analog main channels with source switch clamp circuit analog amplifier anti alias filter and video 9 bit CMOS ADC The analog input ports are configured as follows CONFIDENTIAL DO NOT COPY Page 8 20 File No SG 0156 The function Analog input process diagram as follows TEST SELECTOR AND BUFFER 0 SELECTOR HLNRS ANALOG CONTROL pas 1 0 rte CLAMP ANTLALIAS BYPASS 2 CIRCUIT FILTER SWITCH AMO 0 AIS ALS ANALOG SOURCE CLAMP ANTLALIAS 2 5 AMPLIFIER 52 SWITCH CIRELIIT pur FILTER AID 0 TER E ADS CLAMP ines ANTLALIAS AS CIRCUIT ae FILTER AO FUESEN 0 Alia ANALOG uta CLAMP ANTLALIAS BYPASS
7. CIRCUIT m FILTER SWITCH AID 0 gx E mL c 1c 22127 cda i c MODE GAIN VERTICAL CONTROL CONTROL d id iium CONTROL 1 MODELS Q HEL GUME HOLOG GLIMT GAFIX 0 0 WPOFF SL TCA GLUDL I 4 GAI 28 zn GAI 18 10 CROSS MULTIPLEXER DVHE T CHRIS Gry ADZ2MEYP ABA P Chrominance and luminance path Chrominance path The 9 bit CVBS or chrominance input signal is fed to the input of a quadrate demodulator Where it is multiplied by two time multiplexed sub carrier signals from the sub carrier generation block 0 and 90 phase relationship to the demodulator axis The frequency is dependent on the chosen color standard The chrominance low pass 1 characteristic also influences the grade of cross luminance reduction during horizontal color transient large chrominance bandwidth means strong suppressing of cross luminance If the Y comb filter is disable by 0 the filter influences directly the width of the chrominance notch within the luminance path a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth CONFIDENTIAL DO NOT COPY Page 8 21 File No SG 0156 Luminance path The rejection of the chrominance components with the 9 bit CVBS or Y input signal is achieved by subtracting the demodulated chrominance signal fro
8. found Ch2 Freq 49 41 2 i 4 1 Ch2 Pk Pk 3 60 V REI REC PNE RICE REC RC Ch1 2 00 V 2 00 V MO Op A chi T 30 2004 12 50 00 02 18 55 CH1 DVS 011 pin V13 CH2 DHS U11 013 Run Trig d Chl 3 80 Freq 2 No period found Ch2 i 4 12V Ch2 Freq 48 36kH2 Chil 00V 200 9140 Ous r Chi 7 FFE 1 70 20 30 Sep 2004 02 47 47 CHI DRE U11 pin R19 Tek Run Trig d Ch1 4 04V iE nan Chi Freq 4 13 00MHz 2 00 V M 100ns Chl 7 1 52 0 50 20 30 Sep 2004 02 31 17 CONFIDENTIAL DO NOT COPY Page 9 23 File No SG 0156 POWER ON OFF CHI F1 12DCV ON Tek Prevu GED GARE Rd fact eos A 11 8 11 9V 4 96ms je 2 36ms ChlPk Pk 12 7 V chi Freq No pe Eie found 30 Sep 2004 53 40 03 13 10 CHI F1 12DCV OFF Tek SPP T 1 8 70 1 3 40 256ms 1 S80 0ms 1 Chi 164v Freq 2 No period found ZEE 5009 200ms a Chi CX 30 Sep 2004 53 40 03 16 21 CHI V50DC ON Tek
9. Power saving Capacitor Inductor 12 filter Forward PFC PWM Control OFF All controllers Vb Page 8 28 File No SG 0156 Chapter 9 Waveforms PC Analog Mode 1024x768 75 HZ H sync U1 pin7 CH2 V sync U1 pin8 Tek Run 1 5 Trig d 85 MES e e e e A e shoes MES MH 2 4 i Pk Pk ee 1 5 44 Freq 4 60 02kH2 Ch2 T LEE NO e 1 found 4 Ch2Pk Pk 2 5 32 TR RT CRI ETT TC Y T NU RT E am 2 00 V cna 2 00 V es Ous Ch2 f 1 16 V 24 Sep 2004 12 50 20 02 22 21 G BUF U1 pin4 CH2 V sync Ul pin8 Chi 1 24 i Chl Freq 1 2 948 2 1 Ch2 5 28V anm 00 V IY 4 00 V BT PI Ous Ch2 7 2 28 V 24 Sep 2004 9 39 40 02 31 49 CONFIDENTIAL DO NOT COPY Page 9 1 File No SG 0156 HSYNC SW U6 pin30 CH2 VSYNC SW U6 pin31 Tek Run Trig d d Ch1 4 40 V Freq 60 02 2 Ch2 Pk Pk 1 4 36 2 00 V cha 2 00 V M20 cho 7 HT 24 Sep 2004 39 40 02 56 48 CH1 GCOST U6 pin 29 Tek Run 1 Ch1 3 56 V Freq 75 03 Hz 2 00V 00115 ChT 7 24 Sep 2004 50 20 03 02 46 CHI GBLKSPL U6 pin 38 Tek Run Trig d T 1 Chl 4 4 12V
10. SIECLE BRNO TORT RF TV RF ENT I Chi 2 00V 2 00V 40 0 45 one f ETE 9 30 00 CHI GCLK U19 pin 125 T 1 MN 1 WU 2 00V MI T0 Ons Chl 7 106 49 80 CH1 23SDCLKI 019 pin 114 Y TITTEN T 56 2 00 V 4 00115 Chi f 1 56 249 80 5 CONFIDENTIAL DO NOT COPY Chi Pk Pk 3 64 V Freq 49 47kH2 Ch2 Freq 2 period found Ch2 Pk Pk 4 04 V 27 Sep 2004 02 13 32 Ch1 3 13 V Freq 86 40 2 27 Sep 2004 02 17 06 Chi 8 20V 1 Freq 119 5MH2 27 Sep 2004 02 25 51 Page 9 15 File No SG 0156 CH1 23SDCS 019 pin 109 22111012 ANCIEN i dl xv wwe Li z ep A 49 80 CHI 23SDBAO 019 pin 108 Tek SSP Po sr Yay ws d z 49 80 2350 019 pin 107 Tek Stop BEL ES PEE EE EA RNC RN 2 00 V 100ns Chl f TV 149 80 CONFIDENTIAL DO NOT COPY Ch1 4 76 V Freq 30 87 2 27 5 2004 02 36 00 Ch1 4 74 V Freq 3 839 2 27 Sep 2004 02 41 00 Chl 4 59 V Freq 2 No period found 27 Sep 2004 02 43 29 Page 9 16 File No SG 0156 CH1 23SDCAS 019 106 EAR E MEE
11. Service Manual VISIO Model VIZIO L30WGU V Inc 320A Kalmus Drive Costa Mesa CA 92626 TEL 714 668 0588 FAX 714 668 9099 Top Confidential Table of Contents CONTENTS Sections Features Specifications On Screen Display Factory Preset Timings Pin Assignment BLOCK DIAGRAM Main Board I O Connections Theory of Circuit Operation A N Waveforms e Trouble Shooting Spare Parts List N Complete Parts List Appendix 1 Main Board Circuit Diagram 2 Main Board PCB Layout 3 Assembly Explosion Drawing Block Diagram PAGE VIZIO L30WGU Service Manual VINC Service Manual VIZIO L30WGU COPYRIGHT 2000 V INC ALL RIGHTS RESERVED IBM and IBM products are registered trademarks of International Business Machines Corporation Macintosh and Power Macintosh are registered trademarks of Apple Computer Inc VINC and VINC products are registered trademarks of V Inc VESA EDID DPMS and DDC are registered trademarks of Video Electronics Standards Association VESA Energy Star is a registered trademark of the US Environmental Protection Agency EPA No part of this document may be copied reproduced or transmitted by any means for any purpose without prior written permission from VINC FCC INFORMATION This equipment has been tested and found to comply with the limits of a Class B digital device pursuant to part 15
12. at 04 02 ELTE eres hE PR oe a aa roe eae IFEST 30 Sep 2004 1 69 80 01 32 59 CHI VID VS 010 pin 57 CH2 VID HS 010 pin 56 Tek Run 1 Chi 3 56 V Freq HZ No period found Ch2 4 3 92 V Ch2 Freq 15 77 2 2 00V Ch2 2 00 200ps Chi 7 1 52 30 Sep 2004 41 50 00 01 47 58 CONFIDENTIAL DO NOT COPY Page 9 21 File No SG 0156 CH1 VID DATA U10 pin 53 Tek Run T Trig d i Chl 3 56V i 29 98 H2 14 14 15 p ob Oe 2 00 V M20 0ms chi 30 Sep 2004 12 40 00 01 40 24 CHI VID CLK2 U10 pin 27 1 Ch1 3 50 1 Freq 101 1 Hz da roov D oms a eh 50 00 01 45 12 30 Sep 2004 CHI VID Y7 U10 pin 31 Tek SSP Y NUNC ES PEE DN E RC ORT E PAE MORTE FR S C 2 00 20015 Ch 1 22 V 30 Sep 2004 50 00 02 03 08 CONFIDENTIAL DO NOT COPY Page 9 22 File No SG 0156 CH1 GVS 019 119 CH2 GHS U19 pin 118 Tek Run Trig d i Chl 3 80V 12 EIE Freq 2 No period penes ted Er d herd e as HS uis
13. SUPPORT B 30 1 11 56 1947 1200 0960 STAND SUPPORT A 30 1 57 1947 1200 0950 STAND SUPPORT 30 1 58 1701 0900 0540 STAND GLASS 8 0mm 30 1 59 1947 1200 1160 STAND SUPPORT C 30 1 60 1947 1200 1280 STAND SUPPORT D me 61 1701 0511 0070 V inc 30 62 1712 0100 4870 BASE 30 1 63 1947 2000 0150 BASE RUBBER PAD TM 30 4 64 1947 2000 0100 GLASS RUBBER PAD TM 304A 6 65 1701 1000 0010 BASE FOOT 218 0 1 5T 6 66 1947 2000 0240 GLASS SUPPORT 50 4 13 14 12 Vine VIZIO L80WCU 2830 3223 6103 DESCRIPTIUN PART ND 74 TRAN THIRD ANGLE PROJECTION MODEL No UNLESS OTHERWISE NOTED DSN JESSIE Yu 01 21 05 MATERIAL DWG XX 0 10 C QTY 7 SIZE Al 30 CASE ASS Y 16 X 0 2 Vinc L30WGU ANG SCALE FALLI UNIT MM DWG No 07 SHEET 7 of 7 5 U V
14. 3 59 99 2 NUN RESP EE ROM CN UE E PEE MORTC FR 2 00 V M 10 045 Ch f 24 Sep 2004 11 50 20 03 05 19 CONFIDENTIAL DO NOT COPY Page 9 2 File No SG 0156 CHI SCL U6 pin56 CH2 SDA U6 pin57 Tek Prevu i Ch1 Pk Pk 1 2 96 V Freq 46 53kH2 Ch2 3 04 V Ch2 Freq 21 25kH2 Chi 200 2700 V ELU chit 7 24 Sep 2004 9 10 00 03 21 06 GCLK U6 pin67 Tek Run Trig d i don 18 2 94 EMEN MN ME 1 1 ChlPk Pk 3 72 i ChiFreq 78 17 2 ONCE UT SE CRT DUNT RC 1 00 V 10 0115 Ch f 26 Sep 2004 50 00 18 35 41 CHI U6 pin66 CH2 GVS U6 pin64 Chi 4 32 1 Chi Freq i 60 02 2 i 4 1 Ch2 1 soi 2224 found 24 ww Ch2 i 3 64 V ANEY REC RNC RC RR PAE PAN O Chi 2 00 V 2700 V MIO Ope Ch2 7 26
15. 50 40 00 28 56 GRE U6 pin 70 Tek ET Ch1 3 72 V Freq 2 No period found 2 00 V 200ns Chi T 32 30 Sep 2004 50 40 00 36 38 CONFIDENTIAL DO NOT COPY Page 9 19 File No SG 0156 CH1 DVS 011 pin V13 CH2 DHS U11 U13 EE TES Er Chl 2 00 V 2 00V 40 0 5 Chl f EE 69 80 CHI BLANK 011 pin Y15 Stop ei ee ee E E a ee ee eee 200 10 08 Chi f 50 20 CH1 DCLK 011 pin W12 E Run j Trig d ee a ee ee eee eu 2 00 V 10 015 chi f 50 20 CONFIDENTIAL DO NOT COPY Ch1 3 84 V 1 Freq 2 No period found Ch2 Freq 48 36kH2 Ch2 3 28 V 30 Sep 2004 00 44 16 Chl 4 52V 1 Freq 48 33kH2 30 Sep 2004 00 48 01 Ch1 5 95 V 1 Freq 64 83MH2 30 Sep 2004 00 50 38 Page 9 20 File No SG 0156 DRE 011 pin R19 Tek Run 3 77 V Freq 2 No period found 2 00V 20005 chi 7 V 30 Sep 2004 50 20 00 53 35 TV AV1 AV2 S MODE CHI V1 UT3 pin 38 1 1 Ch1 Pk Pk 4 2 10 i j 71 07 2 ea CETUR Me 4 1
16. DO NOT COPY Page 8 22 File No SG 0156 Decoder output formatter The output interface block of the decoder part contains the 0656 formatter for the expansion port data output XPD7 to XPDO and the control circuit for the signals needed for the internal paths to the scaler and data slicer part It also controls the selection pf scaler and data slicer part It also controls the selection of the reference signals for the RT port and the expansion port The generation of decoder data type control signals SET RAW and SET VBI is also done within this block These signals are decoded from the requested data type for the scaler input and or the data slicer selectable by the control registers LCR2 to LCR24 Data formats at decoder output US teletext WST Raw si port signa VE _ The operation of TA1218F The TA1218N F is an audio video switching IC for TV sets Conforming to I2C bus standards it allows you to perform various switching operations through the bus lines by using a microcomputer Thanks to its 2 channel outputs the TA1218N F can also be used for the PIP systems Furthermore since the presence of a signal on its sync signal output pin can be determined by a microcomputer it is possible to check each input output channel self diagnosis This IC has the same pin assignments as the TA1219AN SDIP36 a 1 channel output version of the TA1218N F CONFIDENTIAL DO NOT COPY Page 8 23 File No SG 0156 TA1218F block diagr
17. OVP function is controlled by 202 and 208 to sense output 12V and 24V When output voltage is over the clamp voltage of ZD2 and ZD8 ZD2 and 208 is turned on to driving Q2 result in Q2 turn on cause U8 have large current flows in to the base of the Q12 result in Pind of the U1 and Pin 2 and Pin7of the 05 immediately down to zero to default power supply Power saving function is controlled by Pin C of CN1 and CN3 When Pin C is low signal Q5 is turned off result in U4 keep off stage cause Q not turn on result in across on C22 voltage not delivered to the Pin 13 of the IC1 to closed IC1 CONFIDENTIAL DO NOT COPY Page 8 26 File No SG 0156 D1 PS206 C55 R1 1 2 222P 222P 33 TO INVERTER 24V o 500v 500V js a1 D2 14 Keep L N SG trace for 3mm at least C2 short 22N50A 150 Q3 13 NC 500V 22A 450V 2SK3520 F1 LF1 LF2 1 500 9 12 5A 250V Time Lag 285 OHM ET24C ET24C 5 Ti BD1 C5 EER35C CN2 oofz2ur 250v jesus R5 R6 R2 NC 13 9 5P 3 96 E 4T5K 2008 gt
18. PWM section of the IC1 The double ended forward converter works as follows In Fig 1 Q3 and Q4 are in series with the top and bottom of the transformer primary Both of this power Mosfet close are turned on simultaneously and turned off simultaneously When they are on all primary and secondary dot ends Pin2 of the T1 are positive and power is delivered to the loads When they turn off current stored in the T1 magnetizing inductance reverses polarity of all windings The dot end of Np tries to go far negative but is caught at ground by diode D7 The no dot end of Np tries to go far positive but is caught at Vdc by diode D4 Thus the emitter of Q3 can never be more than Vdc below its collector and the collector of Q4 can never be more than Vdc above its emitter Now the pin11 point of the IC1 will yield a square waveform of 69KHz frequency to switching Q3 and Q4 and cause T1 start storage energy during and Q4 on time and deliver energy during and Q4 off time When and Q4 is turned on the dot end of the primary power winding Np and secondary go positive with respect to no dot end Current and power flows into the dot end of Np Rectifier diode D3 are forward biased and current power flows output of the dot end of secondary to the LC filters L2 C8 C9 L3 C10 and the load Diode D3 act like the freewheeling diode at Q3 and Q4 turn off Duty cycle is controlled by with compared to pin8 Pin6 voltage is selected by U3 and U2
19. Sep 2004 30 00 18 46 17 CONFIDENTIAL DO NOT COPY Page 9 3 File No SG 0156 CHI GFBK U6 pin66 CH2 GHS U8 pin8 Tek Run Trig d Ch1 4 60 V Freq 60 02 2 Ch2 Freq 60 02kH2 Ch2 3 52 V ENA 19 RR RC RC MASI PAIE OEO TON DON ES TOA EN TEN HEA WEN TOSE Chi 2 00 V 2700 V MIO One chit 7 1 00 26 Sep 2004 50 00 18 58 27 1 B SW U6 43 Run 1 550mV 18 940mv Chi Pk Pk 1 05 V Ch1 Freq 4 11 21 2 Soomv 7 120005 chi 7 PTT 26 Sep 2004 12 49 80 19 11 29 U6 19 Run T Trig d 20 015 chi 7 ET 26 Sep 2004 12 49 80 19 13 30 CONFIDENTIAL DO NOT COPY Page 9 4 File No SG 0156 CHI 011 pin P3 Tek Stop Y 550 1 96 V Freq 14 34MH2 124 500mV 40 0115 chi f 480mV 26 Sep 2004 49 80 19 49 26 RST 166 pin Tek Chi 3 72V Freq 2 1 1 No period LG MM 1 found BERT RR x TE n 26 Sep 2004 ii 47 40 20 00 26 ROMOEN 011 pin Tek SSP 1 ChlPk Pk 1 3 92V Freq 7 381MH2 2009
20. a wide variety of aspect ratio conversions and other special video enhancing features to produce the highest quality image The internal block diagram of FLI2310 is as follows Port 2 8441 555 Input Noise Reducer Deinterlacer Frame Vertical and 20 Horizontal Scalers RBG YCrCb Digital Outputs ipit Processot with Auto Syne and auto Adrusi Rate Converter and Port SDRAM interlace ROBY Cech put Clock Lieneration SDRAM Vertical and Horizontal extemal Enhancers CONFIDENTIAL DO NOT COPY Page 8 13 File No SG 0156 Input Processor Two input digital data ports are available each with separate sync and clock signal inputs Port 1 is a 24 bit data port that accepts the following input formats 24 bit RGB data 24 bit 4 4 4 Y Cr Cb data 24 bit 4 4 4Y Pr Pb data 16 bit 4 2 2 Y Cr Cb data 16 bit 4 2 2 Y Pr Pb data 8 bit Y Cr Cb data 8 bit Y Pr Pb data 8 bit Y Cr Cb data with embedded sync ITU R BT656 D1 format Port 1 has two sets of control inputs H Sync or Ref V Sync or Ref Odd Even Field identification and Data clock inputs Either of the two sets of control input signals can be selected for Port 1 data Port 2 in the SHD 3010 we not use The data is sampled at the rising edge of the input data clock The H and V timing control inputs can be either Sync type signal or Reference Ref type signal Ref signals change logic
21. be fulfilled through SDA and SCL of bus to change the data of control registers of AD9883A The PLL derives a master clock from an incoming H Sync signal The master clock frequency is then divided by an integer value and the divider s output is phase locked to H Sync The PLL characteristics are determined by the loop filter design which controlled by PLL charge pump current CURRENT and VCO range setting VCORNGE The value of VCO range and charge pump current is as follows 51 504 Pixel Clock KVCO Gain Powered On or Range MHz Comments m Serial Bus Sync Activity Detect SOG Band gap Reference Serial Bus Sync Activity Detect SOG Band gap Reference If we adjust contrast or brightness of analog port then the input gain or input offset should be modified through IIC bus The power of AD9883A is supplied 3 3V We can management the power of AD9883A through the register of itself The H Sync input is used as a reference to generate the pixel sampling clock A 5 bit value PHASE adjust the sampling phase in 32 steps across one pixel time so it generate a stable timing relationship between HSOUT and DATACK to digitize the captured analog RGB data The output data is aligned to the leading edge of HSOUT If the signal of sync on green is detected by SOGIN then the SOGOUT will produce a digital composite sync CONFIDENTIAL DO NOT COPY Page 8 4 File No SG 0156 DVI D Interface The Sil169
22. control pins have to be adjusted manually via an I2C register output ports are configured as follows Output VID Output vi Output v2 Output va Y Output VID_Y4 4 34 vs Y7 31 Output VID Y7 CO 50 Output VID UVO C1 49 Output VID UV1 C2 48 Output VID UV2 C3 47 Output VID_UV3 C4 44 Output VID_UV4 C5 43 Output VID_UV5 C6 42 Output VID UV6 Output 07 The operation of SAA7118 The 5 7118 is a video capture device for applications at the image port of VGA controllers SAAT 118 also provides a means for capturing the serially coded data in the vertical blanking interval VBI data Two principal functions are available 1 To capture raw video samples after interpolation to the required output data rate via the scaler 2 Aversatile data slicer data recovery unit The 5 7118 also incorporates field locked audio clock generation The function ensures that there is always the same number of audio samples associated with a field or a set of fields This prevents the loss of synchronization between video and audio during capture or playback The function block diagram as follows CONFIDENTIAL DO NOT COPY Page 8 19 File No SG 0156 ADP 8 0 RES CLKEXT TEST SCL INT nd IR CONTROL PC BUS REGISTER EDEN A11 Fe _ A12 ALORS SC COMPONENTS PROCESSING A121 7 mr m ui 2 IGP1 22 En 5
23. displayed on the panel CONFIDENTIAL DO NOT COPY Page 6 1 File No SG 0156 TUNER UTE TET EET AT THER 4udio TT AL dd TT e MICRORES LE FCI CITED BUT Ce 7 TOSHIBA AUDIO CUT eel JT 1 T _ a _ HEST FILEO 1199 E 5 CONFIDENTIAL DO NOT COPY Page 6 2 File No SG 0145 The function of the Main board is to receive different types of video and audio signal in to compatible digital video and audio format The FQ1236 MK3 tuner processes the TV antenna and the cable into analog signal The audio signal exiting from FQ1236 MK3 is further processed by MSP3440G The purpose is to process the input IF signal into AF signal and control TV sound signal features like volume bass treble and balance The processing procedure conforms to standard recommend for Broadcast Television System Committee BTSC The analog video signals of S video YPbPr TV and A V signals travel directly to video decoder At the decoder all signals are translated from analog signals into compatible digital signal which will be ultimately be processed by theVP3230 amp 5 7118 After the video signal has been converted into digital signals the digital video signal is d
24. out that even pixels on pins DRE 7 0 DGE 7 0 and DBE 7 0 and odd pixels on pins RRO 7 0 RGO 7 0 and RBO 7 0 The PW166B generates the vertical and horizontal timing signals for the display device and internal timing signals for the display port portion of the PW166B The DHS and VHS output signals can be active high or low depending on the HSPOL and VSPOL bits Similarly DENPOL controls the polarity of the DENR DENG and DENB outputs The DDEN bit enables the DHS DVS DENR DENG and DENB outputs The horizontal counter starts with the leading edge of horizontal sync All horizontal timing is referred to this edge Video Port The Video Port VPort is an input interface for video data It accepts incoming data in YUV and RGB formats and supports picture in picture when both the VPort and the GPort are enabled simultaneously The VPort can input data at rates up to 75 MPixels second Setting bit CAPEN to 0 can disable the Video Port The block diagram is as follows CONFIDENTIAL DO NOT COPY Page 8 12 File No SG 0156 VPEN VRI7 0 Data un EN RGB Memory VG 7 0 Register Nod Compress Interface VBI 7 0 VCLK 2 VHS Timing and Sync VVS Decoder VFIELD The operation of FLI2310 The FLI2310 is a highly integrated digital video format converter for LCD TV applications using patented de interlacing and post processing algorithms from Faroudja Laboratories coupled with highly flexible scaling
25. power of PVDD if analog 7 Check ripple dc ac 1 Do auto tune function with full screen Patten 2 15 the timing supported 3 Adjust H size if analog 4 Check U6 if analog 5 Check power of PVDD if analog 6 Check ripple DC AC 1 Do auto tune function with full screen Patten 2 15 the timing supported 3 Adjust H V position if analog 1 Do auto tune function with full screen Patten 2 15 the timing supported 3 Adiust phase if analog 4 Check power of PVDD if analog 5 Check ripple DC AC 1 Adiust contrast amp brightness 2 Adjust gamma 3 Adjust user R G B 4 Check backlight inverter 5 Check signal between U1 amp U6 amp W1 if analog 6 Calibrate ADC with pattern that32scalesof gray if analog NO Color unbalance NO Colors interpolate NO YES YES 1 Adiust user R G B 2 Adiust color temperature R G B 3 Check signal between U6 and W1 if analog 4 Calibrate ADC with Patten that 32 scales of gray if analog 1 Check signal U11 to LVDS 2 Check signal U33 to U11 if digital 3 Check signal U33 to W19 if digital 4 Check signal U6 to U11 if analog 5 Check signal U6 to W 1 if analog Page 10 6 File No SG 0145 IMAGE QUALITY IS NOT GOOD S VIDEO TV COMPOSITE VIDEO1 2 It means image exceed or less than display area 1 15 scaling in fill all 2 15 the timing supported 3 Check UT3 4 Check U10 5 Check ripple dc ac Image s
26. state between active video region and inactive blanking region The polarity of the input H and V control signals is also programmable An Odd Even Field identifier signal input is provided but this is not required when the control inputs are syncs as it is generated within the chip in this case The polarity of the external Odd Even Field identifier is also programmable For SHD 3010 we use ITU R BT656 the ITU R BT656 signals with embedded timing the Ref signals are constructed from EAV End of Active Video and SAV Start of Active Video blocks Table 4 1 SAV and EAV Coding BYTE SEQUENCE BIT FIRST THIRD REN o m Er CONFIDENTIAL DO NOT COPY Page 8 14 File No SG 0156 SDRAM The SDRAM types used with the FLI2310 should be organized as 32 bit wide SDRAM i e one 2M x 32 bit controller up to 166 MHz operations for external SDRAM The built in SDRAM interface SDI controls the access to the SDRAM for the de interlace and the frame rate converter Multiple read channels are used for the de interlace An arbitrator controls the write and read operations based on the status of the FIFOs present at each read and write channel ensuring that underflow of FIFOs do not occur Adequate depth of the FIFOs ensures that no overflow occurs 4MB of SDRAM memory is required for full functionality of the chip The SDI supports use of one 2M x 32 SDRAM The SDI supports SDRAM operation speeds up to 166MHz The SDRAM speed grade requi
27. 0 Changing PHASE will change the set up hold time relationship between the sample clock and the data coming into the external ADC CONFIDENTIAL DO NOT COPY Page 8 10 File No SG 0156 Output GHSFOUT is the field output signal used to tell an external ADC whether even or odd pixels are being captured during half sample mode When 1 the external flow control is enabled each new line is marked by an edge on the GLAVIN input pin GFBK but while EXTFCE 0 the GFBKIN input pin GFBK is used as the input HSYNC signal for pixel counters Display port The display port processes and prepares the data for display The output data is sent out on pins DRE 7 0 DGE 7 0 DBE 7 0 RRO 7 0 RGO 7 0 and RBO 7 0 that is controlled by display timing generator The block diagram of display port is as follows DRA7 0 DGE 7 0 DBE7 0 DRO 7 0 DGO 7 0 D80 7 0 Screen Dis play Data Color Look Up Ez Space Tables Color Demultiplexer Matrix Overlay Data DCLK DHS DVS Display Timing Generator DCKEXT Figure 4 34 Display Port Block Diagram The on screen display data can be merged into the data as the data is output to the display here The on screen display data can also be added as the data is input to the video port or as data is input to the graphics port The gain function is applied to every pixel has the same form as the overlay functions Specially t
28. 0 50 00 CONFIDENTIAL DO COPY Ch1 3 72 V Ch1 Freq 60 02 2 No period found Ch2 Pk Pk 3 64 V 26 Sep 2004 23 08 37 Page 9 8 File No SG 0156 1 GFBK 08 pin3 2 GPEN U33 46 Tek Run Trig d T 1 PERES EN 1 Ch1 3 64 V 1 i i 4 Chl Freq Jia i 60 02 2 Ch2 Freq WR mu wm Ch2 5 1 424V Fe TV BR TORT OTT TV RF X EL 2 00 V Ch2 2 007 20 018 f PAPE 26 Sep 2004 50 00 23 13 42 CH1 GCLK U33 pin46 Tek Run n Trig d i 4 05 V 39 48 2 es i ee 2 2 00 V 20 015 Ch J 1 TAS 26 Sep 2004 50 00 23 18 20 RP54 U33 pin37 CH2 RP59 U33 17 Tek Run T Trig d Ch1 4 00 V Freq 1 010MH2 Ww Ch2Pk Pk 4 71 Ch2 Freq 1 010MH2 Tev Ch1 2 00V 2 00 10005 Chi d 26 Sep 2004 0 50 00 23 53 01 CONFIDENTIAL DO NOT COPY Page 9 9 File No SG 0156 CHI DVS 011 pinV13 CH2 DHS 011 pinU13 Tek Run Trig d ITE NN NETT DOR RC E Chi 2 00V 2 00V 40 0 45 chi f 12 60 20 CHI BLANK U11 pinY15 y i wag py eee EOS i 2 00V 77778140 ous E Chl 7 116 V 50 40 CHI DCLK 011 pin W12 Te
29. 0 P 10mm 3 2 4 5 5 012 D11 FCH20A15 UFA4006G 5 R59 DO 41 8 750K 3 1 4W 4 Heat Sink D6 1N4148 eo lol M 2 1 R61 25 3677 i D13 014 id 10 F4003G UF4003G 1 4W TO 220F lt 1 D 1 Heat Sink r 0 SG6841 U5 1 8 C56 R31 R62 R63 R64 GANE 470P 50V 120 0 24 gt 33 47 2 VDD 7 1WS 1 4W 1 4W 1 VIN SENSE 1 Hy RI RT cs R69 R78 10uF t 33K NC C43 50V PC 621 BL 0 1 KY 5 11 12V Fosc 50KHz e R79 R72 d 1K 10K R71 1K D15 Secondary GND w W i Q11 zi R73 1 414 4 1 2 2 25 1015 100K TO 92 2 R75 D20 PC 621 1 e 1N4148 12B2 1 2W Primary GND gt 209 202 2 012 ads me 25 1815 2 Q2 JP2 R76 TO 92 25 121 C51 100K 0 1uF R80 P 5mm 1K 4 WZ 1K Figure 2 CONFIDENTIAL DO NOT COPY Page 8 27 File No SG 0156 System Block Diagram EMI filiter AC Input Full bridge rectifier Detect Iac Vrms FORWARD Buck capacitor filter Inductor store amp deliver energy PowerMosFe t switching Feedback control PFC PWM control Power MosFet Transformer switching Transfer energy Inductor Diode Retifiler Store and deliver energy Inductor capacitor filter Power Mosfet switching Transformer Diode Retifiler store amp deliver energy Bias voltage FLYBACK PWM control 12Vo 24 OVP Proction fuction CONFIDENTIAL DO NOT COPY
30. 2008 8 com amp 4 4W 2W 2W PG108R 30CPQ100 __ 8 1 2 Ex 0 0022UFI250 m 12 100 47 R4 E 1A 800V TO247 71 1000uF NC 70u 6 A 9 4 2 21 4128 10 11 12 cs3 35V 44W 35V reset e Et 1 4 22R 77 772 12 5Dx25 10 20 4 3 R16 1 4W C15 3 N 88 5 475 1N4148 20pF 30x30 R14 1 C14 1KV Y5P 475k 2 c16 0 0022UF1250 0 68uF R15 C18 400V 4128 R18 220pF 1 0 0022UF 250V 0 47uF 275Vac 14 10K 1 5 100V 7 4 C18 PG108R 220pF 1KVIYSP 7 a D8 2 1N4002 R19 2 R26 Q4 038 gt 25 3520 5 500V 9A Q13 57 09 ie 28C1213 lt 2 1N4002 2 Q9 2801213 712 TE Tok T WM Q6 25 673 C21 A 2 R22 R23 332 250V 1ws 1ws 7 R17 10U 50V 10K Q7 28 1213 C24 220pF NPO T R36 C25 R29 205 p 19 6K 13K 2n2 100V 10K 7B2 23 1 4W 10 50V u1 CM6800 1 7 e U2 TLP621GR R41 R37 2 26 2 UT PINSY 2 VDD gt UA 12V TLP621GR 3 NC 1 C28 c29 c30 cat 6B1 047u C35 C36 63V 13K 50V 0 1uF 1000P 470PF 100 C40 C38 0 01u c39 0 1uF 1000P 0 01uF NPO R30 2 R54 27K NC R57 NC 2 7 7 S Q8 2861213 054 R27 NC 3 6K 7 Figure 1 R55 P6KE150A P6KE150A 0 22 2W D16 D17 T3 7 2625 2 44 49 45 L4 TO MAIN BD 12V R56 2 2 1 1 1 12 1 MM 750K P 5mm 7 5 8uH 5A 4 T T 1 1 4W 33 222P 500V 222 50
31. 3 Check JT8 input if s video 4 Check signal between UT3 and JT5 amp tuner amp JT8 1 Check U10 input 2 Check U10 Power 3 Check 1 Check U19 input 2 Check U19 power 3 Check UT3 Output 1 Check U11 input 2 Check U11 power 3 Check U10 Output 4 Check U10 Clock 1 Check U11 Output 2 U21 input 3 Check U11 amp U21power 4 Check U11 Output Page 10 2 File No SG 0145 DVD HDTV IS NOT DISPLAY CORRECTLY Start NO 2 1 Check video 2 Check host s setting Yes NO 1 Check signal between U3 and JT11 amp JT10 2 Check U3 amp U1 Input output 9 RATS COMECE 3 Check U3 amp U1 Power Yes NO 1 Check U10 input if 480i 2 Check U10 Power if 480i U10 input is correct 3 Check U6 input if 480p 4 Check U6 Power if 480p Yes NO 1 Check U19 input if 480i 3 Check UT3 output if 480i Yes NO 1 U11 input i480i amp 480P 2 Check 011 power 48018480 3 Check U10 Output 48018480 U11 input is correct 1 Check U11 Output LVDS input is correct 2 U21 input 3 Check U11 amp U21power 4 Check U11 Output 1 16 W5 connected is good 2 15 panel working ok CONFIDENTIAL DO NOT COPY Page 10 3 File No SG 0145 TROUBLE OF DC DC CONVERTER NO The voltage is about 12V 1 Check power board 2 Check power cable connection W6 is good NO The voltage is about 12V 5V 3 3V while power plug on 1 W1 amp W4 to keypad connecti
32. 3010 28 1947 1700 0150 SHIELDING AL TAPE 70 0 50 0 3 29 3850 0152 0150 MAIN BD ASS Y VIZIO L30WGU 50 1947 1800 0290 BLOCK 12L 10W 1 5Hmm HOLE6 1 31 1712 0100 6670 10 2 30 1 52 1712 0100 6660 lO BKT1 Gateway 30 1 33 1947 2000 0770 AU PANEL RUBBER BLACK Gateway 5 43010 3 17 34 1712 010075370 SHIELDING TM 30A 1 35 1712 0100 4570 MB SHIELDING TM 30 1 56 1701 0206 1031 REAR COVER Vinc 30 1 37 1701 0800 0870 REAR PLATE Gateway 30 1 38 1936 1100 7401 B C LBL VIZIO L30WGU 8 39 1720 3006 2050 MAC SCREW MF M6 0 20 0L BLK Ni 6 40 1725 5004 2420 MAC SCREW MI M4 0 24 0L NYLOK 4 41 724 2304 1830 SCREW BBC M4 0x18L ZN CC BLK 11 42 1720 0003 0450 SCREW MB M3 0 X4 0L BLK Ni 43 1724 5804 0802 SCREW PBATW M4 0X8L Zn Cc 2 44 1720 7344 0820 MAC SCREW MHSW 44 40 8 0L Ni 4 9 45 1720 5003 0720 SCREW MI M3 0 7 0L NI 2 46 1721 0003 1050 TAP SCREW TB 43 0 10 0L BLK Ni 9 47 1720 0503 0810 MAC SCREW MBSWF M3 0 8 0L Zn Cc 8 48 11720 0003 0420 5 M3 0 4 0L Ni 8 49 1721 0003 1020 TAP SCREW TB 3 0 10 0LNi 12 10 50 1720 0004 0510 MAC SCREW MB MA 0 5 0L Zn Cc 2 51 1720 4103 0610 MAC SCREW FWRF M3 0 6 0L Zn Cc 1 52 1721 0003 0820 TAP SCREW TB 3 0 8 0L Zi 2 53 11721 3003 0650 TAP SCREW TF 3 0 6 0L BLK Ni 1 54 1721 3003 0610 TAP SCREW TF 3 0 6 0L Zn Cc 14 55 1947 1200 0970 5
33. 66B is as follows CONFIDENTIAL DO NOT COPY Page 8 7 File No SG 0156 Fort Fort B 1 01 JTAG Debugger D T5 0 ASO Spo EXTIHT Fad We 15 05 5 1 3RGE 4 7 0 23 02 24 02 OWS DHS DEM PWT165B Internal Block Diagram GREF GFEK FRREXAT Xl PLL The interface of Pw166B is composed by three parts that is microprocessor interface graphics port and display port Microprocessor interface When power is supplied and power key is pressed then the reset circuit lets RESET to high state that will reset the PW166B to initial state After that the RESET will transits to low state and the PW166B start to work that microprocessor executes the programs and configures the internal registers The PW166B uses two internal PLLs to generate the memory and display clocks both MCLK and DCLK are generated from a reference clock input to pin XTALIN according to the following formulas FVCOM XTALIN MPLLM 1 MPLLN 1 FVCOD XTALIN DPLLM 1 DPLLN 1 Where MCLK 2 MPLLP 250MHz FVCOM 550 MHz DCLK FVCOD 2 DPLLP 250MHz FVCOD 550 MHz Valid values for registers MPLLM 7 0 and DPLLM 7 0 are between 0x27 and OxFF MPLLN 5 0 and DPLLN 5 0 are valid from 0x00 to Ox3F MPLLP 2 0 and DPLLP 2 0 are valid from 0x00 to 0x07 For lower power modes do not slow the internal PLLs Instead us
34. 70 40 29 Sep 2004 CHI SYNC DET U3 pin 24 Tek stop m i i i m i i _ i i 3 32 V V 40 0mV dr pos in Ee dd gin Ch1 4 84 V Chi Freq 31 47kH2 ETT RI SOE MT CRT RET DOE EEY DONS BE MNT SD E CON OT 8 2 00 V 20 045 Chl 1 48 29 sep 2004 i 49 20 23 37 1 CONFIDENTIAL DO NOT COPY Page 9 18 File No SG 0156 CHI GFBK U6 pin 66 CH2 GHS U8 pin 8 Tek Run Trig d Ch1 4 76 V D chi Freq 3 31 47 2 Ch2 Pk Pk 3 35 V i 8 4 1 Ch Freq 31 47 2 1 NRI OFT I TPE Chi 2 00 V 2 00V Mj20 0JS chi f 30 Sep 2004 40 60 00 17 23 CH1 GCLK U6 pin 67 Tek Prevu Lows ues dM S sr Bd ERN Reed i j p d ee metn He ee 1 ij f f pi i Chl Pk Pk ees ee bus i diosa Leal Lii Ch 1 F req 1 26 99MH2 i MIETEN T RR 2 00V 20 015 Chi f 1 32 V 30 Sep 2004
35. 9 D8 and D5 which will limit to 5 volts The PW166B let PORTA3 ADCEN to low state that will let FST3125 U8C to output GHS signal which are derived from AD9883A pin65 SOGOUT When PW166B detects exact GHS and GVS timing it will configure the registers of AD9883A to satisfy the operation through SCL and SDA of IIC bus Oppositely while PW166B let PORTB3 DVI ON to high state it means that the analog port is disable and should be in digital interface mode While PW166B let PORTA6 INSEL PORTB4 COMP SEL to High state it means that YPbPr is disable and DVD is enable AD9883A is 8 bit 140 Msps monolithic analog interface for capturing RGB graphics signals from personal computers and workstations It includes 1 25V reference PLL to generate a pixel clock from Hsync and programmable gain offset and clamp circuits The function block of AD9883A is as follows RAN RouTA GAIN 5 GOUTA BOUTA 23 MIDSCV L LU DTACK COAST PROCESSING LJ HSOUT GENERATION t SOU FILT 23 SOGOUT e HEF Bet BYPASS SDA CONFIDENTIAL DO NOT COPY Page 8 3 File No SG 0156 If user changes to analog mode or analog port is resignaled from host device then PW166B will let PORTA INSEL to Low state that enables H Sync V Sync from AD9883A PW166B will changes the power mode PLL divide ratio clock phase VCO range and charge pump current etc that depends on the timing of GHS and GVS The action should
36. CHI V33 V OFF Bs Prevu 4 2 66V i 620 IX uuu dre 1A 700ms i 108 6941 Chi Pk Pk 2 84 V Ch1 NO pened found 100V 1 00115 Chi rt 30 Sep 2004 20 20 20 36 46 CH1 V50 V ON Tek Prevu Meere ke j 1 80 0 2 24ms 16015 Chi 5 20 V 1 Freq he No period found 200 V 0015 Chi E PRI 1241 80 30 Sep 2004 20 42 08 CH1 V50 V OFF Tels Prevu 4 04 V 840 258ms 240ms Ch1 Pk Pk 4 56 V Ch1 Freq No period found 2 00 oms 30 Sep 2004 30 00 20 52 02 CONFIDENTIAL DO NOT COPY Page 9 27 File No SG 0156 CHI V120V ON Tek P revu 4 1 Chi Pk Pk 11 7 V Ch1 Freq No period found 5 00 V 40048 Chl 8 10 V 30 Sep 2004 50 80 20 55 50 CH1 V20V OFF Tek Prev Chi 11 0 1 Freq 2 i i i No period bee Me t E found Ch1 M200ms Chi eee bene 75 90 V 30 Sep 2004 19 80 56 22 07 02 CONFIDENTIAL DO NO
37. DT to PDO A resistor tied to the EXT RES pin is used for impedance matching CONFIDENTIAL DO NOT COPY Page 8 5 File No SG 0156 HDCP Keys EEPROM The Sil 169 comes pre programmed with a production set of HDCP keys in its internal EEPROM In this way the keys are provided the highest level of protection as required by the HDCP specification Silicon Image manages all aspects of the key purchasing and programming There is no need for the customer to purchase HDCP keys from the licensing authority For security reasons the keys cannot be read out of the device Samples of the Sil 169 are available with the B1 public keys as listed in the back of the HDCP specification These are marked with a PUB part number as noted in the Ordering Information section Make sure to request either Public or Production keys when requesting samples Before receiving samples of the Sil 169 with production keys a customer must have signed the HDCP license agreement HDCP Operation The Sil 169 supports High bandwidth Digital Content Protection HDCP by decrypting the pixel data stream received from an HDCP transmitter in the video host system HDCP provides a secure method of delivering high definition content between a host such as a set top box DVD player or D VHS player and display such as an HDTV projector or A V receiver The authentication process involves exchanging calculated values based on the keys and KSV A software driver running o
38. Fae a ae 1 cujus 04 04 04 0 2 00 V 20 015 chi 1 72V 49 80 23SDRAS 019 pin 105 Tek _ _ _ eer TE GT QUT SORT WOR PEEL TES TAAN PSE SOW TOM OPEL OY ST CS 2 00 20 01 Chi f TEN 0249 80 CH1 GFBK U8 pin 6 485 E E E E E E E E E E EEE E E E E E E e 2 00 V 10 038 chi f 149 80 CONFIDENTIAL DO NOT COPY Freq 6 141 2 28 Sep 2004 20 15 46 Chl Pk Pk 4 52V Freq 15 42MH2 28 Sep 2004 20 44 16 Ch1 3 68 V 1 Freq 49 45kH2 28 Sep 2004 22 44 33 Page 9 17 File No SG 0156 CHI GBE 019 pin 155 Tek SSP Ch1 V t Chl Freq E 43 42 2 2909 M46 0ns chit 7 29 Sep 2004 1849 20 23 29 57 480P Y COMP U3 pin 4 Tek Stop Y Ch1 1 10 V l 31 46 2 ERA WON RF IORA TOO UNA IRT IAD TAS EAE ENY MOON TAR POPAT KO EAN RR TONY MESE OPT PON ACEN ISAN NY UEN ENT IUS EEA IERT EEN PENN OEY VONN DAS DAEN RR WSA 500 200us Chl 7 2 39
39. H 15 734kHZ V 60HZ NTSC interlace H 31kHZ V 60HZ NTSC progressive b Signal level Y 1Vp p 0 350Vp p Cr 0 350Vp p Impedance 750 Ypbpr a Frequency 15 764 2 V 60HZ NTSC 480i H 31kHZ V 60HZ NTSC 480p H 45 2 V BOHZ NTSC 720p H 33kHZ V GOHZ NTSC 1080i b Signal level Y 1Vp p pb 0 350Vp p pr 0 350Vp p c Impedance 750 CONFIDENTIAL DO NOT COPY Page 5 4 File No SG 0145 Chapter 6 Block Diagram System Block Diagram 30 WXGA panel Digital AC IN Video bus DC T Speakers Keypad IR Board DVI D SubAudio YPbPr YCbCr S Video AV1 AV2 The monitor s system block diagram is powered by power board that transforms AC source of 100V 240V AC 10 50 60 HZ into DC 12V amp 24Vsource The DC source supplies three important parts of the system block diagram They are the main board and 30 WXGA panel unit The main board receives different types of video signal Afterward the main board process the signals control the various functions of the monitor and outputs control signal video signal and power to the 30 WXGA panel to be displayed The inverter first processes the power send to the panel The function of the inverter is to step up the voltage supplied by the main board to the power that is needed to light up the lamps in the panel simultaneously the digital video signals are processed in the panel and the outcome determines the brightness pixel on off and the color
40. Ma00ns Chi PLE 26 Sep 2004 49 80 20 19 46 CONFIDENTIAL DO NOT COPY Page 9 5 File No SG 0156 CHI DCLK 011 pin W12 Tek Run Y Trig d 4 Chl Pk Pk 5 03 V 1 b 4 4 4 Eis mw EE ware eie i i m x ipid En m uw Ch 1 F req BH 65 47 2 MN NN MN 2 00 V 10 0115 Chi f 26 Sep 2004 12 49 80 20 30 35 CHI DVS UII pinV13 CH2 DHS 011 pinU13 Tek Run Trig d Chi 4 28 V Freq 2 No period found Ch2 Pk Pk 4 72V Ch2 Freq 48 45kH2 Chil v ous E Chi FA T TEN 26 Sep 2004 60 00 20 34 17 CHI BLANK 011 pin Y15 Tek Run Chi 4 88V Freq 48 41 2 2 00 V MU TTE chi 7 TV 26 Sep 2004 30 60 20 40 16 CONFIDENTIAL DO NOT COPY Page 9 6 File No SG 0156 CHI DBE 011 pin Y19 Tek Run T Trig d eines eee eens Dee Ch1 5 54 V Freq 4 066MH2 DC Tt Cc aiiis ia 2 00 V 20015 Chl 7 1 72 26 Sep 2004 50 60 20 46 52 CHI AO U11 pin Tek ET 1 Ch1 Pk Pk j 3 93V Freq 1 472MHz z 26 Sep 2004 50 60 20 54 42 CHI DO 011 pin F4 TREE Chl 1 3 96V 111 wal Chi Freq 1 645MH2 WE Pace Ge p
41. OSD style Translucent Opaque IR Command Set A B CONFIDENTIAL DO NOT COPY Page 3 5 File No SG 0156 Chapter 4 Factory preset timings This timing chart is already preset for the TFT LCD analog amp digital display monitors Horizontal Vertical Horizontal Vertical Pixel Resolution Refresh rate Frequency Frequency Polarity Polarity Rate 640x480 sis 25178 640 480 37 5kHz 75 00Hz 31 500 Remark P positive N negative Native Resolution Vertical Horizontal Refresh Horizontal Vertical Mode No Resolution sync sync Dot rate Rate Frequency Frequency Polarity Polarity 75 ____ na _ ome w am ew Ls sre CONFIDENTIAL DO NOT COPY Page 4 1 File No SG 0156 Chapter 5 Pin Assignment The TFT LCD analog display monitors use a 15 Pin Mini D Sub connector as Pin video input source 1 2 10 11 12 13 14 15 Red Green Blue Ground Ground R Ground G Ground B Ground 5V for DDC Ground No Connection SDA H Sync Composite Sync V Sync SCL CONFIDENTIAL DO NOT COPY Page 5 1 File No SG 0156 The TFT LCD digital display monitors use a 24 Pin DVI D connector as video input source 1 TMDS negative differential input channel 2 2 TMDS positive differential input channel 2 3 Logic Ground 4 Reserved No connection 5 Reserv
42. Receiver uses Panel Link Digital technology to support HDTV and high resolution digital displays for DTV and PC applications It features High bandwidth Digital Content Protection HDCP for secure delivery of high definition video in consumer electronics products The Sil 169 is a DVI 1 0 compliant digital output receiver with built in High bandwidth Digital Content Protection HDCP It provides a simple cost effective solution for DTVs implementing DVI HDCP Pre programmed HDCP keys simplify manufacturing while providing the highest level of security There is no need to use encrypted keys program EPROMS s or cure epoxy coating the functional blocks of the chip STAG OUT 3 HDCP HDCP Decryption Keys Engine EEPROM TMDSTM AOR encrypted Mask unencrypted Digital Panel Link TMDS Core The Panel Link TMDS core accepts as inputs the three TMDS differential data lines and the differential clock The core senses the signals on the link and properly decodes them providing accurate pixel data The core outputs the necessary sync signals HSYNC VSYNC clock ODCK and a display enable DE signal that drives high when video pixel data is present The SCDT signal is output when there is active video on the DVI link and the PLL has locked on to the video SCDT can be used to trigger external circuitry indicating that an active video signal is present or used to place the device outputs in power down when no signal is present by tying SC
43. Setup a Language English France Spain b Gamma Linear Vivid1 Vivid2 Vivid3 c Wide Panoramic Widescreen Zoom Standard d PiP 1 Switch On Off 2 Style Off Small Large 3 Pos Upper left Upper center Upper right Middle left Middle right lower left lower center lower left 4 Source TV DVD AV2 S AV1 5 TV Channel e OSD style Translucent Opaque f IR Command Set A B C 2 PC digital A Picture a Brightness b Contrast c Sharpness d Color Temp User 5000k 6500k 9300k R Red setting G Green setting B Blue setting B Audio a Volume b Treble c Bass d Balance e Spatial C Setup a Language English France Spain b Gamma Linear Vivid1 Vivid2 Vivid3 c Wide Panoramic Widescreen Zoom Standard d PiP CONFIDENTIAL DO NOT COPY Page 3 2 File No SG 0156 1 Switch On Off 2 Style Off Small Large 3 Pos Upper left Upper center Upper right Middle left Middle right lower left lower center lower left 4 Source TV DVD AV2 S AV1 5 TV Channel e OSD style Translucent Opaque f IR Command Set A B C 3 AV2 S AV1 DVD HDTV Mode A Video a Brightness b Contrast c Color d Tint e Sharpness 1 5 f Color Temp normal Warm Cool g Noise Reduct B Audio a Volume b Treble c Bass d Balance e Spatial C Setup a Language English France Spain b Gamma Linear Vivid1 Vivid2 Vivid3 c
44. T COPY Page 9 28 File No SG 0156 Chapter 10 Trouble shooting MONITOR DISPLAY NOTHING PC MODE DVI amp ANALOG Is Power board output 12 Is connector good 3 15 DC DC OK 4 15011 working ok NO LED is lighted It is in power saving No Check video cable Is the timing supported Check GHS and GVSI Check U6 if analog SOG Check U33 If diaital LED is lighting Yes NO Is backlight on 1 Check w6 2 15 inverter ok It means data to LVDS NO 1 15 w5 connected good 2 Check w5 V120 V 3 Check U21 amp U11 4 16 panel U11 no data out NO It means data from U6 or U33 U11 no data in 1 15 011 working good 2 15 U33 amp U6 working good 1 Check U33 if digital 2 Check power of U33 if digital 3 Check 9 if digital 4 Check U6 if analog 5 Check power of U6 if analog 6 Check w1 if analog END CONFIDENTIAL DO NOT COPY Page 10 1 File No SG 0145 Start Input signal is good Yes UT3 input is correct Yes U10 input is correct Yes U19 input is correct Yes U11 input is correct Yes LVDS input is correct Yes 1 16 W5 connected is good 2 15 panel working ok END CONFIDENTIAL DO NOT COPY NO NO NO NO NO NO TV VIDEO1 2 S VIDEO IS NOT DISPLAY CORRECTLY 1 Check video 2 Check hosts setting 1 Check JT5 input if composite 2 Check tuner UT6 PIN12 if TV mode
45. TU R 601 Memory Control This chip has five analog input port and mainly carries out analog to digital conversion for the following digital video processing These input port are clamped to the sync back porch and are amplified by a variable gain amplifier One input is for connection of S VHS carrier chrominance signal Four inputs are for composite video or S VHS luma signal VPC 32xxD provides two analog RGB YCrCb input ports one with Fast Blank capability and one without It is strongly recommended to use analogue 5 MHz anti alias low pass filters on each input including FB While all signals need to be capacitively coupled by 220 nF clamping capacitors the Fast Blank input requires DC coupling input ports are configured as follows Input Vin2 Vin3 Vin4 FB1IN B1 CB1IN G1 Y1IN R1 CR1IN B2 CB2lN G2 Y2IN 74 75 B2CB2N 6 00 CONFIDENTIAL DO NOT COPY _ Input input Input Input Input Input Input Input Input ovid Y2 Sivd C2 Page 8 17 File No SG 0156 Color decoder The standard luma chroma separation and multi standard color demodulation is carried out The color demodulation uses an asynchronous clock thus allowing a unified architecture for all color standards The color decoder also provides several special modes wide band chroma format which is intended for S VHS wide bandwidth chroma Also filter settings are available for processing a PAL help
46. Wide Panoramic Widescreen Zoom Standard d PiP 1 Switch On Off 2 Style Off Small Large 3 Pos Upper left Upper center Upper right Middle left Middle right lower left lower center lower left 4 Source TV DVD AV2 S AV1 5 TV Channel e OSD style Translucent Opaque Command Set A B C CONFIDENTIAL DO NOT COPY Page 3 3 File No SG 0156 4 TV A Video a Brightness b Contrast c Color d Tint e Sharpness f Color Temp normal Warm Cool g Noise Reduct B Audio Volume Treble Bass Balance Spatial MTS Mono Stereo SAP C TV a Source Antenna Cable b Cable mode auto std Hrc irc Channel scan CC Mode CC1 CC2 Text1 Text2 e Parental Control QO 1 Change password New password Confirm password Setup TV Blocking Setup Movie Blocking Blocking Enable On Off Key Lockout On Off All All but power IR Lockout On Off Factory reset Yes No N 03 A C D Setup a Language English France Spain b Gamma Vivid1 Vivid2 Vivid3 and liner c Wide Panoramic Widescreen Zoom and Standard d PiP 1 Switch On Off 2 Style Off Small Large 3 Pos Upper left Upper center Upper right CONFIDENTIAL DO NOT COPY Page 3 4 File No SG 0156 Middle left Middle right lower left lower center lower left 4 Source TV DVD AV2 S AV1 5 PiP TV Channel e
47. am Det Select at Se me Diet in mo 33 331 Vee 23 GND 211 0 10 V D 504 gt 38 C EI dil gt Vou 2 ILE 2 Vaute emi vin 12 Y oui Yin 5 34 14 Cout 10 De Cine dp 15 in SCL SDA Address 11 3 level 02 3 level O4 O5 Syne out 24 e LautT V Loutl Lout Dr Fur B Rout 2 an Route Operation of power board description Figure 1 shows a schematic of the double forward converter construction and boost converter construction Figure 2 shows a schematic of the fly back converter structure Fly back converter topology is shown in Fig 2 Referring it Fig 2 the topology works as follows During their power MosFet on times they store energy in their power transformer while load current is supplied from an output filter capacitor When the power MosFet turns off the energy stored in the power transformer is transferred to the output as load current and to the filter capacitor to replenish the charge it lost when it alone was delivering load current CONFIDENTIAL DO NOT COPY Page 8 24 File No SG 0156 When AC voltage through D1 diode into the B point The B point voltage is AC voltage 2 Vb The Vb around resistors R56 and R59 of figure 2 into the pin3 of U5 566841 via to charge C50 When across the voltage of C50 reaches 16V
48. dc the U5 start operating Once U5 operation the Pin8 of the U5 will yield a square waveform of 50KHz frequency to switching Q10 Power MosFET result in power transformer T3 PQ2625 stored energy during Q10 on time and delivered energy during Q10 off time When Q10 turned off will yield biased voltage due to biased winding The biased voltage provides a steady voltage to charge C50 capacitor after via rectifier diode D14 in order to make U5 8G6841 continue operation Once power transformer T3 start delivering energy to secondary the secondary will yield a DC voltage to output after via rectifier diode 011 and rr type filter of capacitor C46 and inductor L4 and capacitor C47 The V K A of the U7 from high voltage slowly decreases to closely steady voltage when output slowly increases Simultaneously the slightly current follows Pin 1 2 of the photocopier U6 and Pin 3 4 of the linear regulator U7 after output voltage is sensed by sampling resistors R66 and R70 and compared to a reference voltage Vref 2 5Vdc in the reference point Pin1 of the U7 Due to Pin2 of the U5 vary versus current amplitude that follow Pin 1 2 of the U6 The Pin2 of the U5 is fed to a pulse width modulator PWM to control duty cycle with comparator to Pin6 of the U5 so that make output voltage steady PFC converter topology is shown in Fig 1 Referring it Fig 1 the topology works as follows When Q1 turns on off the polarity across L1 reverse and the dot end A po
49. e interlaced by FLI3210 The de interlace processor automatically determines and de interlace the incoming video content static or motion and applies different algorithm to each of the content type An external SDRAM is used to help store the video fields and motion video data processed in FLI3210 More over the internal memory controller in FLI3210 controls the external SDRAM What s more FLI3210 offer programmable functions like video enhancement and PIP picture in picture PIP functions by activating the primary and secondary port simultaneously In short FLI3210 output display port digital signals up to 74 Mpixel sec to the PW166B generate the vertical and horizontal timing signals for display device All functions are controllable by the main board Plus all functions in the IC boards are programmable using 2 Bus CONFIDENTIAL DO NOT COPY Page 6 3 File No SG 0145 Chapter 7 Main Board l o Connections W3 CONNECTION TOP BOTTOM OSD CONTROL Auto Left Right Source W4 CONNECTION TOP BOTTOM 017 W6 CONNECTION TOP BOTTOM 1204 1204 1204 Light 11 Pwm CONFIDENTIAL DO NOT COPY Page 7 1 File No SG 0156 Chapter 8 Theory of Circuit Operation The operation of D SUB 15pin route The D SUB 15pin is input analog signal into the video switch M61323fp Then the signal is process to the A D converter ADC9883 and
50. e the power control bits described in Power Saving Modes configured as follows CONFIDENTIAL DO NOT COPY Page 8 8 File No SG 0156 Mode DCLK GCLK OFF MCLK ri MEM LOW OFF OFF OFF OFF DIS PWDN PWR Normal Used when the chip is in 0 0 0 0 0 typical operation Reduced Used in DPMS with the 1 0 0 1 display turned off but with data inputs continually scanned for input Used when the PW1S8B can 1 1 1 1 1 wail for an external reset signal to bring it out of this lowest power stata The GPIO block incorporates two 8 bit general purpose ports Each bit in each port is individually controllable as either input or output The three ports are configured as follows Pin name Function Type Description PORTAO mput Output 2 SDA PORTA Input Output 2 SCL PORTA2 VPCON Output Control LED Green Blue and Main board Power on off PORTA3 ADCEN Output AD9883 SOGOUT Enable AD9883S0GOUT Enable 2 SCL Panel Bright control Enable or disable Marco vision PORTB6 Not use 7 1231 SDA Input Output 2 SCL CONFIDENTIAL DO NOT COPY Page 8 9 File No SG 0156 Graphics port The graphics port Gport is an input interface for high speed RGB data up to UXGA It accepts incoming data at one or two pixels per clock The GPort can input data at rates up to 236 MPixels second It also has sync separator circuitry timing signals for PLL control and clock bufferi
51. ed No connection 6 DDC2B Clock 7 DDC2B Data 8 Reserved No connection 9 TMDS negative differential input channel 1 10 TMDS positive differential input channel 1 11 Logic Ground 12 Reserved No connection 13 Reserved No connection 14 Power 15 Logic Ground 16 SENSE Pin Pull High 17 TMDS negative differential input channel 0 18 TMDS positive differential input channel O 19 Logic Ground 20 Reserved No connection 21 Reserved No connection 22 Logic Ground 23 IMDS positive differential input reference clock 24 TMDS negative differential input reference clock CONFIDENTIAL DO NOT COPY Page 5 2 File No SG 0145 Four Pin mini DIN S Video Connector Pin Assignment 1 2 GND Luminance Y 4 Chrominance C Signal Level Video Analog 0 1Vp p 75 Video Analog 0 286 75 sync H V 0 3V below Video Y Frequency 15 734Khz V 60HZ NTSC Video Output Connector Signal Level Video Y C Analog 0 7Vp p 75Q sync H V 0 3V below Video Y C RGB Signal a Sync Type TTL Separate Composite or Sync On Green b Sync polarity Positive or Negative c Video Amplitude RGB 0 7 Vp p d Frequency support to 30 70 4 V support to 50 85MHZ Audio Signal a Signal Level 1Vrms b Frequency Response 250HZ 20kHZ CONFIDENTIAL DO NOT COPY Page 5 3 File No SG 0145 Component Signal Ycbcr a Frequency
52. een The PW166B direct control the LED s when PW166B VPCON is low the LED is Green Close power when PW166B VPCON is high the LED is Orange Open power The operation of Analog port The analog port are consisted with 15 pins mini D Sub connector which receiving video signal from host device EEPROM which compliance with DDC1 DDC2B protocol H sync and V sync detecting circuit which regenerate synchronous signal for PW166B detecting video signal matching circuit and AD9883A which capturing RGB graphics signal and digitize each pixel The pin assignment of 15 pins connector are as follows 1 Green signal Blue signal GND Ground GND Ground ND 6 GND RGomd 8 GND B Ground 9 v FoDDC GHSI H Sync 14 RVSI V Sync 15 RGSL SCL CONFIDENTIAL DO NOT COPY Page 8 2 File No SG 0156 RGB graphics signal of host device transmits to the analog port through pin 1 to 3 The video signal should be coupled to RIN GIN BIN and SOGIN of AD9883A through C78 C75 C74 and C76 The EDID data is stored in EEPROM 24LC21 which compliance with DDC1 DDC2B protocol that performs a plug and play function When in DDC1 protocol the host device access the EDID data through RVSI pin14 and RGSA pin12 while RGSL pin15 is held high But in DDC2B protocol the host device access EDID data through RGSA pin12 and RGSL pin15 The SCL SDA should be pull up through R28 R27 and are voltage limitation through D
53. er signal A block diagram of the color decoder as follows Luma 5 Notch te Filter 1 H Delay CrassSwitch IF Compensation Lowpass Filter MIXER Phase Freq DC Reject Demodulator Chroma Chroma ColorPLL AColorACC Output port amp ITU R 656 Output Format This interface uses an YcrCb 4 2 2 data stream at a line locked clock of 13 5 MHz Luminance and chrominance information is multiplexed to 27 MHz in the following order Cb1 Y1 Cr1 Y2 Timing reference codes are inserted into the data stream at the beginning and the end of each video line A Start of active video Header SAV is inserted before the first active video sample A End of active video code EAV is inserted after the last active video sample For activation of this output format the following selections must be assured 13 5 MHz line locked clock Double clock mode enabled TU R656 mode enabled Binary offset for Cr Cb data CONFIDENTIAL DO NOT COPY Page 8 18 File No SG 0156 All data and sync pins operate at TTL compliant levels and can be tristated via I2C registers Additionally the data outputs can be tristated via the YCOE output enable pin immediately This function allows the digital insertion of a 2nd digital video source To minimize crosstalk data and clock pins automatically adopt the output driver strength depending on their specific external load max SOpF Sync and FIFO
54. he pixels are processed as follows Output red pixel input red pixel RCONT 7 0 128 RBRITE 7 0 Output green pixel input green pixel GCONT 7 0 128 GBRITE 7 0 Output blue pixel input blue pixel BCONT 7 0 128 GBRITE 7 0 CONFIDENTIAL DO NOT COPY Page 8 11 File No SG 0156 Where CONT should be set to 0x80 for normal operation The registers 7 0 are unsigned values between 0 and 255 The registers xBRITE 7 0 are signed values between 128 and 127 where 0x00 0 The color look up table replaces each input pixel with a new value based on register tables stored in the PW166B This function is used to compensate the inherent gammas of the display device and the data source It uses piece wise linear function to get the output value The color space expander allows up to all of the 10 bits per pixel coming from the color look up table to be used to create as many gray shades as possible on the display device The color space expansion is performed using Frame Rate Modulation FRM and Dithering Dithering is performed before FRM The de multiplexer registers the display pixels before they output to the display The pixels can also be set to zero here or set to default value The de multiplexer can support one pixel per clock or two pixels per clock mode On one pixel mode the data is sent out on pins DRE97 0 DGE 7 0 and DBE 7 0 every DCLK But two pixels mode the data is sent
55. int of L1 rises to a voltage B point higher than the input voltage Vin Energy stored in L1 during Ton is transferred via D2 to the load and C4 during the Q1 off time Another the steady biased voltage also to charge capacitors C22 and C19 as across them voltage reaches 13Vdc the IC1 CM6800 1 continue operation when Pin C of the CN1 and CN3 is a high signal 5V Once IC1 operation the Pin12 of the IC1 will yield a square waveform of about 69KHz frequency to switching Q1 Power MosFet and cause 1 start storage energy during Q1 on time and deliver energy during Q1 off time It can be shown that the output input voltage relation of such a boost converter is given by Vin Vo B point Eq 1 1 1 Ton T CONFIDENTIAL DO NOT COPY Page 8 25 File No SG 0156 Now throughout the half sinusoids of Vin the Q1 on time denoted by Ton is width modulated in accordance with Eq 1 1 to yield a constant DC voltage Vo B point is about 380Vdc somewhat higher than the peak of input voltage sine wave The on time throughout the sinusoidal half periods is controlled by a PFC control chip IC1 which senses Vo B point via R3 and R14 resistor compares it to an internal reference in a DC voltage error amplifier Pin15 of IC1 and in a negative feedback loop Pin 3 of the IC1 sets Ton to keep Vo constant at the selected value When Vo reaches 380Vdc the FB point Pin 15 of IC1 is closely 2 5Vdc It will drive
56. ize is ok 1 Adiust contrast amp brightness Too dark or light 2 Adjust gamma Adiust color temperature Color unbalance 1 Adiust Color 2 Adiust color temperature R G B 1 Check signal U11 to LVDS 2 Check signal U19 to U11 ite 3 Check signal U10 to U19 4 Check signal UT3 to W10 CONFIDENTIAL DO NOT COPY Page 10 7 File No SG 0145 IMAGE QUALITY IS NOT GOOD DVD HDTV It means image exceed or less than display area 1 18 scaling in fill all 2 Check U21 amp U1 3 Check U19 amp U11 4 Check ripple dc ac 1 Adiust contrast amp brightness 2 Adjust gamma Too dark or gt 3 Adjust color temperature 1 Adiust Color 2 Adiust color temperature R G B Color 1 Check signal U11 to LVDS 2 Check signal U19 to U11 Colors rpolate 3 Check signal U10 to U19 4 Check signal UT3 to w10 CONFIDENTIAL DO NOT COPY Page 10 8 File No SG 0145 DISASSEMBLY INSTRUCTIONS 1 REAR COVER ASS Y REMOVAL Note Spread a mat underneath to avoid damaging the LCD TV surface 1 Remove eleven screws from rear cover 2 Separate the rear cover 3 Remove four small screws and one large screw 2 Power shield 4 Separate the Power shield 5 Remove fifteen screws 2 from Main shield 6 Remove nine screws 6 and three screws 5 from IO 2 8 Separate the Main shield from chassis 1
57. k Run Trig d ae ae CC ON NU NN 2 00 V 10 005 Chl f ATX i3 50 40 CONFIDENTIAL DO NOT COPY Chi Pk Pk 3 80 V Freq 2 No period found Ch2 4 48 V Ch2 Freq 48 37 kH2 27 Sep 2004 00 01 47 4 48 Freq 48 36kH2 27 Sep 2004 00 04 14 Ch1 4 84 V Freq 64 83MH2 27 Sep 2004 00 06 47 Page 9 10 File No SG 0156 CHI DRE pin R19 Tek Run Y Trig d 1 Chl Pk Pk 1 5 04 Freq 2 No period found edd eedem 2 00 V 40 0115 Chi 1 16 V 27 Sep 2004 12 50 40 00 11 00 TXOUTI 021 pin 46 Tek SSP 1 dU tu 0 1 C m Chi Freq YT 4 142 2MH2 ae E E ee EN 500 20 015 Chi 1 16 V 27 Sep 2004 19 50 40 00 15 07 HDTV YPbPr DVD Mode 4801 480 4801 Y COMPI U3 pin 4 Tek Prevu 820 e nee Freq i 1 220 1kH2 TENER ee UNS NCC UN NCC NTC RFT RECEN 500mV 200 5 Chl f 2 34 V 27 Sep 2004 70 40 00 38 32 CONFIDENTIAL DO NOT COPY Page 9 11 File No SG 0156 CHI SYNC DET U3 pin24 Tek SSP Y
58. lows USA UL Canada CSA Germany VDE Switzerland SEV Britain BASEC BS Japan Electric Appliance Control Act or an AC cord that meets the local safety standards VIZIO L30WGU Service Manual Chapter 1 Features 1 Built in TV channel selector for TV viewing 2 Simulatnueous display of PC and TV images 3 Connectable to PC s analog RGB port and digital port 4 Connectable to digital port HDCP 4 Built in s video HDTV composite video and TV out 5 Built in auto adjust function for automatic adjument of screen display 6 Smoothing function enables display of smooth texts and graphics even if image withresolution lower than 1280x768 is magnified 7 Picture In Picture PIP funtion to show TV or VCR images 8 Power saving to reduce consumption power too less than 3W 9 Screen Display user can define display mode ie color brightness contrast sharpness sound setting PIP TV channel program aspect and gamma or reset to factory setting CONFIDENTIAL DO NOT COPY Page 1 1 File No SG 0156 Chapter 2 Specification 1 LCD CHARACTERISTICS Type WXGA TFT LCD Size 30 inch Active Screen Size 29 53 inches Outline Dimension 683 6 H x 431 8 V x 41 6 D Display Area 643 20 H x 385 92 V Pixel Format 1280 horiz By 768 vert Pixels RGB strip arrangement Display Color 16 7M colors Luminance White 600 cd m2 Typ Power Consumption 6 6Watt Typ Weight 5000 g Typ Display Operating M
59. m the CVBS input The comb filtered Cg Cg components are interpolated up sampled by the low pass block characteristic is controlled by LUBW sub address 09H bit4 to modify the width of the chrominance notch without influencing the width of the chrominance notch without influencing the chrominance path The function Chrominance and Luminance diagram as follows CBS IN uU WM ADEL EOMEENSATIEN SUBTRACTOR p LUMINANCE PEAKING TUE D LOW PASS Y DELAY ADJUSTMENT QUADRATURE 08 04 INTERPOLATION DOON 7 0 MODULATOR LOW PASS 3 CAT 7 0 SET RAW YDEL as Je FILTER SET 1 0 m colo CVESIN QUADRATURE LOWPASS 1 ERIGHTAESS or CHAIN COWNSAMPLING CONTRAST NEUE SATURATION CONTROL SUBCARRIER RAW COCHE CHEW HAW DATA Gg bR OUT GENERATION 2 SET imus GAIN AMT OFFSET HREF DUT SECAM CONTROL CHROMNANCE 1 PROCESSING INCREMENT YCOMB DELAY Cp Cg SET RAI SET VH CHROMINANCE PHASE Lt e EL ANPLITLDE SLECARHIER SUBCARRIER DETECTOR CONTROL GENERATION 1 INCREMENT LUE T PAL DELAY LINE GENERATION ire ECAN AND EE ADJUSTMENT RECOMBINATION LOOP FILTER HUEC INCS DCVr CSTD 2 0 ACEC CGAINTED ATCO 3 switch signal CONFIDENTIAL
60. n the host controls the exchange of these values between the host transmitter Sil 170B and the receiver Sil 169 in the display device The KSV and two other values An and Ri are exchanged over the DDC channel I2C bus of DVI The receiver is a slave on this I2C bus Figure 14 shows a typical HDCP system configuration CONFIDENTIAL DO NOT COPY Page 8 6 File No SG 0156 D 23 0 D 23 0 IDCK IDCK HSYNC HSYNC S11 170B VSYNC e VSYNC in 220 x nce Il i 3 3V TxSCL 3 3V TxSDA SDAS SCLS DDC SDA E DDC SCL Host GO METER laa cS DVI k Link Fiaure 14 HDCP Svstem Architecture The operation of PW66B The PW166B is highly integrated System on a chip that interfaces computer graphics and video inputs in virtually any format to a fixed frequency flat panel display An embedded DRAM frame buffer and memory controller perform from rate conversion Computer images from VGA to UXGA resolution input to the chip can be resized to fit on the target display device The on chip microprocessor incorporates with frame buffer resizing circuitry and peripheral circuit should supports the features that is frame rate conversion image scaling automatic image optimization picture in picture on screen display and user adjustment The internal block diagram of PW1
61. ng and conditioning circuitry The graphics port has three input sources that is from analog port digital and de interlace The data cannot exist simultaneously to avoid interference with each other and that is controlled through INSEL COMP SEL INSEL and DVI ON The block diagram of graphics port is as follows 0 G E Register EN YPbPr to G 7 0 and Interface GGO 7 0 Multiplexer GBO 7 0 Clock GCLK Generator GHS Sync GVS Decoder and giri Auto Image Optimization GREF GFBK PEE GBLKSP Control GCOAST The sync decoder detects and processes the horizontal sync GHS vertical sync GVS sync on green GPENSOUT and field GFIELD inputs used for timing There are several bits to indicate the status of the inputs For horizontal sync HSOK 1 indicates that the horizontal line rate is faster than 10KHz For vertical sync VSOK 1 indicates that the vertical field or frame rate is faster than 10Hz For sync on green SOGACT 1 indicates that transitions on GPENSOUT are occurring faster than 10Hz The PLL control block generates the timing signals required for an external PLL GCOAST is an output used to tell the PLL to coast during vertical blanking This is used to keep the PLL from making spurious change due to extra or missing HSYNC pulses Output GREF is a polarity corrected delayed version of the active horizontal sync signal GREF is delayed from the input HSYNC by an amount specified by register PHASE 7
62. ode Transmissive mode normally Black Surface Treatment Hard coating 2H Anti glare treatment of the front polarizer 2 OPTICAL CHARACTERISTICS 2 1 Viewing Angle by Contrast Ratio Y 10 Left 85 typ Right 85 typ Top 85 typ Bottom 85 typ 3 SIGNAL Refer to the Timing Chart 3 1 Sync Signal 1 Type TMDS 2 Input Voltage Level 90 240 Vac 50 60 Hz 3 Input Impedance 50 Signal line 3 2 Operating Frequency RGB Signal support to 30K 70KHz V support to 50 85Hz Pixel Clock support to 110MHz DVI Signal H support to 30K 80KHz V support to 50 85Hz Pixel Clock support to 110MHz CONFIDENTIAL DO NOT COPY Page 2 1 File No SG 0156 S Video Video Y Analog 0 1Vp p 75Q Video C Analog 0 286p p 75Q Component signal YCbCr H 15 734KHz V 60Hz NTSC interlace H 31KHz V 60Hz NTSC progressive YPbPr H 15 734KHz V 60 2 5 4801 H 31KHz V 60 2 5 480 H 45KHz V 60Hz NTSC 720p H 33KHz V 6OHZ NTSC 1080i Composite Video signal 15 734KHz 6 2 NTSC F Type TV RF signal 15 734KHz V 60Hz NTSC Audio Signal Frequency Response 250 Hz 20KHz 4 Input Connectors a RJ11 For RS232 Controls b 24 pin DVI For DVI HDCP input c RCA x2 For DVI HDCP input d D sub 15pin x 1 For Analog RGB e Mini Jack L R x 1 For PC analog Audio input f YPbPr RCA x 3 For HDTV input g YCbCr RCA x 3 For DVD input h S Video 4pin DIN x 1 i RCA
63. of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that the interference will not occur in a particular installation If this equipment does cause unacceptable interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures reorient or relocate the receiving antenna increase the separation between equipment and receiver or connect the into an outlet on a circuit different from that to which the receiver is connected FCC WARNING To assure continued FCC compliance the user must use a grounded power supply cord and the provided shielded video interface cable with bonded ferrite cores Also any unauthorized changes or modifications to Amtrak products will void the user s authority to operate this device Thus VINC Will not be held responsible for the product and its safety CE CERTIFICATION This device complies with the requirements of the EEC directive 89 336 EEC with regard to Electromagnetic compatibility SAFETY CAUTION Use a power cable that is properly grounded Always use the AC cords as fol
64. on is good 2 Check U23 is 12V 5V 3 Check U25 is 12V gt 3 3V U23 amp U25 Voltage Yes NO The voltage is about 12V while power switch on 1 Check U27 pin1 is 12V 2 Check U27 pin 2 4 is OV Yi NO The voltage is about 3 3V while power switch on 1 Check U29 pin1 is 3 3V 2 Check U29 pin 2 4 is OV Yi es es NO The voltage is about 5V while power switch on 1 Check U31 pin1 is 5V 2 Check U31 pin 2 4 is OV es es Y NO The voltage is about 5V while power switch on 1 Check U32 pin1 is 12V 2 Check U32 pin 2 4 is OV Y END CONFIDENTIAL DO NOT COPY Page 10 4 File No SG 0145 TROUBLE OF DDC READING Start NO Analog DDC OK NO Digital DDC OK Yes END CONFIDENTIAL DO NOT COPY Support DDC1 2B 1 Analog cable ok 2 Check signal U2 to W1 3 Check U2 4 15 compliant protocol Support DDC2B 1 Digital cable ok 2 Voltage of VCCX ok 3 Check signal U34 to W9 4 Check U34 5 Is compliant protocol Page 10 5 File No SG 0145 Start YES Image size is ok YES Vertical stripe NO Position shift NO Horizontal stripe NO Too dark or light CONFIDENTIAL DO NOT COPY IMAGE QUALITY IS NOT GOOD PC MODE It means image exceed or less than display area 1 15 scaling in fill all 2 do auto tune function with full screen Patten 3 16 the timing supported 4 Check U33 if digital 5 Check U6 if analog 6 Check
65. output to the pw166B the pw166B generates the vertical and horizontal timing signals for display device The operation of DVI amp HDCP CON route The DVI amp HDCP CON is input digital signal the signal is process to the sil169 Then transfer to the pw166B the pw166B generates the vertical and horizontal timing signals for display device The operation of HDTV amp DVD route HDTV amp DVD signal is transfer to video switch M61323fp the M61323fp can to determine signal witch one signal is to the VP3230 decoder and witch one is to ADC9883 When signal transfer for the VP3230 decoder and output to FLI2310 de interlace then transfer the pw166B generates the vertical and horizontal timing signals for display device When signal to the ADC9883 then output to pw166B generates the vertical and horizontal timing signals for display device The pip mode is signal to saa7118 decoder then transfer to the pw166B generates the vertical and horizontal timing signals for display device The operation of S Video route The S Video signal is input to TA1218N switch then transfer signal to VP3230 decoder and output to FLI2310 de interlace then use graphic port transfer signal to pw166B generates the vertical and horizontal timing signals for display device The pip mode is signal to 7118 decoder then transfer to the pw166B generates the vertical and horizontal timing signals for display device The operation of Video 1 2 route Video 1 2
66. red is application dependent To enable all the possible format conversions usage of a 166 MHz SDRAM is advised SDRAM Interface Block Diagram Pin name Function Type Description MCLKFB VIDMFB Input SDRAM clock feedback RAS 23SDRAS Output SDRAM row address strobe CAS 23SDCAS Output SDRAM column address strobe NE 23SDWEN Output SDRAM write enable SDRAM Compatible Devices Tested fully functional SORAM Devices MBXIEG43242B GLT5640L 32 HY357V643220 MT48LC2M32B2 KAS643232C 5986432 CONFIDENTIAL DO NOT COPY Page 8 15 File No SG 0156 Noise Reducer A motion adaptive frame based recursive noise reduction is performed on both chroma and luma data The external SDRAM frame memory is used for this purpose An innovative noise meter measures the amount of noise in the picture The noise measurement is done within the active video region and not in the blanking region This eliminates the possibility of wrong noise measurement due to the clamping normally done during blanking period by analog to digital converters The degree of sensitivity to motion is programmable Depending on the degree of noise present and motion sensitivity defined the recursive filter values are selected Facial features may be adversely affected if the noise reduction done on such areas uses the recursive filter levels optimized for the overall picture To prevent this and to provide a more natural picture flesh tones are identified and during
67. riod found Ch2 Freq 15 72kH2 1 Ch2 Pk Pk 3 92 V 27 Sep 2004 01 06 54 Ch1 3 37 V Freq 27 39 2 27 2004 01 11 37 Ch1 3 52 V 1 Freq 29 94 Hz 27 Sep 2004 01 14 27 Page 9 13 File No SG 0156 CHI VID Y7 U10 pin 31 CH2 VID YO U10 pin 40 Tek Run T Trig d Ss pe MOTOR tena pepe ae A ORE 1 1 lee e 4 4 4 4 4 40640404 4 4 4 4 0 0 1 8 rey i Ch1 3 70 rt Ch1 Freq 6 763 2 Ch2 Pk Pk 2 6 751 2 Lieu uri a n i C 27 Sep 2004 5 50 00 01 27 38 1 1231 SDA 019 pin 46 2 1231 SCL 019 pin 45 Tek prevu Y 2 88 Freq 21 14 2 Ch2 2 96V Ch2 Freq 45 67 kH2 2909 Ch2 2700 V ELIJT Chi 2 TAN 27 Sep 2004 20 00 01 52 43 CHI 4 U19 pin 191 Tek Prevu Ibit I ce EI ee SE HF eb FE e b ERE ERR Ch1 Freq 4 1 20 11MH2 TEE ROME AVETE RIS 1 o EEN PFIN Fae eS Pe TEER e 2 00V 40 008 Chi 1 96 27 Sep 2004 0 50 00 02 07 51 CONFIDENTIAL DO NOT COPY Page 9 14 File No SG 0156 CH1 GVS 019 119 CH2 GHS U19 pin 118 Tek Run Trig d PES EE
68. signal input to TA1218N switch and transfer signal to VP3230 decoder and output to FLI2310 de interlace then transfer to the pw166B generates the vertical and horizontal timing signals for display device The pip mode is transfer to saa7118 decoder then transfer to the pw166B generates the vertical and horizontal timing signals for display device The operation of TV route TV signal is processes to the tuner and output to TA1218N switch then transfer to VP3230 decoder and output toFLI2310 de interlace then transfer to pw166B generates the vertical and horizontal timing signals for display device The pip mode is signal to 7118 decoder then transfer to the pw166B generates the vertical and horizontal timing signals for display device CONFIDENTIAL DO NOT COPY Page 8 1 File No SG 0156 The operation of keypad There are 8 keys to control and select the function of SHD 3010 and also have two LED to indicate the status of operation They are power Source MENU VA Auto keys and LED 1 The power key through POW and GND to control PW166B PW166B will receive a low signal to turn on or off system while press the power key 2 The other seven keys are on high state because the pull up resistor but will transit to low state dependent on which key pressed and the state will be reader by PW166B through DO to D6 to act corresponding function 3 The LED is constructed with two separate LED which color is blue and Gr
69. the presence of flesh tones the noise reduction algorithm is modified Noise reduction is done only on standard definition PAL and NTSC inputs Microprocessor Interface A standard 2 wire serial interface enables convenient register control All the blocks are fully programmable The device address of the chip is programmed with the hardware settings of the DEV ADDR 1 and ADDR 0 pins preventing conflict with the other devices connected to the bus The slave address can be set to any of the following values Table 4 2 Device address setting DEV ADDR 0 Write Addr Read Addi 00 ___01_ Ch Cu ____ pf Du ___ The operation of VPC3230D The VPC3230D is a high quality single chip video front end which is targeted for 4 3 and 16 9 50 60 and 100 120 HZ TV sets It can be combined with other members of the Digit3000 IC family And or it can be used with 3 part products CONFIDENTIAL DO NOT COPY Page 8 16 File No SG 0156 21 E VIN2O WOUT RGB YCrcb d YCGrCb Input port Analog Front end Analog ompoaonser Front End Adaptive Comb Filter NTSC Matrix Contrast Saturation 4 x ADC pe Brightness Color Decoder Saturation Tint 20 Sealer PIP Panorama Made Contrast Brightness 20 25 MHz 12 Bus Output Formatter ITU R 656 I
70. x3 For CVBS A V input 1 RCA x 3 For CVBS A V input 2 k F terminal RF CVBS RCA x 3 For CVBS A V output 5 POWER SUPPLY Consumption 170W DPM Mode Not Active OFF less than 3 W Low 2096 Power OFF to less than 3W CONFIDENTIAL DO NOT COPY Page 2 2 File No SG 0156 6 Speaker Output 8 5W max X2 7 ENVIRONMENT Operating a Temperature 5 35 C b Relative humidity 10 90 c Altitude 0 10 000 amp Non operating a Temperature 20 50 C b Relative humidity 10 90 c Altitude 0 40 0000ft 8 DIMENSIONS with TILT SWIVEL GATEWAY VERSION a Height 601 1mm b Width 740 0mm c Depth 198 0mm Wynn version a Height 522 0mm b Width 740 0mm c Depth 100 5mm 9 WEIGHT with TILT SWIVEL GATEWAY version a Net 19 1kgs b Gross 25 8kgs Wynn version a Net 14 1kgs b Gross 20 8kgs CONFIDENTIAL DO NOT COPY Page 2 3 File No SG 0156 Chapter 3 On Screen Display Main unit button Power Source MENU PROG A PROG WV Sound Sound Auto OSD Adjustment 1 Analog A Picture a Brightness b Contrast c Auto picture d Manual picture 1 V position 2 Hsize 3 H position 4 Fine tune e Sharpness 1 5 f Color Temp User 9300k 6500k 5000k 1 Red setting 0 100 2 Green setting 0 100 3 Blue setting 0 100 B Audio a Volume b Treble c Bass d Balance e Spatial CONFIDENTIAL DO NOT COPY Page 3 1 File No SG 0156 C
71. y dr ou ene te Ay EIC NM ll KV 77 win A SC YU VAN 2 00 V 2 0046 Chl 1 72V 26 Sep 2004 50 60 20 56 49 CONFIDENTIAL DO NOT COPY Page 9 7 File No SG 0156 CH1 TXOUTO U21 pin 48 Tek Run Trig d M 1 Tia ont Rave 1 lt Y E T TT 500mV 10 05 Chi 1 20 V 12 50 60 DVI Mode 1024x768 75 HZ Chi Pk Pk 762 Freq 91 74 2 26 Sep 2004 22 26 49 RXB U33 pin81 CH2 RXR U33 pin90 Tek Run T Trig d hes ess 4 4 e i 210 Te Chi 1 00 1 00 40 0115 Ch2 f 12 50 60 Ch1 1 25 V Freq 77 68MH2 Ch2 Freq 77 81MH2 Ch2 Pk Pk 1 32 V 26 Sep 2004 22 48 40 GHS 033 pin48 CH2 GVS 033 pin47 TekRun Y Trig d m MM H Me T e B 1 peace or 1 i 1 07101 0707200107031 848 I 4 9 0809 MEE EE PE A EEL EE E E A A E AE TE ENSEM NNI NON SN NUE NNNM OE ON ON NON NER Ch1 rr um Wee Ch2 f 2 12

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