Design a 100A Active Load to Test Power Supplies
Contents
1. A Ao IC 15V POWERED a BYPASSING NOT SHOWN 0 0010 RESISTORS TEPRO TPSM3 Q 15V GATE DRIVE BIAS CONTROL Figure 5 You can derive a detailed active load schematic from the conceptual design 30 EDN SEPTEMBER 22 2011 www edn com DC POWER SUPPLY ae 3 MINIMIZE INDUCTANCE FIGURE 5 S CIRCUIT 10 000 pF COMBINATION OF OS CON FILM AND CERAMIC CAPACITORS MINIMIZE INDUCTANCE Figure 6 The test fixture for dynamic response has massive broadband bypassing and a low inductance layout This setup provides low loss high current power to Q to maintain the amplifier s phase mar gin and provide low delay and linear current gain A gain of 10 differen tial amplifier provides high resolution sensing across the 1 mQ current shunt resistor You can design a power dissi pation limiter that acts on the aver aged input value and Q s temperature It shuts down the FET s gate drive to preclude excessive heating and subse quent destruction Capacitors can be added to the main amplifier to tailor the bandwidth and optimize the loop response CAPACITORS CAN BE ADDED TO THE MAIN AMPLIFIER TO TAILOR THE BANDWIDTH AND OPTIMIZE THE LOOP RESPONSE You can develop a detailed sche matic based on these concepts Figure 5 The main amplifier A responds to dc and pulse inputs You also send it a feedback signal from A that represents load current A sets Q s conductivity through the Q Q ga2. DESIGN A 100A ACTIVE LOAD TO TEST POWER SUPPLIES BY JIM WILLIAMS CONSULTING EDITOR WIDEBAND RESPONSE LETS YOU TEST FOR THE TRANSIENT BEHAVIOR OF YOUR SUPPLY 28 EDN SEPTEMBER 22 2011 ou use an active load test circuit to ensure that a power supply for a microprocessor or for other digital loads supplies 100A tran sient currents This active load can provide a dc load for a power supply and it can rapid ly switch between dc levels These transient loads simulate the fast logic switching in the microprocessor Ideally your regulator output is invariant during a load transient In practice however you will encounter some variations which become problematic if allowable operating voltage tolerances are exceeded You can base your active load circuit on previous designs of wideband loads that operate at lower currents Reference 1 This approach allows you to design a closed loop 500 kHz bandwidth 100A active load having linear response www edn com IMAGE THINKSTOCK Conventional active load circuits have shortcomings Figure 1 The regulator under test drives dc and switched resistive loads Monitor the switched current and the output volt age so that you can compare the stable output voltage versus the load current under both static and dynamic condi tions The switched current is either on or off You cannot control it in the linear region as it changes You can further develop the con cept b
3. IGGER INPUT NOTES T ALMOST ANY SMALL PULSE TRANSFORMER 1 kQ AND 300 pF VALUES ARE TYPICAL You can make a trigger isolator that floats input BNC s ground using an insu lated shell BNC connector A capacitively coupled pulse transformer avoids loading input maintains isolation and delivers the trigger to the output A secondary resistor on T terminates ringing 34 EDN SEPTEMBER 22 2011 nullifying it with the circuit s base line current trim You could also use a different pulse generator Keep in mind parasitic effects due to probe grounding and instru ment interconnection At pulsed 100A levels you can easily induce parasitic current into grounds and interconnections distorting displayed waveforms Use coaxi ally grounded probes particularly at A s output current monitor and preferably anywhere else It is also convenient and com mon practice to externally trigger the oscilloscope from the pulse generator s trigger output There is nothing wrong with this practice in fact it is a recommended approach for ensuring a stable trigger as you move probes between points This practice does however po tentially introduce ground loops due to multiple paths between the pulse generator the circuit and the oscilloscope This condi tion can falsely cause apparent distortion in displayed waveforms You can avoid this effect by using a trigger isolator at the oscillo scope s external tri
4. IV Figure B Q s top Trace A and bottom Trace B currents show identical characteristics despite high speed operation www edn com 20A DIV 20A DIV T ji T 4 T 2 USEC DIV pjan re k 20A DIV eed ER Ih i ae i f 4 l 20A DIV EER eresa t one tenes eens seen eeens 20A DIV 20A DIV SATa www edn com 500 nSEC DIV ES ee Figure 7 When you optimize the dynamic response you get an exceptionally pure 100A current pulse Figure 8 The response becomes overdamped if you set an excessive feedback capacitor value for A Figure 9 An inade quate feedback capacitor value for A decreases the transi tion time but promotes instability Further capacitor reduction causes oscillation Figure 10 Overdoing the FET s response compensation results in corner peaking Figure 11 By opti mizing the dynamic trims the circuit gets a 650 nsec rise time corresponding to a 540 kHz bandwidth Figure 12 The opti mized trims yield a 500 nsec fall time across the bases of Q and Q to a value well under 1 2V 4 and servos that value until Q and Q have a 10 mA average collector bias current The duty cycle of the load overheats if it is on for too long You can fashion a protection circuit with techniques that high power pulse generator designers use references 2 3 and 4 Feed comparator IC the average input vol
5. ent is either on or off there is no controllable linear region www edn com wideband harmonics into the measure ment that may corrupt the oscilloscope display TRANSIENT GENERATOR Placing Q within a feedback loop allows true linear control of the load tester Figure 3 You can now linearly control Q s gate voltage allowing you to set an instantaneous transient cur rent at any point and to simulate nearly any load profile Feedback from Q s source to control amplifier A closes a control loop around Q stabilizing its operating point The instantaneous input control voltage and the value of the current sense resistor set Q s current over a wide bandwidth You use the dc load set potentiometer to bias A to the conduction threshold of Q Small variations in A s output result in large current changes in Q meaning that A need not supply large output excursions The fundamental speed limitation is the small signal bandwidth of the amplifier As long as the input signal stays within this bandwidth Q s current waveform is identical in shape to A s input control voltage allowing linear control of the load current This versatile capability permits you to simulate a wide variety of loads You can improve this circuit by add ing some components Figure 4 A gate drive stage isolates the control amplifier from Q s gate capacitance 100A REG INCLUDING ULATOR UNDER TEST OUTPUT CAPACITORS C
6. er transitions Meaningful dynamic testing requires a rectan gular pulse shape flat on the top and the bottom within 1 to 2 The circuits input band shaping filter removes the aforementioned high speed transition related errors but does not eliminate lengthy tailing in the pulse flats You should check the pulse generator for this issue with a INPUT FROM PULSE GENERATOR TRIGGER OUTPUT INSULATED SHELL BNC well compensated probe at the cir cuit input The oscilloscope should register the desired flat top and flat bottom waveform characteristics In making this measurement if high speed transition related events are bothersome you can move the probe to the bandlimiting 300 pF capacitor This practice is defensible because the waveform at this point determines A s input signal bandwidth Some pulse generator output stages produce a low level dc off set when their output is nominally at its OV state The active load cir cuit processes such dc potentials as legitimate signals resulting in a dc load baseline current shift The active load s input scale factor of 1V 100A means that a 10 mV zero state error produces 1A of dc base line current shift A simple way to check a pulse generator for this er ror is to place it in external trigger mode and read its output with a DVM digital voltmeter If offset is present you can account for it by COAXIAL METAL ENCLOSURE OUTPUT TO Le OSCILLOSCOPE S EXTERNAL TR
7. gger input This simple coaxial component typically comprises isolated ground and signal paths which often couple to a pulse transformer to provide a galvanically isolated trigger event Commercial examples include the Deerfield Laboratory www deerfieldlab com 185 and the Hewlett Packard www hp com 11356A Alternatively you can con struct a trigger isolator in a small BNC equipped enclosure www edn com between loop stability edge rate and pulse purity You can use A s loop compensation trimming capacitor to set the roll off for maximum bandwidth and accommodate the phase shift that Q s gate capacitance and A introduce The FET response adjustment partially compensates Q s inherent nonlinear gain characteristic improving the front and rear pulses corner fidelity see sidebar Trimming procedure with the online version of this article at www edn com 110922df CIRCUIT TESTING You initially test the circuit using a fixture equipped with massive low loss wideband bypassing Figure 6 It is important to do an exceptionally low inductance layout in the high current path Every attempt must be made DC POWER SUPPLY MINIMIZE INDUCTANCE 10 000 pF COMBINATION OF OS CON FILM AND CERAMIC DELIBERATELY CAPACITORS INTRODUCED 20 nH PARASITIC INDUCTANCE Mee INDUCTANCE FIGURE 5 s CIRCUIT Figure 13 You can deliberately introduce a parasitic 20 nH in ductance to test layout
8. gure 16 The regu 100A DIV lator s response to a 100A pulsed load TRACE B SSi iMi Midi Haii 1 00 SS Trace A is well AC controlled on both COUPLED edges Trace B 50A DIV Figure 17 You can use the circuit to create a 100 kHz 100A sine wave load Figure 18 The active load circuit sinks 100A p p in response to a gated random noise input 50A DIV 20 uSEC DIV 100 4 LEADING EDGE I OVERSHOOT i NO 90 l f OVER 80 SHOOT LOAD CURRENT 50 A 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 MINIMUM Q DRAIN VOLTAGE V 1 1 1 2 Figure 19 Active load characteristics feature small current accu racy and regulation errors The bandwidth mildly retards at low currents The compliance voltage is less than 1V at 100A with 4 leading edge overshoot and 1 1V with no overshoot www edn com ACTIVE LOAD CHARACTERISTICS Temperature drift Bandwidth 100 ppm C of reading 20 mA C 540 kHz at 100A with a rise time of 650 nsec 435 kHz at 10A with a rise time of 800 nsec tion are unavailable The event is too thrilling to document Overdoing the FET s response compensation causes peaking in the corners of the waveform Figure 10 Restoring the ac trims to nominal values causes a 650 nsec rise time equivalent to a 540 kHz band width on the leading edge Figure 11 Examining the trailing edge under the same conditions reveals a somewhat faster 500 nsec fall time F
9. igure 12 LAYOUT EFFECTS If parasitic inductance is present in the high current path your design can not remotely approach the previous responses You can deliberately place a tiny 20 nH parasitic inductance in Q s drain path Figure 13 which will cause an enormous waveshape degrada tion deriving from the inductance and the loop s subsequent response Figure 14a A monstrous error dominates the leading edge before recovery occurs at the middle of the pulse s top Additional aberration is evident in the falling edge s turn off The figure s horizontal scale is five times slower than the optimized response Figure 14b The lesson is clear High speed 100A excursions do not tolerate inductance REGULATOR TESTING After you address the compensa tion and layout issues you can test your power supply regulator Figure 15 The six phase 120A Linear Technology Corp www linear com LTC1675A buck regulator acts as a demonstration board The test circuit generates the 100A load pulse Trace A of Figure 16 The regulator main tains a well controlled response on both edges Trace B of Figure 16 The active load s true linear response and high bandwidth permit wide ranging load waveform characteris www edn com tics Although the step load pulse in Figure 16 is the commonly desired test you can generate any load profile A burst of 100A 100 kHz sine waves is an example Figure 17 The response is crisp
10. sensitivity Figure 14 A 20 nH inductance 1 5x 0 075 in flat copper braided wire com pletely distorts a the optimized response 20A DIV MEAG T EEmra EEEE D Note the five b times horizontal scale change be tween a and b a eee 2 uSEC DIV www edn com to minimize inductance in the 100A path You should get good results after you properly trim the circuit if you minimize inductance in the high current path Figure 7 The 100A amplitude high speed waveform is pure with barely discernible top front and bottom rear corner infi delities see sidebars Verifying current measurement and Instrumentation considerations To study the effects of ac trim on the waveform you must perform deliberate misadjustments An overdamped response is typical of excess A feedback capacitance Figure 8 The current pulse is well controlled but the edge rate is TC3829 BASED SIX PHASE _ 4 5V 120A POWER SUPPLY INPUT 7 TO 14V MINIMIZE FIGURE S s INDUCTANCE CIRCUIT Figure 15 Use low impedance connections to test a six phase 120A buck regulator 36 EDN SEPTEMBER 22 2011 slow Inadequate feedback capacitance from A decreases the transition time but promotes instability Figure 9 Further reducing the trim capacitance causes loop oscillation because the loop s phase shift causes a significant phase lag in the feedback Scope photos of uncontrolled 100A loop oscilla TRACE A Fi
11. t age value It compares that voltage to a reference voltage set with the dissipation limit adjust potentiometer If the input duty cycle exceeds this limit comparator IC turns off the FET gate drive through Q Thermal switch S pro vides further protection If Q s heat sink gets too hot S opens and disconnects the gate drive signal By diverting Q s bias voltage transistor Q and the zener diode prevent Q from turning on if the 15V supply is not present A 1 kQ resistor on A s positive input prevents amplifier damage should you lose the 15V power supply Trimming optimizes the dynamic response determines the loop s dc baseline idle current sets the dissipation limit and controls the gate drive s stage bias The dc trims are self explanatory The loop compensation and FET response ac trims at A are subtler Adjust them for the best compromise The pulse edge rates in the main article are not particularly fast but high fidelity response requires some diligence In particular the input pulse must be cleanly defined and devoid of parasitics which would distort the circuits output pulse shape A s 2 1 MHz input RC resistance capacitance net work filters the pulse generator s preshoot rise time and pulse transition aberrations which are well out of band These terms are not of concern Almost all general purpose pulse generators should perform well A potential offender is excessive tailing aft
12. te drive stage which is actively biased using A The voltage drop across the gate drive s input diodes would be high enough to fully turn on Q and Q To prevent this overdrive reduce the voltage across the lower diode with Q Amplifier A determines the gate drive stage bias by comparing Q s averaged collector current with a reference and control ling Q s conduction thus closing a loop That loop keeps the voltage drop VERIFYING CURRENT MEASUREMENT Theoretically Q s source and drain current are equal Realistically they can differ due to the ef TO FIGURE 6 s CAPACITOR BANK AND DC SUPPLY TO FIGURE 5 s CIRCUIT BOTTOM SIDE CURRET NOTE 1 FILM RESISTOR Figure A Use this arrangement for observing Q s top and bot tom dynamic currents 32 EDN SEPTEMBER 22 2011 fects of residual inductances and the 28 000 pF gate capacitance As indicated instantaneous current could be erroneous if these or other terms come into play You can verify that the source and the drain cur rents are equivalent Figure A Add a top side 1 mQ shunt and a gain of 10 differential amplifier to dupli cate the circuit s bottom side current sensing sec tion The results should eliminate concern over Q s dynamic current differences Figure B The two 100A pulse outputs are identical in amplitude and shape promoting confidence in the circuits operation TRACEA 50A DIV TRACE B 50A DIV if 2 SEC D
13. with no untoward dynamics despite the high speed and current You could form a load even from an 80 psec burst of 100A p p noise Figure 18 The load circuit has high accuracy compliance and regulation specifica tions Figure 19 and Table 1 EDN REFERENCES W Williams Jim Load Transient Response Testing for Voltage Regula tors Application Note 104 Linear Technology Corp October 2006 http bit ly p5q2AD gi Overload Adjust HP 274A Pulse Generator Operating and Service Manual Hewlett Packard figures 5 through 13 Ml Overload Relay Adjust HP 214A Pulse Generator Operating and Service Manual Hewlett Packard 1964 pg 5 al Overload Detection Overload Switch HP 214B Pulse Generator Operating and Service Manual Hewlett Packard March 1980 pg 8 AUTHOR S BIOGRAPHY Jim Williams was a staff sci entist at Linear Technology Corp where he specialized in analog circuit and in strumentation design He served in similar capacities at National Semiconductor Arthur D Little and the Instrumentation Labora tory at the Massachusetts Institute of Technology Cambridge MA He en joyed sports cars art collecting antique scientific instruments sculpture and re storing old Tektronix oscilloscopes A long time EDN contributor Williams died in June 2011 after a stroke
14. y REGULATOR OUTPUT VOLTAGE MONITOR IswitcHED AND DC LOAD MONITOR Figure 3 A feedback controlled load step tester allows continu ous FET conductivity control SEPTEMBER 22 2011 EDN 29 REGULATOR UNDER TEST INCLUDING OUTPUT CAPACITORS INPUT AVERAGE FET TEMPERATURE DISSIPATION LIMITER ae a TEMPERATURE SENSE NEGATIVE SHUTDOWN INPUT PULSE GATE DRIVE STAGE 0 001 VO BASELINE DC LOAD SET Figure 4 Adding a differential amplifier provides high resolution sensing across a 1 mQ shunt resistor A dissipation limiter shuts down the gate drive Added capacitors tailor the bandwidth and optimize the loop response 15V 15V O O POWER GATE DRIVE 15V DISSIPATION LIMITER A enue O 100k lt 2 2k 2N3904 TO LOAD POINT l OF SUPPLY 10 pF DISSIPATION UNDER TEST LIMIT 3 O s z 1 f e pF OPENS AT 70 C HEAT SINK Z BASELINE MPENSATION HIGH CURRENT CURRENT ee pal CRITICAL PATH Piel 1000 FET LT 1V CURRENT MINIMIZE e 4324 SINK INDUCTANCE 0 TO 1V 0 TO 100A FET RESPONSE 20 pF CONTROL COMPENSATION AMPLIFIER ia O 5V 4 SV lt SUPPLY UNDER TEST RETURN POINT 10k x10 CURRENT SENSE LT1004 150k een CURRENT 2 5V FEEDBACK pate 1V 100A lo ADJUST 10k 1k cee NOTES 5V REGULATORS LT1121 LT1175 S MOUNTED ON Q HEAT SINK S CANTHERM F20A07005ACFAOGE 1 FILM RESISITOR Q INFINEON IPB015N04LG ph 1N4148 1 uF
15. y including an electronic load switch control Figure 2 The input pulse switches the FET through a drive stage generating a transient load current from the regulator and its output capacitors The size composi tion and location of these capacitors have a profound effect on transient response Although the electronic con REGULATOR PUT SUPPLy A INPUT SUPPLY AT A GLANCE Use active loads to test your power supplies Using wide bandwidth circuitry allows fast transient response Trim the circuit to obtain the cleanest load step signals Minimize the inductance in the high current path Verify the measurements in a separate test setup trol facilitates high speed switching the architecture cannot emulate loads that are between the minimum and the maximum currents Additionally you are not controlling the FET s switch ing speed because doing so introduces EREGULATOR CURRENT VOLTAGE MONITOR MONITOR RewitcHeD LOAD LOAD E SWITCH IswitcHED A SWITCHEDLOAD Figure 1 This conceptual regulator load tester includes switched and dc loads and monitors voltage and current The resistor values set dc and switched load currents RewitcHED LOAD INPUT PULSE IgwitCHED MONITOR REGULA INCLUDING TOR UNDER TEST OUTPUT CAPACITORS VOLTAGE MONITOR NEGATIVE INPUT PULSE BASELINE DC LOAD SET Figure 2 A conceptual FET based load tester permits step load ing Switched curr
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