Spectrum 128 Service Manual
Contents
1. So L 5 7 sna 553800 Las 5 4 4 2 1 5 2 2 5 1 The row signal 5 is subsequently buffered by the and placed one of the five low order data bus lines For example if the CAPS SHIFT key 18 pressed row one output drives data bus DO high and so on The sequence ends with 1 0 address when column 8 is addressed this instance operation of the SPACE key drives DO high Clearly the keyboard scanning routines make the distinction between the CAPS SHIFT and SPACE key by knowing which address line 1S being driven If one of the following keys is pressed the corresponding switch contact on the lower membrane is closed Additionally the CAPS SHIFT switch contact on the upper membrane closes TRUE VIDEO EXTEND MODE CURSOR INV VIDEO EDIT CURSOR BREAK CAPS LOCK cursor DELETE CURSOR For example pressing TRUE VIDEO closes the switch contact at row 1 column 6 on the upper membrane CAPS SHIFT and row 5 column 1 on the lower membrane TRUE VIDEO Similarly pressing any of the following keys results in the corresponding switch contact on the lower membrane closing as well as the SYMBOL SHIFT switch on the upper membrane comma 2111 5500 semi colon quotes For example pressing full stop closes the switch contact a2. 24 IHE 2 1 tt eu f TEC CET L e 14 22 pols 5 sid 1 404 all 4 16 6 FAM Sinclair 5 Da 530 C45 7 i iiu 22 xl 7777 da gt soe 250 24 a ae R3 ET reset g 27 r 1 T fuer Ao 22 ee oy siad IE SEM Cabe TOFTE EEL L CL JUL 165 19 ES e Texas 745 4532 or 17513732 17 H i amp z dX ad m 1 1 n CI aso as ga moi 11 d EE M H n 5 n L MAU Me 35 38 go 4 5 i don ur 41 e a a i i3 L dia hr 2 d ESMMENNES LLL l Es d LE SHIT m L L I Am iiid ar up Me MERE T IEE 51421618 N PPM HT 25
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7. PRETS LIST AND MODIFICATION s 117 O dni LI 80275 E Al i 1411 11 008 An Ik if 5n 36 LV dI ON 3 ip M 2 T I LL 04 4 4 unm 1 11 6 JI H Abt Se ee eS ie ee SES 1 ur LEF AET Lew LEA HN tH n 154 E aS ko Sod X TH 2 TAS TRL 72 1 57 16 51 41 H it M i n Ii 1 ur 121 1 1 AF LE 4 L1 m 1 vM V M n M i 11 ERE 31114 nir vo mi ETE R it tn der 43 ma Al 4 141 411 Al Al 11 ai y 1 TI Mi 1 corte Es 1451 18141
8. 5 from the 280 to the PIC and a receive line CIS TXS from the PIC to the 780 The transmit signal originated by the 280 is output as bit AO from the Port A Data Store in the sound generator IC32 during a write to I O address BFFDy From 1032 the data is converted from logic to RS232 levels in 1033 and routed from there to the PIC A 4 3V zener diode on the keypad receive line limits the positive signal excursion space to 4 3V and the negative signal excursion mark to OV 52000 The transmit signal originated by the PIC follows reciprocal path is input to the 780 from the sound generator as bit 5 in the Port A Data Store during a read from I O address FFFDy NOTE The RS232C receiver IC34 recognises a mark as and a space as any level exceeding 3V 5 8 6 Accesses to the Port A Data Store are identical to those described under the heading RS232 MIDI Interface 55051 Reset Protocol The synchronising seguence which runs after power up or reconnection as seen at the 5232 connector is shown below LET TO PIC 0 0 The significant time delays are as follows a The initial 3 second delay which ensures that the PIC is up and running During this time the keypad is inoperative b 15 delay between the 280 setting TXD high MARKS and the PIC responding by settting TXS high PRESENT If the delay is exceeded the 780 assumes that some other device
9. OIA gt gt 12 INTRODUCTION 1 1 The Spectrum 128 is a derivative of the 48K Spectrum Plus offering 128K of RAM music quality sound greatly improved video quality and higher hardware reliability 1 Ihe firmware is capable of running in Spectrum 48K mode or alternatively in 128K mode which will support paged memory in the form of a RAM disk Extended BASIC to handle the sound facility is provded and a full screen editor is incorporated in the firmware does IS 222 242 Jed SRIAAA list of the principle features appears below a 128K dynamic RAM b 32K ROM c Numeric keypad d TV sound with composite video Elimination of dot crawl single crystal operation f RGB output 4 85232 serial port 1 Musical instrument digital interface MIDI j Software compatible with all previous Spectrums k Edge connector compatible with Spectrum ARCHITECTURE architecture of the Spectrum 128 shown in Figure 1 1 is typical of many microcomputer systems is that it comprises a single microprocessor chip in this instance a Z80A 1180 read only memory ROM a paged random access memory RAM and an input output section The latter handles the keyboard input tape and display functions using the logic gate array and the keypad input sound and RS 232 MIDI interfaces using the sound generator circuit 1032 Ihe analogue circuits
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13. Spectrum ROM ROM 1 Bit clear fetches from the 128K Spectrum ROM 0 85 Set to prevent further accesses to the bank register protection against SPECTRUM programs crashing if the bank register 1S written to in error 4 4 x see para 4 12 2 Clearly dependent on register bits B2 BO the 700 can access page 2 at address 8000 or 000 and the screen in page 5 at address 4000 CO00u screen in page 7 can only be accessed at address 000 On power up or after reset the bank register is cleared and loads page 0 at address 0000 selects the 128K Spectrum ROM at address 00004 and informs the ULA that screen accesses are from page 5 1 6 This mechanism only applies to the non contended RAM area alternative refresh method is adopted for the contended RAM 4 MEMORY ORGANISATION 4 1 The Spectrum 128 has 100 bytes of addressable memory a 32K byte ROM 105 and 128K bytes of dynamic 1606 1022 The latter is organised as eight 16K byte pages as indicated below 7 screen 2 ip contended video page 6 RAM 1656 13 5 screen 1 M 4 3 2 X uncontended page 1 RAM 195 22 0 4 2 Pages 0 3 a
14. Baia Ran 5 vL 4 7 1838 Pin 4 11 Emitter 4 1 Wert per Woe 1 4 gt TABLE 5 2 MAIN PCB COMPONENTS CIPOUIE Value Rating Manufacturer Notes Reference Tolerance Type CAPACITORS Unless otherwise stated all capacitors are axial types 01200 22nF 25V 10 Ceramic C9 C24 Not used 25 100uF 10V 10 80 2610 226 22nF 25V 10 Ceramic 221 LuF 50V 10 Electrolytic C28 22uF 10V 10 80 Electrolytic C29 31 22nF 25 10 Ceramic Qol 100 25V 10 Ceramic e 100nF 25V 10 Ceramic 522 Not used C34 22uF 10 10 80 208 229 10 25 10 Ceramic C36 C40 Not used C41 22nF 25V 10 Ceramic 42 Not used C43 25V 10 Ceramic 44 45 100uF 107 10 80 Electrolytic 46 48 Not used C49 560pF 254 10 Ceramic C50 22uF 10V 10 80 Electrolytic 51 54 Not used 0599002 2208 25 10 Ceramic 2025202 Not used C66 22nF 25V 10 Ceramic C61 100pF 25V 104 Ceramic C 09 013 Not used C14 4 7uF 5V MIN Electrolytic 75 100nF 25V 10 Ceramic Not used C80 22uF 10V 10 80 Electrolytic 81 99 Not used C100 254 10 Ceramic C101 22nF 25V 10 Ceramic C102 103 Not used C104 25V 10 Ceramic C105 180pF 25V 10 Ceramic C106 C110 22nF 25V 10 Ceramic 16V 10 80 Electrolytic Cli 11 25V 10 Ceramic 2115 330 25V
15. 2 Ceramic SRIAAA Rating Manufacturer Notes Reference Tolerance Type CAPACITORS continued C116 10 259 10 ANE Not used 118 119 25V 10 Ceramic C120 100pF 25V 10 Ceramic 254 10 Ceramic 2122 nF 25V 10 Ceramic 2123 luF 100 10 80 124 20pF 25V 2 Ceramic 3 C125 100 25V 10 Ceramic C126 22pF 25 10 Ceramic 2571 luF 10V 10 80 Electrolytic C128 4TnF 25V 10 Ceramic C129 100pF 25V 10 Ceramic C130 Note 6 25V 2 Ceramic 6 COILS Value Rating Manufacturer Notes Reference Tolerance Type COIL SPECTRUM N Devon TFR 1 2 Devon Toroidal I 7 2 winding 13 JKE 1 291 5 18857 14 2 8 15 Not used I 5 7 1004 Taiyo LAL04 0 101K CONNECTORS Reference Description Manufacturer Part No EAR 3 5mm jack socket TUDA PWR 2 co axial socket 5 ribbon connector BURNDY 9503 110120 ribbon connector BURNDY TE 8 55103 RGB 8 DIN socket 9 way D Type connector KEYPAD 6 way telephone jack BICC BT Type 603A 85232 socket 581 5 4 CRYSTALS Cire Cut Reference X1 DIODES Gob wel swe Reference D1 D8 09 12 013 014 015 016 017 018 019 020 027 028 29 030 034 Preguenecy 17 734475 MHz Device IN4148 No
16. ULA RAM 31 ROW COLUMN PAGE 0 1 0 5 The RGB colour bright up and composite sync signals Figure 1 6 are coupled to the RGB output socket via 68 ohm resistors and are suitable for direct input to a wide range of colour monitors same signals are also applied to the encoder IC36 to produce a composite video output at pin 6 The video comprises the following components a Line frame sync with colour burst derived from the composite sync input CS and a burst oscillator sustained by tank circuit L3 The position of the burst relative to the line sync pulse is determined by a threshold level set up on the RAMP input of IC36 by 8113 18 b Colour chrominance is derived by modulating the chroma sub carriers with the colour difference signals decoded from the RGB and bright up signals The latter are first combined using a diode matrix D20 D25 to produce six colour inputs for IC36 two for each colour designated O and l1 Without bright up the presence of any digital colour input at logic 1 drives the l input only producing a pixel display with the colour intensity set for normal viewing With bright up activated the Q and 1 inputs are driven increasing the intensity so as to highlight the pixel display Juda 5 4 924 2 SRIAAA c Luminance grey scale derived by mixing the RGB inputs in a fixed proportion The signal is used to produce the colour diffe
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18. 15 connected and abandons the reset sequence 1 20 SRIAAA The 0 65 delay between the PIC returning to the idle state CORRECT and the 780 setting high 60 the delay is exceeded the keypad assumes that the 280 has been reset and resets itself i e returns to the start of the sequence d The 1 ms delay between the 280 setting TXD high SET and the PIC responding by putting TXS low CORRECT If the delay is exceeded the 780 assumes that some other device is connected and abandons the reset sequence 0 2 Bit Transfer Protocol The protocol for transferring a single bit from the PIC to the 780 as seen at the 5232 connector is shown below MODESTO easy Txp Space gt lt so FAAZ CTS CADY STALTED AT cee 5 8 10 significant levels and time delays are follows a At the start of the transfer the 280 polls TXS which should be idling low If not the 780 assumes that some other device is connected and abandons the transfer Having detected that TXS is low the 180 sets TXD low ATTENTION and waits for the PIC to respond with READY If READY is not received within 15 ms the 280 assumes that the keypad has been disconnected and abandons the transfer c After setting READY high the PIC polls RXS waiting for START If not received within 0 2 ms the PIC assumes that the 280 has been reset and resets itself d On re
19. 6 51 4 8 4 SRIAAA All memory accesses are controlled by the programmable logic array PAL 1029 It does this by decoding the two m s 780 address bits 215 214 with bits B2 BO from the bank register to produce three pairs of supplementary address lines They are UA15 14 specifying the page number in the uncontended RAM space 0 15 14 specifying the page number in the contended RAM space ULAI5 14 controlling bus arbitration and 280 access to the ROM and contended RAM space Ihe decodes are summarised below and described in the following paragraphs 280 operation 07415 2 14 B2 Bl BO ULA15 01 14 15 15 M access X X X 0 0 4000 7 0 1 0 1 0 1 X X 8000 8FFFY 1 X X X 1 O X X 1 0 page 0 access 11000 1 X X X O O page 1 access 11 00 1 1 0 1 page 2 access 1 1 Lu 1 1 0 3 access 11011 1 1 1 page 4 access 1 1 1 0 0 0 1 0 0 page 5 access 11 10 1 0 1 0 1 X X page 6 access 1 1 1 1 G 0 1 1 0 7 access 1 1 1 1 1 0 1 1 1 2415 2414 0 These bits select the first 16K of 180 address space beginning at 0000 and result in the PAL generating ULAI5 14 0 These are decoded by the 101 to produce a signal ROMCS enabling the 105 ALE3 AQ on the 780 address bus provide the instruction address bank register bit 4 determines whether the upper or lower 16 of ROM is acce
20. 8K2 1K5 68R 10KO 4708 1K5 820R 3K3 470R 1KO 820R 3K9 6K8 4K7 15K0 34 Rating Manufacturer Notes Tolerance Type 2 0 5W or 10 290 2 5 6 RESISTORS Continued Circuit Value Reference R112 68KO R113 36KO R114 IKO R115 10KO R116 Not used 8117 8120 1 0 121 R122 1 8123 1808 8124 125 4708 126 3308 8127 1 5 128 8 2 8129 1 0 8130 131 1 5 8132 39K0 j R133 568 8134 756 8135 8 2 8136 RIS 478 8138 4708 TRANSISTORS Circuit Device Reference 1 2 Not used ZTX313 TR4 ZTX650 TR5 ZTX213 TRG 2 313 IR Not used TR8 9 Not used TRIO BC308B TRII TR13 BC239B 21 313 SRLAAA Rating Manufacturer Tolerance Type 2 0 5W Alternative j KSC839 8C213P BC5588 8C184P B8C5498 5 7 Notes Hates 2 TABLE 5 3 KEYPAD PCB COMPONENTS Value Descrip Reference CAPACITORS axial types Rating Tolerance 10V 10 80 25V 10 Cl luF 2 2 ATpF COILS 11 68 ul 10 CONNECTORS 41 2 5 way ribbon connector J3 5 Way connector DIODES 01 BZY88C DZ BZY88C 4 3 INTEGRATED CIRCUITS Id PIC1652 RESISTORS 1 4W 5 RI 2 R3 1KO R4 100K 1 581 Manufacturer Notes Type Electrolytic Ceramic 34815 680K BURNDY TE 251 3
21. d c 2 0V At 1nput less than 47V the regulator may not operate correctly Voltage regulator side of C34 TOV 02048 0 49 mo output and 1 15 pin 8 discernable ripple continued 4 3 1 FUNCTION On board power Supply outputs Clock pulses Crystal 280 Colour encoder CIRCUIT pin lm 019 Kor ut 1052 Id pins 46 47 VOLTAGE WAVEFORM Ti VE GOV Cert 215 wo Check the oscillograms at points A 17 73447 MHz with no jitter check the oscillogram at point C 3 54689 MHz with jitter check the oscillogram at point D 8 8 MHz with no jitter 2 4 58 1 If the basic tests prove satisfactory check the 45V and ground distribution to the ROM 780 ULA and the RAM following Also check the a RD WR MREQ DO D7 and 0 15 lines from the 280 They should all be active immediately following a reset b The RAS CAS lines to the uncontended RAM area 1015 1022 The lines should be active immediately following a rest c The RAS CAS lines to the contended RAM area IC6 to 1013 Compare with the oscillograms at points E and The RESET pushbutton should be operated to obtain a clear trace d The ROM 105 is enabled by an active low signal at pin 4 e The bank register 10312 is loaded with the correct values Immediately after reset pins 2 5 7 10 1
22. latter short circuits caused by hairline solder splatter can be of several ohms resistance and can cause some very misleading fault symptoms Provided first principles are adhered to and a common sense approach is adopted it will be found after a short space of time that fixing a faulty Spectrum is very much a routine operation Power Supply Unit The unstablised external power supply unit is a source of some problems The design is such that at minimum input voltage 215V a C and 1 4 output the voltage trough should not be less than 7 0 at maximum input voltage 265 a c and 600mA output the voltage peak should be less than 13V Initialisation switch on the computer should automatically initialise and produce a clear screen with the statement 1985 Sinclair Research Ltd displayed in the lower left section of the screen This indicates that most of the system is working If the SPECTRUM 128 does not initialise carry out the following basic checks Basic Checks It is difficult to be specific in a fault finding guide because of the large variety of fault conditions which can occur but the following procedure starting with a table of checks set out in order of priority will however isolate the major fault area oscil lograms reproduced on pages 4 6 and 4 7 measured at points referenced on the circuit diagrams FUNCTION CLRUULL REE VOLTAGE WAVEFORM Voltage regulator tve side of C50
23. not shown generate the 17 7 MHz master clock and process the RGB colour monitor and sound signals resultant outputs are suitable for use with colour RGB or black and white monitors and domestic UHF television receivers modulated sound carrier is output with the composite video The computer is built on a single printed circuit board which also includes a regulated power supply fed from an external power pack The keyboard matrix is part of the upper case assembly and is connected to the board via two ribbon cables and 82 digital keypad is also provided connected via a flexible cable can be used as a games controller or calculator pad and has special function keys for use with the full screen editor in built peripheral interface controller PIC performs the keypad scanning routines and delivers an output to the 780 on demand 480A CPU The 2003 is 8 bit single chip central processing unit CPU It is clocked at 3 5 MHz from a divide of an external source controlled by the logic gate array ULA and has a standard three bus input output arrangement These buses are the data Bus Address Bus and Control Bus respectively s 222 SIS 3 4 250 350 20 3 9 Dad SRIAAA Data Bus 07 00 constitutes an 8 bit bi directional data bus with active high tri state input outputs It is used for data exchanges with the memory sound chip and the ULA Address Bus 15 0 constit
24. the 280 asserts MREQ and loads the address bus 413 40 MREQ enables the ROM outputs onto the data bus 07 00 ROMCS decoded from ZA14 15 see para 4 7 selects the chip An external ROM chip select input supplied via the expansion port on pin 25A selectively disables the on board ROM by pulling the select input high By virtue of R33 placed on the ULA side of the ROM the ULA ROMCS output is effectively inhibited Interface 1 uses this mechanism allowing the CPU to read the extension ROM in the interface for microdrive and RS232 applications 1 8 4 12 4 Uncontended 16015 22 The uncontended RAM comprises eight 64K dynamic RAM chips organised as a 64K byte memory with a 256 x 256 row column matrix When 15 is high see para 4 11 separate 8 bit row column addresses are supplied by 1027 as 7 These are derived from the 280 address bus 1 with and 0315 from 1029 The low order address bits A6 AO with provide the row address and are selected at the beginning of the memory access cycle when initially the RAS MREQ output from the 780 is low Later as the row address 15 latched 1027 asserts CAS selecting the high order address bits A13 A7 with 15 4 12 5 Row column address selection and RAS CAS timing for the RAM is decoded in IC27 in conjunction with IC28 and the associated discrete components theoretical timing diagram illustrating the RAS CAS waveforms is given in Figure 1 2 A
25. 068 1159 1160 1161 1017 1162 1163 1164 1023 1165 1022 1166 1167 1198 1169 1170 1171 1031 1372 1173 1174 11 1176 1177 1179 1179 1180 1181 1182 1183 1220 X 1203 1221 1222 1100 1223 1224 1285 1226 FT or L ARK Er ER C32 23 5 1256 fa Qu 52 comm dB 0 1 E P ATE str 1 HL Keyboard 5 connectors 6 TRZ ial 18 1 315 NIS 23 pn EAR mic All ATO AIT 413 AIS 47797 Te address but RI ATO some models 22uf version only 5 gt XI 260 felted or 270 A ia 58 version x edge pins TA i A UV OEC 2 3 2 208 24 m i TN rof R46 ix RAZ 1 635 Ed gg 184457 gt uu T T 3 on ped 218 Tes 1151 62 iced eR PCT eat pet E 30 jav 47k Pg E 220 4 GRE J 2 ULA cf 12
26. 1777 e an 15 ser n al 1 a filt ia EFI 1 12 un A ___ 1 158 ri MI ug uL c5 Jog a _ wr EY M n 3 r 1018 4 HIM 7 1 1881 if 2 4 115 011818 Wia 1 ABSOLUTE He ALL UNLESS SIAMO ARE E Fw dE oc qug T THES CIMPONERTS HAYE An E asi E __ i OR CHANGED IN VALUE ON ISSUE B I uw _ 01 WAS PIO KOW HJ C43 WAS 5 7 AREG Thad ALTERMATIYE SUPP 3 e m 2 n IMi ba T LE TH4TTH 43 m ES EEE i V E EET at gt 25 i Til iT 2m xu In m L mj mU row n la eee ae Fii nus 035 ri 01 Lx c 2221 12 71 VA Ru GA Ee e x ree ili T 6
27. 2 and 15 should be low Check the outputs on the RGB connector g Check the picture on a domestic television and listen for keyclicks each time the ENTER key is pressed following 4 4 Also check the 2 9 1 LUMO output on 1036 pin 7 compare with the oscillogram at AC pn phe oco UTC 17 Sound carrier on IC38 pin 4 compare with the oscillogram at point on the circuit The frequency should be within 2 KHz of 6 0 MHz for U K operation or 2 9 MHz for European operation Adjust as per the Setting Up Instructions if the tolerance is exceeded 111 Drive into the modulator compare with the oscillogram at point J on the circuit Note the d c level at the bottom of the waveform typically 1065 mV Symptomatic Faults As with any complex digital equipment the possible permutations vast thus the following table is not intended to be an exhaustive list of the faults that might occur on the Spectrum It is intended as a guide only to possible courses of action to follow when faults show up in particular areas of the circuit These areas are listed in the table with sub headings in no particular order of priority It is envisaged that the 2 test tape has been loaded or an attempt has been made to load the tape in order to check for a faulty condition AREA 5 TBO SR1AAA Authors Note Table details to follow when production and in ser
28. E UE 2 A 4 22 A p I ae BE D lee LLL coe tt ENTEJSOSS 4eVA e ERFT ZX SPECTRUM ISSUE 2 1 4 OPTIMAL 32K RAM FOR SERVICE MANUALS CONTACT MAURITRON TECHNICAL SERVICES www mauritron co uk TEL 01844 351694 FAX 01844 352554 delle m CIRCUIT DIAGRAM ESK 12740 ISSUE
29. Molex 4494 05 04 Zener Zener General Instrument II 3 WO Jo WW ho Lg 36 DESCRIPTION 280A U7B0 MULTIPLEXER 16 PIN PCF 1306P 8488401 741504 ROM 23 PIN 256 1154 ULA 7 001 4164 HALIOHSCN 1415174 3 8912 1458 MC1488P SN 751888 1489 5 1489 55 51894 1 2000 1376 74504 ZIX 31 39 164 2398 213 3086 5588 650 BA157 EHI ZENER 500MW Dis 134148 COIL 5 PIN NEOSYD FORMER CHOKE BIFILAR WOUND COIL 1 COLL 100 uH CRYSTAL 17 73447 2 POCKET ROM 28 YIN SOCKET EAR MIC 3 5MM SOCKET POWER 3 LEG SOCKET U L 48 PIN SOCKET 3 WAY PIN 6 VAY PIN CONNECTOR S WAY CONNECTOR b VAY p LES oe ES Gee MEM 274 MISCELLANEOUS 36 ae 9g 40 41 MODULATOR LOVER CASE MOULDING KEYBOARD AND TOP CASE SUB ASSY RESET SWITCH SUB ASSY FOOT RUBBER REACTION PLATE PLASTIC 42 43 44 45 46 41 48 49 50 POWER SUPPLY 1 85AMP UK 1850 DATA TRANSFER CABLE 3 5MM INTO TWO 128 SUPER TEST CASSETTE 128 NEVER ENDING STORY CASSETTE CORD SERVICE MANUAL INTRODUCTION BOOK CARTON PLAIN SA LABEL POLY PACK SET 6 0 PART NO 1151 1152 X 1153 A 1016 1155 1054 1156 1157 1158 1067 1
30. and RD WR active low 1 0 read or write cycle and 7 1 and 2 15 low address 7FFOy On selecting the 48K Spectrum mode the 280 writes a 1 into bit 5 of the register thus preventing any further access This action preserves the 780 address space preventing erroneous calls to address 7 crashing the SPECTRUM program bit can only be cleared by uSing the RESET pushbutton or by interrupting the power supply input INPUT QUTPUT The input output functions are controlled by the 280 in conjunction with the and the sound generator circuit 1032 Like its counterpart in the 48K Spectrum the ULA handles the tape recorder read write functions and generates an interrupt during which it scans the main keyboard It also accesses the contended RAM area while generating the drive waveforms for the TV display and produces a simple tone output while obeying the BEEP instruction The sound generator produces high quality music sound by mixing the outputs from up to three programmable tone generators and a noise generator It also handles the RS232 MIDI interface and reads the keypad status Each of these functions and the supporting circuits is described below TV Picture Generation and Sound Output The video compilation section of the ULA operates in conjunction with the memory mapped picture display area in the contended RAM together with the colour encoder 1030 and UHF modulator This combination produces a high re
31. asis that the ULA must access screen pages 5 and 7 at set intervals in order to build up the video for the TV display If the is about to access the RAM and it detects either or A15 1 6 the CPU is also about to access the RAM the inhibits the CPU clock temporarily halting the CPU memory transaction until its own transaction is completed 188 SRIAAA MAA AQ TAS 1027 34 pe ce ee 00 e VAD rca FIGURE 1 2 UNCONTENDED RAM RAS CAS TIMING READ CYCLE SHOWN 1 10 SRIAAA 4 12 10 25412411 4512 12 orl 252 909 5 1 Resistors Rl to 88 in series with the data bus lines perform Similar function to the address port resistors described above They ensure that the ULA does not CPU write data while the ULA is accessing the contended RAM Refresh for the contended RAM is accomplished during normal read cycles i e most rows are refreshed each time the accesses screen pages during picture compilation the remaining rows are refreshed as a result of other read cycles also known to occur at regular intervals within the refresh period Bank Register IC31 The bank register is at address 7FFDy in the 780 address space The register is positive edge triggered and latches 05 00 off the data bus on the negative trailing edge of the BANK output from the PAL IC29 BANK is decoded set high from 1080
32. ceiving START the PIC leaves TXS high if it wants to send zero data bit or puts it low to send 1 STARTED Having received the data bit the 280 sets TXD low STOP the PIC responds with TXS high if not already so STOPPED SR1AAA 0 2 02 0 2 SR1AAA f Having responded with STOP the PIC waits for the 280 to set TXD high STAND EASY the PIC responds by setting TXS ready to transfer the next data bit the 780 does not respond with STAND EASY within 1 3 ms the PIC assumes that the 180 has been reset and resets itself POWER SUPPLIES on board power supply unit receives a unregulated supply from the external Sinclair ZX power pack and derives the following internal supply rails a regulated 5V for the IC logic circuits the and the Sound UHF modulators 5V for the expansion port for the RS232 driver 1033 and the keypad d 12V for the RS232 driver 1033 unregulated 5V to 12 The external power pack incorporates a mains transformer full wave rectifier and capacitive smoothing A thermal fuse is fitted at the transformer input The on board power supply unit Figure 1 5 incorporates a 7805 regulator deriving the 5V power rail and an input supply for the inverter stage TR4 TR5 latter raises the level of the 49V unregulated supply above 1 V resultant square wave at the junction f collector and the inverter coil is subsequen
33. dance with instruction codes loaded by the 280 into 14 internal byte wide registers See below BIT REGISTER 87 86 85 84 82 1 80 Channel Tone Period 8 BIT Fine Tune A Fine Tune 84 Channel C Tone Period BIT Fine fune R5 4 BIT Coarse Tune 86 Noise Period 5 BIT Period Control R2 Channel Tone PerTod R7 Enable TN 0015 Noise Tone TOA RIO Channel Amplitude Bee Rii Channel B Amplitude 113112111110 8 Channel Amplitude NEM 13112 1 10 813 Envelope Period 3 Bil Fine Tune 810 3 811 RIS Envelope Shape Cycle CONT ATT ALT HOLL R16 1 0 Port A Data Store 8 BIT PARALLEL 1 0 on Port A 1 1 0 Port Data Store BIT PARALLEL 1 0 on Port RS232 MIDI interface see below Ihe 280 specifies a register by loading the data bus while writing to address FFFDu in the I O space DA3 DAO supply the octal address between 0 and 15 DA DA4 should be all zero In the address mode 0 7 0 4 with IC32 pin 17 strapped high externally are decoded in 1032 to provide a chip select signal instruction code is then written to the register by writing to address BFFDg BDIR decoded in 026 27 from PSG and RDL define the type of write operation for the sound gene
34. he case Before final assembly reconnect the keyboard ribbon cables they should lie in an S shape and ensure that the legs and leg Springs are in position 22 SECTION 3 SETTING UP AND SYSTEM TEST Sub Section LIST OF CONTENTS Page No Setting Up Instructions Sound Carrier Frequency 2 system Test E SETTING UP INSTRUCTIONS TBD SYSTEM TEST TBD SRIAAA SECTION 4 FAULT FINDING AND REPAIR Sub Section LIST OF CONTENTS Page No 1 Introduction 4 1 Test Equipment 4 1 2 Fault Diagnosis 4 2 Techniques 4 2 Power Supply Unit 4 3 Initialisation 4 3 Symptomatic Faults 4 5 3 Repair 4 6 Fig ILLUSTRATIONS 4 1 Test Oscillograms 4 7 8 INTRODUCTION Test Equipment Section 4 is intended as a guide to fault diagnosis and repair of the SPECTRUM 128 it is assumed that users have a reasonable knowledge of electronic servicing theory and standard fault finding techniques and have access to the test equipment and tools required to carry out the task The table below contains a list of the minimum recommended test equipment and materials 231 SR1AAA Zl SRIAAA EQUIPMENT SPECIFICATION MANUFACTURER Storage Oscilloscope Rise Time 0 02 us cm with 10 probe Variable power Supply unit 2550 SUV Mono cassette recorder With RECORD and PLAYBACK facilities Mains extension lead Safebloc type Multimeter General pupose Colour Television and Open Market Monitor AX Printer Sinclair Tes
35. ions are populated by switch contacts The row outputs and column inputs are shown connected in both cases to separate ribbon cables KBl and KB2 one to the ULA and the other to the high order address lines A15 A8 Pull up resistors R65 through R69 ensure that when the address bus is in the high 4 state or none of the switch contacts is closed row outputs 1 4 remain high When the keyboard scanning routines are entered the CPU performs successive 1 0 read cycles setting the IORQ and RD lines to the ULA low At the same time the I O port addresses placed on the upper half of the address bus are modified with each cycle such that each of the address lines A15 through A8 is set low in turn the other lines remaining high The sequence starts with 1 0 port address FE driving address line A8 low The keyboard matrix also sees this potential on column 6 applied via D6 and the ribbon cable KB2 Thus when any of the switches on the intersection with the column is pressed the corresponding row output supplying the via the second ribbon cable KBl is pulled low 103 DOYE MSH Q 03427 lt 914 71 5 335 335 SNWA TOO sng viva SMOU 7 17 d 6v 01V 2 q civ 508 553800 Los d QN31X3 Baro 3 my 914 SNWN109
36. marised as follows R D6 0 R7 06 7 5 4 2 AO SORT CST TEST REGISTER R16 RS232 785232 0 P O P see para 5 8 4 1 18 SRIAAA It is evident from the Signal directions that the Spectrum 128 adopts the rote of a data communications equipment DCE However DIR and CTS do not perform a handshake but are the same Signal transmitted in opposite directions The transmission format is asynchronous full duplex with 11 bit data frames comprising 1 start bit eight data bits and two stop bits Two stop bits are always sent but the interface can receive satisfactorily with one 5 8 Keypad Scanning 920 1 The keypad Figure 1 7 comprises a 5 x 4 switch matrix and peripheral interface controller PIC with on chip program and Scratchpad memories The PIC operates from a 45V rail derived by a simple stabiliser from the 12V Spectrum supply and is clocked from an external LC network The nominal clock frequency is 2 996 MHz but may vary between 1 278 MHz and 3 835 MHz dependent on component tolerances The master clear input MCLR is active for a period after power up or if the 12V supply is temporarily disconnected 5 044 A two part protocol first synchronises the PIC with the 780 after power up or if the flex cable connection is temporarily broken and then supports the transfer of keystroke data Assuming synchronisation has been achieved see below the keypad scans the ke
37. n this section the ULA is able to inhibit this input bringing the CPU to a temporary halt This mechanism gives the ULA absolute priority allowing it to access the contended RAM without interference from the CPU see RAM description Switching transistor ensures that the clock amplitude 15 15V rather than some arbitrary TIL level This is essential if the CPU is to operate effectively while executing fast machine code programs of the space invader type Dynamic Memory Refresh The CPU incorporates built in dynamic RAM refresh circuitry As part of the instruction OP code fetch cycle the CPU performs a memory request after first placing the refresh address on the lower eight bits of the address bus At the end of the cycle the address is incremented so that over 255 fetch cycles each row of the dynamic RAM is refreshed 1 4 280 address space 15 allocated according to the two 5 bits of the address bus 2 14 15 and the contents of the bank register 1031 which is at address 7FFDy in the 780 1 0 space The significance of the register bits 15 summarised below Bits Function B2 BO Selects the page occupying the top 16K of the 700 address space Any RAM page can occupy the space B3 Instructs the ULA to access the display mapped in page 5 7 Bit set screen in page 7 Bit clear screen in page 5 4 Determines whether instruction fetches are from ROM 0 or ROM 1 Bit set fetches from the 48K
38. ny of the keys remove the membrane tail clamps followed by ten screws securing the keyboard reaction plate Lift the plate clear followed by the membrane and bubble mat below Individual keys can be removed for cleaning by pressing the key and gently prising the retaining sleeve off the underside of the key using a small screwdriver inserted under the rim ASSEMBLY Assembly is generally carried out using the reverse procedure to that of disassembly Do not overtighten the self tapping fixing screws 72 222 2 4 253 SRLAAA When replacing the keyboard components support the upper case half face down so that the keys are clear of the work surface Position the bubble mat membrane and reaction plate so that the hole at either end engages with the locating peg Secure the fixing screws starting with the centre row Tighten fully and back off a 1 4 When clamping the membrane tails ensure that there is good electrical contact between the middle upper and lower tracks This 15 achieved by correctly positioning the packing pieces extensions of the bubble mat and ensuring that the ends of the middle tracks protude 1mm beyond the clamps On new membranes to prevent the possibility of short circuits bond the upper and Tower tracks together close to the edge connector end using double Sided tape When replacing the pcb ensure that the reset pushbutton is correctly located in the cut out provided in the end of t
39. oinclair Spectrum 128 Service SERVICING MANUAL FOR SPECTRUM 128 LIST OF CONTENTS SECTION 1 INTRODUCTION SECTION 2 SYSTEM DESCRIPTION SECTION 3 SETTING UP AND SYSTEM TEST SECTION 4 FAULT FINDING AND REPAIR SECTION 5 PARTS LISTS LIST OF ILLUSTRATIONS Fig No Spectrum 128 Block Diagram Uncontended RAM RAS CAS Timing Keyboard Upper Membrane Keyboard Lower Membrane Spectrum 128 Logic Circuit System 128 Analogue Circuit Keypad Circuit Test Oscillograms Spectrum 128 PCB Component Layout Keypad PCB Component Layout BS LIBE FL NO 1 Os Prepared by BRAVEMAY LTD for SINCLAIR RESEARCH LTD 21 aad SERVICE MANUAL 128 1223 1 SYSTEM DESCRIPTION Sub Section LIST OF CONTENTS Page No 1 Introduction 2 Architecture 153 5 280 CPU Les 4 Memory Organisation 1265 Read Write Operations and Bus Arbitration 1 8 5 TV Picture Generation and Sound Output 1 11 Keyboard Scanning Tape Interface 15 15 Programmable Sound Generator 154 RS232C MIDI Interface 1 18 Keypad Scanning 517 6 Power Supplies 1 22 Fig ILLUSTRATIONS Spectrum 128 Block Diagram Uncontended RAM RAS CAS Timing Keyboard Upper Membrane Keyboard Lower Membrane Spectrum 128 Logic Circuit Spectrum 128 Analogue Circuit Keypad Circuit IS m LS LS pL 4 W ES
40. rator as follows PSG RO BDIR I O ADDRESS OPERATION 0 X 0 0 1 1 1 1 1 WRITE ADDRESS 1 0 1 1 0 BFFDy WRITE DATA 1 i 0 0 1 READ DATA RS232C MIDI interface see below 5 6 3 PSG is decoded in IC29 from IORQ with RD or WR I O read write cycle and ZAL 0 and ZA 15 1 address with 14 high address BFFDy with 14 low 5 7 RS232C MIDI INTERFACE The RS232C MIDI interface is implemented using the Port Data Store in the sound generator chip IC32 The data store is a special register at octal address 16 which accesses 8 bit bi directional port 7 port occupies the same I O space as the sound generator registers and is accessed in much the same way The addition of a read cycle at 1 0 address FFFDy allows the 280 to LIUIUS The port direction is determined by control bit written to register R7 on bus line Do When 06 is low the port is configured an input and when high as output In this application A3 A0 are only used as outputs and A7 A4 as inputs 2 supply an RS232C driver 1033 which converts the TTL outputs to RS232C levels 12V A2 and A3 drive the CTS and RXD interface lines respectively A4 are supplied from an RS232C receiver IC34 which converts the RS232C inputs to TIL levels and 7 are driven by the DTR and TXD interface lines respectively The data register contents are sum
41. re uncontended and are accessed solely by the 180 Pages 4 7 are contended in that the 280 and both require access to pages 5 and 7 in order to generate the memory mapped displays The address of any page of RAM depends on where it appears in the address space of the 280 which 15 structured as follows 0 7 do page 5 on Screen 1 RN ol 00004 12 SRLAAA TABLE 5 1 CASE ASSEMBLY DESCRIPTION MANUFACTURE Base Assembly Final Assembly Table 5 2 Heatsink Retractable Legs 2 off Leg Springs 2 off Bottom Case Moulding Fixings 1 4 in self tap screw 3 off PCB Fibre washer 4 5 16 in self tap screw 2 off heatsink M3 10mm pan hd screw 1 off plain washer 1 off voltage M3 crinkle washer 1 off regulator M3 hex nut 3 1 Keyboard Assembly I Keyboard Reaction Plate Spectrum Membrane Bubble Mat Upper Case Moulding Key Set Tail Clamps 2 off Fixi ngs Double sided adhesive tape 12mm wide Tesafix 959 tails 1 4 in self tap screw 4 off tail clamps 5 16 in self tap screw 10 off reaction plate General Assembly Fixings 5 16 in self tap screw 6 off base 1 2 in self tap screw 2 off keyboard SRI SECTION 5 PARTS LIST Sub Section LIST OF CONTENTS Page No 1 Introduction S 2 Notes
42. read operation is shown when the WRL line from the 280 is high 25220 Contended 16 13 The organisation of the contended and uncontended RAM described above is identical However because ULA15 is low during accesses to the contended area 16027 only sources 7 bit row column address DMA6 DMA7 The m s address bit is sourced by the 2 1 data selector IC30 the start of the memory access cycle Id asserts DRAS and selects the row address as 13 7 off the 280 address bus with VA14 via the selector Later as the row address is latched Id sets DRAS and selects the column address as with 15 4 12 7 RAS CAS timing for the contended RAM area is decoded by the ICI from MREQ and 15 OCAS 15 asserted a short time after DRAS returns high and latches the column address 15 prevents IC27 generating an identical signal for the uncontended RAM The DRAMWE signal also generated by the is a decode of the RD WR waveforms and selects a RAM read or RAM write cycle 4 12 8 It will be apparent from the circuit diagram that the can access the contended RAM by generating a set of addresses independent of those generated by the CPU The address port for the RAM is therefore dualled by the insertion of small value series resistors on the address lines between IC27 and the RAM This ensures that where there is likely to be conflict between the ULA and CPU the ULA address has priority Priority is assigned on the b
43. rence signals in b and in its own right to drive the black and white monitor luminance is bought out at 1036 pin 7 and is applied to the RGB output socket via a complimentary transistor pair TR13 14 The luminance 15 returned to IC36 mixed with the FM modulated sound carrier from 1038 The sound modulator operates at 6 MHz in the UK 5 5 MHz in most other European countries and is tuned by L4 The modulating signal is derived either by the ULA sourced via R112 C123 or the sound generator circuit IC32 513270127 The composite video signal at 1036 pin 6 is finally applied to encapsulated UHF modulator operating on European standard channel 36 The device is current driven via TR10 11 12 to give improved linearity thus reducing the effect of sound on vision and vice versa The effect is further reduced by outputting the sound carrier 20dB down with respect to the picture carrier Keyboard Scanning Every 20ms 1 6 once per maskable interrupt the CPU systematically scans the keyboard recording which keys if any have been depressed The scanning method is described below with the aid of Figures 1 3 and 1 4 As the figures ctearly illustrate the main keyboard consists of an upper and lower membrane The upper membrane 15 organised as an 8 x 5 matrix the intersection of each row and column bridged by a normally open switch contact The lower membrane 15 organised in a Similar manner except that only 16 of the intersect
44. solution 24 line x 32 character eight colour display suitable for use with RGB colour or black and white monitors or a domestic TV receiver The sound output from the ULA or the programmable sound generator is FM modulated and added to the composite video signal for playback through the TV loudspeaker If a monitor is used the sound is available through the MIC socket 22 5 3 4 From the 17 73 MHz external clock X1 IC37 the ULA derives line and field timing for the composite sync signal on pin 23 and a pixel clock for timing accesses to the RAM The ULA also generates two 8 8 MHz clocks on pins 46 47 from which the encoder derives the 4 43 MHz reference and quadrature chroma sub carriers The fact that the pixel and chroma carriers are derived from the same external clock source means that dot crawl is eliminated The dot pattern itself is minimised by adjusting the display line length Ihe digital RGB and bright up signals available from the ULA on pins 19 22 are derived by accessing the picture information located in page 5 or 7 of the contended RAM area at the pixe rate para 4 12 8 The addresses are necessarily independent of the CPU and appear on the address lines to DMAO and DMA7 as two separate bytes timed by the RAS CAS row column address select lines is a decode of bit 3 VB loaded in the bank register IC31 and sets the m s row column address bits as follows VB DMA7
45. ssed 7 15 0 2 14 1 These bits select the RAM page located in the second 16K of the 280 address space beginning at 4000u and result in the PAL generating ULAL5 15 0 and ULA14 1 The ULA lines signal an access of the contended RAM area and prompt 1 1 to assert the DRAS CAS and DRAMWE lines controliinq the read write operation At the same time ULAI5 inhibits the CAS output from 1027 preventing any access to the uncontended RAM area Ihe 2 1 data selector IC30 supplies the m s row and column address bits to the contended 0 first selecting the row address 14 1 while DRAS is low and the column address bit 15 0 when it returns high This combination selects the second 16K bank of RAM in the contended area allowing DMA6 DMAO to access locations in page 5 used for the standard screen display 145 4 10 4 12 4 124 4 12 2 221223 58 1 7415 1 2414 0 These bits select the RAM page appearing in the third 16K of the 280 address space beginning at 8000 and result in the PAL generating 15 UALS 1 and 14 0 The ULA lines signal an access to the uncontended RAM area and enable 1027 to assert the CAS line which together with RAS MREQ and WR control the read write operation Access control lines for the contended RAM area generated by i e CAS DRAS and DRAMWE are not asserted at this time VA15 and 14 respectively s
46. t row 2 column 8 on the upper membrane SYMBOL SHIFT and row 3 column 8 on the lower membrane full stop Tape Interface When LOADing or SAVEing programs using a cassette recorder the ULA transfers information between the MIC and EAR sockets and the data bus performing A D and D A conversions as required During the LOAD operation the CPU executes successive 1 0 read cycles to 0 port address 254 reading the EAR input off bus line D6 When performing a SAVE operation the CPU executes successive 1 0 write cycles to I O port address 254 this time writing data to the MIC output via bus line D3 2 292 2 20 581 ensure that 1 0 cycles are correctly implemented the 1080 line supplying the is gated with address line AO via TRO Thus if any memory transactions occur when AO is high i e not port address 254 then the input 15 forced high inhibiting any attempt to perform the 1 0 cycle ULA Sound Output It should be noted that while SAVEing the level of the MIC output is barely sufficient to modulate the sound carrier to 1039 However during the execution of BEEP instruction the CPU writes instead to port 254 on bus line D4 This effectively boosts the MIC output modulating the sound carrier so that the tone can be easily heard Programmable Sound Generator The audio from the sound generator IC32 is derived from a master clock input supplied by the ULA controlled and shaped in accor
47. t tape Blank tape Open Market Double sided adhesive tape 12mm and 6mm wide Tesafix 959 B D FTESA or 3M equivalent Engineers who are already familiar with the Sinclair SPECTRUM will find some similarities in the SPECTRUM 120 The SPECTRUM 128 however is a more sophisticated device with improved colour and sound circuitry FAULT DIAGNOSIS Techniques In a closed loop system such as a computer because of the inter dependence of numerous component parts fault diagnosis is not necessarily straight forward In addition because of the high speed cyclic operation interpretation of any waveforms on control data and address lines as being valid depends to a large extent on practical experience of the system There are however certain checks with valid waveforms and levels that can be carried out before substituting any integrated circuits Experience has shown that the best method of intially checking waveforms and levels can be to compare with the same point in a known serviceable board The following pages provide a basic fault finding procedure and furnish list of possible faults along with suggested ways of curing them T 252 24 With a densely populated board such the SPECTRUM 128 careful physical examination of the board can sometimes indicate an obvious fault Burnt out discrete components or an overheated track show up immediately as do the attentions of an enthusiastic amateur Bearing in mind the
48. t used IN4148 Not used 157 Not used 157 Not used 2 88 5 1 14148 157 14148 INTEGRATEO CIRCUITS Reference IC1 ULA IC2 CPU 103 4 IC5 16051013 229 126 1027 1020 1029 1030 65 2 1036 1034 1055 1236 1057 1038 SRI AAA Device 70001 7804 1780 Not used SPECTRUM 128 4164 Not used 4164 Not used 7 8401 741 504 HAL1OH8CN 7415157 1415174 AY 3 8912A 1488 1489 Not used 2000 74504 1376 Manufacturer Type Manufacturer Type Signal Signal Rectifier Rectifier Zener Signal Rectifier o Lo tia Manufacturer Ferranti Zilog NEC 15015 9086 Mullard Texas MMI National Not National General Instrument Phillips Motorola Notes Notes RESISTORS 1 4W 5 unless otherwise stated Circuit Reference j 1 1 8 R9 R16 R17 R23 R24 R25 R26 27 R28 R30 1 R31 R32 R33 R34 R35 R36 R37 R38 R57 R58 R59 R60 R61 R62 R64 R65 R67 R68 R69 R70 R72 R73 R74 R78 R79 R80 R86 R87 R88 R89 R90 R91 R95 R96 R98 R99 R100 102 R103 R104 R105 R106 R107 R108 R109 R110 R111 SR1AAA Value 470R 8 2 4708 1 0 180R 470R 10 220K Not used 680R 15R 680R 1KO Not used 1KO 1 8 220R 15R Not used 10KO 6K8 10KO Not used 1KO Not used 2K2 Not used OR 1KO
49. tly rectified and smoothed by 015 C44 producing the 12V output The square wave at collector also supplies a charge pump 111 112 and 028 29 which derives the 12V rail supply is taken from this rail via a zener 119 Ihe following supplies are available on the expansion connector AOV pulsed 4124 238 LAV 232 5B 9 unregulated pin 4A ground pins 6A 14 1 22 2 0 gt Ci cj TM SECTION 2 DISASSEMBLY ASSEMBLY Sub Section LIST OF CONTENTS Page No 1 Disassembly 251 2 Assembly D Isl 1 Iso 25 SR1AAA DISASSEMBLY Umplug all input output connectors and turn the computer upside down to reveal eight fixing screws Release the screws noting the position of two countersunk screws for re assembly turn the computer right side up and separate the case halves To disassociate the case halves carefully disconnect the keyboard ribbon cables from the pcb To remove the pcb from the lower case half remove the board fixing screws and the fixings securing the voltage regulator to the finned heatsink CAUTION If the pcb is to be powered up when separated from the case the pcb with heatsink attached should be removed as a complete assembly The heatsink is secured to the case by two screws Take care not to damage the electrical connections to the regulator To change the keyboard membrane bubble mat or a
50. to Table 5 2 Sud Fig ILLUSTRATIONS 2 Spectrum 128 PCB Component Layout 9 10 Ja Keypad PCB Component Layout Soll INTRODUCTION Parts lists for the SPECTRUM 128 are provided in table form one for the case assembly Table 5 1 one for the main pcb assembly Table 5 2 and another for the keypad pcb assembly Table 5 3 PCB layout diagrams are given in Figures 5 1 and 5 2 the notes to be found in Table 5 2 are explained below 2 NOTES TABLE 5 2 SRIAAA 1 11 RAM chips should have 150ns access time and 128 row refresh This includes parts from the following manufacturers Hitachi Intel Mitsibushi Mostek Motorola NEC OKI Panasonic Toshiba and National 2 If is type KSC839 resistor R24 should be 15 3 Provision has been made on the pcb for a 2 to 22pF film dialectric trimmer should the need arise 4 The ROM should be pin compatible with a 27256 EPROM and have an address access time of less than 400 ns The output enable access time should be less than 250 ns 5 The crystal is series resonant with 20pF and accurate to 10 ppm absolute 10 ppm 20 to 6096 5 ppm per year 0 If preferred the 20uF capacitor used for C124 may be split Into two Parallel capacibors oL 10 2 20 the 008121005 C124 and C130 7 For FTZ German version only 8 6 0 MHz version Type for use in the 5 5 MHz version Iype No for use in most other European countries 4 5 4
51. upply the m s row and column address bits for the uncontended RAM area MA7 and select the second 16K bank of RAM allowing to access locations in 2 241 ZAl4 1 These bits select the RAM page appearing in the top 16K of the 200 address space beginning at C0004 The bits together with B2 BO from the bank register 1031 are decoded by the PAL to select any page from the RAM according to the setting of the supplementary address line pairs For the uncontended RAM space ULA15 is always high allowing 1027 to control read write operations UA15 14 assume one of four possible states reflecting the state of 81 80 and select a page in the range 0 3 For contended RAM accesses ULAl5 is always low allowing to control the read write operations and the data selector IC30 to deliver the m s row and column address bits VA14 15 The latter also assume one of four states and since B2 is set selects a page in the range 4 7 Read Write Operations and Bus Arbitration Ihe following description should be read in conjunction with the circuit diagram given in Figure 1 5 Read Only Memory IC5 The physical ROM is a 32 byte device but appears in the 780 address space as two separate 16K ROM s ROM 1 is the old 48K Spectrum ROM slightlymodified and is selected when bank register bit 4 sets address 14 ROM 0 is the new Spectrum 128 ROM and is selected when bit 4 is clear CPU accesses occur during memory read cycles when
52. utes a 16 015 address bus with active high tri state outputs The address bus provides the address for memory data exchanges and for data exchanges with the ULA It is also used during the interrupt routine see below when scanning the keyboard matrix Control Bus The control bus is a collection of individual Signals which generally organise the flow of data on the address and data buses The block diagram only shows five of these signals although others of minor importance are made available at the expansion port see Figure 1 5 for details Starting with memory request MREQ this signal is active low indicating when the address bus holds a valid address for a memory read or memory write operation Input Output request is also active low but indicates when the address bus holds a valid address for 1 0 read write operations The read and write signals RD and WR are active low and one or other is active indicating that the CPU wants to read or write data to a memory location or I O device All the control signals discussed so far are active low tri state outputs The last control signal described here is the maskable interrupt INT This input is active low and is generated by the ULA once every 20 ms Each time it is received the CPU 1 15 the maskable interrupt routine during which the real time clock is incremented and the keyboard and keypad scanned CPU Clock Returning to the CPU clock mentioned earlier i
53. vice history is known 4 5 cpa SRIAAA REPAIR Renewal of components should be carried out using recognised desoldering heatsinking techniques to prevent damage to the component or to the printed circuit board Other points to be noted are a When replacing a keyboard matrix take care that the ribbon connectors are fully inserted into the board connectors and are not kinked during insertion Make sure there is a good contact made between the voltage regulator body and the associated heatsink in order to ensure adequate heat conduction When the regulator is being replaced it is recommended that a Suitable proprietary thermal grease is applied to the rear surface of the component body The modulator should be replaced as a complete unit When replacing plug in ICs it is advisable to use the correct removal and insertion tools Avoid contaminating the connection pins by handling When handling ICs take normal anti static precautions It is recommended that only a suitably earthed low power soldering iron be used After any component has been renewed the circuit board should be examined carefully to ensure that there are no solder splatters which may cause short circuits between tracks and connector pins 4 6 Al 2329 7X Collector B TRA Base HEUTE V 1 37 Pin 6 Collector E Id Pin 42 IC1 Pin 2 4 6 TET
54. ypad once every other interrupt on demand from the 280 902 keypad scanning routine is much the same routine adopted by the Z80 and ULA when scanning the main keyboard The PIC addresses each column in turn and scans the rows to determine whether a key is pressed The results of the scan are logged and passed to the Z80 on a demand response basis see para 5 8 9 Each demand prompts the PIC to scan a row and report any change in the status since the previous scan If there is no change the PIC responds negatively sending a space in response to the START signal from the 280 In this case the PIC and 280 determine that the next START signal is a call for the result of the row scan at the next column address If the scan indicates that there has been a change in status since the previous scan the PIC responds positively by sending a mark in response to the START signal The 280 responds by sending a further four START signals prompting the PIC to transmit a 4 bit serial code with a 1 set in the bit position corresponding with the particular row Since the 780 keeps a log of the column address by counting the number of START signals it sends and registering the PIC responses since the start of the interrupt it can readily identify the key code from a look up table SRIAAA 5 8 4 physical level data exchanges between the PIC and the 280 are conducted at RS232 signal levels over a single line pair a transmit line
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