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Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification

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11. METAL HEAT SINK ccc C 6 SEATING PLANE d IL ue IL ajaaa C C e H ddddC ATE S eee c Y MILLIMETERS SOLDER BALLS B T T MIN M MAX 3 20 340 0 40 0 50 060 Be 2 80 D E 35 00 BASIC Dyfi 33 00 REF 100 BASIC o 0 50 0 60 0 70 NOTES 1 ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14 5M 1994 c Nus 2 SYMBOL M IS THE BALL MATRIX SIZE ddd xe x 0 30 eee ces om 010 3 CONFORMS TO JEDEC MS 034 AAR 1 DEPOPULATED M 34 e Figure 4 6 FF1152 Flip Chip Fine Pitch BGA Package Specifications Virtex 4 FPGA Packagi
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21. 4X TOP VIEW PIN 1 LD O00000000000000000 0000000000000
22. Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 5 IO_L8N_CC_ADC1_LC_5 D20 5 IO L17P 5 K20 5 IO L17N 5 L19 5 IO L18P 5 E17 5 IO L18N 5 F17 5 IO L19P 5 J23 5 IO L19N 5 K23 5 IO L20P 5 D18 5 IO L20N VREF 5 E18 5 IO L21P 5 K21 5 IO 21 5 Ja 5 IO L22P 5 C18 5 IO L22N 5 C17 5 IO L23P VRN 5 124 5 IO_L23N_VRP_5 H23 5 IO_L24P_CC_LC_5 A17 5 IO L24N CC IC 5 B17 5 IO L9P CC IC 5 D24 5 IO L9N CC IC 5 C24 5 IO L10P 5 D21 5 IO L10N 5 C21 5 IO L11P 5 F24 5 IO L11N 5 F23 5 IO L12P 5 C23 5 IO L12N VREF 5 C22 5 IO L13P 5 H22 5 IO L13N 5 G22 5 IO L14P 5 G17 5 IO 5 H17 5 IO_L15P_5 H24 5 IO L15N 5 G24 5 IO L16P 5 C19 5 IO L16N 5 D19 5 IO L25P CC IC 5 K22 5 IO L25N CC IC 5 L23 5 IO L26P 5 L18 5 IO L26N 5 K18 5 IO L27P 5 L24 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 5 IO 27 5 M24 5 IO L28P 5 D16 5 IO L28N VREF 5 E16 5 IO L29P 5 M22 5 IO L29N 5 N22 5 I
23. V p V C J w 0000000000l060000004 Y 14 00 MAX LID A 7 bbb IC a SEATING PLANE A IXIEUIJ4pdU UUUUUU UUUUUUUUUUUUUJ al ceg T ind jH ae H C 2 Vicia JB AFFF OIC S SF363 Sn Pb SOLDER BALLS 4 MILLIMETERS N B T U MIN NUM MAX E l 179 199 3 0 36 0 40 0 44 Ae 114 A 155 D E 17 00 BASIC 15 20 REF e 0 80 BASIC NOTES 9b 0 45 0 50 0 55 _ i 3 1 ALL DIMENSIONS AND TOLERANCES CONFORM He 7 020 S TO ANSI Y14 5M 1994 bbb 025 3 i me ew 080 3 2 SYMBOL M IS THE BALL MATRIX SIZE eee me 0 65 3 3 CONFORMS TO JEDEC MO 216 BAM 1 DEPOPULATED ae 010 3 EXCEPT FOR DIMENSIONS A b AND ASSOCIATED M 20 e TOLERANCES AS NOTED UGO075 c4 052208 Figure 4 1 SF363 Flip Chip Fine Pitch BGA Package Specifications 270 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Summary FF668 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch
24. Continued Bank Pin Description Pin No Connects in LX40 Number LX60 and SX55 Devices N A GND AF2 N A GND AP2 N A GND J3 N A GND Wa N A GND AJa N A GND B4 N A GND M4 N A GND AB4 N A GND AM4 N A GND E5 N A GND R5 N A GND AES N A GND H6 N A GND V6 N A GND AH6 N A GND 7 GND L7 N A GND 7 GND AL7 N A GND D8 N A GND P8 N A GND ADS N A GND AP8 N A GND G9 N A GND U9 N A GND AG9 N A GND K10 N A GND Y10 N A GND AK10 N A GND C11 N A GND L11 N A GND N11 N A GND AC11 N A GND AN11 N A GND F12 N A GND K12 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SXS5 Devices N A GND M12 N A GND T12 N A GND AD12 N A GND AF12 N A GND J13 N A GND L13 N A GND R13 N A GND W13 N A GND AC13 N A GND AE13 N A GND AJ13 N A GND B14 N A GND M14 N A GND T14 N A GND AB14 N A GND AD14 N A GND AM14 N A GND E15 N A GND R15 N A GND W15 N A GND AE15 N A GND H16 N A GND P16 N A GND V16 N A GND AH16 N A GND AP16 N A GND L17 N A GND AA17
25. Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 7 IO_L2N_7 AAI5 7 IO L3P 7 R21 7 IO L3N 7 R20 7 IO 7 AD16 7 IO VREF 7 AC16 7 IO L5P 7 T23 7 IO L5N 7 T22 7 IO L6P 7 T17 7 IO L6N 7 U17 7 IO L7P 7 U24 7 IO L7N 7 T24 7 IO L8P CC IC 7 Y16 7 IO L8N CC IC 7 Y15 7 IO L9P CC IC 7 W24 7 IO_LIN_CC_LC_7 V24 7 IO L10P 7 AB17 7 IO L10N 7 AB16 7 IO L11P 7 V23 7 IO_L11N_7 V22 7 IO L12P 7 U19 7 IO L12N VREF 7 T18 7 IO L13P 7 W23 7 IO L13N 7 Y23 7 IO L14P 7 AA17 7 IO 7 Y17 7 IO L15P 7 U20 7 IO L15N 7 T20 7 IO L16P 7 AD18 7 IO_L16N_7 ACI7 8 IO L25P CC IC 8 AC7 8 IO L25N CC IC 8 AC6 8 IO L26P 8 Y6 8 IO L26N 8 AA5 8 IO L27P 8 Y8 8 IO 27 8 AA8 8 IO L28P 8 AB5 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 8 IO L28N VREF 8 AB4 8 IO L29P 8 AB7 8 IO L29N 8 AB6 8 IO L30P 8 AD4 8 IO L30N 8 ADS 8 IO L31P 8 AA7 8 IO_L31N_8 Y7 8 IO L32P 8 AD6 8 IO L32N 8 AD5
26. Bank PinDescription hig 8 IO L25P CC IC 8 AG13 8 IO L25N CC LC 8 AH13 8 IO L26P 8 AJA2 8 IO L26N 8 AK12 8 IO L27P 8 AF11 8 IO_L27N_8 AG11 8 IO_L28P_8 AF9 8 IO L28N VREF 8 AE9 8 IO L29P 8 AG12 8 IO_L29N_8 AH12 8 IO L30P 8 AM13 8 IO L30N 8 AM12 8 IO_L31P_8 AK14 8 IO_L31N_8 AL14 8 IO_L32P_8 AK13 8 IO L32N 8 AL13 8 IO L17P 8 AF15 8 IO L17N 8 AG15 8 IO L18P 8 AH10 8 IO L18N 8 AJ10 8 IO_L19P_8 AJ16 8 IO L19N 8 AK16 8 IO L20P 8 AF10 8 IO L20N VREF 8 AGI10 8 IO L21P 8 AH15 8 IO L21N 8 AJ15 8 IO 122 8 AL11 8 IO_L22N_8 AM11 8 IO_L23P_VRN_8 AH14 8 IO L23N VRP 8 14 8 IO L24P CC LC 8 AJ11 8 IO_L24N_CC_LC_8 AK11 8 IO_L1P_8 AB11 8 IO LIN 8 AAI1 8 1 12 8 AK7 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 131 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber FX60 Devices FX40 Devices 8 IO_L2N_8 AJ7 8 IO_L3P_8 AB13 8 IO L3N 8 AA13 8 IO 8 AH8 8 IO VREF 8 AH7 8 IO L5P 8 AC12 8 IO_L5N_8 2 8 IO L6P 8 AM8 8 IO_L6N_8 AM7 8 IO L7P 8 AD14 8 IO_L7N_8 AC13 8 IO_L8P_CC_LC_8 AL8 8 IO_L8N_CC_LC_8 AK8 8 IO L9P CC LC 8 AD12 8 IO L9N CC LC 8
27. A 31919 3 3 A B 3 3 3 3 3 3 B C 9 3 3 3 C D D E E F F G G H H J 110 10 10 10 10 10 9 9 9 9 91 K 10 10 10 10 10 10 10 OPO 919 9 K L 10 10 10 10110110 9 99 919 9L M 110 10 10 10 10 10 10 10 M 10 10 10 10 10 10 9 9 99 9 9 9 N P 10 10 10 10 10 10110 9 9 9 9 9 9 R 10 10 10 10 10 10 10 10 9983183919 988 n T 10 10 10 10110110 9 9 19 919 91 T u 10 10 10 10 10 10 10 FSO 919 9 U v 1010 fo WA 9 9 9 y Ww Ww Y Y AA AA AB 4 4 AB AC 4 d AC AD 41414 414 AD 4 41414 AE Z ess 2 4 6 8 10 4 16 18 20 22 24 26 1 5 7 9 111243 15 17 19 21 23 25 ug075 01 color2 121504 Figure 3 6 FF668 Color Coded SelectlO and Bank Information 248 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Package Pinout Diagram FX20 FF672 Package Pinout Diagram FX20 FF672 XC4VFX20 Top View
28. Bank Pin Description Pin Number 14 IO 2 14 U3 14 IO_L3P_14 U15 14 IO L3N 14 V14 14 IO 14 W4 14 IO_L4N_VREF_14 V4 14 IO_L5P_14 Y6 14 IO L5N 14 W6 14 IO L6P 14 W5 14 IO L6N 14 V5 14 IO L7P 14 U16 14 IO L7N 14 V17 14 IO L8P CC IC 14 W7 14 IO L8N CC LC 14 V7 14 IO L9P CC LC 14 AC3 14 IO L9N CC LC 14 AB3 14 IO L10P 14 4 14 IO L10N 14 Y3 14 IO L11P 14 V13 14 IO L11N 14 V12 14 IO L12P 14 AA5 14 IO L12N VREF 14 AAA 14 IO L13P 14 Y11 14 IO L13N 14 W10 14 IO L14P 14 Y9 14 IO 14 W9 14 IO L15P 14 V15 14 IO L15N 14 W15 14 IO L16P 14 Y8 14 IO L16N 14 Y7 14 IO L25P CC LC 14 AJ4 14 IO_L25N_CC_LC_14 AH4 14 IO_L26P_14 AD6 14 IO L26N 14 AD5 14 IO 1 27 14 Y13 14 IO L27N 14 Y12 14 IO L28P 14 14 IO L28N VREF 14 218 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 14 IO L29P 14 AK4 14 IO L29N 14 AK3 14 IO L30P 14 AH3 14 IO L30N 14 AG3 14 IO L31P 14 AAT 14 IO L31N 14 AA10 14 IO L32P 14 6 14 IO L32N 14 AF5 0 VCCO 0 0 AA17 0 VCCO 0 0 Y20 0 VCCO 0 0 W23
29. 8 j00000000000000000000000000 45 00000000000000000000000000 1 1 2 1 a d e A D DYE e Db aa dd ee Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 Chapter 4 Mechanical Drawings XILINX FF 1148 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch BOTTOM VIEW 54 52 3028 26 24 22 20 18 16 14 12 10 8 64 2 537i 29 27 9s 27121 1917 15 15 1 9 7 5 3 1 D1 TOP VIEW 0 20 4 D 990090 loooooooo loooooooo loooo
30. BOTTOM VIEW TOP VIEW 20 20 1641 i Di g F D gt A 4 PIN 1 Fe 21222919 131211109 8 7 5 5 5 3 2 4 A Too0000000000l00000000000e44a T g B di N 6 OOOOOO00 J E e c2 au A
31. m B oNXXI v Vo ilNocosooHoos o09lcoveaIaMXXBOoNM 1259455978910 4 12 414 16 7184 20 22 24 26 28 30 132 34 36473839 User I O Pins O IO LXXY s AVCCAUXRXA Multi Function Pins ADC1 ADC7 DO D31 CC N GC SM1 SM7 VREF VRN VRP poeezczoeocoo 5 Q O CCLK CS_B D_IN DONE DOUT_BUSY HSWAPEN INIT M2 M1 MO PROG_B PWRDWN_B RDWR_B GNDA RSVD VBATT VCCAUX VCCINT MGTCLK MGTVREF RTERM AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB VINES FE oo 0C FO DE c gri k E gt 0 Zooo N Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use Figure 3 23 FF1517 Flip Chip Fine Pitch BGA Composite Pinout Diagram FX100 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 lt S lt CHADVVUZESETACIOMMOVOWDS RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB UG075_08b_050108 265 Chapter 3 Pinout Diagrams XILINX FF1517 Package Pinout Diagram FX140 266
32. Continued Bank Pin Description Number LX60 and SXS5 Devices 6 IO L15N 6 A9 6 IO L16P 6 F8 6 IO L16N 6 G8 6 IO L25P CC IC 6 C14 6 IO L25N CC IC 6 C13 6 IO L26P 6 E6 6 IO L26N 6 F6 6 IO L27P 6 C5 6 IO 27 6 D5 6 IO L28P 6 G7 6 IO L28N VREF 6 G6 6 IO L29P 6 E14 6 IO L29N 6 D14 6 IO L30P 6 B3 6 IO L30N 6 B2 6 IO L31P 6 H8 6 IO L31N 6 H7 6 IO L32P 6 K8 6 IO L32N 6 J7 7 IO L25P CC SM7 LC 7 AL24 7 IO L25N CC SM7 IC 7 AL25 7 IO L26P SM6 7 AL26 7 IO 26 SM6 7 AK26 7 IO L27P SM5 7 AN22 7 IO 27 SM5 7 AN23 7 IO_L28P_7 AJ25 7 IO L28N VREF 7 AH25 7 IO L29P SMA 7 AP24 7 IO L29N SMA 7 AN24 7 IO L30P SM3 7 AM26 7 IO L30N SM3 7 AM27 7 IO L31P SM2 7 AL23 7 IO L31N SM2 7 AM23 7 IO L32P SMI1 7 AN25 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 97 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 98 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin No Connects In 1x40 Number LX60 and SX55 Devices 7 IO_L32N_SM1_7 AM25 7 IO_L17P_7 AP21 7 IO L17N 7 AP22 7 IO L18P 7 AP29 7 IO L18N 7 AN29 7 IO L19P 7 AK24 7 IO L19N 7 AJ24 7 IO L20P 7 AK27 7 IO L20N VREF 7 AK28 7 IO L21P 7 AG23 7 IO L21N 7 AF24 7 IO L22P 7 AG25 7 IO L22N 7 AG26
33. Bank Pin Description Pin Number FX100 Devices 9 IO_L27N_9 U30 9 IO_L28P_9 U27 9 IO L28N VREF 9 U26 9 IO L29P 9 V28 9 IO L29N 9 U28 9 IO L30P 9 W26 9 IO L30N 9 V25 9 IO L31P 9 V30 9 IO L31N 9 V29 9 IO L32P 9 W27 9 IO L32N 9 V27 10 IO L17P 10 L6 10 IO L17N 10 M6 10 IO L18P 10 M3 10 IO L18N 10 N3 10 IO L19P 10 K4 10 IO L19N 10 L4 10 IO_L20P_10 N5 10 IO_L20N_VREF_10 P5 10 IO_L21P_10 N7 10 IO L21N 10 P7 10 IO_L22P_10 P6 10 IO L22N 10 R6 10 IO L23P VRN 10 N4 10 IO_L23N_VRP_10 P4 10 IO L24P CC LC 10 R8 10 IO L24N CC LC 10 R7 10 IO L1P 10 N12 10 IO LIN 10 M11 10 IO L2P 10 M10 10 IO 2 10 N10 10 IO_L3P_10 G7 10 IO L3N 10 H7 10 IO 10 L8 10 IO VREF 10 M7 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 10 IO L5P 10 P11 10 IO L5N 10 R11 10 IO L6P 10 J6 10 IO L6N 10 K6 10 IO L7P 10 P12 10 IO L7N 10 R12 10 IO L8P CC LC 10 G3 10 IO L8N CC IC 10 H3 10 IO L9P CC LC 10 G6 10 IO L9N CC IC 10 G5 10 IO L10P 10 10 10 IO L10N 10 9 10 IO_L11P_10 K8 10 IO L11N 10 K7 10 IO L12P 10 H4 10 IO L12N VREF 1
34. Bank Pin Description Pin Number FX100 Devices N A GNDA_110 AW8 N A GNDA_111 NC N A GNDA_111 2 NC N A GNDA_111 AB2 NC N A GNDA_111 AD2 NC N A GNDA_111 AG2 NC N A GNDA_111 AK2 NC N A GNDA_112 H2 N A GNDA_112 12 GNDA_112 12 GNDA_112 N2 N A GNDA_112 T2 N A GNDA_113 w2 N A GNDA_113 B1 N A GNDA 113 113 H1 N A GNDA_113 A2 N A GNDA_113 E2 N A GNDA_113 F2 N A GNDA_113 G2 N A GNDA_113 B5 N A GNDA 113 B7 N A 6 113 B9 N A GNDA 114 B12 N A GNDA 114 B15 N A GNDA 114 B17 N A GNDA 114 B19 N A GNDA 114 A20 N A VREEN SM 2 AT21 N A VREFP SM AT20 N A AVDD SM O AT19 VN SM AU21 N A VP SM AU20 N A AVSS_SM 2 AU19 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number ps VREFN_ADC D21 N A VREFP_ADC 2 D20 N A AVDD ADC 0 D19 N A VN ADC C21 N A VP ADC C20 N A AVSS ADC 2 C19 N A GND D3 N A GND P3 N A GND AA3 N A GND AD3 N A GND AP3 N A GND G4 N A GND U4 N A GND AG4 N A GND AU4 N A GND K5 N A GND Y5 N A GN
35. 8 104412 FF676 LX25 Top View 9 13 15 16 OO 18920 22924026 17 19 21 29 25 OOOO OO mSOMOOO ONO 4 Q 69 O O camvzErmrzxcecrommoou Q O O User I O Pins O IO LXXY 4 Multi Function Pins ADC1 ADC7 DO D31 cc N_GC P_GC SM1 SM7 VREF VRN VRP poceczoeooo Q OldDOOOLIO
36. Continued Bank Pin Description Pin No Connects in LX40 Number LX60 and SX55 Devices 5 VCCO_5 K25 5 VCCO_5 C26 5 VCCO_5 F27 5 VCCO_5 B29 5 VCCO_5 E30 5 VCCO_5 A32 6 VCCO_6 A2 6 VCCO 6 C6 6 VCCO 6 F7 6 VCCO_6 J8 6 VCCO 6 B9 6 VCCO 6 E10 6 VCCO 6 H11 6 VCCO_6 A12 6 VCCO 6 D13 7 VCCO 7 AL22 7 VCCO 7 AP23 7 VCCO_7 AG24 7 VCCO_7 AK25 7 VCCO_7 26 7 VCCO 7 AF27 7 VCCO_7 AJ28 7 VCCO_7 AM29 7 VCCO_7 AP33 8 VCCO_8 AP3 8 VCCO_8 AK5 8 VCCO_8 AN6 8 VCCO_8 8 8 VCCO_8 AM9 8 VCCO_8 AE10 8 VCCO 8 AH11 8 VCCO_8 AL12 8 VCCO_8 AP13 9 VCCO 9 R20 9 VCCO 9 23 9 VCCO_9 N26 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 113 Chapter 2 Pinout Tables 114 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin No Connects in LX40 Number LX60 and SX55 Devices 9 VCCO_9 J28 9 VCCO_9 M29 9 VCCO_9 H31 9 VCCO_9 L32 9 VCCO_9 D33 9 VCCO 9 G34 10 VCCO_10 H1 10 VCCO_10 12 10 VCCO_10 D3 10 VCCO_10 GA 10 VCCO 10 K5 10 VCCO 10 N6 10 VCCO_10 M9 10 VCCO_10 R10 10 VCCO_10 P13 11 VCCO 11 AA22 1 VCCO 11 Y25 11 VCCO 11 AC26 1 VCCO 11 AB29 11 VCCO 11 AE30 1 VCCO_11 AH31 1 VCCO_11 AL32 11 VCC
37. AA AB 4 1 BONOCOOOCH MS BSONOOORM AB AC WEE TRE TRE T 69 OOMOOCONCMOOOSAD ac AD MIIODOOOSIOOOCIMWIWIEWI 5 TM TIMFKOSIOOOOLIOOOOM AD AE WW WW Wm Omm m aoo 1 AE OBJIOOOMLIOOOLMETME TW TMONSOMI MI IDOOONOGOOLIBQO AF AG ENMEIOLICGOOORBIONSL IM IM 9 SIODC OMLIMLMONXOOOODOOOME AH OomOOOBNOOOOLIOOOGOCR CW Wt D ese WIL WOOL AJ eB3NOOOCOLIGOOOCRBRIOWMWGHL IC WIL WMOMNMOSNOOOO83S AJ Ak BMNMOOLIOOOODCIOOOOLIO9t suad DIODWMOOLMOMCIOOOOLDGOONM ak AL NMOOOO9OSOOOOLIOOIM9e5SIOo9OoeLieeuosoe ee oco 0099 AL e EOBNOOOOLIOOGUuMOniO e9eoLI O0OooeneooonDeooOSOOOL Se AM AN AN QINLIOOOORIOOOOLIOOOO CROCCO IOOOQmNO Se e O IDOOOUNAd AP AR OLIOOOORIOGOGOLICODeoSIOO e eLieoooSoo0N AR AT at AU OF OOGONOOOOLIOOORISISISIL L JOOOONe 60 OIL IOONEPIO BH EmuumTrEcNCHE NHNHLU NETU3JNITNE LUNEN NCHECHETINSTU NO AW B coBXXESCOMOCEO CKO OECOKCORCOMSOCBXXEC OM AW j 244g ig B ig 2 18 52054 22 User I O Pins Dedicated Pins Other Pins 10_LXxY_ Z ADC S
38. Dedicated Pins Z ADC S SM GND CCLK TCK GNDA B CS B I TDI RSVD D IN O TDO VBATT D DONE M TMS 4 VCCAUX A DOUT BUSY J TDP W5 VCCINT H HSWAPEN C VCCO Y INIT n NO CONNECT 2 T 0 M2 M1 MO MGTCLK P PROG B G MGTVREF W PWRDWN B RTERM U RDWR B Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB o00052 9 2 9 Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use Figure 3 9 FF672 Flip Chip Fine Pitch BGA Pinout Diagram FX60 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB UGO075 04 050108 251 Chapter 3 Pinout Diagrams XILINX FF672 Color Coded SelectlO and Bank Information FF672 Top View 18920 22 24 26 23598949 1044124314151617 19 21 23 25 A 6 6 6 6 5 5 A B 6 6 6 6 6 alale B C 6 6 6 6 6 6 alele sss D 6 6 6 6 6 6 6 6 5 HALE alle D E 6 6 6 6 6 6 6 sss ARLE 6 6 6 6 6 Apne Bb F G 6 6
39. Continued Bank Pin Description Pin Ne ii ERI Number LX60 and SX55 Devices 3 IO L2P GC VRN LC 3 H17 3 IO GC VRP LC 3 JA7 3 IO L3P GC LC 3 H19 3 IO L3N GC IC 3 H18 3 IO I4P GC LC 3 E18 3 IO LAN GC VREF IC 3 E17 3 IO L5P GC LC 3 K18 3 IO L5N GC IC 3 K17 3 IO 6 GC LC 3 E16 3 IO L6N GC LIC 3 F16 3 IO L7P GC LC 3 K19 3 IO L7N GC IC 3 J19 3 IO L8P GC LC 3 G17 3 IO L8N GC LIC 3 G16 4 IO GC LC 4 AF18 4 IO GC IC 4 AE18 4 IO 12 GC LC 4 AG16 4 IO I2N GC IC 4 AF16 4 IO L3P GC LC 4 AH19 4 IO L3N GC LC 4 AH18 4 IO I4P GC LC 4 AK18 4 IO LAN GC VREF LC 4 AK17 4 IO L5P GC LC 4 AG18 4 IO L5N GC ILC 4 AGI17 4 IO Lo6P GC LC 4 AE17 4 IO L6N GC LC 4 AE16 4 IO L7P GC VRN LC 4 AJ19 4 IO GC VRP LC 4 AK19 4 IO L8P GC CC IC 4 AJA7 4 IO L8N GC CC IC 4 AH17 5 IO_L1P_ADC7_5 B23 IO_LIN_ADC7_5 A23 5 IO_L2P_ADC6_5 A26 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 93 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SX55 Devices 5 IO_L2N_ADC6_5 B26 5 IO L3P ADC5 5 A24 5 IO L3N ADC5 5 A25 5 IO 5 G25 5 IO VREF 5 H25 5 IO ADCA 5 C23 5 IO L5N ADCA 5 C24 5 IO 6 ADC3
40. 5158 5 mo c p OoBLIOOOONOCOOOLIOOOONIBIZIZ OOOONOOOOLIOOOOHBIO p E 9 E F IXiMOOOOLIOOOOSNOGOOLICOOGOBNIIOOOLJeeooSNOOOOLMX F a H 099 25 J 6 60 CMOSCHeOCSONCOOCOM J amp eEOOLIOOOOROGMOML 9296969 499 L WIL MOSIOOOCOODLIeeoaMoSieeoorooOo SII L M TREE 69 L MO Mes 69 OOLIMOOOBSIOOO dO M N gw WOOOeXOoOOmm wImMNOSOOOOLOM P QLb IOGGooNOOOOLDWMUMORSOCOMPTTWI WIE MI IOOODmMOOOBNO P R O B5BOONIOOOBMLIOOmwWNL Ww IL Ww Oa WE WE WEE WEE 1 R T EBMOOOOLIOGOOBRIONMUTWIU WC MIC ME MD WOOOSOOOODME u omoLIOOMOC SIOOOCMLIOONL WILL MEI TM CO ODSIOOOOLIOOOmeo u v eo6BloORNOMOMLIOOOORNOMLWLIWMBIYOSIOOOOLIMOOORSOSBOO v w BN 0 4 WOOLIOOMORNOOOOBB w v y AA IEL
41. Bank Pin Description Pin Number 12 IO L19N 12 AH9 12 IO L20P 12 AK7 12 IO L20N VREF 12 AJ7 12 IO L21P 12 AN5 12 IO_L21N_12 AN4 12 IO_L22P_12 AM5 12 IO L22N 12 AL5 12 IO L23P VRN 12 AL8 12 IO L23N VRP 12 12 IO L24P CC LC 12 AT1 12 IO L24N CC IC 12 AR1 12 IO L1P 12 AH5 12 IO LIN 12 AG5 12 IO L2P 12 12 IO 12 AH2 12 IO L3P 12 AG7 12 IO L3N 12 AG6 12 IO 4 12 AJ2 12 IO LAN VREF 12 12 IO L5P 12 12 IO L5N 12 AK1 12 IO L6P 12 AF9 12 IO L6N 12 AF8 12 IO L7P 12 AGS8 12 IO L7N 12 AH7 12 IO L8P CC LC 12 4 12 IO L8N CC IC 12 AH4 12 IO L9P CC LC 12 AJ6 12 IO L9N CC IC 12 AJ5 12 IO L10P 12 AK3 12 IO L10N 12 AK2 12 IO L11P 12 AF11 12 IO_L11N_12 AG10 12 IO L12P 12 AE12 12 IO L12N VREF 12 AE11 12 IO L13P 12 AM3 12 IO L13N 12 AL3 12 IO L14P 12 AM2 174 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 12 IO L14N 12 AMI 12 IO L15P 12 AP2 12 IO L15N 12 AP1 12 IO L16P 12 AL4 12 IO L16N 12 AK4 12 IO L25P CC LC 12 AU2 12 IO L25N CC IC 12 AUI 12 IO L26P 12 AR3 12 IO L26N 12 AR2 12 IO L27P 12 AT4 12 I
42. Bank Pin Description Pin Number 5 IO_L3P_ADC5_5 E27 5 IO_L3N_ADC5_5 D27 5 IO 5 A30 5 IO_L4N_VREF_5 A31 5 IO L5P ADCA 5 G25 5 IO L5N ADCA 5 G26 5 IO L6P ADC3 5 D29 5 IO L6N ADC3 5 E29 5 IO 17 ADC2 5 A28 5 IO L7N ADC2 5 A29 5 IO L8P CC ADCI1 IC 5 D30 5 IO L8N CC ADCI1 LIC 5 D31 5 IO L17P 5 H25 5 IO L17N 5 126 5 IO L18P 5 G30 5 IO L18N 5 H29 5 IO L19P 5 B32 5 IO L19N 5 B33 5 IO L20P 5 129 5 IO L20N VREF 5 K29 5 IO L21P 5 B30 5 IO L21N 5 B31 5 IO L22P 5 C33 5 1 L2N 5 C34 5 IO L23P 5 F31 5 IO L23N VRP 5 G31 5 IO L24P CC ILC 5 B35 5 IO L24N CC IC 5 C35 5 IO L9P CC IC 5 C27 5 IO L9N CC IC 5 B27 5 IO L10P 5 F29 5 IO L10N 5 G28 5 IO L11P 5 J27 5 IO L1IN 5 H27 5 IO L12P 5 C32 5 IO L12N VREF 5 D32 5 IO L13P 5 B28 5 IO L13N 5 C28 162 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 5 IO_L14P_5 A33 5 IO_L14N_5 A34 5 IO_L15P_5 C29 5 IO_L15N_5 C30 5 IO L16P 5 E31 5 IO L16N 5 E32 5 IO L25P CC LC 5 M27 5 IO L25N CC IC 5 L28 5 IO L26P 5 E33 5 IO L26N 5 F33 5 IO L27P 5 H30 5 IO 27 5 J30 5 IO_L28P_5 G32 5 IO_L28N
43. B OOOOGOOLIeoeogeerooeooo c OOOOGRNI9O eeIeOOOORI D OGORIOGGBINILICIYIH GGORNIOGO E OOOOOQGIWAIUIJIDIPIMa 900O0OO F OOLIOONMM G ad 000690 H J OOOOO OOOOO BONSO L QOOOOO M OOOOCUu MOOOON N OOLIOOMEM wWaEMOOLDOO P 4 O20 BOOOOO 8 R OGQGOORIOOGMIKIWIAIHTIEHSONOOQO T 2 OONOCOOOON u 2 2 2 9 9 OOOC 9 C 0 0 0nlninOOOL w ODOONSPCOONAMAO Y 2 3 4 5 6 7 8 9 19441243 4151647184920 Dedicated Pins Z ADC P PROG B C CCLK W PWRDWN B B CS B U RDWR B NI D IN S SM D DONE TCK A DOUT BUSY I TDI H HSWAPEN O TDO INIT M TMS 2 0 0 M2 M1 MO J TDP L TDN Other Pins GND RSVD VBATT VCCAUX VCCINT Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 UG075 02b 050108 SF363 Flip Chip Fine Pitch BGA Pinout Diagram LX15 and FX12 243 Chapter 3 Pinout Diagrams SF363 Package Pinout Diagram LX25 244 SF363 XC4VLX25 Top View
44. OOOOLIOOOORNJOMOOLIe OIMCrOMOO IIDOOONOOOOLIOO AN AP OOLIOOOOBRICGMOOLDI9OtOnNOMOOLDIOOO NOMOOLDOOOORNO AP AR OOOONIOOOOOLIOGOO0 FOSLOOKON OOOTOOCOONSXOO AR AT Ar AU AU AV 69 ON Oc eL 169 OOO AV AW AW 12345 678 g 1054 Aig 197 mage tag O97 99 9 91 9495 26978 G0 User I O Pins Dedicated Pins Other Pins O 1O_LXXY_ Z ADC P PROG B GND Multi Function Pins C CCLK PWRDWN B R RSVD amp ADC1 ADC7 B CS B U RDWR B VBATT DO D31 N D IN S SM 4 VCCAUX cc D DONE K TCK W VCCINT N cc DOUT BUSY TDI N vcco P_GC H HSWAPEN O TDO n NO CONNECT amp LC Y INIT M TMS SM SM7 2 1 0 M2 M1 MO J TDP VREF D TDN Q VRN VRP Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use UGO075 07 050108 Figure 3 21 FF1513 Flip Chip Fine Pitch BGA Composite Pinout Diagram LX100 LX160 and LX200 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 263 Chapter 3 Pinout Diagrams XILINX FF1513 Color Coded Selectl
45. CeecR c D D E OOOO OOOOLIDGQQopRSIOOOOLO OONOOOO E F F OOONQOGOOLIOOOOOBS te oC L M eamosoM oDooooN c H H j 9emoeeeoemr 9 OOOORNIOMOOLIBLWICOSIOOOOLDMLIMOSIOOOOLDOOOO L ONOOOOLIOGWILIMLI9OOLICMm L OLIOOOORIOUBMLUIILIMSOOCOBKWMUBMIIOO 0O0ORIO0O00 M N OOOORIOMCCOLIOOMCSI 999L 50O0aMOSOMMOOLIOOO N P WW aO P R OOOCOCLIGOOORBNIOWLIMUIMCIAIOSOOOODOO9ONOOOO R T OOQOONOLOCEAOANNAAT T u GOONOOOCOLIOOCUINDIABIMUTW YIPIONOOOCGOLIOOOORN u v NOOOOLIOOOOCBIOM IK k EOM OOOLIOOGORIOOO v w GOLICGOOONOOOOLDRBLUIMUTSIHIOWR REIOOMOROOGQOLIO w Y OOOGRBNIOOOOLIOOOORIO AIL 1 y A ONLIMI 13 OOOOLIOOOORIOO AA AB COOLIOOMOCRNIOMOOLI9 O 0 BOCHO MONCOCOCO AB AC OOOORIOOOOLn IM GRNICOMOMUIBMIIWMPSOOOOLDOOO ac AD C OBNIOOOOLIG9O aL KO OLIO ese ML TW OOLIOOO0NO AD AE OOOOCLIOOOC N OM OGMIWLIIOOMOSOOOO AE AF OLIOOGOOBJOMOOLBM o CDCDaMOOLTIMOIMOSIOOOOLIOO AG AH BNI
46. Bank Pin Description Pin NO Connects in XAD Number LX60 and SX55 Devices 0 HSWAPEN 0 T18 0 CCLK 0 R17 0 D IN 0 T16 0 PROG B 0 U22 0 INIT B 0 U21 0 6980 U17 0 DONE 0 U15 0 RDWR B 0 U13 0 VBAIT 0 V22 0 M20 V20 0 PWRDWN B 0 W21 0 TMS 0 V13 0 0 W20 0 TDO 0 V18 0 TCK 0 V14 0 0 W19 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 89 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Do connects m Number LX60 and SX55 Devices 0 DOUT BUSY 0 Y18 0 TDI 0 W17 0 0 F15 0 TDP 0 D15 1 IO D31 LC 1 N19 1 IO LIN D30 LC 1 N18 1 IO 12 D29 IC 1 L15 1 IO L2N D28 LC 1 L14 1 IO L3P D27 LC 1 E21 1 IO L3N D26 LC 1 D21 1 IO D25 LC 1 J14 1 IO_L4N_D24_VREF_LC_1 K14 1 IO L5P D23 LC 1 N20 1 IO L5N D22 LC 1 M20 1 IO L6P D21 LC 1 H14 1 IO L6N D20 LC 1 H13 1 IO L7P D19 LC 1 H22 1 IO D18 LC 1 121 1 IO_L8P_D17_CC_LC_1 F13 1 IO L8N D16 CC LC 1 G13 1 IO L9P GC IC 1 M18 1 IO L9N GC IC 1 L18 1 IO L10P GC LC 1 M17 1 IO 10 GC LC 1 N17 1 IO L11P GC LIC 1 E19 1 IO L11N GC IC 1 D19 1 IO L12P GC LC 1 C17 1 IO L12N GC VREF IC 1 D17 1 IO L13P GC LC 1 C19 1 IO L13N GC LC 1 C18 1 IO L14P GC LC 1 D16 1 IO
47. Bank Pin Description Pin Number FX100 Devices 12 IO L18N 12 AG7 12 IO L19P 12 AG10 12 IO L19N 12 AF10 12 IO L20P 12 AM5 12 IO L20N VREF 12 AL5 12 IO L21P 12 AT4 12 IO L21N 12 AR4 12 IO L22P 12 AK6 12 IO L22N 12 AJ6 12 IO L23P VRN 12 AR6 12 IO L23N VRP 12 AP6 12 IO L24P CC LC 12 12 IO L24N CC LC 12 AG8 12 IO_L1P_12 AB12 12 IO_L1IN_12 AB11 12 IO 12 12 AB10 12 IO 2 12 AC10 12 IO_L3P_12 4 12 1 12 AA13 12 IO 12 AC9 12 IO VREF 12 AC8 12 IO_L5P_12 AC12 12 IO L5N 12 AD11 12 IO_L6P_12 AD10 12 IO L6N 12 AD9 12 IO_L7P_12 AC13 12 IO L7N 12 AB13 12 IO L8P CC IC 12 AD7 12 IO L8N CC LC 12 AC7 12 IO L9P CC IC 12 AF9 12 IO L9N CC LC 12 AF8 12 IO_L10P_12 12 IO L10N 12 AE7 12 IO L11P 12 AC14 12 IO L11N 12 AB15 12 IO L12P 12 AG6 12 IO L12N VREF 12 AG5 214 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 12 IO L13P 12 AN3 12 IO L13N 12 AM3 12 IO L14P 12 AJ5 12 IO 12 AH5 12 IO L15P 12 4 12 IO L15N 12 AN4 12 IO_L16P_12 AL4 12 IO L16N 12 AL3 12 IO L25P CC LC 12 AUS5 12 IO L25N CC LC 12 AT5 12 IO
48. Continued Bank Pin Description Number LX60 and SXS5 Devices 8 IO L13N 8 AN13 8 IO L14P 8 IO L14N 8 AM5 8 IO_L15P_8 AJ10 8 IO L15N 8 AJ9 8 IO_L16P_8 AP5 8 1 L16N 8 AN5 9 IO_L17P_9 P20 9 IO L17N 9 R19 9 IO L18P 9 L28 9 IO L18N 9 L29 9 IO L19P 9 P24 9 IO L19N 9 R24 9 IO L20P 9 H32 9 IO L20N VREF 9 J32 9 IO L21P 9 M27 9 IO L21N 9 M28 9 IO 122 9 H33 9 IO L22N 9 H34 9 IO L23P VRN 9 J31 9 IO_L23N_VRP_9 K31 9 IO L24P CC IC 9 L30 9 IO L24N CC IC 9 L31 9 IO L1P 9 H27 9 IO LIN 9 H28 9 IO L2P 9 C32 9 IO I2N 9 D32 9 IO L3P 9 127 9 IO L3N 9 K27 9 IO 9 M25 9 IO LAN VREF 9 M26 9 IO L5P 9 N22 9 IO L5N 9 N23 9 IO L6P 9 H29 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 101 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Deseription Number LX60 and SXS5 Devices 9 IO_L6N_9 H30 9 IO_L7P_9 C33 9 IO_L7N_9 C34 9 IO_L8P_CC_LC_9 D34 9 IO_L8N_CC_LC_9 E34 9 IO_L9P_CC_LC_9 G30 9 IO L9N CC IC 9 G31 9 IO L10P 9 129 9 IO L10N 9 J30 9 IO L11P 9 E32 9 IO L1IN 9 E33 9 IO L12P 9 N25 9 IO L12N VREF 9 P26 9 IO L13P 9 P22 9 IO L13N 9 R21 9 IO L14P 9 F33 9 IO L14N 9 F34 9 IO L15P 9 K28 9 IO L15N 9 K29 9 IO L16P 9 G32
49. 195955979 g 1041124131415 1647181920212223242526 2728293034 3233349536373839 A B 6 6 6 6 6 6 6 6 6 5 5 5 5 5 9 9 D 6le ele leleje e 6 515 5 5 5 s 9 9 9 9 E 616 lelele e 6 6 6 6 5 5 5 s5 5 9 1919 6 6 6 6 6 6 6 6 lele 5 5 5 5 5 9 G 10 104040 6 6 6 6 6 5 5 5 5 5 5 5 9 9 9 H 10 10 10 10 6 6 6 felele 5 5 5 5 9 9 9 9 l9 J 10 10 10 6 6 6 6 le 515 5 s5 s 9 9 9 o o K 10 10 10 10 10 6 lel le 515 515 9 13 18 L 10 10 10 10 10 6 5 5 5 5 5 je o o 13 M 10 10 10 10 10 10 5 5 5 9 9 9 9 18 13 N 10 10 10 10 10 10 10 40 9 9 9 9 9 13 P 10 10 10 10 10 10 10 10 9 9 9 13 13 13 R 10 10 10 10 10 10 10 9 9 9 13 18 18 T 10 10 10 10 10 10 10 10 10 9 9 9 9 18 18 18 U 14 14114 10 10 10 10 14 14 9 9 9 9 9 9 13 1313 14 14 14 14 10 1411414114 14 9 9 9 9 9 13 13 13 13 Ww 14141414 14 14 14 14 14 14 t4 14 9 9 13 13 13 13 13 13 13 Y 14 14 M4Ma 14 14 14 14 14 14 13 13 13 1313 13 13 118118 AA 14 14 14 14 14 44 44 12 12 13 13 13 13 13413 13 13 18 18 1813 AB 14 M4 14 12 12 12 12 12 13 13 13 13 13 11 13 13 13 13 AC 14 1444 12 12 12 12 12112012 13 13 anjam n 18 13 hs AD 44l14l14 12 12112112 4 alala AE 14 14 1412 12 11 11 Ti 1111 AF 14 14 14 1212 12 num nuin AG 14 1212112112 12 ubl 111111111111 nin 11 AH 14114112 12 12 1242 8 8 8 1 11 afi n AJ 14 12 12 12
50. AD AE OONOGQBRIOQRBI OInInInIOSIOOSOO AE AF OOOOO000Q00p0 AF 8 6 8 12345678 g104412 1314451617 19 21 23 25 User I O Pins Dedicated Pins O IO LXXY Multi Function Pins ADC1 ADC7 DO D31 CC N_GC P_GC ADC PROG_B CCLK PWRDWN_B CS_B RDWR_B D_IN SM DONE TCK DOUT_BUSY TDI HSWAPEN TDO INIT TMS SM1 SM7 M2 M1 MO TDP VREF TDN VRN VRP o Hj m mj go zu li N e 8 e G9 o 18 920 2992426 Other Pins GND RSVD VBATT VCCAUX VCCO NO CONNECT Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use 075 01b 050108 XILINX Figure 3 4 FF668 Flip Chip Fine Pitch BGA Pinout Diagram LX15 SX25 and FX12 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF668 Package Pinout Diagram LX25 LX40 LX60 and SX35 Figure 3 5 FF668 Flip Chip Fine Pitch BGA Pinout Diagram LX25 LX40 LX60 and SX35 FF668 Package Pinout Diagram LX25 LX40 LX60 and SX35 FF668 LX25 LX40 LX60 and SX35 Top View
51. 34 50 MAX 34 50 MAX d LID ccc C SEATING PLANE ux aaa E M S Y MILLIMETERS N 3 T U MIN NOM MAX E a ae se 3 25 0 40 050 0 60 e 150 165 180 D E 40 00 BASIC 38 00 e 1 00 BASIC NOTES b 0 50 0 60 0 70 aaa c 0 20 1 ccc Re Ke 0 25 ded me ms 0 25 2 eee ae 0 10 M 39 2 3 ALL DIM TO ASM SYMBOL M IS THE CONFORMS f DODD O00 OOOUOCUUDUIDCUOOCOUOCOUUUOCOOCOUCOCOOUU ot Gadd MICA B eee MIC SOLDER BALLS Y14 5M 1994 PIN MATRIX SIZE C MS 034 AAU 1 D TO JEDE NSIONS AND TOLERANCES CONFORM EPOPULAT Figure 4 7 FF1513 Flip Chip Fine Pitch BGA Package Specifications ED 276 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Summary FF1517 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch BOTTOM_VIEW C3 0 20 4X TOP VIEW B D gt A PIN 1 LD D1 8 32 30 28 24 ee 60 18 16 14 12 10 8 CASES Meg o7 be oF ar CAN RC RE BE AERE E OO DO ODOUOOOOOO 99990900000000000e4
52. BOTTOM VIEW D1 CCESSCCCESSOCEESO o o o o o o o o o 84 99 20 5 53 el 18 16 14 1e 10 19 17 15 13 11 9 fc CAWVZZE PAC ToAAMSOD TOP VIEW in D FIN 1 Xd cups
53. Bank Pin Description Pin Number GND AN16 N A GND F17 N A GND T17 N A GND AD17 N A GND AF17 N A GND AT17 N A GND J18 N A GND U18 N A GND W18 N A GND AC18 N A GND AE18 N A GND AJ18 N A GND M19 N A GND T19 N A GND V19 N A GND AB19 N A GND AD19 N A GND AF19 N A GND AM19 N A GND E20 N A GND R20 N A GND U20 N A GND AC20 N A GND AE20 N A GND AR20 N A GND H21 N A GND P21 N A GND T21 N A GND V21 N A GND AB21 N A GND AD21 N A GND AH21 N A GND C22 N A GND L22 N A GND R22 N A GND U22 N A GND AA22 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 233 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 234 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices N A GND AC22 N A GND AL22 N A GND AU22 N A GND D23 N A GND P23 N A GND T23 N A GND AD23 N A GND AP23 N A GND G24 N A GND R24 N A GND U24 N A GND AE24 N A GND AG24 N A GND AU24 N A GND K25 N A GND P25 N A GND T25 N A GND 25 GND AD25 N A GND AF25 N A GND AH25 N A GND AK25 N A GND C26 N A GND N26 N A GND R26 N A GND AC26 N A GND AE26 N A GND AG26 N A GND AJ26 N A GND AN26 N A GND F27 N A GND P27 N A GND T27 N A GND AF27 N A GND AH27 N A GND AT27 N A GND 128 w
54. Bank Pin Description Pin Number 7 IO_L22P_7 AP29 7 IO 22 7 AN29 7 IO_L23P_VRN_7 AN27 7 IO L23N VRP 7 AN28 7 IO L24P CC IC 7 AL28 7 IO L24N CC IC 7 AM28 7 IO L1P 7 AT33 7 IO LIN 7 AR33 z IO I2P 7 AJ30 7 IO I2N 7 AK31 7 IO L3P 7 AM30 7 IO L3N 7 AL30 7 IO_L4P_7 AM31 7 IO VREF 7 AL31 7 IO L5P 7 AP24 7 IO L5N 7 AR24 7 IO L6P 7 AP32 7 IO L6N 7 AN32 7 IO_L7P_7 AN30 7 IO_L7N_7 AP31 7 IO L8P CC IC 7 AK29 7 IO L8N CC IC 7 AJ29 7 IO L9P CC IC 7 AT24 7 IO_LIN_CC_LC_7 AT25 7 IO_L10P_7 AW34 7 IO L10N 7 AV34 7 IO_L11P_7 AW30 7 IO L11N 7 AW31 7 IO_L12P_7 AV33 7 IO L12N VREF 7 AU33 7 IO_L13P_7 AP25 7 IO L13N 7 26 7 IO_L14P_7 AT31 7 IO L14N 7 AT30 7 IO L15P 7 AU25 7 IO L15N 7 AV25 7 IO L16P 7 AR31 7 IO L16N 7 AR32 166 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 8 IO_L25P_CC_LC_8 AW12 8 IO L25N CC LIC 8 AV12 8 IO L26P 8 AW9 8 IO 26 8 AV9 8 IO L27P 8 AN14 8 IO 27 8 AM13 8 IO_L28P_8 AT11 8 IO L28N VREF 8 AR11 8 IO L29P 8 AT13 8 IO L29N 8 AR13 8 IO L30P 8 AV10 8 IO L30N 8 AU10 8 IO L31P 8 AW14 8 IO 91 8 AV14 8 IO L32P 8 AW11 8
55. p E O e mueeoerpeeeesmm F oowONJooomngoeeeseooDAX F MMOCHBONCOCO eeeoNoOeeo IOMX H eeNeoee9 u oocomi H J 4 WOW o 9v9 99 2 1 J 5 L XMOOCONOMOCOLMNEY OOBOIAOOCEM L M BB OOOAM I 0OoOoBPNICWIDBNITOOOONOINOS M N BOOLIOOOSROAMLWMLIOOGOORNOOOOMO N P P R R T WAR IOOANMOSNOOOMS T u OOOO u v 2 Vv w 6 w v Y A AA AB AB Ac 9 Ac AD AD AE MABWEEMFETEGO SISISIGM TN SIC 4 AE AF 9 OooEooBlXXBCOCSISIS IB XXII oO oOx AF 423 4 5 8 7 8 g 1044 12 14 16 718 20 22 24 26 Vi IN amp lt 3 m
56. 8 1044124414 FF 16 1517 XCAVFX140 Top View 18 920 22 24 26 28 30 82 84 96 98
57. Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Number FX60 Devices FX40 Devices 5 IO L25N CC LC 5 E28 5 IO L26P 5 E19 5 IO L26N 5 F19 5 IO L27P 5 K24 5 IO L27N 5 L24 5 IO L28P 5 L21 5 IO L28N VREF 5 M22 5 IO L29P 5 L26 5 IO L29N 5 125 5 IO L30P 5 P22 5 IO_L30N_5 N22 5 IO L31P 5 P24 5 IO L31N 5 N24 5 IO 132 5 N23 5 IO L32N 5 M23 6 IO L1P 6 G10 6 IO_LIN_6 H10 6 IO I2P 6 D10 6 IO I2N 6 C10 6 IO L3P 6 F10 6 IO L3N 6 F9 6 IO I4P 6 H9 6 IO VREF 6 19 6 IO L5P 6 F11 6 IO L5N 6 E11 6 IO L6P 6 D9 6 IO L6N 6 E9 6 IO 17 6 D12 6 IO L7N 6 D11 6 IO_L8P_CC_LC_6 C9 6 IO L8N CC LC 6 C8 6 IO L17P 6 J12 6 IO L17N 6 H12 6 IO_L18P_6 E7 6 IO_L18N_6 E6 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 127 Chapter 2 Pinout Tables XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber FX60 Devices FX40 Devices 6 IO_L19P_6 E13 6 IO L19N 6 E12 6 IO L20P 6 K9 6 IO L20N VREF 6 K8 6 IO_L21P_6 E14 6 IO L21N 6 D14 6 IO L22P 6 C7 6 IO L22N 6 D7 6 IO L23P VRN 6 C15 6 IO L23N VRP 6 C14 6 IO L24P CC LC 6 F6 6 IO L24N CC LC 6 G6 6 IO L9P CC LC 6 C13 6 IO L9N CC LC 6 C12 6 IO L10P 6 E8 6 IO L10N 6 F8 6 IO L11P
58. Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 133 Chapter 2 Pinout Tables XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber FX60 Devices FX40 Devices 9 IO L14N 9 H29 9 IO L15P 9 K32 9 IO L15N 9 K31 9 IO L16P 9 M26 9 IO L16N 9 M25 9 IO L25P CC LC 9 P32 9 IO L25N CC IC 9 N32 9 IO L26P 9 R32 9 IO L26N 9 R31 9 IO L27P 9 R29 9 IO L27N 9 P29 9 IO_L28P_9 R28 9 IO L28N VREF 9 R27 9 IO L29P 9 T31 9 IO L29N 9 T30 9 IO L30P 9 129 9 IO L30N 9 T28 9 IO L31P 9 T26 9 IO L31N 9 R26 9 IO L32P 9 U28 9 IO L32N 9 U27 10 IO L17P 10 N5 10 IO L17N 10 N4 10 IO_L18P_10 P5 10 IO L18N 10 P4 10 IO_L19P_10 P10 10 IO_L19N_10 P9 10 IO L20P 10 R4 10 IO_L20N_VREF_10 R3 10 IO L21P 10 T5 10 IO L21N 10 T4 10 IO_L22P_10 P7 10 IO_L22N_10 P6 10 IO L23P VRN 10 p11 10 IO_L23N_VRP_10 R11 134 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in
59. www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 11 IO_L9P_CC_LC_11 AD25 11 IO L9N CC IC 11 AE24 11 IO L10P 11 AE28 11 IO L10N 11 AE29 11 IO 11 AL34 11 IO L1IN 11 AK34 11 IO L12P 11 AP39 11 IO L12N VREF 11 AN39 11 IO L13P 11 AF28 11 IO L13N 11 AF29 11 IO L14P 11 AN37 11 IO 11 AN38 11 IO L15P 11 AH30 11 IO L15N 11 AG30 11 IO L16P 11 AK33 11 IO L16N 11 AJ32 11 IO L25P CC IC 11 AU35 11 IO L25N CC IC 11 AU36 11 IO L26P 11 AM33 11 IO L26N 11 AL33 11 IO L27P 11 AT34 11 IO L27N 11 AT35 11 IO L28P 11 AT36 11 IO L28N VREF 11 AR36 11 IO L29P 11 AW36 11 IO L29N 11 AW37 11 IO L30P 11 AV37 11 IO L30N 11 AU37 11 IO L31P 11 AW35 11 IO L31N 11 AV35 11 IO L32P 11 AR34 11 IO L32N 11 AP34 12 IO L17P 12 AL6 12 IO L17N 12 AK6 12 IO L18P 12 AN3 12 IO_L18N_12 AN2 12 IO_L19P_12 AH10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 173 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued
60. d LID UUOUUUUUUUUUU Poole MICIA B deee MIC SOLDER BALLS MILLIMETERS MIN NOM MAX swe 30 0 40 0 50 0 60 i uda Ries 8 40 D E 27 00 BASIC DYE1 25 00 REF e 1 00 BASIC b 0 60 0 70 aaa 0 20 1 ALL DIMENSIONS AND TOLERANCES CONFORM ees 0 35 TO ANSI Y14 5M 1994 c 0 30 2 SYMBOL M IS THE BALL MATRIX SIZE 7 040 CONFORMS TO JEDEC MS 034 AAI 1 DEPOPULATED M 96 8 e Ol e ccc ddd eee Que Figure 4 3 FF672 Flip Chip Fine Pitch BGA Package Specifications 272 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 Summary W 5 TOP V H XWVMW 00 v 2 ui Ddod MICA B le eee MIC SOLDER BALLS 24 00 MAX d LID Ju 1 LD a W BOTTOM VI FF676 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch XILINX 273 BALL MATRIX SIZ JEDEC MS 034 AAL 1 ALL DIMENSIONS AND TOLERANCES CONFORM
61. 104 AB39 NC N A RXNPADA 104 AA39 NC N A AVCCAUXMGT 104 AH38 NC N A AVCCAUXTX 104 AE38 NC Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 223 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 104 AC38 NC N A TXPPADA_104 AC39 NC N A 104 AD39 NC N A VTTXB_104 AF38 NC N A TXPPADB_104 AE39 NC N A TXNPADB_104 AF39 NC N A AVCCAUXRXB_104 AJ38 NC N A RXPPADB_104 AH39 NC N A VTRXB_104 AG39 NC N A RXNPADB 104 AJ39 NC N A AVCCAUXRXA 105 AM38 N A RXPPADA 105 AL39 N A 105 AN39 N A RXNPADA_105 AM39 N A AVCCAUXMGT_105 AV37 N A AVCCAUXTX_105 AT38 N A VTTXA_105 AP38 N A TXPPADA_105 AP39 N A TXNPADA_105 AR39 N A VTTXB_105 AU38 N A TXPPADB_105 AT39 N A TXNPADB_105 AU39 N A AVCCAUXRXB_105 AV36 N A RXPPADB_105 AW37 N A VTRXB 105 AV38 N A RXNPADB 105 AW36 N A MGTCLK P 105 AW34 N A MGTCLK_N_105 AW33 N A RTERM_105 AV34 N A MGTVREF_105 AV32 N A AVCCAUXRXA_106 AV30 N A RXPPADA_ 106 AW31 N A VTRXA_106 AW29 N A RXNPADA_106 AW30 224 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Pa
62. 113 A7 N A RXNPADA 113 A8 N A AVCCAUXMGT_113 C2 N A AVCCAUXTX_113 B4 N A 113 B6 N A TXPPADA_113 A6 N A TXNPADA_ 113 A5 N A VTTXB 113 B3 N A TXPPADB 113 A4 N A TXNPADB_113 A3 N A AVCCAUXRXB_113 D2 N A RXPPADB_113 C1 N A VTRXB 113 B2 N A RXNPADB 115 D1 N A MGTCLK_P_113 F1 N A MGTCLK N 113 G1 N A AVCCAUXRXA_114 B18 N A RXPPADA 114 A19 N A VTRXA 114 A17 N A RXNPADA 114 A18 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 227 Chapter 2 Pinout Tables 228 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices N A AVCCAUXMGT_114 B11 N A AVCCAUXIX 114 B14 N A VTTXA 114 B16 N A TXPPADA 114 A16 N A TXNPADA 114 A15 N A VTTXB 114 B13 N A TXPPADB 114 A14 N A TXNPADB 114 A13 N A AVCCAUXRXB 114 B10 N A RXPPADB 114 A11 N A VTRXB 114 A12 N A RXNPADB 114 A10 N A GNDA 101 B20 N A GNDA 101 B21 N A GNDA 101 B23 N A GNDA 101 B25 N A GNDA 101 B28 N A GNDA 102 B31 N A GNDA 102 B33 N A GNDA 102 B35 N A GNDA 102 A38 N A GNDA 102 E38 N A GNDA 102 F38 N A GNDA 102 G38 N A GNDA 102 B39 N A GNDA 102 E39 N A GNDA 102 H39 N A GNDA 102 H38 N A 1053 138 GNDA_103 L38 N A GNDA_103 N38 N A GNDA_103 T38 N A GNDA_103 W38 N A GNDA_104 Y38 NC N A GND
63. 9 K L MY 4 L M BENOOCOCMOINMMBINC 2 On nin Ofn M N 6 TIniiniin 4 TwB Tinjiniinjniin n O OO Olnjin N P MNOOMNIINAIN njnjni wBOjLdIniniininjnjinj Lg Onin P R INinONCn liniin jJ Ug lO di TN J OOw OPJn n R T ni niGCo9 Oud L Ta OO M AM IOOaOoOOOnlInIn T nini J1OOOONOKITIWET9cc cOSOOOCRMITOIn n u v 160 e ya eM IL OO OO n n v w nin OOOuM Jooooenmee ever uoooowyooMe w v ninlOLIOOOORNIOOCQOOLIOOO RIOMOOLIES Y AA n nlo OONIOOOOLICe oQOoSNOOOOLIOOONMV AA AB in nlNe9OOOLIOOOQRNOOOOLIOOOOBRIOI N4 AB Ac OC ODCLIGOOOSIOOO0L Ac AD OOOLIG OOBNOOOOLIOOBR S AD AE MIABWEEMEBTEG QinininiGEIMITEN 3 mill AF 9 oo0kooBMXXBIBCOOChninnilalBlIXI S AF 1 2 3 4 5 6 7 8 9 1944 124314 4516 4718 192054 2299249526 User I O Pins Dedicated Pins Other Pins O IO LXXY 4 Z ADC S SM GND E AVCCAUXRXA Multi Function Pins C CCLK TCK GNDA J AVCCAUXRXB amp ADC1 ADC7 B CS B TDI R RSVD L AVCCAUXTX DO D31 N D IN O TDO VBATT AVCCAUXMGT O cc D DONE M TMS 4 VCCAUX V VTRXA Gc Al DOUT BUSY J TDP W VCCINT VTTXA m H HSWAPEN L N VCCO lt VTRXB 6 sm1 sm7 Y INIT n NO CONNECT 5 VTTXB VREF 21111101 M2 M1 MO X MGTCLK VRN P PROG B G MGTVREF U RDWR B eo 0 OF ODO Notes 1 SM and ADC functio
64. AK AL AL AM OBIOLIOOOORIOOOOLISISIS OOOOLIe 6 0OO0O00b5lO AM AN BEE INCNEENM UH NEUu3NiuH HNu NEtHNCcENUNmEE AN AP BXXE9VO O oOoso oNMoosudoocoVviesBXXEOooN S P 125455978910 12 414 16 2184 20 22 24 26 28 30 132 34 User I O Pins Dedicated Pins Other Pins O IO LXXY Z ADC 5 SM GND E AVCCAUXRXA RXNPADA Multi Function Pins C CCLK K TCK GNDA 3 AVCCAUXRXB 5 RXPPADA amp ADCi ADC7 B CS B TDI RI RSVD lu AVCCAUXTX TXPPADA DO D31 Ni D IN O TDO VBATT m AVCCAUXMGT TXNPADA cc D DONE M TMS 4 VCCAUX V VTRXA RXNPADB NGC DOUT BUSY J TDP W VCCINT A VTTXA dod H HSWAPEN L TDN VCCO VTRXB lt gt TXPPADB 97 Y INIT n NO CONNECT VTTXB TXNPADB 69 VREF 2 1 0 M2 M1 MO X MGTCLK VRN P PROG B Gl MGTVREF U RDWR B Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use 075 06 050108 Figure 3 19 FF1152 Flip Chip Fine Pitch BGA Pinout Diagram FX100 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 261 Chapter 3 Pinout Diagrams XILINX FF1152 Color Coded SelectlO and Bank Information Z camvz Ermrxerommoou FF1152 Top View
65. VREFN_SM 2 AV19 N A VREFP_SM 2 AV20 N A AVDD SM O AW21 N A VN_SM AW19 N A VP_SM 2 AW20 N A AVSS_SM AV18 N A VREEN ADC B20 VREFP_ADC B21 N A AVDD ADC B22 N A VN ADC A20 N A VP ADC A21 AVSS_ADC A19 N A GND B1 N A GND H1 N A GND GND AHI N A GND AVI N A GND A2 N A GND L2 N A GND AA2 N A GND AL2 N A GND AW2 N A GND D3 N A GND P3 186 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A GND AD3 N A GND AP3 N A GND G4 N A GND U4 N A GND AG4 N A GND AU4 N A GND K5 N A GND Y5 N A GND AK5 N A GND C6 N A GND N6 N A GND AC6 N A GND AN6 N A GND F7 N A GND TZ N A GND AF7 N A GND AT7 N A GND J8 N A GND W8 N A GND GND AW8 N A GND B9 N A GND M9 N A GND AB9 N A GND GND E10 N A GND R10 N A GND AE10 N A GND AR10 N A GND H11 N A GND V11 N A GND AH11 N A GND AV11 N A GND A12 N A GND L12 N A GND AA12 N A GND AG12 N A GND AL12 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 187 UG075 v3 3 September 19 2008 Chapter 2 Pinou
66. 282 Support for Compact Thermal Models 283 Referentes ia weds deco a WX A 6 a Ra wi ER GRO RR E WC o Cans 284 Chapter 6 Package Marking Virtex 4 Device Package 285 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Preface About This Guide This guide describes Virtex 4 device pinouts and package specifications it also includes pinout diagrams and thermal data Organization of This Guide This document is comprised of the following chapters Chapter 1 Packaging Overview Provides an introduction to the Virtex 4 family with a summary of maximum I Os available in each device package combination Also includes table of pin definitions Chapter 2 Pinout Tables Provides pinout information for all Virtex 4 devices and packages Chapter 3 Pinout Diagrams Provides pinout diagrams for all Virtex 4 package device combinations Chapter 4 Mechanical Drawings Provides mechanical drawings of all Virtex 4 FPGA packages Chapter 5 Thermal Specifications Provides thermal data associated with Virtex 4 FPGA packages Discusses power management strategy and thermal management options for Virtex 4 FPGAs Chapter 6 Package Marking Defines the markings on Virtex 4 FPGA packages Related Documentation The following documents
67. A ts o o PPP W cC d279ZXr 4cr 0nmUOu oo oo o o 0000 ooo Sos oooo oooo ooo oo lt Y a METAL HEAT SINK SEATING PLANE E E WOO UVVUUUVV vuU E Oe Ut c oaa C add C A B Preece MIC SOLDER BALLS 5 t MILLIMETERS N L MIN NUM MAX E A 3 90 3 40 0 40 0 50 0 60 Ae xe 9 80 D E 40 00 BASIC Di E1 38 00 RE NOTES e 00 BASIC gb 0 50 0 60 0 70 1 ALL DIMENSIONS AND TOLERANCES CONFORM aaal x 0 20 TO ASME Y14 5M 1994 ig ice Ba 2 SYMBOL M IS THE PIN MATRIX SIZE ddd me Be 0 25 eee xe 010 3 CONFORMS TO JEDEC MS 034 AAU 1 DEPOPULATED M 39 8 Figure 4 8 FF1517 Flip Chip Fine Pitch BGA Package Specifications Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 27
68. XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued FF668 Flip Chip Fine Pitch BGA Package Bank Pin Description Pin Number LX15 e I GND AD24 N A GND A25 N A GND B25 N A GND AE25 N A GND AF25 N A GND B26 N A GND N26 N A GND AE26 N A VCCAUX M9 N A VCCAUX N9 N A VCCAUX po N A VCCAUX W10 N A VCCAUX H11 N A VCCAUX W11 N A VCCAUX J12 N A VCCAUX V15 N A VCCAUX H16 N A VCCAUX W16 N A VCCAUX H17 N A VCCAUX N18 N A VCCAUX P18 N A VCCAUX R18 N A VCCINT K9 N A VCCINT L9 N A VCCINT T9 N A VCCINT U9 N A VCCINT J10 N A VCCINT K10 N A VCCINT L10 N A VCCINT T10 N A VCCINT U10 N A VCCINT V10 N A VCCINT J11 N A VCCINT L11 N A VCCINT T11 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 49 Chapter 2 Pinout Tables 50 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices N A VCCINT V11 N A VCCINT M12 N A VCCINT R12 N A VCCINT M15 N A VCCINT R15 N A VCCINT J16 N A VCCINT L16 N A VCCINT T16 N A VCCINT V16 N A VCCINT JA7 N A VCCINT K17 N A
69. 1234p 678 1249 1455 1857 185 9205 19 95 08 A 6 6 6 6 6161616 5 5 5 5185 515 5 5 6 6 6 6 6 6 6 6 6 5 55 5 5 55 5 5 5 161666 616 66 6 515155 515155 5 D 10 6 616 6 6 6 6 6 5 515155 51555 E 10 10 6 6 6 6 6 66 55 55155 5 5 F 10161616 6 6 6 5 5 5 5 5 55 G 110 10 6 6 6 6 6 6 5 515155 9199 H 0 1006 6 6 6 5 5 99819 9 J 10 10 6 6 6 6 5 5 9 9 99 K 10 10 10 1010 6 6 5 5gN9 9 9 91 9 L 1010110110 10 6 5 9 9 9 M 10 10 1011010110 EOS 99 N 0 10 10 10 10 10 9 9 9 9 9 P J10 10 10 10 10 a9 9819 99 R 10 10 10 19 10 10 99 99 T 1010 10 8 79 919 919 U M0 10 10 10 10 8 8 7 9 9 Suse V 0 10 10 10 10 8 8 TT 9 9 W 110 10 10 10 8 8 T T7 T T 1911919 Y 10 10 10 8 8 8 8 8 T T ap pp 9 9 AA 8 8 8 8 8 8 8 PARENT LAE 8 8 8 8 8 8 8 8 7 7 7 7 7 7 99 8 8 8 8 8 8 8 8 1 v B AD 8 8 8 8 8 8 8 8 AE 8 8 8 8 8 8 8 8 8 8 7t pe te pe 8 8 8 8 8 8 8 8 7 1 Js Je oe 1234p y Bg 10 18 0066 18 90 80 04 06 ug075 10 color2 121504 Figure 3 13 FF676 Color Coded SelectlO and Bank Information z cdmuzzraAc crommoour Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 255 Chapter 3 Pinout Diagrams XILINX FF1148 Package Pinout Diagram LX40 LX60 and SX55 256 FF1148 XC4VLX40 XC4VLX60 and XC4VSX55 Top View
70. 8 X P Y Ns 27 84 00 MAX A LID ccc C P and SEATING PLANE _ A t OF HUUUUUUUUUUUUUUUUUUUU ERE aaalC i eH LL I Oca B 2eee MIC 5 SOLDER BALLS M MILLIMETERS N B T L MIN NOM MAX E A 265 2 85 0 40 0 50 0 60 Ae 105 195 145 D E 27 00 BASIC D E 25 00 REF e 1 00 BASIC NOTES 9b 0 50 060 0 70 aaa e 0 20 1 ALL DIMENSIONS AND TOLERANCES CONFORM eee ama oe 155 TO ANSI Y14 5M 1994 ddd lt 0 25 2 SYMBOL M IS THE BALL MATRIX SIZE eee ee 7 010 3 CONFORMS TO JEDEC MS 034 AAL 1 DEPOPULATED M 26 8 Figure 4 2 FF668 Flip Chip Fine Pitch BGA Package Specifications Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 271 UG075 v3 3 September 19 2008 Chapter 4 Mechanical Drawings XILINX FF672 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch BOTTOM VIEW TOP VIEW A020 do Di Fr D gt PIN 1 LD 4 16552455225 20 518 71 515 5 124 109 85 65 1521 A ipoosendsasauecosonaoancs N C gt
71. 8 8 8 8 68 7 n ililia AK 14 14 1242 12 8 8 s8 8 8 7 z Izah nu AL 1211212112 12 8 8 8 j e a E AA 41 14 14 AM 12 12 12 12 12 8 18 8 z vz z n ilil AN 12 12 12 8 8 8 8 8 8 8 z 7 z z n fat AP 12 2 0320 8 8 8 88 8 12 12 12181918 8 8 8 8 AF AT 12 12 1212 8 8 8 8 8 8 a AU 1242 8 8 8 8 8 8 AE AW 42a teh 7 Fg Mig tig iz grat ag og a7 31 3233349536373839 ug075_08 color2_01107 Figure 3 25 FF1517 Color Coded SelectlO and Bank Information lt S lt CHADVVUZESETACIOMmMOIOVS Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 267 Chapter 3 Pinout Diagrams XILINX 268 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Chapter 4 Mechanical Drawings Summary This chapter provides mechanical drawings of the following Virtex 4 FPGA packages SF363 Flip Chip Fine Pitch BGA Package Specifications 0 80 mm pitch page 270 e FF668 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch page 271 e FF672 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch page 272 FF676 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch page 273 e FF1148 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch page 274 e FF1152 Flip Chip Fi
72. ADCA 5 C24 5 IO L5N ADCA 5 D24 5 IO 6 ADC3 5 C23 5 IO L6N ADC3 5 C22 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 125 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 126 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Number FX60 Devices FX40 Devices 5 IO_L7P_ADC2_5 J25 5 IO_L7N_ADC2_5 H25 5 IO L8P CC ADC1 LC 5 G22 5 IO CC ADC1 LC 5 H22 5 IO L17P 5 K26 5 IO L17N 5 126 5 IO L18P 5 D21 5 IO L18N 5 E21 5 IO L19P 5 E27 5 IO L19N 5 D27 5 IO L20P 5 K23 5 IO L20N VREF 5 L23 5 IO L21P 5 C28 5 IO 121 5 C27 5 IO L22P 5 H20 5 IO L22N 5 J20 5 IO L23P VRN 5 G28 5 IO L23N VRP 5 G27 5 IO L24P CC LC 5 F20 5 IO L24N CC LC 5 G20 5 IO L9P CC LC 5 G25 5 IO L9N CC LC 5 F25 5 IO L10P 5 D22 5 IO L10N 5 E22 5 IO L11P 5 D25 5 IO L11N 5 C25 5 IO L12P 5 122 5 IO_L12N_VREF_5 K22 5 IO L13P 5 G26 5 IO L13N 5 F26 5 IO L14P 5 121 5 IO_L14N_5 21 5 IO L15P 5 E26 5 IO L15N 5 D26 5 IO L16P 5 F21 5 IO L16N 5 G21 5 IO L25P CC LC 5 F28 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package
73. ERS mAnz M MAX 3 20 3 40 0 50 0 60 alt Ke 2 80 35 00 BASIC 33 00 EF 00 BASIC oO Ul e 0 60 0 70 aaa Wwe 0 20 Cec ne 2 0 35 dod Wwe 0 30 j eee QU Ke 0 10 34 2 UT fo lL dddd c deeeM C SOLDER BALLS NOTES ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14 5M 1994 SYMBOL IS THE BALL MATRIX SIZE CONFORMS TO JEDEC MS 034 AAR 1 DEPOPULATED Figure 4 5 FF1148 Flip Chip Fine Pitch BGA Package Specifications 274 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Summary FF1152 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 0 20 BOTTOM VIEW 145532 30 28 26 24 22 20 8 18 14 12 11g 8 7 e 5 4 3 2 1 0000000000000000 000000000000000 ooooooooo0o0000000
74. TO ANSI Y14 5M 1994 2 SYMBOL M IS TH Si 3 CONFORMS j NOT 0 3 0 0 60 1 00 0 70 0 20 0 25 0 25 0 10 F 0 60 26 Figure 4 4 FF676 Flip Chip Fine Pitch BGA Package Specifications 27 00 BASIC 1 00 BASIC 5 25 00 R Ais 0 40 0 65 0 50 Ae Ke Ae Ke Ae Ke Re Ke Y NI me ul P 5 T bci o u LJ e lt MOOWLOT IX I SZOeHD gt F gt fVLAAE T T 1 199900000000000000000000006 a 00000000000000000000000000 5 o 7510000000000000 0000000000000 1 U 2 ee 0 o 0O0000000000000000000000000 U n 00000000000000000000000000 x 00000000000000000000000000 q U x 5 0000000000000 0000000000000 1 LJ Y a 00000000000000000000000000 z j x 1 0 4 g 310000000000000 0000000000000 A SF Toooo0o000000000000000000000 i 9 5 gt z 2 00000000000000000000000000 210000000000000 0000000000000 Z 2 00000000000000000000000000 x 2 ooo00000000000000000000000 ul 8 00000000000000000000000000 o Zz 9
75. Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 23 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 a ies 5 IO_L16P_5 F19 5 IO L16N 5 G19 9 IO L25P CC LC 5 M17 5 IO L25N CC LC 5 M18 5 IO L26P 5 M20 5 IO L26N 5 L20 5 IO L27P 5 M15 5 IO 127 5 M16 5 IO L28P 5 M19 5 IO L28N VREF 5 L19 5 IO L29P 5 N16 5 IO L29N 5 N17 5 IO L30P 5 N18 5 IO L30N 5 N19 5 IO L31P 5 P16 5 IO L31N 5 P17 5 IO L32P 5 P19 5 IO_L32N_5 P20 6 IO L1P 6 B6 6 IO LIN 6 A6 6 1 12 6 A5 6 1 6 B5 6 IO L3P 6 C6 6 IO L3N 6 C5 6 IO 6 B4 6 IO VREF 6 C4 6 IO L5P 6 D5 6 IO L5N 6 E5 6 IO L6P 6 A3 6 IO L6N 6 B3 6 IO 7 6 D4 6 IO_L7N_6 D3 6 IO L8P CC LC 6 B2 6 IO L8N CC LC 6 C1 24 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX SF363 Flip Chip Fine Pitch BGA Package Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 nas 6 IO L17P 6 J4 6 IO_L17N_6 19 6 IO L18P 6 H1 6 IO_L18N_6 G1 6 IO_L19P_6 J6 6 I
76. XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number GND G23 N A GND U23 N A GND K24 N A GND Y24 N A GND C25 N A GND N25 N A GND AC25 N A GND F26 N A GND T26 N A GND AF26 N A VCCAUX J4 N A VCCAUX T5 N A VCCAUX W6 N A VCCAUX H7 N A VCCAUX VCCAUX po N A VCCAUX G12 N A VCCAUX N12 N A VCCAUX P15 N A VCCAUX N18 N A VCCAUX F19 N A VCCAUX AF19 N A VCCAUX W20 N A VCCAUX H21 N A VCCAUX L22 N A VCCAUX V23 N A VCCINT K7 N A VCCINT T7 N A VCCINT L8 N A VCCINT N8 N A VCCINT R8 N A VCCINT VCCINT F9 N A VCCINT M9 N A VCCINT T9 N A VCCINT V9 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 87 Chapter 2 Pinout Tables 88 XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee N A VCCINT G10 N A VCCINT J10 N A VCCINT L10 N A VCCINT N10 N A VCCINT R10 N A VCCINT M11 N A VCCINT P11 N A VCCINT AB11 N A VCCINT L12 N A VCCINT R12 N A VCCINT P13 N A VCCINT T13 N A VCCINT L14 N A VCCINT N14 N A VCCINT M15 N A VCCINT T15 N A
77. 12 12 12 12 12 2 2 20 2 21212 14 1111 11 11 12 1211211212 2l 28022022 12 2 11 11 11 11 11 12112112 POA AA 11 11 11 11 2 2 21212 11 11 222 2 2 11 11 11 12345597598 910 4124 414151647218192051225424 526 72859304192 459445364738 49 Figure 3 22 FF1513 Color Coded SelectlO and Bank Information z cdmuzzrac crommoou ug075 07 color2 122104 264 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Package Pinout Diagram FX100 FF1517 Package Pinout Diagram FX100 FF1517 XC4VFX100 Top View
78. 164 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 6 IO_L27N_6 B6 6 IO_L28P_6 J10 6 IO_L28N_VREF_6 J9 6 IO_L29P_6 F16 6 IO_L29N_6 F15 6 IO L30P 6 H9 6 IO L30N 6 G8 6 IO L31P 6 Kil 6 IO L31N 6 L11 6 IO L32P 6 L10 6 IO L32N 6 K9 7 IO L25P CC SM7 IC 7 AP27 7 IO L25N CC SM7 IC 7 AR27 7 IO L26P SM6 7 AV30 7 IO L26N 59 6 7 AU30 7 IO L27P SM5 7 AR26 7 IO L27N 5 7 26 7 IO_L28P_7 AW29 7 IO L28N VREF 7 AV29 7 IO L29P SMA 7 AV27 7 IO L29N SMA 7 AW27 7 IO L30P SM3 7 AT29 7 IO L30N SM3 7 AR29 7 IO L31P SM2 7 AU26 7 IO L31N SM2 7 AU27 7 IO L32P 5 7 AT28 7 IO L32N 7 AR28 7 IO_L17P_7 AL26 7 IO L17N 7 AM27 7 IO L18P 7 AU31 7 IO L18N 7 AU32 7 IO_L19P_7 AV28 7 IO L19N 7 AU28 7 IO L20P 7 AW32 7 IO L20N VREF 7 AV32 7 IO L21P 7 AW25 7 IO L21N 7 AW26 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 165 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued
79. 2 IO_L1P_D15_CC_LC_2 U16 2 IO LIN D14 CC_LC_2 V16 2 IO L2P D13 IC 2 Yn 2 IO L2N D12 IC 2 W11 2 IO_L3P_D11_LC_2 W16 2 IO_L3N_D10_LC_2 W15 2 IO_L4P_D9_LC_2 V12 2 IO_L4N_D8_VREF_LC_2 V11 2 IO_L5P_D7_LC_2 U15 2 IO_L5N_D6_LC_2 U14 2 IO_L6P_D5_LC_2 Y13 2 IO_L6N_D4_LC_2 Y12 2 IO L7P D3 1C 2 V14 2 IO L7N D2 IC 2 W14 2 IO_L8P_D1_LC_2 W13 2 IO_L8N_D0_LC_2 V13 3 IO GC CC IC 3 A14 3 IO LIN GC CC IC 3 B14 3 IO L2P GC VRN LC 3 C13 3 IO L2N GC VRP LC 3 D13 3 IO L3P GC LC 3 D14 3 IO L3N GC LC 3 C14 3 IO I4P GC LC 3 E13 3 IO GC VREF LC 3 F13 3 IO L5P GC LC 3 E15 3 IO L5N GC IC 3 D15 3 IO L6P GC LC 3 B12 3 IO GC LC 3 C12 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 71 Chapter 2 Pinout Tables XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee 3 IO_L7P_GC_LC_3 F15 3 IO L7N GC LC 3 F14 3 IO L8P GC LC 3 A13 3 IO L8N GC LC 3 A12 4 IO L1P GC IC 4 AAI4 4 IO_LIN_GC_LC 4 AA13 4 IO L2P GC IC 4 2 4 IO 2 GC IC 4 AA12 4 IO L3P GC LC 4 4 4 IO L3N GC LC 4 AC14 4 IO I4P GC LC 4 AC13 4 IO LAN GC VREF LC 4 AC12 4 IO L5P GC LC 4 AD15 4 IO L5N GC IC 4 AD14 4 IO L6P GC LC 4 AD13 4 IO 6 GC LC 4 AE13 4 IO_L7P_GC_VRN_LC_4 AE15 4 IO_L7N_GC_VRP_LC_4 AF15 4 IO_L8
80. 3 IO GC VREF IC 3 F20 3 IO L5P GC LC 3 L21 3 IO L5N GC LC 3 L20 3 IO LoP GC LC 3 F19 3 IO L6N GC LC 3 F18 3 IO L7P GC LC 3 K21 3 IO L7N GC IC 3 121 3 IO L8P GC LC 3 G18 3 IO GC LC 3 H18 4 IO GC LC 4 22 4 IO_LIN_GC_LC_4 AP21 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices 4 IO_L2P_GC_LC_4 AN20 4 IO_L2N_GC_LC_4 AP20 4 IO L3P GC LC 4 AM22 4 IO L3N GC ILC 4 AN22 4 IO L4P GC LC 4 AL20 4 IO GC VREF LC 4 AL19 4 IO L5P GC LC 4 AK21 4 IO L5N GC LC 4 AL21 4 IO LoP GC LC 4 AK19 4 IO L6N GC LC 4 AJ19 4 IO L7P GC VRN IC 4 AJ21 4 IO GC VRP LC 4 AJ20 4 IO L8P GC CC IC 4 AM21 4 IO L8N GC CC IC 4 AM20 5 IO L1P ADC7 5 C28 5 IO L1N ADC7 5 C27 5 IO 2 ADC6 5 K28 5 IO ADC6 5 L28 5 IO_L3P_ADC5_5 K29 5 IO_L3N_ADC5_5 L29 5 IO I4P 5 G28 5 IO VREF 5 H28 5 IO L5P ADCA 5 129 5 IO_L5N_ADC4_5 H29 5 IO_L6P_ADC3_5 E28 5 IO_L6N_ADC3_5 F28 5 IO L7P ADC2 5 E29 5 IO ADC2 5 F29 5 IO L8P CC ADCI1 LC 5 J27 5 IO L8N CC ADCI LC 5 K27 5 IO L17P 5 G31 5 IO L17N 5 F31 5 IO L18P 5 D26 5 IO L18N 5 E26 5 IO L
81. 6 I Ocon ninin nin l T U ni n Jiniin in CO NLO IKILLUWIE 9 9 69 S 69 SOM jn Tn Tin n u v nl n n n n n OGoWMI E 169 9 9 9 SI O 69 OL TO O ad In Tn n v nininiininiad Tw OO mI deor IOO0aOohloiimnin w v nininr 1OO OON ec ore e Oo00O00L nin v AA LIOOOONOMOCOLIC OOFDIe OO IOOO nlnl aa AB AB AC Ac AD Derieeoo IDOO0 Ap AE OOORJIOOOOLIOOOQqCHNIGInInInI 1 OO0O05IOO AE AF NOOOOLJOOOONO OOGnInIn inid e O0O0O0OL 1 2 3 4 5 6 7 8 194412431445 16 4718 19205 2242349626 User I O Pins O 10_LXXY_ Z PROG_B GND Multi Function Pins C CCLK PWRDWN B RSVD amp ADC1 ADC7 B CS B RDWR B VBATT 9 DO D31 N D IN SM VCCAUX e cc D DONE TCK VCCINT N GC A DOUT BUSY TDI VCCO D P GC H HSWAPEN TDO NO CONNECT 6 LC INIT TMS SM1 SM7 0 M2 M1 MO TDP VREF TDN VRN VRP Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use UG075 10a 050108 Figure 83 11 FF676 Flip Chip Fine Pitch BGA Pinout Diagram LX15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 253 UG075 v3 3 September 19 2008 Chapter 3 Pinout Diagrams FF676 Package Pinout Diagram LX25 254
82. N A GND AL17 N A GND D18 N A GND P18 N A GND AD18 N A GND A19 N A GND G19 N A GND U19 N A GND AA19 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 117 Chapter 2 Pinout Tables 118 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SXS5 Devices N A GND AG19 N A GND K20 N A GND T20 N A GND Y20 N A GND AB20 N A GND AK20 N A GND C21 N A GND L21 N A GND N21 N A GND AC21 N A GND AN21 N A GND F22 N A GND K22 N A GND M22 N A GND 22 GND Y22 N A GND AD22 N A GND AF22 N A GND 125 GND L23 N A GND W23 N A GND AC23 N A GND AE23 N A GND AJ23 N A GND B24 N A GND M24 N A GND AB24 N A GND AD24 N A GND AM24 N A GND E25 N A GND R25 N A GND AE25 N A GND H26 N A GND V26 N A GND AH26 N A GND A27 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin No Connects in LX40 Number LX60 and
83. N A VCCINT AF13 N A VCCINT AH13 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SXS5 Devices N A VCCINT N14 N A VCCINT R14 N A VCCINT W14 N A VCCINT AC14 N A VCCINT AE14 N A VCCINT M15 N A VCCINT P15 N A VCCINT T15 N A VCCINT V15 N A VCCINT AD15 N A VCCINT AH15 N A VCCINT J16 N A VCCINT R16 N A VCCINT W16 N A VCCINT AA16 N A VCCINT P17 N A VCCINT V17 N A VCCINT U18 N A VCCINT AA18 N A VCCINT AC18 N A VCCINT P19 N A VCCINT T19 N A VCCINT Y19 N A VCCINT AF19 N A VCCINT G20 N A VCCINT L20 N A VCCINT U20 N A VCCINT AA20 N A VCCINT AC20 N A VCCINT 21 VCCINT M21 N A VCCINT T21 N A VCCINT Y21 N A VCCINT AB21 N A VCCINT G22 N A VCCINT 122 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 121 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 122 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin No Connects in LX40 Number LX60 and SX55 Devi
84. Number FX60 Devices FX40 Devices 10 IO L24P CC LC 10 T6 10 IO L24N 10 R6 10 IO 10 L9 10 IO LIN 10 L8 10 IO L2P 10 H5 10 IO L2N 10 H4 10 IO L3P 10 L10 10 IO L3N 10 M10 10 IO 10 M8 10 IO LAN VREF 10 M7 10 IO L5P 10 F5 10 IO L5N 10 G5 10 IO L6P 10 G3 10 IO L6N 10 H3 10 IO L7P 10 F4 10 IO_L7N_10 F3 10 IO_L8P_CC_LC_10 J5 10 IO L8N CC LC 10 J4 10 IO L9P CC IC 10 J6 10 IO L9N CC LC 10 K6 10 IO L10P 10 K4 10 IO L10N 10 K3 10 IO 10 N10 10 IO L11N 10 N9 10 IO L12P 10 N8 10 IO L12N VREF 10 N7 10 IO L13P 10 L6 10 IO L13N 10 L5 10 IO L14P 10 14 10 IO L14N 10 L3 10 IO L15P 10 M6 10 IO L15N 10 M5 10 IO L16P 10 M3 10 IO L16N 10 N3 10 IO L25P CC LC 10 V5 10 IO L25N CC LC 10 U5 10 IO_L26P_10 U3 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 135 Chapter 2 Pinout Tables 136 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 10 IO L26N 10 T3 10 IO L27P 10 U8 10 IO L27N 10 T8 10 IO L28P 10 R8 10 IO L28N VREF 10 R7 10 IO L29P 10 T9 10 IO L29N 10 R9 10 IO L30P 10 v4 10 IO L30N 10 V3 10 IO L31P 10 T11 10 IO L31N 10 T10 10 IO L32P 10 U7 10 IO L32N 10 U6 1 IO L17P 11 AA26 NC 11 IO L
85. SM GND AVCCAUXRXA Multi Function Pins C CCLK TCK Ml GNDA J AVCCAUXRXB 4 RXPPADA amp ADCi ADC7 B CS B TDI RI RSVD lij AVCCAUXTX TXPPADA 9 DO D31 N D IN OQ TDO VBATT m AVCCAUXMGT TXNPADA Occ D DONE M TMs 4 VCCAUX Vi VTRXA RXNPADB NGC BUSY Y INIT a VTTXA RXPPADB a iu H HSWAPEN J TDP VCCO Kj VTRXB lt gt TXPPADB SM1 SM7 2 0 0 M2 M1 MO L n NOCONNECT VTTXB TXNPADB VREF P PROG B X MGTCLK VRN PWRDWN_B G MGTVREF VRP U RDWR B T RTERM Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use 075 08 050108 Figure 3 24 FF1517 Flip Chip Fine Pitch BGA Composite Pinout Diagram FX140 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Color Coded SelectlO and Bank Information FF1517 Color Coded SelectlO and Bank Information FF1517 Top View
86. T EMOOCOONOOOCOLDnPBAMW BINICBIWEIIWONSOOOOLDIE T u CHONOCOCL t i ludo OLInininiV u v BOCCONI ER OT LT M d P Ini nini n n n A v w KBD Se IgE IU RS IO 1 Ld S IIniniininininininin e w v eHmininjnjnjninj nj 8 5 WAS 5 Ju niininjinininj Y AA eoBininjn n njiinig il ORO KI EMIL JST TS TuS ni nininjiinlb l4 AA AB Main Inininininji4OOCOL 5 4 5 m 4 IInininin nin ni n AB B nininininjinin OCOfMSI jw wf 4 ISON NNNnnn ac AD C9 OOONSIOW IMMO OC 9 nini nin nnllo ap MEMMOMIMNZd NOOCOKOSOGNDOCSSOCOOMMMMEAM AE AF OANMNNiNinOOOUOCODONDOCOLOC O NOCMNNUES AF BNinininininini 1XC9OOORSIO OQ L Io 90e eoOorlnininE e Ac AH dQBinininr 16e oOoOSOOqQDQOLI9cecegemieooereoo ninnES Vi Au AJ QoBInInIn oNOoOoooLeooe5seeeero eee 0Ininn A4 AJ AK EMEN CIninin OOOLIOOOONOGOO roooomsgo oooLnooMe AL AL AM inn OOSIOOCOOLISISIS OOOOLIJe OOSIOOOBP AN BBTIBGIIninin n njn njnj njn njnj njn njnjnjn ninjnG NT NN S mE AN AP Bxxiininj ninjnjnjnjnjnjnjnjnjnjnjnjnjinjinjinjininIIXIXIEl o N AP 1 2 3 4 5 6 7 8 10 215144516 718492054225424 526 28 3041324 34 User Pins Dedicated Pins Other Pins O 1 LXXY Z ADC 5 SM GND E AVCCAUXRXA RXNPADA Multi Function Pins C CCLK K TCK GNDA 3 AVCCAUXRXB 4 RXPPADA amp A
87. 1 IO L19N 11 AC27 1 IO L20P 11 AB25 11 IO L20N VREF 11 AB26 1 IO L21P 11 AG30 11 IO L21N 11 AG31 11 IO L22P 11 AH32 11 1 122 11 AH33 1 IO L23P VRN 11 AC25 1 IO L23N VRP 11 AD26 1 IO L24P CC LC 11 AF29 1 IO_L24N_CC_LC_11 AF30 11 IO_L1P_11 AA28 11 IO_L1N_11 AA29 11 IO 12 11 W24 11 IO_L2N_11 Y24 11 IO_L3P_11 AB30 11 IO L3N 11 AA30 1 14 11 W25 11 IO_L4N_VREF_11 Y26 11 IO L5P 11 AE33 1 IO L5N 11 AE34 11 IO L6P 11 AC32 1 IO L6N 11 AC33 1 IO L7P 11 AC29 1 IO L7N 11 AC30 1 IO_L8P_CC_LC_11 AD34 11 IO_L8N_CC_LC_11 AC34 11 IO_L9P_CC_LC_11 AA25 11 IO L9N CC IC 11 AA26 1 IO L10P 11 AE32 1 IO L10N 11 AD32 11 IO_L11P_11 AC28 11 IO_L11N_11 AB28 11 IO L12P 11 AD30 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 105 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Da connect m 1x0 Number LX60 and SX55 Devices 11 IO_L12N_VREF_11 AD31 11 IO L13P 11 AG32 11 IO L13N 11 AG33 11 IO L14P 11 AF33 11 IO 11 AF34 11 IO L15P 11 AE29 11 IO L15N 11 AD29 11 IO L16P 11 AF31 11 IO L16N 11 AE31 11 IO L25P CC LC 11 AK31 11 IO L25N CC IC 11 AK32 11 IO L26P 11 AK33 11 IO L26N 11 AK34 11 IO 127 11 AM32 11 1 L27N 11
88. 1 VCCO_1 H16 1 VCCO_1 L17 1 VCCO 1 D18 1 VCCO 1 P18 1 VCCO 1 N21 1 VCCO 1 F22 1 VCCO 1 J23 1 VCCO_1 M24 2 VCCO_2 AF22 2 VCCO_2 AT22 2 VCCO_2 AJ23 2 VCCO_2 AM24 2 VCCO_2 AH16 2 VCCO 2 AL17 2 VCCO_2 AP18 2 VCCO_2 AU18 2 VCCO_2 AG19 3 VCCO 3 G19 3 VCCO 3 K20 4 VCCO 4 AK20 4 VCCO 4 AN21 5 VCCO_5 D22 5 VCCO_5 E25 5 VCCO_5 H26 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 219 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 5 VCCO_5 L27 5 VCCO_5 D28 5 VCCO_5 G29 5 VCCO_5 K30 5 VCCO 5 C31 5 VCCO 5 F32 6 VCCO 6 C3 6 VCCO 6 E5 6 VCCO 6 D8 6 VCCO 6 G9 6 VCCO 6 K10 6 VCCO 6 C11 6 VCCO_6 12 6 VCCO_6 JA3 6 VCCO 6 E15 7 VCCO 7 AR25 7 VCCO 7 AL27 7 VCCO 7 AP28 7 VCCO_7 AU29 7 VCCO_7 AK30 7 VCCO_7 AN31 7 VCCO_7 AT32 7 VCCO_7 AR35 7 VCCO_7 AU37 8 VCCO_8 AP8 8 VCCO_8 AU9 8 VCCO_8 AK10 8 VCCO_8 AN11 8 VCCO_8 AT12 8 VCCO_8 AJ13 8 VCCO_8 AM14 8 VCCO_8 AR15 9 VCCO 9 V26 9 VCCO 9 U29 9 VCCO 9 N31 9 VCCO 9 T32 9 VCCO 9 193 220 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continu
89. 11 12112 12 8 8 8 8 8 8 8 8 2 221212 TE 1 111 12 12 12 8 8 8 8 8 8 8 8 2 2 2 AEEA Gi aee te te I Es 12 12 12 12 8 8 8 8 8 8 s THp pat e 12 12 12 8 8 8 8 8 8 T 2 e Le 423 45 8 7 8 g 1044 1245144516 718920 22 245 26 728 430 32 34 ug075 06 color2 011905 Figure 3 20 FF1152 Color Coded SelectlO and Bank Information 262 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Package Pinout Diagram LX100 LX160 and LX200 FF1513 Package Pinout Diagram LX100 LX160 and LX200 FF1513 XC4VLX100 XC4VLX160 and XC4VLX200 Top View 9955959 3233343536373839
90. 13 IO L28N VREF 13 13 IO L29P 13 13 IO L29N 13 13 IO L30P 13 13 IO L30N 13 13 IO L31P 13 13 IO L31N 13 13 IO L32P 13 13 IO L32N 13 14 IO L17P 14 14 IO L17N 14 14 IO L18P 14 14 IO L18N 14 14 IO L19P 14 14 IO L19N 14 14 IO L20P 14 14 IO L20N VREF 14 14 IO L21P 14 14 IO L21N 14 14 IO L22P 14 14 IO L22N 14 14 IO L23P VRN 14 14 IO L23N VRP 14 14 IO L24P CC LC 14 14 IO L24N CC LC 14 14 IO L1P 14 14 IO 14 14 IO L2P 14 14 IO 2 14 14 IO L3P 14 110 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Ne Connects in PRAO Number LX60 and SX55 Devices 14 IO L3N 14 T8 14 IO 14 R7 14 IO LAN VREF 14 R6 14 IO L5P 14 P2 14 IO L5N 14 P1 14 IO_L6P_14 R4 14 IO L6N 14 T4 14 IO L7P 14 R3 14 IO L7N 14 R2 14 IO L8P CC LIC 14 R1 14 IO L8N CC LC 14 T1 14 IO L9P CC LC 14 T6 14 IO L9N CC LC 14 T5 14 IO L10P 14 T3 14 IO L10N 14 U3 14 IO L11P 14 U8 14 IO L11N 14 U7 14 IO L12P 14 U2 14 IO L12N VREF 14 U1 14 IO L13P 14 U12 14 IO L13N 14 U11 14 IO L14P 14 U10 14 IO L14N 14 V10 14 IO L15P 14 U6 14 IO L15N 14 U5 14 IO L16P 14 V3 14 IO L16N 14 V2 14 IO L25P CC LC 14 A
91. 2 5 1 4 7 FX100 35 0 0 1 2 2 9 9 6 0 4 9 4 4 FF1517 FX100 40 0 0 1 2 2 9 5 5 7 4 6 41 FX140 40 0 0 1 2 0 8 6 5 0 4 1 37 280 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Virtex 4 FPGA Power Management Strategy Virtex 4 FPGA Power Management Strategy Xilinx relies on a multi prong approach with regards to the heat dissipating potential of Virtex 4 devices Design and Silicon Significant power reduction in Virtex 4 devices at the 90 nm node is achieved through innovative process and circuit design Transistor leakage current is minimized 50 better than comparable devices by using the power efficient Virtex 4 FPGA architecture Despite these improvements and a lower operating voltage the Virtex 4 devices pack higher gate density and can do more in a shorter time than the previous generation of FPGAs Compared to previous generations the power consumption is lower for the same design same function and gate density in a Virtex 4 FPGA implementation However with the increase in resources associated with higher gate density devices switching at faster rates Xilinx anticipates more work will be done more quickly thus dissipating more power than before Packaging At the package component level Xilinx has selected the more efficient flip chip BGA packages which present a low thermal path to the outside This package incorporates a heat spreader with a thermal
92. 6 6 6 6 6 5 5 5 5 S G H 6 6 6 6 6 6 5 5 5 alele H J 6 6 6 6 5 515 J K 6 6 6 6 6 5 5 ISI SIS K L 8 8 6 6 6 515 5 5 L M 8 6 6 1010 10 9 9 9 5 5 8 8 19 19 10 10 10 9 9 9 9 9 5 5 5 N P 8 8 8 10 10 10 10 10 9 9 9 9 9 7 P R 8 8 10 10 10 9 99 7 R T 8 8 8 8 vy 7 AAR T U 8 8 8 8 8 7 7 7 7 7 U V 8 8 8 8 7 ee bep V Ww 8 8 8 8 8 8 717 Ww 8 8 8 8 8 8 v EE Y AA 8 8 8 8 8 8 8 2 mv v AA AB 8 8 8 8 8 8 7 ENS 8 8 818 8 8 za E EZ gb AC AD 8 8 8 8 8 8 8 7 7 7 7 717 AD AE AE AF AF 4 16 18 20 225 24826 2345678 104412431 15 17 19 21 23 25 1 3 5 7 9 ug075_04 color 2_121504 Figure 3 10 FF672 Color Coded SelectlO and Bank Information 252 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Package Pinout Diagram LX15 FF676 Package Pinout Diagram LX15 FF676 LX15 Top View
93. 6 H3 6 IO L29P 6 G12 6 IO L29N 6 Gil 6 IO L30P 6 K3 6 IO L30N 6 J3 6 IO L31P 6 L10 6 IO L31N 6 L9 6 IO L32P 6 M5 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 6 IO L32N 6 L5 7 IO L25P CC SM7 LC 7 AB24 7 IO L25N CC SM7 LIC 7 AC24 7 IO L26P SM6 7 AB20 7 IO L26N SM6 7 AB19 7 IO 27 SM5 7 W20 7 IO_L27N_SM5_7 W19 7 IO_L28P_7 W18 7 IO L28N VREF 7 V18 7 IO_L29P_SM4_7 AD24 7 IO L29N SMA 7 AD23 7 IO L30P SM3 7 AA20 7 IO SM3 7 AA19 7 IO L31P SM2 7 AC23 7 IO L31N SM2 7 AC22 7 IO L32P SM1 7 AB22 7 IO 5 7 AB21 7 IO L17P 7 V21 7 IO L17N 7 U21 7 IO L18P 7 AC19 7 IO L18N 7 AC18 7 IO L19P 7 AA24 7 IO L19N 7 AA23 7 IO L20P 7 AA18 7 IO L20N VREF 7 Y18 7 IO L21P 7 Y22 7 IO L21N 7 AA22 Z IO L22P 7 AD20 7 IO L22N 7 AD19 7 IO L23P VRN 7 W21 7 IO L23N VRP 7 Y20 7 IO L24P CC LC 7 AC21 7 IO L24N CC IC 7 AD21 7 IO L1P 7 P24 7 IO LIN 7 R23 7 IO L2P 7 AB15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 57 Chapter 2 Pinout Tables 58 XILINX
94. 6 J11 6 IO_LI1N_6 J10 6 IO_L12P_6 G8 6 IO_L12N_VREF_6 H8 6 IO_L13P_6 G12 6 IO_L13N_6 G11 6 IO_L14P_6 J7 6 IO L14N 6 K7 6 IO L15P 6 1 6 IO L15N 6 L11 6 IO_L16P_6 G7 6 IO_L16N_6 H7 6 IO L25P CC LC 6 D16 6 IO L25N CC LC 6 D15 6 IO L26P 6 D6 6 IO L26N 6 C5 6 IO L27P 6 K13 6 IO L27N 6 K12 6 IO L28P 6 D5 6 IO L28N VREF 6 D4 6 IO L29P 6 M13 128 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 6 IO_L29N_6 L13 6 IO_L30P_6 E4 6 IO L30N 6 E3 6 IO L31P 6 M12 6 IO L31N 6 M11 6 IO L32P 6 C4 6 IO_L32N_6 C3 7 IO_L25P_CC_SM7_LC_7 AH27 7 IO L25N CC SM7 LC 7 AJ27 7 IO L26P SM6 7 AL25 7 IO L26N SM6 7 AM25 7 IO 127 SM5 7 AF26 7 IO L27N SM5 7 AG26 7 IO L28P 7 AD24 7 IO L28N VREF 7 AE24 7 IO L29P SMA 7 AG25 7 IO_L29N_SM4_7 AH25 7 IO L30P SM3 7 AL26 7 IO L30N SM3 7 AM26 7 IO L31P SM 7 AF25 7 IO L31N SM2 7 AF24 7 IO L32P SMI1 7 AJ26 7 IO_L32N_SM1_7 AJ25 7 IO L17P 7 AG28 yj IO L17N 7 AG27 7 IO L18P 7 AH23 7 IO L18N 7 AG23 7 IO L19P 7 AE28 7 IO L19N 7 AF28 7 IO L20P 7 AF23 7 IO L20N VREF 7 AE23 7 IO L21P 7 A
95. 7 IO L23P VRN 7 AH23 7 IO L23N VRP 7 AH24 yd IO L24P CC LC 7 AN28 7 IO L24N CC IC 7 AM28 7 IO_L1P_7 AK29 7 IO LIN 7 AJ29 7 IO I2P 7 AF28 7 IO L2N 7 AE27 7 IO L3P 7 AF26 7 IO L3N 7 AE26 7 IO I4P 7 AN32 7 IO LAN VREF 7 AN33 7 IO L5P 7 AK21 7 IO L5N 7 AL21 7 IO L6P 7 AH28 7 IO L6N 7 AH29 7 IO 17 7 AP30 7 IO L7N 7 AN30 7 IO_L8P_CC_LC_7 AG27 7 IO_L8N_CC_LC_7 AG28 7 IO L9P CC LC 7 AM21 7 IO L9N CC LC 7 AM22 7 IO L10P 7 AM30 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Ne ii ERI Number LX60 and SX55 Devices 7 IO L10N 7 AL30 7 IO L11P 7 AP27 7 IO L11N 7 AN27 7 IO L12P 7 AP31 7 IO L12N VREF 7 AP32 7 IO L13P 7 AK22 7 IO L13N 7 AK23 7 IO L14P 7 AL28 7 IO L14N 7 AL29 7 IO L15P 7 AP25 7 IO L15N 7 AP26 7 IO L16P 7 AJ27 7 IO L16N 7 AH27 8 IO L25P CC LC 8 AL11 8 IO L25N CC LC 8 AL10 8 IO L26P 8 8 IO L26N 8 AF11 8 IO_L27P_8 AM12 8 IO L27N 8 AM11 8 IO L28P 8 AL9 8 IO L28N VREF 8 AK9 8 IO L29P 8 AP11 8 IO L29N 8 AP10 8 IO_L30P_8 AH10 8 IO L30N 8 AG10 8 IO_L31P_ AN12 8 IO L31N 8 AP12 8 IO L32P 8 8 IO L32N 8 AN9 8 IO_L17P_8 AH12 8 IO L17N 8
96. 8 IO L17P 8 AD9 8 IO_L17N_8 ADS 8 IO L18P 8 Y3 8 IO L18N 8 WA 8 IO L19P 8 AC9 8 IO L19N 8 AC8 8 IO L20P 8 AAA 8 IO L20N VREF 8 AA3 8 IO L21P 8 8 IO L21N 8 8 IO L22P 8 Y5 8 IO 22 8 W5 8 IO L23P VRN 8 w9 8 IO L23N VRP 8 W8 8 IO L24P CC LC 8 ACA 8 IO L24N CC IC 8 AC3 8 IO LIP 8 AD11 8 IO LIN 8 AD10 8 IO L2P 8 IA 8 IO 8 L3 8 IO L3P 8 ABI 8 IO 8 ACI1 8 IO_L4P_8 M4 8 IO_L4N_VREF_8 N4 8 IO L5P 8 T9 8 IO L5N 8 T8 8 IO L6P 8 P5 8 IO L6N 8 R5 8 IO L7P 8 AA10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 59 Chapter 2 Pinout Tables 60 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 8 IO L7N 8 AB10 8 IO L8P CC IC 8 P4 8 IO L8N CC IC 8 R3 8 IO L9P CC IC 8 W10 8 IO_L9N_CC_LC_8 Y10 8 IO L10P 8 N3 8 IO L10N 8 P3 8 IO L11P 8 U6 8 IO L11N 8 U5 8 IO L12P 8 T4 8 IO L12N VREF 8 T3 8 IO L13P 8 U7 8 IO L13N 8 V6 8 IO L14P 8 U4 8 IO L14N 8 V4 8 IO L15P 8 U9 8 IO L15N 8 V8 8 IO L16P 8 V3 8 IO L16N 8 W3 9 IO L17P 9 M20 9 IO L17N 9 M19 9 IO L18P 9 P16 9 IO L18N 9 N16 9 IO L19P 9 N21 9 IO_L19N_9 M21 9 IO L20P 9 N18 9 IO L20N VREF 9 N17 9 IO L21P 9 P19 9 IO 121 9 N19 9 IO L22P 9 R17 9 1 L2N 9 R16
97. 8 IO_L20P_8 8 IO L20N VREF 8 Y7 8 IO 1215 8 8 IO_L21N_8 Y9 8 IO_L22P_8 AD5 8 IO L22N 8 AD4 8 IO_L23P_VRN_8 AE7 8 IO L23N VRP 8 AD7 8 IO L24P CC LC 8 AC6 8 IO L24N CC LC 8 AB6 8 IO L1P 8 W2 8 IO_LIN_8 W1 8 IO_L2P_8 V6 8 IO_L2N_8 V5 8 IO L3P 8 W7 8 IO L3N 8 V7 8 IO 8 W4 8 IO_L4N_VREF_8 W3 8 IO L5P 8 W6 8 IO_L5N_8 W5 8 IO L6P 8 Y2 8 IO LoN 8 Y1 8 IO_L7P_8 AA4 8 IO_L7N_8 AA3 8 IO L8P CC LC 8 Y4 8 IO_L8N_CC_LC_8 Y3 8 IO L9P CC LC 8 Y6 8 IO L9N CC LC 8 Y5 8 IO L10P 8 8 IO 8 8 IO_L11P_8 AC4 8 IO_L11N_8 AB4 8 IO L12P 8 AB3 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF668 Flip Chip Fine Pitch BGA Package Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued Bank Pin Description Pin Number LX15 eve ede 8 IO L12N VREF 8 AB2 8 IO L13P 8 AC5 8 IO L13N 8 AB5 8 IO L14P 8 AC2 8 IO 8 AC1 8 IO_L15P_8 AF3 8 IO L15N 8 AE3 8 IO L16P 8 AD2 8 IO L16N 8 AD1 9 IO L17P 9 N21 9 IO L17N 9 N20 9 IO L18P 9 p25 9 IO L18N 9 P24 9 IO_L19P_9 P23 9 IO L19N 9 P22 9 1 20 9 R26 9 IO L20N VREF 9 R25 9 IO L21P 9 P20 9 IO L21N 9 P19 9 IO L22P 9 R24 9 1 L2N 9 R23 9 IO L23P VRN 9 R22 9 IO L23N VRP 9 R21 9 IO L24P CC LC 9 T24 9
98. 9 IO L23P VRN 9 21 9 IO L23N VRP 9 P20 9 IO L24P CC LIC 9 R18 9 IO L24N CC IC 9 P18 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 EZ XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 10 IO L17P 10 M10 10 IO L17N 10 M9 10 IO L18P 10 N8 10 IO L18N 10 N7 10 IO L19P 10 M11 10 IO L19N 10 N11 10 IO L20P 10 P8 10 IO L20N VREF 10 R8 10 IO L21P 10 P11 10 IO L21N 10 P10 10 IO L22P 10 P6 10 IO L22N 10 N6 10 IO L23P VRN 10 N9 10 IO L23N VRP 10 P9 10 IO L24P CC LC 10 R7 10 IO_L24N_CC_LC_10 R6 0 vcco_o 0 T11 0 M13 0 VCCO 00 R14 0 vcco 0 L16 1 VCCO 1 J12 1 VCCO_1 H15 2 VCCO 2 V15 2 VCCO 2 W12 3 VCCO_3 B13 3 VCCO_3 E14 4 VCCO_4 AB13 4 VCCO 4 4 5 VCCO 5 A16 5 VCCO 5 D17 5 VCCO 5 G18 5 VCCO 5 K19 5 VCCO 5 C20 5 VCCO 5 F21 5 VCCO_5 J22 5 VCCO_5 M23 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 61 Chapter 2 Pinout Tables 62 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Descri
99. Date Code Stepping Identification Step 0 is not always marked Package Lot Code Speed Grade Ope rati ng Ran ge ug075 ch06 01 020906 Figure 6 1 Virtex 4 Device Package Marking Table 6 1 Xilinx Device Marking Definition Example Item Definition Xilinx Logo Xilinx logo Xilinx name with trademark and trademark registered status Family Brand Family name with trademark and trademark registered status Virtex 4 This line is optional and Logo could appear blank 1st Line Device name 2nd Line Package type and pin count circuit design revision the location code for the wafer fab the geometry code and date code A Gin the third letter of a package type indicates a Pb free RoHS compliant package For more details on Xilinx Pb Free and RoHS Compliant Products see http www xilinx com system_resources lead_free index htm 3rd Line 12 Ten alphanumeric characters for Assembly Lot and Step information The last digit is usually an A or an M if a stepping version does not exist In this example the last number on this line indicates the stepping version of the device 2 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 285 UG075 v3 3 September 19 2008 Chapter 6 Package Marking XILINX Table 6 1 Xilinx Device Marking Definition Example Continued Item Definition Device speed grade and temperature range If a grade is not marked on the package
100. FF1513 Package e FF1513 Package Pinout Diagram LX100 LX160 and LX200 page 263 e FF1513 Color Coded SelectIO and Bank Information page 264 FF1517 Package e FF1517 Package Pinout Diagram FX100 page 265 e FF1517 Package Pinout Diagram FX140 page 266 e FF1517 Color Coded SelectIO and Bank Information page 267 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX SF363 Package Pinout Diagram LX15 and FX12 SF363 Package Pinout Diagram LX15 and FX12 Figure 3 1 User Pins O IO LXXY 4 Multi Function Pins ADC1 ADC7 DO D31 cc N_GC P_GC SM1 SM7 VREF VRN VRP oDoocoecoeooo SF363 XC4VLX15 and XC4VFX12 Top View 1 2 g 5 6 7 9 1041 x 415164 7194920
101. GND AA6 N A GND C9 N A GND AD9 N A GND M10 N A GND N10 N A GND P10 N A GND R10 N A GND 11 GND M11 N A GND N11 N A GND P11 N A GND R11 N A GND U11 N A GND E12 N A GND K12 N A GND L12 N A GND N12 N A GND P12 N A GND T12 N A GND U12 N A GND AB12 N A GND A13 N A GND J13 N A GND K13 N A GND L13 N A GND M13 N A GND N13 N A GND P13 N A GND R13 N A GND T13 N A GND U13 N A GND V13 N A GND AF13 N A GND A14 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 47 Chapter 2 Pinout Tables 48 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices N A GND J14 N A GND K14 N A GND L14 N A GND M14 N A GND N14 N A GND P14 N A GND R14 N A GND T14 N A GND U14 N A GND V14 N A GND AF14 N A GND E15 N A GND K15 N A GND L15 N A GND N15 N A GND P15 N A GND T15 N A GND U15 N A GND AB15 N A GND K16 N A GND M16 N A GND N16 N A GND P16 N A GND R16 N A GND U16 N A GND M17 N A GND N17 N A GND P17 N A GND R17 N A GND C18 N A GND AD18 N A GND F21 N A GND P21 N A GND AA21 N A GND J24 N A GND V24 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008
102. IO L13N 10 T15 10 IO L14P 10 M10 10 IO L14N 10 N10 10 IO L15P 10 E4 10 IO L15N 10 E3 10 IO L16P 10 D2 10 IO L16N 10 D1 10 IO L25P CC LC 10 P11 10 IO L25N CC IC 10 R11 10 IO L26P 10 T13 10 IO L26N 10 U13 10 IO L27P 10 M8 10 IO L27N 10 M7 10 IO L28P 10 P9 10 IO L28N VREF 10 N8 10 IO L29P 10 L6 10 IO L29N 10 M6 10 IO L30P 10 N7 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 171 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 172 XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 10 IO L30N 10 P7 10 IO L31P 10 R9 10 IO L31N 10 R8 10 IO L32P 10 U12 10 IO L32N 10 T11 11 IO_L17P_11 AR37 11 IO L17N 11 AR38 11 IO L18P 11 AM35 11 IO L18N 11 AL35 11 IO_L19P_11 AP35 11 IO L19N 11 AN35 11 IO L20P 11 AT39 11 IO L20N VREF 11 AR39 11 IO L21P 11 AG28 11 IO L21N 11 AH29 11 IO L22P 11 AP36 11 IO L22N 11 AP37 11 IO L23P VRN 11 AN33 11 IO L23N VRP 11 AN34 11 IO L24P CC IC 11 AU38 11 IO L24N CC IC 11 AT38 11 IO L1P 11 AG33 11 IO LIN 11 AF33 11 IO 12 11 AC28 11 IO 11 AD29 11 IO L3P 11 AD27 11 IO L3N 11 AC27 11 IO 11 AE31 11 IO VREF 11 AE32 11 IO L5P 11 AD26 11 IO L5N 11 AE26 11 IO L6P 11 AF31 11 IO L6N 11 AG32 11 IO_L7P_11 AH32 11 IO LN 11 AH33 11 IO L8P CC IC 11 AJ34 11 IO L8N CC IC 11 AH34
103. IO L31P 15 AM36 15 IO L31N 15 AL36 15 IO L32P 15 AK36 15 IO L32N 15 AK37 16 IO L17P 16 AC8 16 IO L17N 16 AB8 16 IO L18P 16 AD2 16 IO L18N 16 ADI 16 IO L19P 16 AD5 16 IO L19N 16 AD4 16 IO L20P 16 AB13 16 IO L20N VREF 16 AC13 16 IO L21P 16 AB15 16 IO L21N 16 AC14 16 IO L22P 16 AC10 180 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 16 IO L22N 16 AD9 16 IO L23P VRN 16 AD7 16 IO L23N VRP 16 AC7 16 IO L24P CC IC 16 AE3 16 IO L24N CC IC 16 AE2 16 IO L1P 16 V4 16 1 16 W4 16 IO 2 16 V3 16 IO 2 16 V2 16 IO L3P 16 W2 16 IO L3N 16 W1 16 IO_L4P_16 Y7 16 IO_L4N_VREF_16 Y6 16 IO_L5P_16 Y4 16 IO_L5N_16 AA4 16 IO L6P 16 Y3 16 IO L6N 16 Y2 16 IO L7P 16 AA3 16 IO L7N 16 AB3 16 IO L8P CC LC 16 Y1 16 IO_L8N_CC_LC_16 AAI 16 IO L9P CC LC 16 AA14 16 IO_LIN_CC_LC_16 AA13 16 IO L10P 16 AA6 16 IO L10N 16 AA5 16 IO L11P 16 AB6 16 IO L11N 16 AB5 16 IO L12P 16 AB2 16 IO L12N VREF 16 AB1 16 IO L13P 16 16 IO L13N 16 AC2 16 IO L14P 16 AB7 16 IO L14N 16 16 IO L15P 16 AB11 16 IO L15N 16 AB10 16 IO L16P 16 AC5 16 IO L16N 16 ACA 16 IO L25P CC IC 16 AC12 Virtex 4
104. IO L5P 6 F10 6 IO L5N 6 E10 6 IO L6P 6 A6 6 IO L6N 6 A5 6 IO 17 6 E9 6 IO L7N 6 F9 6 IO L8P CC LC 6 B6 6 IO L8N CC LC 6 C6 6 IO L17P 6 E7 6 IO L17N 6 D6 6 IO L18P 6 E6 6 IO L18N 6 E5 6 IO L19P 6 F7 6 IO L19N 6 G7 6 IO L20P 6 C2 6 IO L20N VREF 6 C1 6 IO L21P 6 H8 6 IO L21N 6 H7 6 IO 122 6 D3 6 IO L22N 6 E4 6 IO L23P VRN 6 G6 6 IO L23N VRP 6 G5 6 IO L24P CC LC 6 E3 6 IO L24N CC LC 6 E2 6 IO L9P CC LC 6 G10 6 IO L9N CC LC 6 G9 6 IO L10P 6 F8 6 IO L10N 6 G8 6 IO L11P 6 B7 6 IO L11N 6 C7 6 IO L12P 6 C5 6 IO L12N VREF 6 D5 6 IO L13P 6 A9 36 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF668 Flip Chip Fine Pitch BGA Package Table 2 2 FF668 Package LX15 LX25 LX40 LX60 9 25 SX35 and FX12 Devices Continued Bank Pin Description Pin Number LX15 e I 6 IO L13N 6 B9 6 IO L14P 6 A3 6 IO L14N 6 B3 6 IO L15P 6 A4 6 IO L15N 6 B4 6 IO L16P 6 C4 6 IO L16N 6 D4 6 IO L25P CC IC 6 D2 6 IO L25N CC IC 6 D1 6 IO L26P 6 E1 6 IO L26N 6 F1 6 IO L27P 6 F4 6 IO L27N 6 F3 6 IO L28P 6 G4 6 IO L28N VREF 6 G3 6 IO L29P 6 H6 6 IO L29N 6 H5 6 IO L30P 6 G2 6 IO L30N 6 G1 6 IO L31P 6 H4 6 IO_L31N_6 H3 6 IO L32P 6 H2 6 IO L32N 6 H1 7 IO L25P CC SM7 IC 7 AD19 7 IO L25N CC SM7 IC 7 AC19 7
105. J OOOOLIGONONOBL WI 6 409 WwILWMORDOOOLOOOO L OOOORIGIMaOO mw Ew e ST 9 DO Lm O am L M OOORNIOOOOLIOOCMUIMI M ecre oueomenreMmoaMroo MNMOSOOOO M N OOOOLIOGWO wg esc Ce oW LM MOoSOoOodooLOoOO N P OOLIGOOORIOMOOLMLUIMO D OL Ww LM P R GOOOBNOMOOLIOOMORNOO tsMm WoW WM WOOL JJ DOMONOOOO R T 196 sa aM WwOoMOSOOOOLDOOG T u OOOLIOOOORIOMOOLIILIM SNe WIL IM OOOSOMOOLIOOOO U V IS IN NI WBYIONOaMOOLIOOOONGOGOO v w OONOOOOLJOONMO wA Wm P w v OOOO OMONOCMORONBIUDNWZDOTOBOMONCMOOCHOCCOO A OLIOOOORIOMOOLIOOCNMIMBSIKLI AMET T Tut OMOGOLIOOOORNIOG AA AB GOOBRIOOOOLIOOMORBIOIOL WE TRE TE TRE TRO OL TO OO RIOOOO AB AC OOOOLIOGOMONOCGOWLJIMU IW ANAA lm IODOIuMOSOOOOLIOOO AC AD OQOGC9 GO NIOBM OMIT 1M gesagt I OOoOSOMOOLIOOOO AD AE OOOONOM C OMBRE RE TR eS mL M e eO SIORMOOLIOCGM OSI GOOO AE MI IO Ww AF AG OOOLIOOOORJOCMI TM TM GRONODaMemPeEMIMOSNOMOODOOOO AG AH OOOORIOMOOLDIMOfMGBIeAGdOoeCOOo Ie es DM MOoOoDoOoOoONGOOO AH AJ OMO ONU CO AJ AK 3 4 4 AK AL AL AM OOORNIOG OCA
106. L26P 12 AK7 12 IO L26N 12 AJ7 12 IO L27P 12 AH10 12 IO L27N 12 AH9 12 IO L28P 12 AT3 12 IO L28N VREF 12 AR3 12 IO L29P 12 AM8 12 IO L29N 12 AM7 12 IO_L30P_12 AP5 12 IO L30N 12 AN5 12 IO L31P 12 AU6 12 IO L31N 12 AT6 12 IO L32P 12 AL8 12 IO L32N 12 AK8 13 IO_L17P_13 AA36 13 IO L17N 13 AB36 13 IO L18P 13 AA35 13 IO L18N 13 AB35 13 IO_L19P_13 W30 13 IO L19N 13 W29 13 IO 1200 13 AB37 13 IO L20N VREF 13 AC37 13 IO L21P 13 Y32 13 IO L21N 13 Y31 13 IO 122 13 AB23 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 215 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 13 IO L22N 13 AA23 13 IO L23P VRN 13 AA33 13 IO L23N VRP 13 AB33 13 IO L24P CC LC 13 AA25 13 IO L24N CC LC 13 AA24 13 IO L1P 13 N37 13 IO LIN 13 M37 13 IO L2P 13 K37 13 IO 2 13 K36 13 IO L3P 13 R36 13 IO 13 P36 13 IO_L4P_13 M36 13 TO_L4N_VREF_13 L36 13 IO_L5P_13 R37 13 IO 5 13 P37 13 IO_L6P_13 R34 13 IO L6N 13 P35 13 IO_L7P_13 U36 13 IO_L7N_13 T36 13 IO_L8P_CC_LC_13 T35 13 IO L8N CC LC 13 T34 13 IO L9P CC IC 13 V37 13 IO L9N CC LC 13 U37 13 IO L10P 13 V35 13 IO L10N 13 U35 13 IO_L11P_13 V34 13 IO L11N 13 V33 13 IO L12P 13 W37 13 IO L12N VREF 13 Y37 13 IO L13P 13 W36 13 IO L13N 13 Y3
107. LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Ne Connects in PRAO Number LX60 and SX55 Devices 13 IO_L24N_CC_LC_13 V30 13 IO L1P 13 T23 13 IO 13 U23 13 IO L2P 13 R26 13 IO 2 13 T26 13 IO L3P 13 T24 13 IO L3N 13 T25 13 IO 13 R27 13 IO VREF 13 R28 13 IO L5P 13 p29 13 IO L5N 13 R29 13 IO L6P 13 N32 13 IO L6N 13 P32 13 IO L7P 19 P30 13 IO L7N 13 P31 13 IO L8P CC LC 13 N33 13 IO L8N CC IC 13 N34 13 IO L9P CC LC 13 P34 13 IO_LIN_CC_LC_13 R34 13 IO L10P 13 R31 13 IO L10N 13 T31 13 IO L11P 13 R32 13 IO L11N 13 R33 13 IO L12P 13 T28 13 IO L12N VREF 13 U28 13 IO L13P 13 T29 13 IO L13N 13 T30 13 IO L14P 13 T33 13 IO L14N 13 T34 13 IO L15P 13 U26 13 IO L15N 13 U27 13 IO L16P 13 U30 13 IO L16N 13 U31 13 IO L25P CC LC 13 Y32 13 IO L25N CC LC 13 Y33 13 IO L26P 13 W27 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 109 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables Z XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin No Connects In 1x40 Number LX60 and SX55 Devices 13 IO L26N 13 13 IO L27P 13 13 IO L27N 13 13 IO L28P 13
108. N A 110 VTTXB 110 AU2 N A TXPPADB 110 AT1 N A TXNPADBE 110 AUI N A AVCCAUXRXB 110 AV4 N A RXPPADB_110 AW3 N A VTRXB_110 AV2 N A RXNPADB 110 AWA N A MGTCLK P 110 AW6 N A MGTCLK_N_110 AW7 N A RTERM_110 AV6 N A MGTVREF_110 AV8 N A AVCCAUXRXA_111 AA2 NC N A RXPPADA 111 Y1 NC N A VTRXA_111 AB1 NC N A RXNPADA 111 NC N A AVCCAUXMGT_111 AH2 NC N A AVCCAUXTX_111 AE2 NC N A VTTXA_111 AC2 NC N A TXPPADA_111 NC N A TXNPADA_ 111 AD1 NC N A VTTXB 111 AF2 NC N A TXPPADB 111 AE1 NC N A TXNPADB 111 AF1 NC N A AVCCAUXRXB 111 AJ2 NC N A RXPPADB 111 AH1 NC N A VTRXB_111 AG1 NC N A RXNPADB_111 NC N A AVCCAUXRXA_112 K2 N A RXPPADA 112 JA N A VTRXA 112 L1 N A RXNPADA 112 K1 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number AVCCAUXMGT_112 U2 N A AVCCAUXTX_112 P2 N A 112 2 TXPPADA 112 112 N1 N A VTTXB_112 R2 N A TXPPADB_112 P1 N A TXNPADB_112 R1 N A AVCCAUXRXB_112 V2 N A RXPPADB_112 U1 N A VTRXB_112 T1 N A RXNPADB_112 V1 N A AVCCAUXRXA_ 113 B8 N A RXPPADA 113 A9 N A
109. RTERM U RDWR B 075 06 050108 Figure 3 18 FF1152 Flip Chip Fine Pitch BGA Pinout Diagram FX60 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Package Pinout Diagram FX100 FF1152 Package Pinout Diagram FX100 FF1152 XC4VFX100 Top View
110. VCCINT Y15 N A VCCINT E16 N A VCCINT N16 N A VCCINT R16 N A VCCINT M17 N A VCCINT P17 N A VCCINT T17 N A VCCINT JA8 N A VCCINT L18 N A VCCINT R18 N A VCCINT H19 N A VCCINT M19 N A VCCINT P19 N A VCCINT L20 N A VCCINT U20 Notes 1 2 3 This voltage is also referred to as Vcc cowric in the Virtex 4 Configuration Guide For LX25 devices connect this reserved pin to GND For LX25 devices connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vecaux is acceptable www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package FF1148 Flip Chip Fine Pitch BGA Package As shown in Table 2 5 the following Virtex 4 LX and SX devices are available in the FF1148 flip chip fine pitch BGA package e XCAVLXAO e XC4VLX60 e XC4VLX80 e 4 00 e XC4VLX160 e XC4VSX55 Pinouts in the following devices are identical e LX40 LX60 and SX55 LX80 LX100 and LX160 The No Connect column in Table 2 5 shows pins that are not available in LX40 LX60 and SX55 devices To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices
111. VREF 6 F4 6 IO L29P 6 F16 6 IO L29N 6 F15 6 IO L30P 6 C4 6 IO L30N 6 D4 6 IO L31P 6 E16 6 IO L31N 6 D16 6 IO L32P 6 E3 6 IO L32N 6 F3 204 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 7 IO_L25P_CC_SM7_LC_7 AT31 7 IO L25N CC SM7 LC 7 AU31 7 IO_L26P_SM6_7 AR29 7 IO 26 SM6 7 AT29 7 IO_L27P_SM5_7 AP31 7 IO_L27N_SM5_7 AR31 7 IO L28P 7 AN29 7 IO L28N VREF 7 AP29 7 IO_L29P_SM4_7 AL30 7 TO_L29N_SM4_7 AM30 7 IO L30P SM3 7 AT30 7 IO L30N SM3 7 AU30 7 IO_L31P_SM2_7 AN30 7 IO L31N SM2 7 AP30 7 IO_L32P_SM1_7 AK29 7 IO L32N 7 AL29 7 IO_L17P_7 AP32 7 IO_L17N_7 AR32 7 IO L18P 7 AU28 7 IO L18N 7 AU27 7 IO L19P 7 AM32 7 IO L19N 7 AN32 7 IO L20P 7 AT28 7 IO L20N VREF 7 AR28 7 IO L21P 7 AJ30 7 IO L21N 7 AK31 7 IO 122 7 AN28 7 IO_L22N_7 AN27 7 IO L23P VRN 7 AL31 7 IO L23N VRP 7 AM31 7 IO L24P CC LIC 7 AM28 7 IO 124 CC IC 7 AL28 7 IO L1P 7 AP37 7 1 7 AR37 7 IO 12 7 AT24 7 IO 7 AR24 7 IO L3P 7 AT36 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 205 UG075 v3 3 September 19 2008 Chapter 2 Pinout Table
112. are also available for download at http www xilinx com virtex4 Virtex 4 Family Overview The features and product selection of the Virtex 4 family are outlined in this overview Virtex 4 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 4 family Virtex 4 FPGA User Guide Chapters in this guide cover the following topics Clocking Resources Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 7 UG075 v3 3 September 19 2008 Preface About This Guide XILINX Digital Clock Manager DCM Phase Matched Clock Dividers PMCD Block RAM and FIFO memory Configurable Logic Blocks CLBs SelectIO Resources SelectIO Logic Resources Advanced SelectIO Logic Resources XtremeDSP for Virtex 4 FPGAs User Guide This guide describes the XtremeDSP slice and includes reference designs for using DSP48 math functions and various FIR filters e Virtex 4 FPGA Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption Boundary Scan and JTAG configuration reconfiguration techniques and readback through the SelectM AP and JTAG interfaces e Virtex 4 PCB Designer s Guide This designer s guide provides information on the design of PCBs for Virtex 4 devices It considers all aspects of the PCB from the syst
113. damage to components Also condensation can be an issue with these devices e Outside the package itself the board on which the package sits can have a significant impact on thermal performance As much as 60 to 80 of the dissipated heat can go through the BGA balls and thus to the board Using the standard four layer JEDEC boards these with their multiple internal vias show very efficient junction to board resistances Designs can be implemented to take advantage of the board s ability to spread heat The effect of the board is dependent on its size and how it conducts heat Board size the level of copper traces on it the number of buried copper planes all lower the junction to ambient thermal resistance for a package mounted on it The cold ring junction to board thermal resistance for Virtex 4 FPGA packages are given in Table 5 1 Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources on the board particularly if the board is not cooled effectively An otherwise cooler component can be heated by other heat contributing components on the board Table 5 1 lists the junction to board thermal parameters for Virtex 4 FPGA packages A standard JEDEC type board in still air was used for the data estimation Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources particularly if the boar
114. exploiting the fabric and using several embedded circuits and systems such as PowerPC devices MGTs SelectIO buses with DCI and so forth presents a power consumption challenge that must be managed Unlike features in an ASIC or a microprocessor the combination of FPGA features utilized in an end user application will not be known to the component supplier Therefore it remains a challenge for Xilinx to predict the power requirements of a given Virtex 4 device when it leaves the factory Accurate estimates are obtained when the board design takes shape For this purpose Xilinx offers and supports a suite of integrated device power analysis tools to help end users quickly and accurately estimate their design power requirements The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users Therefore Xilinx devices do not come with preset thermal solutions The end user s operating conditions dictate the appropriate solution The Virtex 4 FPGA package offering see Table 5 1 is tailored to include medium to high power options that allow external management of power to suit the user application Table 5 1 also shows the thermal resistance data for Virtex 4 devices in the packages Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 279 UG075 v3 3 September 19 2008 Chapter 5 Thermal Specifications XILINX offered The data includes junction to ambient in still air a
115. interface material TIM as shown in Figure 5 1 Thermal Interface Material TIM oo Substrate UGO75_c05_01_081905 Figure 5 1 Heat Spreader with Thermal Interface Material Materials with better thermal conductivity and consistent process applications deliver low thermal resistance up to the heat spreader The junction to case thermal resistance top of heat spreader of all Virtex 4 FPGA packages is less than 0 5 eC watt Typically this value is between 0 1 to 0 3 eC watt for the larger packages 35 mm x 35 mm and above Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 281 UG075 v3 3 September 19 2008 Chapter 5 Thermal Specifications x XILINX e Heat Sinking Solutions at the System Level Depending on the system s physical as well as mechanical constraints the expectation is that the thermal budget will be maintained with custom or OEM heat sink solutions providing the third prong in the thermal management strategy At this point Xilinx has left the heat sink solution to the system level designers who can tailor the design and solution to the constraints of their systems being fully aware that the part has certain inherent capabilities for delivering the heat to the surface The Virtex 4 FPGA packages can be grouped into medium and high performance packages based on their power handling capabilities All Virtex 4 FPGA packages can use thermal enhancements ranging from simple
116. n nin T uU WIinjniinjnjinjnjnjnj jnjninjUIJIDIIMIBIW IgE Y PIin niin niin ni j n n n n n u v AMANO MK pCO 2 njininjrjmnjmnjnjnjnjnjnjn v w nin jnjnimimjnjn nimn mnj 188 1O O ad n in ini nj n in w v njni njnjnjinjn nj n jO OO ORIJO FA WIE TW E TW OP eo n in n E J n in n n Y AA n nininininl 1 OCOOOHUOCOORINIM NM AA AB nininm JOOMCONIOWMOOLI9 006 BOOUOSBONOMNn AB AC OOOONOOOOLDnMUMGDCGWOLMUMEMDPNOOOOLOOO AC AD COBNIOOOOLIG9O aL TOOL IO esses TL TM OOLIOOCQONO AE OOOCOLIOOOCQCBNOMDLWILICOOCODSIGOMITMDIIOOMONOOOO AE AF OLIOGOOBNJOMOOLIMOOC QGCDIODOmOO LIMOMOSOOOOLIOO AF AG OOONIOOOOLIOOIMQGNeQOOCODLDIeIoosIOoOOLIOOOON AH OQOCG OLIOGOMORSI OW eO mL 0e 5 909o09LI OOOORIOOO AJ AJ AK AK AL AL AM AM AN OOOORNIOOOOLJIOOOQOCRISISISQDLIe 6 6 10 OO0O0LIOCL AN AP 5 1 2 8 4 5 6 8 9 1044112441445164 7184920 5122 424 526 28 93041324434 User I O Pins Dedicated Pins Other Pins O 1 LXXY Z ADC P PROG B Multi Function Pins C CCLK PWRDWN B RSVD amp ADC1 ADC7 B CS B U
117. v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 11 VCCO 11 AP38 11 VCCO 11 AR35 11 VCCO 11 AUS39 11 VCCO 11 AV36 12 VCCO 12 AF12 12 VCCO_12 AG9 12 VCCO_12 AH6 12 VCCO_12 AJ3 12 VCCO_12 AL7 12 VCCO_12 AM4 12 VCCO_12 AN1 12 VCCO_12 ARS 12 VCCO_12 AT2 13 VCCO 13 AA37 13 VCCO 13 P38 13 VCCO 13 R35 13 VCCO 13 T32 13 VCCO 13 U29 13 VCCO 13 U39 13 VCCO 13 V26 13 VCCO 13 V36 13 VCCO 13 W33 14 VCCO 14 J3 14 VCCO 14 M4 14 VCCO_14 N1 14 VCCO_14 R5 14 VCCO 14 T2 14 VCCO 14 U9 14 VCCO 14 V6 14 VCCO 14 W13 14 VCCO_14 Y10 15 VCCO_15 AA27 15 VCCO_15 AB34 15 VCCO_15 AC31 15 VCCO_15 AD38 15 VCCO_15 AE35 15 VCCO_15 AG39 15 VCCO_15 AH36 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 185 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 15 VCCO_15 AL37 15 VCCO_15 Y30 16 VCCO_16 AA7 16 VCCO 16 AB14 16 VCCO_16 ABA 16 VCCO 16 ACI 16 VCCO 16 AC11 16 VCCO_16 AD8 16 VCCO_16 16 VCCO_16 AF2 16 VCCO_16 W3
118. 0 05 23 e Removed FF676 package information from the guide e Made minor changes to pin definitions in Table 1 3 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 09 30 05 Version 24 Revision Added information on the FF676 package to all the chapters in this guide Revised Table 1 3 page 14 Added LVDSEXT and updated all INIT_ to INIT_B_0 All dedicated configuration pins are in bank 0 Updated INIT B and PROG B references for consistency Corrected package pinout diagram pins AE16 in Figure 3 15 and AC34 in Figure 3 17 Revised mechanical drawings for the FF672 Figure 4 3 and FF1760 Figure 4 9 packages Added FF676 package Figure 4 4 Removed A A cross sections from all the mechanical drawings in Chapter 4 Mechanical Drawings Revised and updated Chapter 5 Thermal Specifications 01 24 07 3 0 Deleted all references to FF1760 package Not supported For all pinout tables where applicable Corrected HSWAPEN B 0 to HSWPEN 0 active High Deleted table end notes regarding ADC functionality formerly Note 1 and SM functionality formerly Note 2 Subsequent table end notes renumbered Table 2 3 Added NC for FX20 Devices to Pins J25 L25 N25 T25 U2 N2 R2 and Y2 Corrected pinout diagram Figure 3 7 Table 2 8 Added NC for FX100 Devices to Pins Y38 AB38 AD38 AG38 AK38 W39 W1 Y2 AB2 AD2 AG2 and AK2 Correct
119. 0 J4 10 IO L13P 10 H5 10 IO L13N 10 15 10 IO L14P 10 L5 10 IO L14N 10 M5 10 IO L15P 10 N9 10 IO L15N 10 N8 10 IO L16P 10 K3 10 IO L16N 10 L3 10 IO L25P CC LC 10 T11 10 IO L25N CC IC 10 U11 10 IO L26P 10 R4 10 IO L26N 10 T4 10 IO L27P 10 T13 10 IO L27N 10 U12 10 IO L28P 10 T10 10 IO L28N VREF 10 T9 10 IO L29P 10 R3 10 IO L29N 10 T3 10 IO L30P 10 T8 10 IO L30N 10 U8 10 IO L31P 10 T6 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 211 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 10 IO L31N 10 T5 10 IO L32P 10 U10 10 IO L32N 10 V9 11 IO L17P 11 AG33 11 IO L17N 11 AG32 11 IO L18P 11 AH34 11 IO L18N 11 AJ34 11 IO L19P 11 AJ37 11 IO L19N 11 AK37 11 IO L20P 11 AJ36 11 IO L20N VREF 11 AK36 11 IO L21P 11 AF30 11 IO L21N 11 AG30 11 IO L22P 11 AL36 11 IO L22N 11 AM36 11 IO L23P VRN 11 AH33 11 IO L23N VRP 11 AJ32 11 IO L24P CC IC 11 AK34 11 IO L24N CC LC 11 AL34 11 IO L1P 11 AC30 11 IO 11 AC29 11 IO 12 11 AC28 11 IO I2N 11 AD27 11 IO LI3P 11 AD35 11 IO L3N 11 AD34 11 IO 4 11 AC32 11 IO LAN VREF 11 AB31 11 IO L5P 11 AD31 11 IO L5N 11 AD30 11 IO L6P 11 AE37 11 IO L6N 11 AD37 11 IO L7P 11 AD29 11 IO L7N 11 AE29 11 IO L8P CC IC 11 AE36 11 IO L8N CC
120. 008 XILINX FF 1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 113 GNDA_113 E2 113 GNDA_113 H2 113 GNDA_113 12 113 GNDA_113 2 113 GNDA_113 12 113 GNDA_113 B3 113 GNDA_113 B5 113 GNDA_113 B7 113 GNDA_113 A8 114 GNDA_114 B9 NC NC 114 GNDA 114 11 NC NC 114 GNDA_114 B14 NC NC 114 GNDA_114 B16 NC NC 114 GNDA_114 B18 NC NC 114 GNDA_114 B19 NC NC N A VREFN_SM 2 AL17 N A VREFP SM 2 AL16 AVDD_SM 9 15 VN SM AM17 N A VP SM AVSS_SM 2 VREFN_ADC 2 D20 NC N A VREFP_ADC D19 NC N A AVDD_ADC 9 D18 NC N A VN ADC O C20 NC N A VP ADC O C19 NC N A AVSS ADC C18 NC N A GND J3 N A GND w3 N A GND AJ3 N A GND M4 N A GND AB4 N A GND AM4 N A GND E5 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 149 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 150 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60
121. 02 GNDA_102 P34 103 GNDA_103 R33 103 GNDA_103 U33 103 GNDA_103 W33 103 GNDA_103 AB33 103 GNDA_103 AD33 103 GNDA 103 AE34 105 GNDA 105 AP27 105 105 AN28 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 147 Chapter 2 Pinout Tables 148 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 105 GNDA_105 AN30 105 GNDA_105 AP30 105 GNDA_105 AF33 105 GNDA 105 AH33 105 105 AK33 105 105 AP33 105 GNDA_105 AN34 106 GNDA_106 AP16 NC 106 GNDA_106 AN19 NC 106 GNDA_106 AN21 NC 106 GNDA_106 AN24 NC 106 GNDA 106 AN26 NC 109 GNDA 109 AN6 NC 109 GNDA_109 NC 109 GNDA_109 AN11 NC 109 GNDA_109 AN13 NC 109 GNDA_109 AN16 NC 110 GNDA_110 AN1 110 GNDA_110 AC2 110 GNDA_110 AE2 110 GNDA_110 AG2 110 GNDA_110 AK2 110 GNDA_110 AN2 110 GNDA_110 AP2 110 GNDA_110 AN4 110 GNDA_110 AP5 112 GNDA_112 AA2 112 GNDA_112 ABI 112 GNDA_112 M2 112 GNDA_112 2 112 GNDA_112 T2 112 GNDA_112 w2 113 GNDA_113 B1 113 GNDA_113 H1 113 GNDA_113 L1 113 GNDA 113 A2 113 GNDA 113 B2 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2
122. 075 v3 3 September 19 2008 Preface About This Guide 10 XILINX www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Chapter 1 Packaging Overview Summary This chapter covers the following topics e Introduction e Device Package Combinations and Maximum I Os e Pin Definitions Introduction This section describes the pinouts for Virtex 4 devices in the 0 80 mm and 1 00 mm pitch flip chip fine pitch BGA packages Virtex 4 devices are offered exclusively in high performance flip chip BGA packages that are optimally designed for improved signal integrity and jitter Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins All of the devices supported in a particular package are pinout compatible and are listed in the same table one table per package Pins that are not available for the smaller devices are listed in the No Connects column of each table VCCO_ pins listed as No Connects can be required for larger devices This must be considered when migrating into a larger part within the same package Each device is split into eight or more I O banks to allow for flexibility in the choice of I O standards see the Virtex 4 FPGA User Guide Global pins including JTAG configuration and power ground pins are listed at the end of each table Table 1 3 prov
123. 10 4 IO L3P GC LC 4 AB17 4 IO L3N GC LC 4 AC17 4 IO L4P GC LC 4 AF11 4 IO_L4N_GC_VREF_LC_4 AF10 4 IO L5P GC LC 4 AE14 4 IO L5N GC LC 4 AE13 4 IO LoP GC LC 4 AE10 4 IO Lo6N GC LC 4 AD10 4 IO L7P GC VRN LC 4 AD17 4 IO L7N GC VRP LC 4 AD16 4 IO L8P GC CC IC 4 AD12 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 33 Chapter 2 Pinout Tables XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 4 IO L8N GC CC IC 4 AD11 5 IO L1P 5 C17 5 IO LIN 5 D17 5 IO 12 5 C20 5 IO I2N 5 B20 5 IO L3P 5 B18 5 IO L3N 5 A18 5 IO 5 D20 5 IO VREF 5 D19 5 IO L5P 5 E17 5 IO L5N 5 F17 5 IO L6P 5 C21 5 IO L6N 5 B21 5 IO 17 5 C19 5 IO L7N 5 D18 5 IO L8P CC LC 5 A24 5 IO L8N CC LC 5 A23 5 IO L17P 5 G19 5 IO L17N 5 F19 5 IO L18P 5 E23 5 IO L18N 5 E22 5 IO L19P 5 F20 5 IO L19N 5 E20 5 IO L20P 5 C26 5 IO L20N VREF 5 C25 5 IO L21P 5 D23 5 IO L21N 5 C23 5 IO 122 5 H20 5 IO L22N 5 G20 5 IO L23P VRN 5 G22 5 IO L23N VRP 5 G21 5 IO L24P CC LC 5 F24 5 IO L24N CC LC 5 F23 5 IO L9P CC LC 5 G18 5 IO L9N CC LC 5 G17 34 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 200
124. 100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 14 IO L6N 14 K1 14 IO L7P 14 L4 14 IO L7N 14 L3 14 IO L8P CC LC 14 M3 14 IO L8N CC IC 14 M2 14 IO L9P CC LC 14 N5 14 IO L9N CC IC 14 N4 14 IO L10P 14 L1 14 IO L10N 14 M1 14 IO L11P 14 P6 14 IO 14 R6 14 IO L12P 14 P5 14 IO L12N VREF 14 P4 14 IO L13P 14 N3 14 IO L13N 14 N2 14 IO L14P 14 V13 14 IO L14N 14 V12 14 IO L15P 14 T8 14 IO L15N 14 U8 14 IO L16P 14 P2 14 IO L16N 14 P1 14 IO L25P CC IC 14 T1 14 IO L25N CC IC 14 U1 14 IO L26P 14 U3 14 IO L26N 14 U2 14 IO L27P 14 V7 14 IO L27N 14 W7 14 IO L28P 14 W10 14 IO_L28N_VREF_14 W9 14 IO_L29P_14 W6 14 IO_L29N_14 W5 14 IO_L30P_14 AA10 14 IO L30N 14 Y9 14 IO L31P 14 AA11 14 IO L31N 14 14 IO L32P 14 Y13 14 IO L32N 14 W12 178 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 15 IO L17P 15 AB27 15 IO L17N 15 AB28 15 IO L18P 15 AE34 15 IO L18N 15 AD34 15 IO L19P 15 AD31 15 IO L19N 15 AD32 15 IO L20P 15 AF36 15 IO L20N V
125. 11 IO L14P 11 AB32 NC 1 IO L14N 11 AC32 NC 11 IO L15P 11 29 NC 1 IO L15N 11 AA28 NC 11 IO L16P 11 AB31 NC 11 IO L16N 11 AB30 NC 11 IO L25P CC LC 11 AE32 NC 11 IO L25N CC IC 11 AE31 NC 11 IO L26P 11 AD27 NC 11 IO L26N 11 AD26 NC 11 IO L27P 11 AF31 NC 11 IO L27N 11 AF30 NC 11 IO L28P 11 AC25 NC 11 IO L28N VREF 11 AD25 NC 11 IO L29P 11 AE29 NC 11 IO L29N 11 AF29 NC 11 IO L30P 11 AJ32 NC UG075 v3 3 September 19 2008 137 Chapter 2 Pinout Tables XILINX No Connects in No Connects in FX40 Devices Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Fn Number FX60 Devices 11 IO L30N 11 AJ31 11 IO L31P 11 AG31 1 IO L31N 11 AG30 11 IO L32P 11 AH30 11 IO L32N 11 AJ30 12 IO L17P 12 AJ4 12 IO L17N 12 AK3 12 IO L18P 12 AE4 12 IO L18N 12 AE3 12 IO L19P 12 AM5 12 IO L19N 12 AL5 12 IO L20P 12 AC7 12 IO L20N VREF 12 AB8 12 IO_L21P_12 AL4 12 IO_L21N_12 AK4 12 IO L22P 12 AF5 12 IO L22N 12 AF4 12 IO L23P VRN 12 AF8 12 IO L23N VRP 12 AE7 12 IO L24P CC LC 12 AH4 12 IO L24N CC LC 12 AH3 12 IO L1P 12 12 IO 12 W4 12 IO L2P 12 V8 12 IO 12 V7 12 IO L3P 12 5 12 IO L3N 12 AAA 12 IO_L4P_12 W7 12 IO LAN VREF 12 W6 12 IO L5P 12 Y8 12 IO L5N 12 Y7 12 IO L6P 12 Y4 12 IO L6N 12 Y3 12 IO L7P 12 AC5 12 IO L7N 12 AB5 1
126. 13 IO L15N 13 U35 13 IO L16P 13 U33 13 IO L16N 13 V33 13 IO L25P CC LC 13 W34 13 IO L25N CC IC 13 W35 13 IO L26P 13 W36 13 IO L26N 13 W37 13 IO L27P 13 Y37 13 IO L27N 13 Y38 176 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 13 IO_L28P_13 Y39 13 IO_L28N_VREF_13 AA39 13 IO L29P 13 AA36 13 IO L29N 13 Y36 13 IO L30P 13 Y33 13 IO L30N 13 Y34 13 IO L31P 13 AB36 13 IO L31N 13 AB37 13 IO L32P 13 AB38 13 IO L32N 13 AA38 14 IO L17P 14 U10 14 IO L17N 14 T9 14 IO L18P 14 R4 14 IO L18N 14 R3 14 IO L19P 14 T6 14 IO L19N 14 T5 14 IO L20P 14 R2 14 IO L20N VREF 14 R1 14 IO L21P 14 T4 14 IO L21N 14 T3 14 IO L22P 14 U7 14 IO L22N 14 U6 14 IO L23P VRN 14 V10 14 IO L23N VRP 14 V9 14 IO L24P CC IC 14 U5 14 IO L24N CC IC 14 V5 14 IO L1P 14 H4 14 IO 14 J4 14 IO L2P 14 K4 14 IO 2 14 K3 14 IO L3P 14 H3 14 IO L3N 14 H2 14 IO 4 14 J2 14 IO LAN VREF 14 JA 14 IO L5P 14 L5 14 IO L5N 14 M5 14 IO L6P 14 K2 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 177 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX
127. 13P 12 Y16 12 IO L13N 12 AAI5 12 IO L14P 12 12 IO L14N 12 AD4 12 IO L15P 12 AH3 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 107 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Ne ii Number LX60 and SX55 Devices 12 IO L15N 12 AH2 12 IO L16P 12 AG2 12 IO L16N 12 AGI 12 IO L25P CC IC 12 AC10 12 IO_L25N_CC_LC_12 AB10 12 IO L26P 12 AK3 12 IO L26N 12 AK2 12 IO L27P 12 AF8 12 IO L27N 12 AE8 12 IO L28P 12 AH5 12 IO L28N VREF 12 AH4 12 IO L29P 12 AB13 12 IO L29N 12 2 12 1 130 12 2 12 IO L30N 12 AMI 12 IO L31P 12 AG8 12 IO L31N 12 AG7 12 IO L32P 12 AM3 12 IO L32N 12 AL3 13 IO L17P 13 V33 NC 13 IO L17N 13 V34 NC 13 IO L18P 13 U32 NC 13 IO L18N 13 U33 NC 13 IO L19P 13 V25 NC 13 IO L19N 13 U25 NC 13 IO L20P 13 V28 NC 13 IO_L20N_VREF_13 V29 NC 13 IO_L21P_13 V23 NC 13 IO_L21N_13 V24 NC 13 IO L22P 13 w32 NC 13 IO_L22N_13 V32 NC 13 IO_L23P_VRN_13 Y34 NC 13 IO L23N VRP 13 W34 NC 13 IO L24P CC LC 13 W30 NC 108 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package
128. 14 1 IO_L6P_D21_LC_1 C11 1 IO_L6N_D20_LC_1 D11 1 IO_L7P_D19_LC_1 D16 1 IO L7N D18 LC 1 C16 1 IO L8P D17 CC IC 1 E13 1 IO L8N D16 CC LC 1 D12 2 IO L1P D15 CC IC 2 AA14 2 IO_LIN_D14_CC_LC_2 AB14 2 IO_L2P_D13_LC_2 AC12 2 IO_L2N_D12_LC_2 2 IO_L3P_D11_LC_2 AA16 2 IO L3N D10 LC 2 AA15 2 IO_L4P_D9_LC_2 AB13 2 IO D8 VREF IC 2 AA13 2 IO L5P D7 LC 2 AC14 2 IO_L5N_D6_LC_2 AD14 2 IO_L6P_D5_LC_2 AA12 2 IO_L6N_D4_LC_2 AAT 2 IO L7P D3 LC 2 AC16 32 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued FF668 Flip Chip Fine Pitch BGA Package Bank Pin Description Pin Number LX15 e I 2 IO_L7N_D2_LC_2 AC15 2 IO_L8P_D1_LC_2 AC13 2 IO L8N D0 LC 2 AD13 3 TO_L1P_GC_CC_LC_3 B15 3 IO LIN GC CC IC 3 B14 3 IO 12 GC VRN LC 3 A12 3 IO L2N GC VRP LC 3 A11 3 IO L3P GC LC 3 C15 3 IO L3N GC LIC 3 C14 3 IO GC LC 3 B13 3 IO GC VREF LIC 3 B12 3 IO L5P GC LC 3 A16 3 IO L5N GC LC 3 A15 3 IO LoP GC LC 3 A10 3 IO 6 GC LC 3 B10 3 IO 7 GC LC 3 B17 3 IO L7N GC LC 3 A17 3 IO L8P GC LC 3 C13 3 IO L8N GC LC 3 C12 4 IO GC LC 4 AF12 4 IO_LIN_GC_LC_4 AE12 4 IO L2P GC LC 4 AC10 4 IO_L2N_GC_LC_4 AB
129. 16 N A VCCAUX U16 N A VCCAUX AB16 N A VCCAUX AD16 N A VCCAUX L19 N A VCCAUX N19 N A VCCAUX V19 N A VCCAUX AC19 N A VCCAUX W21 N A VCCAUX AB22 N A VCCAUX V24 N A VCCAUX N25 N A VCCAUX U26 N A VCCAUX K27 N A VCCINT AC8 N A VCCINT U10 N A VCCINT W10 N A VCCINT AA10 N A VCCINT vil N A VCCINT Yl N A VCCINT N12 N A VCCINT R12 N A VCCINT U12 N A VCCINT W12 N A VCCINT P13 N A VCCINT T13 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 153 Chapter 2 Pinout Tables 154 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber 0 Devices FXA0 Devices N A VCCINT V13 N A VCCINT Y13 N A VCCINT N14 N A VCCINT R14 N A VCCINT U14 N A VCCINT W14 N A VCCINT AC14 N A VCCINT M15 N A VCCINT P15 N A VCCINT T15 N A VCCINT V15 N A VCCINT AB15 N A VCCINT AD15 N A VCCINT N16 N A VCCINT R16 N A VCCINT W16 N A VCCINT AC16 N A VCCINT M17 N A VCCINT P17 N A VCCINT V17 N A VCCINT Y17 N A VCCINT AB17 N A VCCINT AD17 N A VCCINT L18 N A VCCINT N18 N A VCCINT R18 N A VCCINT U18 N A VCCINT AA18 N A VCCINT AC18 N A VCCINT M19 N A VCCINT T19 N A VCCINT Y19 N A VCCINT AB19 N A VCCINT L20 N A VCCINT N20 N A VCCINT U20 N A VCCINT W20 www Xilinx com Virtex 4 FPGA Packaging
130. 17N 11 AA25 NC 11 IO L18P 11 AC30 NC 11 IO L18N 11 AC29 NC 11 IO L19P 11 AB28 NC 11 IO L19N 11 AB27 NC 1 IO L20P 11 AB26 NC 11 IO L20N VREF 11 AB25 NC 11 IO L21P 11 AD32 NC 11 IO L21N 11 AD31 NC 11 IO L22P 11 AD30 NC 11 IO L22N 11 AD29 NC 11 IO L23P VRN 11 AC28 NC 11 IO L23N VRP 11 AC27 NC 11 IO L24P CC LC 11 AG32 NC 11 IO L24N CC 1C 11 AH32 NC 11 IO 11 V29 NC 11 IO LIN 11 V28 NC 11 IO L2P 11 U32 NC 11 IO 11 U31 NC 11 IO L3P 11 V30 NC 11 IO L3N 11 U30 NC www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Virtex 4 FPGA Packaging and Pinout Specification www xilinx com FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 11 IO 11 W25 NC 11 IO VREF 11 W24 NC 11 IO_L5P_11 W32 NC 11 IO L5N 11 V32 NC 11 IO L6P 11 W26 NC 11 IO L6N 11 Y26 NC 11 IO L7P 11 Y29 NC 11 IO L7N 11 w29 NC 11 IO L8P CC LC 11 W27 NC 11 IO L8N CC LC 11 V27 NC 11 IO L9P CC LC 11 W31 NC 11 IO L9N CC LC 11 W30 NC 11 IO L10P 11 Y32 NC 11 IO L10N 11 Y31 NC 11 IO L11P 11 Y28 NC 11 IO LIIN 11 Y27 NC 11 IO L12P 11 Y24 NC 11 IO L12N VREF 11 AA24 NC 11 IO L13P 11 AA31 NC 11 IO L13N 11 AA30 NC
131. 19 2008 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Da connect m 1x0 Number LX60 and SX55 Devices 10 IO L9N CC LC 10 E2 10 IO L10P 10 J6 10 IO_L10N_10 J5 10 IO_L11P_10 H5 10 IO L11N 10 4 10 IO L12P 10 N10 10 IO L12N VREF 10 N9 10 IO L13P 10 P12 10 IO L13N 10 P11 10 IO_L14P_10 G3 10 IO_L14N_10 G2 10 IO_L15P_10 L8 10 IO_L15N_10 M8 10 IO L16P 10 K6 10 IO L16N 10 L6 10 IO L25P CC LC 10 K3 10 IO L25N CC LC 10 L3 10 IO L26P 10 K2 10 IO L26N 10 K1 10 IO L27P 10 M6 10 IO L27N 10 M5 10 IO L28P 10 M3 10 IO L28N VREF 10 M2 10 IO L29P 10 L1 10 IO L29N 10 M1 10 IO L30P 10 N5 10 IO L30N 10 P5 10 IO L31P 10 P7 10 IO_L31N_10 P6 10 IO L32P 10 T10 10 IO L32N 10 R9 1 IO L17P 11 AA23 11 IO L17N 11 AA24 1 IO L18P 11 AJ34 104 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Fn No Connects In 1x40 Number LX60 and SX55 Devices 11 IO L18N 11 AH34 11 IO L19P 11 AD27
132. 19P 5 E31 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 201 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices 5 IO L19N 5 D31 5 IO L20P 5 G25 5 IO VREF 5 H25 5 IO L21P 5 L31 5 IO L21N 5 L30 5 IO 122 5 F25 5 IO L22N 5 F24 5 IO L23P VRN 5 K31 5 IO L23N VRP 5 J31 5 IO L24P CC LC 5 C25 5 IO L24N CC LC 5 D25 5 IO L9P CC LC 5 D29 5 IO L9N CC LC 5 C29 5 IO L10P 5 G27 5 IO L10N 5 H27 5 IO L11P 5 J30 5 IO L11N 5 H30 5 IO L12P 5 D27 5 IO L12N VREF 5 E27 5 IO L13P 5 G30 5 IO L13N 5 F30 5 IO L14P 5 126 5 IO_L14N_5 K26 5 IO L15P 5 D30 5 IO L15N 5 C30 5 IO L16P 5 F26 5 IO L16N 5 G26 5 IO L25P CC LC 5 E32 5 IO L25N CC LC 5 D32 5 IO L26P 5 M28 5 IO L26N 5 M27 5 IO L27P 5 G33 5 IO 127 5 G32 5 IO L28P 5 L26 5 IO L28N VREF 5 M26 5 IO L29P 5 F33 5 IO L29N 5 E33 202 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Descriptio
133. 2 6 IO I2P 6 B10 6 IO I2N 6 C10 6 IO L3P 6 All 6 IO_L3N_6 B11 6 IO 6 C9 6 IO LAN VREF 6 C8 6 IO L5P 6 G12 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 95 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SX55 Devices 6 IO L5N 6 G11 6 IO L6P 6 F10 6 IO L6N 6 G10 6 IO 17 6 D11 6 IO_L7N_6 D10 6 IO_L8P_CC_LC_6 H10 6 IO L8N CC LC 6 H9 6 IO L17P 6 A14 6 IO L17N 6 A13 6 IO L18P 6 D7 6 IO L18N 6 D6 6 IO L19P 6 D9 6 IO L19N 6 E9 6 IO L20P 6 A4 6 IO_L20N_VREF_6 A3 6 IO L21P 6 E13 6 IO L21N 6 E12 6 IO L22P 6 A5 6 IO L22N 6 B5 6 IO L23P VRN 6 E8 6 IO L23N VRP 6 E7 6 IO L24P CC LC 6 19 6 IO L24N CC IC 6 K9 6 IO L9P CC LC 6 B13 6 IO L9N CC LC 6 B12 6 IO L10P 6 A8 6 IO L10N 6 B8 6 IO L11P 6 E11 6 IO_L11N_6 F11 6 IO_L12P_6 A6 6 IO_L12N_VREF_6 B6 6 IO_L13P_6 H12 6 IO L13N 6 J11 6 IO_L14P_6 B7 6 IO L14N 6 C7 6 IO L15P 6 A10 96 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices
134. 2 AH17 2 IO_L18N_LC_2 AG17 2 IO_L19P_LC_2 AE22 2 IO L19N LC 2 AD21 2 IO L20P LC 2 AE18 2 IO L20N VREF LC 2 AD17 2 IO L21P LC 2 AV22 2 IO L21N LIC 2 AW22 2 IO L22P IC 2 AU18 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 159 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 160 XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 2 IO L22N ILC 2 AT18 2 IO_L23P_VRN_LC_2 AU22 2 IO L23N VRP IC 2 AU21 2 IO L24P CC IC 2 AN18 2 IO_L24N_CC_LC_2 AP17 2 IO_L25P_CC_LC_2 AM23 2 IO L252N CC IC 2 AN22 2 IO L26P LC 2 AW17 2 IO L26N LC 2 AV17 2 IO L27P LC 2 AK23 2 IO LZN LC 2 AL23 2 IO L28P LC 2 AU17 2 IO L28N VREF IC 2 AUI16 2 IO L29P IC 2 AG23 2 IO L29N LC 2 AH23 2 IO_L30P_LC_2 AN17 2 IO L30N LC 2 AM17 2 IO_L31P_LC_2 AH22 2 IO L31N LC 2 AJ22 2 IO L32P LC 2 AK17 2 IO L32N LC 2 AL16 2 IO L33P IC 2 AE23 2 IO L33N LC 2 AF23 2 IO L34P LC 2 AW16 2 IO L34N LC 2 15 2 IO_L35P_LC_2 AC22 2 IO L35N LC 2 AC20 2 IO L36P LC 2 AT16 2 IO_L36N_VREF_LC_2 AT15 2 IO_L37P_LC_2 AU23 2 IO_L37N_LC_2 AV23 2 IO_L38P_LC_2 AR16 2 IO L38N LC 2 AP16 2 IO_L39P_LC_2 AR23 2 IO L39N LC 2 AT23 2 IO L40P CC IC 2 AK16 2 IO L40N CC LC 2 AJ16 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 Septembe
135. 2 AH19 2 IO L8N D0 LC 2 AH18 3 IO LIP GC CC IC 3 H17 3 IO LIN GC CC IC 3 JA7 3 IO L2P GC VRN LC 3 K16 3 IO GC VRP LC 3 L16 3 IO L3P GC LC 3 K18 3 IO L3N GC IC 3 K17 3 IO L4P GC LC 3 J16 3 IO LAN GC VREF LC 3 J15 3 IO_L5P_GC_LC_3 K19 3 IO_L5N_GC_LC_3 J19 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 3 IO_L6P_GC_LC_3 J14 3 IO_L6N_GC_LC_3 K14 3 IO L7P GC LC 3 H19 3 IO L7N GC LC 3 H18 3 IO L8P GC LC 3 L15 3 IO L8N GC LC 3 L14 4 IO L1P GC LC 4 AD21 4 IO GC LC 4 AD20 4 IO L2P GC LC 4 AF16 4 IO I2N GC LC 4 AE16 4 IO GC LC 4 AE21 4 IO L3N GC LC 4 AF21 4 IO L4P GC LC 4 AE18 4 IO GC VREF IC 4 AE17 4 IO L5P GC LC 4 AF20 4 IO L5N GC LC 4 AF19 4 IO LoP GC LC 4 AGI17 4 IO L6N GC LC 4 AG16 4 IO L7P GC VRN LC 4 AD19 4 IO L7N GC VRP LC 4 AE19 4 IO L8P GC CC IC 4 AF18 4 IO L8N GC CC IC 4 AG18 5 IO ADC7 5 H24 5 IO L1N ADC7 5 J24 5 IO 2 ADC6 5 E23 5 IO ADC6 5 F23 5 IO L3P ADC5 5 E24 5 IO ADC5 5 F24 5 IO 5 G23 5 IO VREF 5 H23 5 IO 5
136. 26 N A VCCINT AB26 N A VCCINT AF26 N A VCCINT AH26 N A VCCINT AK26 N A VCCINT AM26 N A VCCINT G27 N A VCCINT N27 N A VCCINT R27 N A VCCINT AE27 N A VCCINT AG27 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 195 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A VCCINT AJ27 N A VCCINT K28 N A VCCINT M28 N A VCCINT T28 N A VCCINT V28 N A VCCINT AH28 N A VCCINT N29 N A VCCINT AA29 N A VCCINT AL29 N A VCCINT F30 N A VCCINT T30 N A VCCINT AD30 N A VCCINT AP30 N A VCCINT W31 N A VCCINT AG31 N A VCCINT H32 N A VCCINT M32 N A VCCINT AB32 N A VCCINT AK32 N A VCCINT R33 N A VCCINT AE33 Notes 1 This voltage is also referred to as Vcc cowric in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable 196 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package FF1517 Flip Chip Fine Pitch BGA Package As shown in Table 2 8 Virtex 4 XC4VFX140 and XC4VFX100 devices are available in the FF1517 flip chip fine pitch BGA package The No Connect column in Table 2 8 shows pins th
137. 26 N A VCCINT AK26 N A VCCINT N27 N A VCCINT R27 N A VCCINT AC27 N A VCCINT AE27 N A VCCINT AG27 N A VCCINT AJ27 N A VCCINT P28 N A VCCINT T28 N A VCCINT Y28 N A VCCINT AH28 N A VCCINT N29 N A VCCINT AJ29 N A VCCINT W31 N A VCCINT AJ31 N A VCCINT AB32 N A VCCINT P34 Notes 1 This voltage is also referred to as Vcc conric in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 239 Chapter 2 Pinout Tables XILINX 240 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Chapter 3 Pinout Diagrams Summary This chapter provides pinout diagrams for each Virtex 4 FPGA package device combination Note that multi function I O pins are represented in these diagrams by symbols for only one of the pin s available functions with precedence given to functionality in the following order VREF VRP or VRN SM1 SM7 ADC1 ADC7 D0 D31 GC cc LC For example a pin description such as IO_L25N_CC_SM1_LC_7 is represented with an SM1 SM7 symbol a pin description such as IO GC VREF LC 4 is represented with a VREF symbol and a pin description such as IO L8P D17 CC LC 1 is represented with a D0 D31 symbol SF363 Pac
138. 37 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 238 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices N A VCCINT U19 N A VCCINT W19 N A VCCINT AC19 N A VCCINT AE19 N A VCCINT M20 N A VCCINT P20 N A VCCINT T20 N A VCCINT V20 N A VCCINT AB20 N A VCCINT AD20 N A VCCINT AF20 N A VCCINT AH20 N A VCCINT R21 N A VCCINT U21 N A VCCINT AA21 N A VCCINT AC21 N A VCCINT AE21 N A VCCINT M22 N A VCCINT P22 N A VCCINT T22 N A VCCINT V22 N A VCCINT AB22 N A VCCINT AD22 N A VCCINT AK22 N A VCCINT R23 N A VCCINT U23 N A VCCINT AC23 N A VCCINT AE23 N A VCCINT AG23 N A VCCINT P24 N A VCCINT T24 N A VCCINT AD24 N A VCCINT AF24 N A VCCINT L25 N A VCCINT N25 N A VCCINT R25 N A VCCINT U25 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number VCCINT W25 N A VCCINT AE25 N A VCCINT AG25 N A VCCINT AJ25 N A VCCINT P26 N A VCCINT T26 N A VCCINT AD26 N A VCCINT AF26 N A VCCINT AH
139. 38 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 12 IO_L8P_CC_LC_12 AB3 12 IO_L8N_CC_LC_12 AA3 12 IO L9P CC LC 12 AB7 12 IO L9N CC LC 12 AB6 12 IO L10P 12 6 12 IO L10N 12 Y6 12 IO L11P 12 AG3 12 IO L11N 12 AF3 12 IO L12P 12 W9 12 IO_L12N_VREF_12 Y9 12 IO L13P 12 9 12 IO L13N 12 AA8 12 IO L14P 12 ACA 12 IO L14N 12 AC3 12 IO L15P 12 AF6 12 IO L15N 12 AE6 12 IO L16P 12 AD5 12 IO L16N 12 AD4 12 IO_L25P_CC_LC_12 AK6 12 IO L25N CC LIC 12 AJ6 12 IO L26P 12 AM3 12 IO L26N 12 AL3 12 IO L27P 12 AG8 12 IO L27N 12 AG7 12 IO L28P 12 AD7 12 IO L28N VREF 12 AD6 12 IO L29P 12 AM6 12 IO L29N 12 AL6 12 IO L30P 12 12 IO L30N 12 AG5 12 IO L31P 12 AC10 12 IO L31N 12 AC9 12 IO L32P 12 5 12 IO L32N 12 AH5 0 VCCO Y15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 139 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 140 XILINX Table 2 6 FF1152 Package FX40 FX60 and
140. 4 1 IO L36P LC 1 J17 1 IO L36N VREF LC 1 K17 1 IO_L37P_LC_1 D25 1 IO_L37N_LC_1 C25 1 IO_L38P_LC_1 D17 1 IO L38N LC 1 E17 1 IO L39P IC 1 B25 1 IO L39N LC 1 A25 1 IO L40P LC 1 B17 1 IO L40N LC 1 C17 2 IO LIP D15 CC IC 2 AN25 2 IO LIN D14 CC LIC 2 AN24 2 IO L2P D13 IC 2 AT14 2 IO I2N D12 LC 2 AR14 2 IO L3P D11 LC 2 AV24 158 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 2 IO L3N D10 LC 2 AW24 2 IO 4 D9 LC 2 AV15 2 IO LAN D8 VREF IC 2 AUI15 2 IO L5P D7 LC 2 AL24 2 IO L5N D6 LC 2 AM25 2 IO L6P D5 LC 2 AP15 2 IO L6N D4 LIC 2 AP14 2 IO_L7P_D3_LC_2 AJ24 2 IO L7N D2 IC 2 AK24 2 IO L8P D1 LC 2 AH15 2 IO D0 LC 2 AG16 2 IO L9P GC CC IC 2 22 2 IO_LIN_GC_CC_LC 2 AR22 2 IO L10P GC IC 2 AM18 2 IO L10N GC IC 2 AL18 2 IO_L11P_GC_LC_2 AT21 2 IO L11N GC LC 2 AR21 2 IO L12P GC IC 2 AT19 2 IO L12N GC VREF LC 2 AR19 2 IO L13P GC LIC 2 AP21 2 IO L13N GC IC 2 AN20 2 IO L14P GC IC 2 AP19 2 IO L14N GC IC 2 AR18 2 IO L15P GC LC 2 AM21 2 IO L15N GC IC 2 AM20 2 IO L16P GC IC 2 AU20 2 IO L16N GC IC 2 AT20 2 IO L17P LC 2 AG22 2 IO L17N LC 2 AF21 2 IO L18P LC
141. 5 F25 5 IO L6N ADC3 5 F26 5 IO L7P ADC2 5 D24 5 IO L7N ADC2 5 D25 5 IO L8P CC ADC1 LC 5 B27 5 IO L8N CC ADC1 LC 5 C27 5 IO L17P 5 C22 5 IO L17N 5 B22 5 IO L18P 5 A30 5 IO L18N 5 B30 5 IO L19P 5 K24 5 IO L19N 5 J24 5 IO L20P 5 C29 5 IO L20N VREF 5 C30 5 IO L21P 5 B21 5 IO L21N 5 A21 5 IO L22P 5 E28 5 IO L22N 5 F28 5 IO L23P VRN 5 E22 5 IO L23N VRP 5 D22 5 IO L24P CC LC 5 A31 5 IO L24N CC LC 5 B31 5 IO L9P CC LC 5 F23 5 IO L9N CC LC 5 E23 5 IO L10P 5 D26 5 IO L10N 5 E26 5 IO L11P 5 F24 5 IO 5 E24 5 IO L12P 5 D27 94 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SXS5 Devices 5 IO L12N VREF 5 E27 5 IO L13P 5 G23 5 IO L13N 5 H24 5 IO L14P 5 A28 5 IO L14N 5 A29 5 IO L15P 5 B25 5 IO L15N 5 C25 5 IO L16P 5 J25 5 IO L16N 5 K26 5 IO L25P CC LC 5 B28 5 IO L25N CC IC 5 C28 5 IO L26P 5 D30 5 IO L26N 5 D31 5 IO L27P 5 G27 5 IO 27 5 G28 5 IO L28P 5 F29 5 IO L28N VREF 5 F30 5 IO_L29P_5 D29 5 IO L29N 5 E29 5 IO L30P 5 L25 5 IO L30N 5 L26 5 IO L31P 5 B32 5 IO L31N 5 B33 5 IO L32P 5 E31 5 IO L32N 5 F31 6 IO L1P 6 D12 6 IO LIN 6 C1
142. 6 13 IO L14P 13 W32 13 IO L14N 13 Y33 13 IO 15 13 W35 13 IO L15N 13 W34 13 IO L16P 13 Y34 13 IO L16N 13 AA34 216 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 13 IO L25P CC IC 13 AC35 13 IO L25N CC IC 13 AC34 13 IO L26P 13 AA26 13 IO L26N 13 Y26 13 IO L27P 13 AA31 13 IO L27N 19 AA30 13 IO L28P 13 AC25 13 IO L28N VREF 13 AC24 13 IO L29P 13 AB28 13 IO L29N 13 AB27 13 IO L30P 13 AB26 13 IO L30N 13 AB25 13 IO L31P 13 AA29 13 IO L31N 13 Y29 13 IO L32P 13 AA28 13 IO L32N 13 Y27 14 IO L17P 14 AF4 14 IO L17N 14 AE4 14 IO_L18P_14 AC5 14 IO L18N 14 AB5 14 IO L19P 14 W17 14 IO L19N 14 W16 14 IO L20P 14 AD4 14 IO L20N VREF 14 AC4 14 IO_L21P_14 W14 14 IO L21N 14 Y14 14 IO L22P 14 AB7 14 IO L22N 14 AA6 14 IO 1250 VRN 14 W12 14 IO L23N VRP 14 W11 14 IO L24P CC LC 14 AF3 14 IO L24N CC LC 14 AE3 14 IO L1P 14 U6 14 IO L1N 14 U5 14 IO_L2P_14 V3 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 217 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued
143. 60 8 10 112 1 3456789 816 18 920 29 2426 28 030 327734 13 15 17 19 21 23 25 27 29 31 33 A A B B C 10 10 10 D 10 10 10 9 9 D E 10101010 9 9 9 E F 10 10110110 99 F G 10 10 10 10 9 9 9 9 G H 1010 10 10 959 99 919191 H J 110 10 10110110 9 9 9 9 9 9 J K 10 10 10 10 9 99 99 99 K L 10 10 10 1010 10 10 919199 99 L M 10 10 10 1010110110 10 919199 9191919 10 10 10110 10 10 9 9 9 9 9 9 N P 10110110 1011010110 9 9 9 9 9 P R 10 10 9 919 919 R T 10 10 T U U V V WwW 11 11 Ww Y 1211212112 12 11 11 Y AA 12 12 12 12 12 1111 11 11 1111 11 AA AB 12142 12 12 12 12 11114 11114 11 11 12 12 12 12 1211212112 11 1111 11 11 11 11 11 AC AD 1212 12 12 12 12 1111 11111 11 11 11 AD AE 12 12 12 12 12 12 12 11 1111 11 11 AE AF 42 12 12 12 12 12 11 11 11 1111 AF AG 12 12 12 12 12 12 12 11 11 11 11 12 12 12 12 11 11 11 11 AH AJ 11212 1111 11 11 AJ AK 212112 1111 11 11 AK AL 12 12 Ji 11 11 AL AM 12112112 1111 11 AM AN AN AP AP 131445164718 49205 229374 9528572849303 324494 ug075 05 color2 122104 42345 87 8 g 105 12
144. 68 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 Bank Pin Description Pin Number 9 IO L22P 9 K36 9 1 22 9 L36 9 IO L23P VRN 9 H39 9 IO L23N VRP 9 J39 9 IO_L24P_CC_LC_9 M33 9 IO_L24N_CC_LC_9 N32 9 IO_L1P_9 D34 9 IO LIN 9 D35 9 IO L2P 9 C37 9 IO I2N 9 C38 9 IO L3P 9 E34 9 IO L3N 9 F34 9 IO 9 F35 9 IO LAN VREF 9 G35 9 IO L5P 9 D36 9 IO L5N 9 D37 9 IO L6P 9 H33 9 IO L6N 9 H34 9 IO L7P 9 E36 9 IO L7ZN 9 F36 9 IO L8P CC LC 9 C39 9 IO L8N CC IC 9 D39 9 IO L9P CC LC 9 J32 9 IO_LIN_CC_LC_9 K32 9 IO L10P 9 G36 9 IO L10N 9 G37 9 IO L11P 9 E37 9 IO L1IN 9 E38 9 IO L12P 9 H35 9 IO L12N VREF 9 J35 9 IO L13P 9 M30 9 IO L13N 9 M31 9 IO L14P 9 E39 9 IO L14N 9 F39 9 IO L15P 9 J34 9 IO L15N 9 K34 9 IO L16P 9 F38 9 IO L16N 9 G38 169 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 9 IO_L25P_CC_
145. 7 UG075 v3 3 September 19 2008 Chapter 4 Mechanical Drawings XILINX 278 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Chapter 5 Thermal Specifications Summary Introduction This chapter provides thermal data associated with Virtex 4 FPGA packages The following topics are discussed e Introduction e Virtex 4 FPGA Power Management Strategy e Some Thermal Management Options Support for Compact Thermal Models CTM e References Virtex 4 devices are offered exclusively in thermally efficient flip chip BGA packages This FPGA family s three product lines have different thermal needs The LX devices are the base family members with traditional Virtex II FPGA features implemented in the smaller process technology The FX and SX family members take system integration a few steps further with the incorporation of embedded circuits on top of the base FPGA fabric Similar to Virtex II FPGAs all Virtex 4 family members feature versatile SelectIO resources that support a variety of I O standards on board digitally controlled impedance DCI and many other popular features contained in earlier Virtex FPGA products In addition the FX family incorporates faster RocketIO multi gigabit transceivers MGTs and one or more embedded PowerPC devices The SX devices include an embedded DSP The extent of system integration in a fully configured design that is
146. 7 N A VCCINT V7 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices N A VCCINT J8 N A VCCINT L8 N A VCCINT F9 N A VCCINT V9 N A VCCINT J10 N A VCCINT R10 N A VCCINT L12 N A VCCINT R12 N A VCCINT P13 N A VCCINT T13 N A VCCINT L14 N A VCCINT N14 N A VCCINT M15 N A VCCINT T15 N A VCCINT M17 N A VCCINT V17 N A VCCINT J18 N A VCCINT T19 N A VCCINT V19 N A VCCINT J20 N A VCCINT L20 N A VCCINT Y21 N A VCCINT R22 N A VCCINT U22 Notes 1 This voltage is also referred to as Vcc cowric in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 69 Chapter 2 Pinout Tables XILINX FF676 Flip Chip Fine Pitch BGA Package As shown in Table 2 4 Virtex 4 XC4VLX15 and XC4VLX25 devices are available in the FF676 flip chip fine pitch BGA package The No Connect column in Table 2 4 shows pins that are not available in LX15 devices To be assured of having the ve
147. 7 AA16 7 VCCO 7 AD17 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 83 Chapter 2 Pinout Tables 84 XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee 7 VCCO_7 U18 7 VCCO 7 Y19 7 VCCO 7 AC20 7 VCCO 7 AF21 7 VCCO 7 W22 7 VCCO_7 AB23 7 VCCO_7 AE24 8 VCCO_8 VCCO_8 AB3 8 VCCO_8 AE4 8 VCCO_8 AA6 8 VCCO_8 AD7 8 VCCO_8 U8 8 VCCO_8 Y9 8 VCCO_8 AC10 8 VCCO_8 AF11 9 VCCO_9 N20 NC 9 VCCO_9 T21 NC 9 VCCO_9 122 NC 9 VCCO_9 M23 NC 9 VCCO_9 R24 NC 9 VCCO_9 H25 NC 9 VCCO_9 L25 NC 9 VCCO_9 V25 NC 9 VCCO_9 AA26 NC 10 VCCO_10 F1 NC 10 VCCO 10 T1 NC 10 VCCO 10 J2 NC 10 VCCO 10 W2 NC 10 VCCO_10 M3 NC 10 VCCO_10 R4 NC 10 VCCO_10 V5 NC 10 VCCO_10 L6 NC 10 VCCO_10 P7 NC N A VREFN_SM AE18 NC VREFP_SM 9 7 NC www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee N A AVDD SM AE16 NC N A VN SM AF18 NC N A VP SM 2 A
148. 8 XILINX Virtex 4 FPGA Packaging and Pinout Specification www xilinx com Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued FF668 Flip Chip Fine Pitch BGA Package No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 5 IO_L10P_5 B24 5 IO L10N 5 B23 5 IO L11P 5 F18 5 IO L11N 5 E18 5 IO L12P 5 E21 5 IO L12N VREF 5 D21 5 IO L13P 5 A20 5 IO L13N 5 A19 5 IO L14P 5 D22 5 IO L14N 5 C22 5 IO L15P 5 A22 5 IO L15N 5 A21 5 IO L16P 5 D24 5 IO L16N 5 C24 5 IO L25P CC LC 5 D26 5 IO L25N CC LC 5 D25 5 IO L26P 5 H22 5 IO L26N 5 H21 5 IO L27P 5 E25 5 IO 127 5 E24 5 IO L28P 5 G24 5 IO L28N VREF 5 G23 5 IO L29P 5 F26 5 IO L29N 5 E26 5 IO L30P 5 H24 5 IO L30N 5 H23 5 IO L31P 5 G26 5 IO L31N 5 G25 5 IO_L32P_5 H26 5 IO_L32N_5 H25 6 IO L1P 6 D10 6 IO 6 C10 6 1 12 6 D9 6 IO I2N 6 C8 6 IO L3P 6 A8 UG075 v3 3 September 19 2008 35 Chapter 2 Pinout Tables XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 6 IO L3N 6 A7 6 IO 6 D8 6 IO VREF 6 D7 6
149. 8 6 IO L10P 6 A7 6 IO L10N 6 B7 6 IO L11P 6 C7 6 IO L11N 6 B6 6 IO L12P 6 19 6 IO L12N VREF 6 H8 6 IO L13P 6 A5 6 IO L13N 6 B5 6 IO L14P 6 D8 6 IO L14N 6 E8 6 IO_L15P_6 A4 6 IO L15N 6 A3 6 IO L16P 6 C6 6 IO L16N 6 D6 6 IO L25P CC LC 6 D4 6 IO L25N CC IC 6 D3 6 IO L26P 6 F5 6 IO L26N 6 F4 6 IO L27P 6 B2 6 IO L27N 6 C1 6 IO L28P 6 K10 6 IO L28N VREF 6 L9 6 IO L29P 6 E3 6 IO L29N 6 F3 6 IO L30P 6 H6 6 IO L30N 6 G5 6 IO L31P 6 G4 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 75 Chapter 2 Pinout Tables XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number 6 IO L31N 6 H4 6 IO L32P 6 16 6 IO L32N 6 15 7 IO L25P CC SM7 IC 7 AB16 7 IO L25N CC SM7 LC 7 AA17 7 IO 126 SM6 7 AF20 7 IO L26N SM6 7 AE20 7 IO L27P SM5 7 Y16 7 IO L27N SM5 7 Y17 7 IO L28P 7 V17 7 IO L28N VREF 7 U17 7 IO L29P SMA 7 AB17 7 IO L29N SMA 7 AA18 7 IO_L30P_SM3_7 AD18 7 IO L30N SM3 7 AD19 7 IO L31P SM2 7 AC16 7 IO L31N SM2 7 AD16 7 IO L32P SM1 7 AC17 7 IO_L32N_SM1_7 AC18 7 IO L17P 7 AF22 7 IO L17N 7 AF23 7 IO L18P 7 AA20 7 IO L18N 7 AB21 7 IO L19P 7 Y18 7 IO L19N 7 AA19 7 IO L20P 7 W18 y IO L20N VREF 7 V18 y IO L21P 7 AE21 7 IO L21N 7 AE22 7 IO L22P 7 AD20 7 IO_L22
150. 8 IO_L15P_8 Y8 8 IO L15N 8 Y7 8 IO L16P 8 AF5 8 IO L16N 8 AE5 9 IO L17P 9 N24 NC 9 IO L17N 9 P23 NC 9 IO L18P 9 P24 NC 9 IO L18N 9 25 NC 9 1 19 9 R26 NC 9 IO_L19N_9 P26 NC 9 IO L20P 9 R20 NC 9 IO L20N VREF 9 R21 NC 9 IO L21P 9 R22 NC 9 IO L21N 9 R23 NC 9 IO L22P 9 T25 NC 9 IO L22N 9 R25 NC 9 IO L23P VRN 9 T23 NC 9 IO L23N VRP 9 T24 NC Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 79 Chapter 2 Pinout Tables XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number pean 9 IO L24P CC IC 9 U22 9 IO L24N CC IC 9 T22 9 IO LIP 9 121 9 IO LIN 9 21 9 1 12 9 H22 9 IO I2N 9 H23 9 IO L3P 9 G24 9 IO L3N 9 G25 9 IO 9 M20 9 IO LAN VREF 9 M21 9 IO L5P 9 J23 9 IO L5N 9 K22 9 IO L6P 9 J24 9 IO L6N 9 H24 9 IO L7P 9 K23 9 IO 9 L23 9 IO L8P CC IC 9 125 9 IO L8N CC IC 9 126 9 IO L9P CC IC 9 G26 9 IO L9N CC IC 9 H26 9 IO L10P 9 M22 9 IO L10N 9 N21 9 IO L11P 9 K25 9 IO L11IN 9 K26 9 IO L12P 9 L24 9 IO L12N VREF 9 M24 9 IO L13P 9 N22 9 IO L13N 9 N23 9 IO L14P 9 M26 9 IO 9 N26 9 IO L15P 9 L26 9 IO L15N 9 M25 9 IO L16P 9 20 9 IO L16N 9 21 9 IO L25P CC IC 9 U24 9 IO L25N CC IC 9 U25 9 IO L26P 9 V26 80 www xilinx com Virtex 4 FPGA Packaging and Pinou
151. 8 LC 1 N24 1 IO L8P D17 CC IC 1 G15 1 IO L8N D16 CC LC 1 H15 1 IO L9P GC IC 1 M21 1 IO L9N GC IC 1 N20 1 IO L10P GC IC 1 N19 1 IO L10N GC LIC 1 P19 1 IO L11P GC LC 1 F21 1 IO L11N GC IC 1 E21 1 IO L12P GC IC 1 R18 1 IO L12N GC VREF LC 1 P17 1 IO L13P GC IC 1 G22 1 IO GC LIC 1 G21 1 IO L14P GC IC 1 N18 1 IO L14N GC IC 1 M17 1 IO L15P GC IC 1 122 1 IO L15N GC LC 1 H22 1 IO L16P GC CC IC 1 L18 1 IO L16N GC CC LC 1 M18 1 IO L17P CC LC 1 N23 1 IO L17N CC LC 1 N22 1 IO L18P VRN LC 1 K18 1 IO L18N VRP LC 1 K17 1 IO L19P LC 1 M23 1 IO L19N LC 1 L23 1 IO L20P LC 1 C18 1 IO VREF IC 1 C17 1 IO L21P LC 1 G23 1 IO L21N LC 1 F23 1 IO L22P LC 1 H17 1 IO_L22N_LC_1 JA7 1 IO L23P LC 1 E23 198 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 1 IO_L23N_LC_1 E22 1 IO L24P LC 1 G17 1 IO L24N LC 1 G16 2 IO D15 CC IC 2 AM25 2 IO LIN D14 CC LC 2 AN25 2 IO L2P D13 LC 2 AL16 2 IO D12 LC 2 AK16 2 IO_L3P_D11_LC_2 AN24 2 IO L3N D10 LC 2 AM23 2 IO 4 D9 LC 2 AJ16 2 IO D8 VREF IC 2 AH15 2 IO L5P D7 LC 2 AL24 2 IO L5N D6 IC 2 AL23 2
152. 8 WS8 8 VCCO 8 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 45 Chapter 2 Pinout Tables 46 lt XILINX Table 2 2 FF668 Package LX15 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 8 VCCO 8 AE8 8 VCCO_8 Wo 9 VCCO 9 M18 9 VCCO 9 K19 9 VCCO 9 U19 9 VCCO 9 L22 9 VCCO 9 T22 9 VCCO 9 L25 9 VCCO 9 T25 9 VCCO 9 P26 10 VCCO 10 N1 10 VCCO 10 12 10 VCCO 10 2 10 VCCO 10 L5 10 VCCO 10 T5 10 VCCO 10 K8 10 VCCO 10 U8 10 VCCO_10 R9 VREFN_SM AE15 N A VREFP_SM AE16 N A AVDD SM 9 AF17 N A VN 8M AF15 N A VP_SM AF16 N A AVSS SM 2 AE17 N A GND B1 N A GND P1 N A GND GND A2 N A GND B2 N A GND AE2 N A GND AF2 N A GND C3 N A GND Ja N A GND V3 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued FF668 Flip Chip Fine Pitch BGA Package Bank Pin Description Pin Number LX15 e I GND F6 N A GND N6 N A
153. 9 19 21 23 25 27 29 31 38 B5 E EBB ABEBnn n n n n n n nj n nj nin njn n n n njn n n n EE NM s c D I0DOONOOOOLI9SC ONOOS e J0000ROOM C E F eB3ORIOOOOLIOOOGRNI GGGQGLDIOOSONOOOOPQLIOOOBRO BROOCODOCSOCONCOOSDOODONSSSSO OCONOCEE H J BBOOCOCTOCOONOCOOCHOFABONZOOCOOCOOCONSE BiBO 1006 0NIOOOOOLDM dL CeOLIOO6MOSROOONMIX M eEOCOONSOCOCOCHU Sd TB Wa IOOoOoWOoOoOoOoLOcNMIX N METYIBIPIONIORMIOOLIOOOOMB P T INTR ID am um Io cooNOOMN R iMOOOONOOOCELDM A MBPIICW PIE WPDNOSOOOOLDIES T OBIONOOOOLI AMT WO ad 5 TE Td COL IOOCBMIV u 1 LE adt v m 6 Ww DUO w omo OOOC TIT ET M WAR WOSOOOO OHO v o9NOOOCOLIOOMOBIOIKLDILUWL WIETWETREE TO OOLIOOOORBIPIO AA OOODL WI ad PORRO Ld TL AB eIMOOONSOWOOLDOOWW Ww Wt adam 1 OWORIOXOOOLIOme Ac eENOOOOLI GOOONOMMIAILIImeoomeceoormnooooNoO AD VINO OLJOOMcoSIO
154. 9 IO L16N 9 G33 9 IO L25P CC IC 9 R22 9 IO L25N CC LC 9 R23 9 IO L26P 9 K32 9 IO L26N 9 K33 9 IO L27P 9 N27 9 IO L27N 9 P27 9 IO L28P 9 M30 9 IO L28N VREF 9 M31 9 IO L29P 9 194 9 IO L29N 9 K34 9 IO L30P 9 N29 9 IO L30N 9 N30 9 IO L31P 9 L33 9 IO L31N 9 L34 9 IO L32P 9 M32 102 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Ne ii Number LX60 and SX55 Devices 9 IO L32N 9 M33 10 IO L17P 10 F1 10 IO_L17N_10 G1 10 IO_L18P_10 J4 10 IO L18N 10 K4 10 IO L19P 10 H3 10 IO L19N 10 H2 10 IO L20P 10 P10 10 IO L20N VREF 10 9 10 IO L21P 10 M7 10 IO L21N 10 N7 10 IO L22P 10 L5 10 IO L22N 10 L4 10 IO_L23P_VRN_10 J2 10 IO L23N VRP 10 JA 10 IO L24P CC LC 10 R11 10 IO L24N CC LC 10 T11 10 IO_L1P_10 C4 10 IO L1N 10 C3 10 IO L2P 10 F5 10 IO 10 G5 10 IO L3P 10 D4 10 1 10 E4 10 IO 10 M10 10 IO LAN VREF 10 L9 10 IO L5P 10 N13 10 IO L5N 10 N12 10 IO L6P 10 F4 10 IO L6N 10 F3 10 IO L7P 10 C2 10 IO 10 D2 10 IO L8P CC LC 10 D1 10 IO L8N CC LC 10 E1 10 IO L9P CC LC 10 E3 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 103 UG075 v3 3 September
155. A 10 IO L12N VREF 10 M3 10 IO L13P 10 M6 10 IO L13N 10 M5 10 IO L14P 10 N3 10 IO L14N 10 N2 10 IO L15P 10 N5 10 IO L15N 10 N4 10 IO L16P 10 P3 10 IO L16N 10 P2 10 IO L25P CC IC 10 R8 10 IO L25N CC IC 10 R7 10 IO_L26P_10 T4 10 IO L26N 10 T3 10 IO L27P 10 T7 10 IO L27N 10 T6 10 IO L28P 10 U3 10 IO L28N VREF 10 U2 10 IO L29P 10 v4 10 IO L29N 10 U4 10 IO L30P 10 V2 10 IO L30N 10 V1 10 IO L31P 10 T8 10 IO L31N 10 U7 10 IO L32P 10 U6 10 IO L32N 10 U5 0 VCCO 0 V12 0 VCCO 0 J15 1 VCCO_1 Ell 1 VCCO_1 E16 44 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued FF668 Flip Chip Fine Pitch BGA Package No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 2 VCCO_2 AB11 2 VCCO 2 AB16 3 VCCO 3 B11 3 VCCO_3 B16 4 VCCO_4 4 VCCO_4 AD15 5 VCCO_5 H18 5 VCCO_5 B19 5 VCCO_5 E19 5 VCCO_5 H19 5 VCCO_5 J19 5 VCCO 5 B22 5 VCCO 5 F22 5 VCCO 5 F25 6 VCCO 6 F2 6 VCCO 6 B5 6 VCCO 6 F5 6 VCCO 6 B8 6 VCCO 6 E8 6 VCCO 6 J8 6 VCCO 6 H9 6 VCCO 6 H10 7 VCCO 7 W17 7 VCCO_7 W18 7 VCCO 7 V19 7 VCCO 7 AB19 7 VCCO 7 AE19 7 VCCO 7 AA22 7 VCCO 7 AE22 7 VCCO_7 AA25 8 VCCO_8 AA2 8 VCCO_8 AAS 8 VCCO_8 AE5 8 VCCO 8 V8 8 VCCO
156. A 104 AB38 NC www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number GNDA 104 AD38 NC N A GNDA_104 AG38 NC N A GNDA_104 AK38 NC N A GNDA_104 W39 NC N A GNDA_105 AV35 N A GNDA_105 AL38 N A GNDA_105 AN38 N A GNDA_105 AR38 N A GNDA_105 AW38 N A GNDA_105 AK39 N A GNDA_105 AV39 N A GNDA_105 AW20 N A GNDA_105 AV23 N A GNDA_105 AV26 N A GNDA_106 AW26 N A GNDA_106 AV27 N A GNDA_106 AV29 N A GNDA_106 AV31 N A GNDA_106 AW32 N A GNDA 106 AV33 N A GNDA_106 AW35 N A GNDA_109 AV9 N A GNDA_109 AV11 N A GNDA_109 AV13 N A GNDA_109 AV14 N A GNDA_109 AW14 N A GNDA_109 AV17 N A GNDA_109 AV20 N A GNDA_110 AK1 N A GNDA 110 AV1 N A GNDA 110 AL2 N A GNDA 110 AN2 N A GNDA 110 AR2 N A GNDA 110 AW2 N A GNDA 110 AV5 N A GNDA 110 AW5 N A GNDA 110 AV7 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 229 Chapter 2 Pinout Tables 230 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in
157. A3 113 VTTXB 113 D2 113 TXPPADB_113 Cl 113 TXNPADB_113 D1 113 AVCCAUXRXB_113 G2 113 RXPPADB_113 F1 113 VTRXB 113 E1 113 RXNPADB 113 G1 113 MGTCLK P 113 JA 113 MGTCLK N 113 K1 114 AVCCAUXRXA 114 B17 NC NC 114 RXPPADA 114 A18 NC NC 114 VTRXA 114 A16 NC NC 114 RXNPADA 114 A17 NC NC 114 AVCCAUXMCT 114 B10 NC NC 114 AVCCAUXTX 114 B13 NC NC 114 VTTXA 114 B15 NC NC 114 TXPPADA 114 A15 NC NC 114 TXNPADA 114 A14 NC NC 146 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 114 VITXB_114 B12 NC NC 114 TXPPADB_114 A13 NC NC 114 TXNPADB 114 A12 NC NC 114 AVCCAUXRXB 114 B8 NC NC 114 RXPPADB 114 A10 NC NC 114 VTRXB 114 All NC NC 114 RXNPADB_114 A9 NC NC 101 GNDA 101 A19 NC NC 101 GNDA 101 B20 NC NC 101 GNDA 101 B22 NC NC 101 GNDA 101 B24 NC NC 101 GNDA 101 B27 NC NC 101 GNDA 101 B29 NC NC 102 GNDA 102 A30 102 GNDA 102 B31 102 GNDA 102 A33 102 GNDA 102 B33 102 GNDA 102 C33 102 GNDA 102 E33 102 GNDA 102 H33 102 GNDA 102 L33 102 GNDA 102 M33 102 GNDA 102 N33 102 GNDA 102 P33 102 GNDA_102 B34 102 GNDA_102 L34 1
158. A5 14 IO L25N CC IC 14 AAA 14 IO L26P 14 AAI 14 IO_L26N_14 Y1 14 IO_L27P_14 AB3 14 IO L27N 14 AA3 14 IO L28P 14 AB2 14 IO L28N VREF 14 AB1 14 IO L29P 14 AA6 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 111 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 112 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description p No Connects In 1x40 Number LX60 and 9 55 Devices 14 IO_L29N_14 Y6 NC 14 IO L30P 14 Y8 NC 14 IO L30N 14 Y7 NC 14 IO L31P 14 Y9 NC 14 IO L31N 14 w9 NC 14 IO L32P 14 W11 NC 14 IO_L32N_14 W10 NC 0 VCCO U14 0 VCCO T17 0 VCCO W18 0 VCCO V21 1 VCCO 1 G14 1 VCCO_1 K15 1 VCCO 1 C16 1 VCCO 1 N16 1 VCCO 1 B19 1 VCCO 1 M19 1 VCCO 1 E20 1 VCCO 1 H21 2 VCCO 2 AG14 2 VCCO_2 AK15 2 VCCO 2 AC16 2 VCCO_2 AN16 2 VCCO_2 AB19 2 VCCO 2 AM19 2 VCCO 2 AE20 2 VCCO 2 AH21 3 VCCO 3 F17 3 VCCO 3 J18 4 VCCO_4 AF17 4 VCCO_4 AJ18 5 VCCO 5 A22 5 VCCO 5 D23 5 VCCO 5 G24 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices
159. AE12 8 IO L10P 8 AL9 8 IO_L10N_8 AK9 8 IO L11P 8 ADI 8 IO_L11N_8 1 8 IO L12P 8 AD10 8 IO L12N VREF 8 AD9 8 IO L13P 8 AE14 8 IO L13N 8 AF14 8 IO_L14P_8 AJ9 8 IO_L14N_8 AH9 8 IO_L15P_8 AE13 8 IO_L15N_8 AF13 8 IO L16P 8 AL10 8 IO_L16N_8 AM10 9 IO L17P 9 L31 9 IO_L17N_9 L30 9 IO_L18P_9 J32 9 IO_L18N_9 H32 9 IO_L19P_9 N29 9 IO_L19N_9 N28 132 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber FX60 Devices FX40 Devices 9 IO_L20P_9 N27 9 IO_L20N_VREF_9 M28 9 IO_L21P_9 N30 9 IO L21N 9 M30 9 IO L22P 9 M32 9 IO L22N 9 M31 9 IO L23P VRN 9 P31 9 IO_L23N_VRP_9 P30 9 IO L24P CC LC 9 P27 g IO_L24N_CC_LC_9 P26 9 IO 9 E31 9 IO LIN 9 D31 9 IO L2P 9 D29 9 IO L2N 9 C29 9 IO L3P 9 E32 9 IO L3N 9 F31 9 IO 9 28 9 IO VREF 9 H27 9 IO L5P 9 G30 9 IO L5N 9 F30 9 IO L6P 9 D30 9 IO L6N 9 C30 9 IO L7P 9 G32 9 IO L7N 9 G31 9 IO_L8P_CC_LC_9 F29 9 IO_L8N_CC_LC_9 E29 9 IO_L9P_CC_LC_9 29 9 IO_LIN_CC_LC_9 129 9 IO L10P 9 D32 9 IO L10N 9 C32 9 IO L11P 9 J31 9 IO_L11N_9 J30 9 IO L12P 9 K28 9 IO L12N VREF 9 J27 9 IO_L13P_9 L29 9 IO_L13N_9 L28 9 IO L14P 9 H30
160. AGIT 8 IO L18P 8 AN7 8 IO L18N 8 AM7 8 IO_L19P_8 ANI10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 99 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 100 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SXS5 Devices 8 IO L19N 8 AM10 8 IO L20P 8 AF10 8 IO L20N VREF 8 AE9 8 IO L21P 8 AJA2 8 IO L21N 8 AK12 8 IO L22P 8 AN8 8 IO_L22N_8 AM8 8 IO_L23P_VRN_8 AJ11 8 IO_L23N_VRP_8 AK11 8 IO L24P CC LC 8 AP7 8 IO L24N CC LC 8 AP6 8 IO L1P 8 AL5 8 IO LIN 8 ALA 8 IO L2P 8 AK4 8 IO_L2N_8 AJA 8 IO L3P 8 APA 8 IO L3N 8 AN4 8 IO 8 AD10 8 IO_L4N_VREF_8 AD9 8 IO_L5P_8 AN14 8 IO_L5N_8 AP14 8 IO L6P 8 AJ6 8 IO L6N 8 AJ5 8 IO L7P 8 AK7 8 IO L7N 8 AJ7 8 IO L8P CC LC 8 AN3 8 IO L8N CC LC 8 AN2 8 IO L9P CC LC 8 AK13 8 IO L9N CC LC 8 AL13 8 IO L10P 8 AL6 8 IO L10N 8 AK6 8 IO L11P 8 AL8 8 IO_L11N_8 AK8 8 IO_L12P_8 AH8 8 IO L12N VREF 8 AH7 8 IO L13P 8 AM13 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices
161. AM33 11 IO L28P 11 AJ31 11 IO L28N VREF 11 AJ32 11 IO L29P 11 AB22 11 IO L29N 11 AB23 11 IO L30P 11 AL33 11 IO L30N 11 AL34 11 IO L31P 11 AM31 11 IO L31N 11 AL31 11 IO L32P 11 AJ30 11 IO L32N 11 AH30 12 IO L17P 12 AC9 12 IO L17N 12 AC8 12 IO L18P 12 AG3 12 IO_L18N_12 AF3 12 IO L19P 12 AF6 12 IO L19N 12 AE6 12 IO L20P 12 AF5 12 IO L20N VREF 12 AF4 12 IO L21P 12 106 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Fn No Connects In 1x40 Number LX60 and SX55 Devices 12 IO L21N 12 12 IO 1220 12 AJ2 12 IO L22N 12 AJ1 12 IO L23P VRN 12 AG6 12 IO L23N VRP 12 AG5 12 IO_L24P_CC_LC_12 AE7 12 IO_L24N_CC_LC_12 AD7 12 IO_L1P_12 AB6 12 IO 12 AB5 12 IO L2P 12 AC3 12 IO 12 AC2 12 IO L3P 12 Yn 12 IO L3N 12 AAT 12 IO 12 AD2 12 IO LAN VREF 12 ADI 12 IO L5P 12 Y14 12 IO L5N 12 AA13 12 IO L6P 12 AC5 12 IO L6N 12 ACA 12 IO 17 12 12 IO_L7N_12 12 IO L8P CC LC 12 AAQ 12 IO L8N CC LC 12 AA8 12 IO_L9P_CC_LC_12 Y13 12 IO L9N CC LC 12 Y12 12 IO L10P 12 AE3 12 IO L10N 12 AE2 12 IO L11P 12 AD6 12 IO L11N 12 AD5 12 IO L12P 12 AC7 12 IO_L12N_VREF_12 AB8 12 IO L
162. ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2004 2008 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries The PowerPC name and logo are registered trademarks of IBM Corp and used under license All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Version Revision 08 02 04 1 0 Initial Xilinx release Printed Handbook version 09 03 04 1 1 Added Chapters 2 and 3 10 05 04 1 2 Removed FF1152 package information from Chapters 2 and 3 11 05 04 1 3 Added FF1152 pinout information and revised TDN TDP ADC and SM pin references 11 30 04 2 0 e Revised four pins affecting only XC4VFX100 devices in the FF1152 package e Added FF676 pinout information e Corrected symbol used for pin AN28 in the FF1513 pinout diagram e Added MGT pin definitions to Table 1 3 12 21 04 21 e Changed four VCCO pins to No Connects in Banks 9 and 10 affecting only 4 20 devices in the FF672 package e Added a colorized SelectIO and bank information diagram for each package e Made minor changes to pin definitions in Table 1 3 01 19 05 22 e Corrected pin A9 in the FF1152 package Table 2 6 affecting only XC4VFX100 devices e Corrected the FF1152 pinout diagrams 02 1
163. AUX AK18 N A VCCAUX AAI9 N A VCCAUX W21 N A VCCAUX K22 N A VCCAUX 125 VCCAUX AL25 N A VCCAUX AK28 N A VCCAUX R29 N A VCCAUX M30 N A VCCAUX AB30 N A VCCAUX AE31 N A VCCAUX V32 N A VCCAUX AH32 N A VCCAUX AC33 N A VCCAUX AL33 N A VCCINT AB6 N A VCCINT AF6 N A VCCINT V8 N A VCCINT L9 N A VCCINT L11 N A VCCINT AE11 N A VCCINT AGI N A VCCINT M12 N A VCCINT AD12 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number VCCINT AF12 N A VCCINT L13 N A VCCINT N13 N A VCCINT R13 N A VCCINT U13 N A VCCINT AE13 N A VCCINT AGI13 N A VCCINT K14 N A VCCINT M14 N A VCCINT P14 N A VCCINT T14 N A VCCINT AD14 N A VCCINT AF14 N A VCCINT L15 N A VCCINT N15 N A VCCINT R15 N A VCCINT AA15 N A VCCINT AC15 N A VCCINT AE15 N A VCCINT AGI15 N A VCCINT AJ15 N A VCCINT P16 N A VCCINT T16 N A VCCINT AD16 N A VCCINT AF16 N A VCCINT N17 N A VCCINT R17 N A VCCINT U17 N A VCCINT AC17 N A VCCINT AE17 N A VCCINT T18 N A VCCINT V18 N A VCCINT AB18 N A VCCINT AD18 N A VCCINT AF18 N A VCCINT AH18 N A VCCINT R19 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 2
164. B_110 AF8 N A MGTCLK_P_110 AF10 N A MGTCLK_N_110 AF11 N A RTERM_110 AE10 N A MGTVREF 110 AE12 N A AVCCAUXRXA_112 2 NC N A RXPPADA_112 N1 NC N A VTRXA 112 R1 NC RXNPADA 112 NC N A AVCCAUXMGT 112 AA2 NC N A AVCCAUXTX 112 V2 NC www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices N A VTTXA 112 T2 NC N A TXPPADA 112 T1 NC N A TXNPADA 112 U1 NC N A VTTXB 112 W2 NC N A TXPPADB_112 V1 NC N A TXNPADB 112 W1 NC N A AVCCAUXRXB_112 AB2 NC N A RXPPADB_112 AA1 NC N A VTRXB_112 Y1 NC N A RXNPADB_112 AB1 NC N A AVCCAUXRXA 113 B4 N A RXPPADA 113 A4 N A 115 2 RXNPADA 113 A3 N A AVCCAUXMCGT 113 G2 N A AVCCAUXTX 113 D2 N A 113 C2 N A TXPPADA_113 B1 N A 113 C1 N A VTTXB 113 E2 N A TXPPADB 113 D1 N A TXNPADB_113 E1 N A AVCCAUXRXB 113 H2 N A RXPPADB 113 G1 N A VTRXB_113 F1 N A RXNPADB_113 H1 N A MGTCLK_P_113 K1 N A MGTCLK_N_113 L1 N A GNDA_102 A18 N A GNDA 102 B19 N A GNDA 102 B21 N A GNDA 102 B25 N A GNDA 102 E25 N A GNDA 102 H25 N A GNDA 102 E26 N A GNDA 102 H26 Virtex 4 FPGA Packaging and Pinout
165. CAUXTIX 101 B26 N A 101 B24 N A TXPPADA 101 A24 N A 101 A25 N A VTTXB 101 B27 N A TXPPADB 101 A26 N A TXNPADB 101 A27 N A AVCCAUXRXB 101 B30 N A RXPPADB 101 A29 N A 101 A28 N A RXNPADB 101 A30 N A AVCCAUXRXA 102 B32 N A RXPPADA_ 102 A31 N A 102 A33 N A RXNPADA 102 A32 N A AVCCAUXMGT 102 C38 N A AVCCAUXTX 102 B36 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 102 B34 N A TXPPADA_102 A34 N A TXNPADA_102 A35 N A VTTXB_102 B37 N A TXPPADB_102 A36 N A TXNPADB_102 A37 N A AVCCAUXRXB_102 D38 N A RXPPADB_102 C39 N A VTRXB_102 B38 N A RXNPADB_102 D39 N A MGTCLK_P_102 F39 N A MGTCLK_N_102 G39 N A AVCCAUXRXA_103 K38 N A RXPPADA 103 J39 N A VTRXA_103 L39 N A RXNPADA_103 K39 N A AVCCAUXMGT 103 U38 N A AVCCAUXTX 103 P38 N A VTTXA_103 M38 N A TXPPADA_103 M39 N A TXNPADA_103 N39 N A VTTXB_103 R38 N A TXPPADB_103 P39 N A TXNPADB_103 R39 N A AVCCAUXRXB_103 V38 N A RXPPADB_103 U39 N A VTRXB_103 T39 N A RXNPADB 103 V39 N A AVCCAUXRXA 104 AA38 NC N A RXPPADA_ 104 Y39 NC N A
166. CO_10 T7 10 VCCO_10 M9 10 VCCO_10 R10 11 VCCO 11 Y25 NC 11 VCCO 11 AC26 NC 11 VCCO 11 W28 NC 11 VCCO 11 AB29 NC 11 VCCO 11 AE30 NC 11 VCCO 11 V31 NC 11 VCCO 11 AH31 NC 11 VCCO_11 AA32 NC 12 VCCO_12 AD3 NC 12 VCCO_12 AG4 NC 12 VCCO_12 Y5 NC Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 141 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 142 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 12 VCCO_12 AK5 12 VCCO_12 AC6 12 VCCO_12 AF7 12 VCCO_12 W8 12 VCCO_12 AB9 101 AVCCAUXRXA 101 B21 101 RXPPADA 101 A20 101 VTRXA 101 A22 101 RXNPADA 101 A21 101 AVCCAUXMGT 101 B28 101 AVCCAUXTX 101 B25 101 101 B23 101 101 A23 101 101 A24 101 VTTXB 101 B26 101 TXPPADB 101 A25 101 TXNPADB 101 A26 101 AVCCAUXRXB 101 B30 101 RXPPADB 101 A28 101 VTRXB 101 A27 101 RXNPADB 101 A29 102 AVCCAUXRXA 102 B32 102 102 A31 102 VTRXA 102 C34 102 RXNPADA 102 A32 102 AVCCAUXMGT_102 J33 102 AVCCAUXTX_102 F33 102 102 D33 102 TXPPADA 102 D34 102 102 E34 102 VTTXB 102 G33 102 TXPPADB 102 F34 102 TXNPADB 102 G34 102 AVCCAUXRXB_102 K33 www xilinx com Virtex 4 FPGA Packaging and P
167. CWMLIOONL WIL WIE MEI COO DSIOOOOLIOOOme v JOOOOCBNIOSXMUII MHYIOSIOOOOLIMOOOBNOSIS w nBM OOOOLIOOOQ9oRNOOOOLIMCI4IP MOOLIOOMNORIOOOOMIn v nin OOLIOOOONOOOOLBINIBIUIDINIW IO HIE OONSORSJOOOOLDIOO nn AA nini 100 ORIG9OOOLIOOWMMRNIKId Aw AB in nlONOMOUI JOOOOBNIOIOULD TIL TE TM OSIOOOOLIadeaMONSIOOOl n n ac njinlOCG9OLIOG OORIOO OL WE ETE 0 OL TO OO SOM O OL Shih AD WIL TW TEE TE TE T TOO OOOLIOOOOlnlin AE njinlOONSIOO OIM LIB E TEE RP OF T OO ld OO ODIO ON AF n n OOOCMIL IOO OL METEO TM CIO MIL AG in nlOL I6 9O OOBRJ CMB E Ta Co AONO OO ML TRE 1 Oo AH IdninOOOBNOOOOLIOOOOGRCW 65 10 ese MIL TM OL 1a o OObO njn AJ WIL WM OMNOSNOOOOlInIn AK ad DIDWMOOLIWMOaMe iooooLbd onm AL NIOOOOODNOCOOOLIOOMQ9SOeOoeL veuooeec uuvooomwe AM AN AP QINLIOOOORIOOOOLIOOOOGCRIDOCOLIOOOGRIG eOL10O0O0O0 N9 AR H amp O OOLIOOOORIOGGOLICO OoSIOO AT QOBuUOOOOLIOOOONOOOOCLDIOGIISISINe Oc ODO NOOOOCLM AU OF OO KONCOOCOCHOOCONSISISM NOOCON OCHIOONES
168. D AK5 N A GND C6 N A GND N6 N A GND AC6 N A GND AN6 N A GND F7 N A GND T7 N A GND AF7 N A GND AT7 N A GND J8 N A GND W8 N A GND AJ8 N A GND M9 N A GND AB9 N A GND AM9 N A GND E10 N A GND R10 N A GND AE10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 231 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 232 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices N A GND AR10 N A GND H11 N A GND V11 N A GND AF11 N A GND AH11 N A GND L12 N A GND AA12 N A GND AE12 N A GND AG12 N A GND AL12 N A GND D13 N A GND M13 N A GND P13 N A GND AD13 N A GND AF13 N A GND AP13 N A GND G14 N A GND L14 N A GND N14 N A GND R14 N A GND U14 N A GND AE14 N A GND AG14 N A GND AU14 N A GND K15 N A GND M15 N A GND P15 N A GND T15 N A GND Y15 N A GND AD15 N A GND AF15 N A GND AK15 N A GND C16 N A GND N16 N A GND R16 N A GND AC16 N A GND AE16 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued
169. D U22 N A GND AA22 N A GND AL22 N A GND D23 N A GND P23 N A GND AB23 N A GND AD23 N A GND AP23 N A GND G24 N A GND R24 N A GND U24 N A GND AA24 N A GND AC24 N A GND AG24 N A GND AU24 N A GND K25 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 189 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A GND P25 N A GND T25 N A GND Y25 N A GND AB25 N A GND AF25 N A GND AH25 N A GND AK25 N A GND C26 N A GND L26 N A GND N26 N A GND R26 N A GND AA26 N A GND AC26 N A GND AG26 N A GND AJ26 N A GND AN26 N A GND F27 N A GND K27 N A GND P27 N A GND T27 N A GND AF27 N A GND AH27 N A GND AK27 N A GND AT27 N A GND J28 N A GND N28 N A GND W28 N A GND AJ28 N A GND AW28 N A GND B29 N A GND M29 N A GND AB29 N A GND AM29 N A GND E30 N A GND R30 N A GND AE30 N A GND AR30 N A GND H31 190 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Ba
170. DCi ADC7 B CS B I TDI R RSVD w AVCCAUXTX P TXPPADA 9 DO D31 D IN O TDO VBATT I AVCCAUXMGT TXNPADA cc D DONE M TMS VCCAUX V VTRXA RXNPADB N cC A DOUT BUSY J TDP WA VCCINT VTTXA RXPPADB is jd H HSWAPEN TDN VCCO lt VTRXB Q TXPPADB 6 SM1 9 7 Y INIT n NO CONNECT 5 VTTXB TXNPADB VREF 2 1 0 M2 M1 MO X MGTCLK VRN P PROG_B IG MGTVREF U RDWR B Notes 1 SM and ADC functionality in multi function user I O pins i 2 Dedicated SM and ADC pins are reserved for future use Figure 3 17 FF1152 Flip Chip Fine Pitch BGA Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 s reserved for future use UG075_06_043008 Pinout Diagram FX40 259 Chapter 3 Pinout Diagrams XILINX FF1152 Package Pinout Diagram FX60 FF1152 XC4VFX60 Top View 260 camvzErmrxcecrommoour User I O Pins O IO LXXY Multi Function Pins ADC1 ADC7 DO D31 cc N_GC P_GC SM1 SM7 VREF VRN VRP 9 1112131415 16 718 20 54 2255 2452 260 28 90 5 02 04
171. Devices FX40 Devices N A GND R5 N A GND AE5 N A GND H6 N A GND V6 N A GND AH6 N A GND L7 N A GND AAT N A GND AL7 N A GND D8 N A GND P8 N A GND AD8 N A GND G9 N A GND U9 N A GND AG9 N A GND K10 N A GND V10 N A GND Y10 N A GND AK10 N A GND C11 N A GND N11 N A GND W11 N A GND GND F12 N A GND P12 N A GND T12 N A GND V12 N A GND Y12 N A GND AF12 N A GND J13 N A GND R13 N A GND U13 N A GND W13 N A GND AJ13 N A GND M14 N A GND P14 N A GND V14 N A GND AB14 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Number FX60 Devices FX40 Devices N A GND AM14 N A GND E15 N A GND N15 N A GND R15 N A GND U15 N A GND AC15 N A GND AE15 N A GND H16 N A GND P16 N A GND V16 N A GND Y16 N A GND AH16 N A GND L17 N A GND N17 N A GND U17 N A GND AA17 N A GND AC17 N A GND M18 N A GND P18 N A GND AB18 N A GND AD18 N A GND AM18 N A GND G19 N A GND U19 N A GND AA19 N A GND AG19 N A GND K20 N A GND M20 N A GND V20 N A GND Y20 N A GND AB20 N A GND AK20 N A GND C21 N A GND N21 N A GND U21 N A GND AA21 N A GND AC21 Virtex 4 FPGA Packaging and Pin
172. E27 7 IO L21N 7 AE26 7 IO L22P 7 AL24 7 IO_L22N_7 AK24 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 129 Chapter 2 Pinout Tables XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 7 IO L23P VRN 7 AK27 7 IO L23N VRP 7 AK26 7 IO L24P CC IC 7 24 7 IO L24N CC IC 7 AH24 7 IO 11 7 AK32 7 IO LIN 7 AK31 7 IO I2P 7 AL19 7 IO I2N 7 18 7 IO L3P 7 AM32 7 IO L3N 7 AM31 7 IO 7 AC23 7 IO_L4N_VREF_7 AC22 7 IO L5P 7 AL31 7 IO L5N 7 AL30 7 IO L6P 7 AM20 7 IO L6N 7 AL20 7 IO 17 7 AM30 7 IO 7 AL29 7 IO L8P CC IC 7 AL21 7 IO L8N CC LC 7 AK21 7 IO L9P CC LIC 7 AJ29 7 IO L9N CC LC 7 AK29 7 IO L10P 7 AM22 7 IO L10N 7 AM21 7 IO L11P 7 AH29 7 IO_L11N_7 AH28 7 IO L12P 7 AE22 7 IO L12N VREF 7 AD22 7 IO L13P 7 AM28 7 IO L13N 7 AM27 7 IO L14P 7 AM23 7 IO_L14N_7 AL23 7 IO L15P 7 AK28 7 IO L15N 7 AL28 7 IO L16P 7 AK23 7 IO L16N 7 AK22 130 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued
173. F RTERM and GNDA Virtex 4 User I Os amp Virtex 4 FPGA Package Device RocketlO MGT Pins E363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517 Available User I Os 240 320 320 z XC4VLX15 RocketIO Transceivers N A N A N A Differential I O Pairs 120 160 160 Available User I Os 240 448 448 XCAVLX25 RocketIO Transceivers N A N A N A Differential I O Pairs 120 224 224 Available User I Os 448 640 5 XC4VLX40 RocketIO Transceivers N A N A E Differential I O Pairs 224 320 5 3 Available User I Os 448 640 XC4VLX60 RocketIO Transceivers N A N A 2 Differential I O Pairs 224 320 z Available User I Os 768 E XCAVLX80 RocketIO Transceivers N A 5 Differential I O Pairs 384 z 12 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 EZ XILINX Device Package Combinations and Maximum I Os Table 1 2 Virtex 4 FPGA Available I Os and RocketlO MGT Pins per Device Package Combination Continued Virtex 4 Device XC4VLX100 User I Os amp RocketlO MGT Pins Available User I Os Virtex 4 FPGA Package RocketIO Transceivers Differential I O Pairs XC4VLX160 Available User I Os RocketIO Transceivers Differential
174. F17 NC N A AVSS_SM AF16 NC N A GND Al N A GND L1 N A GND AAI N A GND D2 N A GND P2 N A GND AD2 N A GND G3 N A GND U3 N A GND K4 N A GND Y4 N A GND C5 GND N5 N A GND AC5 N A GND F6 N A GND T6 N A GND AF6 N A GND 17 GND W7 N A GND B8 N A GND M8 N A GND 8 GND AB8 N A GND E9 N A GND N9 N A GND R9 N A GND GND H10 N A GND M10 N A GND P10 N A GND V10 N A GND All N A GND L11 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 85 Chapter 2 Pinout Tables 86 XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued No Connects in Bank Pin Description Pin Number LX15 Devices N A GND N11 N A GND AAI1 N A GND D12 N A GND P12 N A GND T12 N A GND AD12 N A GND G13 N A GND N13 N A GND U13 N A GND K14 N A GND Y14 N A GND C15 N A GND N15 N A GND AC15 N A GND F16 N A GND P16 N A GND T16 N A GND JA7 N A GND N17 N A GND R17 N A GND W17 N A GND B18 N A GND M18 N A GND P18 N A GND AB18 N A GND E19 N A GND N19 N A GND R19 N A GND AE19 N A GND H20 N A GND V20 N A GND A21 N A GND L21 N A GND AA21 N A GND D22 N A GND P22 N A GND AD22 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008
175. F363 flip chip fine pitch BGA package The No Connect column in 20 Table 2 1 shows pins that are not available in LX15 devices XILINX To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Bank Pin Description Pin Number in LX1 0 HSWAPEN 0 E13 0 CCLK 0 E11 0 DIN 0 E9 0 PROG B 0 F12 0 INIT B 0 E12 0 0580 0 DONE 0 F11 0 RDWR_B_0 F9 0 VBATT 0 T13 0 M2 0 R11 0 PWRDWN B 0 T10 0 TMS 0 T8 0 0 R12 0 TDO 0 R10 0 TCK 0 T9 0 0 T12 0 DOUT BUSY 0 T11 0 TDI 0 R9 0 0 10 0 TDP 0 F10 1 IO L1P D31 ILC 1 F15 1 IO L1N D30 LC 1 E15 1 IO 12 D29 IC 1 E6 1 IO L2N D28 LC 1 F6 1 IO L3P D27 LC 1 D15 1 IO L3N D26 LC 1 E14 1 IO L4P D25 IC 1 E7 1 IO D24 VREF LC 1 D6 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 7 XILINX SF363 Flip Chip Fine Pitch BGA Package Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Descriptio
176. FPGA Packaging and Pinout Specification www xilinx com 181 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 182 XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 16 IO L25N CC IC 16 AD11 16 IO L26P 16 AF1 16 IO_L26N_16 16 IO L27P 16 AF4 16 IO L27N 16 16 IO L28P 16 AE6 16 IO L28N VREF 16 AD6 16 IO L29P 16 AF6 16 IO L29N 16 AF5 16 IO L30P 16 AG2 16 IO L30N 16 AGI 16 IO L31P 16 AE9 16 IO L31N 16 AE8 16 IO L32P 16 AG3 16 IO L32N 16 AF3 0 VCCO 0 AA17 0 VCCO 0 W23 0 VCCO 0 0 Y20 1 VCCO 1 A17 1 VCCO 1 B24 1 VCCO 1 C21 1 VCCO 1 D18 1 VCCO 1 E25 1 VCCO 1 F22 1 VCCO 1 G19 1 VCCO 1 H16 1 VCCO 1 J23 1 VCCO 1 L17 1 VCCO 1 M24 1 VCCO 1 P18 1 VCCO 1 T22 1 VCCO 1 U19 2 VCCO 2 AC21 2 VCCO 2 AD18 2 VCCO 2 AF22 2 VCCO 2 AH16 2 VCCO 2 AJ23 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 2 VCCO_2 AL17 2 VCCO_2 AM24 2 VCCO_2 AN21 2 VCCO_2 AP18 2 VCCO_2 AR15 2 VCCO_2 A
177. FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 0 VCCO 0 0 T17 0 VCCO 0 W18 0 VCCO R20 1 VCCO 1 G14 1 VCCO 1 F17 2 VCCO 2 AJ18 2 VCCO 2 AH21 3 VCCO 3 K15 3 VCCO 3 jig 4 VCCO_4 AF17 4 VCCO_4 AE20 5 VCCO_5 E20 5 VCCO_5 H21 5 VCCO_5 L22 5 VCCO_5 D23 5 VCCO_5 P23 5 VCCO_5 G24 5 VCCO_5 K25 5 VCCO_5 C26 5 VCCO_5 F27 6 VCCO_6 D3 6 VCCO_6 C6 6 VCCO 6 F7 6 VCCO_6 18 6 VCCO 6 E10 6 VCCO 6 H11 6 VCCO 6 L12 6 VCCO 6 D13 6 VCCO 6 C16 7 VCCO 7 AM19 7 VCCO_7 AL22 7 VCCO_7 AD23 7 VCCO_7 AG24 7 VCCO_7 AK25 7 VCCO_7 AF27 7 VCCO_7 AJ28 7 VCCO_7 AM29 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 7 VCCO_7 AL32 8 VCCO_8 AJ8 8 VCCO_8 AM9 8 VCCO_8 AE10 8 VCCO 8 AH11 8 VCCO_8 AA12 8 VCCO_8 AL12 8 VCCO_8 AD13 8 VCCO_8 AG14 8 VCCO_8 AK15 9 VCCO 9 N26 9 VCCO 9 T27 9 VCCO 9 128 9 VCCO_9 M29 9 VCCO_9 E30 9 VCCO_9 R30 9 VCCO_9 H31 9 VCCO_9 L32 10 VCCO_10 P3 10 VCCO_10 G4 10 VCCO_10 U4 10 VCCO_10 K5 10 VCCO_10 N6 10 VC
178. Figure 3 16 FF1148 Color Coded SelectlO and Bank Information 258 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Package Pinout Diagram FX40 FF1152 Package Pinout Diagram FX40 FF1152 XC4VFX40 Top View N 11124314151617 18 20 22 24 26 _28 30 32 34
179. G B 0 P21 0 INIT B 0 P19 0 CS BO T16 0 DONE 0 R19 0 RDWR B 0 W15 0 0 R21 0 M2_0 T20 0 PWRDWN B 0 AA16 0 TMS 0 Y14 0 0 V18 0 TDO 0 W17 0 TCK 0 AA14 0 0 W19 0 DOUT_BUSY_0 Y18 0 TDI 0 AA15 0 0 D17 0 TDP 0 C17 1 IO D31 LC 1 G18 1 IO_L1N_D30_LC_1 F18 1 IO L2P D29 LC 1 H14 1 IO_L2N_D28_LC_1 H13 1 IO L3P D27 LC 1 G17 1 IO D26 LC 1 G16 1 IO L4P D25 LC 1 G15 1 IO_L4N_D24_VREF_LC_1 H15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 123 Chapter 2 Pinout Tables 124 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 1 IO L5P D23 LC 1 E18 1 IO D22 LC 1 E17 1 IO L6P D21 LC 1 F15 1 IO L6N D20 LC 1 F14 1 IO L7P D19 LC 1 E16 1 IO L7N D18 LC 1 F16 1 IO L8P D17 CC IC 1 F13 1 IO L8N D16 CC LC 1 G13 2 IO LIP D15 CC IC 2 AH22 2 IO LIN D14 CC IC 2 22 2 IO_L2P_D13_LC_2 AK18 2 IO L2N D12 LC 2 AK17 2 IO_L3P_D11_LC_2 AG22 2 IO_L3N_D10_LC_2 AG21 2 IO D9 LC 2 AH17 2 IO_L4N_D8_VREF_LC_2 AJ17 2 IO L5P D7 LC 2 AJ21 2 IO L5N D6 LC 2 AJ20 2 IO L6P 5516 2 AJ19 2 IO L6N D4 IC 2 AK19 2 IO L7P 5316 2 AG20 2 IO L7N D2 IC 2 AH20 2 IO L8P LC
180. H HSWAPEN O TDO 6 LC Y INIT M TMS smi SM7 2 1 0 M2 M1 J TDP C VREF L TDN VRP Other Pins GND RSVD VBATT VCCAUX VCCINT VCCO NO CONNECT Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use UG075 02 050108 Figure 3 2 SF363 Flip Chip Fine Pitch BGA Pinout Diagram LX25 XILINX www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX SF363 Color Coded SelectlO and Bank Information SF363 Color Coded SelectlO and Bank Information SF363 Top View 6 8 10441244144516 7184520 S camvz Ermrxerommoou z cdmvzzrazxc crommoou 2 4 0 98 10 412 1314151647184920 ug075_02 color_122104 Figure 3 3 SF363 Color Coded SelectlO and Bank Information Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 245 UG075 v3 3 September 19 2008 Chapter 3 Pinout Diagrams FF668 Package Pinout Diagram LX15 SX25 and FX12 246 FF668 XC4VLX15 XC4VSX25 and XC4VFX12 Top View 2 18 920 22 24 1044 121314451647 19 21 26
181. I O Pairs XC4VLX200 Available User I Os RocketIO Transceivers Differential I O Pairs XCAVSX25 Available User I Os RocketIO Transceivers Differential I O Pairs XCAVSX35 Available User I Os RocketIO Transceivers Differential I O Pairs XCAVSX55 XC4VFX12 Available User I Os RocketIO Transceivers Differential I O Pairs Available User I Os SF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517 RocketIO Transceivers Differential I O Pairs XC4VFX20 Available User I Os RocketIO Transceivers Differential I O Pairs XC4VEX40 Available User I Os RocketIO Transceivers Differential I O Pairs XC4VEX60 Available User I Os RocketIO Transceivers Differential I O Pairs Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 13 UG075 v3 3 September 19 2008 Chapter 1 Packaging Overview XILINX Table 1 2 Virtex 4 FPGA Available I Os and RocketlO MGT Pins per Device Package Combination Continued Virtex 4 User l Os Virtex 4 FPGA Package Device RocketlO MGT Pins SF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517 Available User I Os 576 768 XCAVFX100 RocketIO Transceivers 20 20 Differential I O Pairs 288 384 Available User I Os 768 XC4VFX140 RocketIO Tran
182. IO 6 D5 LC 2 AR17 2 IO L6N D4 IC 2 AP17 2 IO_L7P_D3_LC_2 AJ24 2 IO L7N D2 IC 2 AK24 2 IO L8P D1 LC 2 AM17 2 IO L8N D0 LIC 2 AM16 2 IO L9P GC CC IC 2 AF23 2 IO L9N GC CC IC 2 AE22 2 IO L10P GC LIC 2 8 2 IO L10N GC LC 2 AH17 2 IO L11P GC LC 2 AR22 2 IO L11N GC LC 2 AR21 2 IO L12P GC IC 2 AR19 2 IO L12N GC VREF LC 2 AR18 2 IO L13P GC IC 2 AH22 2 IO GC IC 2 AG21 2 IO L14P GC IC 2 AP19 2 IO_L14N_GC_LC_2 ANI19 2 IO L15P GC IC 2 AG22 2 IO L15N GC LC 2 AF21 2 IO 16 GC LC 2 AG20 2 IO L16N GC LC 2 AH19 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 199 Chapter 2 Pinout Tables 200 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices 2 IO_L17P_LC_2 AH24 2 IO_L17N_LC_2 AH23 2 IO L18P LC 2 AK17 2 IO L18N LC 2 AJA7 2 IO L19P LC 2 AT23 2 IO L19N LC 2 AU23 2 IO L20P LC 2 AG17 2 IO L20N VREF LC 2 AG16 2 IO L21P LC 2 AN23 2 IO_L21N_LC_2 AR23 2 IO L22P LC 2 ANI18 2 IO L22N LC 2 ANI17 2 IO 1250 VRN ILC 2 AK23 2 IO L23N VRP IC 2 AJ22 2 IO L24P CC IC 2 AM18 2 IO L24N CC IC 2 AL18 3 IO LIP GC CC IC 3 120 3 IO LIN GC CC IC 3 J19 3 IO 12 GC VRN LC 3 K19 3 IO L2N GC VRP LC 3 L19 3 IO L3P GC LC 3 H20 3 IO GC LC 3 H19 3 IO L4P GC LC 3 G20
183. IO 126 5 6 7 AA19 7 IO L26N SM6 7 AA20 7 IO L27P SM5 7 Y17 7 IO 27 SM5 7 AA17 7 IO L28P 7 AB20 7 IO L28N VREF 7 AC20 7 IO L29P SMA 7 AC18 7 IO 29 5 7 AB18 7 IO L30P SM3 7 AF21 7 IO L30N SM3 7 AF22 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 37 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 38 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 7 IO L31P SM2 7 AF18 7 IO L31N SM2 7 AE18 7 IO L32P SM1 7 AE21 7 IO_L32N_SM1_7 AD21 7 IO_L17P_7 AF19 7 IO_L17N_7 AF20 7 IO_L18P_7 Y19 7 IO_L18N_7 W19 7 IO L19P 7 AF23 7 IO L19N 7 AE23 7 IO L20P 7 Y20 7 IO L20N VREF 7 Y21 7 IO L21P 7 AA18 7 IO_L21N_7 Y18 7 IO_L22P_7 AF24 7 IO_L22N_7 AE24 7 IO L23P VRN 7 AE20 7 IO L23N VRP 7 AD20 7 IO L24P CC LIC 7 AC21 7 IO_L24N_CC_LC_7 AB21 7 IO L1P 7 V21 7 IO LIN 7 V22 7 IO 12 7 W25 7 IO I2N 7 W26 7 IO L3P 7 W21 7 IO L3N 7 W22 7 IO 4 7 W23 7 IO_L4N_VREF_7 W24 7 IO L5P 7 W20 7 IO L5N 7 V20 7 IO L6P 7 Y25 7 IO L6N 7 Y26 7 IO 17 7 AB24 7 IO L7N 7 AB25 7 IO L8P CC LC 7 AA24 7 IO_L8N_CC_LC_7 Y24 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Virtex 4 F
184. IO L24N CC IC 9 T23 9 IO L1P 9 121 9 IO 1 9 120 9 1 12 9 J23 9 IO I2N 9 122 9 IO L3P 9 K22 9 IO L3N 9 K21 9 IO 9 126 9 IO VREF 9 125 9 IO L5P 9 L19 9 IO L5N 9 K20 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 41 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables lt XILINX Table 2 2 FF668 Package LX15 LX40 LX60 SX25 SX35 and FX12 Devices Continued Bank Pin Description Pin Number 9 IO L6P 9 L21 9 IO L6N 9 L20 9 IO L7P 9 K24 9 IO 9 K23 9 IO L8P CC ILC 9 K26 9 IO L8N CC IC 9 K25 9 IO L9P CC ILC 9 M19 9 IO L9N CC IC 9 N19 9 IO L10P 9 L24 9 IO L10N 9 L23 9 IO L11P 9 M25 9 IO L1IN 9 M24 9 IO L12P 9 L26 9 IO L12N VREF 9 M26 9 IO L13P 9 M21 9 IO L13N 9 M20 9 IO L14P 9 M23 9 IO L14N 9 M22 9 IO L15P 9 N25 9 IO L15N 9 N24 9 IO L16P 9 N23 9 IO L16N 9 N22 9 IO L25P CC IC 9 R20 9 IO L25N CC ILC 9 R19 9 IO L26P 9 T26 9 IO L26N 9 U26 9 IO L27P 9 U23 9 IO L2ZN 9 V23 9 IO L28P 9 U25 9 IO L28N VREF 9 U24 9 IO L29P 9 U22 9 IO L29N 9 U21 9 IO L30P 9 T21 9 IO L30N 9 T20 9 IO L31P 9 U20 9 IO L31N 9 T19 42 No Connects in LX15 SX25 and FX12 Devices www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 EZ XILINX Virtex 4 FPGA Packaging and Pinout Specification www
185. IO L32N 8 10 IO_L17P_8 AL14 8 IO_L17N_8 AL13 8 IO L18P 8 AUS 8 IO L18N 8 IO L19P 8 AR12 8 IO L19N 8 AP12 8 IO L20P 8 AR9 8 IO L20N VREF 8 IO L21P 8 AV13 8 IO L21N 8 AUI13 8 IO L22P 8 AT10 8 IO 22 8 AT9 8 IO L23P VRN 8 AU12 8 IO L23N VRP 8 AU11 8 IO_L24P_CC_LC_8 AV8 8 IO L24N CC IC 8 AV7 8 IO L1P 8 AV5 8 IO LIN 8 AUS 8 IO L2P 8 AJ10 8 IO_L2N_8 AJ9 8 IO L3P 8 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 167 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 8 IO L3N 8 AN8 8 IO 4 8 AL9 8 IO LAN VREF 8 AK9 8 IO L5P 8 5 IO L5N 8 AN15 8 IO L6P 8 AP7 8 IO 8 AN7 8 IO L7P 8 AR8 8 IO_L7N_8 AR7 8 IO_L8P_CC_LC_8 AV4 8 IO_L8N_CC_LC_8 AV3 8 IO L9P CC IC 8 ALI 8 IO L9N CC IC 8 AK11 8 IO_L10P_8 AW5 8 IO L10N 8 AWA 8 IO L11P 8 AW7 8 IO L11IN 8 AW6 8 IO L12P 8 AM10 8 IO L12N VREF 8 AL10 8 IO L13P 8 AM11 8 IO L13N 8 AN10 8 IO L14P 8 AHI13 8 IO L14N 8 AJA2 8 IO L15P 8 AN12 8 IO_L15N_8 AP11 8 IO L16P 8 AU7 8 IO L16N 8 AUG 9 IO L17P 9 K33 9 IO L17N 9 L33 9 IO L18P 9 H37 9 IO L18N 9 H38 9 IO L19P 9 N30 9 IO L19N 9 29 9 IO L20P 9 L34 9 IO L20N VREF 9 L35 9 IO L21P 9 J36 9 IO L21N 9 J37 1
186. Input Power supply pins for the output drivers per bank RocketIO Multi Gigabit Transceiver MGT Pins Input Analog power supply for receive circuitry of the RocketIO MGT 1 2V AVCCAUXTX_ Input Analog power supply for transmit circuitry of the RocketlO MGT 1 2V AVCCAUXMGT_ Input Analog power supply for global bias 2 5V GNDA_ Input Ground for the analog circuitry of the RocketIO MGT MGTCLK_ Input Differential reference clock for the RocketlO MGT 16 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Pin Definitions Table 1 3 Virtex 4 FPGA Pin Definitions Continued Pin Name Direction Description REL d Input Positive differential receive port of the RocketIO MGT ADU Input Negative differential receive port of the RocketlO MGT Dm Output Positive differential transmit port of the RocketlO MGT Output Negative differential transmit port of the RocketlO MGT Input Receive termination supply for the RocketIO MGT 0V 2 5V vb Input Transmit termination supply for the RocketIO MGT 1 2V 1 5V Notes 1 All dedicated pins JTAG and configuration are powered by Vcc cowric 2 For more information on lower capacitance pins see the Virtex 4 User Guide UG070 3 For more information on RocketIO transceiver pins see the Virtex 4 RocketIO Multi Gigabit Transceiver User Guide UGO076 Virtex 4 FPGA Packa
187. L14N GC LC 1 C15 1 IO L15P GC LC 1 D20 1 IO L15N GC LC 1 C20 90 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Da connects m Number LX60 and SX55 Devices 1 IO_L16P_GC_CC_LC_1 M16 1 IO L16N GC CC LC 1 N15 1 IO L17P CC LC 1 B20 1 IO L17N CC LC 1 A20 1 IO L18P VRN LC 1 K16 1 IO L18N VRP LC 1 L16 1 IO L19P LC 1 J20 1 IO L19N LC 1 L19 1 IO L20P LC 1 H15 1 IO L20N VREF LC 1 J15 1 IO L21P LC 1 G21 1 IO L21N LC 1 H20 1 IO L22P LC 1 G15 1 TO_L22N_LC_1 F14 1 IO L23P LC 1 F21 1 IO L23N 1 1 F20 1 IO L24P LC 1 A15 1 IO L24N LC 1 B15 2 IO LIP D15 CC IC 2 AJ22 2 IO L1N D14 CC LC 2 AJ21 2 IO L2P D13 LC 2 AC15 2 IO D12 LC 2 AB15 2 IO L3P D11 LC 2 AG22 2 IO L3N D10 LC 2 AH22 2 IO I4P D9 LC 2 AL14 2 IO_L4N_D8_VREF_LC_2 AK14 2 IO_L5P_D7_LC_2 AG21 2 IO L5N D6 ILC 2 AF20 2 IO L6P D5 LC 2 AF14 2 IO L6N D4 IC 2 AG13 2 IO L7P D3 LC 2 AE21 2 IO L7N D2 IC 2 AF21 2 IO L8P D1 LC 2 AP15 2 IO D0 IC 2 AN15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 91 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables
188. L8P CC LC 10 K3 10 IO L8N CC LC 10 K2 10 IO L9P CC LC 10 JA 10 IO L9N CC LIC 10 K1 10 IO L10P 10 I4 10 IO L10N 10 L3 10 IO L11P 10 M5 10 IO L11N 10 M4 10 IO L12P 10 M7 10 IO L12N VREF 10 M6 10 IO L13P 10 L2 10 IO L13N 10 M1 10 IO L14P 10 N3 10 IO 10 N2 10 IO L15P 10 M2 10 IO L15N 10 N1 10 IO L16P 10 N7 10 IO L16N 10 N6 10 IO L25P CC LC 10 v2 10 IO_L25N_CC_LC_10 V1 10 IO L26P 10 Y1 10 IO L26N 10 10 IO L27P 10 U6 10 IO L27N 10 U5 10 IO L28P 10 R7 10 IO L28N VREF 10 R6 10 IO L29P 10 W3 10 IO L29N 10 V3 10 IO L30P 10 WA 10 IO L30N 10 V4 82 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number DD T 10 IO L31P 10 Y3 NC 10 IO L31N 10 Y2 NC 10 IO L32P 10 V6 NC 10 IO L32N 10 W5 NC 0 VCCO TH 0 VCCO M13 0 VCCO 0 R14 0 VCCO 0 L16 1 VCCO 1 J12 1 VCCO_1 15 2 VCCO 2 V15 2 VCCO 2 W12 3 VCCO_3 B13 3 VCCO_3 E14 4 VCCO_4 AB13 4 VCCO 4 AE14 5 VCCO 5 A16 5 VCCO 5 D17 5 VCCO 5 G18 5 VCCO 5 K19 5 VCCO 5 C20 5 VCCO 5 F21 5 VCCO_5 B23 5 VCCO_5 E24 5 VCCO_5 A26 6 VCCO_6 B3 6 VCCO_6 E4 6 VCCO_6 H5 6 VCCO_6 A6 6 VCCO_6 D7 6 VCCO_6 G8 6 VCCO_6 k9 6 VCCO_6 C10 6 VCCO_6 F11 7 VCCO_
189. LC 11 AD36 212 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 11 IO_L9P_CC_LC_11 AE32 11 IO L9N CC LC 11 AD32 11 IO L10P 11 AF35 11 IO L10N 11 AG35 11 IO L11P 11 AF36 11 IO L11IN 11 AG36 11 IO L12P 11 AE34 11 IO L12N VREF 11 AF34 11 IO L13P 11 AG37 11 IO L13N 11 AH37 11 IO L14P 11 AF31 11 IO 11 AG31 11 IO_L15P_11 AF33 11 IO L15N 11 AE33 11 IO L16P 11 AH35 11 IO L16N 11 AJ35 11 IO L25P CC IC 11 AF29 11 IO L25N CC IC 11 AE28 11 IO L26P 11 AN35 11 IO L26N 11 AN34 11 IO_L27P_11 AM37 11 IO L27N 11 AN37 11 IO L28P 11 AH30 11 IO L28N VREF 11 AH29 11 IO L29P 11 AL35 11 IO L29N 11 AM35 11 IO L30P 11 AM33 11 IO L30N 11 AN33 11 IO L31P 11 AK33 11 IO L31N 11 AK32 11 IO L32P 11 AG28 11 IO L32N 11 AF28 12 IO L17P 12 12 IO L17N 12 AL6 12 IO L18P 12 AH7 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 213 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in
190. LC_9 R28 9 IO_L25N_CC_LC_9 R29 9 IO L26P 9 M35 9 IO L26N 9 N35 9 IO L27P 9 K37 9 IO 27 9 K38 9 IO_L28P_9 N33 9 IO L28N VREF 9 N34 9 IO L29P 9 P31 9 IO L29N 9 P32 9 IO L30P 9 K39 9 IO L30N 9 L39 9 IO L31P 9 L38 9 IO L31N 9 M38 9 IO L32P 9 M36 9 IO 2 9 M37 10 IO L17P 10 R14 10 IO L17N 10 T14 10 IO L18P 10 E2 10 IO L18N 10 E1 10 IO L19P 10 12 10 IO L19N 10 R12 10 IO L20P 10 K7 10 IO L20N VREF 10 L8 10 IO L21P 10 H5 10 IO L21N 10 15 10 IO L22P 10 G3 10 IO L22N 10 G2 10 IO L23P VRN 10 J6 10 IO L23N VRP 10 K6 10 IO L24P CC LC 10 F1 10 IO L24N CC IC 10 G1 10 IO L1P 10 A5 10 IO LIN 10 A4 10 IO L2P 10 A3 10 IO L2N 10 B3 10 IO L3P 10 B5 170 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 10 IO L3N 10 C5 10 IO 4 10 C4 10 IO_L4N_VREF_10 D4 10 IO L5P 10 D6 10 IO L5N 10 D5 10 IO L6P 10 C3 10 IO L6N 10 C2 10 IO L7P 10 E6 10 IO L7N 10 F6 10 IO L8P CC LC 10 H7 10 IO L8N CC IC 10 17 10 IO L9P CC LC 10 G7 10 IO L9N CC IC 10 G6 10 IO L10P 10 F5 10 IO L10N 10 G5 10 IO L11P 10 M11 10 IO L11N 10 N12 10 IO L12P 10 F4 10 IO L12N VREF 10 F3 10 IO L13P 10 R16 10
191. N A VCCINT AG15 N A VCCINT AJ15 N A VCCINT M16 N A VCCINT P16 N A VCCINT T16 N A VCCINT V16 N A VCCINT AD16 N A VCCINT AF16 N A VCCINT AM16 N A VCCINT G17 N A VCCINT U17 N A VCCINT W17 N A VCCINT AC17 N A VCCINT AE17 N A VCCINT AJ17 N A VCCINT AR17 N A VCCINT K18 N A VCCINT V18 N A VCCINT AB18 N A VCCINT N19 N A VCCINT R19 N A VCCINT W19 N A VCCINT AC19 N A VCCINT AE19 N A VCCINT F20 N A VCCINT V20 N A VCCINT AB20 N A VCCINT AD20 N A VCCINT AP20 N A VCCINT R21 N A VCCINT U21 N A VCCINT AA21 N A VCCINT AE21 N A VCCINT AG21 N A VCCINT V22 N A VCCINT AB22 N A VCCINT AD22 N A VCCINT AK22 194 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A VCCINT E23 N A VCCINT L23 N A VCCINT R23 N A VCCINT U23 N A VCCINT AA23 N A VCCINT AC23 N A VCCINT AN23 N A VCCINT H24 N A VCCINT P24 N A VCCINT T24 N A VCCINT AB24 N A VCCINT AD24 N A VCCINT AF24 N A VCCINT AH24 N A VCCINT L25 N A VCCINT N25 N A VCCINT R25 N A VCCINT U25 N A VCCINT W25 N A VCCINT AA25 N A VCCINT AC25 N A VCCINT AG25 N A VCCINT AJ25 N A VCCINT K26 N A VCCINT M26 N A VCCINT P26 N A VCCINT 26 VCCINT Y
192. N14 8 IO_L17N_8 AP14 8 IO_L18P_8 AP10 8 IO_L18N_8 ANI10 8 IO L19P 8 AK13 8 IO L19N 8 AK12 8 IO L20P 8 AJ10 8 IO L20N VREF 8 AJ9 8 IO L21P 8 AJ12 8 IO L21N 8 AH12 8 IO 122 8 AM10 8 IO_L22N_8 AL10 8 IO L23P VRN 8 AN13 8 IO L23N VRP 8 AN12 8 IO L24P CC LC 8 AT11 8 IO L24N CC LC 8 AU11 8 IO_L1P_8 AH14 8 IO LIN 8 AH13 8 IO 12 8 AR7 8 IO 8 AP7 8 IO L3P 8 AT18 8 IO L3N 8 AU17 8 IO L4P 8 AUS 8 IO VREF 8 AU7 8 IO L5P 8 AT16 8 IO L5N 8 AU16 8 IO L6P 8 AT8 8 IO_L6N_8 AR8 8 IO 17 8 AP16 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 207 Chapter 2 Pinout Tables 208 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices 8 IO_L7N_8 AR16 8 IO L8P CC LC 8 ANS 8 IO L8N CC LC 8 IO L9P CC LC 8 AT15 8 IO L9N CC LC 8 AU15 8 IO_L10P_8 AT9 8 IO_L10N_8 AR9 8 IO L11P 8 AN15 8 IO L11N 8 AP15 8 IO L12P 8 IO L12N VREF 8 AN9 8 IO_L13P_8 AM15 8 IO_L13N_8 AL14 8 IO_L14P_8 AL9 8 IO L14N 8 AK9 8 IO L15P 8 AJ14 8 IO L15N 8 AK14 8 IO L16P 8 AU10 8 IO_L16N_8 AT10 9 IO_L17P_9 N33 9 IO_L17N_9 M33 9 IO_L18P_9 H37 9 IO_L18N_9 G37 9 IO_L19P_9 R32 9 IO L19N 9 P32 9 IO L20P 9 P31 9 IO L20N VREF 9 P30 9 IO L21P 9 R31 9 IO L21N 9 T31 9 I
193. NC N A TXNPADA_103 N26 NC N A VTTXB 103 R25 NC N A TXPPADB 103 P26 NC N A AVCCAUXMGT 103 U25 NC N A TXNPADB 103 R26 NC N A RXPPADB 103 U26 NC N A VTRXB 103 T26 NC N A AVCCAUXRXB 103 V25 NC N A RXNPADB 103 V26 NC N A AVCCAUXRXA 105 Y25 N A 105 W26 N A VTRXA_105 AA26 N A 105 26 AVCCAUXMGT 105 AE24 N A AVCCAUXTX 105 AC25 N A 105 AB25 N A 105 AB26 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 63 Chapter 2 Pinout Tables 64 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices N A TXNPADA_105 AC26 N A VTTXB 105 AD25 N A TXPPADB 105 AD26 N A TXNPADB 105 AE26 N A AVCCAUXRXB 105 AE23 N A RXPPADB 105 AF24 N A VTRXB 105 AF25 N A RXNPADB_105 AF23 N A MGTCLK_P_105 AF21 N A MGTCLK_N_105 AF20 N A RTERM_105 AE21 N A MGTVREF 105 AE19 N A AVCCAUXRXA 110 AD2 N A RXPPADA 110 ACI N A VTRXA_110 110 AD1 N A AVCCAUXMGT 110 AE7 N A AVCCAUXTX 110 110 110 2 110 AF3 N A VTTXB 110 AE5 N A TXPPADB 110 AF4 N A TXNPADB_110 AF5 N A AVCCAUXRXB_110 AE8 N A RXPPADB_110 AF7 N A VTRXB_110 AF6 N A RXNPAD
194. NT AE7 N A VCCINT VCCINT V8 N A VCCINT AH8 192 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A VCCINT AM8 N A VCCINT N9 N A VCCINT VCCINT F10 N A VCCINT T10 N A VCCINT AD10 N A VCCINT AP10 N A VCCINT J11 N A VCCINT W11 N A VCCINT AG11 N A VCCINT M12 N A VCCINT AB12 N A VCCINT AD12 N A VCCINT AH12 N A VCCINT AK12 N A VCCINT L13 N A VCCINT N13 N A VCCINT R13 N A VCCINT AE13 N A VCCINT AG13 N A VCCINT AN13 N A VCCINT H14 N A VCCINT K14 N A VCCINT M14 N A VCCINT P14 N A VCCINT V14 N A VCCINT Y14 N A VCCINT AD14 N A VCCINT AF14 N A VCCINT AH14 N A VCCINT AK14 N A VCCINT L15 N A VCCINT N15 N A VCCINT U15 N A VCCINT W15 N A VCCINT AA15 N A VCCINT AC15 N A VCCINT AE15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 193 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number
195. N_7 AD21 7 IO L23P VRN 7 AA15 7 IO L23N VRP 7 AB15 7 IO L24P CC LC 7 AC19 7 IO L24N CC IC 7 AB19 7 IO L1P 7 V21 76 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee ee 7 IO LIN 7 V22 7 IO_L2P_7 Y23 7 IO L2N 7 W23 7 IO L3P 7 AA23 7 IO L3N 7 AA24 7 IO 7 T18 7 IO_L4N_VREF_7 T19 7 IO L5P 7 Y22 7 IO L5N 7 W21 7 IO L6P 7 AE25 7 IO L6N 7 AD25 7 IO L7P 7 AE26 7 IO L7N 7 AD26 7 IO L8P CC LC 7 AC24 7 IO_L8N_CC_LC_7 AB24 7 IO_L9P_CC_LC_7 AC23 7 IO L9N CC IC 7 AD24 7 IO L10P 7 AF24 7 IO L10N 7 AF25 7 IO 7 AC22 7 IO 7 AB22 7 IO L12P 7 V19 7 IO 112 VREF 7 U19 7 IO L13P 7 W19 7 IO_L13N_7 Y20 7 IO L14P 7 Y21 7 IO L14N 7 AA22 7 IO L15P 7 AE23 7 IO L15N 7 AD23 7 IO L16P 7 AB20 7 IO L16N 7 AC21 8 IO L25P CC LC 8 AF8 8 IO L25N CC LC 8 AE8 8 IO L26P 8 AD10 8 IO L26N 8 AD9 8 IO L27P 8 AE10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 77 Chapter 2 Pinout Tables XILINX Table 2 4 FF676 Package LX15 a
196. O 11 AD33 11 VCCO 11 AG34 12 VCCO_12 AHI 12 VCCO_12 AL2 12 VCCO_12 AD3 12 VCCO_12 AGA 12 VCCO 12 AC6 12 VCCO 12 7 12 VCCO_12 ABO 12 VCCO_12 AA12 12 VCCO 12 Y15 13 VCCO 13 U24 NC 13 VCCO 13 T27 NC 13 VCCO 13 W28 NC www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 EZ XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin No Connects In 1x40 Number LX60 and SX55 Devices 13 VCCO_13 13 VCCO 13 13 VCCO 13 13 VCCO 13 18 VCCO 13 14 VCCO 14 14 VCCO 14 14 VCCO 14 14 VCCO 14 14 VCCO 14 14 VCCO 14 14 VCCO 14 14 VCCO 14 N A VREFN_SM 2 AN17 N A VREFP_SM 2 AN18 N A AVDD SM 9 AP19 VN_SM 2 AP17 N A VP_SM 2 AP18 N A AVSS_SM AN19 VREEN ADC N A VREFP ADC B18 AVDD_ADC 9 B16 N A VN_ADC A17 N A VP ADC 2 A18 AVSS_ADC N A GND B1 N A GND C1 N A GND N1 N A GND ACI N A GND AN1 N A GND F2 N A GND T2 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 115 Chapter 2 Pinout Tables 116 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices
197. O 122 9 M35 9 IO L22N 9 L35 9 IO L23P VRN 9 R33 9 IO L23N T33 9 IO L24P CC LC 9 N35 9 IO L24N CC LC 9 N34 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 9 IO 9 K32 9 IO LIN 9 192 9 IO 12 9 D34 9 IO I2N 9 C34 9 IO L3P 9 G35 9 IO L3N 9 F35 9 IO 9 D35 9 IO VREF 9 C35 9 IO L5P 9 E37 9 IO L5N 9 D37 9 IO L6P 9 F34 9 IO L6N 9 E34 9 IO 17 9 G36 9 IO L7N 9 F36 9 IO L8P CC LC 9 H33 9 IO L8N CC LC 9 H32 9 IO L9P CC LC 9 195 9 IO_LIN_CC_LC_9 H35 9 IO_L10P_9 E36 9 IO L10N 9 D36 9 IO L11P 9 L34 9 IO L11N 9 K34 9 IO L12P 9 J34 9 IO L12N VREF 9 H34 9 IO L13P 9 197 9 IO_L13N_9 J36 9 IO_L14P_9 N30 9 IO_L14N_9 M31 9 IO_L15P_9 N32 9 IO L15N 9 M32 9 IO L16P 9 L33 9 IO L16N 9 K33 9 IO L25P CC LC 9 T30 9 IO L25N CC LC 9 T29 9 IO L26P 9 U33 9 IO L26N 9 U32 9 IO L27P 9 U31 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 209 Chapter 2 Pinout Tables 210 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in
198. O L10N GC LC 1 E19 1 IO L11P GC LC 1 E21 1 IO L11N GC LC 1 D21 1 IO L12P GC IC 1 C19 1 IO L12N GC VREF LC 1 C18 1 IO L13P GC LC 1 D22 1 IO_L13N_GC_LC_1 C22 1 IO_L14P_GC_LC_1 G20 1 IO L14N GC IC 1 F19 1 IO L15P GC IC 1 J22 1 IO L15N GC LIC 1 H22 1 IO L16P GC CC IC 1 T20 1 IO L16N GC CC IC 1 T19 1 IO_L17P_CC_LC_1 G22 1 IO L17N CC IC 1 F21 1 IO_L18P_VRN_LC_1 P19 1 IO L18N VRP LC 1 N18 1 IO L19P LC 1 H23 1 IO L19N LC 1 G23 1 IO L20P LC 1 L18 1 IO L20N VREF IC 1 M18 1 IO L21P LC 1 F23 1 IO L21N LC 1 E22 1 IO L22P LC 1 G18 1 IO L22N LC 1 H17 1 IO L23P LC 1 C23 1 IO L23N IC 1 B23 1 IO L24P LC 1 E18 1 IO L24N LC 1 F18 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 157 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 1 IO_L25P_LC_1 F24 1 IO L25N IC 1 E24 1 IO L26P LC 1 A18 1 IO L26N IC 1 B18 1 IO L27P LC 1 D24 1 IO LZN LC 1 C24 1 IO L28P IC 1 U20 1 IO L28N VREF LC 1 U18 1 IO L29P LC 1 A24 1 IO L29N IC 1 A23 1 IO L30P LC 1 T18 1 IO L30N LC 1 R18 1 IO L31P IC 1 N23 1 IO L31N LC 1 M23 1 IO L32P CC IC 1 P17 1 IO L2N CC IC 1 R17 1 IO L33P CC LC 1 L24 1 IO L33N CC IC 1 K23 1 IO L34P LC 1 M17 1 IO L34N LC 1 N17 1 IO L35P IC 1 K24 1 IO L35N LC 1 J2
199. O L19N 6 J5 6 IO L20P 6 H3 6 IO L20N VREF 6 H2 6 IO L21P 6 K5 6 IO L21N 6 K4 6 IO L22P 6 K1 6 IO_L22N_6 J2 6 IO_L23P_VRN_6 L5 6 IO_L23N_VRP_6 L4 6 IO L24P CC LC 6 K3 6 IO L24N CC LC 6 K2 6 IO L9P CC LC 6 F3 6 IO L9N CC LC 6 E3 6 IO L10P 6 C3 6 IO L10N 6 C2 6 IO L11P 6 F5 6 IO L11IN 6 FA 6 IO L12P 6 D2 6 IO L12N VREF 6 E2 6 IO L13P 6 G5 6 IO L13N 6 G4 6 IO L14P 6 E1 6 IO L14N 6 F1 6 IO_L15P_6 H5 6 IO L15N 6 H4 6 IO L16P 6 F2 6 IO L16N 6 G2 6 IO L25P CC LIC 6 M4 6 IO L25N CC IC 6 M3 6 IO L26P 6 M1 6 IO L26N 6 L1 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 25 Chapter 2 Pinout Tables 26 XILINX Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 a ies 6 IO_L27P_6 M6 6 IO_L27N_6 M5 6 IO_L28P_6 M2 6 IO L28N VREF 6 L2 6 IO L29P 6 N5 6 IO L29N 6 N4 6 IO_L30P_6 N3 6 IO_L30N_6 N2 6 IO L31P 6 p5 6 IO L31N 6 P4 6 IO L32P 6 P2 6 IO_L32N_6 P1 7 IO_L25P_CC_SM7_LC_7 T17 7 IO L25N CC SM7 LC 7 T18 7 IO 126 5 6 7 U18 7 IO L26N SM6 7 U19 7 IO L27P SM5 7 T15 7 IO 27 5 7 U15 7 IO L28P 7 V19 7 IO L28N VREF 7 V20 7 IO 129 SMA 7 U16 7 IO L29N SMA 7 U17 7 IO L30P SM3 7 W18 7 IO L30N SM3 7 W19 7 IO L31P SM2 7 Y17 7 IO L31N SM2 7 W17 7 IO_L32P
200. O L27N 12 AR4 12 IO L28P 12 AM7 12 IO L28N VREF 12 AM6 12 IO L29P 12 AR6 12 IO L29N 12 AP6 12 IO L30P 12 AP5 12 IO L30N 12 4 12 IO L31P 12 AT6 12 IO L31N 12 12 IO L32P 12 AUS 12 IO L32N 12 AT3 13 IO L17P 13 T38 13 IO L17N 13 U38 13 IO L18P 13 V29 13 IO L18N 13 V30 13 IO L19P 13 U36 13 IO L19N 13 U37 13 IO L20P 13 V32 13 IO L20N VREF 13 W32 13 IO L21P 13 W26 13 IO L21N 13 W27 13 IO L22P 13 V34 13 IO L22N 13 V35 13 IO L23P VRN 13 V37 13 IO L23N VRP 13 V38 13 IO L24P CC LC 13 V39 13 IO L24N CC IC 13 W39 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 175 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 13 IO L1P 13 R31 13 IO LIN 13 R32 13 IO L2P 13 P34 13 IO_L2N_13 P35 13 IO L3P 13 T29 13 IO L3N 13 U28 13 IO 13 P36 13 IO VREF 13 P37 13 IO L5P 13 N37 13 IO L5N 13 N38 13 IO L6P 13 N39 13 IO L6N 13 P39 13 IO L7P 13 R34 13 IO L7N 13 T34 13 IO L8P CC LC 13 T31 13 IO L8N CC IC 13 U30 13 IO L9P CC LC 13 R36 13 IO L9N CC IC 13 T36 13 IO L10P 13 T33 13 IO L10N 13 U32 13 IO L11P 13 R37 13 IO L11N 13 R38 13 IO L12P 13 R39 13 IO L12N VREF 13 T39 13 IO L13P 13 V25 13 IO L13N 13 U26 13 IO L14P 13 V27 13 IO L14N 13 U27 13 IO L15P 13 T35
201. O L30P 5 B16 5 IO L30N 5 C16 5 IO L31P 5 N24 5 IO L31N 5 N23 5 IO L32P 5 A15 5 IO L32N 5 B15 6 IO L1P 6 H8 6 IO LIN 6 H7 6 IO 12 6 A8 6 IO L2N 6 A7 6 IO L3P 6 F8 6 IO L3N 6 F7 6 IO_L4P_6 G7 6 IO_L4N_VREF_6 H6 6 IO L5P 6 E8 6 IO L5N 6 E7 6 IO L6P 6 B7 6 IO L6N 6 C7 6 IO L7P 6 D8 6 IO L7ZN 6 C8 6 IO L8P CC IC 6 D6 6 IO L8N CC IC 6 E6 6 IO L17P 6 B9 6 IO L17N 6 A9 6 IO L18P 6 C3 6 IO L18N 6 D3 6 IO L19P 6 G10 6 IO_L19N_6 F10 6 IO 20 6 E3 6 IO L20N VREF 6 F3 6 IO L21P 6 E10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 55 Chapter 2 Pinout Tables 56 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 6 IO L21N 6 D10 6 IO L22P 6 K6 6 IO L2N 6 15 6 IO_L23P_VRN_6 B10 6 IO L23N VRP 6 A10 6 IO L24P CC LC 6 H4 6 IO L24N CC IC 6 G4 6 IO L9P CC IC 6 J9 6 IO L9N CC IC 6 K10 6 IO L10P 6 B6 6 IO L10N 6 C6 6 IO L11P 6 H9 6 IO L11IN 6 G9 6 IO L12P 6 D5 6 IO L12N VREF 6 E5 6 IO L13P 6 D9 6 IO L13N 6 C9 6 IO L14P 6 C4 6 IO L14N 6 D4 6 IO L15P 6 K8 6 IO L15N 6 K7 6 IO L16P 6 G5 6 IO L16N 6 F4 6 IO L25P CC IC 6 E11 6 IO_L25N_CC_LC_6 D11 6 IO_L26P_6 L7 6 IO_L26N_6 M6 6 IO L27P 6 C11 6 IO_L27N_6 B11 6 IO_L28P_6 J4 6 IO L28N VREF
202. O L4P GC LC 4 Y6 4 IO GC VREF LC 4 W6 4 IO L5P GC LC 4 W11 4 IO_L5N_GC_LC_4 W10 4 IO L6P GC LC 4 Y7 4 IO 6 GC LC 4 W7 4 IO L7P GC VRN LC 4 Y10 4 IO L7N GC VRP LC 4 Y9 4 IO L8P GC CC LC 4 W9 4 IO L8N GC CC IC 4 WS8 5 IO 5 B15 5 IO LIN 5 A15 5 IO 12 5 A16 5 IO I2N 5 B16 5 IO L3P 5 C15 5 IO L3N 5 C16 5 IO 5 B17 5 IO VREF 5 C17 5 IO L5P 5 D16 5 IO L5N 5 E16 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 7 XILINX SF363 Flip Chip Fine Pitch BGA Package Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 5 IO L6P 5 A18 5 IO L6N 5 B18 9 IO 17 5 D17 5 IO 5 D18 5 IO L8P CC LC 5 B19 5 IO L8N CC IC 5 C20 5 IO L17P 5 JA7 5 IO L17N 5 J18 5 IO L18P 5 H20 5 IO L18N 5 G20 5 IO L19P 5 J15 5 IO L19N 5 J16 5 IO L20P 5 H18 5 IO L20N VREF 5 H19 5 IO L21P 5 K16 5 IO L21N 5 K17 5 IO 122 5 K20 5 IO L22N 5 J19 5 IO L23P VRN 5 L16 5 IO L23N VRP 5 L17 5 IO L24P CC LC 5 K18 5 IO L24N CC IC 5 K19 5 IO_L9P_CC_LC_5 F18 5 IO_LIN_CC_LC_5 E18 5 IO L10P 5 C18 5 IO L10N 5 C19 5 IO L11P 5 F16 5 IO L11N 5 F17 5 IO L12P 5 D19 5 IO L12N VREF 5 E19 5 IO L13P 5 G16 5 IO L13N 5 G17 5 IO L14P 5 E20 5 IO L14N 5 F20 5 IO L15P 5 H16 5 IO L15N 5 H17
203. O and Bank Information FF1513 Top View 423 4 5 7 B g 1044124514 15 16 4718 49205 4 22 9324 9526 5728 598034 92 3494 35 96 3758 59 10 10 10 4 4 1 10 10 a STR T 1 1 1010 10 10 1 1 1 1 9 9 9 10 10 1010110 1 4 9 9 9 9 9 10 10 10 10 10 al 4 1 9 9 9 9 9 10 1011010110 1 at p al 9 9 9 9 9 1010110 1010110 dE ET 1 1 1 9 9 9 9 10 10 1 1 141 9 9 9 9 9 9 10 10 10 1 1 9 9 9 9 9 9 10110 TIA 111 9 9 9 9 9 9 9 10 10 1 1 1 9 9 9 9 9 9 10 10 10 10 10 1 1 9 9 9 9 9 9 9 1010 10 10 1 9 9 91919 10 10 10 10 1 1 9 9 9 10 10 1010 10 101111 1 9 9 10 10 10 10 ab 1 TER 1 10 10 1 1 A 2 11111 2 2 11 11 14 11 12 12 2 11 14 11 11 11111 12112 12 2 2 11 11 11 11 12 12 12 12 12 alee 212 11 11 11111 12 12 1212 12 12112 z 2 EZ 11 11 1111 11 1212 1211211212 2 2 2 11 11 12112112112 12112112 219 212 11 11 12 1211211212 12 2 2 2 11 11 11 12112112 12112112 212 P 2 2 2 11 14 12112112112 22 2 2 22 11 11 11 11 11 11 1212 12112112 Z222 2 21 2 11 11 11 14 11
204. OOC OLIOGOMORIOM ean 1 6 20 AH AJ AJ AK OOOORIOOOOCLIOGOOOOBRIOOGOOLIOOOON eOOOLIOOOO AK AL ORNOOOCOLIOOOORIOG eOLIDC esoOxseeeei OOOONOO AL 5 124467 8 g 104412451445 16 718 520 22 24 26 28 930 32 34 User I O Pins Dedicated Pins Other Pins O 1 LXXY s Z ADC P PROG B Multi Function Pins CCLK PWRDWN B RSVD amp ADC7 B CS B U RDWR B VBATT DO D31 Ni D IN S SM VCCAUX cc D DONE K TCK VCCINT N GC A DOUT BUSY TDI VCCO D P GC H HSWAPEN O TDO NO CONNECT 8 LC Y INIT M TMS SM1 SM7 2 1 0 M2 M1 MO J TDP 69 VREF L TDN Q VRN VRP Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for Figure 3 15 FF1148 Flip Chip Fine Pitch BGA Pinout Diagram LX80 LX100 and LX160 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 future use UG075_05_043008 257 Chapter 3 Pinout Diagrams XILINX FF1148 Color Coded SelectlO and Bank Information FF1148 Top View 2 4 0
205. OOO0O0O0000LIOOO0O0 zZ cdmuzzracromnmoou o PAX UP O AC 9 111243 445 Qoo joe ee a 1 Dedicated Pins ADC CCLK CS_B D_IN DONE DOUT_BUSY ok m mU z IN HSWAPEN INIT M2 M1 MO 20 2224 1718919 21 23 25 PROG B PWRDWN B RDWR B rj e go HH mw lw s rm SM TCK TDI TDO TMS TDP TDN 2 Dedicated SM and ADC pins are reserved for future use 26 Other Pins GND RSVD VBATT VCCAUX VCCINT VCCO NO CONNECT Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use UGO075 10 050108 Figure 3 12 FF676 Flip Chip Fine Pitch BGA Pinout Diagram LX25 XILINX www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Color Coded SelectlO and Bank Information FF676 Color Coded SelectlO and Bank Information FF676 Top View
206. OOOOCNGGOGOLIOOeONOOOQOQLIOOOBO c H H J J XMOONOOC OCHOCOCOCONSODODHOSOONCMOOHOCOCHS L BHNOOOOLICOOOOSIOC OOLUMAIWMORIOOOOLIOOOONEB L M BO wt IOOWN CO NIOOONX M EOCOONSOCOCL 4ST Wat N P VIIOOOCOCLIOOQLIM UI UBMEIYIHIPIONO MOOLIOO PONENM P R 1 kN kD WI M R T BICI EI OSOOOOLDIEe T u OB3ONOOOOCLENLAWIE WEE ad WEM MOOO u v OBOOOEDJOOBCUMUJI B WOOL umm amada v w ENMIOOOGONOCSEIBBBUROSIaMIBLI OOOONOOOOMC w v o moOOBNOOOOC JI am M WAR WI Y AA OoNMOOOOLIOOWONIOIKIUIME TSUTIL T I 169O OL IOOO ONDIO AA AB ad LO Ud 109 OO IOOCBMIE AB AC 4NMIOOCOPCNOWOOCLIOOmN WW i OoMNOSIOO OOLIOm amp ac AD CENOOC OO COONCHABIPODSN SOCHOCOOCOCHS AE amp NOOOOLIC 90DOSOOO9LIOOOONOOBI AE AF AF AG MODOOOOLIGOGOOONOC OC AH QOlOOOLI OOORNOOGOOLIeeeeneoo e Je 5OoOoNOMI AH AJ OBLIOOOONOOOOLIGOOOCRIe eeeLrIoee 10000IN9 AJ AK
207. OOOOOOOCL4 Id OOLIOOOOhRl P ROOOGOOQOO a a MOOSGOOBO R TONOONOCOOM kE OOO OT u OWOOOOON MN Ea NOOOOKOO u v OOLIOOOO Pal 4 a a OOOQOELIOO v w ad d KI 2 O Ld QOOOOQOOW v OO00000 9OOOMLIBUQOIALDIEeO GOGOOO Y AA ONOO OOOO00009999 eo0e0 OONO AA AB ee D NOOOCCOOCO AB Ac AC AD QCOOOOCOCSOLIOODOONSSLOSOO OO AD AE OORIOGRIODRIC O0ISISIe 10 e OO AE AF SSS OCC OOO AF 1 2 3 4 5 6 7 8 1944124914 15161718 9205 22 3245 26 User I O Pins Dedicated Pins Other Pins O IO LXXY Z ADC P PROG B GND Multi Function Pins CCLK W PWRDWN B R RSVD amp ADC1 ADC7 B CS B U RDWR B VBATT 9 DO D31 N D IN S SM 4 VCCAUX e cc Di DONE K TCK m VCCINT N GC A DOUT BUSY I TDI VCCO P GC H HSWAPEN TDO n NO CONNECT 6 LC Y INIT M TMS 9 7 2 1 0 M2 M1 MO J TDP 69 VREF L TDN VRN VRP Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 UG075_01_050108 247 Chapter 3 Pinout Diagrams XILINX FF668 Color Coded SelectlO and Bank Information FF668 Top View 1 2 8 4 5 6 7 8 9 10441244144516 718 920 122 424 26
208. Overview XILINX Table 1 3 Virtex 4 FPGA Pin Definitions Continued Pin Name Direction Description TMS 0 Input Boundary Scan Mode Select TDP 0 TDN 0 N A Temperature sensing diode pins Anode TDP Cathode TDN Reserved Pins SUED AVSS_SM Input This pin is reserved for future use and should be connected to GND VN_SM Input This pin is reserved for future use and should be connected to GND VP_SM Input This pin is reserved for future use and should be connected to GND VREFN_SM Input This pin is reserved for future use and should be connected to GND VREFP_SM Input This pin is reserved for future use and should be connected to GND BED AVC AVSS_ADC Input This pin is reserved for future use and should be connected to GND VN_ADC Input This pin is reserved for future use and should be connected to GND VP_ADC Input This pin is reserved for future use and should be connected to GND VREFN_ADC Input This pin is reserved for future use and should be connected to GND VREFP_ADC Input This pin is reserved for future use and should be connected to GND RSVD N A Reserved pin do not connect Other Pins GND Input Ground eros Input oe key memory backup supply If unused this pin should be tied to cc or GND VCcCAUX Input Power supply pins for auxiliary circuits VCCINT Input Power supply pins for the internal core logic Vcco
209. PGA Packaging and Pinout Specification www xilinx com Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued FF668 Flip Chip Fine Pitch BGA Package No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 7 IO L9P CC LC 7 AC25 7 IO L9N CC LC 7 AC26 7 IO L10P 7 AB26 7 IO_L10N_7 AA26 7 IO_L11P_7 AD25 7 IO_L11N_7 AD26 7 IO L12P 7 Y22 7 IO L12N VREF 7 Y23 7 IO L13P 7 AC22 7 IO L13N 7 AB22 7 IO L14P 7 AB23 7 IO L14N 7 AA23 7 IO L15P 7 AD22 7 IO L15N 7 AD23 7 IO L16P 7 AC23 7 IO L16N 7 AC24 8 IO L25P CC LC 8 AF8 8 IO L25N CC LC 8 AF7 8 IO_L26P_8 8 IO_L26N_8 Y8 8 IO_L27P_8 Y10 8 IO_L27N_8 AA10 8 IO_L28P_8 AC7 8 IO L28N VREF 8 AB7 8 IO L29P 8 AC9 8 IO_L29N_8 IO L30P 8 AE6 8 IO L30N 8 AD6 8 IO L31P 8 AF9 8 IO L31N 8 AE9 8 IO L32P 8 ADS 8 IO L32N 8 AC8 8 IO_L17P_8 AF4 8 IO_L17N_8 AE4 8 IO_L18P_8 UG075 v3 3 September 19 2008 39 Chapter 2 Pinout Tables 40 XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 8 IO_L18N_8 AC3 8 IO_L19P_8 AF6 8 IO_L19N_8 AF5
210. P_GC_CC_LC_4 AF14 4 IO L8N GC CC IC 4 AF13 5 IO L1P 5 B15 5 IO LIN 5 A15 5 IO L2P 5 C16 5 IO 5 B16 5 IO L3P 5 D16 5 IO L3N 5 C17 5 IO 5 H17 5 IO_L4N_VREF_5 G17 5 IO L5P 5 B17 5 IO L5N 5 A17 5 IO L6P 5 E17 5 IO L6N 5 F17 5 IO L7P 5 A18 5 IO L7N 5 A19 5 IO L8P CC LC 5 C18 72 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee ee 5 IO L8N CC IC 5 C19 5 IO L17P 5 G19 5 IO L17N 5 G20 5 IO L18P 5 A22 5 IO L18N 5 A23 5 IO L19P 5 B22 5 IO L19N 5 C22 5 IO L20P 5 J20 5 IO L20N VREF 5 K20 5 IO L21P 5 K18 5 IO 21 5 L19 5 IO L22P 5 E22 5 IO L22N 5 F22 5 IO L23P VRN 5 E23 5 IO L23N VRP 5 F23 5 IO L24P CC LC 5 C23 5 IO L24N CC LC 5 D23 5 IO L9P CC LC 5 D18 5 IO Lo9N CC IC 5 D19 5 IO L10P 5 F18 5 IO L10N 5 E18 5 IO L11P 5 B19 5 IO L11N 5 A20 5 IO L12P 5 H18 5 IO L12N VREF 5 J19 5 IO_L13P_5 B20 5 IO L13N 5 B21 5 IO L14P 5 D20 5 IO 5 C21 5 IO L15P 5 D21 5 IO L15N 5 E21 5 IO L16P 5 E20 5 IO L16N 5 F20 5 IO L25P CC LC 5 A24 5 IO L25N CC LC 5 B24 5 IO L26P 5 C24 5 IO L26N 5 D24 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 Septem
211. RDWR B VBATT DO D31 N D IN S SM VCCAUX e cc D DONE K TCK VCCINT N GC A DOUT BUSY U TDI VCCO P_GC H HSWAPEN O TDO NO CONNECT 6 LC Y INIT M TMS smi SM7 2 1 0 M2 M1 Mo J TDP amp VREF O VRN VRP Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use 075 05b 081408 Figure 3 14 FF1148 Flip Chip Fine Pitch BGA Pinout Diagram LX40 LX60 and SX55 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Package Pinout Diagram LX80 LX100 and LX160 FF1148 Package Pinout Diagram LX80 LX100 and LX160 FF1148 XC4VLX80 XC4VLX100 and XC4VLX160 Top View 8 16 718 20 22 4 24 26 2 28 430 32 434 104112 1 3 5 7 9 13 445 19 21 23 25 27 29 31 33
212. REF 15 AE36 15 IO L21P 15 AJ39 15 IO L21N 15 AH39 15 IO L22P 15 AG37 15 IO L22N 15 AG38 15 IO L23P VRN 15 AH37 15 IO L23N VRP 15 AH38 15 IO L24P CC IC 15 AF34 15 IO L24N CC IC 15 AF35 15 IO L1P 15 27 15 IO LIN 15 AA28 15 IO L2P 15 W29 15 IO L2N 15 W30 15 IO L3P 15 AA34 15 IO L3N 15 AA35 15 IO LAP 15 Y29 15 IO VREF 15 AA30 15 IO L5P 15 AC38 15 IO 15 AC39 15 IO L6P 15 AA31 15 IO L6N 15 Y31 15 IO L7P 15 AC35 15 IO L7N 15 AB35 15 IO L8P CC IC 15 AB33 15 IO L8N CC IC 15 AA33 15 IO L9P CC LC 15 AC33 15 IO L9N CC IC 15 AC34 15 IO L10P 15 AD37 15 IO L10N 15 AC37 15 IO L11P 15 AC32 15 IO L11N 15 AB31 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 179 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 15 IO L12P 15 AE39 15 IO L12N VREF 15 AD39 15 IO L13P 15 AF38 15 IO L13N 15 AF39 15 IO L14P 15 AD35 15 IO L14N 15 AD36 15 IO L15P 15 AC30 15 IO L15N 15 AB30 15 IO L16P 15 AE37 15 IO L16N 15 AE38 15 IO L25P CC LC 15 AJ36 15 IO L25N CC IC 15 AJ37 15 IO L26P 15 AG35 15 IO L26N 15 AG36 15 IO L27P 15 AJ35 15 IO L27N 15 AH35 15 IO L28P 15 AK38 15 IO L28N VREF 15 AK39 15 IO L29P 15 AM37 15 IO L29N 15 AM38 15 IO L30P 15 AL38 15 IO L30N 15 AL39 15
213. RN VRP Multi Function Pins FF672 XC4VFX60 Top View 42345 Big Bg 105412 184 167 1845205922 524 20 A Vie BNOOCOCSCLOOOONOBS OMPOOO A B EBAWSES B NOOLIOOOONOC OOLIOOOONOGOOmO D
214. SX55 Devices N A GND 127 GND AA27 N A GND AL27 N A GND D28 N A GND P28 N A GND AD28 N A GND AP28 N A GND G29 N A GND U29 N A GND AG29 N A GND K30 N A GND Y30 N A GND AK30 N A GND GND N31 N A GND AC31 N A GND AN31 N A GND F32 N A GND T32 N A GND AF32 N A GND A33 N A GND Ja3 N A GND W33 N A GND AJ33 N A GND B34 N A GND M34 N A GND AB34 N A GND AM34 N A GND AN34 N A VCCAUX N8 N A VCCAUX F9 N A VCCAUX T9 N A VCCAUX AH9 N A VCCAUX J10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 119 Chapter 2 Pinout Tables 120 XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Number LX60 and SXS5 Devices N A VCCAUX AA10 N A VCCAUX M11 N A VCCAUX ADI N A VCCAUX 2 VCCAUX U16 N A VCCAUX AJ16 N A VCCAUX Y17 N A VCCAUX R18 N A VCCAUX F19 N A VCCAUX V19 N A VCCAUX H23 N A VCCAUX L24 N A VCCAUX AC24 N A VCCAUX P25 N A VCCAUX AF25 N A VCCAUX G26 N A VCCAUX W26 N A VCCAUX AJ26 N A VCCAUX AB27 N A VCCINT K7 N A VCCINT AB7 N A VCCINT AF9 N A VCCINT L10 N A VCCINT K11 N A VCCINT AB11 N A VCCINT J12 N A VCCINT L12 N A VCCINT R12 N A VCCINT AC12 N A VCCINT 2 VCCINT K13 N A VCCINT M13 N A VCCINT T13 N A VCCINT AD13
215. SelectIO and Bank Information 262 FF1513 Package Pinout Diagram LX100 LX160 and LX200 263 FF1513 Color Coded SelectIO and Bank Information 264 FF1517 Package Pinout Diagram 0 265 FF1517 Package Pinout Diagram 40 266 FF1517 Color Coded SelectIO and Bank Information 267 Chapter 4 Mechanical Drawings ee 269 SF363 Flip Chip Fine Pitch BGA Package Specifications 0 80 mm pitch 270 FF668 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 271 FF672 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 272 FF676 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 273 FF1148 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 274 FF1152 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 275 FF1513 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 276 FF1517 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 277 Chapter 5 Thermal Specifications P tear 279 80 Ora P 279 4 5 281
216. Specification www xilinx com 65 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 66 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices N A GNDA_103 125 NC N A GNDA_103 L25 NC N A GNDA 103 N25 NC N A GNDA 103 T25 NC N A GNDA 105 AF19 N A GNDA_105 AE20 N A GNDA_105 AE22 N A GNDA_105 AF22 N A GNDA_105 W25 N A GNDA_105 AA25 N A GNDA_105 AE25 N A GNDA_110 AC2 N A GNDA_110 AE3 N A GNDA_110 AE6 N A GNDA_110 AE9 N A GNDA_110 AF9 N A GNDA_110 AE11 N A GNDA_110 AF12 N A GNDA_112 N2 NC N A GNDA_112 R2 NC N A GNDA_112 U2 NC N A GNDA_112 2 NC N A GNDA_113 n N A GNDA 113 M1 N A 113 B2 N A GNDA 113 F2 N A 113 12 GNDA_113 K2 N A GNDA_113 L2 N A GNDA 113 M2 N A GNDA 113 B3 N A GNDA 113 A5 N A GNDA 113 B5 N A SM 2 AE18 NC N A VREFP_SM 2 AE17 NC N A AVDD SM 9 AE16 NC www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pi
217. T BUSY 0 T14 0 TDI 0 U11 0 TDN_O E12 0 TDP 0 F12 1 IO L1P D31 IC 1 J15 1 IO LIN D30 LC 1 J14 1 IO 12 D29 IC 1 K13 1 IO D28 LC 1 JA3 1 IO 13 D27 IC 1 H14 1 IO L3N D26 LC 1 G14 1 IO_L4P_D25_LC_1 H13 1 IO_L4N_D24 VREF LC 1 H12 1 IO_L5P_D23_LC_1 J16 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 51 Chapter 2 Pinout Tables 52 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 1 IO_L5N_D22_LC_1 H16 1 IO L6P D21 LC 1 K12 1 IO L6N D20 LC 1 Kil 1 IO_L7P_D19_LC_1 G16 1 IO L7N D18 LC 1 G15 1 IO_L8P_D17_CC_LC_1 H11 1 IO_L8N_D16_CC_LC_1 J11 2 IO LIP D15 CC IC 2 V16 2 IO LIN D14 CC IC 2 W16 2 IO L2P D13 LC 2 Y12 2 IO L2N D12 LC 2 Yul 2 IO_L3P_D11_LC_2 U16 2 IO L3N D10 LC 2 U15 2 IO L4P LC 2 wil 2 IO D8 VREF IC 2 vi 2 IO L5P D7 LC 2 W15 2 IO_L5N_D6_LC_2 W14 2 IO_L6P_D5_LC_2 Y13 2 IO L6N D4 IC 2 W13 2 IO L7P D3 LC 2 U14 2 IO L7N D2 IC 2 V14 2 IO L8P D1 LC 2 V13 2 IO L8N D0 LC 2 V12 3 IO LIP GC CC IC 3 F15 3 IO LIN GC CC IC 3 E15 3 IO L2P GC VRN LC 3 F14 3 IO GC VRP IC 3 F13 3 IO L3P GC LC 3 D15 3 IO L3N GC LC 3 D14 3 IO L4P GC LC 3 D13 3 IO GC VREF LC 3 E13 3 IO L5P GC LC 3 C14 3 IO
218. T22 2 VCCO_2 AU19 2 VCCO_2 AV16 2 VCCO_2 AW23 3 VCCO_3 20 3 VCCO_3 N21 4 VCCO_4 AG19 4 VCCO_4 AK20 5 VCCO_5 A27 5 VCCO_5 A37 5 VCCO_5 B34 5 VCCO_5 C31 5 VCCO_5 D28 5 VCCO_5 F32 5 VCCO_5 G29 5 VCCO_5 H26 5 VCCO_5 K30 5 VCCO 5 L27 6 VCCO 6 A7 6 VCCO 6 B14 6 VCCO 6 C11 6 VCCO 6 D8 6 VCCO_6 E15 6 VCCO_6 F12 6 VCCO 6 G9 6 VCCO 6 J13 6 VCCO_6 K10 7 VCCO_7 AK30 7 VCCO_7 AL27 7 VCCO_7 AN31 7 VCCO_7 AP28 7 VCCO_7 AR25 7 VCCO_7 AT32 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 183 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 7 VCCO_7 AU29 7 VCCO_7 AV26 7 VCCO_7 AW33 8 VCCO_8 AJ13 8 VCCO 8 AK10 8 VCCO_8 AM14 8 VCCO_8 AN11 8 VCCO_8 8 8 VCCO 8 AT12 8 VCCO 8 AUS 8 VCCO 8 AV6 8 VCCO 8 AW13 8 VCCO_8 AW3 9 VCCO_9 D38 9 VCCO_9 E35 9 VCCO_9 G39 9 VCCO_9 H36 9 VCCO_9 J33 9 VCCO_9 L37 9 VCCO_9 M34 9 VCCO_9 N31 9 VCCO_9 P28 10 VCCO_10 B4 10 VCCO_10 C1 10 VCCO 10 E5 10 VCCO_10 F2 10 VCCO_10 H6 10 VCCO_10 L7 10 VCCO_10 N11 10 VCCO 10 P8 10 VCCO 10 R15 10 VCCO 10 T12 11 VCCO 11 AD28 11 VCCO 11 AE25 11 VCCO 11 AF32 11 VCCO 11 AG29 11 VCCO 11 AJ33 11 VCCO 11 AM34 184 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075
219. VCCINT L17 N A VCCINT T17 N A VCCINT U17 N A VCCINT V17 N A VCCINT K18 N A VCCINT L18 N A VCCINT T18 N A VCCINT U18 Notes 1 This voltage is also referred to as Vcc in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package FF672 Flip Chip Fine Pitch BGA Package As shown in Table 2 3 Virtex 4 XC4VFX60 XC4VFX40 and XC4VFX20 devices are available in the FF672 flip chip fine pitch BGA package The No Connect column in Table 2 3 shows pins that are not available in FX20 devices To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Bank Pin Description Pin Number No Connects in FX20 Devices 0 HSWAPEN 0 K16 0 CCLK 0 M14 0 DIN 0 L13 0 PROG B 0 K17 0 INIT B 0 L15 0 CSBO0 M12 0 DONE 0 K15 0 RDWR B 0 R11 0 VBATT 0 L17 0 M20 M16 0 PWRDWN B 0 U12 0 TMS 0 T10 0 MO 0 P14 0 TDO 0 R13 0 TCK 0 U10 0 0 R15 0 DOU
220. Virtex 4 FPGA Packaging and Pinout Specification UGO075 v3 3 September 19 2008 XILINX 7 XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING
221. X35 The No Connect column in Table 2 2 shows pins that are not available in LX15 SX25 and FX12 devices To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Bank Pin Description Pin Number LX15 diris 0 HSWAPEN 0 G16 0 CCLK 0 G14 0 D IN 0 G12 0 PROG B 0 H15 0 INIT B 0 G15 0 CS BO G11 0 DONE 0 H14 0 RDWR B 0 H12 0 VBATT 0 Y16 0 M2 0 W14 0 PWRDWN B 0 W13 0 TMS 0 Y11 0 0 W15 0 TDO 0 Y13 0 TCK 0 W12 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 31 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 2 FF668 Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 Devices Continued Bank Pin Description Pin Number LX15 e I 0 M1_0 Y15 0 DOUT BUSY 0 Y14 0 TDI 0 Y12 0 0 G13 0 TDP 0 H13 1 IO L1P D31 LC 1 F14 1 IO D30 LC 1 F13 1 IO L2P D29 IC 1 F12 1 1 2 D28 LC 1 F11 1 IO_L3P_D27_LC_1 F16 1 IO L3N D26 LC 1 F15 1 IO L4P D25 LC 1 D14 1 IO_L4N_D24 VREF LC_1 D13 1 IO_L5P_D23_LC_1 D15 1 IO_L5N_D22_LC_1 E
222. XB_109 AP13 NC 109 RXNPADB_109 AP15 NC 110 AVCCAUXRXA_110 AD2 110 RXPPADA_110 ACI 110 VTRXA_110 110 RXNPADA 110 AD1 110 AVCCAUXMGT_110 AL2 110 AVCCAUXTX_110 AH2 110 110 AF2 110 TXPPADA_110 110 TXNPADA_110 AGI 110 VTTXB_110 AJ2 110 TXPPADB 110 1 110 TXNPADB 110 AJ 110 AVCCAUXRXB 110 AM2 110 RXPPADB 110 110 VTRXB_110 AK1 110 RXNPADB_110 AM1 110 MGTCLK_P_110 AP3 110 MGTCLK_N_110 AP4 110 110 AN3 110 MGTVREF_110 AN5 112 AVCCAUXRXA_112 N2 112 RXPPADA_112 M1 112 VTRXA 112 P1 112 RXNPADA 112 N1 112 AVCCAUXMCT 112 Y2 112 AVCCAUXIX 112 U2 112 VTTXA 112 R2 112 TXPPADA 112 R1 112 TXNPADA 112 T1 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 145 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Ba k Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 112 VTTXB 112 V2 112 TXPPADB 112 U1 112 TXNPADB 112 V1 112 AVCCAUXRXB 112 AB2 112 RXPPADB 112 Y1 112 VTRXB 112 W1 112 RXNPADB_112 AA1 113 AVCCAUXRXA 113 B6 113 113 A7 113 VTRXA 113 A5 113 RXNPADA 113 A6 113 AVCCAUXMCGT 113 F2 113 AVCCAUXTX 113 C2 113 113 B4 113 TXPPADA 113 A4 113 TXNPADA_ 113
223. XILINX Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices Continued Bank Pin Description Pin Da connect m 1x0 Number LX60 and SX55 Devices 2 IO_L9P_GC_CC_LC_2 AC19 2 IO_LIN_GC_CC_LC_2 AB18 2 IO_L10P_GC_LC_2 AD16 2 IO GC LIC 2 AF15 2 IO L11P GC LC 2 AN20 2 IO L11N GC IC 2 AP20 2 IO L12P GC IC 2 AD17 2 IO L12N VREF IC 2 AC17 2 IO_L13P_GC_LC_2 AM20 2 IO_L13N_GC_LC_2 AL19 2 IO_L14P_GC_LC_2 7 2 IO L14N GC IC 2 AB16 2 IO L15P GC LIC 2 AL18 2 IO GC IC 2 AM18 2 IO_L16P_GC_LC_2 AM17 2 IO_L16N_GC_LC_2 AM16 2 IO L17P LC 2 AD21 2 IO L17N LC 2 AD20 2 IO L18P LC 2 AM15 2 IO_L18N_LC_2 AL15 2 IO L19P LC 2 AJ20 2 IO L19N LC 2 AL20 2 IO L20P LC 2 AJ15 2 IO 1208 VREF IC 2 AJ14 2 IO L21P LC 2 AG20 2 IO L21N IC 2 AH20 2 IO L22P LC 2 AG15 2 IO L22N 1 6 2 AH14 2 IO_L23P_VRN_LC_2 AD19 2 IO L23N VRP IC 2 AE19 2 IO_L24P_CC_LC_2 AL16 2 IO L24N CC IC 2 AK16 3 IO L1P GC CC IC 3 F18 3 IO LIN GC CC IC 3 G18 92 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1148 Flip Chip Fine Pitch BGA Package Table 2 5 FF1148 Package LX40 LX60 LX80 LX100 LX160 and SX55 Devices
224. _L5N_GC_LC_3 B14 3 IO_L6P_GC_LC_3 C13 3 IO_L6N_GC_LC_3 C12 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices 3 IO L7P GC IC 3 A14 3 IO GC LC 3 A13 3 IO GC LC 3 A12 3 IO L8N GC LC 3 B12 4 IO LIP GC LC 4 AE15 4 IO LIN GC LC 4 AF15 4 IO L2P GC LC 4 AF14 4 IO L2N GC LC 4 AF13 4 IO L3P GC LC 4 AD15 4 IO L3N GC LC 4 AD14 4 IO_L4P_GC_LC_4 AE13 4 IO GC VREF IC 4 AD13 4 IO L5P GC LC 4 AB14 4 IO_L5N_GC_LC_4 AC14 4 IO_L6P_GC_LC_4 AC13 4 IO L6N GC LC 4 AC12 4 IO_L7P_GC_VRN_LC_4 4 4 IO_L7N_GC_VRP_LC_4 AA13 4 IO L8P GC CC LIC 4 AB12 4 IO_L8N_GC_CC_LC 4 AA12 5 IO ADC7 5 G20 5 IO LIN ADC7 5 F20 5 IO L2P ADC6 5 H19 5 IO L2N ADC6 5 J19 5 IO 13 ADC5 5 E22 5 IO L3N ADC5 5 E21 5 IO 5 G19 5 IO_L4N_VREF_5 H18 5 IO_L5P_ADC4_5 G21 5 IO_L5N_ADC4_5 F22 5 IO L6P ADC3 5 F19 5 IO L6N ADC3 5 F18 5 IO L7P ADC2 5 E23 5 IO L7N ADC2 5 D23 5 IO L8P CC ADCI1 IC 5 E20 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 53 Chapter 2 Pinout Tables 54 XILINX
225. _SM1_7 V17 7 IO_L32N_SM1_7 V18 7 IO_L20P_7 R19 7 IO L20N VREF 7 R20 7 IO L21P 7 R15 7 IO L21N 7 R16 7 IO I23P VRN 7 T19 7 IO L23N VRP 7 T20 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 7 XILINX SF363 Flip Chip Fine Pitch BGA Package Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 7 IO L24P CC LC 7 R17 7 IO L24N CC IC 7 R18 8 IO L25P CC LC 8 U3 8 IO_L25N_CC_LC_8 U2 8 IO_L26P_8 T4 8 IO_L26N_8 T3 8 IO L27P 8 T6 8 IO L27N 8 U6 8 IO L28P 8 V2 8 IO L28N 8 V1 8 IO L29P 8 U5 8 IO_L29N_8 UA 8 IO L30P 8 W3 8 IO L30N 8 W2 8 IO_L31P_8 Y4 8 IO_L31N_8 W4 8 IO_L32P_8 V4 8 IO_L32N_8 V3 8 IO_L20P_8 R2 8 IO L20N VREF 8 R1 8 IO 1215 8 R6 8 IO L21N 8 R5 8 IO L23P VRN 8 T2 8 IO L23N VRP 8 T1 8 IO L24P CC LC 8 R4 8 IO L24N CC LC 8 R3 0 VCCO 0 D10 0 VCCO 0 U11 1 VCCO_1 D7 1 VCCO_1 D14 2 VCCO_2 U7 2 VCCO_2 U14 3 VCCO_3 A9 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 27 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 28 XILINX Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Descr
226. _VREF_5 G33 5 IO_L29P_5 A35 5 IO L29N 5 A36 5 IO L30P 5 J31 5 IO L30N 5 K31 5 IO L31P 5 B36 5 IO L31N 5 B37 5 IO L32P 5 L30 5 IO L32N 5 L31 6 IO L1P 6 A14 6 IO LIN 6 A13 6 IO 2 6 E12 6 IO 6 E11 6 IO L3P 6 B13 6 IO L3N 6 C13 6 IO 6 D11 6 IO LAN VREF 6 D10 6 IO L5P 6 D14 6 IO_L5N_6 C14 6 IO L6P 6 All 6 IO L6N 6 A10 6 IO 17 6 E13 6 IO L7N 6 F13 6 IO L8P CC IC 6 B10 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 163 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 6 IO L8N CC IC 6 C10 6 IO L17P 6 J14 6 IO L17N 6 H13 6 IO L18P 6 E9 6 IO L18N 6 F9 6 IO L19P 6 C12 6 IO L19N 6 D12 6 IO L20P 6 B7 6 IO L20N VREF 6 C7 6 IO L21P 6 D15 6 IO L21N 6 C15 6 IO 22 6 G10 6 IO L22N 6 H10 6 IO L23P VRN 6 A9 6 IO L23N VRP 6 A8 6 IO_L24P_CC_LC_6 E8 6 IO_L24N_CC_LC_6 F8 6 IO L9P CC IC 6 F14 6 IO L9N CC IC 6 E14 6 IO L10P 6 H12 6 IO L10N 6 JA2 6 IO L11P 6 G13 6 IO_L11N_6 G12 6 IO L12P 6 C9 6 IO L12N VREF 6 D9 6 IO L13P 6 B15 6 IO L13N 6 A15 6 IO L14P 6 F11 6 IO L14N 6 G11 6 IO L15P 6 B12 6 IO L15N 6 B11 6 IO_L16P_6 B8 6 IO L16N 6 C8 6 IO L25P CC IC 6 E16 6 IO L25N CC 6 D16 6 IO L26P 6 D7 6 IO L26N 6 E7 6 IO 27 6 A6
227. airflow to schemes that can include passive as well as active heat sinks This is particularly true for the bigger flip chip BGA packages where system designers have the option to further enhance the packages with bigger and more elaborate heat sinks to handle excesses of 20 watts with arrangements that consider system physical constraints Some Thermal Management Options The flip chip thermal management chart in Figure 5 2 illustrates simple but incremental power management schemes that can be applied on a flip chip BGA package 282 Low End Bare Package with 1 6Watts Moderate Air 8 12 C Watt Bare Package Package can be used with moderate airflow within a system Mid Range Passive H S Air 4 10 Watts 5 10 C Watt Packaged Used with Various Forms of Passive Heat Sinks Heat spreader techniques High End Active Heat Sink Package Used with 8 25 Watts 2 3 C Watt Active Heat Sinks or Better TEC and board level heat spreader techniques UGO075 c5 02 091205 Figure 5 2 Thermal Management Options for Flip Chip BGA Packages For moderate power dissipation less than 6 watts the use of passive heat sinks and heat spreaders attached with thermally conductive double sided tapes or retainers with TIM around 0 2 C watt can offer quick thermal solutions in these packages The use of lightweight finned external passive heat sinks can be effective for dissipati
228. and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices N A VCCINT AA20 N A VCCINT AC20 N A VCCINT M21 N A VCCINT T21 N A VCCINT V21 N A VCCINT Y21 N A VCCINT AB21 N A VCCINT R22 N A VCCINT U22 N A VCCINT W22 N A VCCINT AA22 N A VCCINT T23 N A VCCINT V23 N A VCCINT Y23 N A VCCINT AB23 N A VCCINT R24 N A VCCINT U24 N A VCCINT AC24 N A VCCINT P25 N A VCCINT T25 N A VCCINT V25 N A VCCINT M27 Notes 1 This voltage is also referred to as Vcc_conric in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 155 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables FF1513 Flip Chip Fine Pitch BGA Package As shown in Table 2 7 Virtex 4 XC4VLX100 XC4VLX160 and XC4VLX200 devices are available in the FF1513 flip chip fine pitch BGA package Pinouts in each of these devices are identical XILINX To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to th
229. at are not available in FX100 devices To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 8 FF1517 Package FX140 and FX100 Devices Bank Pin Description Pin Number jb aedi 0 HSWAPEN 0 V23 0 CCLK 0 W20 0 DIN 0 Y16 0 PROG B 0 W22 0 INIT B 0 V24 0 CS BO Y17 0 DONE 0 Y19 0 RDWR B 0 Y18 0 VBATT 0 W24 0 M2 0 Y22 0 PWRDWN B 0 Y21 0 TMS 0 AA16 0 0 Y23 0 0 AB16 0 TCK 0 AA18 0 0 24 0 DOUT BUSY 0 AA20 0 TDI 0 AB17 0 0 E18 0 TDP 0 E19 1 IO L1P D31 ILC 1 L24 1 IO D30 LC 1 K23 1 IO 12 D29 IC 1 D17 1 IO L2N D28 LC 1 E17 1 IO L3P D27 LC 1 K24 1 IO L3N D26 LC 1 J24 1 IO_L4P_D25_LC_1 L16 1 IO D24 VREF LC 1 M16 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 197 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 1 IO L5P D23 LC 1 H24 1 IO L5N D22 LC 1 H23 1 IO L6P D21 LC 1 J16 1 IO LoN D20 LC 1 K16 1 IO L7P D19 LC 1 M25 1 IO L7N D1
230. ber 19 2008 73 Chapter 2 Pinout Tables XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee 5 IO L27P 5 A25 5 IO 27 5 B25 5 IO L28P 5 G21 5 IO L28N VREF 5 G22 5 IO L29P 5 B26 5 IO L29N 5 C26 5 IO L30P 5 D25 5 IO L30N 5 D26 5 IO L31P 5 E25 5 IO L31N 5 E26 5 IO L32P 5 F24 5 IO L32N 5 F25 6 IO L1P 6 G11 6 IO_LIN_6 F10 6 IO L2P 6 E11 6 IO_L2N_6 E10 6 IO L3P 6 D11 6 IO L3N 6 D10 6 IO 6 G9 6 IO_L4N_VREF_6 H9 6 IO_L5P_6 C11 6 IO L5N 6 B11 6 IO_L6P_6 B10 6 IO_L6N_6 A10 6 IO L7P 6 A9 6 IO L7N 6 A8 6 IO L8P CC LC 6 C9 6 IO L8N CC IC 6 B9 6 IO L17P 6 F8 6 IO L17N 6 E7 6 IO L18P 6 B4 6 IO L18N 6 C4 6 IO_L19P_6 E6 6 IO L19N 6 F7 6 IO L20P 6 J8 6 IO L20N VREF 6 K8 74 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee ee 6 IO L21P 6 E5 6 IO L21N 6 D5 6 IO L22P 6 A2 6 IO L22N 6 B1 6 IO_L23P_VRN_6 G7 6 IO_L23N_VRP_6 G6 6 IO L24P CC LC 6 C3 6 IO L24N CC LC 6 C2 6 IO L9P CC IC 6 D9 6 IO L9N CC IC 6 C
231. ces N A VCCINT 122 VCCINT W22 N A VCCINT AC22 N A VCCINT AE22 N A VCCINT X23 N A VCCINT M23 N A VCCINT Y23 N A VCCINT AD23 N A VCCINT AF23 N A VCCINT N24 N A VCCINT AE24 N A VCCINT AD25 N A VCCINT J26 N A VCCINT N28 N A VCCINT AE28 Notes 1 This voltage is also referred to as Vcc in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package FF1152 Flip Chip Fine Pitch BGA Package As shown in Table 2 6 Virtex 4 XC4VFX40 XC4VFX60 and XC4VFX100 devices are available in the FF1152 flip chip fine pitch BGA package The No Connect columns in Table 2 6 show pins that are not available in FX60 and FX40 devices To be assured of having the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 0 HSWAPEN 0 P20 0 CCLK 0 T18 0 D IN 0 R17 0 PRO
232. ckage Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number AVCCAUXMGT_106 AV22 N A AVCCAUXTX_106 AV25 N A VTTXA_106 AV28 N A TXPPADA_106 AW28 N A TXNPADA_106 AW27 N A VTTXB 106 AV24 N A TXPPADB 106 AW25 N A TXNPADB_106 24 AVCCAUXRXB_106 AV21 N A RXPPADB_106 AW22 N A VTRXB_106 AW23 N A RXNPADB_106 AW21 N A AVCCAUXRXA_109 AV10 N A RXPPADA_ 109 AW9 N A VTRXA_109 11 RXNPADA_109 AW10 N A AVCCAUXMGT_109 AV18 N A AVCCAUXTX_109 AV15 N A VTTXA_109 AV12 N A TXPPADA_109 AW12 N A TXNPADA_109 AW13 N A VTTXB_109 AV16 N A TXPPADB_109 15 TXNPADB 109 AW16 N A AVCCAUXRXB_109 AV19 N A RXPPADB_109 AW18 N A VTRXB_109 AW17 N A RXNPADB_109 AW19 N A AVCCAUXRXA_110 AM2 N A RXPPADA_110 110 AN1 N A RXNPADA_110 AM1 N A AVCCAUXMGT_110 AV3 N A AVCCAUXTX_110 AT2 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 225 Chapter 2 Pinout Tables 226 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices N A 110 AP2 N A TXPPADA 110 AP1
233. d Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 105 RXPPADB_105 AP32 105 VTRXB_105 AN33 105 RXNPADB_105 AP31 105 MGTCLK_P_105 AP29 105 MGTCLK_N_105 AP28 105 RTERM_105 AN29 105 MGTVREF 105 AN27 106 AVCCAUXRXA_106 AN25 NC 106 RXPPADA_106 AP26 NC 106 VTRXA_106 AP24 NC 106 RXNPADA_106 AP25 NC 106 AVCCAUXMGT_106 AN18 NC 106 AVCCAUXTX_106 AN22 NC 106 VITXA_106 AN23 NC 106 TXPPADA_106 AP23 NC 106 TXNPADA 106 AP22 NC 106 VTTXB 106 AN20 NC 106 TXPPADB 106 AP21 NC 106 TXNPADB 106 AP20 NC 106 AVCCAUXRXB 106 AN17 NC 106 RXPPADB_106 AP18 NC 106 VTRXB 106 AP19 NC 106 RXNPADB 106 AP17 NC 109 AVCCAUXRXA 109 AN7 NC 109 RXPPADA_109 AP6 NC 109 VTRXA_109 AP8 NC 109 RXNPADA_109 AP7 NC 109 AVCCAUXMGT_109 AN14 NC 109 AVCCAUXTX_109 AN10 NC 109 VTTXA 109 NC 109 TXPPADA_109 AP9 NC 109 TXNPADA 109 AP10 NC 109 VTTXB 109 AN12 NC 109 TXPPADB_109 AP11 NC www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 109 TXNPADB_109 AP12 NC 109 AVCCAUXRXB_109 AN15 NC 109 RXPPADB 109 AP14 NC 109 VTR
234. d is not cooled effectively An otherwise cooler component can be heated by other heat contributing components on the board Support for Compact Thermal Models CTM Table 5 1 provides the traditional thermal resistance data for Virtex 4 devices These resistances are measured using a prescribed JEDEC standard that may not necessarily reflect the actual user environment The quoted 0 4 and numbers are environmentally dependent and JEDEC has traditionally recommended that these be used with that awareness For more accurate junction temperature prediction these may not be enough and a system level thermal simulation may be required Though Xilinx will continue to support these figure of merit data for Virtex 4 FPGA boundary condition independent compact thermal models BCI CTM are available to assist end users in their thermal simulations Two resistor as well as eight to 10 resistor network models are offered for all Virtex 4 devices These compact models seek to capture the thermal behavior of the packages more accurately at pre determined critical points junction case top leads etc with the reduced set of nodes as illustrated in Figure 5 3 Unlike a full 3D model these are computationally efficient and work well in an integrated system simulation environment The two resistor model can be made up with the data provided in Table 5 1 Delphi CTM models are available on the Xilinx support download center at http www xilinx co
235. ed Bank Pin Description Pin Number 9 VCCO_9 M34 9 VCCO_9 E35 9 VCCO_9 H36 9 VCCO_9 C37 9 VCCO_9 L37 10 VCCO_10 J3 10 VCCO 10 M4 10 VCCO_10 R5 10 VCCO 10 H6 10 VCCO 10 L7 10 VCCO 10 P8 10 VCCO 10 U9 10 VCCO 10 N11 10 VCCO 10 T12 11 VCCO 11 AD28 11 VCCO 11 AG29 11 VCCO 11 AC31 11 VCCO_11 AF32 11 VCCO 11 AJ33 11 VCCO 11 AM34 11 VCCO 11 AE35 11 VCCO_11 AH36 11 VCCO 11 AL37 12 VCCO 12 AUS 12 VCCO 12 AMA 12 VCCO 12 AR5 12 VCCO 12 AH6 12 VCCO 12 AL7 12 VCCO 12 ADS 12 VCCO 12 AG9 12 VCCO_12 AC11 12 VCCO_12 AB14 13 VCCO 13 AB24 13 VCCO 13 AA27 13 VCCO 13 Y30 13 VCCO 13 W33 13 VCCO 13 AB34 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 221 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 222 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices 13 VCCO_13 R35 13 VCCO_13 V36 13 VCCO_13 AA37 14 VCCO_14 W3 14 VCCO 14 AJ3 14 VCCO 14 4 14 VCCO_14 AE5 14 VCCO 14 V6 14 VCCO 14 AA7 14 VCCO 14 Y10 14 VCCO 14 W13 14 VCCO 14 V16 N A AVCCAUXRXA 101 B22 N A RXPPADA 101 A21 N A 101 A23 N A 101 A22 N A AVCCAUXMGT 101 B29 N A AVC
236. ed pinout diagram Figure 3 23 Figure 3 18 Changed AH3 and AH4 to CC changed AC34 to RXPPADB Figure 3 25 Removed SelectIO pin designation on AA3 Table 5 1 Corrected 4 0 LFM for XC4VFX20 FF672 from 13 3 to 13 5 Added Chapter 6 Package Marking 06 08 07 9 1 Introduction in Chapter 1 Added text advising that VCCO_ pins listed as No Connects can be required for larger devices Table 1 3 Added text to Description of PWRDWN_B_0 advising to leave pin floating Table 2 7 Corrected note callout on AVDD ADC pin B22 to 3 Chapter 6 Deleted section Virtex 4 LX SX and FX Device Marking 05 29 08 32 Table 1 3 Rephrased last sentence of PWRDWN B 0 description describing how to connect this signal Figure 3 14 page 256 Corrected symbols for AE16 and AG16 in pinout diagram Figure 4 1 page 270 Updated drawing including JEDEC specification in Note 3 Updated References page 284 09 19 08 3 3 Figure 3 14 page 256 Corrected symbol for AG16 in pinout diagram UGO075 v3 3 September 19 2008 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 Table of Contents deed ee Gel eee ag 2 Preface About This Guide Organization of This Guides 7 Related Documentation unusu 0000s y Additional Reso
237. em level down to the minute details This guide focuses on strategies for making design decisions at the PCB and interface level e Virtex 4 RocketIO Multi Gigabit Transceiver User Guide This guide describes the RocketIO Multi Gigabit Transceivers available in the Virtex 4 FX family e Virtex 4 FPGA Embedded Tri Mode Ethernet MAC User Guide This guide describes the Tri Mode Ethernet Media Access Controller available in the Virtex 4 FX family e PowerPC 405 Processor Block Reference Guide This guide is updated to include the PowerPC 405 processor block available in the Virtex 4 FX family Additional Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase visit the following Xilinx website http www xilinx com support 8 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Typographical Conventions Typographical Conventions The following typographical conventions are used in this document Convention Meaning or Use Example See the Virtex 4 Configuration References to other documents Guide for more information Italic font sd The address F is asserted after Emphasis in text clock event 2 Underlined Text Indicates a link to a web page http www xilinx com virtex4 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG
238. ging and Pinout Specification www xilinx com 17 UG075 v3 3 September 19 2008 Chapter 1 Packaging Overview 18 XILINX www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Chapter 2 Pinout Tables Summary This chapter provides pinout information for the following packages SF363 Flip Chip Fine Pitch BGA Package LX15 LX25 and FX12 devices are available in this package FF668 Flip Chip Fine Pitch BGA Package LX15 LX25 LX40 LX60 SX25 SX35 and FX12 devices are available in this package FF672 Flip Chip Fine Pitch BGA Package FX60 FX40 and FX20 devices are available in this package FF676 Flip Chip Fine Pitch BGA Package LX15 and LX25 devices are available in this package FF1148 Flip Chip Fine Pitch BGA Package LX40 LX60 LX80 LX100 LX160 and SX55 devices are available in this package FF1152 Flip Chip Fine Pitch BGA Package FX100 FX60 and FX40 devices are available in this package FF1513 Flip Chip Fine Pitch BGA Package LX100 LX160 and LX200 devices are available in this package FF1517 Flip Chip Fine Pitch BGA Package FX140 and FX100 devices are available in this package Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 19 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables SF363 Flip Chip Fine Pitch BGA Package As shown in Table 2 1 Virtex 4 XC4VLX15 XC4VLX25 and XC4VFX12 devices are available in the S
239. ication www xilinx com UG075 v3 3 September 19 2008 29 Chapter 2 Pinout Tables 30 XILINX Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 a ies N A GND P18 N A GND A19 N A GND Y19 N A GND A20 N A GND B20 N A GND W20 N A GND Y20 N A VCCAUX H6 N A VCCAUX N6 N A VCCAUX F8 N A VCCAUX R8 N A VCCAUX F13 N A VCCAUX R13 N A VCCAUX H15 N A VCCAUX N15 N A VCCINT G6 N A VCCINT P6 N A VCCINT F7 N A VCCINT G7 N A VCCINT P7 N A VCCINT R7 N A VCCINT F14 N A VCCINT G14 N A VCCINT P14 N A VCCINT R14 N A VCCINT G15 N A VCCINT P15 Notes 1 This voltage is also referred to as Vec_conric in the Virtex 4 Configuration Guide 2 Connect this reserved pin to GND 3 Connect this reserved pin to 2 5V sharing the same PCB supply distribution as Vccayx is acceptable www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 FF668 Flip Chip Fine Pitch BGA Package FF668 Flip Chip Fine Pitch BGA Package As shown in Table 2 2 the following Virtex 4 LX and SX devices are available in the FF668 flip chip fine pitch BGA package e XCAVLXI5 e XCAVLX25 e XCAVLXAO e XCAVLX60 e XCAVSX25 e XCAVSX35 e XCAVEXI2 Pinouts in the following devices are identical e LXI5 25 and FX12 e LX25 LX40 LX60 and S
240. ides definitions for all pin types For the very latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 11 UG075 v3 3 September 19 2008 Chapter 1 Packaging Overview Device Package Combinations and Maximum I Os Table 1 1 shows the maximum number of user I Os possible in Virtex 4 FPGA flip chip packages e SF denotes flip chip fine pitch BGA 0 80 mm pitch e FF denotes flip chip fine pitch BGA 1 00 mm pitch XILINX Table 1 1 Flip Chip Packages Package SF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517 Pitch mm 0 80 mm 1 00 mm 1 00 mm 1 00 mm 1 00 mm 1 00 mm 1 00 mm 1 00 mm Size mm 17x17 27x27 27x27 27x27 35x35 35x35 40 x 40 40 x 40 Maximum I Os 240 448 352 448 768 576 960 768 Table 1 2 Virtex 4 FPGA Available I Os and RocketlO MGT Pins per Device Package Combination Table 1 2 shows the number of available I Os the number of RocketIO multi gigabit transceivers MGTs and the number of differential I O pairs for each Virtex 4 XCAVLX XCAVSX and XCAVFX device package combination The number of I Os per package includes all user I Os except the fifteen control pins CCLK DONE M0 M1 M2 PROG B PWRDWN B TCK TDI TDO TMS HSWAPEN DXN DXP AND RSVD and the RocketIO MGT pins AVCCAUXTX AVCCAUXRX AVCCAUXMGT TXP TXN RXP RXN VTTX VTRX MGTCLK MGTVRE
241. inout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description Pin No Connects in No Connects in Number FX60 Devices FX40 Devices 102 RXPPADB_102 194 102 VTRXB_102 H34 102 RXNPADB_102 K34 102 MGTCLK 102 M34 102 MGTCLK_N_102 N34 103 AVCCAUXRXA_103 T33 103 RXPPADA_103 R34 103 VTRXA_103 U34 103 RXNPADA 103 T34 103 AVCCAUXMGT 103 AC33 103 AVCCAUXTX 103 Y33 103 VTTXA 103 V33 103 TXPPADA 103 V34 103 TXNPADA 103 W34 103 VTTXB 103 AA33 103 TXPPADB 103 Y34 103 TXNPADB_103 AA34 103 AVCCAUXRXB_103 AE33 103 RXPPADB_103 AC34 103 VTRXB_103 AB34 103 RXNPADB 103 AD34 105 AVCCAUXRXA 105 AG33 105 105 AF34 105 105 AH34 105 RXNPADA 105 AG34 105 AVCCAUXMGT 105 AN32 105 AVCCAUXTX_105 AL33 105 VTTXA_105 AJ33 105 TXPPADA_105 AJ34 105 TXNPADA_105 AK34 105 VTTXB_105 AM33 105 TXPPADB 105 AL34 105 TXNPADB 105 AM34 105 AVCCAUXRXB_105 AN31 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 143 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 144 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continue
242. iption Pin Number in LX1 a ies 3 VCCO_3 A12 4 VCCO 4 Y8 4 VCCO 4 Y13 5 VCCO 5 K15 5 VCCO 5 L15 5 VCCO 5 A17 5 VCCO 5 E17 5 VCCO 5 L18 5 VCCO 5 D20 5 VCCO 5 120 5 VCCO 5 N20 6 VCCO_6 D1 6 VCCO_6 jl 6 VCCO_6 N1 6 VCCO_6 L3 6 VCCO 6 A4 6 VCCO_6 E4 6 VCCO_6 K6 6 VCCO_6 L6 7 VCCO 7 T16 7 VCCO_7 Y18 7 VCCO_7 U20 8 VCCO 8 U1 8 VCCO 8 Y3 8 VCCO_8 T5 N A VREFP SM W14 NC N A VREFN_SM 2 W15 NC N A AVDD SM 9 W16 NC N A VP SM 2 Y14 NC VN SM Y15 NC N A AVSS SM 9 Y16 NC GND B1 N A GND wi www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX SF363 Flip Chip Fine Pitch BGA Package Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 nas N A GND 1 GND A2 N A GND Y2 N A GND G3 N A GND P3 N A GND C7 N A GND H7 N A GND J7 N A GND K7 N A GND L7 N A GND M7 N A GND N7 N A GND V7 N A GND G8 N A GND P8 N A GND G9 N A GND po N A GND G10 N A GND P10 N A GND U10 N A GND D11 N A GND G11 N A GND P11 N A GND G12 N A GND P12 N A GND G13 N A GND P13 N A GND C14 N A GND H14 N A GND J14 N A GND K14 N A GND L14 N A GND M14 N A GND N14 N A GND V14 N A GND G18 Virtex 4 FPGA Packaging and Pinout Specif
243. is document ASCII package pinout files are also available for download from the Xilinx website Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Bank Pin Description Pin Number 0 HSWAPEN 0 V23 0 CCLK 0 W20 0 D IN 0 Y16 0 PROG B 0 W22 0 INIT B 0 V24 0 CSBO0 Y17 0 DONE 0 Y19 0 RDWR B 0 Y18 0 VBATT 0 W24 0 M20 Y22 0 PWRDWN B 0 Y21 0 TMS 0 AA16 0 0 Y23 0 TDO 0 AB16 0 TCK_0 AA18 0 0 Y24 0 DOUT BUSY 0 AA20 0 TDI 0 AB17 0 TDN 0 H19 0 TDP 0 H20 1 IO L1P D31 IC 1 F26 1 IO LIN D30 LC 1 F25 1 IO L2P D29 IC 1 K16 1 IO I2N D28 LC 1 L16 1 IO L3P D27 IC 1 E26 1 IO L3N D26 LC 1 D26 1 IO D25 IC 1 J16 1 IO LAN D24 VREF IC 1 H15 1 IO_L5P_D23_LC_1 M25 1 IO_L5N_D22_LC_1 N24 156 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 1 IO 6 D21 IC 1 G16 1 IO L6N D20 LC 1 G15 1 IO 17 D19 IC 1 T23 1 IO L7N D18 LC 1 R22 1 IO L8P D17 CC IC 1 A16 1 IO L8N D16 CC IC 1 B16 1 IO L9P GC LC 1 C20 1 IO GC IC 1 D20 1 IO L10P GC LC 1 D19 1 I
244. kage e SF363 Package Pinout Diagram LX15 and FX12 page 243 e SE363 Package Pinout Diagram LX25 page 244 e SE363 Color Coded SelectIO and Bank Information page 245 FF668 Package e FF668 Package Pinout Diagram LX15 SX25 and FX12 page 246 e FF668 Package Pinout Diagram LX25 LX40 LX60 and SX35 page 247 e FF668 Color Coded SelectIO and Bank Information page 248 FF672 Package e FF672 Package Pinout Diagram FX20 page 249 e FF672 Package Pinout Diagram FX40 page 250 e FF672 Package Pinout Diagram FX60 page 251 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 241 UG075 v3 3 September 19 2008 242 Chapter 3 Pinout Diagrams XILINX e FF672 Color Coded SelectIO and Bank Information page 252 FF676 Package e FF676 Package Pinout Diagram LX15 page 253 e FF676 Package Pinout Diagram LX25 page 254 e FF676 Color Coded SelectIO and Bank Information page 255 FF1148 Package e FF1148 Package Pinout Diagram LX40 LX60 and SX55 page 256 e FF1148 Package Pinout Diagram LX80 LX100 and LX160 page 257 e FF1148 Color Coded SelectIO and Bank Information page 258 FF1152 Package e FF1152 Package Pinout Diagram FX40 page 259 e FF1152 Package Pinout Diagram FX60 page 260 e FF1152 Package Pinout Diagram FX100 page 261 e FF1152 Color Coded SelectIO and Bank Information page 262
245. m support download index htm Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 283 UG075 v3 3 September 19 2008 Chapter 5 Thermal Specifications XILINX DELPHI BCI CTM Topology for Two Resistor Model FCBGA Junction UG075_c05_02_081905 Figure 5 3 Thermal Model Topologies References The following websites contain additional information on heat management and contact information http www wakefield com e http www aavidthermalloy com http www qats com Refer to the following websites for interface material sources e Power Devices http www powerdevices com Bergquist Company http www bergquistcompany com e AOS Thermal Compound http www aosco com Chomerics http www chomerics com e Kester http www kester com Refer to the following websites for CFD tools that Xilinx supports with thermal models Flomerics Flotherm and FloPCB http www flotherm com e ANSYS Icepak http www ansys com products icepak 284 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Chapter 6 Package Marking Virtex 4 Device Package Marking All Virtex 4 devices have package markings similar to the example shown in Figure 6 1 and explained in Table 6 1 7 XILINX Virtex 4 Device Type XCAVLX25 Circuit Design Revision Cxx Designates a Step 1 Device Dxx Designates a Step 2 Device
246. mation 245 FF668 Package Pinout Diagram LX15 SX25 and 2 246 FF668 Package Pinout Diagram LX25 LX40 LX60 and SX35 247 FF668 Color Coded SelectIO and Bank Information 248 FF672 20 249 FF672 Package Pinout Diagram 40 250 FF672 60 251 FF672 Color Coded SelectIO and Bank Information 252 FF676 Package Pinout Diagram 15 253 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 XILINX FF676 Package Pinout Diagram 25 254 FF676 Color Coded SelectIO and Bank Information 255 FF1148 Package Pinout Diagram LX40 LX60 and 5 55 256 FF1148 Package Pinout Diagram LX80 LX100 and LX160 257 FF1148 Color Coded SelectIO and Bank Information 258 FF1152 Package Pinout Diagram 40 259 FF1152 Package Pinout Diagram 6 260 FF1152 Package Pinout Diagram 0 261 FF1152 Color Coded
247. n Description Pin Number No Connects in FX20 Devices 2 AF18 NC N A VP_SM 2 AF17 NC N A AVSS_SM 9 AF16 NC N A GND G3 N A GND U3 N A GND K4 N A GND Y4 N A GND C5 N A GND N5 N A GND AC5 N A GND F6 N A GND T6 N A GND 17 GND W7 N A GND B8 N A GND M8 N A GND AB8 N A GND E9 N A GND R9 N A GND H10 N A GND V10 N A GND All N A GND L11 N A GND AAT N A GND D12 N A GND P12 N A GND T12 N A GND AD12 N A GND G13 N A GND N13 N A GND U13 N A GND K14 N A GND Y14 N A GND C15 N A GND N15 N A GND AC15 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 67 Chapter 2 Pinout Tables 68 XILINX Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices N A GND F16 N A GND T16 N A GND JA7 N A GND W17 N A GND B18 N A GND M18 N A GND AB18 N A GND E19 N A GND R19 N A GND H20 N A GND V20 N A GND L21 N A GND AA21 N A GND D22 N A GND P22 N A GND AD22 N A GND G23 N A GND U23 N A GND K24 N A GND Y24 N A VCCAUX F5 N A VCCAUX T5 N A VCCAUX J6 N A VCCAUX W6 N A VCCAUX M7 N A VCCAUX N12 N A VCCAUX P15 N A VCCAUX H21 N A VCCAUX L22 N A VCCAUX P23 N A VCCAUX F25 N A VCCAUX G25 N A VCCINT K5 N A VCCINT G6 N A VCCINT T
248. n Pin Number 5 IO L30P 5 D24 5 IO L30N 5 E24 5 IO L31P 5 C33 5 IO L31N 5 C32 5 IO L32P 5 C24 5 IO L32N 5 C23 6 IO L1P 6 C10 6 IO LIN 6 D10 6 1 12 6 H10 6 IO I2N 6 J10 6 IO L3P 6 J11 6 IO L3N 6 K11 6 1 6 F10 6 IO_L4N_VREF_6 G10 6 IO L5P 6 F11 6 IO L5N 6 G11 6 IO L6P 6 H9 6 IO L6N 6 J9 6 IO 17 6 D11 6 IO L7N 6 E11 6 IO_L8P_CC_LC_6 E9 6 IO L8N CC LC 6 F9 6 IO L17P 6 F13 6 IO L17N 6 E13 6 IO L18P 6 C8 6 IO L18N 6 C7 6 IO L19P 6 C13 6 IO L19N 6 C12 6 IO L20P 6 D7 6 IO VREF 6 E7 6 IO L21P 6 J14 6 IO_L21N_6 H14 6 1 122 6 F6 6 IO_L22N_6 F5 6 IO L23P VRN 6 F14 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 203 Chapter 2 Pinout Tables XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 6 IO_L23N_VRP_6 E14 6 IO L24P CC LC 6 D6 6 IO L24N CC LC 6 E6 6 IO L9P CC LC 6 K13 6 IO L9N CC LC 6 JA2 6 IO L10P 6 K9 6 IO L10N 6 L10 6 IO L11P 6 H12 6 IO L11N 6 G12 6 IO L12P 6 C9 6 IO L12N VREF 6 D9 6 IO L13P 6 E12 6 IO L13N 6 D12 6 IO L14P 6 G8 6 IO L14N 6 H8 6 IO L15P 6 H13 6 IO L15N 6 G13 6 IO L16P 6 6 IO_L16N_6 F8 6 IO L25P CC LC 6 D14 6 IO_L25N_CC_LC_6 C14 6 IO_L26P_6 C5 6 IO_L26N_6 D5 6 IO_L27P_6 D15 6 IO_L27N_6 C15 6 IO L28P 6 E4 6 IO L28N
249. n Pin Number in LX1 1 IO L5P D23 LC 1 D13 1 IO L5N D22 LC 1 C13 1 IO L6P D21 LC 1 C8 1 IO L6N D20 LC 1 D8 1 IO_L7P_D19_LC_1 D12 1 IO_L7N_D18_LC_1 C12 1 IO L8P D17 CC LC 1 C9 1 IO L8N D16 CC LC 1 D9 2 IO D15 CC IC 2 V16 2 IO D14 CC LC 2 V15 2 IO L2P D13 LC 2 V6 2 IO L2N D12 IC 2 V5 2 IO L3P D11 LC 2 T14 2 IO D10 LC 2 U13 2 IO L4P D9 ILC 2 U8 2 IO_L4N_D8_VREF_LC_2 T7 2 IO L5P D7 LC 2 V13 2 IO L5N D6 IC 2 V12 2 IO 6 D5 LC 2 V9 2 IO L6N D4 IC 2 V8 2 IO L7P 3 LC 2 U12 2 IO L7N D2 IC 2 V11 2 IO L8P D1 LC 2 V10 2 IO L8N D0 LC 2 U9 3 IO_L1P_GC_CC_LC_3 B12 3 IO LIN GC CC IC 3 A11 3 IO L2P GC VRN LC 3 A10 3 IO L2N GC VRP LC 3 B9 3 IO L3P GC IC 3 C11 3 IO_L3N_GC_LC_3 B11 3 IO L4P GC IC 3 10 8 IO_L4N_GC_VREF_LC_3 C10 3 IO_L5P_GC_LC_3 B13 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 21 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 22 XILINX Table 2 1 SF363 Package LX15 LX25 and FX12 Devices Continued Bank Pin Description Pin Number in LX1 a ies 3 IO_L5N_GC_LC_3 A13 3 IO LoP GC LC 3 A8 3 IO_L6N_GC_LC_3 B8 3 IO L7P GC LC 3 B14 3 IO L7N GC LC 3 A14 3 IO L8P GC LC 3 A7 3 IO L8N GC LC 3 B7 4 IO GC LC 4 W13 4 IO GC LC 4 W12 4 IO L2P GC LC 4 Y5 4 IO I2N GC IC 4 W5 4 IO L3P GC LC 4 Y12 4 IO L3N GC IC 4 Y11 4 I
250. n input a Low level on DONE can be configured to delay the start up sequence In SelectMAP mode BUSY controls the rate at which configuration data is DOUT BUSY 0 in u T In bit serial modes DOUT gives preamble and configuration data to down stream devices in a daisy chain HSWAPEN Input Enable I O pull ups during configuration When Low this pin indicates that the configuration memory is being INIT B 0 Bidirectional cleared When held Low the start of configuration is delayed During open drain configuration a Low on this output indicates that a configuration data error has occurred MO 0 M1_0 M2_0 Input Configuration mode selection PROG B 0 Input Active Low asynchronous reset to configuration logic This pin has a permanent weak pull up resistor Active Low power down pin unsupported Driving this pin Low can PWRDWN B 0 Input adversely affect device operation and configuration PWRDWN B is internally unsupported pulled High which is its default state It does not require an external pull up Do not connect this pin to GND leave it floating or pull it up to Vcc RDWR B 0 Input In Select MAP mode this is the active low Write Enable signal TCK 0 Input Boundary Scan Clock TDI 0 Input Boundary Scan Data Input TDO 0 Output Boundary Scan Data Output Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 15 UG075 v3 3 September 19 2008 Chapter 1 Packaging
251. nality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB UG075_04c_050108 Figure 3 7 FF672 Flip Chip Fine Pitch BGA Pinout Diagram FX20 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 249 Chapter 3 Pinout Diagrams FF672 Package Pinout Diagram FX40 FF672 XC4VFX40 Top View XILINX
252. nd LX25 Devices Continued Bank Pin Description Pin Number eee 8 IO L27N 8 AF9 8 IO L28P 8 W10 8 IO L28N VREF 8 Y10 8 IO L29P 8 AA10 8 IO L29N 8 AB10 8 IO_L30P_8 AE11 8 IO L30N 8 AF10 8 IO L31P 8 AE12 8 IO L31N 8 AF12 8 IO L32P 8 ACH 8 IO L32N 8 AD11 8 IO L17P 8 AC6 8 IO L17N 8 AB6 8 IO L18P 8 AE6 8 IO L18N 8 AD6 8 IO L19P 8 AB7 8 IO L19N 8 AA7 8 IO L20P 8 W9 8 IO L20N VREF 8 V8 8 IO L21P 8 AC8 8 IO_L21N_8 AC7 8 IO L22P 8 AF7 8 IO L22N 8 AE7 8 IO L23P VRN 8 AB9 8 IO L23N VRP 8 AA9 8 IO L24P CC LC 8 AC9 8 IO L24N CC LC 8 ADS 8 IO L1P 8 ABI 8 IO LIN 8 AA2 8 IO L2P 8 AB2 8 IO 8 AA3 8 IO L3P 8 AC2 8 IO L3N 8 ACI 8 IO 8 V7 8 IO VREF 8 U7 8 IO_L5P_8 AA4 8 IO_L5N_8 Y5 78 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee ee 8 IO_L6P_8 Y6 8 IO_L6N_8 AA5 8 IO L7P 8 ABA 8 IO L7N 8 AC3 8 IO L8P CC LC 8 8 IO_L8N_CC_LC 8 AD1 8 IO_L9P_CC_LC_8 AF3 8 IO Lo9N CC IC 8 AF4 8 IO L10P 8 AB5 8 IO L10N 8 ACA 8 IO L11P 8 AD3 8 IO LI1N 8 AE2 8 IO L12P 8 U9 8 IO L12N VREF 8 T8 8 IO L13P 8 AE3 8 IO L13N 8 AF2 8 IO L14P 8 AD5 8 IO 8 AD4
253. nd at various air speeds in LFM junction to case and junction to board data based on standard JEDEC four layer measurements Compact thermal models for these products are available on the Xilinx support download center at http www xilinx com support download index htm Table 5 1 Thermal Resistance Data Package Device Package Body Size uc 0B SUA E LX and SX Devices SF363 LX15 17 0 0 5 5 6 20 8 14 7 12 9 12 0 LX25 17 0 0 3 4 9 19 0 13 5 11 8 11 0 FF668 LX15 27 0 0 6 44 142 9 3 7 8 74 LX25 27 0 0 4 4 0 134 87 7 3 6 7 LX40 27 0 0 3 3 6 13 0 8 5 74 6 5 LX60 27 0 0 2 34 124 8 1 6 8 6 2 SX25 27 0 0 4 3 9 134 87 7 3 6 7 SX35 27 0 0 2 3 6 12 7 8 3 7 0 64 FF676 LX15 27 0 0 6 44 142 9 3 7 8 74 LX25 27 0 0 4 4 0 13 4 8 7 7 3 6 7 FF1148 LX40 35 0 0 3 2 8 11 0 6 7 5 5 4 9 LX60 35 0 0 2 2 6 10 6 64 5 3 4 8 LX80 35 0 0 2 24 10 4 6 3 5 1 4 6 LX100 35 0 0 1 22 10 1 6 1 5 0 4 5 LX160 35 0 0 1 24 9 7 5 9 4 8 43 SX55 35 0 0 2 24 10 3 6 3 5 1 4 6 FF1513 LX100 40 0 0 1 2 3 9 7 5 8 4 7 42 LX160 40 0 0 1 22 9 3 5 6 4 5 4 0 LX200 40 0 0 1 2 0 9 1 5 5 44 4 0 FX Devices SF363 FX12 17 0 0 5 5 7 20 8 14 7 12 9 12 0 FF668 FX12 27 0 0 6 44 142 9 3 7 8 74 FF672 FX20 27 0 0 4 3 8 13 5 87 74 6 8 FX40 27 0 0 2 3 3 12 6 82 6 9 6 3 FX60 27 0 0 1 34 12 0 727 6 5 5 9 FF1152 FX40 35 0 0 2 2 6 10 7 6 5 5 3 4 8 FX60 35 0 0 2 2 5 10 2 6
254. ne Pitch BGA Package Specifications 1 00 mm pitch page 275 e FF1513 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch page 276 e FF1517 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch page 277 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 269 UG075 v3 3 September 19 2008 Chapter 4 Mechanical Drawings XILINX SF363 Flip Chip Fine Pitch BGA Package Specifications 0 80 mm pitch BOTTOM VIEW TOP VIEW Al BALL PAD CORNER 4x e ooo Wih 7 8 re D 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 5 3 1 A PIN 1 LD i 3 C 7 ES D G x J 0000000 El E L T
255. ng and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 275 Chapter 4 Mechanical Drawings XILINX FF1513 Flip Chip Fine Pitch BGA Package Specifications 1 00 mm pitch 38g 776359497 Mog 72S O
256. ng up to 10 20 watts in the bigger packages The more efficient external heat sinks tend to be tall and heavy To help protect component joints from heat sink induced stress cracks the use of spring loaded pins or clips that transfer the mounting stress to a circuit board is advisable whenever a bulky heat sink is considered The diagonals of some of these heat sinks may be designed with extensions to allow direct connection to the board As stated earlier the flip chip BGA packages offered for Virtex 4 devices are thermally enhanced BGAs with the die facing down These packages have an exposed metal heat sink at the top These high end thermal packages lend themselves to the application of efficient external heat sinks passive or active for further heat removal efficiency Again precautions must be taken to prevent component damage when a www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Support for Compact Thermal Models CTM bulky heat sink is attached The thermal interface resistance needs to be controlled to take full advantage of these packages e An active heat sink may include a simple heat sink incorporating a mini fan or even a Peltier Thermoelectric Cooler TEC with a fan to carry away any dissipated heat When considering the use of a TEC for heat management consultation with experts in using the device is important because these devices can be reversed and cause
257. nk Pin Description Pin Number N A GND V31 N A GND AH31 N A GND AV31 N A GND A32 N A GND L32 N A GND AA32 N A GND AL32 N A GND D33 N A GND P33 N A GND AD33 N A GND AP33 N A GND G34 N A GND U34 N A GND AG34 N A GND AU34 N A GND K35 N A GND Y35 N A GND AK35 N A GND C36 N A GND N36 N A GND AC36 N A GND AN36 N A GND F37 N A GND T37 N A GND AF37 N A GND AT37 N A GND A38 N A GND J38 N A GND W38 N A GND AJ38 N A GND AW38 N A GND B39 N A GND M39 N A GND AB39 N A GND AM39 N A GND AV39 N A VCCAUX H8 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 191 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A VCCAUX Y8 N A VCCAUX L9 N A VCCAUX AC9 N A VCCAUX P10 N A VCCAUX AF10 N A VCCAUX U11 N A VCCAUX AJ11 N A VCCAUX K12 N A VCCAUX Y12 N A VCCAUX AM12 N A VCCAUX J15 N A VCCAUX AL15 N A VCCAUX H18 N A VCCAUX AK18 N A VCCAUX AA19 N A VCCAUX AN19 N A VCCAUX G21 N A VCCAUX W21 N A VCCAUX K22 N A VCCAUX AM22 N A VCCAUX J25 N A VCCAUX AL25 N A VCCAUX H28 N A VCCAUX Y28 N A VCCAUX AK28 N A VCCAUX L29 N A VCCAUX AC29 N A VCCAUX P30 N A VCCAUX AF30 N A VCCAUX U31 N A VCCAUX AJ31 N A VCCAUX Y32 N A VCCAUX AM32 N A VCCINT R7 N A VCCI
258. oOLHooodomgOooooLrleeee1e 42 AB AC NMIOOOLIO0DOONOC OCLIGOOONOo eeeLuc AD e e EOOOONOOOOLI ee opoONOOOOLIee AD AE VIAM DIMITSEN TTG OD ISTIS SSIGISITT CGU AE AF 9 9oo08oomMxxiMCOOCSI ISIIMIXIX EI o C AF 1 2 3 4 5 6 7 8 9 1011121914 4516 4718 192054 2259245526 User I O Pins Dedicated Pins Other Pins O 1 LXXY s Z ADC 5 SM GND E AVCCAUXRXA RXNPADA Multi Function Pins C CCLK TCK GNDA 3 AVCCAUXRXB 4 RXPPADA amp ADC1 ADC7 B CS B I TDI R RSVD LJ AVCCAUXTX TXPPADA DO D31 D IN O TDO VBATT m AVCCAUXMGT TXNPADA cc D DONE M TMS 4 VCCAUX Vi VTRXA RXNPADB NGC Al DOUT BUSY J TDP W VTTXA 4 RXPPADB decus H HSWAPEN L TDN VCCO lt VTRXB 4 TXPPADB SM1 SM7 Y INIT n NO CONNECT 5 VTTXB TXNPADB VREF 2 1 0 M2 M1 MO X MGTCLK CQ P PROG B Gl MGTVREF U RDWR B Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use UGO075 04b 050108 Figure 3 8 FF672 Flip Chip Fine Pitch BGA Pinout Diagram FX40 250 www Xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Package Pinout Diagram FX60 FF672 Package Pinout Diagram FX60 User I O Pins O IO LXXY ADC1 ADC7 DO D31 CC N_GC P_GC SM1 SM7 VREF V
259. oOoOOLec oopoomOoOOOeLDooooNOOBM AE 9IADOOORQOOOLIOOOONOCOCLIOee 910000L I AF iBMOSOOOOLI OG OOONOCOC 9 oNeeool JOOOIE e Ac omBmOoOOneoooNOoOdmnoLeceeemmeooereoooSOMIV AH oBLIJOOOOROOOOLIGOOQOR GOOGOLIOeS 10000 N9 EaAMoOoSooOooDooooNOeeQrOooooNOOPOOODOOMOC eomooOoOLIOOOONSJOO IISISIOOOORJOO e 6 OOOORBI IO AL e BIOLIOOOONOOOOLIISISIS OOOOLIee O0O0S000BIO am EHBTEGNENB ALULNE ETUEZJTE NUABEEBCE TEN AN BXXH V3O o ortooHoosusooecovesaMxxNHoolN ap 1 2 3 4 5 6 7 8 9 104 12441 415104 718492054225424 26 28 93041324434 Notes 1 SM and ADC functionality in multi function user I O pins is reserved for future use 2 Dedicated SM and ADC pins are reserved for future use Dedicated Pins Other Pins S E AVCCAUXRXA RXNPADA C CCLK K TCK GNDA J AVCCAUXRXB 3 RXPPADA B CS B TDI R RSVD w N D IN O TDO VBATT m AVCCAUXMGT TXNPADA D DONE M TMS 4 VCCAUX V VTRXA RXNPADB A DOUT BUSY J TDP W VCCINT VTTXA RXPPADB H HSWAPEN L TDN VCCO lt VTRXB lt gt TXPPADB Y INIT n NO CONNECT 2 VTTXB TXNPADB 2 1 0 M2 M1 MO X MGTCLK P PROG B G MGTVREF PWRDWN B T
260. oooo loooooooo loooooooo o o o o o o o o loooooooo PIN 1 LD ve O000000000000000000000000000000 o o o o o o o o o o o o o o o o o o o o o o o Oi o Oo Oo Oo 0000006000000000 LAP L 32 00 A SEATING PLANE ccc C 11 32 00 gone HEAT 5 NK aaa C MILLIM
261. out Specification www xilinx com 151 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables 152 XILINX Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber FX60 Devices FXA0 Devices N A GND F22 N A GND T22 N A GND V22 N A GND Y22 N A GND AF22 N A GND J23 N A GND R23 N A GND U23 N A GND W23 N A GND AA23 N A GND AJ23 N A GND M24 N A GND T24 N A GND AB24 N A GND AM24 N A GND E25 N A GND R25 N A GND U25 N A GND AE25 N A GND H26 N A GND V26 N A GND AH26 N A GND L27 N A GND AA27 N A GND AL27 N A GND D28 N A GND P28 N A GND AD28 N A GND G29 N A GND U29 N A GND AG29 N A GND K30 N A GND Y30 N A GND AK30 N A GND C31 N A GND N31 N A GND AC31 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1152 Flip Chip Fine Pitch BGA Package Table 2 6 FF1152 Package FX40 FX60 and FX100 Devices Continued Bank Pin Description umber FX60 Devices FXA0 Devices N A GND F32 N A GND T32 N A GND AF32 N A VCCAUX AE8 N A VCCAUX V9 N A VCCAUX AB10 N A VCCAUX U11 N A VCCAUX N13 N A VCCAUX T14 N A VCCAUX M
262. ption Pin Number No Connects in FX20 Devices 5 VCCO 5 E24 6 VCCO 6 E4 6 VCCO 6 H5 6 VCCO 6 A6 6 VCCO 6 L6 6 VCCO 6 D7 6 VCCO 6 G8 6 VCCO 6 K9 6 VCCO 6 C10 6 VCCO 6 Fil 7 VCCO_7 AA16 7 VCCO 7 AD17 7 VCCO 7 U18 7 VCCO 7 Y19 7 VCCO 7 AC20 7 VCCO 7 T21 7 VCCO_7 W22 7 VCCO_7 AB23 7 VCCO_7 R24 8 VCCO_8 M3 8 VCCO_8 AB3 8 VCCO 8 R4 8 VCCO_8 V5 8 VCCO_8 AA6 8 VCCO_8 AD7 8 VCCO_8 U8 8 VCCO_8 Y9 8 VCCO 8 AC10 9 VCCO_9 P17 NC 9 VCCO_9 N20 NC 10 VCCO_10 P7 NC 10 VCCO_10 N10 NC N A AVCCAUXRXA_102 B20 N A RXPPADA 102 A19 N A VTRXA 102 A21 N A RXNPADA 102 A20 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF672 Flip Chip Fine Pitch BGA Package Table 2 3 FF672 Package FX60 FX40 and FX20 Devices Continued Bank Pin Description Pin Number No Connects in FX20 Devices N A AVCCAUXMGT 102 C25 N A AVCCAUXTX 102 B23 N A 102 B22 N A 102 A22 N A 102 A23 N A VTTXB 102 B24 N A TXPPADB 102 A24 N A TXNPADB 102 A25 N A RXPPADB 102 C26 N A VTRXB 102 B26 N A AVCCAUXRXB 102 D25 N A RXNPADB 102 D26 N A MGICLK P 102 F26 N A MGTCLK 102 G26 N A AVCCAUXRXA_103 K25 NC N A RXPPADA 103 126 NC N A VTRXA_103 L26 NC N A RXNPADA_103 K26 NC N A AVCCAUXTX_103 P25 NC N A VTTXA_103 M25 NC N A TXPPADA_103 M26
263. r 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number 3 IO LIP GC CC IC 3 P20 3 IO LIN GC CC IC 3 N20 3 IO L2P GC VRN IC 3 J19 3 IO I2N GC VRP IC 3 K19 3 IO L3P GC IC 3 N22 3 IO L3N GC LC 3 M22 3 IO L4P GC IC 3 121 3 IO LAN GC VREF IC 3 120 3 IO_L5P_GC_LC_3 M21 3 IO_L5N_GC_LC_3 M20 3 IO_L6P_GC_LC_3 L20 3 IO_L6N_GC_LC_3 L19 3 IO_L7P_GC_LC_3 P22 3 IO_L7N_GC_LC_3 P21 3 IO_L8P_GC_LC_3 L21 3 IO L8N GC LC 3 K21 4 IO L1P GC LC 4 AH20 4 IO LIN GC IC 4 AH19 4 IO 12 GC LC 4 AF19 4 IO GC IC 4 AF18 4 IO L3P GC IC 4 AJ21 4 IO_L3N_GC_LC_4 AJ20 4 IO_L4P_GC_LC 4 AG20 4 IO LAN GC VREF IC 4 AF20 4 IO L5P GC IC 4 AL20 4 IO L5N GC LC 4 AL19 4 IO_L6P_GC_LC 4 AH18 4 IO_L6N_GC_LC_4 AG18 4 IO L7P GC VRN LC 4 AL21 4 IO L7N GC VRP IC 4 AK21 4 IO L8P GC CC LIC 4 AK19 4 IO LN GC CC IC 4 AJ19 5 IO_L1P_ADC7_5 B26 5 IO LIN ADC7 5 A26 5 IO 2 ADC6 5 E28 5 IO L2N ADC6 5 F28 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 161 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued
264. r I Os after configuration unless the SelectMAP port is retained gu P These lower capacitance clock pins connect to Clock Capable I Os These cc Input Output pins do not support LVDS outputs and they become regular user I Os when not needed for clocks These lower capacitance clock pins connect to Global Clock Buffers These 2 pins do not support LVDS outputs and they become regular user I Os ee when not needed for clocks For single ended clock inputs use P side pins only 14 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX Pin Definitions Table 1 3 Virtex 4 FPGA Pin Definitions Continued Pin Name Direction Description LC Input Output These lower capacitance pins do not support LVDS outputs svn T Vus Menu ee I VN mo VRP Input Output This pin is for the DCI voltage reference resistor of P transistor per bank to be pulled Low with reference resistor Dedicated Configuration Pins Configuration clock Output and input in Master mode or Input in Slave CCLK 0 Input Output Tod CS_B_0 Input In SelectMAP mode this is the active low Chip Select signal D IN 0 Input In bit serial modes D IN is the single data input DONE is a bidirectional signal with an optional internal pull up resistor As an output this pin indicates completion of the configuration process DUNE input Our As a
265. ry latest Virtex 4 FPGA pinout information visit www xilinx com and check for any updates to this document ASCII package pinout files are also available for download from the Xilinx website Table 2 4 FF676 Package LX15 and LX25 Devices Bank Pin Description Pin Number 0 HSWAPEN 0 K16 0 CCLK 0 M14 0 D IN 0 L13 0 PROG B 0 K17 0 INIT B 0 K15 0 CSBO0 M12 0 DONE 0 L15 0 RDWR B 0 R11 0 L17 0 M2_0 M16 0 PWRDWN B 0 U12 0 TMS 0 T10 0 MO 0 P14 0 TDO 0 R13 0 TCK 0 U10 0 0 R15 0 DOUT_BUSY_0 T14 0 TDI 0 U11 0 0 F12 0 TDP 0 E12 1 IO D31 IC 1 J14 1 IO L1N D30 LC 1 H14 1 IO 12 D29 IC 1 JA3 1 IO D28 ILC 1 H13 1 IO 13 D27 IC 1 J16 1 IO L3N D26 LC 1 J15 1 IO D25 IC 1 K13 1 IO LAN D24 VREF IC 1 K12 1 IO L5P D23 IC 1 G15 70 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee ee 1 IO_L5N_D22_LC_1 G14 1 IO_L6P_D21_LC_1 H12 1 IO_L6N_D20_LC_1 H11 1 IO_L7P_D19_LC_1 H16 1 IO_L7N_D18_LC_1 G16 1 IO_L8P_D17_CC_LC_1 J11 1 IO_L8N_D16_CC_LC_1 K11
266. s XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number 7 IO L3N 7 AU36 7 IO 4 7 AU25 7 IO_L4N_VREF_7 AT25 7 IO L5P 7 AP36 7 IO L5N 7 AR36 7 IO L6P 7 AP25 7 IO L6N 7 AP24 7 1 17 7 AP35 7 IO L7N 7 AP34 7 IO L8P CC LC 7 AU26 7 IO L8N CC LC 7 26 7 IO L9P CC LC 7 AT35 7 IO L9N CC LC 7 AU35 7 IO_L10P_7 AR26 7 IO L10N 7 AP26 7 IO_L11P_7 AR34 7 IO_L11N_7 AT34 7 IO L12P 7 AR27 7 IO L12N VREF 7 AP27 7 IO L13P 7 AU33 7 IO L13N 7 AU32 7 IO L14P 7 AM27 7 IO_L14N_7 AM26 7 IO L15P 7 AR33 7 IO L15N 7 AT33 7 IO L16P 7 AK27 7 IO L16N 7 AL26 8 IO L25P CC LC 8 AL13 8 IO L25N CC LC 8 AM13 8 IO_L26P_8 AP11 8 IO_L26N_8 AR11 8 IO L27P 8 AR14 8 IO L27N 8 AR13 8 IO L28P 8 AL11 8 IO 2 8 AM11 206 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number IO L29P 8 AT14 8 IO_L29N_8 AT13 8 IO_L30P_8 AP12 8 IO_L30N_8 AR12 8 IO L31P 8 AU13 8 IO L31N 8 AU12 8 IO L32P 8 AK11 8 IO L32N 8 AJA1 8 IO L17P 8 A
267. sceivers 24 Differential I O Pairs 384 Pin Definitions Table 1 3 provides a description of each pin type listed in Virtex 4 FPGA pinout tables The f suffix appended to some pin descriptions indicates the bank in which that pin resides Pins that do not have this suffix appended are not associated with any particular bank For a description of RocketIO transceiver pins see the Virtex 4 RocketIO Multi Gigabit Transceiver User Guide UGO76 Table 1 3 Virtex 4 FPGA Pin Definitions Pin Name Direction Description User I O Pins All user I O pins are capable of differential signalling and can implement LVDS LVDSEXT ULVDS BLVDS LVPECL or LDT pairs Each user I O is labeled IO LXXY 7 where IO LXXY Input Output IO indicates a user I O pin LXXY indicates a differential pair with XX a unique pair in the bank and Y P N for the positive negative sides of the differential pair Multi Function Pins IO LXXY ZZZ 8 Multi function pins are labelled IO LXXY ZZZ where ZZZ represents one or more of the functions described below For a given multi function pin ZZZ is one or more of the following ADC1 through ADC7 input pins are reserved for future use but can be aen used for I O or other designated functions In SelectMAP mode D0 through D31 are configuration data pins These pins Dn Input Output become use
268. t Specification UG075 v3 3 September 19 2008 XILINX FF676 Flip Chip Fine Pitch BGA Package Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number eee 9 IO L26N 9 U26 9 IO 1 27 9 W24 9 IO L27N 9 V24 9 IO L28P 9 U21 9 IO L28N VREF 9 T20 9 IO L29P 9 W25 9 IO L29N 9 W26 9 IO L30P 9 Y25 9 IO L30N 9 Y26 9 IO L31P 9 AB25 9 IO L31N 9 AA25 9 IO L32P 9 AC26 9 IO 22 9 AB26 10 IO L17P 10 R2 10 IO L17N 10 P3 10 IO_L18P_10 N4 10 IO L18N 10 P4 10 IO L19P 10 R1 10 IO L19N 10 P1 10 IO_L20P_10 P6 10 IO_L20N_VREF_10 P5 10 IO_L21P_10 T2 10 IO_L21N_10 R3 10 IO_L22P_10 U4 10 1 22 10 T3 10 IO L23P VRN 10 T4 10 IO L23N VRP 10 R5 10 IO L24P CC LC 10 U2 10 IO L24N CC IC 10 U1 10 IO L1P 10 D1 10 IO L1N 10 E1 10 IO L2P 10 H3 10 IO 10 J3 10 IO L3P 10 G2 10 IO L3N 10 G1 10 IO 4 10 K6 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com 81 UG075 v3 3 September 19 2008 Chapter 2 Pinout Tables XILINX Table 2 4 FF676 Package LX15 and LX25 Devices Continued Bank Pin Description Pin Number pean 10 IO_L4N_VREF_10 L7 10 IO L5P 10 H2 10 IO L5N 10 H1 10 IO_L6P_10 E2 10 IO L6N 10 F2 10 IO L7P 10 K5 10 IO L7N 10 L5 10 IO
269. t Tables XILINX Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A GND D13 N A GND K13 N A GND M13 N A GND P13 N A GND AD13 N A GND AF13 N A GND AK13 N A GND AP13 N A GND G14 N A GND L14 N A GND N14 N A GND U14 N A GND W14 N A GND AE14 N A GND AG14 N A GND AJ14 N A GND AU14 N A GND K15 N A GND M15 N A GND P15 N A GND V15 N A GND Y15 N A GND AD15 N A GND AF15 N A GND AK15 N A GND C16 N A GND N16 N A GND U16 N A GND W16 N A GND AC16 N A GND AE16 N A GND AN16 N A GND F17 N A GND T17 N A GND V17 N A GND AF17 N A GND AT17 N A GND J18 188 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1513 Flip Chip Fine Pitch BGA Package Table 2 7 FF1513 Package LX100 LX160 and LX200 Devices Continued Bank Pin Description Pin Number N A GND W18 N A GND AC18 N A GND AJ18 N A GND AW18 N A GND B19 N A GND M19 N A GND V19 N A GND AB19 N A GND AD19 N A GND AM19 N A GND E20 N A GND R20 N A GND AE20 N A GND AR20 N A GND H21 N A GND T21 N A GND V21 N A GND AB21 N A GND AH21 N A GND AV21 N A GND A22 N A GND L22 N A GN
270. the product is considered commercial grade Other variations for the 4th line 106 xxxx The xxxx indicates the SCD for the device An SCD is a special ordering code that is not always marked in the device top mark 4th Line 10CES The ES indicates an Engineering Sample 10CESn The n is a numeral n 1 2 3 The ESn indicates an Engineering Sample n for example ES1 ES2 ES3 and so on 10CESnL This device marking is only used for Virtex 4 FX engineering sample devices The L or indicates that only left MGTs are available and the R indicates that only the right 10CESnR MGTs are available when looking at the device from the bottom side up Notes 1 Some Virtex 4 LX and SX Step 1 devices do not have the 1 marked on the package top mark 2 FXStep 0 devices do not have the 0 marked on the package top mark 286 www xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008
271. urces reco idc et Kod br kd ed dba kar 8 Typographical Conventions sss 9 Chapter 1 Packaging Overview Fer ETT 11 Latrodoctiob cei REERR Lek vn PCR ES EO rd exer v rex ies ee dicia a i 11 Device Package Combinations and 0 12 Pint Definitions cis ce LARGE RR 14 Chapter 2 Pinout Tables d Ero e Pent PER PP 19 SF363 Flip Chip Fine Pitch BGA 0 00 20 FF668 Flip Chip Fine Pitch BGA turus 31 FF672 Flip Chip 6 51 FF676 Flip Chip 6 70 FF1148 Flip Chip 6 89 FF1152 Flip Chip Fine Pitch BGA 123 FF1513 Flip Chip Fine Pitch BGA Package 0 0 00s e eee 156 FF1517 Flip Chip 6 197 Chapter 3 Pinout Diagrams ve HED HERES EER GeV 241 SF363 Package Pinout Diagram LX15 and 2 243 SF363 Package Pinout Diagram LX25 suse 244 SF363 Color Coded SelectIO and Bank Infor
272. ww xilinx com Virtex 4 FPGA Packaging and Pinout Specification UG075 v3 3 September 19 2008 XILINX FF1517 Flip Chip Fine Pitch BGA Package Table 2 8 FF1517 Package FX140 and FX100 Devices Continued Bank Pin Description Pin Number GND N28 N A GND R28 N A GND W28 N A GND AJ28 N A GND M29 N A GND P29 N A GND AB29 N A GND AM29 N A GND E30 N A GND R30 N A GND AE30 N A GND AR30 N A GND H31 N A GND V31 N A GND AH31 N A GND L32 N A GND AA32 N A GND AL32 N A GND D33 N A GND P33 N A GND AD33 N A GND AP33 N A GND G34 N A GND U34 N A GND AG34 N A GND AU34 N A GND K35 N A GND Y35 N A GND AK35 N A GND C36 N A GND N36 N A GND AC36 N A GND AN36 N A GND F37 N A GND T37 N A GND AF37 N A GND AT37 Virtex 4 FPGA Packaging and Pinout Specification www xilinx com UG075 v3 3 September 19 2008 235 Chapter 2 Pinout Tables 236 XILINX Table 2 8 FF1517 Package FX140 and FX100 Devices Continued No Connects in Bank Pin Description Pin Number FX100 Devices N A VCCAUX 17 VCCAUX U7 N A VCCAUX M8 N A VCCAUX AB8 N A VCCAUX R9 N A VCCAUX AE9 N A VCCAUX V10 N A VCCAUX K12 N A VCCAUX AM12 N A VCCAUX J15 N A VCCAUX AL15 N A VCC
273. xilinx com FF668 Flip Chip Fine Pitch BGA Package Table 2 2 FF668 Package LX15 LX40 LX60 SX25 SX35 and FX12 Devices Continued No Connects in Bank Pin Description Pin Number LX15 SX25 and FX12 Devices 9 IO L32P 9 V26 9 IO L32N 9 V25 10 IO L17P 10 N7 10 IO L17N 10 M7 10 IO L18P 10 P5 10 IO L18N 10 P4 10 IO L19P 10 P8 10 IO L19N 10 N8 10 IO L20P 10 R4 10 IO_L20N_VREF_10 R3 10 IO L21P 10 P7 10 IO L21N 10 P6 10 IO L22P 10 R2 10 IO L22N 10 R1 10 IO L23P VRN 10 R6 10 IO L23N VRP 10 R5 10 IO L24P CC LC 10 U1 10 IO L24N CC IC 10 T1 10 IO L1P 10 J7 10 IO LIN 10 J6 10 IO L2P 10 15 10 IO 10 J4 10 IO L3P 10 K7 10 IO L3N 10 K6 10 IO L4P 10 J2 10 IO VREF 10 J1 10 IO L5P 10 L7 10 IO L5N 10 L6 10 IO L6P 10 K5 10 IO L6N 10 K4 10 IO L7P 10 K3 10 IO L7N 10 K2 10 IO L8P CC LC 10 L4 10 IO L8N CC IC 10 L3 10 IO L9P CC LC 10 M8 UG075 v3 3 September 19 2008 43 Chapter 2 Pinout Tables lt XILINX Table 2 2 FF668 Package LX15 LX40 LX60 SX25 SX35 and FX12 Devices Continued Bank Pin Description Pin Number LX15 eve cade 10 IO L9N CC IC 10 L8 10 IO L10P 10 L1 10 IO L10N 10 K1 10 IO_L11P_10 M2 10 IO L11N 10 M1 10 IO L12P 10 M

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