SYSTEMY WBUDOWANE - Uniwersytet Jana Kochanowskiego w
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1. ABLE INTERRUPT UT s0 00 UE si 03 S0 sl PUT s0 00 e e L critical timing e P main ENABLE INTERRUPT ETURN ENABLE Dr in Ignacy Pardyka Inf UJK ADDRESS JUMP isr Rok akad 2011 2012 38 96 The interrupt input is not recognized until the INTERRUPT ENABLE flag is set In timing critical functions or areas where absolute predictability is required temporarily disable the interrupt Re enable the interrupt input when the time critical function is complete Always return from a sub routine call with the RETURN instruction The interrupt input is automatically disabled Use the RETURNI instruction to return from an interrupt The interrupt vector is always located at the most significant memory location where all the address bits are ones Jump to the interrupt service routine UG129 c4 02 051404 Figure 4 2 Example Interrupt Flow Systemy wbudowane Rok akad 2011 2012 40 96 Interrupts Interrupts Interrupt Timing Diagram Begin executing interrupt service routine 5 clock cycles ax F4 FA F4 EA F4 Fn H Interrupt recognized PREEMPTED INSTRUCTION ADDRESS 9 0 INTERRUPT INTERRUPT ACK i I I I Call to interrupt Jump to interrupt I vector assert service routine ADD sn sl instruction INTERRUPT ACK pre empted PC saved to stack Flags preserved Interrupt disabled2. Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 53 96 Output Destinations Output Ports Declaration Figure 6 8 Use CONSTANT Directives to Declare Output Port Addresses Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 55 96 Input and Output Ports Output Operations Output Destinations Address Decoding PORT B 1 i i NI rn PicoBlaze Microcontrolle K EN IN PORT 7 0 OUT PORT 7 0 gt PORT ID 7 0 READ STROBE WRITE STROBE UG129 c6 07 052004 Figure 6 7 Simple Address Decoding for Designs with Few Output Destinations Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 54 96 Instruction Storage Configurations Instruction Storage Configurations Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 56 96 Instruction Storage Configurations Instruction Store Standard Configuration KCPSM3 IN PORT 7 0 OUT PORT 7 0 PORT ID 7 0 RESET READ STROBE WRITE STROBE INTERRUPT ACK Instruction ROM INTERRUPT Block RAM INSTRUCTION 17 0 ADDRESSY 9 0 10 UG129 c7 01 051504 Figure 7 1 Standard Implementation using a Single 1Kx18 Block RAM as the Instruction Store Systemy wbudowane Dr in Ignacy Pardyka Inf UJK Two Microcontrollers Sharing a Common Program Memory KCPSM3 Block RAM KCPSM3 18 DOPB 1 0 amo S INSTRUC
3. PicoBlaze Programming Using PicoBlaze Instructions Clearing a Register and Setting the ZERO Flag Figure 3 4 Clearing a Register and Setting the ZERO Flag Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 69 96 PicoBlaze Programming Using PicoBlaze Instructions Set Bit Figure 3 6 16 Setting a Bit Location Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 71 96 PicoBlaze Programming Using PicoBlaze Instructions Clearing a Register without Modifying the ZERO Flag Figure 3 5 Clearing a Register without Modifying the ZERO Flag Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 70 96 PicoBlaze Programming Using PicoBlaze Instructions Clear Bit Figure 3 7 Clearing a Bit Location Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 72 96 PicoBlaze Programming PicoBlaze Programming Using PicoBlaze Instructions Using PicoBlaze Instructions 16 Bit Addition 16 Bit Subtraction Figure 3 8 16 Bit Addition Using ADD and ADDCY Instructions Figure 3 9 16 Bit Subtraction Using SUB and SUBCY Instructions Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 73 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 74 96 Using PicoBlaze Instructions Using PicoBlaze Instructions Destructive Negate Non destructive Negate F
4. CALL RETURN Stack Preserved ZERO ZERO Flag Flag ge Preserved CARRY CARRY Flag Flag 0 INTERRUPT ENABLE UG129_c4_03_051404 Figure 4 3 Interrupt Timing Diagram Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 41 96 Address Modes Direct Addressing Figure 5 1 Directly Addressing Scratchpad RAM Locations Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 43 96 Scratchpad RAM Scratchpad RAM Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Address Modes Indirect Addressing Rok akad 2011 2012 Figure 5 2 Indirect Addressing Initializes All of RAM with a Simple Subroutine Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 42 96 44 96 Scratchpad RAM FETCH Operation 64 Byte Scratchpad RAM DATA IN 7 0 DATA OUTT 7 0 Register sx FALSE t WRITE ENABLE Register sy or Literal kk ADDRESS 5 0 7 6 UG129 aC 11 051604 Figure C 5 FETCH Operation Examples FETCH sX sY Read scratchpad RAM location specified by the gt c mtemte 6 register S into register sx FETCH sX kk Read scratchpad RAM location specified by the immediate constant kk into register sX Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 45 96 Input and Output Ports Input and Output Ports Input Operations e Output Operations Dr in Igna
5. 0 RETURNI ENABLE Return from interrupt service routine PC TOS g RETI ENABLE Re enable interrupt ZERO Preserved ZERO CARRY sX 0 RL sX Rotate register sX left sX sX 6 0 sX 7 R CARRY sX 7 RR sX Rotate register sX right sX sX 0 sX 7 1 Dr in Ignacy Pardyka Inf UJK PicoBlaze Instruction Codes PicoBlaze Instruction Set Instructions Systemy wbudowane Rok akad 2011 2012 STORE sX sY Write register sX to scratchpad RAM RAM sY sX STORE sX sY location pointed to by register sY STORE sX ss Write register sX to scratchpad RAM RAM ss sX location ss SUB sX kk Subtract literal kk from register sX sX sX kk S g SUB sX sY Subtract register sY from register sX sX sX sY K SUBCY sX kk Subtract literal kk from register sX with sX sX kk CARRY S SUBC CARRY borrow SUBCY sX sY Subtract register sY from register sX with sX sX sY CARRY SUBC CARRY borrow Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 85 96 87 96 PicoBlaze Instruction Set Instructions SLO sX Shift register sX left zero fill sX sX 6 0 0 CARRY sX 7 SL1 sX Shift register sX left one fill sX sX 6 0 1 0 CARRY sX 7 SLA sX Shift register sX left through all bits sX sX 6 0 CA
6. Input If the INTERRUPT ENABLE flag is set by the application code generate an INTERRUPT Event by asserting this input High for at least two CLK cycles If the INTERRUPT ENABLE flag is cleared this input is ignored RESET Input Reset Input To reset the PicoBlaze microcontroller and to generate a RESET Event assert this input High for at least one CLK cycle A Reset Event is automatically generated immediately following FPGA configuration CLK Input Clock Input The frequency may range from DC to the maximum operating frequency reported by the Xilinx ISE development software All PicoBlaze synchronous elements are clocked from the rising clock edge There are no clock duty cycle requirements beyond the minimum pulse width requirements of the FPGA OUT PORT 7 0 Output Output Data Port Output data appears on this port for two CLK cycles during an OUTPUT instruction Capture output data within the FPGA at the rising CLK edge when WRITE STROBE is High PORT ID 7 0 Output Port Address TheI O port address appears on this port for two CLK cycles during an INPUT or OUTPUT instruction Systemy wbudowane Rok akad 2011 2012 Dr in Ignacy Pardyka Inf UJK 5 96 7 96 PicoBlaze Interface PicoBlaze Interface Connections PicoBlaze Microcontroller IN PORT 7 0 INTERRUPT OUT PORT 7 0 PORT ID 7 0 HEAD STROBE WHITE STROBE INTERRUPT ACK UG129 c2 01 052004 Figure 2 1 PicoBlaze I
7. Instruction Codes Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0 ADD sX kk 0 1 1 0 0 0 ADD sX sY 0 1 1 0 0 1 0 0 0 0 ADDCY sX kk 0 1 1 0 1 0 ADDCY sX sY 0 1 1 0 1 1 0 O 0 0 AND sX kk 0 0 1 0 1 0 AND sX sY 0 0 1 0 1 1 0 O 0 0 CALL 1 1 0 0 0 0 0 0 CALL C 1 1 0 0 0 1 1 0 CALL NC 1 1 0 0 0 1 1 1 CALL NZ 1 1 0 0 0 1 0 1 CALL Z 1 1 0 0 0 1 0 O Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 PicoBlaze Instructions Instruction Codes Table D 1 PicoBlaze Instruction Codes Cont d Instruction 17 16 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 LOAD sX kk 0 0 0 0 0 0 LOAD sX sY 0 0 0 0140 1 0 0 00 OR sX kk 0 0 1 1 0 0 OR sX sY 0 O 1 1 0 1 0 0 0 0 OUTPUT sX sY 1 0 1 1 0 1 0 0 0 0 OUTPUT sX pp 16 10 05 RETURN 1 0 1 0 1 0 0 0 0 0 0 04 0 4 0 0 0 0 0 RETURN C 1 0 1 0 1 1 1 0 0 0 0 00 0 010 0 0 RETURN NC 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 RETURN NZ 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 00 RETURN Z 1 0 1 0 1 1 0 0 0 0 0 04 0 4 0 0 0 0 0 RETURNI DISABLE 1 1 1 0 0 0 0 0 0 0 0 04 0 4 0 0 0 00 RETURNI ENABLE 1 1 1 0 0 0 0 0 0 0 0 04 0 4 0 0 0 0 1 Rok akad 2011 2012 90 96 92 96 PicoBlaze Instructions Instruction Co
8. RETURNI must specify if further interrupt is to be enabled or disabled 17 14 enen easte s 4 1 o o o oTo o o o o o o oe o 17 14 RETURNI isaste 5 1 s oTo o o To To o o o oToTo o e o o onmi Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 16 96 Instruction Set PicoBlaze Instruction Set ENABLE DISABLE INTERRUPT These instructions are used to set and reset the INT ENABLE flag Before using ENABLE INTERRUPT a suitable interrupt routine must be associated with the interrupt address vector located at address 3FF Interrupts should never be enabled whilst performing an interrupt service routine ENABLE INT ENABLE Lg 0 DISABLE Interrupts are masked when the INT_ENABLE flag is low This is the default state of the flag following device configuration or a KCPSMS reset The INT ENABLE is also reset during an active interrupt 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE INTERRUPT 1 1 1 1 o o o jo jo o o jo jojo o jo jo f 17 16 15 14 ide 12 id 1 OO 6 y G S59 4 3 2 1 0 DISABLE INTERRUPT 1 1 1 1 0 ojo o o o o jo jojo o jo jo 0 es Ze Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 17 96 Instruction Set PicoBlaze Instruction Set AND The AND instruction performs a bit wise logical AND operation between two operands For example 00001111 AND 00110011 will produce the result 00000011 The first operand is
9. constant port identifier using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 1 10 9 8 7 6 5 4 3 2 141 0 INPUTsXPP 0 0 0 1 o o x x x x p p p p p p p p CC SX Constant PORT ID dv dG ide dW dS 2 dw du 9 v G 9 4 9 2 1 0 iNPUTsX Y ojojo 1 o t x x x x v v v v o ojojo ZZ ZZ sX sY d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 33 96 Instruction Set PicoBlaze KCPSM3 RESET KCPSM 3 contains an internal reset control circuit to ensure the correct start up of KCPSM3 following device configuration or global reset GSR This reset can also be activated within your design reset The KCPSM3 reset is sampled synchronous to the clock and used to form a controlled internal reset signal which is distributed locally as required A small filter circuit see right ensures that the release of the internal reset is clean and controlled internal reset Release of Reset after configuration CLK _ GSR 1 internal reset ADDRESS 9 0 000 004 INSTRUCTION 17 0 inst000 Application of user reset input The reset input can be tied to logic 0 if not required and the filter will still be used to ensure correct power up sequence EE Teese Loi Lor Loi Loi LI Lori Lo L EISE internal reset ZA ADDRESS 9 0 INSTRUCTION 17 0 Ze Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok
10. http www xilinx com ipcenter processor central picoblaze Mediatronix pBlazIDE Integrated Development Environment for PicoBlaze http www mediatronix com pBlazeIDE htm Xilinx System Generator User Guide Designing PicoBlaze Microcontroller Applications http www xilinx com support sw manuals sysgen ug pdf MicroBlaze 32 bit Soft Processor Core http www dilinx com microblaze UG331 Spartan 3 Generation FPGA User Guide Chapter 8 Using Dedicated Multiplexers http www xilinx com support documentation user_guides ug331 pdf XST User Guide Chapter 9 Mixed Language Support http toolbox xilinx com docsan xilinx10 books docs xst xst pdf Systemy wbudowane Rok akad 2011 2012 96 96
11. of result are zero Reset in all other cases SLA sX ome e ZERO Set if all bits of result are zero Reset in all other cases ZERO Set if all bits of result are zero Reset in all other cases Each instruction must specify the register as s followed by a hexadecimal digit The assembler supports register naming to simplify the process Bit2 Bit1 BitO Instruction 129916 9159514 013232 41 OOG G 01236 775 93 29120 1 1 0 SLO sX 1jojojo ojo x x x x ojojofofo 3 3 3 1 0 0 SLX sX ee 0 0 0 SLA sX sX 0 1 0 RL sX o e i Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 29 96 Instruction Set PicoBlaze Instruction Set FETCH The FETCH instruction enables data held in the 64 byte internal scratch pad memory to be transferred any of the internal registers The storage address in the range 00 to 3F can be defined by a constant value or indirectly as the contents of any other register The Flags are not affected by this operation Scratch pad Scratch pad memory memory 3F 3F sX sX Constant sY i address address opetstetsIskss e EEEEEEEE s x Each FETCH instruction must specify the destination register as s followed by a hexadecimal digit It must then specify the storage address using a register value in a similar way or specify a 6 bit constant storage address using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the proces
12. the flags before use The ability to specify any constant is useful in forming control sequences and counters sX sX Constant EES wee Es a ren fore E t E sX sX sY ES TESTES ESI E lt ERSTE E es E E TESTES Ee ES ERES Set if result of addition exceeds FF Set if all bits of result are zero CARRY Reset in all other cases ZERO Reset in all other cases Each ADD instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDsXKk 0 1 1 0 O O x x x X K k kK k k k k k sX Constant els de Ek e I w o K 7 6 5 4 9 2 1 0 ApDsXsY o t 1j0 o 1 x x x x v y v v 0 0 0 jo FH CUO OT sX sY al Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 23 96 Instruction Set PicoBlaze Instruction Set TEST The TEST instruction performs a bit wise logical AND operation between two operands Unlike the AND instruction the result of the operation is discarded and only the flags are affected The ZERO flag is set if all bits of the temporary result are low The CARRY flag is used to indicate the ODD PARITY of the temporary
13. C aaa JUMP NC aaa If CARRY flag not set jump to aaa If CARRY 0 PC aaa 2 Pe 0 RN Unconditionally return from subroutine PC TOS 1 JUMP NZ aaa If ZERO flag not set jump to aaa If ZERO 0 PC aaa E RETURN C If CARRY flag set return from subroutine If CARRY 1 PC TOS 1 JUMP Z aaa If ZERO flag set jump to aaa If ZERO 1 PC aaa RET C LOAD sX kk Load register sX with literal kk sX kk RETURN NC If CARRY flag not set return from If CARRY 0 PC TOS 1 E RET NC subroutine LOAD sX sY Load register sX with register SY sX sY SS SAEC RETURN NZ If ZERO flag not set return from If ZERO 0 PC TOS 1 OR sX kk Bitwise OR register sX with literal kk sX sX OR kk 0 RET NZ subroutine ste s M MM RETURN Z If ZERO flag set return from subroutine If ZERO 1 PC TOS 1 3 OUTPUT sx sY Write register sX to output port location PORT_ID sY RET Z OUT sx sY pointed to by register sY OUT PORT sX OUTPUT sX pp Write register sX to output port location pp PORT ID pp OUT sX pp OUT PORT sX 84 96 PicoBlaze Instruction Codes PicoBlaze Instruction Set Instructions CARRY Preserved CARRY INTERRUPT_ENABLE 1 Instruction Description Function ZERO CARRY RETURNI DISABLE Return from interrupt service routine Pe TOS RETI DISABLE Interrupt remains disabled ZERO Preserved ZERO CARRY Preserved CARRY INTERRUPT ENABLE
14. If sX lt sY CARRY 1 PC 3FF Registers are unaffected COMPARE sX kk Compare register sX with literal kk Set If sX kk ZERO 1 COMP CARRY and ZERO flags as appropriate If sX lt kk CARRY 1 Registers are unaffected FETCH sx sY FETCH sx sY Read scratchpad RAM location pointed to sX RAM sY by register sY into register sX DISABLE INTERRUPT Disable interrupt input DINT INTERRUPT_ENABLE 0 FETCH sX ss Read scratchpad RAM location ss into sX RAM ss register sX INPUT sX sY Read value on input port location pointed PORT ID sY Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 83 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 IN sX sY to by register sY into register sX sX IN PORT INPUT sX pp Read value on input port location pp into PORT ID pp IN PER sX IN PORT Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 81 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 82 96 PicoBlaze Instruction Codes PicoBlaze Instruction Codes Instructions Instructions JUMP aaa Unconditionally jump to aaa PC aaa JUMP C aaa If CARRY flag set jump to aaa If CARRY 1 P
15. OR sX sY CALL C aaa SUBCY sX sY XOR sX sY CALL NC aaa COMPARE sX sY TEST sX sY RETURN RETURN Z Interrupt Group Storage Group RETURN NZ RETURN C RETURNI ENABLE STORE sX ss RETURN NC RETURNI DISABLE STORE sX sY FETCH sX ss Note that call and return supports E ER up to a stack depth of 31 11 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane PORT ID 7 0 READ STROBE WRITE STROBE OUT PORTO Program Counter Interrupt Shadow Flags ADDRESS 9 0 Program Counter Stack Rok akad 2011 2012 Shift and Rotate Group SRO sX SRI sx SRX sX SRA sX RR sX SLO sX SL1 sx SLX sX SLA sX RL sx Input Output Group INPUT sX pp INPUT sX sY OUTPUT sX pp OUTPUT sX sY Rok akad 2011 2012 10 96 12 96 Instruction Set PicoBlaze Instruction Set JUMP Under normal conditions the program counter PC increments to point to the next instruction The address space is fixed to 1024 locations 000 to 3FF hex and therefore the program counter is 10 bits wide It is worth noting that the top of memory is 3FF hex and will increment to 000 PC PC LT TT TTT ttt lt LILI it 1 Normal instruction The JUMP instruction may be used to modify this sequence by specifying a new address However the JUMP instruction may be conditional A conditional JUMP will only be performed if a test performed on either the ZERO flag or CARRY flag is valid The JUMP instruction has no effect on the status of the f
16. RRY S 2 including CARRY CARRY sX 7 SLX sX Shift register sX left Bit sX 0 is sX sX 6 0 sX 0 unaffected CARRY sX 7 SRO sX Shift register sX right zero fill sX 0 sX 7 1 8 CARRY sX 0 SR1 sX Shift register sX right one fill sX 1 sX 7 1 0 CARRY sX 0 SRA sX Shift register sX right through all bits sX CARRY X 7 1 S including CARRY CARRY sX 0 SRX sX Arithmetic shift register sX right Sign sX sX 7 sX 7 1 S extend sX Bit sX 7 Is unaffected CARRY sX 0 Dr in Ignacy Pardyka Inf UJK PicoBlaze Instruction Set Instructions Systemy wbudowane Rok akad 2011 2012 Instruction Description Function ZERO CARRY TEST sX kk Test bits in register sX against literal kk If SX AND kk 0 ZERO 1 Update CARRY and ZERO flags Registers CARRY odd parity of sX are unaffected AND kk TEST sX sY Test bits in register sX against register sX If SX AND sY 0 ZERO 1 D Update CARRY and ZERO flags Registers CARRY odd parity of sX are unaffected AND kk XOR sX kk Bitwise XOR register sX with literal kk sX sX XOR kk 0 XOR sX sY Bitwise XOR register sX with register sY sX sX XOR sY 0 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 86 96 88 96 PicoBlaze Instruction Set Instructions SX One of 16 possible register locations rang
17. SYSTEMY WBUDOWANE PicoBlaze XILINX 8 bit Embedded Microcontroller User Guide UG129 Dr in Ignacy Pardyka UNIWERSYTET JANA KOCHANOWSKIEGO w Kielcach Rok akad 2011 2012 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 1 96 PicoBlaze PicoBlaze User Guide UG129 v2 0 January 28 2010 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 3 96 Introduction Introduction e PicoBlaze e PicoBlaze Functional Blocks Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 2 96 Introduction PicoBlaze Functional Blocks PicoBlaze Block Diagram PicoBlaze Structure o 5 y 1Kx1 8 64 Byte PORT_ID ja E Scratchpad RAM D e OUT PORT a Flags RSI Constants Zero Carry Enable f Operand 1 Operand 2 UG129 c1 01 051204 Figure 1 1 PicoBlaze Embedded Microcontroller Block Diagram Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 4 96 PicoBlaze Interface Signals PicoBlaze Interface Signals Systemy wbudowane Rok akad 2011 2012 Dr in Ignacy Pardyka Inf UJK PicoBlaze Interface PicoBlaze Interface Signals Table 2 1 PicoBlaze Interface Signal Descriptions Signal Direction Description The data is captured on the rising edge of CLK IN PORT 7 0 Input Input Data Port Present valid input data on this port during an INPUT instruction INTERRUPT Input Interrupt
18. TION 17 0 1Kx18 INSTRUCTION 17 0 DOPA 1 0 DOA 15 0 DOB 15 0 ADDRESS 9 0 ADDRA 9 0 ADDRB 9 0 ADDRESS 9 0 UG129 c7 04 051804 Figure 7 4 Two PicoBlaze Microcontrollers Sharing a Common Code Image Systemy wbudowane Dr in Ignacy Pardyka Inf UJK Rok akad 2011 2012 Rok akad 2011 2012 57 96 59 96 Instruction Storage Configurations Instruction Store Loading the Program UART or JTAG Programmer Block RAM 18 1Kx18 DIPA 1 0 DOPB 1 0 DIA 15 0 DOB 15 0 WEA ADDRA 9 0 ADDRBJ 9 0 KCPSM3 INSTRUCTION 17 0 ADDRESS 9 0 UG129 c7 03 051504 Figure 7 3 Standard Configuration with UART or JTAG Program Loader Dr in Ignacy Pardyka Inf UJK Systemy wbudowane PicoBlaze Development Tools PicoBlaze Development Tools Systemy wbudowane Dr in Ignacy Pardyka Inf UJK Rok akad 2011 2012 Rok akad 2011 2012 58 96 60 96 KCPSM3 Assembler Files filename psm gt PicoBlaze source program Block RAM pass1 dat initialization ROM form vhd gt pass2 dat Assembler ee templates for a ROM form v gt KCPSM3 EXE pass3 dat Ge iles possibly variety of design 4 4 useful for debugging ROM form coe pass4 dat assembly errors flows pass5 dat Assembled PicoBlaze lt filename gt vhd lt filename gt log de formatted to initiali i ablock RAM foravanely A sa constants txt Assembler report files of design flows
19. a Inf UJK Systemy wbudowane Rok akad 2011 2012 27 96 Instruction Set PicoBlaze Instruction Set SUBCY The SUBCY instruction performs an 8 bit subtraction of two operands together with the contents of the CARRY flag The first operand is any register and it is this register which will be assigned the result of the operation The second operand may also be any register or an 8 bit constant value Flags will be effected by this operation The SUBCY operation can be used in the formation of subtract and down counter processes exceeding 8 bits sx sX Constant CARRY EE EECH us sX sX sY CARRY EEEEEEEEFK ESIESTESTESIES TES ESTE EIERE FE Set if result is negative Set if all bits of result are zero CARRY Reset in all other cases ZERO Reset in all other cases Each SUBCY instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRONO MKIMKMGEEEEREKGEKERE sX Constant 17 16 15 14 139512 1 109 8 7 Oo o 4 9 2 1 0 suBcYsxev o 1 1 1 1 1 x x x xj v v v v 0 jo 0 o my MER es sX sY al Dr in Ignacy Pardyka Inf UJK Systemy wbudo
20. akad 2011 2012 35 96 Instruction Set PicoBlaze Instruction Set READ and WRITE STROBES These pulses are used by external circuits to confirm input and output operations In the waveforms below it is assumed that the content of register sE is 47 and the content of register sA is 42 TE irre D Ee em E Re Ld P E c EE E Ek ADDRESS 0 INSTRUCTION 17 0 PORT ID 7 0 OUT PORT 7 0 WRITE STROBE READ_STROBE ee 1 t KCPSMS captures data into s2 Use WRITE STROBE to clock register on this clock edge enable external circuit and capture data on this clock edge PORT_ID 7 0 is valid for 2 clock cycles providing additional time for external decoding logic and enabling the connection of synchronous RAM The WRITE STROBE is provided on the second clock cycle to confirm an active write by KCPSM3 In most cases the READ STROBE will not be utilised by the external decoding logic but again occurs in the second cycle and indicates the actual clock edge on which data is read into the specified register Note for timing critical designs your timing specifications can allow 2 clock cycles for PORT ID and data paths and only the strobes need to be constrained to a single clock cycle Ideally a pipeline register can be inserted where possible see Design of Input Ports Design of Output Ports and Connecting Memory a Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 34 96 Moving Data Moving D
21. alue of sY is within the address range 17 16 15 14 13 12 11 10 9 8 7 6 9 aU 8 2 1 0 STOREsX PP 1 0 1 1 1 o x x x x o 0 s s s s s s OO sx Constant address 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STORE sx s t1 o 1 1 t1 1 x x x x v v y y 00 0 O Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 30 96 Instruction Set PicoBlaze Instruction Set OUTPUT The OUTPUT instruction enables the contents of any register to be transferred to logic external to KCPSM3 The port address in the range 00 to FF can be defined by a constant value or indirectly as the contents of any other register The Flags are not affected by this operation Port Value sX PORT_ID Address Constant O lt OAN ANTT e kkkt Port Value sX PORT_ID Address sY EIERE EE DICH DOE EE The user interface logic is required to decode the PORT ID port address value and capture the data provided on the OUT PORT The WRITE STROBE is set during an output operation see READ and WRITE STROBES and should be used to clock enable the capture register or write enable a RAM see Design of Output Ports Each OUTPUT instruction must specify the source register as s followed by a hexadecimal digit It must then specify the output port address using a register value in a similar way or specify an 8 bit constant port identifier using 2 hexadecimal digits The assembler supports register naming and constant labels to simpli
22. alues for RETURN instructions which can not be defined Bit11 Bit 10 Condition z 3 0 0 if Zero Te Te 3T T T TeTeToTeToTeToToTo o 0 1 ifNOTZero 1 0 if Carry Bit 12 0 UNCONDITIONAL 1 1 if NOT Carry 1 CONDITIONAL a Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 15 96 Instruction Set PicoBlaze Instruction Set CALL The CALL instruction is similar in operation to the JUMP instruction in that it will modify the normal program execution sequence by specifying a new address The CALL instruction may also be conditional In addition to supplying a new address the CALL instruction also causes the current program counter PC value to be pushed onto the program counter stack The CALL instruction has no effect on the status of the flags Sor be Unconditional or P m SG EE a EE condition valid TEES eee Dl New Address E Se aaa aja a a a a a a a a F p CALL C aaa ncon d ional or GAN TAN aaa condition valid The program counter stack supports a depth of 31 address values This enables nested CALL sequences to a depth of 31 levels to be performed However the stack will also be used during an interrupt operation and hence at least one of these levels should be reserved when interrupts are enabled The stack is implemented as a separate cyclic buffer When the stack becomes full it simply overwrites the oldest value Hence it is not necessary to reset the stack pointer when performing a softwar
23. any register and it is this register which will be assigned the result of the operation A second operand may also be any register or an 8 bit constant value Flags will be effected by this operation The AND operation is useful for resetting bits of a register and performing tests on the contents see also TEST instruction The status of the ZERO flag will then control the flow of the program sX sX Constant LLLLLLLI ITT AND sX sX sY C111 lt OIII ano aen sns o es scs Set if all bits of result are zero CAREY o ZERO Reset in all other cases Each AND instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process w 1G ds 14 d9 2 dd 8G v G 6 A 9 2 4 ANDsXkk 0 0 1 0 1 0 x x X X K K K KJk k k k sX Constant 17 16 15 14 13 12 11 10 9 8 7 6 5 4 302 1 0 ANDsXsY ojo t1j0o 1 1 x x x x y v v y 0 o jojo Cc sX sY al Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 19 96 Instruction Set PicoBlaze Instruction Set LOAD The LOAD instruction provides a method for specifying the contents of any register The new value can be a constant or the c
24. ata Scratchpad RAM Registers lt i IN_PORT OUT_PORT INPUT LOAD sX sY OUTPUT INPUT sX sY LOAD sX kk OUTPUT sX sY PORT_ID Instruction Store INPUT sX kk OUTPUT sX kk UG129 c3 05 060404 Figure 3 26 Data Movement Instructions Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 36 96 JUMP JUMP and CALL RETURN ADDRESS 000 If CARRY is set load the PC with the address of the label skip over Call my subroutine Save the current PC to top of CALL RETURN stack Load the PC with the address of my subroutine Skip over JUMP main my subroutine RETURN Return from my subroutine Load the PC with the top of the CALL RETURN stack plus 1 Execute the instruction immediately following the associated CALL instruction UG129 c3 06 051404 Figure 3 27 Example JUMP and CALL RETURN Procedures Systemy wbudowane Rok akad 2011 2012 37 96 Dr in Ignacy Pardyka Inf UJK Interrupts Interrupts Interrupt Logic Interrupt signal PicoBlaze Microcontroller INTERRUPT INTERRUPT ACK UG129 c4 01 060404 Figure 4 1 Simple Interrupt Logic Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 39 96 Interrupts Interrupts Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Interrupts Interrupts Interrupt Flow DDRESS 000 INTERRUPT input asserted
25. cy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 47 96 Scratchpad RAM Stack Operations in Program Stack in RAM Figure 5 4 Use Scratchpad RAM to Emulate PUSH and POP Stack Operations Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 Input Operation Input Operation FPGA Logic PicoBlaze Microcontroller 8 Register sv or PORT mg READ STROBE 7 7 4 UG129_c6_01_052004 Figure 6 1 INPUT Operation and FPGA Interface Logic Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 46 96 48 96 Input Operation Port Timing The PicoBlaze microcontroller captures the value on IN PORT 7 0 into register s0 on this clock edge 0 1 2 3 4 CLK INSTRUCTION 17 0 mees aptent LU PORT_DI7 0 A Si A IN_PORTI7 0 AAAMAAMAMAM MAMAMAMAAAAA READ STROBE Captured Value from Register s0 IN PORT 7 0 UG129 c6 02 060404 Figure 6 2 Port Timing for INPUT Instruction Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 Input from FIFO Using READ STROBE PicoBlaze Microcontroller IN PORT 7Z 0 OUT PORT 7 0 PORT ID 7 0 If performance is adequate remove the flip flip and combine READ STROBE the READ STROBE and PORT ID decode logic WRITE STROBE FIFO READ DATA OUT p READ STROBE PORT ID 1 PORT ID 0 UG129 c6 04 060404 F
26. des RL sX 1 0 0 0 0 0 RR sX 110 0 0 0 0 SLO sX 1 0 0 0 0 0 SL1 sX 1 0 0 0 0 0 SLA sX 1 0 0 0 0 0 SLX sX 1 0 0 0 0 0 SRO sX 110 0 0 0 0 SR1 sX 1 0 0 0 0 0 SRA sX 1 0 0 0 0 0 SRX sX 38 399 o1 FG ho STORE sX ss ENEE STORE sX sY EMEN kt Ta Dr in Ignacy Pardyka Inf UJK Related Materials and References 9 Related Materials and References Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Systemy wbudowane Rok akad 2011 2012 Rok akad 2011 2012 0 00 00 1 0 0 0 0 0 1 010 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 01 0700 010 0 0 0 0 0 010 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 010 0 0 0 0 1 1 0 0 0 ps s S s s 0 010 PicoBlaze Instructions Instruction Codes SUB sX kk 0 1 1 1 00 SUB sX sY 0 1 1 1 0 1 0 0 SUBCY sX kk OWL ck JL 28 SUBCY sX sY 0 1 1 1 1 1 0101 10 0 TEST sX kk 0 DEE 0 T 0 TEST sX sY 0 1 0 0 11 0 0 0 XOR sX kk 0 0 1 1 1 0 XOR sX sY 0 0 1 1 1 1 0 0 0 0 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 94 96 Related Materials and References Bibliography Dr in Ignacy Pardyka Inf UJK PicoBlaze 8 bit Embedded Microcontroller Download PicoBlaze reference designs and additional files
27. e reset This also explains why there are no instructions to control the stack and why no other memory needs to be reserved or provided for the stack Each CALL instruction must specify the 10 bit address as a 3 digit hexadecimal value The assembler supports labels to simplify this process Bit11 Bit 10 Condition 17 15 14 11 0 n T CTS oloo T T TeTaTaTaT aTaTaTaTa 0 1 INOT Zero 1 0 if Carry Bit12 0 UNCONDITIONAL 1 1 if NOT Carry 1 CONDITIONAL ad Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 14 96 Instruction Set PicoBlaze Instruction Set RETURNI The RETURNI instruction is a special variation of the RETURN instruction which should be used to conclude an interrupt service routine The RETURNI is unconditional and therefore will always load the program counter PC with the last address on the program counter stack the address is not incremented in this case since the instruction at the address stored will need to be executed The RETURNI instruction restores the flags to the condition they were in at the point of interrupt The RETURNI also determines the future ability of interrupts using ENABLE and DISABLE as an operand Stack Preserved CARRY CARRY 4 1 INTERRUPT ENABLE PC aneii os i RE E E 8 ce ea E lt lt Preserved LJ ZERO ZERO 0 By DISABLE It is the responsibility of the programmer to ensure that a RETURNI is only performed in response to an interrupt Each
28. fy the process 17 16 15 4 13 12 W 10 9 8 7 6 5 4 3 2 1 0 ouTPUTsXPP 1 0 1 1 0 jo x x x x p p p p p p p p_ SX Constant PORT ID 17 16 15 14 13 1 i WW 2 JI 5 4 9 2 1 0 ourpuTsxisy 1jojt 1Jo t x x x x v ly v ly jo 000 O a Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 32 96 Instruction Set PicoBlaze Instruction Set INPUT The INPUT instruction enables data values external to KCPSM3 to be transferred into any one of the internal registers The port address in the range 00 to FF can be defined by a constant value or indirectly as the contents of any other register The Flags are not affected by this operation sX Port Value PORT_ID Address Constant OTT TES ONN AAT T e Erbe sX Port Value PORT_ID Address sY EE S m EBEEEEEK e TEES RES LS ES FS f cs ERES Fs FS RESISTE The user interface logic is required to decode the PORT D port address value and supply the correct data to the IN PORT The READ STROBE is set during an input operation see READ and WRITE STROBES but it is not always necessary for the interface logic to decode this strobe However it can be useful for determining when data has been read such as when reading a FIFO buffer see Design of Input Ports Each INPUT instruction must specify the destination register as s followed by a hexadecimal digit It must then specify the input port address using a register value in a similar way or specify an 8 bit
29. igure 3 12 Destructive Negate 2 s Complement Function Overwrites Original Value Figure 3 13 Non destructive Negate Function Preserves Original Value Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 75 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 76 96 PicoBlaze Programming Using PicoBlaze Instructions Hardware Multiplier Using PicoBlaze Instructions Assembler Program for Hardware Multiplier 18x18 Multiplier PicoBlaze Microcontroller IN PORT 7 0 OUT PORTT 7 0 PORT ID 7 0 READ STROBE WRITE STROBE UG129 c3 02 052004 Figure 3 15 8 bit by 8 bit Hardware Multiplier Using the FPGA s 18x18 Multipliers Figure 3 16 8 bit by 8 bit Multiply Routine Using Hardware Multiplier Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 77 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 78 96 PicoBlaze Instruction Codes PicoBlaze Instruction Codes PicoBlaze Instruction Set Instructions Table 3 1 PicoBlaze Instruction Set alphabetical listing Instruction Description Function ZERO CARRY ADD sX kk Add register sX with literal kk sX sX kk g ADD sX sY Add register sX with register sY sX sX sY ADDCY sX kk Add register sX with literal kk with sX sX kk CARRY S ADDC CARRY bit ADDCY sX sY Add register sX with reg
30. igure 6 4 READ STROBE Indicates a Successful INPUT Operation Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 49 96 51 96 Input and Output Ports Input Operations Multiple Input Sources Multiplex to Form a Single IN PORT Port Registering the multiplexer output is allowed because PORT ID is asserted for two clock cycles Registering improves performance IN C PicoBlaze Microcontroller IN PORT 7 0 OUT PORT 7 0 PORT ID 7 0 READ STROBE WRITE STROBE PORT ID O PORT ID 1 UG129 c6 03 060404 Figure 6 3 Multiplex Multiple Input Sources to Form a Single IN PORT Port Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 50 96 Input and Output Ports Output Operations Output Operation FPGA Interface FPGA Logic PicoBlaze Microcontroller Register sx B OUT_PORTT 7 0 WRITE_STROBE Register sy or rom ia UG129 c6 05 052004 Figure 6 5 OUTPUT Operation and FPGA Interface Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 52 96 Input and Output Ports Output Operations Output Operation Port Timing Use WRITE STROBE as the clock enable to capture output values in FPGA logic 0 1 l2 3 4 CLK A A A Contents of WRITE_STROBE H US OUT PORT 7 0 UG129 c6 06 060404 FPGA Register Figure 6 6 Port Timing for OUTPUT Instruction Dr in
31. ing from s0 through sF or specified as a literal SY One of 16 possible register locations ranging from s0 through sF or specified as a literal aaa 10 bit address specified either as a literal or a three digit hexadecimal value ranging from 000 to 3FF or a labeled location kk 8 bit immediate constant specified either as a literal or a two digit hexadecimal value ranging from 00 to FF or specified as a literal pp 8 bit port address specified either as a literal or a two digit hexadecimal value ranging from 00 to FF or specified as a literal SS 6 bit scratchpad RAM address specified either as a literal or a two digit hexadecimal value ranging from 00 to 3F or specified as a literal RAM n Contents of scratchpad RAM at location n TOS Value stored at Top Of Stack Dr in Ignacy Pardyka Inf UJK Systemy wbudowane PicoBlaze Instructions Instruction Codes Rok akad 2011 2012 COMPARE sX kk 01 0 0 COMPARE sX sY 0 1 0 0 DISABLE INTERRUPT 1 1 1 0 ENABLE INTERRUPT 1 dy I 0 FETCH sX ss 0 0 0 1 FETCH sX sY 0 00 1 INPUT sX sY 0 00 0 INPUT sX pp 0 0 0 0 JUMP 1 10 0 JUMP C 1 10 0 JUMP NC 1 10 0 JUMP NZ 1 10 0 JUMP Z 1 10 0 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 89 96 91 96 Table D 1 PicoBlaze Instruction Codes PicoBlaze Instructions
32. is any register and it is this register which will be assigned the result of the operation The second operand may also be any register or an 8 bit constant value Flags will be effected by this operation Note that this instruction does not use the CARRY as an input and hence there is no need to condition the flags before use The CARRY flag indicates when an underflow has occurred For example if s05 contains 27 hex and the instruction SUB s05 35 is performed then the stored result will be F2 hex and the CARRY flag will be set sX sX Constant LLLLLLLI 4 LLLLLLLI edikki sX sX sY Eelere Set if result is negative E Set if all bits of result are zero CARRY Reset in all other cases ZERO B Reset in all other cases Each SUB instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SUBsXKk 0 1 1 1 ofo x x x x k k k k k k k k sX Constant 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SUB sxs o t 1 t o 1 x x x x v v v v 0 0 jojo a sX sY d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 25 96 Instruction Set PicoB
33. ister sY with sX sX sY CARRY 4 ADDC CARRY bit AND sX kk Bitwise AND register sX with literal kk sX sX AND kk 4 0 AND sX sY Bitwise AND register sX with register sY sX sX AND sY 4 0 CALL aaa Unconditionally call subroutine at aaa TOS PC PC aaa CALL C aaa If CARRY flag set call subroutine at aaa If CARRY 1 TOS PC PC aaa CALL NC aaa If CARRY flag not set call subroutine at If CARRY 0 TOS PC aaa PC aaa CALL NZ aaa If ZERO flag not set call subroutine at aaa If ZERO 0 TOS PC T PC aaa PicoBlaze Instruction Codes CALL Z aaa If ZERO flag set call subroutine at aaa If ZERO 1 TOS PC PC aaa Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 79 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 PicoBlaze Instruction Set Instructions PicoBlaze Instruction Set Instructions Instruction Description Function ZERO CARRY ENABLE INTERRUPT Enable interrupt input EINT INTERRUPT ENABLE 1 Interrupt Event Asynchronous interrupt input Preserve Preserved ZERO ZERO flags and PC Clear INTERRUPT_ENABLE Preserved CARRY CARRY Se Jump to interrupt vector at address INTERRUPT ENABLE 0 COMPARE sX sY Compare register sX with register sY Set If sX sY ZERO 1 2 TOS PC COMP CARRY and ZERO flags as appropriate
34. lags Condition PC not valid SSES See PC p d Ege ES ESTEE ES ES JUMP aaa Y New Address JUMP Z aaa alalalalalslalalalal JUMP NZ aaa Unconditional or JUMP C aaa condition valid JUMP NC aaa Each JUMP instruction must specify the 10 bit address as a 3 digit hexadecimal value The assembler supports labels to simplify this process Bit 11 Bit 10 Condition Z AL 0 0 if Zero apr IER EXERESEHELELERERERER 0 1 ifNOTZero 1 0 if Carry Bit12 0 UNCONDITIONAL 1 1 if NOT Carry CONDITIONAL d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 13 96 Instruction Set PicoBlaze Instruction Set RETURN The RETURN instruction is the complement to the CALL instruction The RETURN instruction may also be conditional In this case the new program counter PC value will be formed internally by incrementing the last value on the program address stack This ensures that the program will execute the instruction following the CALL instruction which resulted in the subroutine The RETURN instruction has no effect on the status of the flags Condition not valid PC PD aoe el PC o Y 1 RETURN RETURN Z RETURN NZ Unconditional or RETURN C condition valid RETURN NC It is the responsibility of the programmer to ensure that a RETURN is only performed in response to a previous CALL instruction such that the program counter stack contains a valid address The cyclic implementation of the stack will continue to provide v
35. laze Instruction Set COMPARE The COMPARE instruction performs an 8 bit subtraction of two operands Unlike the SUB instruction the result of the operation is discarded and only the flags are affected The ZERO flag is set when all the bits of the temporary result are low and indicates that both input operands were identical The CARRY flag indicates when an underflow has occurred and indicates that the second operand was larger than the first For example if s05 contains 27 hex and the instruction COMPARE s05 35 is performed then the CARRY flag will be set 35227 and the ZERO flag will be reset 35427 Temporary sX Constant CONT ITTITTT ikk Temporary sX sY RER ilIII IIIITITI Set if sY or kk is greater than sX Set if operands are equal CARRY Reset in all other cases ZERO Reset in all other cases Each COMPARE instruction must specify the first operand register as s followed by a hexadecimal digit The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 11 10 9 8 7 6 5 4 32 1 0 COMPARE sX kk 0 1 0 1 0jo x x x x k k k k k k k k NK 2 sX Constant 17 16 15 14 deb 3G apod 5 d y G 5 4 32 1 0 COMPARE sX sY 0 1 0 1 0 1 x x x x y y y y ojo o 0 n a sX sY 6 Dr in Ignacy Pardyk
36. ll be effected by this operation The XOR operation is useful for inverting bits contained in a register which is useful in forming control signals sX sX Constant TTTTTTT a LLLILILIIIT X0R sX sX sY SIE e morro XR n CS ESTEE SES E Set if all bits of result are zero CARRY o ZERO Reset in all other cases Each XOR instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 M 10 9 8 7 6 5 4 3 2 1 0 XORsXkk o o 1 1 1 fo x x x x k k k k k k k ki sX Constant 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XoRsXsY 0j0 1 1 1 1 x x x x v v v jv j0 0 0 0 Cc sX sY d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 21 96 Instruction Set PicoBlaze Instruction Set ADD The ADD instruction performs an 8 bit addition of two operands The first operand is any register and it is this register which will be assigned the result of the operation A second operand may also be any register or an 8 bit constant value Flags will be effected by this operation Note that this instruction does not use the CARRY as an input and hence there is no need to condition
37. lt filename gt coe lt filename gt m labels txt Assembled PicoBlaze lt filename gt hex F i i ormatted version of input code formatted for other lt filename gt fmt GENEE p utilities lt filename gt dec UG129 c10 01 052004 Figure 10 1 KCPSMS Assembler Files Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 61 96 KCPSM3 Simple Base System KCPSM3 PicoBlaze WINE IN PORT 7 0 OUT PORTO ED INTERRUPT PORT ID ZO SZ PECET READ STROBE SE gt CLK WRITE_STROBE Program ROM i INTERRUPT ACK INSTRUCTION 17 0 X ADDRESS 9 0 ADDRESS 9 0 INSTRUCTION 1 7 0 CLK Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 63 96 KCPSM3 Application Program Template Figure B 1 PicoBlaze Application Program Template for KCPSM3 Assembler Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 62 96 PicoBlaze Development Tools Using PicoBlaze Microcontroller Module Sample Toplevel Verilog Module module toplevel input clk output 7 0 leds input 7 0 sliders input 3 0 buttons testprg progrom address address instruction instruction clk clk kcpsm3 pblaze address address instruction instruction Port id port id write_strobe write_strobe out port out port read strobe read strobe in port in
38. nterface Connections Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 PicoBlaze Interface PicoBlaze Interface Signals cont d Table 2 1 PicoBlaze Interface Signal Descriptions Cont d Signal Direction Description READ STROBE Output Read Strobe When asserted High this signal indicates that input data on the IN PORT 7 0 port was captured to the specified data register during an INPUT instruction This signal is asserted on the second CLK cycle of the two cycle INPUT instruction This signal is typically used to acknowledge read operations from FIFOs WRITE STROBE Output Write Strobe When asserted High this signal validates the output data on the OUT_PORT 7 0 port during an OUTPUT instruction This signal is asserted on the second CLK cycle of the two cycle OUTPUT instruction Capture output data within the FPGA on the rising CLK edge when WRITE STROBE is High INTERRUPT ACK Output Interrupt Acknowledge When asserted High this signal acknowledges that an INTERRUPT Event occurred This signal is asserted during the second CLK cycle of the two cycle INTERRUPT Event This signal is optionally used to clear the source of the INTERRUPT input Systemy wbudowane Rok akad 2011 2012 Dr in Ignacy Pardyka Inf UJK 6 96 8 96 PicoBlaze Interface Signals PicoBlaze KCPSM3 KCPSM3 is a very simple 8 bit microcontroller primarily for the Spartan 3 devices but also
39. ontents of any other register The LOAD instruction has no effect on the status of the flags sX Constant CITT TTT lt 4 sX sY ESTEE ESTEE E OV ESTER LE E Since the LOAD instruction does not effect the flags it may be used to reorder and assign register contents at any stage of the program execution The ability to assign a constant with no impact to the program size or performance means that the load instruction is the most obvious way to assign a value or clear a register The first operand of a LOAD instruction must specify the register to be loaded as register s followed by a hexadecimal digit The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 LoADsXKk o ojojo ojO x x x x k K K k K K k k sX Constant 121621528141 912 iW w G y 0 a 4 J 2 1 0 LOAD sXsY 0 0 0 0 0 1 x x x x y y y yjo o o jo sX sY al Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 18 96 Instruction Set PicoBlaze Instruction Set OR The OR instruction performs a bit wise logical OR operation between two operands For example 00001111 OR 00110011 will produce the result 00111111 The first operand is any register and it is this register which will be assigned the result of the operation A second
40. operand may also be any register or an 8 bit constant value Flags will be effected by this operation OR provides a way to force any bits of the specified register to be set which can be useful in forming control signals sX sX Constant C11 lt AOIN OR sX sX sY CITIT lt gt OIII OR Ed Set if all bits of result are zero CARRY 0 ZERO Reset in all other cases Each OR instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process i is us 3134 319 32 at WW G9 v G 5 4 S 2 1 0 zb MEC E E UG CORE ESTEE EST SLE SES USES E o o sX Constant 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ORsXsY 0j0 1 1 0 1 x x x x v v jv jv 0 0 ofo SS SS GN sX sY g Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 20 96 Instruction Set PicoBlaze Instruction Set XOR The XOR instruction performs a bit wise logical XOR operation between two operands For example 00001111 XOR 00110011 will produce the result 00111100 The first operand is any register and it is this register which will be assigned the result of the operation A second operand may also be any register or an 8 bit constant value Flags wi
41. port reg interrupt 1 b0 interrupt ack 1 bZ reset reset Clk clk Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 64 96 Instruction Memory Module Generated by KCPSM3 Assembler module testprg address instruction clk input 9 0 address input clk output 17 0 instruction RAMB16 818 ram 1024 x 18 DI 16 h0000 DIP 27500 EN 1 b1 WE 1 b0 SSR 1 b0O CLK clk ADDR address DO instruction 15 0 DOP instruction 17 16 synthesis init 00 410740074004C6064601C5014502C405C304A40083010013C4050400C3040311 00000000000000000000000000000000A00054148201000E0205A000500F5010 0000000000000000000000000000000000000000000000000000000000000000 init O1 init 02 endmodule Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Using PicoBlaze Instructions Complementing a Register Value Figure 3 2 Complementing a Register Value Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 Rok akad 2011 2012 65 96 67 96 PicoBlaze Programming PicoBlaze Programming Dr in Ignacy Pardyka Inf UJK Systemy wbudowane PicoBlaze Programming Using PicoBlaze Instructions Inverting an Individual Bit Location Rok akad 2011 2012 Figure 3 3 Inverting an Individual Bit Location Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 66 96 68 96
42. result Parity checks typically involve a test of all bits i e if the contents of s5 3D 00111101 the execution of TEST s5 FF will set the CARRY flag indicating ODD parity Bit testing is typically used to isolate a single bit For example TEST s5 04 will test bit2 of the s5 register which would set the CARRY flag if the bit is high reset if the bit is low and set the ZERO flag if the bit is low reset if the bit is high Temporary sX Constant TTT a LILIIIITI AND Temporary SX sY EFFFEFFFF coors AW IIIIIIT Set if there are an odd number of bits 2 Set if all bits of temporary result are zero GARDA set to 1 in the temporary result AES DH Reset in all other cases Each TEST instruction must specify the first operand register as s followed by a hexadecimal digit The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process v 1 1 11 2 WW WW 9 G FY GO o 9 2 1 0 ce HOST Y ESO C ESTE ES ES eae dee sX Constant Mm 16 15 14 8 12 M 10 9 8 7 6 5 4 2 1 0 TESTsXsY 0 1 0 0 1 1 x x x x yjy y y jojo jo o sX sY d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 22 96 Instruction Set PicoBlaze Instruction Set ADDCY The ADDCY instruction performs an addition of two 8 bit operands together wi
43. s Although the assembler will reject constants greater than 3F it is the responsibility of the programmer to ensure that the value of sY is within the address range 17 16 15 14 13 12 1 10 9 8 7 6 5 4 3 2 14 0 FETCH sxX PP 0 0 0 1 1jO x x x xjO 0 s s s s s sX Constant address if 419 wis 12 dd dU 9 oO y B d amp d 9 2 1 0 FETCH sx sY ojojo 1 t 1 x x x x v v v vj0 0 jo o C sX sY d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 31 96 Instruction Set PicoBlaze Instruction Set STORE The STORE instruction enables the contents of any register to be transferred to the 64 byte internal scratch pad memory The storage address in the range 00 to 3F can be defined by a constant value or indirectly as the contents of any other register The Flags are not affected by this operation Scratch pad Scratch pad memory memory 3F 3F SX SX p ESI EE FER EUER ER EEN ro tcx DIE SE Constant T Poe lojols s s s s s e Each STORE instruction must specify the source register as s followed by a hexadecimal digit It must then specify the storage address using a register value in a similar way or specify a 6 bit constant storage address using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process Although the assembler will reject constants greater than 3F it is the responsibility of the programmer to ensure that the v
44. suitable for use in Virtex ll and Virtex IIPRO devices Although it could be used for processing of data it is most likely to be employed in applications requiring a complex but non time critical state machine Hence it has the name of K constant Coded Programmable State Machine This revised version of popular KCPSM macro has still been developed with one dominant factor being held above all others Size The result is a microcontroller which occupies just 96 Spartan 3 Slices which is just 5 of the XC3S200 device and less than 0 3 of the XC3S5000 device Together with this small amount of logic a single block RAM is used to form a ROM store for a program of up to 1024 instructions Even with such size constraints the performance is respectable at approximately 43 to 66 MIPS depending on device type and speed grade KCPSM3 IN PORT 7 0 INTERRUPT RESET OUT PORT 7 0 Interface to logic PORT _ID 7 0 READ STROBE Interface to logic Block Memory WRITE STROBE Program INTERRUPT ACK INSTRUCTION 17 0 INSTRUCTION 17 0 X ADDRESS 9 0 ADDRESSJ9 0 One of the most exciting features of the KCPSM3 is that it is totally embedded into the device and requires no external support The very fact that ANY logic can be connected to the module inside the Spartan 3 or Virtex Il device means that any additional features can be added to provide ultimate flexibility It is not so much what is inside the KCPSM3 module that makes it
45. th the contents of the CARRY flag The first operand is any register and it is this register which will be assigned the result of the operation A second operand may also be any register or an 8 bit constant value Flags will be effected by this operation The ADDCY operation can be used in the formation of adder and counter processes exceeding 8 bits sX sX Constant CARRY s ESTER 86 ES E GERI SZ SKKKKEKEK 0O sX sX sY CARRY KEEKEREKI lt St L Set if result of addition exceeds FF Set if all bits of result are zero CARRY Reset in all other cases ZERO Reset in all other cases Each ADDCY instruction must specify the first operand register as s followed by a hexadecimal digit This register will also form the destination for the result The second operand must then specify a second register value in a similar way or specify an 8 bit constant using 2 hexadecimal digits The assembler supports register naming and constant labels to simplify the process 17 16 15 14 13 12 14 10 9 8 7 6 5 4 3 2 141 0 ADDCYsXkk 0 1 1 0 1 O x x X X k K k K K k k k sX Constant 17 16 15 14 13 12 di do 590 o 7y G o9 4 9 2 1 0 ApDCYsXsY o 1 1 o t 1 x x x x v v v y 000 o sX sY d Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 24 96 Instruction Set PicoBlaze Instruction Set SUB The SUB instruction performs an 8 bit subtraction of two operands The first operand
46. useful but the environment in which it lives al Rok akad 2011 2012 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Instruction Set Instruction Set Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 PicoBlaze Interface Signals PicoBlaze KCPSMB3 Architecture 16 Registers Port 8 bit Address Control IN PORT 7 0 Arithmetic Logical Shift Rotate Scratch Pad Memory 64 Bytes 18 bit instruction word EN 8bit data path MM 8 bit port address EM 10 bit program address PRM Constants INTERRUPT INTERRUPT_ACK Interrupt Control Program Flow Control INSTRUCTION 17 0 Program ROM RAM Operational control amp Instruction decoding 1024 words 9 96 Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Instruction Set Instructions X and Y refer to the definition of the storage registers s in the range 0 to F kk represents a constant value in the range 00 to FF aaa represents an address in the range 000 to 3FF pp represents a port address in the range 00 to FF ss represents an internal storage address in the range 00 to 3F Program Control Group Arithmetic Group Losical Gron JUMP Zoa ADDCY aX kk Ra a gt gt pe AND sX kk JUMP NZ aaa SUB sX OR sX kk JUMP C aaa SUBCY SX m XOR sX kk JUMP NC aaa COMPARE sX TEST sX kk CALL aaa ADD sX sY LOAD sX sY CALL Z aaa ADDCY sX sY AND sX sY CALL NZ aaa SUB sX sY
47. wane Rok akad 2011 2012 26 96 Instruction Set PicoBlaze Instruction Set SRO SR1 SRX SRA RR The shift and rotate right group all modify the contents of a single register All instructions in the group have an effect on the flags sX CARRY UA Set if all bits of result are zero SROSX 0 gt TTEEEEE gt L ZERO ERR AE sX CARRY SR1 sX ale gt H ZERO 0 SX CARRY T SRX sX Leo De ZERO Set if all bits of result are zero Reset in all other cases SRA sX one ZERO Set if all bits of result are zero Reset in all other cases RR sX CARRY ah cae ZERO Set if all bits of result are zero Reset in all other cases Each instruction must specify the register as s followed by a hexadecimal digit The assembler supports register naming to simplify the process Bit2 Bit1 BitO Instruction 17 16 15 14 13 12 11 10 0 SRO sX 9 8 7 6 5 4 3 2 1 1 1 0 ajejojo ojoixj xjxjxjoj0 0 0 1 5 4 RX 0 1 0 SRX sX mcr E 0 0 0 SRA sX sX 1 0 0 RR sX m a Dr in Ignacy Pardyka Inf UJK Systemy wbudowane Rok akad 2011 2012 28 96 Instruction Set PicoBlaze Instruction Set SG IMS IONS AE The shift and rotate left group all modify the contents of a single register All instructions in the group have an effect on the flags CARRY sX p Set if all bits of result are zero SLO sx CCCI 0 ZERO Shieh en 2 CARRY SX SL1 sX Chen zero 0 CARRY sX T SLX sX SE ee eege ZERO Set if all bits
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