User Manual and Parts List DAC 670 MK5 CAMAC OPTO
Contents
1. HYTEC ELECTRONICS LTD 5 Cradock Road Reading Berkshire RG2 OJT U K Tel 44 0 118 9757770 Fax 44 0 118 9757566 Email sales hytec electronics co uk VAT Reg No 285 247927 Web Site www hytec electronics co uk User Manual and Parts List DAC 670 MK5 CAMAC OPTO ISOLATED DUAL 18 BIT DAC 18 Bit Binary Resolution 18 Bit Absolute Accuracy Also at 64 Amy Street Leicester LE3 2FB U K Sales amp Service North Directors R R T Tatham G S Cross Secretary R R Tatham Registered Office 5 Cradock Road Reading Berkshire RG2 OJT Incorporated in England No 1246940 Issue 2 Page 1 Doc Hytec DAC 670 Author RRIT Doc no 55 Date 25 11 98 DAC 670 MK5 CAMAC OPTO ISOLATED DUAL 18 BIT 18 Bit Binary Resolution 18 Bit Absolute Accuracy DESCRIPTION Overview The 670 Mk5 is high precision Dual 18 bit optically isolated Digital to Analog Converter DAC designed to be used as a accurate voltage source or as the fine trim on a high voltage system such as the focus control on an electron microscope It may also be used to provide very accurate ramp voltages to test ADC systems General applications include Automatic test equipment scientific instrumentation beam positioners and very high quality digital audio Description It is a single width CAMAC module which contains two completely separate opto isolated 18 bit DACs Each converter circuit includes facilities such as referenc2. 0 00019 of final value LSB change bus 1 2 LSB 0 00019 of final value Glitch energy is 500 mV x 500nS for major carry ole Output Noise Band Width O 100KHz 60 uV RMS Bipolar 20 uV RMS Unipolar Temperature Coefficients Gain 5 ppm of FSR oC max 5 C 40 C Offset 1 ppm of FSR oC max 5 C 40 C Voltage Range Software Set See Chart for details NOMINAL OUTPUT VOLTAGE VALUES 0 00000 V to 9 99996 V 0 00000 V to 4 99998 V 10 00000 V to 9 999924 V 5 00000 V to 4 999962 V Isolation voltage 500 Volts peak to peak max Normal Working voltage 250 V peak to peak Note Due to the packing density used in the module it is not to be used to isolate Mains voltages etc If it is used in a High voltage system always put it at the low voltage end of the circuit and please take all safety precautions Output Accuracy True 18 bit absolute accuracy at 200C ambient After 20 min warm up No missing Code OoC 500C Isolated Digital Output set via F30 F28 functions 4 Per DAC OFF state O 30 V on sink 5 mA at 0 5 V DAC output stable pulse output unstable signal TTL signal isolated to the DAC in question supply Low 1 DAC in transition Sinks 8 loads Isolated Digital Inputs 4 per DAC Input TTL compatible 0 1 mA logic 0 8 20 mA logic 1 Reverse diode protected current limited by 270 ohms resistor Normally the end is taken to 5 V and end to the TTL output Isolate
3. Note the 37 way plug must always be used to give the analog power inputs A test socket is supplied with each unit just to get it going It does not give isolated outputs but does power up the system Try to minimize the output current used to avoid heating up the module The DACs have four programmable signal ranges which may be selected via CAMAC Commands F30 Ax Bit sets The first two are Unipolar OV to 10V and OV to 5V if the output is being externally powered by floating supplies this may be referenced so as to be 0 to 10V or 0 to 10V etc It is coded in straight binary The second two ranges are 10V and 5V coded in 2 s Compliment binary Bit 18 MSB Other types of coding may wire linked see the circuit diagram for details As two separate multiturn trim components are used for each range there is no change in setup between ranges however due to the use of relays there is a delay time of up to 10 mS between goings from one output range to the other This delay is only present when going from Range to Range not value to value SPECIFICATION Analog Output Full 4 wire Sense Circuit Mode A 5 mA Output Current all Ranges Mode B 50 mA Output Current all Ranges standard Note one pair only of sense links must be made externally to the unit either via the Lemo or 37 way Cannon socket If not fitted uncontrolled voltages up 15 V may come from the outputs Setting Time ole 10V step 45 uS 1 2 LSB
4. 180pf 63V Ceramic 220pf 63V Ceramic 6 8 MFD 20 35V Tant Bead 6 8 MFD 20 35V Tant Bead 10 MFD 20 25V Tant Bead 1 10 MFD 20 25V Tant Bead 6 8 MFD 20 35V Tant Bead 6 8 MFD 20 35V Tant Bead 0 MFD 20 25V Tant Bead 0 MFD 1205 25V Tant Bead 5 MFD 20 16V Tant Bead 5 MFD 20 16V Tant Bead 0 MFD 1205 25V Tant Bead 47 MFD 20 6 3V Tant Bead 0 MFD 20 25V Tant Bead 0 MFD 20 25V Tant Bead 0 1 MFD 80 20 100V Mono Ceramic 0 1 MFD Ceramic C51 80 20 100V Mono 0 1 mfd 803 203 Ceramic Ceramic 4 2 100V Mono Note All ceramic Caps x330 pF are 2 63 Volts All ceramic Caps gt 330 pf but lt 2200 pF are 10 63V MCT Metal cased Tantalum Plugs PL1 37 Way Cannon D type plug with female screw lock retention PL2 37 Way Cannon D type plug with female screw lock retention Sockets SK3 4 Pole Lemo RA0304 mating part LEMO F0304NY SK4 4 Pole Lemo RA0304 N Relays RL1 RL2 Single Pole Change Over Farnell No 224 480 RL3 Siemens Part No V23026 A1001 B201 5V Coil RL4 RL5 Dual Pole Change Over Farnell No 177 825 RL6 Ormron G6H H 2100 5V Coil RL7 RL8 Single Pole Change Over Farnell No 224 480 RL9 Siemens Part No V23026 A1001 B201 RL10 RL11 Dual Pole Change Over Farnell No 177 825 RL12 Ormron G6H 2100 LED 1 off Red 0 2 inch clip Chassis Kit 1 off Benney CM 1 Kit long screen 1 off Jacking Screw I C Sockets 1 off
5. R13 560 R53 220 R14 560 R54 220 R15 270 44 R55 270 R16 270 R56 270 R17 560 R57 270 R18 560 R58 270 R19 K R59 270 R20 K R60 270 R21 470 2 R61 270 R22 470 R62 270 R23 80k 2 R63 270 R24 80K R64 270 R25 OK R65 270 R26 5K R66 270 R27 OK R67 270 R28 4 7K R68 270 R29 2 2K 5 R69 270 R30 K R70 270 R31 K R71 270 R32 5K R72 270 R33 270 R73 270 R34 270 R74 270 R35 270 R75 220 R36 270 R76 220 R37 270 R77 3 3K R38 270 R78 20K R39 270 R79 41 2K 0 25 Vishay R40 270 R80 41 2K 0 25 Vishay R81 41 2K 0 25 Vishay R101 1K 2 R82 2 15 0 25 Vishay R102 1K 2 R83 M ohm 5 film low TC R103 51 2 R84 SKO R104 68 2 R85 15K R105 68 2 R86 K 2 R106 47 2 5W or BZX70 C7V5 R87 K z R107 NOT FITTED R88 50 25 R108 NOT FITTED R89 68 2 R109 NOT FITTED R90 68 2 R 0 NOT FITTED R91 47 2 5W or BZX 70 C7V5 R 1 NOT FITTED R92 3 3K R112 NOT FITTED R93 20K 2 R 3 NOT FITTED R94 41 2K 0 25 Vishay R 4 NOT FITTED R95 41 2K 0 255 Vishay R 5 NOT FITTED R96 41 2K o 0 255 Vishay R116 NOT FITTED R97 2K 4 0 255 Vishay R117 100K ohms R98 M ohm 5 film low TC R118 820 R99 Not fitted R100 Not fitted Resistor Packs all common power unless noted RP1 1K 9 pin 4 RP8 2 2K 10 pin 4 RP2 1K 9 pin RP9 2 2K 10 pin RP3 1K 9 pin RP10 3 3K 10 pin RP4 10K 10 pin 1 RP11 3 3K 10 pin RP5 330 8 pin 4R s 2 RP12 560 9 pin RP6 330 8 pin 4R s 2 RP7 270 9 pin Var
6. has altered the state of the DAC A when the New D C value will be true and stable LAM is set on DAC B by an external Current 5mA into the opto input pair on PL2 pin 11 and 29 Equivalent circuit 1 6V Zener diode with 270 Ohm resistor LAM is set after a preset time 50us after a command which has altered the state of the DAC B when the New D C value will be true and stable Open as standard when closed makes both the Data Register 19 bits long Does not do anything extra to the DAC Open as standard when closed makes both Data Registers 20 bits long given LK3 also closed Open Special Function Expansion option not implemented This link adds in the high power 50mA Driver circuit on DAC A E This mode takes out the High power driver and restricts the available output current to 5mA it does improve the Noise performance and reduces the internal temperature rise in the module This Link adds in the High power 50mA Driver circuit on DAC B This mode takes out the High power driver and restricts the available output current to 5mA it does improve the noise performance and reduces the internal temperature rise in the module Each DAC has links on the internal 5V 18V 15V and 18V amp 15V power line these are for Test purposes and must normally be made 5V Power has been made available on pin 3 of PL1 and 2 it must be restricted to 50 mA max to avoid overheating Tabl
7. opto input Read back via FO A3 bit R10 F28 A10 Clear Set Enable front panel decrement of the data value in F30 A10 Set DAC A s data register counter via PL1 opto input Read back via F0 A3 bit R11 F28 A11 Clear DAC A Range control Clear 0 to 10V or 10V mode F30 All Set Set 0 to 5V or 5V range Read back via FO A3 bit R12 F28 A12 Clear Bit set DAC B Mode clear 0 10V or 10V mode F30 A12 Set 0 10V mode Straight Binary code Bit 18MSB Set 10V Range bit code 2 s complement Binary Read back via FO A3 10V R 13 set F28 A13 Clear Set Enable front panel increment of the F30 A13 Set data value in DAC B data register counter via PL2 opto input Read back via F0 A3 bit R 14 F28 A14 Clear Set Enable front panel decrement of the F30 A14 set data value in DAC B s data register counter via PL2 opto input Read back via F0 A3 bit 15 F28 A15 Clear DAC B range control bit clear 0 to 10V or 10V F30 A15 Set Set 0 to 5V or 5V range Read back via FO A3 bit 16 LK1 A C LK1 A B standard LK2 A C LK2 AB standard LK3 LK6 A C Standard LK7 A C Standard LK7 A B Note 670 LINK CHART See 670 Circuit Diagram LAM is set on DAC A by an external Current 5uA into the opto input pair on PL1 pin 11 and 29 Equivalent circuit 1 6V Zener diode with 270 Ohm Resistor LAM is set after a preset time 50us after command which
8. the adjustment potentiometer on each range interact and a strategy of halving the apparent areas on each adjustment together with a lot of patience should produce the correct result with repeated adjustments 10V range set VR8 VR16 to give 10 000000V then set 9 999924V via VR6 VR14 repeat until both are correct 5V range set VR7 VR15 to give 5 000000V then set VR5 VR13 to give 4 999962V repeat until both are correct Parts List 670 Page 1 PARTS LIST FOR HYTEC 670 MK V Integrated Circuits 1 SN74LS123N 4 40 SN74LS14N 2 SN74LS132N 2 41 SN74193N 10 3 SN74LS32N 2 42 SN74193N 4 SN7414N 5 43 SN74193N 5 SN7401N 1 44 SN74193N 6 SN74LS32N 45 SN74193N 7 SN74LS08N 2 46 N8234B si 8 N825100 P670 P8 1 1 5 47 SN75452N dL S S 9 SN74LS123N 48 HP2630 5 0 SN74LS123N 49 SN74193N 1 SN74LS123N 50 SN74193N 2 SN74LS375N 51 SN74193N 3 SN74LS279N L 52 SN74193N 4 SN74S188N P670 P114 S 53 SN74193N S S 5 SN745188N P670 P15 S 54 HP2630 S S 6 SN74S188N P670 P1 6 1 S 55 HP253 S S 7 SN74622N 56 HP253 8 SN74S244N 6 57 HP253 9 SN74S244N 58 HP253 20 SN74S244 59 HP253 21 F93L34B 2 60 HP253 22 F9334B 61 HP253 23 ILQ05 2 61 HP253 24 ILQ05 63 HP253 25 SN74LS132N 64 HP2630 26 DM8092N 1 65 HP2630 Dal SN74LS08N L 66 HP253 28 SN74LS622N 67 HP253 29 SN74LS244N 68 HP253 30 SN74LS244N 69 HP253 31 SN74LS244N 70 HP253 32 SN74S240N 1 71 HP253 33 HP2531 23 T2 HP253 34 HP2531 13 HP253 35 HP2531 74 HP
9. 10 when set to 1 enables the front panel increment of DAC LANG Bit 11 when set to 1 enables the front panel decrement of DAC VA Bit 12 is used by DAC A to control its output range 0 0V 10V or 10V 1 OV 5V or 5V See table for detail Bit 13 is used DAC B to control Unipolar or Bipolar operation Oo 0V 10V or OV 5V 1 10V or 5V Bit 14 when set to 1 enables the front panel increment of DAC EBs Bit 15 when set to 1 enables the front panel decrement of DAC Biss Bit 16 is used by DAC B to control its output range O TS O 10V or 10V 1 0 5V or 5V operation See table for details F2 F2 F2 F8 F8 F8 F9 F9 F9 F9 F24 F24 F24 F25 F25 F25 F25 F26 F26 F26 AO Al A3 AO Al ALS AO Al A2 A15 AO A15 AO Al A2 A3 AO Al A15 AO Al A2 A3 AO Al A15 Read and Clear DAC A Counting Registers 18 bits of data gives X and Q Note Data field may be extended to 20 bits via LK3 and 4 Read and Clear DAC B Counting Registers 18 bits of data gives X and Q Note Data field may be extended to 20 bits via LK3 and 4 Read and Clear DAC A Counting Registers also clear DAC B LAM gives X and Q Test LAM Q DAC A LAM set and enabled gives X Test LAM Q DAC A LAM set and enabled gives X Test all LAM s in the module Q DAC A
10. 253 36 HP2531 75 HP2630 37 SN74LS14N 76 AD1139K 2 38 SN74LS14N 77 AD1139K 39 SN74LS14N 78 BUF634 on special PCB 79 OP 07C 80 BUF634 on special PCB 81 OP 07C 82 SN74S188N S S socketed S S x AD1139J for 17 bit units absolute accuracy Normal 18 bits Voltage Regulations VReg 1 uA7818C VReg 2 uA7918C VReg 3 uA7818C All mounted on the Rear panel VReg 4 uA7918C With double mica insulator Kits VReg 5 uA7815C VReg 6 uA79L15C VReg 7 LM2931A T5 0 VReg 8 uA7815C VReg 9 uA79L15C VReg 10 LM2931A T5 0 Transistors TR1 ZTX314 1 TR2 2N3903 TR3 2N3903 TR4 2N3903 TRS 2N3903 TR6 2N3903 TR7 2N3903 Diodes D1 IN5401 1 D17 IN4004 D2 BZY88C3V0 1 D18 IN914 D3 IN914 7 D19 IN4004 D4 IN914 D20 IN914 D5 IN914 D21 IN4004 D6 IN914 D22 IN914 D7 HP5082 2811 4 D23 IS12 D8 HP5082 2811 D24 18512 D9 HP5082 2811 D25 1812 D10 HP5082 2811 4 D26 185121 D11 IN4004 D27 18121 D12 IN4004 fit backwards D28 18121 D13 IN4004 D29 IN4004 D14 IN4004 fit backwards D30 IN4148 D15 IN4004 D31 IN4148 D16 IN914 D32 IN4148 fit back to front not as shown on the ident screen Note 1N4148 or 1N914 or 1N916 may be used in place of each other Resistors all Mullard MFR25 1 50ppm Metal Film R1 22K 1 R41 270 R2 10K 5 R42 270 R3 220 6 R43 270 R4 27K 1 R44 270 R5 15K 5 R45 270 R6 220 R46 270 R7 1K 8 R4T 270 R8 1K R48 270 R9 1K R49 270 R10 1K R50 270 R11 560 6 R51 270 R12 560 R52 270
11. 28 pin turned pin low profile IC8 4 off 16 pin turned pin low profile IC14 16 and IC82 Heat Sink 2 off Hytec special of Elantec Power Buffers Fuses FS1 1A FS2 1A FS3 3A FS4 0 25A 0 5A FS5 0 25A 0 5A FS6 0 25A 0 5A FSi 0 25A 0 5A Fuse Holders 6 off normal 6 off IC socket type P C B 1 off 670 issue 5 Note There are wire mods to this PCB under IC s
12. able both A and B LAM s gives X F27 AO Test the DAC A LAM before enable latch Q 1 if LAM set gives X F27 Al Test the DAC B LAM before enable latch Q 1 if LAM set gives X F27 A2 Test the DAC A Output is stable Q 1 if it is gives Oe F27 A3 Test the DAC B Output is stable Q 1 if it is gives Ib A NOTE Hytec bit set commands on the 670 are controlled by individual F30 set and F28 clear commands via sub address each command gives the X response F30 Ax set that bit only ie F30 A6 sets bit 6 which Reads back via R7 F28 Ax clears that bit only ie F28 A6 clears bit set bit 6 and read back R7 All bits are clear simultaneously by the clear commands F9 A2 and the general clear Z S2 Also cleared by the power up Clear system All F28 amp F30 sub address codes 0 15 give the X response F28 A0 A3 Clear DAC A Bit set opto outputs via PL1 F30 A0 3 Set Read back via FO A3 A0 Bit 1 A3 Bit R4 when set ie The sub address number plus 1 gives FO A3 Read back bit number F28 A4 Ab Clear DAC B Bit set opto output via PL2 Read back via F30 A4 A7 Set FO A3 A4 Bit R5 A7 Bit R8 when set F28 A8 Clear Bit set DAC A Mode Clear Unipolar F30 A8 Set Bipolar Read back bit R9 Unipolar coded in straight binary bit 18 MSB 10V Range coded 2 s complement Binary F28 A9 Clear Front panel increment of the data value in F30 A9 Set DAC A s data Register Counter via PL1
13. d Digital Control Inputs Increment DAC if enabled Decrement DAC if enabled Set DAC LAM if selected by wire link option 0 1 mA logic 0 8 20 mA logic 1 D TYPE PLUG Input Bit 4 I HO 19 37 O Ne Input Bit 4 I Input Bit 3 1 10 18 36 O Input Bit 3 I Input Bit 2 I O0 17 35 O Input Bit 2 I Input Bit 1 I 0 16 34 O Input Bit 1 I Bit A3 Bit 4 Open Coll O P 1 OLS 33 O Bit A3 Bit 4 output emitter I Bit A2 Bit 3 Open Col1 0 P t O 14 32 O Bit A2 Bit 3 output emitter I Bit Al Bit 2 Open Col1 0 P TIG ka 31 O Bit Al Bit 2 output emitter I Bit AO Bit 1 Open Col1 0 P t 0 12 30 O Bit AO Bit 1 output emitter I LAM input I ALO N 29 O LAM input I Decrement Data input I 0 10 28 O Decrement Data Input I Increment Data input I 10 9 27 0 Increment Data Input I Isolated Analog Earth Ret o 8 26 O Data valid open Co11 0 P Ret P8 CAMAC 24V Output Non Iso O 7 25 O 24V Power input 21 30V Ret P22 Camac OV Output Non Iso o 6 24 O Isolated Analog Earth Camac 24V Output Non Iso O C5 23 O 124V Power input 21 30V Ret P4 Isolated Analog Earth O 4 22 O Isolated Analog Earth Isolated 5V Line ret P22 0 3 21 O Main Analog power sense return Main Analog power output 0 2 20 O Main Analog power sense return Main Analog power output 10 AS VIEWED FROM FRONT OF MODULE MK2 up
14. e Programme Control DAC A DAC B Output Range Bit Set Bit Set F30 Ax Sets A8 All A12 A15 F28 Ax Clears A8 A11 A12 A15 0 to 10 V 0 0 0 0 0 to 5V 0 1 0 1 10V 1 0 1 0 5V 1 I 1 1 Read back bit Via FO A3 R9 R12 R13 R16 Adjustments DAC A Top of PCB VR J 0 10V Gain PCB LAYOUT PATTERN SET UP VOLTAGES VR 3 0 10V Offset A B A B V 2 O 5V Gain VR1 VR2 9 999962 V 4 999981 V VR 4 0 5V Offset VR3 VR4 0 000000 V 0 000000 V VR 6 10V Gain VR5 VR6 4 999962 V 9 999924 V VR 8 410V Offset VR7 VR8 5 000000 V 10 000000 V VR 5 5 V Gain VR 7 45v Offset Adjustments DAC B Bottom of PCB VR 9 0 10V Gain PCB LAYOUT PATTERN SET UP VOLTAGE VR 1 0 10V Offset A B A B VR 0 0 5V Gain VR9 VR10 9 999962 V 4 999981 V VR 12 0 5V Offset VR11 VR12 0 000000 V 0 000000 V VR 4 10 V Gain VR13 VR14 4 999962 V 9 999924 V VR 6 10 Vv Offset VR15 VR16 5 000000 V 10 000000 V VR iS a A i Gain VR 5 N offset Adjustment Procedures First let the module warm up for 20 minutes into an equivalent to normal operational load Basically the DAC to be adjusted is switched between 0 and full scale by software and the adjustments are made as follows 0 10V range set VR3 VR11 to give 0 000000V then set 9 999962V via VR1 VR9 repeat until both are correct 0 5V range set VR4 VR12 to give 0 000000V then set 4 999981V via VR2 VR10 repeat until both are correct 10V range and 5V range it will be found the
15. es and power regulators so as to make them totally separate be truly Isolated the module needs to be powered by two transformer isolated 21 30 Volt stabilised power supplies connected via the two 37 way Cannon sockets However the CAMAC power supplies may be selected if desired at the loss of isolation The data for the DAC is stored in to counting registers formed from parallel data entry up down synchronous counters These counting registers may be loaded incremented or decremented and read via CAMAC Command In addition four optically isolated digital inputs allow either register to be incremented or decremented via the front panel Each time the data stored in the DAC data register is altered an automatic micro sequence is started that transfers the data from the register into the main DAC in such a way as to minimise transmission glitches from the analog output This circuit also triggers a monostable multivibrator that is used to drive an opto isolator to provide a digital output signal for each DAC for the whole time the Analog value from the DAC is in transition changing from one value to the next This is very useful when testing ADCs to know when the output is not True H he data from the data registers is passed through opto isolators and fed into the two separate hybrid laser trimmed DAC chips which contain data latches and current to voltage amplifiers The Analogue output is passed in voltage for
16. iable Resistors VR1 50K Muliturn BOURNS VR2 50K n BOURNS VR3 50K m BOURNS VR4 50K n BOURNS VR5 50K BOURNS VR6 50K x BOURNS VR7 50K BOURNS VR8 50K BOURNS VR9 50K BOURNS VR10 50K m BOURNS VR11 50K n BOURNS VR12 50K BOURNS VR13 50K n BOURNS VR14 50K BOURNS VR15 50K m BOURNS VR16 50K BOURNS Capacitors Cl 10uF 35V M C T 1 C2 47uF 20V M C T 4 G3 22uF 6V M C T 2 C4 22uF 6V M C T C5 330pf 63V Ceramic 3 C6 56pf 63V Ceramic 1 Cy 2 2nF 10 63V Ceramic 6 C8 2 2nF 63V Ceramic Co 2 2nF 63V Ceramic C10 2 2nF 63V Ceramic C11 2 2nF 63V Ceramic C12 2 2nF 63V Ceramic C25 5 MFD 20 16V Tant Bead C26 15 MFD 20 16V Tant Bead C27 0 MFD 20 25V Tant Bead C28 47 MFD 20 6 3V Tant Bead C29 10 MFD 20 25V Tant Bead C30 10 MFD 20 25V Tant Bead C31 0 1 MFD 80 20 100V Mono Ceramic C32 0 1 MFD 80 20 100V Mono Ceramic C33 10 MFD 203 25V Tant Bead C34 10 MFD 20 25V Tant Bead C35 0 1 MFD 80 20 100v Mono Ceramic c36 0 1 MFD 80 20 100V Mono Ceramic C49 10 MFD 20 C50 10 MFD 20 25V Tant Bead C52 0 1 MFD 80 20 100V Mono 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 3262 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C37 C38 C39 C43 C44 C45 C46 C47 C48 25V Tant Bead 16 330pf 63V Ceramic 330pf 63V Ceramic 820pf 10 63V Ceramic 820pf 63V Ceramic 180pf 63V Ceramic 220pf 63V Ceramic
17. m from the DAC outputs into a precision power amplifier working at unity gain This has been included so that a fully sensing four wire output system can be provided together with allowing high output currents without self heating effects on the DACs As can readily be seen to get near 18 bit performance over any reasonable length of output lines a fully sensing circuit is necessary Consider the case when used on 10V full scale 1 LSB bit is about 38 uV A 30 m ohms wire and connector resistance with a 5 mA load would give a 150 uV error 4 bits To help get over these problems The output amplifier has two stages The first is a very temperature stable and low noise high gain operational amplifier within the DAC chip with a 5mA drive capability The second is a high power unity gain power driver A wire link allows the first amplifier alone to be used for low current work and the power buffer together with the precision amplifier for high power work In either case a fully symmetrical differential amplifier circuit is used Precision temperature matched resistor networks inside the DAC chip have been employed so as to give peak performance The power output driver amplifier is capable of providing 50mA There are two output options where sense links must be fitted but only one set at a time i e if Lemo output is used fit links at the far end of the Lemo cable if the 37 way Cannon output is chosen then the links will be at its far end
18. or B LAM set gives X Clear DAC A Counting Register gives X Clear DAC B Counting Register gives X Clear all 16 bit set lines to zero gives X Clear both DAC A and B Counting Registers Clear and disable all LAM s same action as ZS2 on Dataway gives X Clear DAC A LAM gives X Clear both DAC A and B IAM s gives X Overwrite the DAC A Counting Register 18 bit data field Note Data field may be 20 bits if LK3 and LK4 are made gives X and Q Overwrite the DAC B Counting Register 18 bit data field Note Data field may be 20 bits if LK3 and IK4 are made gives X and Q Overwrite the DAC A Counting Register and clear the DAC A LAM gives X and Q Overwrite the DAC B Counting Register and clear the DAC B LAM gives X and Q Disable DAC A LAM gives X Disable B LAM gives X Disable DAC A and B LAM gives X Increment the DAC A Counting Register by 1 independent of the state of the bit set enable gives X and Q Increment the DAC B Counting Register by 1 independent of the state of the bit set enable gives X and Q Decrement the DAC A Counting Register by 1 independent of the state of the bit set enable gives X and Q Decrement the DAC B Counting Register by 1 independent of the state of the bit set enable gives X and Q Enable DAC A LAM gives X Enable DAC B LAM gives X En
19. side down Notes I shows a current input paired to I normally driven by 10mA at 3V 21 30V The floating stabilised input voltage range Open Coll Open Collector transistor collector NPN transistor PX PL1 2 Pin Number X O P Output Ret Return Non Iso Non Isolated FO FO FO FO AO Al A2 A3 670 MK2 FUNCTION CODES Read DAC A Counting Register gives 18 bits of data gives X and Q Note if LK3 and LK4 are made then 20 bit data is possible Read the DAC B Counting Register gives 18 bits of data gives X and Q Read the opto isolated digital data inputs data field 8 bits Bits 1 4 are from DAC A input socket Bits 5 8 are from DAC B input socket Both sockets are 37 way Cannons gives X See the 670 Control data Chart for both FO A2 and FO A3 Read the state of the bit set control lines 16 bit data field gives X Note Data Read back bits are Sub address plus 1 Bits 1 4 are opto isolated data output lines for DAC A via PL1 Bits 5 8 are opto isolated data output lines for DAC B via PL2 Bits 9 12 are control bits for DAC A See F28 and F30 for details Bits 13 16 are control bits for DAC B See F28 and F30 for details Bits 1 4 may be used as desired by the program Bits 5 8 may be used as desired by the program Bit 9 is used by DAC Ato control Unipolar or Bipolar operation 0 Unipolar 1 Bipolar See table for detail Bit
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