EDP-CM-LPC1113 CPU Module User Manual
Contents
1. 3 4 5 6 8 3V3 C501 1 100nF 509 C510 100nF 10uF 10V SGND A SGND 501 4 TX EN 50 000MHZ XO53050US ND TXDO PII ENET TXDI 9 ENET RXD0 3V3 10 RXDI 504 14 RX ER R505 6506 502 3V3 lt bk ETH N X 100nF 8 CRS ETH RX P E 1 16 MDC ETH TX N SGNDA P117 ETH TX P 15 REF CLK 8507 0503 ETH LNK LED il 100nF LEDs Active Low 508 506 507 10uF 10V 100nF C 1 DP83848CVV SGND SGND 3V3 3V3 8514 1501 10K 1 CANHO 5 SD CS SD I 501 SPI MOSIL 3 Jumper 4 CANO TX LOCAL MH adici sc 1 6 RX LOCAL 512 BOND SPI_MISO1 7 1206 8 CANLO ST2S008V1A 513 SN65HVD230D SGND Checked By Title Hitex UK Ltd Ethernet CAN SD Sir William Lyons Road hitex mum Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPCx B Coventry DEVELOPMENT TOOLS Date 19 03 2010 c Hitex UK Ltd Sheet5 of5 File DAPCB Designs DXP EDP CM LPCx Rev2. 3 4 5 6 7 8 3V3 c301 c302 100nF 100nF SGND 43V3 305 5 RESIN 5 PO 10 PIO2 0 P3 25 PIOO 1 P3 2578001 42 UNA A gt P27 P102 1 28 PIO0 2 E P2 S PIO2 2 PO A PIOO 3 im 2002 3 CNTRL DC SCL j 20 PIO2 4 CNTRL DC SDA P0 22 PIO2 5 P2 6 EVGI GPIO42 EVM9 GPIOSS PO 19 PIO2 7 297100 8 P2 0 02 8 Tpo wo 01 PIO0 9 P2 3 PIO2 9 TCK SWCLK P2 4 PIO2 10 TDI PO 1U PIO2 11 IMS SWDIO PIOI 0 36 Pl 19 PIO3 0 IDO SWO T PI 20 PIO3 1 TRST PI 22 PIO3 2 TMS SWDIO PIOI 3 _ Pl 23 PIO3 3 PO 23 PIOT 4 4 EVMS GPIO47 PO 6 PO 7 21 PIOI 8 XTAL MUST BE POSITIONED CLOSE TO BOTH U201 AND U301 P0 S PIOI 9 Pl IS PIOI 10 30 PIO1 11 LPCI343FBD48 Checked By muc Hitex UK Lid Sir William Lyons Road itex Size Number Revision University of Warwick Science Park h Approved By A3 EDP CM LPC B DEVELOPMENT TOOLS Date 19 03 2010 Hitex UK Ltd Sheet of5 File DAPCB Designs DXP EDP CM LPCx Rev BILPC1343 SchDoc Author A Davison 3 4 5 6 8 1 2 3 4 5 6 7 8 AN3 MOTOR MOTOR P2H ASCI TX TTL EVM6 GPIO49 12408 E m olderlink 409 Wr P425 P433 2 2 2 26 2 E
3. Only populate with P2_3 PIO2 9 LPC1768 and LPC2368 P2 5 PIO2 2 P26 A 2 7702 1 2 R211 av Eo POSU 2 GPIO4 UR DER GPIO6 MCIDAT2 GPIO8 MCIDAT3 MESE Hadrz P3 25 PIOO LPC1768 SGND EVGI GPIO42 3V3 3V3 A 209 R204 P201 TRST TRST TDI TDI TMS SWDIO TMS SWDIO TCK SWCLK TCK SWCLI RICK RICK TDO SWO TDO SWO FRESIN FRESIN C201 E penn 2X10 Header 22pF R205 JTAG ICX8V TIA 32 768kHz 32 768KHz C202 SGNH 5 SGND SGND 22pF Only with Only Populate for LPC1768 LPC2368 Or LPC2368 CSTCEI2M0GSS NE LY 12MHz TMS SWDIO TCK SWCLK TDO SWO TDI RESIN Header 5X2 LPC2368FBD100 LPC1768FBD100 SGND MCPI20T 300 TT 43V3 203 LUN E NN jim c210 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF SGND Checked By Title Hitex UK Ltd LPC2368 and JTAG Sir William Lyons Road Size Number Revision University of Warwick Science Park h Approved By EDP CM LPCx B Colby DEVELOPMENT TOOLS Date 19 03 2010 c Hitex UK Ltd Sheei2 of5 File DAPCB Designs DXP EDP CM LPCx Rev BILPC2368 SchDoc Author A Davison 2 3 4 5 6 7 8
4. PIO3 3 HRI JP413 2 1 MOTORH1_ENC1 413 2 3 Default 4 1 435 2 3 GPIO12 MCI JP435 2 1 Default PIO3 5 JP433 2 3 GPIO2 MCI DATO JP433 2 1 Default Not Connected Options As the circuit board for the LPC1113 is also used for higher pin count MCU such as LPC2368 and LPC1768 there are some configurations options that are not used These are shown on the circuit schematic but do not have any relevance for this LPC1113 module as the pins are not connected These jumper options are detailed below JP401 2 1 Default AN2 JP401 2 3 AN10 JP402 2 1 Default AN1 402 2 3 AN9 404 2 1 Default AN5 404 2 3 AN13 408 2 1 Default AN3 408 2 4 AN11 408 2 3 CPU_DACOO_GPIO17 414 2 1 MOTORH2_ENC2 Electrocomponents plc Page 15 EDP CM LPC1113 CPU Module 414 2 3 Default 1 415 2 1 JP415 2 3 Default MOTORP1H JP416 2 1 JP416 2 3 Default MOTORP1L 419 2 1 CANO_TX 419 2 4 Default CANO_TX_LOCAL 419 2 3 I2C GENO SDA JP420 2 1 RX JP420 2 4 Default LOCAL 420 2 3 I2C GENO SCL JP423 2 1 Default IRQ GPIO16 CNTRL I2C INT JP423 2 3 GPIO18 I2C GENO INT JP424 2 1 Default
5. 5 GPIO47 EVM6 GPIO49 7 GPIO51 EVM8 GPIO53 9 GPIO55 GPIOO GPIO1 GPIO2 MCIDATO GPIO7 125 GPIO9 125 WS MCICLK GPIO12 MCICMD GPIO14 MCIPWR MOTORPOH Electrocomponents plc Page 6 EDP CM LPC1113 CPU Module MOTORPOL MOTORHO ENCO MOTORH1 MOTORP2H MOTORP2L EMG TRAP Local User LED1 2 3 Alphabetical Listing of MCU Pins Pin Alphabetic Listing of Available 1 0 3 RESET PIOO_O 4 PIOO_1 CLKOUT CT32BO_MAT2 10 PIOO 2 SSELO CT16BO CAPO 14 3 15 PIOO 4 SCL 16 PIOO 5 SDA 22 PIOO 6 SCKO 23 PIOO 7 8 5 27 PIOO 8 MISOO CT16BO MATO 40 PIO1 4 AD5 CT32B1 MAT3 WAKEUP 45 PIO1 5 SRTS CT32BO 46 PIO1 6 RXD CT32BO MATO 47 PIO1 7 TXD CT32BO MAT1 9 PIO1 8 CT16B1 CAPO 17 PIO1 9 CT16B1 MATO 30 PIO1 10 AD6 CT16B1 MAT1 42 PIO1 11 AD7 2 PIO2 O sDTR SSEL1 13 PIO2 1 s8DSR SCK1 26 PIO2 2 8 DCD MISO1 38 PIO2 3 SRI MOSI1 19 PIO2 4 20 PIO2 5 1 PIO2 6 11 PIO2 7 12 PIO2 8 24 PIO2 9 25 PIO2 10 31 PIO2 11 SCKO 36 _0 0 37 PIO3 1 4DSR 43 2 4DCD 48 3 tRI 18 4 21 5 29 SWCLK PIOO 10 5 16 MA
6. 59 P602 15 GPIO39 AD8 60 P601 17 12 GENO SCL 7 amp 8 P603 29 2 GENO SDA 5 amp 6 P603 28 12 GEN1 SCL 119 P602 45 2 GEN1 SDA 117 P602 44 IRQ GPIO16 CNTRL I2C INT 37 P603 11 IRQ GPIO18 I2C GENO INT 39 P603 10 GPIO20 I2C GEN1 INT 41 P603 9 GPIO22 I2C INT 43 P602 7 MOTOR TCO FB 122 P601 48 MOTORHO ENCO 116 P601 45 MOTORH1_ENC1 118 P601 46 MOTORH2_ENC2 120 P601 47 MOTORPOH 102 P601 38 MOTORPOL 100 P601 37 MOTORP1H 106 P601 40 MOTORP1L 104 P601 39 MOTORP2H 110 P601 42 MOTORP2L 108 P601 41 MOTORPWM 112 P601 43 P603 46 P603 46 P603 46 P603 46 SPI SSC 05 55 101 P602 36 SPI SSC CLK 98 P601 36 Electrocomponents plc Page 10 EDP CM LPC1113 CPU Module SPI SSC MRST MISO 94 601 34 SPI 55 MTSR MOSI 96 P601 35 P603 39 P603 38 P603 37 P603 36 P601 P601 P603 43 P603 43 P603 43 Note This spread sheet is derived from the Pin Allocation Spreadsheet for this CPU Module The user manual for the base board also contains details of the back plane signals and the pin outs 2 5 Mapping Aid R101 417 IMOTORP2H 10 PIOO_2 SSELO CT16B0_CAPO SG R102 gt A m ESET VCC CM 6 EVGO GPIO40 JP430 EVG1 GPIO42
7. Default User LED1 Selecting JP406 position 2 3 allows use of the on board user led LED1 0401 Note EVGO GPIO4O is also available on JP407 PIO1 10 PIOO 2 SSELO CT16BO CAPO JP417 2 1 MOTORP2H JP417 2 3 Default Electrocomponents plc Page 12 EDP CM LPC1113 CPU Module RS PIOO 3 PIOO 6 SCKO JP431 2 3 5 1 RX TTL JP438 2 3 JP438 2 1 Default JP431 2 1 Default 8 MISOO CT16BO MATO JP418 2 1 MOTORP2L JP418 2 3 Default Port PIO1 Options 1 4 AD5 CT32B1 MAT3 WAKEUP JP403 2 1 Default ANO 403 2 3 AN8 1 6 RXD CT32BO MATO JP440 2 1 Default ASCO RX TTL JP440 2 4 440 2 3 AN14 Position 2 1 is the main RS232 UART channel Incoming logic level receive traffic is routed from the Communication Module PIO1 7 TXD CT32B0 1 JP439 2 1 Default ASCO TX TTL JP439 2 4 AN7 JP439 2 3 AN15 Position 2 1 is the main RS232 UART channel Outgoing logic level transmit traffic is routed to the Communication Module where it is translated into RS232 RS485 logic levels 1 8 CT16B1 CAPO 1 434 2 3 GPIO14 MCI PWR 1 434 2 1 Default PIO1_9 CT16B1_MATO 437 2 3 GPIO9 125 RX WS JP437 2 1 Default EVM1_GPI023 437 2 4 CPU DACOO GPIO17 Note CPU DACOO GPI
8. CPU DACOO GPIO17 A JP429 2 EVG2 GPIO44 CPU DACO1 GPIO19 d JP428 EVG17 GPIO65 JP418 IMOTORP2L 27 00 8 500 1680 MATO EVG18 GPIO66 JP411 EMG TRAP 38 P1O2_3 RI MOSI1 EVG11 GPIO59 JP410 lANo gt t 40 PIO1 4 ADS CT3281 MAT3 WAKEUP Fon 405 42 1 11 AD7 AN12 440 46 6 2 0 MATO AN14 3 5 0 TX TTL Jp439 7 PIO1 7 TXD CT3280 1 URSUS AN15 Jp409 IMOTORPOH a 26 B6 0 4DTR EVG9 GPIO57 24 __ 9 MOTORPOL 43 2 EVG12 GPIO60 25 2 10 26 P102_2 DCD MISO1 EVG3 GPIO46 EVG4 GPIO48 8 30 PIO1 10 AD6 CT16B1 1 2 P102_0 DTR SSEL1 111 37 PIO3 1 05 EVG10 GPIO58 31 02 11 5 Jp413 MOTORH1 hs EVG13_GPI061 EVMe GPIO49 21 Joss Gploz MCIDATO JP434 14 00 3 17 PIO1 9 CT16B1 MATO GPIO45 PIO1 8 CT16B1 CAPO GPIO14 MCIPWR JP435 45 P101_5 RTS CT32B0_CAPO EVM3 GPIO43 18 PIO3 4 y GPIO12 MCICMD JP436 EVM2 GPIO41 CAPADC 11 PIO2 7 GPIO10 MCICLK 20 02 5 no USB functionality 19 02 4 no US
9. 5 1 RX TTL 1 424 2 3 JP425 2 1 Default 5 1 TX TTL 1 425 2 3 TX JP427 2 1 MOTOR TCO FB JP427 2 3 Default User LEDO 4 Zero Ohm Links CAN Load Resistor JP501 This link when inserted includes a 120 ohm resistor across CANHO and CANLO The default is connected This option is irrelevant as the LPC1113 does not a CAN peripheral This jumper is provided for the LPC1768 LPC2368 variants of the Command Module which have a CAN transceiver fitted REF R101 This zero ohm link when inserted provides a 3 3V reference for the EDP platform The 3 3V used is the local supply voltage derived from a local voltage regulator This link should be used in the absence of a 3 3V voltage reference voltage provided by the Analogue Module when fitted The default position is not connected AGND amp VAGND R102 This link when inserted provides a way of connecting the VAGND to the SGND This is the default position The two grounds alternatively can be connected to each other on the analogue module or on the base board Electrocomponents plc Page 16 EDP CM LPC1113 CPU Module RS 5 Software Support The NXP Command Module for the RS EDP platform is supported by all of the necessary software drivers to make driving of the platform very easy All the low level support for the devices controlled I2C for example have been written as well as a te
10. GPIO1 EVG2 GPIO44 EVMO GPIO21 P405 422 P430 P438 2 30PIOL 11 2 oldertink 8 11 2 isolderlink 2 olderlink AA Solderlink m m 27 m m ANI2 e 14 GPIO62 m 7 GPIOS4 em CPU GPIO17 m GPIO7 DSRX CLK EVGO GPIO40 MOTOR PIH IRQ GPIOI6 CNTRL RC INT 8 GPIO53 ASCO TX TTL n 2 gt F 1P439 Wir406 415 423 P431 olderlink 2 2 2 2 25 00 2 misolderlink e 2 ZEN 2 Misolderink mamo 6 2 olderlink m 3 Eun 401 lo E m LEDI Q401 e EVGIS GPIO63 em IRQ GPIOI8 DC GENO INT em ASCI RX TIL m ANIS N 402 EVGS GPIOSO 30R MOTOR PIL ASCI TTL EVM7 GPIOSI ASCO RX TTL E E ii Es F JP440 jia 2 4 Solderlink Pl 18 PIO1 10 2 H1 4 GPIO40 26 2 p29 2 P2 0 1028 2 m PO 3 PIO1 6 ANO ER Solderlink olderlink NALED YELLOW m Ld m EVG8_GPIOS6 m EVG16_GPIO64 m EVM10_GPIO68_ASCO CTS em ASCI TX TTL em ANI4 SGND Checked By Title Hitex UK Lid Link Options Sir William Lyons Road hitex Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPC B DEVELOPMENT TOOLS Date 19 03 2010 c Hitex UK Ltd Sheet4 of5 File DAPCB Designs DXP EDP CM LPCx Rev BUumpers SchDoc Author A Davison 1 2 3 4 5 6 7 8
11. GPIO63 84 P601 29 EVG16 4 85 P602 28 EVG17 GPIO65 86 P601 30 EVG18 GPIO66 87 P602 29 EVG19 GPIO67 88 P601 31 EVG20 069 ASCO RTS 92 P601 33 EVMO GPIO21 42 P601 8 EVM1 GPIO23 44 P601 9 EVM2 41 CAPADC 62 P601 18 EVM3 GPIO43 64 P601 19 EVM4_GPI045 66 P601 20 EVM5 47 68 601 21 EVM6 49 70 601 22 Electrocomponents plc Page 9 EDP CM LPC1113 CPU Module EVM7 GPIO51 72 P601 23 EVM8_GPIO53 74 P601 24 EVM9_GPIO55 76 P601 25 EVM10_GPIO68_ASCO_CTS 90 P601 32 GPIOO 21 603 13 GPIO1 22 P603 15 GPIO2 MCI DATO 23 P603 14 GPIO3 24 P603 16 GPIO4 MCI DAT1 25 P603 17 GPIOS 125 TX WS 26 P603 19 GPIO6 MCI DAT2 27 P603 18 GPIO7 125 RX CLK 28 P603 20 GPIO8 MCI DAT3 29 P603 22 GPIO9 125 RX WS 30 P603 21 GPIO10 MCI CLK 31 P603 23 GPIO11 125 RX SDA 32 P603 24 GPIO12 MCI CMD 33 GPIO13 125 TX CLK 34 P603 25 14 MCI PWR 35 P603 12 GPIO15 125 TX SDA 36 P603 8 24 AD7 45 P602 8 GPIO25 AD15 46 P601 10 26 AD6 47 P602 9 GPIO27 AD14 48 P601 11 GPIO28 AD5 49 P602 10 GPIO29 AD13 50 P601 12 GPIO30 4 51 602 11 GPIO31 ADI2 52 P601 13 GPIO32 AD3 53 P602 12 GPIO33 AD11 54 P601 14 GPIO34 55 P602 13 GPIO35 AD10 56 P601 15 GPIO36_AD1 57 P602 14 GPIO37 AD9 58 P601 16 GPIO38
12. 2 2 link options EVGO 40 2 Link options User LED1 8 VDDIO 20 PIO2 5 19 02 4 5 VSSIO 30 PIO1 10 AD6 CT16B1 MAT1 3 link options EVG5 GPIO50 3 link options EVG8_GPIO56 3 link options EVGO GPIO40 36 _0 0 2 link options MOTORPOH 2 link options EVG9 GPIO57 37 PIO3_1 DSR 2 link options MOTORHO_ENCO 2 link options EVG10_GPIO58 38 P1O2_3 RI MOSI1 2 link options EMG_TRAP 2 link options EVG11_GPIO59 43 PIO3_2 DCD 2 link options MOTORPOL 2 link options EVG12 GPIO60 48 PIO3_3 RI 2 link options MOTORH1_ENC1 2 link options EVG13 GPIO61 41 VSSIO 44 VDDCORE 45 PIO1 5 SRTS CT32BO EVM5_GPI047 10 PIOO 2 SSELO CT16BO CAPO 2 link options MOTORP2H 2 link options EVG17 GPIO65 27 PIOO 8 MISOO CT16BO MATO 2 link options MOTORP2L 2 link options EVG18 GPIO66 Electrocomponents plc Page 4 EDP CM LPC1113 CPU Module 2 PIO2 O SDTR SSEL1 2 link options GPIOO 2 link options EVG6 GPIO52 31 PIO2 11 SCKO 2 link options GPIO1 2 link options EVG7 GPIO54 13 PIO2_1 HDSR SCK1 2 link options ASC1_TX_TTL_ASCO_DTR 2 link options CAN1_RX 26 PI02_2 4DCD MISO1 2 link option EVG4_GPI048 2 link option EVG19 GPIO67 25 2 10 2 link option CPU DACO1 019 2 link option EVG3 046 24 PIO2 9 2 link option CPU DACOO GPIO17 2 link option EVG2 44 23 PIOO 7 8 5 EVM9_GPIO55 22 PIOO 6 SC
13. 3 Pl 19 2030 2 PL28 PIOO 2 2 P2 8 2 22 1025 2 waolderlink H m CPUDACOO GPIO17 m EVG9 GPIOS7 em EVGI7 GPIO65 em CANI TX em GPIO2 MCIDATO AN2 MOTOR H0 ENCO MOTOR P2L ASCI TX TTL 5 DTR EVM4 GPIO45 P401 410 Was P426 P434 2 2 2 2 Misolderlink c cec SEE olderlink PO 21 PIOLE 2 milsolderlink m m m m em EVGIO GPIOSS m EVGIS GPIO66 em CANI RX m GPIOI4 MCIPWR ANI EMG TRP CANO RX MOTOR TCO FB EVM3 GPIO43 AA 3V3 P402 Mirai 427 435 2 2 2 PO 24 2 LS 0 a oe E 0 2 RX LOCAL P2 6 2 ms Bene e 20 PIO2 4 2 solderlink P 419 m lo m m AN9 em 11 GPIOS9 Solderlink em 12C GENO SDA m LEDO 0402 em GPIOI2 MCICMD IE BC848C R404 ANO MOTOR POL EVG4 GPIO48 EVM2 GPIO41 CAPADC 2 23 01 4 2 03 22003 2 2 1 TX LOCAL P2 5 PIO2 2 2 pied 19 P102 7 2 KEA Solderlink ToO ere Oe ooo olderlink Solderlink E Solderlink ALED YELLOW E m ANS m EVGI2 GPIO60 m 12C GENO SCL m EVGI9 GPIO67 em MCICLK SGND ANS MOTOR ENCI GPIO0 EVG3 GPIO46 EVMI GPIO23 yu P ij ta 437 P404 Wir P421 P429 olderlink E 2 31 23 103 3 2 PO 10 1020 2 P2 4 PIO2 10 2 S PIO1 9 2 CPU GPIO17 m m m m ANI3 m VG13_GPIO61 em EVG6 GPIOS2 e CPU DACOI GPIO19 em GPIO9 DSRX WS MOTOR H2 ENC2
14. B Ethernet SchDoc Author A Davison 3 4 5 6 8 80 00 mm MEN OO mE e 6094 zm T 6022 YN Sul 3 425 JP426 JP429 JP42 HEN HER JP430 JP431 m B SEN 5e JP434 EmA JP435 JP436 9025 9002
15. B functionality CNTRL I2C SCL 15 00 4 5 CNTRL I2C SDA 16 00 5 SDA Electrocomponents plc Page 11 OVE 23 PIOO 7 5 12 PIO2 8 22 PIOO 6 5 13 P102_1 DSR SCK1 JP407 421 57 422 EVG19 GPIO67 EVG5 GPIO50 EVG8 GPIO56 EVGO GPIO40 GPIOO EVG6 GPIO52 GPIO1 5 JP438 JP437 JP43 MET JP431 EVG7 GPIO54 GPIO7 125 RX EVMO_GPIO21 GPIO9 125 RX WS 1 GPIO23 CPU GPIO17 EVMS5 GPIO47 EVM9 GPIO55 5 1 TX TTL EVM7 GPIO51 5 1 RX TTL 8 426 8 GPIO53 Asc1 TX TTL EDP CM LPC1113 CPU Module RS 3 Solder Link Options Many of the options for the Command Module board require a solder bridge to be made or a track to be cut The CM board has been designed to be configured in the most popular setting by using a small track between the options which will require cutting with a sharp knife before making the alternate connection options A documents called a Mapping Aid exist to help explain the resources available on the MCU and how it can interface with the other modules within the system An extract from it is in t
16. DP CM LPCx B Coventry DEVELOPMENT TOOLS Date 19 03 2010 c Hitex UK Ltd Sheetl of3 File D PCB Designs DXP EDP CM LPCx Rev B Module Connectors SchDoc Author A Davison 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 3V3 3V3 3V3BAT JP201 202 203 1 3 AN 1 3 AN REF 1 ERE E e Bolderlink e Bolderlink e Bolderlink PO 0 46 PO T 47 PO 2 PIO1 7 98 6 4 PIO0 3 S PIO1 9 CS SD SPI SCKT SPI MISO1 SPI MOSII PO 10 PIO2 0 PO 112102 11 CNTRL SPI CLK CNTRL SPI CS_NSS CNTRL SPI MRST CNTRL SPI MTSR PO 19 PIO2 7 20 PIO2 4 21 PIOI 8 22 PIO2 5 23 PIO1 4 P0 24 25 T 0 26 CNTRL DC SDA CNTRL DC SCL 24 2 USB D USB DEV D 0 TXDO 95 P1 1 TXDI 945 P1 4 ENET TX PI 8 CRS P1 9 RXDO PI 10 ENET RXDI P1 14 RX P1 15 REF CLK PI 16 MDC 17 18 10 I9 PIO3 0 21 02 3 35 22 PIO3 2 Pl 23 PIO3 3 EVMS GPIO47 28 PIOO 2 29 PIOO 8 30 PIOI 11 P1 31 A 20 PIO3 1 34 A Ar P2 0 2 8 P2 1 0 6 9 GPIOSS
17. EDP CM LPC1113 CPU Module EDP CM LPC1113 CPU Module User Manual Version 1 02 5th August 2010 Electrocomponents plc Page 1 EDP CM LPC1113 CPU Module Contents 1 Introduction 3 2 Pin Allocation 4 2 1 Allocation of MCU pins to backplane functions 4 2 2 Resources Used Available by LPC1113 6 2 3 Alphabetical Listing of MCU 7 2 4 Backplane Base Board Signals 8 2 5 c 14 3 Solder Link Options 12 4 Zero Ohm Links 16 5 Software Support 17 5 1 RSEDP Test i ERE 17 2 Test S lle ite rie eise 17 5 3 MG2 Test Ente 18 Electrocomponents plc Page 2 EDP CM LPC1113 CPU Module RS 1 Introduction The RS EDP platform is a system has been designed to utilise many different manufacturers microprocessors To support NXP range or ARM Cortex MCU s a single Command Module CM has been designed to accommodate four different device types These are LPC2368 ARM7 LPC1768 Cortex M3 LPC1343 Cortex M3 and LPC1113 Cortex MO Each of the boards comes with its own suite of software to fully exercise the RS EDP Application Modules and the peripherals available on the MCU device In an RS EDP system there is usually one Command Module CPU Modu
18. GPIO37 9 GPIO38 GPIO39 ADS EVG0 GPIO40 EVM2 GPIO4I CAPADC EVGI GPIO42 EVM3 GPIO43 EVG2 GPIO44 EVM4 GPIO45 EVG3 GPIO46 EVMS GPIO47 EVG4 048 EVM6 GPIO49 EVGS 050 EVM7 GPIOST EVG6 GPIOS2 EVMS GPIOS3 EVG7 GPIOS4 EVM9 GPIOSS EVGS GPIOS6 EVG9 GPIOS7 EVGIO GPIOSS EVGIT GPIOSS EVGI2 GPIO60 EVGI3 GPIO61 EVGI4 GPIO62 EVGIS GPIO63 EVGI6 GPIO64 EVGI7 GPIO6S EVGIS GPIO66 EVGI9 GPIO67 ASCO RX TTL EVMIO GPIO68 ASCO CTS ASCO TX TTL EVG20 GPIO69 ASCO RTS ASCI RX TTL SPI SSC MISO ASCITX TTL SPI SSC MTSR_MOSI ASCI TX TTL ASCO DTR SPI SSC CLK USB DEBUG Dt ASCI TTL_ASCO DSR MOTOR POL USB DEBUG D SPI_SSC CS_NSS MOTOR CNTRL SPICLK ETH TX MOTOR PIL CNTRL SPI MRST MOTOR CNTRL SPI MTSR ETHRX P MOTOR P2L CNTRL SPI CS NSS N MOTOR P2H CNTRL DC SDA ETH LNK LED MOTOR PWM CNTRL SCL ETH RX LED EMG USB HOST D ETH SPD LED MOTOR ENCU USB HOST D GENI SDA MOTOR ENCI USB DEV D GENI SCL MOTOR H2_ENC2 USB DEV D CANI RX MOTOR TCO FB CANHO CANI TX TEVEN CANLO VCC_CM 3V3 4 D gt 3V3 VCC gt 3V3 CM vid D gt 3V3 3V3 lt D gt 3V3 gt 5 5V 4 SGND SGND SGND 99 SGND 4 D Aor P E Moe Tyco Amp 100 Way A MI 12VGND 13 12VGND Tyco Amp 140 Way Checked By Title Hitex UK Lid Module Connectors Sir William Lyons Road hitex mum Size Number Revision University of Warwick Science Park Approved By A3 E
19. KO 2 link options 5 1 TTL 2 Link options EVMS8 GPIO53 12 PIO2 8 2 link options 5 1 TX TTL 2 Link options EVM7 GPIO51 21 PIO3 5 2 Link options EVM6 49 2 Link options GPIO2 MCIDATO 9 PIO1 8 CT16B1 CAPO 2 Link options EVM4_GP1045 2 Link options 14 MCIPWR 18 PIO3 4 2 Link options GPIO43 2 Link options GPIO12 MCICMD 11 PIO2 7 2 Link options EVM2 GPIO41 CAPADC 2 Link options GPIO10 MCICLK 17 PIO1 9 CT16B1 MATO 3 link options GPIO9 125 RX WS 3 link options EVM1 GPIO23 3 link options CPU DACOO 017 14 PIOO 3 2 link option GPIO7 125 RX 2 Link options EVMO GPIO21 47 PIO1_7 TXD CT32B0_MAT1 3 Link options ASCO TX TTL 3 link options AN7 3 link options AN15 46 PIO1 6 RXD CT32B0 MATO 3 Link options ASCO RX TTL 3 link options AN6 3 link options AN14 Electrocomponents plc Page 5 EDP CM LPC1113 CPU Module 2 2 Resources Used Available by LPC1113 Resources Used Available to LPC1113 ANO ANA AN6 AN7 AN8 AN12 AN14 AN15 ASCO TX TTL ASCO RX TTL 5 1 TX TTL 5 1 RX TTL 5 1 TX TTL ASCO DTR CNTRL 12 SCL CNTRL 12 SDA CPU DACOO GPIO17 CPU DACO1 GPIO19 EVGO GPIO40 EVG1 GPIO42 EVG2 GPIO44 EVG3 GPIO46 EVG4_GPIO48 EVG5_GPIO50 EVG6_GPIO52 EVG7_GPIO54 EVG8_GPIO56 EVG9 GPIO57 EVG10 GPIO58 EVG11 GPIO59 EVG12 GPIO60 EVG13 GPIO61 EVG17_GPIO65 EVG18_GPIO66 EVG19 GPIO67 EVMO GPIO21 EVM1 GPIO23 2 041 EVM3 GPIO43 EVMA GPIO45
20. O17 is also available on JP430 PIO2 9 1 10 AD6 CT16B1 MAT1 JP407 2 1 Default JP407 2 3 JP407 2 4 Note EVGO GPIO4O is also available on JP406 PIOO 1 Electrocomponents plc Page 13 EDP CM LPC1113 CPU Module 1 11 AD7 405 2 1 Default ANA 405 2 3 AN12 Port PIO2 Options PIO2_0 DTR SSEL1 JP421 2 1 Default JP421 2 3 PIO2_1 DSR SCK1 JP426 2 1 Default ASC1_TX_TTL_ASCO_DTR JP426 2 3 CAN1_RX PIO2_2 DCD SISO1 JP428 2 1 Default JP428 2 3 PIO2_3 RI MOSI1 JP411 2 1 EMG_TRAP JP411 2 3 Default PIO2_7 JP436 2 3 GPIO10_MCI_CLK JP436 2 1 Default PIO2 8 JP432 2 3 5 1 TX TTL 432 2 1 Default PIO2 9 JP430 2 3 CPU DACOO GPIO17 JP430 2 1 Default Note CPU DACOO 17 is also available on JP437 PIO1 9 PIO2_10 429 2 3 CPU_DACO1_GPIO19 429 2 1 Default 2 11 5 0 1 422 2 1 Default 422 2 3 Electrocomponents plc Page 14 EDP CM LPC1113 CPU Module RS Port Options PIO3 409 2 1 409 2 3 Default PIO3_1 DSR JP410 2 1 MOTORHO_ENCO JP410 2 3 Default PIO3_2 DCD 412 2 1 MOTORPOL JP412 2 3 Default
21. T2 32 TDI PIOO 11 ADCO CT32BO MAT3 34 amp 28 TDO PIO1 1 AD2 CT32B1 MATO amp PIOO 9 510 1680 1 33 amp 39 TMS PIO1 0 AD1 CT32B1 amp SWDIO PIO1 3 AD4 CT32B1 35 TRST PIO1 2 AD3 CT32B1 MAT1 44 VDDCORE VDDIO 5 VSSIO 41 VSSIO 6 XTALIN Electrocomponents plc Page 7 EDP CM LPC1113 CPU Module 7 XTALOUT 2 4 Backplane Base Board Signals Break Out Base Board Signal Name EDPCON1 EDPCON2 Connector HCSO 53 amp 54 HCS1 55 8 56 HCS2 57 amp 58 HCS3 59 8 60 HPSEN 51 amp 52 HRD 45 amp 46 P603 26 P603 27 HWR 47 amp 48 WRH 49 amp 50 P603 47 P603 47 P603 47 P603 47 P603 48 P603 48 P603 48 P603 48 P603 44 P603 44 P603 44 P603 42 P603 45 P603 45 P603 45 ADO 412 42 A1_AD1 39 8 40 A2_AD2 37 8 38 A3 AD3 35 amp 36 A4 33 8 34 A5 AD5 31 amp 32 A6 AD6 29 amp 30 A7 AD7 27 amp 28 8 AD8 25 amp 26 A9 AD9 238 24 A10 AD10 21822 A11 AD11 19 amp 20 A12 AD12 17 amp 18 A13 AD13 15 amp 16 A14 AD14 13 amp 14 A15 AD15 11 amp 12 ALE 43 amp 44 6 3 P603 2 AN1 4 P603 6 AN2 5 603 1 AN3 6 P603 5 7 602 2 5 8 602 4 AN6 9 P602 1 AN7 10 P602 3 AN8 11 601 2 AN9 12 601 4 AN10 13 P601 1 Electroco
22. allows you communicate with the MC2 motor drive module across the 12 backplane network present in the RSEDP system You can have up to three MC2 motor drives fitted and this suite of software allows you to communicate with all of them Electrocomponents plc Page 18 Module Position 1 EDPCONI IO Connector 3V3 P101 RIO AN REF 2 m ANI AN3 ANS ANG ANT ANS ANIO ANIT 2 ANIS ANI4 ANIS Ro SGND pm VAGND VAGND 500 Gri VAGND GPIO2 MCIDATO GPIO3 GPIO4 MCIDATI GPIOS DSTX WS EDPCON Bus Control Connector GPIO6 MCIDAT2 GPIO7 DSRX GPIO8 MCIDAT3 GPIO9 DSRX WS DSRX SDA GPIOI2 MCICMD GPIOI3 DSTX CLK RESIN GPIOI4 MCIPWR GPIOIS DSTX SDA FRESOUT GPIO16 CNTRL DC INT CPU DACO0 GPIOI7 12 GENO SDA IRQ_GPIO18 12 GENO INT CPU GPIOI9 12 GENO SCL IRQ GPIO20 12C GENI INT EVMO0 GPIO21 1 IRQ GPIO22 DC INT EVMI GPIO23 SGND Ais ADIS SEND GPIO24 AD7 GPIO25 ADIS ADIA GPIO26 GPIO27 ADI4 13 GPIO28 ADS GPIO29 ADI3 12 ADI2 GPIO30 AD4 GPIO31 ADI2 GPIO32_AD3 GPIO33 ADIT AD7 GPIO35 ADI GPIO36 ADI
23. he section above The options are as follows VDDA JP201 1 2 VDDA on the MCU is connected to 3 3V JP201 2 3 VDDA on the MCU is connected to AN_REF on the backplane The LPC1113 does not use this VDDA reference so the jumper setting is irrelevant This function is provided for the LPC1768 and LPC2368 variants of this CM VDDA is the power supply voltage to the on board ADC circuitry Using a lower noise AN_REF signal will yield better results The AN_REF signal is usually provided by a stable voltage reference source present on the Analogue Module Vref JP202 1 2 VREF on the MCU is connected to 3 3V JP202 2 3 VREF on the MCU is connected to AN_REF on the backplane The LPC1113 does not use this Vref signal This function is provided for the LPC1768 and LPC2368 variants of this CM This is the voltage reference that is used to measure the analogue input voltages against An AN_REF signal will provide better results than the 3 3V signal The AN_REF signal is usually provided by a stable voltage reference source present on the Analogue Module VBAT JP203 1 2 VBAT on the MCU is connected to 3 3V JP203 2 3 VREF on the MCU is connected to 3V3_ BATT on the backplane This option is irrelevant as the LPC1113 does not a VBAT terminal This jumper is provided for the LPC1768 LPC2368 variants of the Command Module Port PIOO Options PIOO_1 CLKOUT CT32B0_MAT2 406 2 1 406 2 3
24. le Always check the software to see if the baud rate has been changed Some of the provided software may includes 5 1 RSEDP Test Suite This software exercises the NXP LPC1113 MCU peripherals including the on board ADC PWM output input capture 12C and I O The software also allows you to exercise the basic Application Modules which the Communication Module the Digital MO Module and the Analogue Module A suite of drivers and test menus are provided to fully exercise all the hardware on these boards 5 2 MC1 Test Suite This is similar to the RSEDP Test Suite but the test menus provided are for the MC1 Brushed DC Motor Drive Application Module The motors are nominally 12V brushed DC motors running in a full H bridge configuration The test suite allows you to accelerate the motor change its direction turn the brake on and off as well as allowing the monitoring of motor current DC link voltage and tacho feedback signals The MC1 motor drive module also has many external inputs for limit switch detection and conditioning of motor related stimuli The provided software library will therefore allow you to fully exercise your motor Electrocomponents plc Page 17 EDP CM LPC1113 CPU Module RS 5 3 MC2 Test Suite This is similar to the MC1 test suite but for brushless DC AC motors The software assumes you have an MC2 motor drive module fitted and you want to communicate to it via I2C packets This set of software therefore
25. le CM and one or more Applications Modules AM plugged in to the Base Board BB These NXP modules have been designed as the Command Module for the system The Command Module in a system dictates whether the whole system is 3 3V one or a 5 0V one All of these modules use 3 3V microprocessor and consequently the I O is mostly 3 3V also To tell the rest of the system the Command Module is a 3 3V one not a 5 0V one the Vcc CM line on the base board is connected to 3 3V by the tracking on the Command Module board This Vcc CM is used as a reference by the other modules such as the analogue module to limit the output voltage to 3 3V The command voltage line is also used by the RESET circuit as the voltage reference to pull up to after the reset line has been asserted low The CPU Module maps the I O of the NXP MCU on the board to the backplane of the RS EDP system As there are quite a few dual function pins on the NXP processors and hence several link options have been made to accommodate the various options the user may wish to use Extensive use of the 12C capability is used to communicate to the application modules in the system Electrocomponents plc Page 3 EDP CM LPC1113 CPU Module 2 Pin Allocation 2 1 Allocation of MCU pins to backplane functions The CM has been mapped to the backplane to maximise the functionality of the system and the AMs A document called a Pin Allocation Spreadsheet exists which details the mappi
26. mponents plc Page 8 EDP CM LPC1113 CPU Module AN11 14 P601 3 AN12 15 603 4 AN13 16 P602 6 AN14 17 P603 3 AN15 18 P602 5 TTL 89 P602 30 ASCO TX TTL 91 P602 31 5 1 RX TTL 93 P602 32 5 1 RX TTL ASCO DSR 99 P602 35 5 1 TX TTL 95 P602 33 5 1 TX TTL ASCO DTR 97 P602 34 CANO RX 61 amp 62 CANO TX 63 amp 64 CAN1 RX 121 P602 46 TX 123 P602 47 CANHO 89 amp 90 P603 40 CANLO 91 8 92 603 41 12 SCL 79 8 80 603 35 CNTRL 12 SDA 77 amp 78 P603 34 CNTRL_SPI_HCS_NSS 75 amp 76 P603 33 CNTRL SPI CLK 69 amp 70 P603 30 CNTRL SPI MRST 718 amp 72 P603 31 CNTRL SPI MTSR 73 8 74 603 32 CPU DACOO GPIO17 38 P603 7 CPU DACO1 019 40 P601 7 TRAP 114 P601 44 ETH LNK LED 111 P602 41 ETH RX 109 P602 40 ETH RX LED 113 P602 42 ETH_RX 107 P602 39 SPD LED 115 P602 43 ETH_TX 105 P602 38 ETH_TX 103 P602 37 EVGO_GPIO40 61 P602 16 EVG1 GPIO42 63 P602 17 EVG2 44 65 P602 18 EVG3 GPIO46 67 P602 19 EVG4 GPIO48 69 P602 20 EVG5 50 71 602 21 EVG6 GPIO52 73 602 22 EVG7 54 75 602 23 EVG8 GPIO56 77 602 24 EVG9 GPIO57 78 P601 26 EVG10 GPIO58 79 602 25 EVG11 GPIO59 80 P601 27 EVG12 GPIO60 81 P602 26 EVG13 GPIO61 82 P601 28 EVG14 GPIO62 83 P602 27 EVG15
27. ng of the pins to the backplane The details of this mapping are detailed below Below are detailed the pin number of the MCU the pin name a comment on its usage and the signals name to which it is allocated on the backplane As the same PCB is used for variants of LPC processor some of the mapping may appear a little strange For example this device has no CAN but is allocated some CAN resource on the backplane This is because other NXP variants do have a CAN controller on board and the mapping is done to accommodate this other device RS EDP BASE BOARD LPC1113FBD48 Comment mapping Pin Name of function used on PIC Name 34 amp TDO PIO1 1 AD2 CT32B1 MATO amp 28 PIOO 9 MOSIO CT16BO 1 JTAG interface on LPC module 32 TDI PIOO 11 ADCO CT32BO MAT3 JTAG interface on LPC module 338 TMS PIO1 0 AD1 CT32B1 8 39 SWDIO PIO1 3 AD4 CT32B1 JTAG interface on LPC module 35 TRST PIO1 2 AD3 CT32B1 MAT1 JTAG interface on LPC module 29 SWCLK PIOO 10 5 16 MAT2 JTAG interface on LPC module 40 PIO1 4 AD5 CT32B1 MAT3 WAKEUP 2 link options ANO 2 link options AN8 3 RESET PIOO_O 42 PIO1 11 AD7 2 link options 2 link options AN12 XTALIN XTALOUT 15 PIOO 4 SCL CNTRL 12 SCL 16 PIOO_5 SDA CNTRL I2C SDA 1 PIO2 6 EVG1 GPIO42 4 PIOO 1 CLKOUT CT32B0 MAT
28. st menu to exercise each of the modules independently of the others This therefore provides working example of the code which will allow students and users to cut and paste various sections into their own applications Each Applications Module has its own collection of header files which provides the support for the functions that control it Each module has its own set of high level functions that can be called to operate and control the hardware This makes life a lot easier for the user who can then spend most of his time working at the higher level application layer The software has been packed up as several ZIP file which can be downloaded and unpacked Most of the projects have been written for the Keil uVision environment The majority of the applications written use the serial comm channel ASCO for outputting data to a terminal emulator With this in mind a serial terminal emulation program should be used to read traffic outputted from the RS EDP platform Hyper Terminal is included in windows as part of the Windows Operating system but this does not work reliability With this in mind it may be worth looking at other terminal emulator especially if they are to be used with USB RS232 converters The terminal emulator should be set up for 115 200 baud 8 data bits no stop bit no parity No flow control The default jumper options for JP439 and JP430 should be left in place to ensure serial traffic is routed to the communication modu
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