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Model 4P Service Manual (1984)(Tandy)

1. 9309 AUNUL 38 076948 1NON4 n Nr 8 57 fa TH Ta REAR REV 8709427
2. 1983 MADE IN EST 9700407 REV 126625 E MS PER ECT TANDY 8 77 TRNG2H 15 83 TAROT 5 58 GESSI 9 Parts List Main PCB Assembly Model 4P Computer Item Sym Description Part Number 1 1 PCB Main Logic 8709427 2 21 Staking Pin 8529014 3 1 Socket 8 Pin DIP U79 8599611 4 16 Socket 16 DIP U115 139 8509003 5 1 Socket 18 076 85090 6 6 18 Socket 2 Pin 039 41 8509009 47 5 51 62 63 84 11 7 3 Socket 24 Pin DIP Ul6 24 44 85 9 l 8 4 Socket 4 Pin 026 43 8509992 U72 81 9 1 Connector 4 Pin J8 851921 18 1 Connector 3 Pin J1 11 1 Connector 6 Pin J9 8519211 12 1 Connector Dual 8 J6 8519184 13 1 Connector 34 Pin J5 14 1 Connector 34 Pin 47 15 1 Connector 25 74 851910
3. k PCB ev 277 our 6 95 57 2 65 E 2 i PICTURE 55 1 F401 24 av Lo VERTICAL 10201 AN5763 ew 300 nav zw peo 8 HH F Ty 23 52 mor 8265 15 201 T 0022 1 I Eod 10809 50020 800v uer ser 1 Mou E for Masse 16301 ANST53 Jv ner naso E 0 1 E E 4 sa 9365 362 ase H serra 22 2568 a 510 100 MAIN PCB NOTE 1 ALL RESISTANCE VALUES ARE INDICATED K 10 OMM M 10 OHM 2 ALL CAPACITANCE VALUES ARE INDICATED pF yr APPROVED BY TITLE MODEL DRAWING 86 VIDEO MONITOR 8790613 0 23757 180 Parts List 9 video Monitor 8799612 Model 4P Computer Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor 0 01 uF 63 v Poly 1 8 0047 uF 18887 Cer 8 0022 uF 5 v Cer 9 0922 uF 1999V Cer 1 uF 25 1 203 22 5 Cer 22 uF
4. SELE EO m A e o x vss 2 Ds sem oec papera a on 2950 eos ups 4 Co i M 425 gt pr K do 56 6 gt ANGAN 5 19 55 ds ease A 8 73 025539 26 81 ZONY dud 2 4 x A 4 1276018 C rohs de a 1 lt Ed gt 24 SE 5 at gt HO SN g aor Canem BR eph RE SEE 5 85 3 a 5 88 Sugo l n 00 ud SET VIDEO 75
5. EM n E 128 pcm um quee ap zm ids n Bel V 58584811 THAI SR 38958339 ay cape 39 23 P uo 1 Corp once ________ 24 r 8 112 70 71 SUM som merae E 5521 EE GE us ufo ED Gr GO on HEADER 72 Ea d
6. 325 4 scolo s 1 48 TRNSRS 82 Mar 84 TANGY INC HEN 6 5 9 822 GESSL 136 Parts List Model Gate Array PC Board Sym Description Part Number 1 6 Capacitor 1 mfd 50V Mono 8374104 9 18 Capacitor 1 mfd 50 Mono Axial 8374104 52 24 Capacitor 1 mfd 50V Mono Axial 8374104 C27 31 Capacitor 1 mfd 50V Mono Axial 8374104 C33 Capacitor 1 mfd 50V Mono Axial 8374104 C34 Capacitor 1 mfd 50V Mono Axial 8374104 C36 Capacitor 1 mfd 50V Mono Axial 8374104 41 Capacitor 1 mfd 50 Mono 1 8374104 42 Capacitor 1 50V Mono Axial 8374104 C45 Capacitor 1 mfd 50V Mono Axial 8374104 50 Capacitor 1 50V Mono 1 8374104 55 57 Capacitor 1 mfd 50V Mono 1 8374104 C61 Capacitor 1 mfd 50V Mono Axial 8374104 C67 Capacitor 1 mfd 50V Mono Axial 8374104 C69 Capacitor 1 mfd 50V Mono Axial 8374104 C70 Capacitor 1 mfd 50V Mono Axial 8374104 C72 Capacitor 1 mfd 50V Mono Axial 8374104 C73 Capacitor 1 mfd 50V Mono Axial 8374104 Capacitor 1 mfd 50V Mono Axial 8374104 C78 Capacitor 1 mfd 50V Mono Axial 8374104 C81 89 Capacitor 1 mfd 50V Mono Axial 8374104 C91 Capacitor 1 mfd 50V Mono Axial 8374104 C92 Capacitor 1 mfd 50V Mono Axial 8374104 94 96 Capacitor 1 mfd 50V Mono Axial 8374104 C98 Capacitor 1 m
7. 1 ALL RESISTANCE VALUES ARE IN OHMS K 1800 NOTE ess OTHERWISE setcineo z A F LN its pe 0 M n T Sinwa n ADE I 134 MEET 745245 54 ae m Miis 54 EB Car lt iau s Rc Gap mon 3 dti 3 D LER cer Yet DLYVWA con 5 Li sure d Ec 5 En CET 5 3 3 23 233 SAS Ire aie EET 339 57755567 case Leze iue dr 52 NENE 5 MAN LOGIC id MODEL n PROJECT 509 N A lcs s ses Carey E Sur rum 29 65 34245 peSPAGE SIL mem mE lt P 25 05018 CED poen 4 SERE 48 RAMBUSENX T i 2 ER 533 ET z n
8. Real Time Clock L5 Ladd AM Ree Line Printer del i ble Reo hi ate Graphics Port SOUR uke MILES dydene Me Bo ad YO BUS Port ci FDC Circuit ARI pte E MOD SAO se ped sa arp s a Ea RS 232C Circuit Troubleshooting specific Schematic8000192 PCB Art 1700254 Parts List Assembly Mini Disk Drives Tandon TM 50 Power Supply Assembly Power Supply Description 5 Theory of Operation 7 74 22 004 Troubleshooting Chart 2 Testing and Adjustments 2 2 2 2 Schematic 8000164 65W Power Supply 8790049 161 Component Layout 65W Power Supply 8790049 163 Circuit Trace 65W Power Supply 8790049 164 Parts List 65W Power Supply 8790049 165 CREDISpIAY 2262265 a ie Ep a de eA de RE HEP Specifications PEE Adjustment Procedures Theory of Operati
9. CATA OL 0 33188 2010 OL TIVNHXINI INWIEZIO Z TN OL TVYNSFINI NadSIGAIG N3dSIG 59407 x LIIHS 1499 84955 ern xAVOT Lqus gaus zen diVuS gvus zen 8 2583 Figure 5 31 Video Blanking Timing 116 617 2610 x 2004 T TN OL TWNYALNI OL 5 388 3 2010 OL TIVNS3 INI OT LAIHS 353 85 1090 CATO TVYDD E VDO LAYS TES cen givus uss iming ideo Figure 5 32 Inverse Vi 117 OLIO zen Tre XA uus 5 2 12 Graphics The Graphics 17 on the is provided to attach the optional Graphics Board The port provides 00 07 Data Lines A0 A3 Address Lines and RESET for the necessary interface signals for the Graphics Board GEN is generated by negative ORing Port selects GSEL0 8C 8FH and GSELI 80 83H together by 1 4 of 74LS08 U4 sulting signal is negative ANDed with IORQ by 1 4 of 74532 U24 Seven timing signals are provided to allow synchroniza tion of Main Logic Board Video and Graphics Board Video These timing signals VSYNC HSYNC DISPEN DCLK and J Three control signals from the Graphics Board are used to sync to CPU access and select different video modes WAIT
10. 540 2 1 x 178 y NHSVY t ij que e e Li E HSAN c OES gt _ WA j 1 TT 1 Wiod 2 EG Figure 5 9 1 Cycle Timing 4 2 50ns dir 42 VIVO GITVA LaW gaw Gav 7305 VINI vsc gvua aa 05944 x INSSVM NESVY 2 52 m EEE s TT 5 10 Memory Read Cycle Timing 43 VIVO ALIUM LOK GN KIYE 999 SVI SVY 89 8 8 gt mr er pre EG er Oa Az LL D 589 ee II nf oes Figure 5 11 Memory Write Cycle Timing 4 1 SELO 1 5 SELI 0 0V ROM 0 5V Mode 0 SELO 0 5811 0 0000 3788 14K ROM 1 gt 0 3800 Keyboard 1K 3C00 3FFF Video 1K 0000 OFFF Boot ROM 4000 48 1000 37FF RAM Read Only 10K 37E8 37E9 Print
11. m ui Ds 10 vis RI os 68 14 0825 200 803 s bi 806 Bor gt Ap ar 88 ror 852322 fa RICINT 200 901 502 505 804 805 806 Do 852326 LOGIC en oe TANDY CORP 8709524 REV REST VIDEO POWER 293 um am ens 824 1 C2 ma 65 8709524 REV 82066 134 385 4 FRONT SILKSCREEN H im x e EE 7 dl pista ii sr se EF FS a i z
12. iti Ei k si seri 3 38 256048 135 riri 5 CORP 1700284 vw F gt ERIR rn 8 055 87099524
13. Doane E fe SEZ 06 00 gt 198 98 a5 558 SELECT AND LOGIC 882885 NO 9000233 oF RAMBUSOIR RAMBUSENX SE 4 E ver 3 EE x E n 5 76120139 M va x4 EBEE To E Tor aS Iw i uis Teint SE a 11111111 PER S DID EY NR GE RASEND 42 a ASO RASEN Ge n RAST gt an e ra PE 11111111 A L 5 4 ELM p an e 6458 i 11111111 11111111 537 4 4 i dos m T eum YO gt eu 11111111 LL Li yo ETF ES 1 Ce c MU ER 2767 ARAM WI Td l 11111111 11111111 2 asta 3 3s Ig nes let ea r t poste 555 w 4 5 5 PA Ex ta u Ga 5 oot UIS
14. ROY TITAS AS T 195 ALVIS AZE WWX MOT WYA 777 8 BUT OSGIA XI HV AINO ALTIUM Wwe HOVdONS JOVANI 354889 Xv WO 1004 008 Figure 5 6 Memory 39 x AS 1 1145 AS T 115 THAT 31415 a AZE WHY 8 NTE 85171 avd ous HOVdNE 35 4930 300W x AS t TTS Ag g 135 TAFT ALVIS AZE AZE 854388 HDVANE 354830 2 MX OSGIA 191 19 Figure 5 7 Memory MOLT wey MOL Wo 56843 IA 82089 ubim 6 4 Woy 6 843 N N N N N umouyun as Aux DIEA PIRA 2183 1 490 58 isnw indui 109 indo indu foquiAs mo UO BA AA SMHOIIAVM VIVO UTTVA 8 15 8 100 N LWua gvua 0594 x 9 8 IO 8 898 ep ei a z Ty 2MHZ 100ns dir Figure 5 8 M1 Cycle Ti 41 dov gt ae
15. gt UM ee f 58884 ea a sTOK9 ON FIGURE 5 29 Video RAM CPU Access Timing 113 RAO RA3 row addresses from the CRTC are used to control which scan line is being displayed The Model 4P has a 4 bit full adder 7415283 0101 to modify the Row address During character display DLYGRAPHIC is high which applies a high to all 4 bits to be added to row address This will result in subtract ing one from Row address count and allow all characters to be displayed one scan line lower The purpose is so inverse char acters will appear within the inverse block When a graphic block is displayed DLYGRAPHIC is low which causes the row address to be unmodified Moving jumper from E14 E15 to E15 E16 will disable this circuit DLYCHAR and DLYGRAPHICS are inverse signals and control which data is to be loaded into the internal shift register of U102 When DLYCHAR is low and DLYGRAPHIC is high the Char acter Generator ROM U103 is enabled to output data When DLYCHAR is high and DLYGRAPHIC is low the graphics char acters are internally buffered to the shift register The data is loaded into the internal shift register on the rising edge of SHIFT when LOADS is low Serial video data is output U102 19 The video information is inver
16. 1195 Ag g1as T3A81 YLVIS YTE WWE gt OSGIA MT K INO X T WON 1008 1994285 ADVANI f 5 22 99 WON 2 TTS AG T 415485 81415 3 NYE 1 YTE WYN T MIT WYN G I D O3QIA XI AGAIN YDVdDUS WWE AG g wou 39 AS 1 195 BIVIS gt AZE WVE oro 170 MT UT 08437 MP RINO SLIUM HFT WVH WON 1008 TOVADIS 5 23 100 x WON AS 1 1195 195 TAFT SINLS WYU NZE m 641710 39Vdous 39 4930 AS x WOH T THAT YLVIS WVY UTE wr T T 05198 WTD FOVADUS ROVINA TIAS 195 HZ XI 5 24 101 HO HOLT LIT 26 2 2030 LEE lt Yet T T Bu p4e pe VIII ag iv ag is
17. rr 50 4 vert 1 vert 5 horiz DC 5 u d horiz DC 1 v a vert 5 horiz DC 2 5 us d horiz la RER ONL D Bec des dee im y pec 248 9 Tao 2888 FA i gt E ScuEMOTIC POWER SUPPLY E 2000164 0 2 419 vert 5 horiz DC 5 v vert 5 horiz DC 161 4 01032055 OL 33 038 AINO 35 4 34 4 3WVS ONINHVM ceo z 2 9 2 2 lt o 2 22 3 Coe oun 1 NOI pi tA A WOO SIH piu 52668 70 it 010 0058 OL 5 YAMOd MS9 4900 188 J 5 S ov m V OT ZH 09 05 21 e 155 6 5 AGNV1 vm 8150041 se gt gt 5 2 k INI O 94 163 PARTS LIST Power Supply Assembly 8790049 65W C34 C35 C36 C37 C38 Printed Circuit Board Fan Output 2 pin verticle Bridge 2A 600PIV lOpF 35V elect radial
18. Model 4P Computer Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Transformer Transformer IC IC IC IC IC 56 kohm 6 8 ohm 1 2 ohm 4 7 kohm 22 kohm 33 ohm 8 2 ohm 1 kohm 68 kohm 1 ohm 1 kohm 1 2 kohm 2 2 kohm 1 kohm 3 3 kohm 22 kohm 15 kohm 1 ohm 2 7 kohm 56 ohm 82 kohm 15 kohm 22 kohm 229 229 279 159 159 199 kohm kohm kohm ohm ohm kohm 479 ohm 479 ohm 56 kohm 56 kohm 15 75 15 75 25 733 PNP 1 4W 5 Carbon 1 4W 5 Carbon 1 2W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 2W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 2W 5 Met Oxide 1 4W 5 Carbon 2W 5 Met Oxide 1 2W 5 Carbon 1 2W 5 Carbon 1 2W 5 Carbon 1 Mohm 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 2W 18 Solid 1 2W 1 Solid 1 2W 19 Solid 1 2W 19 Solid 1 24 108 Solid KHz Drive KHz Flyback Signal Amp 28C1313 G NPN Signal Amp
19. Radio Shaek ervice TRS 80 Model 4P 4P Gate Array Catalog Number 26 1080 CUSTOM MANUFACTURED IN U S A BY RADIO SHACK A DIVISION OF TANDY CORPORATION 80 Model 4P 4P Gate Array Service Manual Copyright 1984 Tandy Corporation All Rights Reserved Reproduction or use without express written permission from Tandy Corporation of any portion of this manual is prohibited While efforts have been taken the preparation of this manual to assure its accuracy Tandy Corporation assumes no liability resulting from any errors or omissions in this manual or from the use of the information contained herein 14 1 2 13 SECTION SECTION SECTION V 5 1 5 1 1 5 1 2 5 1 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 9 5 1 10 5 1 11 5 1 12 5 1 13 5 1 14 5 1 15 5 1 16 5 1 17 5 2 5 2 1 5 2 2 5 2 3 Introduction S a apuma 1 System Overview Ge tis eos UE 3 Optional Features ceci qe RA HET 3 System Block Diagram ss leda 5 Specifications Ced Ya 7 0 0 6 Penphersllnterfaces bee saa 9 Power Requiremen
20. i dk L PPPPI ME sumen son ANUUUGTION SCHEMATIC GRAPHICS 4 195 9 0000000 S2IHdvuo9 20 JAS LNJNOdWO2 BEZOOLI HI 21626048 ON 1394 8 8 DIHdVYED n n 9 539 SWALSAS AUNVL 9 6616 000000 20000002 di 338 T00 00079 198 SECTION EXPLODED VIEWS PARTS LIST 199 EXPLODED VIEW PARTS LISTS Contained in this section are exploded views and correspond ing parts lists for the major assemblies of the Model 4P Portable Computer These exploded views are divided into four major assemblies Case Assembly Main Chassis Assembly Disk Drive Assembly Keyboard Assembly 201 Case Assembly Model 4P Computer 202 Parts List Case Assembly Model 4P Computer Assembly 1 1 Case Housing 8719346 2 1 Cover Front 8719348 3 2 Clawbolt 8569199 4 2 Latch Guard 8719486 5 1 Keyboard Stop Cover 8779186 6 1 Pocket Inside 8719348 7 1 Handle Case 8 2 Rivet Blind 8579049 9 1 Power Cord 8709475 18 2 Clip Cord 11 4 Screw 8 32 x 1 2 Truss Head 8569203 12 2 Screw 10 32 x 1 2 PPH 8569202 13 1 Label Handle 14 1 Door Rear Panel 8719349 15 1 Retainer Door 8729252 16 5 Fastene
21. 89 R6 10 2 35 The other error amplifier U1 serves as a shut down compar ator The positive terminal pin 14 is set at the 5 0 volt ref erence and pin 13 the negative terminal or shut down pin is tied to the current limit latch The output of this error amplifier equal to Vreg since both error amplifier outputs are tied to the wave shaping logic will rapidly increase toward the 5 0 volts Recall that if Vreg exceeds the peak sawtooth voltage pulses are inhibited and the power supply shuts down Base Drive Figure 5 42 illustrates the BASE DRIVE circuitry which turns switching transistor Q7 on and off in response to the output of the pulse generator portion of U1 The ON circuit is shown in Figure 8a and the OFF circuit is shown in Figure 8b Waveforms for these circuits appear in Figure 5 43 The output transistor of 01 combined with forms a Darling ton pair This circuit provides the relatively large current nec essary through coupling capacitor C8 to turn on Q7 R23 limits this base current to a value large enough to turn on Q7 quickly but not so large that it will exceed the ratings of Q3 C8 or the base emitter junction of Q7 or so large that the turn off time of Q7 is excessive As Q3 turns on C8 charges to approximately 5 volts and Q7 is driven into saturation Energy is stored in the primary winding of T1 as the collector current of Q7 increases or ramps up at arate deter
22. indu ak indui cia SWHOJ3AVA GITVA LGW g OW dav 852838 cage 100 INK cvud gvua GAL AAA XXX c ioat J xXDW 1594 SVY 888 8 gt GET VEERE EEE nici TN aund cw A M HSAN o gr se ru o 2888 gt ee S 2882 2 153 Figure 5 25 1 Cycle Timing 2 2 102 102 aue J sti ie ef OT 1594 8 8 1 1 x TNASVH NASVA s EEE Eu LR PE dauna HSAN fr EE iL dl EE 27 4MHZ iming Figure 5 26 M1 Cycle Ti 103 VIVA AAA ro s ANNNYYY AX uzZr c2 lt ais zv gt a X OW _ 0544 Er 2 x TNHSVY 689114 58384 jp Figure 5 27 Memory Re
23. In MODIN LPIN RESERVED DISKIN FDC STATUS REG FDC TRACK REG FDC SECTOR REG FDC DATA REG RTCIN 52321 MODEM STATUS RESERVED UART STATUS REG UART HOLDING REG D R RD STATUS RD INT MASK REG RESERVED RESERVED RESERVED RESERVED 68510 RESERVED RESERVED RESERVED RESERVED GSEL1 46 VO Port Description Name CASSOUT Port Address FC FF Access WRITE ONLY Description Output data to cassette or for sound generation Note Model does not support cassette storage this port is only used to generate sound that was to be output via cassette port The Model 4P sends data to onboard sound circuit DO Cassette output level sound data output 01 Reserved 52 07 Undefined MODIN CASSIN Port Address FC FF Access READ ONLY Description Configuration Status DO 0 1 CASSMOTORON STATUS D2 MODSEL STATUS D3 ENALTSET STATUS D4 ENEXTIO STATUS D5 NOT USED D6 FAST STATUS D7 0 Name LPOUT Port Address 8 FB Access WRITE ONLY Description Output data to line printer 20 07 ASCII BYTE BE PRINTED 47 Name Port Address F8 FB Access READ ONLY Description Input line printer status 00 03 RESERVED D4 FAULT 1 TRUE 0 FALSE D5 UNIT SELECT 1 TRUE 0 FALSE 06 OUTPAPER 1 0 FALSE D7 BUSY 1 TRUE 0 FALSE Nam
24. BLOCK DIAGRAM Figure 5 64 175 MLIINCA 03014 DEFLECTION P C B TOP VIEW 176 Parts List 9 Video Monitor 879 612 Model 4P Computer 181 Item Sym Description Part Number 1 PCB Assembly CRT 031985 1 Clip Fuse 19739398 1 Connector Pin 19411 78 A 1 Fuse 2 25 25100 79 1 Spring Tension 434 1 12 A 1 Socket Pin 194 1 37 A 1 Socket Cylindrical 19631001 1 Cord Terminal 316 1 15 B 1 Cord Terminal 31608101 40A 101 Capacitor 4 7 uF 5fV Elec 26 4 RB 475M5 v C102 Capacitor 120 pF 5 Cer 19 CK45B1H121K C1 3 Capacitor 8 1 uF 5 V Mylar 19 CQ92M1H194K 104 Capacitor 22 uF 1087 Elec 20 CE 4C226ML V C1 5 Capacitor 22 5807 Cer CK45E2H222P C281 Capacitor 22 uF 5 Mylar 19 CQ92M1H223K C282 Capacitor 22 uF 5 V Mylar 10 92 1 223 203 Capacitor L uF 5 V Mylar 1 CQ92M1H1 3K C284 Capacitor 9 33 uF 169 Tant 185 515 1 334 C2 5 Capacitor 4 7 uF 16V Tant 19 CS15E1C475K C286 Capacitor 4 7 uF 16V Tant 19 CS15E1C475K C287 Capacitor 33 uF 16V Elec 20 4 336 16 C2 8 Capacitor 33 uF 16V Elec 20 4 336 16 C289 Capacitor 339 uF 35V Elec 20 4 337 35 C21 Capacitor 33 uF 5 Mylar 19 CQ92M1H333K C211 Capacitor 220 uF 16 Elec 2 CE 4C227M16V C212 Capacitor 199 uF 16 Elec 20 4 1 7 16 C391 Capacitor 220 pF
25. t3 peak charge t4 voltage at loaded value vin 160 volts Figure 5 39 Kick Start Latch With C1 charging rapidly through the low resistance of satu rated Q4 via Vbe5 the reference supply inside develops its 5 0 volt output when the voltage across C1 exceeds about 8 volts At this point the supply has not quite yet started but U1 has supply at pin 10 All that remains is to start up the pulse generator so that the supply operates and replenishes the charge in C14 on each cycle thus maintaining DC source for U1 of about 15 volts Completion of the start up sequence occurs when the soft start circuit described in the next section has started the pulse generator Control Section The control section consists of the control IC the primary half of the feedback optocoupler U2 and the base drive circuit for the switching transistor The control circuit IC has three major parts an internal regulator a pulse generator and an error am plifier section The internal reference is a regulated 5 0 DC voltage This voltage provides the reference voltages for the comparators used in the pulse generator as well as the DC supply voltage for the feedback optical coupler and the internal circuits of U1 ex cept for its output transistors The pulse generator section of the control IC has four major parts sawtooth oscillator b wave shaping and output cir cuit c regulating comparator d dead ti
26. 4 0 Read amp Clock X 1 Read amp Hold Bit 5 0 Read RAM amp Clock Y 1 Read amp Hold Y Bit 6 0 Write RAM amp Clock X 1 Write amp Hold Bit 7 0 Write RAM amp Clock Y 1 Write amp Hold Notes 1 Bit 1 should be set high all of the time otherwise correct memory refresh is not guaranteed 2 2 7 control the auto Increment auto Decrement func lion allowing a fast automatic updating of the RAM address 3 This register is cleared on reset Intermix Control Register Description HEX Address 8E 810 Mixing of text and graphics is not possible and the video display is forced into 640 x 240 mode of operation 1 Text and graphics will be mixed and the normal Model 4 control register will allow switching be tween 640 and 240 graphics and 512 x 192 graphics Bit 1 No connection Bit 2 No connection Bit 3 No connection Bit 4 No connection Bit 5 No connection Bit 6 No connection Bit 7 No connection Graphics Theory of Operation The Model 4 graphics board is designed to be minimum chip solution for the addition of graphics to the Model 4 GPU board The design is composed of three major elements the dynamic RAM the timing logic and gate array Figure 5 65 shows block diagram of the graphics board The details of the gate ar ray logic are shown in Figure 5 66 general overview of the operation of the graphics board is as follows The timing logic provide
27. 5V ROM Don t Care RAM 14K 1 1 48K 61K 1K 2K 64K VO Port Assignment Port FF FB F4 F7 Fo F3 Fo F1 F2 F3 EC EF E8 E9 EA EB E4 E7 E0 A0 DF 9C 9F 94 9B 90 93 8C 8F 88 8B 88 8A 89 88 84 87 80 83 Normally Used FF F8 F4 FO FI F2 F3 EC E8 E9 EA EB 4 9C 90 88 89 84 Out CASSOUT LPOUT DRVSEL DISKOUT FDC COMMAND REG FDC TRACK REG FDC SECTOR REG FDC DATA REG MODOUT RS2320UT UART MASTER RESET BAUD RATE GEN REG UART CONTROL AND MODEM CONTROL REG UART TRANSMIT HOLDING REG WR NMI MASK REG WR INT MASK REG RESERVED BOOT RESERVED SEN GSELO CRTCCS CRCT ADD REG CRCT DATA REG OPREG GSEL1 In MODIN LPIN RESERVED DISKIN FDC STATUS REG TRACK REG FDC SECTOR REG FDC DATA REG RTCIN RS232IN MODEM STATUS RESERVED UART STATUS REG UART HOLDING REG RESET D R RD NMI STATUS RD INT MASK REG RESERVED RESERVED RESERVED RESERVED GSELO RESERVED RESERVED RESERVED RESERVED GSEL1 107 Port Description CASSOUT Name Port Address FF Access WRITE ONLY Description Output data to cassette or for sound generation Note Model does not support cassette storage this port is only used to generate sound that was to be output via cas
28. If FAST is a logic low the U148 generates a 2 02752 MHz clock If FAST is a logic high U148 generates a 4 05504 MHz signal PCLK pin 23 of U148 is filtered through a ferrite bead FB2 and 220 Resistor R9 and then fed to the CPU U45 PCLK is generated as a symmetrical clock and is never allowed to be short cycled eg Not al lowed to generate a low or high pulse under 110 nanoseconds 5 2 4 1 Video Timing The video timing is also generated by U148 with the help of a PLL Multiplier Module PMM U146 These two ICs generate all the necessary timing signals for the four video modes 64 x 16 32x 16 80 x 24 and 40 x 24 Two reference clocks are required for the four video modes One reference clock is 10 1376 MHz Itis generated internally to 0148 and is used by the 64 x 16 32 x 16 modes The second reference clock is a 12 672 MHz 12M clock which is generated by the PMM U146 12M clock is used by the 80 x 24 and 40 x 24 modes A 1 2672 MHz 1 2M16 signal is output from pin 3 of U148 and is generated from the master reference clock the 20 2752 MHz crystal 1 2M16 is used for a reference clock for the PMM The PMM is internally set to oscillate at 12 672 MHz which is output as 12M U148 divides 12M by 10 to generate a second 1 2672 MHz clock 1 2M10 which is fed into pin 5 of U146 PMM The two 1 2672 MHz signals are internaily compared in the PMM where it corrects the 12 672 MHz output so it is synchronized with the 20 27
29. More simply stated the control chain uses an amplified version of the output voltage CHANGE to adjust the width of the base drive pulse through the action of a control voltage at a compar ator input from 5 reference in Ul Voltage goes down po Voltage poes un compensating change in output CRS b C10 11 15V 160V R23 Primary Secondary 5 48 Control Chain Simplified Schematic 5 4 4 Troubleshooting Chart for 65 Watt Power Supply Trouble open fuse Current limit cycle pulses at pin 8 of U1 i e supply shut down Cause shorted line input filter capacitor shorted bridge shorted filter capacitor shorted switching transistor single rectifier open in bridge open filter capacitor shorted snubber capacitor or resistor open opto coupler shorted supply output shorted output rectifier open or shorted output filter capacitor defective crowbar no aux DC supply no kick start no base drive dead time control divider malfunction under voltage protect divider malfunction PWM feedback malfunction 158 Remedy check and or replace C33 C32 C31 C30 check BR1 check C29 C26 R39 check Q7 C37 R40 C26 T1 pri Q3 Q1 R37 check and or replace BR1 check C29 check C37 R40 check U2 check computer for short on 5V 12V CRT 12V DISK 12V outputs and clear shorted condition check CR5 CR6 CR7 CR8 check C16 C18 C25 C23 C10
30. NO 8000235 130 VIDEO LOGIC 09 07 aay E ES m te r utes ae x 574 G5 s H 07 4 22n ae zoREO sr nour Shemen GRAPHICS BOARD me an 34 PIN HEADER Poe 5 cn te 7 5 897 DB Poa 1 ET LE PANTER D 806 15 134 PIN EDGE 24 ur GARD CONN 21 1 Sie DE 5 2 ET gep um mest do os 4 4 dos E lt gt r er m Rex PH 29 ME 1 FAULT a re fie us UNIT SELECT 2925 zi 59 26303220 WE 308 QUIPAPER ou 529 533 ED TE 6 6 Ls cas gg Seen 2 24 fre EAGER 1 EVEN I 138 7 9 11 6 643171 0 29282720 3353549374 seas 2 59 24 00 xo 3 3 M
31. dc Erg TA e T m GE 11111111 7 us 4 5 FOE E Iz ET EBE YT T ED e RES ta EE te msn w bi re pim H an K O v o rs_ Gen ak ab us m pr d tan 2 EH 8000192 69 resa Toon M he ER Lage EUR 18 29 sr ER gt 2 va PEE EE RE FI Hi a 4 4 CG 9 a E zn w E Lu a spd A 8544 84 Cao Cte 14 08 w ad ie E si CS i E pis 41 58 EM ol 5 E du abs 69 65 1 ap 300 1
32. ferential across the line signals by using the EMF set up by the signal current on one side of the line to oppose the signal current flowing in the other side C33 serves as a transient by pass capacitor to protect the power supply from large transient voltages that appear on the AC power line C33 also improves the efficiency of the RFI filter choke T2 by terminating the line in a low impedance to absorb and dissipate any remaining dit ferential RF energy R38 is a negative temperature coefficient thermistor which lim its the turn on surge current of the power supply filter capacitor C29 The resistance of this thermistor when cold is approxi mately 10 ohms Asthe filter capacitor charges toward the peak value of the AC input voltage it draws less current from the line Atthe same time the heating effect of the current flowing in the thermistor causes its resistance to decrease until it reaches its rated hot resistance of less than 1 ohm As you can see the thermistor dissipates very little power when the power supply is in operation The thermistor is designed to cool rapidly enough during power loss or turn off to limit the turn on surge after only a few seconds cool down a Latch Circuit 160v 30 01 92 fuse fast acting 3 0 amp unit is selected to ignore the short term turn on surges but open quickly in the event of an abnormally high current that would result from a component failu
33. voss om PCB m VIDEO CONTROL VIDEO DRIVE 470 2 ono m RAW VIDEO 2 4 weer 3 Foo E ag 1 BRT LOW 44 M H PICTURE 5 gii bs HORIVE 6 22 EB BH CONTROL 8 VERTICAL lt vomve 8 6909 Heke gets EE n a 286 D 208 najo 330 47 50v i B li 7 E 209 0022 500v INT 8319 92 ANSTSS 5 n 562 RGP 1 1 030 ERE 600 25 T rl T301 7 L 25623720 1 or 40 1 or nsus re ha 285 C310 MAIN PCS ISSUED 1 1 88 NOTE 1 ALL RESISTANCE VALUES ARE INDICATED IN OHM K 10 0HM M 10 0HM 2 ALL CAPACITANCE VALUES ARE INDICATED IN pF 8 10 APPROVED BY TITLE 3 7 83 CHECKED BY SCHEMATIC DIAGRAM MODEL DRAWING NO D 23535 Revised on Moy 16 1983 VIDEO BRT WIPER BRT LOW H DRIVE CONTROL V DRIVE GND 52 5953 VIDEO DRIVE mos 0103 282228 or 2818730009 Rios RIGA viogo CONTROL
34. 07 SOUND DATA RESERVED OPREG Port Address 84 Access WRITE ONLY Description Output to operation reg 00 01 02 03 04 05 06 07 SEL1 0 0 1 1 SELO SEL1 SELO MODE 0 0 1 1 9 2 1 3 8064 0 64 1 80 character mode INVERSE 0 Inverse video disabled 1 Inverse video enabled SRCPAGE Points to the page to be mapped as new page 0 U64K L32K Page 1 U64K U32K Page Enables mapping of new page 0 Page mapping disabled 1 Page mapping enabled DESPAGE Points to the page where new page is to be mapped 0 L64K U32K Page 1 L64K L32K Page PAGE 0 Page 0 of Video Memory 1 Page 1 of Video Memory 50 5 1 8 Video Circuit The heart of the video display circuit in the Model is the 68045 Cathode Ray Tube Controtler CRTC U85 The CRTC is preprogrammed video controller that provides two screen formats 64 by 16 and 80 by 24 The format is controlled by pin 3 of the 8064 The generates all of the neces sary signals required for the video display These signals are VSYNC Vertical Sync HSYNC Horizontal Sync for proper sync of the monitor DISPEN Display Enable which indicates when video data should be output to the monitor the refresh memory addresses 0 13 which addresses the video RAM and the row addresses RAO RA4 which indica
35. 161 to modify the Row address During character display DLYGRAPHIC is high which applies a high to all 4 bits to be added to row address This will result in subtract ing one from Row address count and allow all characters to be displayed one scan line lower The purpose is 50 inverse char acters will appear within the inverse block When graphic block is displayed DLYGRAPHIC is low which causes the row address to be unmodified Moving jumper from E14 E15 to 15 16 will disable this circuit DLYCHAR and DLYGRAPHICS are inverse signals and con trol which data is to be loaded into the shift register U63 When DLYCHAR is low and DLYGRAPHIC is high the Character Generator ROM U42 is enabled to output data when is high DLYGRAPHIC is low the graphics characters from U41 74LS15 is buffered by U43 74LS244 to the shift register The data is loaded into the shift register on the rising edge of SHIFT when LOADS is low Blanking is accomplished by masking off LOADS so no data will be loaded and zero data will be shifted out with the serial input of U63 pin 1 grounded Serial video data is out put U63 pin 13 and is mixed with inverse and or hires graph ics information by 1 4 or 74LS86 U143 The video data is then mixed with a DO7 Rate clock either DOT and DCLK to create distinct dots on the monitor DOT and DCLK are inverse signals and are provided to allow a choice to obtain the best video resul
36. 1800 4800 75 300 J 2000 7200 110 6 600 2400 9600 D 134 5 1200 L 3600 19200 The same message less the character signifying the baud rate is transmitted to the host with the same baud rate and protocol This message is the signal to the host to stop transmitting test bytes After the program has transmitted the baud rate message it reads from the UART data register in order to clear any overrun error that may have occurred due to the test bytes coming in during the transmission of the message This is because the re ceiver must be made ready to receive sync byte signalling the beginning of the command file For this reason it is important that the host wait until the entire baud rate message 16 char acters is received before transmitting the sync byte which is equal to FF hex When the loader receives the sync byte the message Loading is displayed on the screen Again the same message is trans mitted to the host and again the host must wait for the entire transmission before starting into the command file If the receiver should intercept a receive error while waiting for the sync byte the entire operation up to this point is aborted The video display is cleared and the message Error x is displayed near the bottom of the screen where x is a letter from B to H meaning parity error framing error parity amp framing errors overrun error par
37. 220 uF 169 Elec 29 4 227 16 318 Capacitor 199 pF 5 Cer NPO CC45CH1H1 LJ 311 Capacitor 47 uF 5 V Poly 5 CQ92P1H472J C313 Capacitor 1000 uF 25V Elec 205 CER 4C198M25V C314 Capacitor 9 933 uF 4 v Poly 5 CQ92P2G333J C315 Capacitor 9 947 uF 4 v Poly l CQ92P2G473K C316 Capacitor 1 uF 25 v Elec 20 CE 4C1 5M25 v C317 Capacitor 01 uF 63 v Poly 10 CQ92P2J1 3K Parts List 9 Video Monitor 879 613 Green Screen Model 4P Computer Capacitor 1 uF 63 v Poly 10 Capacitor 47 uF 1 v Cer Capacitor 22 uF 5 v Cer Capacitor 0 0022 uF 1 Cer Capacitor 18 uF 25V Elec 29 Capacitor 22 uF 5 v Cer Capacitor 0 0022 uF 5 v Cer Capacitor 82 uF 4 Poly 5 Capacitor 228 uF 169 Elec 29 Capacitor 9 991 uF 18889 Cer Diode lfE 1 Silicon Diode 1 1 Silicon Diode VD1221 Varistor Diode VD1221 Varistor Diode BBT4 Silicon Diode BBT4 Silicon Diode BBT4 Silicon Diode Silicon Diode BBT4 Silicon Deflection Yoke IC AN5763 Linear V Processor IC AN5763 Linear H Processor Coil Coil 10 uH Linearity 38 uH Width Not Used Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carbon 1 kohm 1 4W 5
38. 25 2228 NPN 25 536 28C2373 K L NPN Signal Amp Hor Output 183 RD1 4MB S 563J 1 4 5 6R8J RD1 2MB S 1627 1 4 5 4727 RD1 4MB S 2247 1 4 5 3311 1 4 5 8R2J 1 4 5 1 3J 8 6837 RD1 2MB S 1R J RD1 4MB S 193J RD1 4MB S 122J RD1 4 5 2225 RD1 4MB S 1837 1 4 5 3327 RD1 4 5 2237 RD1 4MB S 153J RSM2P1 1J RD1 4MB S 2727 RSM2P56 J RD1 2MB S 823J RD1 2MB S 154J RD1 2MB S 224J RD1 4MB S 1857 RD1 4MB S 2247 31 4245 5 2247 RD1 4MB S 2747 RD1 4MB S 151J RD1 4MB S 151J RC1 2GF1 4K RC1 2GF471K RC1 2GF471K RC1 2GF563K RC1 2GF563K 19851991MA 1789198 25 733 28C1313 G 25 2228 28 536 28C2373 K L Parts List 9 video Monitor 8790612 Model 4P Computer VR2 l Var Resistor 199 kohm 175119139A VR2 2 Var Resistor 20 kohm 1751191994 VR283 Resistor 129 kohm 1751191394 VR3 L Var Resistor 1 kohm 1751199594 VR3 2 Var Resistor 549 kohm 17511 16 A VR3 3 Var Resistor 2 Mohm 17691 93 A 501 Cathode Ray Tube 5598100 40A 184 Parts List 9 Video Monitor 879 613 Green Screen Model 4P Computer 185 Item Description Part Number 1 Assembly CRT 031885 1 Clip Fuse 1973 3 8 A 1 Connector Pin 19411 78 A 1 Fuse 2A 25 v 251 79 A 1 Spring Tension 43471 12 Socket Pin 194010370 1 Socket Cylind
39. 4 74F 50V elect radial 0 047uF 50 63V stacked metal 0 47uF 50 63V stacked metal 0 068uF 50 63V stacked metal luF 50 elect radial 0 001 63V poly 47uF 25V elect radial luF 50V elect radial 2200 10 elect radial 2200uF 109 elect radial 2200 6 3V elect radial 0 01 50 63V stacked metal 100uF 35V elect radial 1000pF 1007 ceramic disc 2200 16V elect radial 0 16 50 63V stacked metal 16V elect radial 100uF 35V elect radial 100uF 25V elect radial 047uF 50 63V stacked metal 0lpF 50 63V stacked metal 470 16V elect radial 0 1uF 250VDC metal poly 2200 16V elect radial 220 200V elect radial Not Used 4700 pF 125VAC ceramic disc 220uF 200V elect radial 4700pF 125VAC ceramic disc 4700pF 125VAC ceramic disc 220F 125VAC ceramic disc 1 250VAC metal paper Not Used Not Used 001 50 63V stacked metal 001uF 630V poly 022 63V poly 165 8709365 8519214 8160402 8326103 8325474 8393474 8394474 8393684 8325014 8392104 8326472 8325014 8328224 8328224 8328220 8393104 8327103 8302106 8328221 8304104 8328331 8327103 8327102 8393474 8393104 8327461 8394106 8328221 8327226 8303475 8327226 8303475 8303475 8393432 8393106 8392014 8392017 8393422 PARTS LIST Power Supply Assembly 8790049 65W 39 022 63V poly 8393422 Diode
40. 5 Cer 10 CK45B1H221K C302 Capacitor 47 5 V Elec 1 4 RB 474K5 v C343 Capacitor 199 pF 5 Cer 10 CK45B1H191K 304 Capacitor 9 922 uF 5 Mylar 19 CQ92M1H223K C3 5 Capacitor 0 018 uF 5 V Mylar 10 CQ92M1H183K C3 6 Capacitor 18 uF 5 V Mylar 10 CQ92M1H183K C387 Capacitor 4 7 uF 587 Elec 29 4 475 50 C3 8 Capacitor 1 uF 59V Mylar 10 CQ92M1H1 3K C3 9 Capacitor 220 uF 16V Elec 20 CE 4C227M16V C31 Capacitor 199 pF 5 Cer NPO CC45CH1H1 LJ C311 Capacitor 47 uF 5 V Poly 5 CQ92P1H472J C313 Capacitor 1999 uF 25V Elec 20 CE 4C1 8M25V C314 Capacitor 33 4 v Poly 5 092 263330 C315 Capacitor 47 uF 4 v Poly 10 092 20473 C316 Capacitor 1 uF 25 v Elec 2 4 105 25 C317 Capacitor l uF 63 v Poly 19 CQ92P2J1 3K DEFLECTION P C B BOTTOM VIEW 177 TRIOS QIO3 MOR SIDE JG 5 26 Wr TT CRTP C B TOP VIEW iS TRIO3 QIO3 CRTP C B BOTTOM VIEW 178 Hifi Biao 5 I
41. 5 v Cer 0 0082 uF 4 v Poly 5 220 uF l6V Elec 20 l uF 19 Cer 1 E l Silicon 19E 1 Silicon VD1221 Varistor VD1221 Varistor BBT4 Silicon BBT4 Silicon BBT4 Silicon 1 Silicon BBT4 Silicon Diode Diode Diode Diode Diode Diode Diode Diode Diode Deflection Yoke IC AN5763 Linear V Processor IC AN5763 Linear H Processor Coil 1 uH Linearity Coil 38 uH Width Not used Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 15 kohm 1 4W 5 Carbon 1 Mohm 1 4W 5 Carbon 228 ohm 1 4W 5 Carbon 33 ohm 1 4W 5 Carbon 91 ohm 1 4W 5 Carbon 47 kohm 1 4W 5 Carbon 1 kohm 1 4W 5 Carbon 1 1 4W 5 Carbon 1 5 kohm 3W 5 Met Oxide 5 6 kohm 1 4W 5 Carbon 4 7 kohm 1 4W 5 Carbon 4 7 kohm 1 4W 5 Carbon 199 ohm 1 4W 5 Carbon 182 CQ92P2J1 3K 45 472 45 2 222 CK45E3A222P CE 4 RP 106 25 CK45E2H222P 45 2 222 092 208220 4 227 16 102 19E 1 19E 1 vD1221 VD1221 BBT4 BBT4 BBT4 BBT1f BBT4 58151 3 A 5763 5763 14341 4 A 14331 14 A RD1 4MB S 153J RD1 4MB S 1 5J 01 4 5 2217 RD1 4MB S 3307 RD1 4MB S 47320 RD1 4MB S 1 2J RD1 4MB S 192J RSM3P152J 53 4348 5 5627 1 4 8 4722 01 4 5 472 RD1 4MB S 1817 Parts List 9 Video Monitor 879 612
42. 8064 MODSEL Video Mode 0 0 64x16 0 1 32x16 1 0 80x24 1 1 40x24 This is the state to be written to latch U89 Signal is inverted before being input to U127 09 0 1 TYNY LXI 508 0 1 TVNNSINI ONIWIL SANIT SANIT TOULNOD SANIT Jaod 854208 dana Laod WHININd ANIT 1104 180 HST TVIN3S TIDIYTO 6 ONY 2583 SNIWIL agram 1 Model 4P Functional Block Di 5 Figure 24 LT NId 9711 MTIZETSU EE GET A V NId 9210 58 3 ps NId LSVA 3884 6T 9210 1544 MTDA 8T LESA lr i NId 6572 L FT NIA 9 ss ETT 581 K T WOT 102 DN z Figure 5 2 System Timing 25 DOLK the reference clock selected is output from 0127 DCLK is fed back into U127 for internal timing reference and is also fed to the clock input 0128 74LS161 0128 is configured to preload with count of 9 each time it reaches count of 0 This generates signal output of TC 128 pin 15 that occurs at the start of every character time of video output TC is used to gen erate LOADS Load Shift Register QA and QC of U128 are used to generate SHIFT XADR7 CRTCLK and LOAD for proper timing for the four video modes QA QB and QC which
43. 919 ohm 1 4W 5 8207191 R25 Resistor 910 ohm 1 4W 5 8207191 R26 Resistor 159 ohm 1 4W 5 8207115 R27 Resistor 19 kohm 1 4W 5 8207310 R28 Resistor 19 kohm 1 4W 5 8207319 R29 Resistor 279 kohm 1 4W 5 8207427 R3 Resistor 20 kohm 1 4W 5 8207320 R31 Resistor 4 7 kohm 1 4W 5 8287247 thru R33 R34 Resistor 3 6 kohm 1 4W 5 8207236 R36 Resistor 128 ohm 1 4 5 8207112 37 Resistor 150 ohm 1 4W 5 8277115 thru R39 R42 Resistor 4 7 kohm 1 4W 5 8207247 R43 Resistor lf kohm 1 4W 5 8207310 R44 Resistor thru 46 1 Resistor Pak 27 ohm 16 8298827 2 Resistor 1 5 1 SIP 8290015 Resistor Pak 150 ohm 1 Pin SIP 8298813 81 Parts List Main PCB Assembly Model 4P Computer U23 U24 U25 U26 U27 028 029 5930 031 032 033 034 035 036 037 038 039 041 042 043 044 045 046 7418123 Multivibrator 7418374 Flip Flop 7415244 Octal Buffer 741538 Quad 2 Input NAND 74LS 8 Quad 2 Input AND 74LS 4 Hex Inverter 74185245 Transceiver 7415244 Octal Buffer 7415367 Hex Driver 741504 Hex Inverter 74LS74 Flip Flop 7418582 2 Input NOR 74532 Quad 2 Input OR MCM68A316E Character ROM 7415244 Octal Buffer 74SLS166 8 Bit Shift Reg 7415175 Quad Flip Flop 74584 Hex Inverter 7418153 Multiplexer 7415244 Octal Buffer 4916 2K x 8 RAM Static 7415157 Multiplexer 68 45 CRTC 7415273 Flip Flop 74LS373 Octal Latch 74LS157 Mu
44. C11 C12 C19 C20 check Q6 Check and or replace CR4 C14 T1 aux check R26 Q4 Q5 VR1 CR1 C1 check Ut R23 C8 R24 check C2 R4 R5 Ut for V ref check R27 R25 C9 Q9 check and or replace U1 U2 C3 5 4 5 Testing and Adjustments The following tests should be performed to guarantee correct operation of the power suply after repairs have been made The first test checks the primary circuits and is to be made without AC power applied The second test is a complete operational test with AC power applied Primary Checks T2 1 NO AC POWER APPLIED 1 Apply 35 volts via 170 ohm 5 watt resistor from Q4 emitter to the primary side of ground Primary side ground is the point labeled 1 the schematic Also apply 35 volts DC via 120k ohm resistor and normally closed SPST switch from Pin 13 of U1 to primary ground Observe the voltage across 14 as it charges it reaches value near 31 volts it should drop to near 16 volts as Q5 and 1 turn on 2 Check U1 pin 8 and or Q7 base for base drive pulse a 40 kHz square wave of 8 4 volts respectively 3 Switch the SPST switch connecting the 120k ohm resistor from Pin 13 of U1 and check for loss of base drive pulses on Q7 Operational Checks T2 U1 U2 APPLY AC POWER 1 Apply rated maximum loading for condition 1 Model II use or condition 2 5 1 4 Hard Disk use 2 Apply 120 VAC input voltage and observe Q7 current via loop on P
45. Figure 5 59 Video Adjustment Figure 5 60 Display a white Screen full screen of the character and adjust the centering magnet on the deflection yoke to make L Figure 5 60 Internal Brightness Adjustment Figure 5 61 Set the remote brightness control to the center position and ad just VR302 to hold the raster at the point at which is first visible VIDEO RASTER Figure 5 61 Video Distortion Adjustment Figures 5 62 5 63 Insert a video distortion correcting magnet onto the magnetic holder if required and rotate it for adjustment Pincushion Barrel Correction Top Bottom and Sides Perform this adjustment if the CRT exhibits the abnormal ef fects shown in Figure 5 62 Step 1 Push the magnet on the yoke mounting pin as shown Figure 5 63 A magnet should be placed only on the pin that corresponds to the affected area Step 2 Rotate the magnet to obtain the desired video display labeled NORMAL on Figure 5 62 Step 3 If the desired video display cannot be obtained replace with a proper magnet mlt re Te 1 iy Ci ADJUSTING 12 07 MAGNET Figure 5 62 Trapezoidal Correction Corners Procedure Perform this adjustment if the CRT exhibits the abnormal ef fects as shown in Figure 5 63 Push magnet onto the yoke mounting pin as shown in Figure 5 63 Magnet should be placed only on the pin that corres
46. NE i Dee ED 1 cui INVERSE 1 vies 8664 lee pt 2 pe te Eea 8 3 qae dms Capone gle I M P some CRE 2007 D pt m _RAMADEN T n 2 ME 4 Romer ENIOBUSINT EI 2 re sa 3 cas 03 61 ENEXTIO 92 120 abi mn 5 et k 44 T TOC lan en lf 34 api r EDER id DISKENE 4 77 vern moon GR EE oura ni em Cs rene aeee p STES ienen Eri een A6 C ORE NA 2 68 31580888 ale 11111111 11111111 un te LI ole una E SEEN 11111111 x sd gt Ter pasenia TM 1 P z oe Ft R R 11111111 11111111 T M Cu 15 use Lx use F I I LI o 0 411111111 11111111 s d Bh 4l 9 TTT PE o E 11111111 LLECLELLI aa du
47. R W ARRAY 64K X4 2 ADDRESS DYNAMIC HS DISPLAY ENABLE MEMORY DATA OUT CLOCK DATA MODEL 4 BUFFER RAS TIMING CAS TIMING MUX SIGNALS S L DOTCLK STROBE LOGIC SHIFT REGISTER GRAPHICS VIDEO Figure 5 65 Model 4 Graphics Controller Block Diagram 190 SELECT R W 2 85 vs ENABLE CLOCK MUX CPU DATA BUS VIDRAMWR OPTIONSWR DECODE XOFFSETWR LOGIC YOFFSETWR VIDRAMRD WAIT CLEAR TIMING 585 CPU SHIFT CPU VIDEO REGISTER amp CONTROL gene LOGIC YCLK GRAPHICS CHARCLK ALPHA OPTIONS REGISTER RAM 4 DATA 1 0 gt VIDRAMWR RAM 8 MEMORY ADDRESS MUX CPU VIDEO Figure 5 66 Block Diagram 191 1 CAS S ET E STROBEL 1 1 1 STROBE2 Figure 5 67 Model 4 Graphics Timing Diagram PALIOL8 Inputs Outputs 1 DCLK 12 CAS 2 13 RAS 31 14 VIDRAMWR 4H 15DI 5 BDI 16 STRB1 6 17 CLK 18 STRB2 8 BCLK 19 XADR7 9 DJ 11 Equations CAS FP H BDI DJ RAS X VIDRAMWR GEN IIN STRB1 H BDI DCLK CLK DCLK STRB2 XADR7 I DJ ly Figure 5 68 192 One unusual feature of the system timing is the CAS signal CAS is clocked twice for each RAS cycle This allows eight bits of d
48. RESET not needed 0 Reset Asserted Problem 1 Reset Negated D6 MOTOROFF 0 Motoroff Asserted 1 Motoroff Negated D7 INTRQ 0 Asserted 1 INTAQ Negated Name WRINTMASKREG Port Address 0 Access WRITE ONLY Description Output INT Latch 20 01 RESERVED 02 0 Real time interrupt disabled 1 Real time clock interrupt enabled D3 ENIOBUSINT 0 External IO Bus interrupt disabled 1 External IO Bus interrupt enabled D4 ENXMITINT 0 5232 Xmit Holding Reg empty int disabled 1 232 Xmit Holding Reg empty int enabled D5 D6 D7 Name ENRECINT 0 85232 Rec Data Reg full int disabled 1 85232 Rec Data Reg full int enabled ENERRORINT 0 5232 UART Error interrupts disabled 1 5232 UART Error interrupts enabled RESERVED RDINTSTATUS Port Address 0 Access READ ONLY Description Input INT Status 00 01 02 03 04 05 06 07 RESERVED IOBUS INT 232 XMIT INT 232 REC INT 85232 ERROR INT RESERVED BOOT Port Address 9C 9F Access WRITE ONLY Description Enable or Disable Boot ROM 00 01 07 0 Boot ROM Disabled 1 Boot ROM Enabled RESERVED 90 93 Access WRITE ONLY Description Sound output 00 01
49. Set Transfer Address to 43998 Note 2 Errors while loading ROM Image Display Set Transfer Error Address at end Message of ROM Image Normally 3 15H Note 2 ROM Image Present Note 3 92 ROM Image Present lt P gt pressed 2 Display ROM Image is loaded message Wait for lt ENTER gt or BREAK to be pressed Write protect memory Mode f Set CPU speed to 2MHz 93 Switch boot ROM out of Memory jump to Transfer Address Initialize RS 232 Port Note 6 Wait for Carrier Detect Determine Correct Baud Rate Transmit Baud Rate Detect Message wait for Sync Byte FFH Load program from RS 232 Display and transmit error Transfer control to address received Notes 1 If the boot sector was not 256 bytes in length then it is as sumed to be a Model package and the ROM image will be needed If the sector is 256 bytes in length then the sector is scanned for the sequence CDxx00H The is the first byte of a Z80 unconditional subroutine call The next byte can have any value The third byte is tested against a zero What this check does is test for any refer ences to the first 256 bytes of memory Radio Shack Model operating systems and many other packages all reference the ROM at some point during the b
50. be pressed Write protect memory Mode Set CPU speed to 2 2 32 Switch boot ROM out of Memory Jump to Transfer Address Initialize RS 232 Port Note 6 Wait for Carrier Detect Determine Correct Baud Rate Transmit Baud Rate Detect Message wait for Sync Byte FFR Load program from RS 232 Display and transmit error Transfer control to address received Notes 1 If the boot sector was not 256 bytes in length then it is as sumed to be a Model ill package and the ROM image will be needed the sector is 256 bytes in length then the sector is scanned for the sequence CDxx00H The CD is the first byte of a Z80 unconditional subroutine call The next byte can have any value The third byte is tested against a zero What this check does is test for any refer ences to the first 256 bytes of memory All Radio Shack Model operating systems and many other packages all reference the ROM at some point during the boot sector Most boot sectors will display a message if the system can not be loaded To save space these routines use the Model ROM calls to display the message Several ROM calls have their entry points in the first 256 bytes of mem and these references are detected by the boot ROM Packages that do not reference the Model ROM in the boot sector can still cause the Model III R
51. controls the CPU access by causing the CPU to WAIT till video is in retrace area before allowing any writes or reads to Graphics Board RAM ENGRAF is asserted when Graphics video is displayed ENGRAF also disables inverse video mode on Main Logic Board Video CL166 Clear 74L166 is used to enable or disable mixing of Main Logic Board Video and Graph ics Board Video If CL166 is negated high then mixing is al lowed in all for video modes 80 x 24 40 x 24 64 x 16 and 32 x 16 If CL166 is asserted low this will clear the video shift reg ister U63 which allows no video from the Main Logic Board In this state 8064 is automatically asserted low to put screen in 80 x 24 video mode Refer to Figure 5 16 Graphic Board Video Timing for timing relationships Refer to the Model 4 4P Graph ics Board Service information for service or technical informa tion on the Graphics Board 5 2 13 Sound The sound circuit in the Model 4P is compatible with the Sound Board which was optional in the Model 4 Sound is generated by alternately setting and clearing data bit DO during an OUT to port 90H The state of DO is latched U129 1 2 of 741 574 and the output is amplified by Q2 which drives 80 speaker The speed of the software loop determines the frequency and thus the pitch of the resulting tone Since the Model 4P does not have a cassette circuit some existing software that used the cassette output for sound would have been lost The Mo
52. 1773 FDC chip Port No Function FOH Command Status Register F1H Track Register F2H Sector Register F3H Data Register 5 2 16 RS 232 C Circuit RS 232C Technical Description The RS 232C circuit for the Model 4P computer supports asynchronous serial transmissions and conforms to the EIA RS 232C standards at the input output interface connector The heart of the circuit is the TR1865 Asynchronous Receiver Transmitter U33 It performs the job of converting the parallel byte data from the CPU to a serial data stream including start stop and parity bits For a more detailed de scription of how this LSI circuit performs these functions re fer to the TR1865 data sheets and application notes The transmit and receive clock rates that the TR1865 needs are supplied by the Baud Rate Generator U73 BR1943 This circuit takes the 5 0688 MHz supplied by the system timing circuit and the programmed information received from the CPU over the data bus and divides the basic clock rate to provide two clocks The rates available from the BRG go from 50 Baud to 19200 Baud See the BRG table for the complete list 124 BRG Programming Table Transmit Receive Supported Nibble Baud 16X by Loaded Rate Clock SETCOM OH 50 0 8 kHz Yes 1H 75 1 2 kHz Yes 2H 110 1 76 kHz Yes 3H 134 5 2 1523 kHz Yes 4H 150 2 4 kHz Yes 5H 300 4 8 kHz Yes 6H 600 9 6 2 Yes 7H 1200 19 2 kHz Yes 8H 1800 28 8 kHz Yes 9H 2000 32 081 kHz Yes AH 2400 38 4 kHz Yes B
53. 5 2 5 2 Port Map Decoding Port Map Decoding is accomplished by Gate Array 4 2 U106 U106 decodes the low order address A0 A7 from the CPU and decodes the port being selected signal allows the CPU to read from a selected port and the OUT signal allows the CPU to write to the selected port Refer to Port Assignment 5 2 6 ROM The Model 4P contains only a 4K x 8 Boot ROM U69 This ROM is used only to boot up a Disk Operating System into the RAM memory If Model operation or DOS is required then the RAM from location 0000 37FFH must be loaded with an im age of the Model II or 4 ROM code and then executed A sys tem program called MODEL is supplied with the Model 4P to provide the ROM image for proper Model Ill operation On power up the Boot ROM is selected and mapped into location 0000 If the Boot ROM is not required after boot up the Boot ROM must be mapped out by OUTing to port 9CH with DO set or by selecting Memory Map modes 2 or 3 In Mode 1 the RAM is write enabled for the full 14K This allows the RAM area mapped where Boot ROM is located to be written to while ex ecuting out of the Boot ROM Refer to Memory Maps The Model 4P Boot ROM contains all the code necessary to initialize hardware detect options selected from the keyboard read a sector from a hard disk or floppy and load a copy of the Model ROM Image as mentioned into the lower 14K of RAM 87 The firmware is
54. 68A332 4 X 8 300NS ROM 8075332 70 7415245 Tranceiver 8020245 072 7415244 Octal Buffer 8020244 073 1943 Clock Gen 8040943 077 7416 Inverter 8000016 078 74185240 Octal Buffer 8020240 NOTE Starred IC to be socketed 139 Parts List Model 4P Gate Array PC Board Sym Description Part Number 081 7415157 Multiplexer 8020157 082 4016 2K X 8 RAM Static 20045 8040116 083 7418373 Octal Latch 8020373 084 7415244 Octal Buffer 8020244 085 7416273 Octal Flip Flop 8020273 086 7415245 Tranceiver 8020245 087 74F04 Inverter 8015004 088 741611 Triple 3 AND 8020011 089 741527 Triple 3 NOR 8020027 091 741504 Inverter 8020004 092 741500 Quad 2 8020000 094 Delay Line 8429020 U95 741 504 Inverter 8020004 U96 741532 Quad 2 In OR 8020032 U98 741874 Flip Flop 8020074 0101 7415283 Binary Adder 8020283 0102 4 3 Video Support Array 8040543 U103 IC MCM68A316E Character ROM 8049007 0104 741 504 Inverter 8020004 0105 741532 Quad 2 In 8020032 0106 IC 4 2 Address Decode Array 8040542 0108 7418551 AND OR Invert 8020051 0109 741 502 2 NOR 8020002 0110 7415157 Multiplexer 8020157 0111 7415157 Multiplexer 8020157 0114 74564 AND OR Invert 8010064 0115 74532 Quad 2 In OR 8010032 0116 745112 2 Flip Flop 8010112 0117 74F0
55. Boot Sector Size 1 for 256 2 for 512 4057H RS 232 Baud Rate only valid RS 232 boot 4059H Function Key Selected 0 No function key selected F1 or lt 1 gt 86 F2 or lt 2 gt 87 F3 or lt 3 gt 88 85 84 lt Left Shift gt 82 lt Right Shift gt 83 Reserved 80 81 and 89 90 405BH Break Key Indication non zero if lt Break gt pressed 405CH Disk type 0 for LDOS TRSDOS 6 1 for TRSDOS 1 Keep in mind that Model ROM image will initialize these areas so this information is useful only to the Model 4 mode programmer 5 1 7 RAM Two configurations of Random Access Memory RAM are available on the Model 4P 64K and 128K The 64K and 128K Option use the 6665 type 64K x 1 200NS Dynamic RAM which requires only a single 5v supply voltage 37 The DRAMs require multiplexed incoming address lines This is accomplished by ICs U111 and U112 which are 74LS157 multiplexers Data to and from the DRAMs are buffered by 74LS245 U117 which is controlled by Page Map PAL U110 The proper timing signals RASO RAS1 and are generated by a delay line circuit U97 U115 1 2 of a 748112 and 0116 1 4 of a 74 08 are used the generate a precharge circuit During M1 cycles of the 280 in 4 MHz mode the high time in MREQ has a minimum time of 110 nanosecs The spec ification of 6665 DRAM requires a minimum of 120 nanosecs so this circuit will shorten the signal dur
56. CDO and CD1 of the FDDS chip control the divisor which divides REFCLK With DC1 grounded logic low CDO when a logic low generates a di vide by 1 for MFM mode and when logic high generates a di vide by 2 for FM mode CDO is controlled by the signal DDEN which is Double Density enable or MFM enable The FDDS de tects the leading edges of RD pulses and adjusts the phase of the internal clock to generate the separated clock SEPCLK to the FDC chip The separate long and short term timing correc tors assure the clock separation to be accurate The separated Data SEPD is used as the RDD input to the chip Floppy Disk Controller Chip The 1793 is an MOS LSI device which performs the functions of a floppy disk formatter controller in a single chip implemen tation The following port addresses are assigned to the internal registers of the 1793 FDC chip Port No Function FOH Command Status Register Track Register F2H Sector Register F3H Data Register 5 1 16 RS 232 C Circuit 85 232 Technical Description The RS 232C circuit for the Model computer supports asyn chronous serial transmissions and conforms to the EIA RS 232C standards at the input output interface connector J4 The heart of the circuit is the TR1865 Asynchronous Receiver Transmitter 030 It performs the job of converting the parallel byte data from the CPU to a serial data stream including start Stop and parity bits For a more detailed des
57. Carbon 1 kohm 1 4W 5 Carbon 1 5 kohm 3W 5 Met Oxide 5 6 kohm 1 4W 5 Carbon 4 7 kohm 1 4W 5 Carbon 4 7 kohm 1 4W 5 Carbon 199 ohm 1 4W 5 Carbon 15 kohm 1 Mohm 220 ohm 33 ohm 91 ohm 47 kohm CQ92P2J193K 45 472 45 2 222 45 222 4 186 M25V 45 2 222 45 2 222 CQ92P26G822J 4 227 16 45 1 2 1 1 10 1 01221 vD1221 4 4 4 BBT19 BBT 4 58151903 9 5 763 5763 14341 4 A 14331 14 A RD1 4MB S 1539 1 4 5 1 5J RD1 4MB S 221 7 1 4 8 3307 1 4 5 4730 RD1 4MB S 172 1 4 8 1720 RSM3P152J RD1 4MB S 562J RD1 4MB S 472J 1 4048 8 472 RD1 4MB S 1017 Parts List 9 Video Monitor 8790613 Green Screen Model 4P Computer Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Transformer Transformer IC IC IC IC IC 25 733 PNP 28C1313 G 28C2228Y E 25 536 NPN Signal Amp 298C2373 K L NPN Hor Output 1 4W 5 Carbon 1 4W 5 Carbon 1 2W 5 Carbon 1 4W 5 Carbon 1 4W 5 Carb
58. Data Reg full int enabled D6 ENERRORINT 0 85232 UART Error interrupts disabled 1 RS232 UART Error interrupts enabled 07 RDINTSTATUS Port Address 0 Access READ ONLY Description Input INT Status 00 01 RESERVED 02 03 IOBUS INT 04 232 05 RS232 REC INT D6 RS232 UART ERROR INT D7 RESERVED Name BOOT Port Address 9C 9F Access WRITE ONLY Description Enable or Disable Boot ROM 0 ROM Disabled 1 Boot ROM Enabled 01 07 RESERVED Port Address 90 93 WRITE ONLY Description Sound output Do SOUND DATA Di D7 RESERVED 110 Port Address 84 Access WRITE ONLY Description Output to operation reg DO SELO 1 SEL1 SELO MODE 0 0 0 0 1 1 1 0 2 1 1 3 02 8064 0 64 character mode 1 80 character mode D3 INVERSE 0 Inverse video disabled 1 Inverse video enabled D4 SRCPAGE Points to the page to be mapped as new page 0 U64K L32K Page 1 U64K U32K Page D5 ENPAGE Enables mapping of new page 0 Page mapping disabled 1 Page mapping enabled D6 DESPAGE Points to the page where new page is to be mapped 0 L64K U32K Page 1 L64K L32K Page D7 PAGE 0 Page 0 of Video Memory 1 Page 1 of Video Memory 111 5 2 8 Video Circuit The heart of the video display c
59. WRITE ONLY Description Output to FDC Control Registers Port FO FDC Command Register Port F1 FDC Track Register Port F2 Sector Register Port F3 FDC Data Register Refer to FDC Manual for Bit Assignments Name DISKIN Port Address FO Access READ ONLY Description Input FDC Control Registers Port FO Status Register Port F1 Track Register Port F2 Sector Register Port F3 FDC Data Register Refer to FDC Manual for Bit Assignment Name MODOUT Port Address EC EF Access WRITE ONLY Description Output to Configuration Latch 00 RESERVED 01 CASSMOTORON Sound enable 0 Cassette Motor Off Sound enabled 1 Cassette Motor On Sound disabled D2 MODSEL 0 64 or 80 character mode 1 32 or 40 character mode D3 ENALTSET 0 Alternate character set disabled 1 Alternate character set enabled D4 ENEXTIO 0 External Bus disabled 1 External Bus enabled D5 RESERVED D6 FAST 0 2 MHZ Mode 1 4 MHZ Mode D7 RESERVED Name RTCIN Port Address EC EF Access READ ONLY Description Clear Real Time Clock Interrupt 00 07 DONT CARE Name RS2320UT Port Address E8 Access WRITE ONLY Description UART Control Data Control Modem Control BRG Control Port EB UART Master Reset Port E9 BAUD Rate Gen Register Port EA UART Control Register Modem Control Reg Port EB UART Transm
60. X and Y ad dress register and then read or write to the desired location However the options control register allows the programmer to Set the graphics board for automatic incrementing or decre menting of memory addresses This makes it easy to use only 2 single accesses to memory for most situations A new feature provided by the Model 4 graphics board is the ability to scroll in a vertical or horizontal direction Scrolling in the horizontal direction is controlled by the X offset register This register scrolls one character 8 bits for each increment or decrement of value Scrolling in the vertical direction is con trolled by the Y offset register This register scrolls one line for each increment or decrement of value The following summarizes the features of the board in an I O map format Port Addressing Address Decimal Function 80 128 Write the X register address 0 127 81 129 Write the Y register address 0 255 82 130 Read write to the graphics memory specified by the X and Y address register 83 131 Write to the options control register 8c 140 Write to the X address offset register 8D 141 Write to the Y address offset register 8E 142 Write to the intermix control register Options Control Register Description Hex Address 83 Bit 0 0 Graphics OFF 1 Graphics ON Bit 1 0 Waits OFF 1 Waits ON Bit 2 0 Increment x Reg 1 Decrement x Reg Bit 3 0 Increment Y Reg 1 Decrement Reg 8
61. a four bit synchronous counter U128 7415161 These two ICs gen erate all the necessary timing signals for the four video modes 64 x 16 32 x 16 80 x 24 and 40 x 24 Two reference clock sig nals are required for the four video modes One reference clock the 10 1376 MHz signal 10M is generated by U126 and is used by the 64 x 16 and 32 x 16 modes The second refer ence clock is a 12 672 MHz 12M signal which is generated by Phase Locked Loop PLL circuit and is used by the 80 x 24 and 40 x 24 modes The PLL circuit consists of U147 74LS93 U148 NE564 PLL and U149 74LS90 The original 20 2752 MHz clock is divided by 16 through 0147 which generates 1 2672 MHz signal The output of U147 is reduced in amplitude by the voltage divider network R27 and R28 and the output is coupled to the reference input of U148 by C227 The PLL NE564 is adjusted to oscillate at 12 672 MHz by the tuning capacitor C231 This 12 672 MHz clock is then divided by 10 through U149 to generate a second 1 2672 MHz signa which is fed to a second input of U148 The two 1 2672 MHz signals are compared internally to the PLL where it corrects the 12 672 MHz output so it is synchronized with the 20 2752 MHz clock MODSEL and 8064 signals are used to select the desired video mode 8064 controls which reference clock is used by 0127 and MODSEL controls the single or double character width mode Refer to the following chart for selecting each video mode
62. are referred to as and J are fed to the Graphics Port J7 for reference timings of Hires graphics video Refer to Video Tim ing Figs 5 3 and 5 4 for timing reference 5 1 5 Address Decode The Address Decode section will be divided into two subsec tions Memory Map decoding and Port Map decoding 5 1 5 1 Memory Map Decoding Memory Map Decoding is accomplished by a 16L8 PAL U109 Four memory map modes are available which are compatible with the Model lil and Mode 4 microcomputers second 1618 PAL U110 is used in conjunction with U109 for the memory map control which also controls page mapping of the 32K RAM pages Refer to Memory Maps below 5 1 5 2 Port Map Decoding Port Map Decoding is accomplished by three 74151385 U87 088 and 0107 These ICs decode the low order address 0 A7 from the CPU and decode the port being selected The IN signal from U108 enables U87 which allows the CPU to read from a selected port and the signal also from 0108 en ables U88 which allows the CPU to write to the selected port 0107 only decodes the address and the and OUT signals are ANDed with the generated signals 5 1 6 ROM The Model 4P contains only a 4K x 8 Boot ROM U70 This ROM is used only to boot up a Disk Operating System into the RAM memory If Model il operation or DOS is required then the RAM from location 0000 37FFH must be loaded with an im age of the Model or 4 ROM code and then execute
63. can be generated by NANDing IN and the I O port address Output port device use is the same as the input port device in use in that the external I O devices must be enabled by writing to port OECH with bit 4 on in the user software in the same fashion For either input or output devices the IDBUSWAIT control line can be used in the normal way for synchronizing slow devices to the CPU Note that since dynamic memories are used in the Model 4P the wait line should be used with caution Holding the CPU in a wait state for 2 msec or more may cause loss of mem ory contents since refresh is inhibited during this time It is rec ommended that the IOBUSWAIT line be held active no more than 500 psec with 25 duty cycle The Model 4P will support Z80 Mode 1 interrupts RAM jump table is supported by the LEVEL BASIC ROMs image and the user must supply the address of his interrupt service routine by writing this address to locations 403E and 403F When an in terrupt occurs the program will be vectored to the user sup plied address if Bus interrupts have been enabled To enable Bus interrupts the user must set bit 3 of Port OEOH 5 2 15 FDC Circuit The TRS 80 Model 4P Floppy Disk Interface provices a stan dard 5 1 4 floppy disk controller The Floppy Disk Interface supports both single and double density encoding schemes Write precompensation can be software enabled or disabled beginning at any track although th
64. data re ceived by the UART to a test byte equal to 55 hex The receive is first set to 19200 baud If ten bytes are received which are not equal to the test byte the baud rate is reduced This sequence is repeated until a valid test byte is received If ten failures occur at 50 baud the entire process begins again at 19200 baud If a valid test byte is received the program waits for ten more to ar rive before concluding that it has determined the correct baud rate If at this time an improper byte is received or a receiver er ror overrun framing or parity is intercepted the task begins again at 19200 baud In order to get to this point the host or the modem must assert CD true The host must transmit a sequence of test bytes equal to 55 hex with 8 data bits odd parity and 1 or 2 stop bits The test bytes should be separated by approximately 0 1 second to avoid overrun errors When the program has determined the baud rate the message Found Baud Rate is displayed on the screen where x is a letter from A to P meaning 50baud 150 1800 M 4800 B 75 300 2000 7200 110 600 2400 9600 0 134 5 1200 L 3600 19200 The same message less the character signifying the baud rate is transmitted to the host with the same baud rate and protocol This message is the signal to the host to stop transmitting test bytes After the program has transmitted the baud r
65. describe the operation of the Flyback Converter cir cuit For the purpose of this discussion we will assume that the duration of the ON time equals the duration of the OFF time and Vo rated output voltage Figure 5 35 Basic Flyback Converter 143 ON 1 Switch 1 1 1 time microsec e uk Timi t ming T ta amps 4xIav Isw volts 2xVin Bai vin pk vin av4 Vsw te time microsec time microsec volts 2xVin pk n Vo Vin av n 1 am I 4 10 1 1 1 19 1 1 gt time microsec time microsec Figure 5 36 When the switch is closed ON at time ta Vin is impressed across the primary winding of inductor L and the current Isw in creases linearly from zero until the switch opens OFF at time tb Note that Isec is zero while the switch is closed This is be cause Vsec is negative with respect to Vo thus reverse biasing diode D Note that Vsw is also zero while the switch is closed When the switch opens at time tb the magnetic field of L in stantly collapses and reverses polarity At this moment Vsw is equal to Vin plus the voltage across L just before the switch opened also equal to Vin Therefore at the instant the mag net c field reverses polarity Vsw 2Vin 144 During the interval when the switch is open tb to tc th
66. disk drive is not available 7 Drive Not Ready and no Index Disk in drive door open 8 Error 9 Seek Error 11 Lost Data 12 ID Not Found Display String RST 10H Accepts HL Pointer to text to be displayed Text must be terminated with null 0 DE Offset position on screen where text is to be displayed A 0000H will be the upper left hand cor ner of the display Returns Success Always A Altered DE Points to next position on video HL Points to the null 0 Display Block 18H Accepts HL Points to control vector in the format 0 Screen Offset 2 Pointer to text terminated with null 4 Pointer to text terminated with null n word FFFFH End of control vector or n word FFFEH Next word is new Screen Offset If Z flag is set on entry then the first screen offset is read from DE instead of from the control vector Each string is positioned after the previous string unless entry is found This is used heavily in the ROM to re duce duplication of words in error messages Returns Success Always DE Points to next position on video Byte Fetch RST 20H Accepts None Returns 2 Success byte NZ Failure error code in Errors Any errors from the disk call and 2 ROM Image can t be loaded Too many extents 10 ROM Image can t be loaded Disk drive is not ready File Loader RST 288 None Returns 2 Success NZ Failure error code in Errors Any
67. in Figure 5 44 a functions exactly as described earlier in the Basic Principle section That is the switch Q7 is controlled by the base drive waveform developed by the control section shut down control kick start reset Control Bus R33 Latch 99 Detector c Current Limit Sense Figure 5 44 Primary Side Protection 153 Snubber Circuit Practical transformers cannot couple 100 of the stored en ergy from the primary to the secondary since all of the flux from the primary fails to link all the secondary turns A circuit using this practical transformer behaves as though a small fraction of the primary inductance was not wound on the core of the trans former but instead placed apart from the primary and in series with it This small separately acting inductance does not par ticipate in the transformer action and is called the leakage inductance If the resonant circuit consisting of this leakage inductance and the stray capacitance in the adjacent circuit has sufficient Q relatively low resistance losses a damped oscillation will oc cur in this resonant circuit when the transistor switch opens The peak value of this oscillation will add to the Vce 2 x Vin which appears across the transistor switch just after turn off The combined peak Vce may exceed the transistor breakdown rating if not damped out by the action of a snubber circuit When Q7 turns off the energy stored in the le
68. in that it can be disas sembled in major component blocks after removal of the case cover These major component blocks include the disk drives the power supply main CPU board the CRT display and the monitor board Accessory components such as the power cord additional diskettes and operating manual can be stored in convenient recesses in the removable front cover base This cover base provides protection for the CRT and disk drives dur ing transport It also serves as the base in the non operating po sition of the computer The cover base is held in place with snap locks on each side These locks are positive action with protective boss to vent accidental opening of the cover base To remove merely unsnap the lock and release the catch from the main assembly latch The following procedures are noted in sequential order required to provide access to some of the components Some parts removal does not require previous steps Those which do are noted For reassembly of unit reverse order of disassembly instructions 1 main assembly of the Model has removable cover which allows access to all internal components when removed Remove all connections to the rear of the unit These include the AC power cord printer cable port connector and RS 232 C connector The printer cable and port connectors are edge card type connectors ex ercise care in their removal 2 Place the unit Bezel CRT face down
69. levels the auxiliary power supply provides the required DC voltage to op erate the control section The latch is reset when the current limit or under voltage sensors operate thus removing DC volt age to the Control IC There are four secondary or output voltages in addition to the auxiliary supply 5 05 volt 12 volt CRT 12 volt Disk and 12 volt The 5 05 and 12 DISK voltages are regulated by the control circuit response to the frequency compensated feedback control signal which comes from the load sense sec tion Since the load sensing occurs on the secondary side an optical coupler circuit is necessary to provide safety isolation between the primary side common ground and the secondary Side common ground All secondary voltages including the auxiliary 12 voltage share the same magnetic flux linkage in the transformer core and are controlled by the flyback inductor Any change in sec ondary load currents cause a change in the shared magnetic flux This change in the flux of the inductor sets up an EMF electromotive force which causes a flux in opposition to the one which resulted from the change in load current Thus the original change tends to be counteracted and the current deliv ered to the load remains constant 146 The output filters reduce the remaining ripple voltage compo nents of the AC line and switching frequencies to levels low enough to prevent interference with the circuits operated by the su
70. mem ory map of the system is set to Mode 0 See Memory Map for details This will cause the Z80 to fetch instructions from the boot ROM The Initialization section of the Boot ROM now performs these functions Disables maskable and non maskable interrupts nterrupt mode 1 s selected Programs the CRT Controller Initializes the boot ROM control areas in RAM Sets up a stack pointer Issues a Force Interrupt to the Floppy Disk Controller to abort any current activity Sets the system clock to 4mhz Sets the screen to 64 x 16 9 Disables reverse video and the alternate character sets 10 Tests for lt gt key being pressed 11 Clears all 2K of video memory N This is a specia test If the lt gt is being pressed then control is transferred to the diagnostic package in the ROM All other keys are scanned via the Keyboard Scanner ee p LHOVX o dere Rn TOLD mo router ail wwe 2 Ip du MMM MMM nnn rr 80 24 Figure 5 3 Video Timing 64 x 16 Mode 27 183 i r cc jc xQVO T mum I xSQVOT NOT 40 24 Mode 32 16 Figure 5 4 Video Timing 28 Keyboard scanner is now called It scan
71. power cord If okay go to 3 if bad replace or repair 3 Check power switch and bulb If okay go to 1 if bad replace power switch or bulb 4 Wait a few seconds for CRT to warm up Adjust brightness and contrast at the front of console If video display comes on go to 9 if not go to 5 5 Check power switch If okay go to 6 if bad replace 6 Checkfor AC power at input to power supply If okay go to 7 if bad replace or repair AC wiring harness 7 Check power supply for correct output voltages Refer to Power Supply Section 5 4 If okay go to 8 if bad refer to Power Supply Troubleshooting 5 3 4 8 Checkfor video and sync signals from Main Logic Board at J9 Refer to CPU Board Section and Schematic If okay refer to CRT Display Adjustment Section 5 5 2 if bad refer to CPU Board Troubleshooting Section 5 1 17 or 5 2 17 9 Does message The Floppy Disk Drive 15 Not Ready ap pear If yes go to 15 if not go to 10 19 11 12 13 14 15 16 17 18 19 Does message Close the Floppy Drive Door And Try Again appear If yes go to 17 if not go to 11 Does message The Floppy Disk Drive Is Not Available appear If yes then go to 19 if not go to 12 Does message CRC Error Try Again Or Use Another Disk appear If yes then go to 19 if not go to 13 Does message Seek Error Try Again Or Use Another Disk appear If yes then go to 19 if not go to 14 Does any other message appea
72. present The next test is to check two bytes at location 000 If these addresses contain E9E1H then the ROM image is considered to be present 4 See Disk Director Searcher for more information 5 See File Loader for more information 6 The RS 232 loader is described under RS 232 Boot Disk Directory Searcher When the ROM image is to be loaded it is always read from the floppy in drive 0 Before the operation begins some checks are made First the boot sector is read in from the floppy and the first byte is checked to make sure it is either FEH If the byte contains some other value no attempt will be made to read the ROM image from that disk The location of the directory cylinder is then taken the boot sector and the type of disk is deter mined This is done by examining the Data Address Mark that was up by the Floppy Disk FDC during the read of the sector if the DAM equals 1 the disk a TRSDOS 1 x style disk If the DAM equals 0 then the disk is LDOS 5 1 TRSDOS 6 style disk This is important since TRSDOS 1 disks number sectors starting with 1 and LDOS style disks number sectors starting with 0 Once the disk type has been determined an extra test is made if the disk is a LDOS style disk This test reads the Granule Al location Table GAT to determine if the disk is single sided or double sided The directory is then read one recor
73. rising edge of DRVSEL also triggers a one shot 1 2 of U54 74LS123 which produces a Motor On to the disk drives The duration of the Motor On signal is approxi mately three seconds The spindle motors are not designed for continuous operation Therefore the inactive state of the Motor On signal is used to clear the Drive Select Latch which de se lects any drives which were previously selected The Motor On one shot is retriggerable by simply executing another OUT in struction to the Drive Select Latch Wait State Generation and WAITIMOUT Logic As previously mentioned a wait state to the CPU can be initi ated by an OUT to the Drive Select Latch with D6 set Pin 5 of U98 will go high after this operation This signal is inverted by 1 4th of U79 and is routed to the CPU where it forces the Z80A into a wait state The Z80A will remain in the wait state as long as WAIT is low Once initiated the will remain low until one of five conditions is satisfied One half of U77 a five input NOR gate is used to perform this function INTQ RE SET CLRWAIT and WAITIMOUT are the inputs to the NOR gate If any one of these inputs is active logic high the output ofthe NOR gate U77 pin 5 will go low This output is tied to the clear input of the wait latch When this signal goes low it will clear the Q output U98 pin 5 and set the Q output U98 pin 6 This condition causes WAIT to go high which allows the 780 to exit the
74. routine to not load the Model ROM image even if it appears that ihe operating system being booted requires it lt N gt 29 Instructs the Control routine to load the Model ROM image even if it is already loaded This is useful if the ROM image has been corrupted or when switch ing ROM images Note that this will not cause the ROM image be loaded if the boot sector check indicates that the Model ROM image is not needed Press lt F3 gt lt L gt to accomplish that The Selection group used determining which file will be read from disk when the ROM image is loaded For details of this operation see the Disk Directory Searcher If more than one of the Selection group keys are pressed the last one de tected will be the one that is used The Miscellaneous keys are lt Break gt Pressing this key is simply re corded by setting location 405BH non zero It is up to an operating system to use this flag if desired Terminates the Keyboard rou tine Any other keys pressed up to that time will be acted upon lt Enter gt is useful for experi enced users who do not want to wait until the keyboard timer expires Enter The Control section now takes over and follows the following flowchart Begin 1 Goto 1 Hard Disk Boot lt F2 gt or lt 2 gt pressed Goto 2 Floppy Disk Boot
75. supply it discharges toward zero Why is it important to shut down the supply if the input AC line drops below 90 volts The answer will become clear when an inherent characteristic of the circuit is discussed namely its negative input resistance Imagine the situation where the supply is delivering full power to its load and the AC input voltage drops five or ten volts The supply control circuit responds by increasing the time of the switching transistor thus increasing the average current in the primary winding The only way the DC supply can deliver more current is to draw it from the AC line So the negative change in AC input voltage was accompanied by a positive change in AC input current Another way to describe this characteristic is that the supply is a constant power device that is Pin Vinxlin constant Thus if V decreases will increase and vice versa The supply will thus draw more and more current from the AC line if the AC voltage continues to decrease In order to limit the average cur rent to a safe value the control circuit senses the input voltage and shuts down the supply before the AC voltage level be comes too low or the AC current input becomes too high Secondary Outputs Each of the secondary windings consist of a half wave rectifier followed by a pi filter The input capacitor of the filter stores the charge delivered to it when the rectifier is biased ON by the larity of the tra
76. three seconds The spindle motors are not designed for continuous operation Therefore the inactive state of the Motor On signal is used to clear the Drive Select Latch which de se lects any drives which were previously selected The Motor On one shot is retriggerable by simply executing another OUT in struction to the Drive Select Latch Wait State Generation and WAITIMOUT Logic As previously mentioned a wait state to the CPU can be initi ated by an OUT to the Drive Select Latch with D6 set Pin 18 of U18 will go high after this operation This signal is inverted by 1 4th of U15 and is routed to the CPU where it forces the 280A into a wait state The Z80A will remain in the wait state as long as WAIT is low Once initiated the WAIT will remain low until one of five conditions is satisfied If INTRQ DRQ and RESET inputs become active logic high it causes WAIT to go high which allows the 280 to exit the wait state An internal timer in U18 serves as a watchdog timer to insure that a wait condition will not persist long enough to destroy dynamic RAM contents This internal watchdog timer logic will limit the duration of a wait to 1024 5 even if the FDC chip should fail to generate DRQ or an INTRQ If an OUT to Drive Select Latch is initiated with O6 reset logic low a WAIT is still generated The internal timer in U18 will count to 2 which will clear the WAIT state This allows the WAIT to occur only during the OUT instru
77. to be executed Restart RAM Location Default Use 0 Cold Start Boot 8 4000H Disk Request 10 4003H Display string 18 4006H Display block 20 4009H Byte Fetch Called by Loader 28 400CH File Loader 30 400FH Keyboard scanner 38 4012H Reserved for future use 66 4015H NMI Floppy Command Complete The above routines have fixed entry parameters These are de scribed here Disk Request RST 8H Accepts A 1 for floppy 2 for hard disk B Command Initialize 1 Restore 4 Seek 6 Read 12 All reads have an im plied seek Sector number to read The contents of the location disktype 405CH are added to this value before an actual read If the disk is two sided floppy just add 18 to the sector number DE Cylinder number Only E is used in floppy operations HL Address where data from a read opera tion is to be stored Returns 2 Success Operation Completed NZ Error Error code in Error Codes 3 Hard Disk drive is not ready 4 Fioppy disk drive is not ready 5 Hard Disk drive is not available 6 Floppy disk drive is not available 7 Drive Not Ready and no Index Disk in drive door open 8 CRC Error 9 Seek Error 11 Lost Data 12 ID Not Found Display String RST 10H Accepts HL Pointer to text to be displayed Text must be terminated with a null 0 DE Offset position on screen where text is to be displayed A 0000H will be the upper left hand cor ner of the display Returns Su
78. transceiver used to buffer data to and from the FDC and RS 232 circuits The direction of data transfer is controlled by the combination of control signals DISKIN RS2321N RDINT and RDNMI If any of these sig nals is active logic low U70 is enabled to drive data onto the CPU data bus If both signals are inactive logic high U70 is enabled to receive data from the CPU board data bus A sec ond buffer 036 is used to buffer the FDC chip data to the FDC RS232 Data Bus 00 7 U36 is enabled all the time and its direction controlled by DISKIN Again if DISKIN is active logic low data is enabled to drive from the FDC chip to the Main Data Busses If DISKIN is inactive logic high data is en abled to be transferred to the FDC chip Nonmaskable Interrupt Logic Gate Array 4 4 018 is used to latch data bits D6 and D7 on the rising edge of the control signal WRNMI This enables the con ditions which will generate a non maskable interrupt to the CPU The NMI interrupt conditions which are programmed by doing an OUT instruction to port E4H with the appropriate bits set If data bit 7 is set an FDC interrupt is enabled to generate an NMI interrupt If data bit 7 is reset interrupt requests request from the FDC are disabled If data bit 6 is set a Motor Time Out is enabled to generate an NMI interrupt If data bit 6 is reset in terrupts on Motor Time Out are disabled An IN instruction from port E4H enables the CPU to d
79. while it is run ning These are 4000H to 40FFH and 4300H to 43FFH For 512 byte boot sectors the second area is 4300H to 44FFH If the Model ROM Image is loaded additional areas are used See the technical reference manual for the system you are us ing for a list of these areas Operating systems that want to support a software restart by re executing the contents of the boot ROM can accomplish this in one of two ways If the operating system relies on the Model lil ROM Image then jump to location 0 as you have in the past If the operating system is a Model 4 mode package a simple way is to code the following instructions in your assembly and load them before you want to reset Absolute Location Instruction 0000 DI 0001 LD 0003 OUT These instructions cause the boot ROM to become address able After executing the OUT instruction the next instruction executed will be one in the boot ROM These instructions also exist in the Model lil ROM image at location 0 The boot ROM has been written so that the first instruction is at address 0005 The hardware must be in memory mode 0 or else the boot ROM will not be switched in This operation can be done with an OUT instruction and then 0 can be executed to have the ROM switched in Restarts can redirected at any time while the ROM is switched in All restarts jump to fixed locations in RAM and these areas may be changed to point to the routine that is
80. 1 32 or 40 character mode D3 ENALTSET 0 Alternate character set disabled 1 Alternate character set enabled D4 ENEXTIO 0 External IO Bus disabled 1 External IO Bus enabled D5 RESERVED D6 FAST 0 2 MHZ Mode 1 4 MHZ Mode D7 RESERVED Name RTCIN Port Address EC EF Access READ ONLY Description Clear Real Time Clock Interrupt 00 07 DONT Name RS232OUT Port Address E8 EB Access WRITE ONLY Description UART Control Data Control Modem Control Control Port 8 UART Master Reset Port 9 Rate Gen Register Port EA UART Control Register Modem Control Reg Port EB UART Transmit Holding Reg Refer to Model or 4 Manual for Bit Assignments Name RS232IN Port Address 58 Access READ ONLY Description Input UART and Modem Status Port 8 MODEM STATUS Port 9 RESERVED Port EA UART Status Register Port EB UART Receive Holding Register Resets DR Refer to Model or 4 Manual for Bit Assignments WRNMIMASKREG Port Address E4 E7 Access WRITE ONLY Description Output NMI Latch 50 05 RESERVED 06 0 Disables Motoroft 1 Enables Motoroff 07 ENINTRQ 0 Disables INTRQ NMI 1 Enables NMI Name RDNMISTATUS Port Address 4 E7 Access READ ONLY Description Input NMI Status 00 0 02 04 RESERVED 05
81. 144148 switching 8150148 CR2 Diode 1N4002 1A 50PIV 8150002 CR3 Diode 1N4002 1A 50PIV 8150002 CR4 Diode 1N4934 1A 100PIV 8150934 CR5 Diode MBR1035 8 10A 35V TO 220 8150035 CR6 Diode MUR810 8A 100PIV TO 220 8150810 CR7 Diode 184934 8A 100PIV 8150934 8 MUR810 8A 100PIV TO 220 8150810 CR9 Not Used CR10 Diode 1 4002 1A 50 PIV 8150002 CR11 Diode 1N4002 1A 50 PIV 8150002 Fl 3 amp AGC 8479104 Inductor 5 0uh 10 8419006 L2 Inductor 30uh 8419008 L3 Not Used L4 Inductor 30uh 5A 8419008 L5 Inductor 100uh 8419009 01 Transistor 5051 PNP TO 202 8100051 Q2 Transistor MPSA55 PNP 0 92 8100055 Q3 Transistor MPSUOlA NPN TO 202 8111001 Q4 Transistor MPSU51A PNP TO 202 8100051 Q5 Transistor 5001 NPN TO 202 8111001 Q6 SCR 8A 50PIV TO 220 8140122 Q7 Transistor MJE13006 NPN 8A 400V 8110006 Q8 Transistor MPSA55 PNP TO 92 8100055 Q9 Transistor MPSA05 NPN TO 92 8110005 Ul IC MC34060 Switching Regulator or 8060060 IC uA TL494 Switching Regulator 8060494 U2 IC Opto isolator 4N35 8170035 U3 pA TL431 Positive Shunt Reg 8060428 Resistor 1 4W 5 8207210 R2 Resistor 68 ohm 1 4W 5 8207068 R3 Resistor 28K 1 4W 1 8200328 R4 Resistor 39K 1 4W 5 8207339 R5 Resistor 15K 1 4W 5 8207315 166 PARTS LIST Power Supply Assembly 8790049 65W R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R
82. 32 8150256 8051912 MISCELLANEOUS HARDWARE PRP S i S iS RHE ES Clip Fuse PC Mount 1 4 Fuse Fl 8559042 Connector 2 Pin Vert 41 8519214 Connector 3 Pin J3 8519153 Connector 13 Pin J2 8519154 Bracket Heatsink TO 220 CR5 6 8 8729167 Heatsink Transistor TO 220 07 8549003 Insulator TO 220 Mica Q7 CR5 6 8 8539003 Nut KEPS 84 40 Q7 CR5 6 8 8579003 Screw 4 40 x 3 8 Q7 CR5 6 8 8569002 Washer Shoulder Q7 CR5 6 8 8589026 Wire Jumper 20 Ga W1 2 5 6 5 Wire Jumper 20 Ga W7 Wire Jumper 20 Ga W4 Wire Stranded 600V W3 8433006 168 5 5 CRT DISPLAY 5 5 1 Specifications The supply voltage is 12 000 DC 0 10V from a regulated power supply The room temperature is 25 degrees Power Input 1K 30uA 12V Input Level Horizontal Positive going Sync Vertical Negative going Sync Video Positive White Video Bandwidth 10Hz 12MHz Horizontal Retrace Vertical Retrace Scanning Frequency Horizontal Vertical Resolution at Center Resolution at Corner Geometric Distortion Pin Barrel distortion on top bottom on Sides Trapezoidal Distortion top bottom leftiright Parellogram Distortion Raster Tilt Linearity Vertical Size Video 24 rows Horizontal Size Video 80 characters Row Unit A V V V dB Sec Sec Hz Hz Lines Lines Inch Inch Inch Inch Inch Degree Inch Inch 169 Nomina 0 85
83. 38 R39 R40 R41 R42 2 VR2 VR3 Resistor 4 7K 1 4W 5 Resistor 10 1 4W 5 Resistor 22K 1 4W 5 Resistor 4 7K 1 4W 5 Resistor 4 7K 1 4W 5 Resistor 100 ohm 1 4W 5 Not Used Resistor 18K 1 4W 5 Resistor 330 ohm 1 4W 5 1 20 linear Pot Resistor 3 32K 1 4W 1 Resistor 100 ohm 1 4W 5 Resistor 10 ohm 1 4W 5 Resistor 1 ohm 1 4W 5 Resistor 10 1 4W 5 Resistor 150 ohm 1 4W 5 Resistor 330 ohm 1 4W 5 Resistor 27 ohm 2W 10 Resistor 22 ohm 1 2W 5 Resistor 22K 1 4W 5 Resistor 56K 1W 5 Resistor 390K 1 4W 5 Resistor 22 ohm 1 4W 5 Resistor 28K 1 4W 1 Resistor 6 65 1 4W 1 Not Used Resistor 1 1 4W 5 Resistor 100 ohm 1 4W 5 Resistor 1 1 4W 58 Resistor 68 ohm 1 4W 5 Resistor 100 1 4W 5 Resistor 0 22 ohm 2W 10 Thermistor 10 ohm 25c Resistor 56K 1W 5 Resistor 82 ohm 5W 5 Resistor 56K 1 4W 5 Resistor 4 7K 1 4W 5 Transformer Power 65W flyback Line Choke 5 5mH side 2A Zener 1N5232B 5 6V Zener 1N5256B 30V Voltage Regulator 79M12 12V 167 8207247 8207310 8207322 8207247 8207247 8207110 8207318 8207133 8279211 8200232 8207110 8207010 8207001 8207310 8207115 8207133 8248127 8217022 8207322 8247356 8207439 8207022 8200328 8200266 8207210 8207110 8207210 8207068 8207110 8248022 8298010 8248356 8248082 8207356 8207247 8790063 8790045 81502
84. 4 the peak current in the secondary Third the turns ratio is set by the ratio of the average primary voltage Vsw over a full cycle at its lowest value to the maxi mum permissible output voltage Vo The lowest Vsw value oc curs at low AC line and maximum output load In practice the actual turns ratio the ratio of peak to average voltages and currents and the duty cycle may be adjusted to compensate for circuit losses Line fuse amp surge Limiting EML input DC filter supply soft start latch Semi Control duty cycle control oscillator current limit output driver reference with soft start Switch current Fourth notice the ringing or oscillation that appears on the peak portion of Vsw and Vsec This oscillation occurs at the resonant frequency of the leakage inductance of the inductor L and the parasitic capacitance of the circuit The parasitic capacitance includes the interwinding capacitance of the inductor and stray capacitance of the switch If this oscillatiion is not damped by suitable means the peak voltages may easily exceed the breakdown rating of the switch or the insulation in the inductor Block Diagram The basic circuit illustrated in Figure 5 35 can be divided into three functional blocks Input DC supply primary and second ary To make use of this model we need to expand it to provide control for the switch timing and to include suffic
85. 50 8489073 8489971 8799612 8799613 8539050 8589084 8729246 8539049 8792049 8729243 8729242 8719341 8569199 8729288 8719362 8719367 8729245 8729253 8729287 8569128 8569203 8569205 8569203 8569221 8579048 8569202 8569108 Disk Drive Assembly Parts List Disk Drive Assembly Model 4P Computer Assembly 1 1 Weldment Support 8859029 2 2 Disk Drive Tandon 58 1 8790121 3 1 Cable Assembly FDC 879945 _ 4 1 Cable Assembly DC Harness 8709456 5 2 Handle Disk Drive 8719353 6 7 Screw 6 1 4 Rolok 8569128 7 6 Screw 6 32 1 4 PPH Mach CSRS 207 Keyboard Assembly Model 4P Microcomputer 208 Parts List Keyboard Assembly Model 4P Computer Assembly Item Qty 1 I 2 1 3 4 4 1 5 4 6 2 7 1 8 1 9 8 Bottom Keyboard Case Keyboard Assembly Top Keyboard Case Cable Assembly Keyboard Spring Keyboard Support Support Keyboard Cable Tie Nameplate Keyboard Screw 6 x 1 2 Thd Forming 8719342 879 53 8719343 8719469 8719914 8719336 8559027 8719367
86. 52 MHz clock MODSEL and 8064 signals are used to select the desired video mode 8064 controls which reference clock is used by U127 and MODSEL controls the single or double character width mode Refer to the following chart for selecting each video mode 8064 MODSEL Video Mode 0 0 64x16 0 1 32x16 1 0 80x24 1 1 40x24 This is the state to be written to latch U85 Signal is inverted before being input 0148 TUOI sna O I 10d sne O I TVNNSINI 833408 3804 YILNINd 834308 SNIWIL SINIT VIVO SANIT TOMINOD amu SANIT 893990 SNIWIL vnr Figure 5 19 Model Functional Block Diagram DCLK the reference clock selected is output from 0148 0148 generates SHIFT XADR7 CRTCLK LOADS and LOAD for proper timing for the four video modes U149 also generated H I and J which are fed to the Graphics Port J7 for reference timings of Hires graphics video Refer to Video Timing Figs 5 3 and 5 4 for timing reference 5 2 5 Address Decode The Address Decode section will be divided into two subsec tions Memory Map decoding and Port Map decoding 5 2 5 1 Memory Map Decoding Memory Map Decoding is accomplished by Gate Array 4 2 U106 Four memory map modes are available which are com patible with the Model and Model 4 microcomputers U106 is used for memory map control which also controls page map ping of the 32K RAM pages Refer to Memory Maps below
87. 563K RC1 2GF563K 1 851 1LMA 19861993vA 25 733 25 1313 6 25 2228 28 536 F 28C2373 K L Parts List 9 video Monitor 879 613 Green Screen Model 4P Computer Item Description Part Number VR2 1 Var Resistor 180 kohm 175110139 VR292 Var Resistor 2 17511010 VR2 3 Resistor 199 kohm 175119139A VR391 Var Resistor 1 kohm 17511 5 A VR3 2 Var Resistor 5 kohm 17511 16 A VR3 3 Var Resistor 2 Mohm 17691 93 A VT591 Cathode Ray Tube 55971 77 188 5 6 OPTIONS 5 6 1 Graphics Board Introduction and Programming Information The 4 graphics board provides low cost method of add ing an advanced graphics function to your Model 4 CPU The graphics board is software compatible with the Model J graph ics board but is also capable of several advanced features not found on the Mode 3 board The Model 4 graphics board provides 640 x 240 or 512 x 192 dot graphics The 640 x 240 dot graphics may be displayed as an independent display similar to the Model J or it may be mixed with the 80 x 24 text display The 512 x 192 dot graphics is always mixed with the 64 x 16 display The Model 4 graphics board uses a 32K byte memory How ever the graphics display uses a maximum of 19K on screen The remaining memory is not normally visible on screen This 32K byte memory is organized as an X Y matrix of 128 x 256 To access the memory the CPU must set up the
88. 64 741532 Quad 2 Input OR 8020032 066 1488 Driver 8959188 U67 IC 1489 Receiver 8959189 068 1489 Receiver 8959189 069 7415244 Octal Buffer 8828244 078 7415367 Driver 8020367 071 741827 Triple 3 Input NOR 8020027 072 TR1865 UART 8940865 073 7415174 Flip Flop 8929174 074 7415367 Driver 8020367 075 741 5139 1 of 4 Demultiplexer 8020139 076 BR1943 Clock Generator 8940943 077 741538 Quad 2 Input 8020038 078 741584 Hex Inverter 8020004 079 9216 8949216 089 7415245 Transceiver 8020245 081 01793 8030793 082 7415260 5 Input NOR 8020260 083 IC 7416 Inverter 8000016 084 7415245 Transceiver 8020245 085 IC 741592 2 Input NOR 8020002 086 7415174 Flip Flop 8920174 087 745884 Hex Inverter 8020004 088 741 5368 Driver 8929368 U9 741838 Quad 2 Input NAND 8020038 091 7416 Inverter 8888816 092 741593 Binary Counter 8828893 093 7416 Inverter 8000016 094 741508 Quad 2 Input AND 8020008 83 Parts List Main PCB Assembly Model 4P Computer IC IC IC 7415 4 Hex Inverter 741588 Quad 2 Input 74LS74 Flip Flop 741506 Quad 2 Input NAND 74LS195 Shift Register 7415249 Octal Buffer 74LS32 Quad 2 Input OR 741574 Flip Flop Delay Line 74LS74 Flip Flop MC14 4 Binary Counter 74L
89. 8 2 700 15 840 Limit 1 0 TTL Compatible TTL Compatible TTL Compatible 3 9 5 1 000 500 47 63 800 680 0 05 0 038 0 150 0 100 0 100 1 0 10 0 20 0 20 AEE MOT v 188 INI 01 lt 188 10904 1094 gt 5 100 3504 gt 8 2084 100 5 gt 1 21808 W LNOZINOH NS r gt ANS 1 MOVBATI 8 01 83 35 MOVEATI 3 1280 WILA 83 10231 68820 TVOlN3A 1 5 100 0 03 p 2 NI 03 3904 20101 200 10181 1010 231330 IOSAQ 380121 4 6 IOGLA 1051842 Figure 5 49 Video Monitor 8790613 612 170 5 5 2 Adjustment Procedures Horizontal Synchronization Adjustment Figures 5 50 thru 5 52 When there is a pattern on the CRT as shown in Figure 5 50 5 51 adjust VR301 to terminate scrolling and then do VR301 slightly to move the video into the center of the raster as illus trated in Figure 5 52 2 5 50 5 51 PICTURE RASTER Figure 5 52 Vertical Synchronization Adjustment Figures 5 53 5 54 Adjust VR201 to stop scrolling when video is rolling upward or do
90. 8 Quad 2 In AND 8015008 0118 7415245 Tranceiver 8020245 0121 741514 Hex Inverter 8020014 0124 7418174 Flip Flop 8020174 0125 7415244 Octal Buffer 8020244 0129 741874 Flip Flop 8020074 0133 140 6665 64K DRAM 20035 8040665 0142 741 502 2 In NOR 8020002 0146 PLL Multimodule 8409036 0148 IC 4 1 System Timing Array 8040541 NOTE Starred IC to be socketed 140 Parts List Model 4P Gate Array PC Board Sym Description Part Number Ul7 Socket 28 Pin DIP 8509007 Ul8 Socket 24 Pin DIP 8509001 031 Socket 40 8509002 033 Socket 40 DIP 8509002 042 Socket 40 Pin DIP 8509002 U45 Socket 40 Pin DIP 8509002 069 Socket 24 DIP 8509001 070 Socket 20 DIP 8509009 073 Socket 18 DIP 8509006 082 Socket 24 8509001 086 Socket 20 DIP 8509009 0102 Socket 40 8509002 0103 Socket 24 8509001 0106 Socket 40 DIP 8509002 0133 140 Socket 16 Pin DIP 8509003 0148 Socket 24 DIP 8509001 0153 160 Socket 16 DIP 8509003 1 Crystal 20 2752 MHz 2 Lead 8409031 Y2 Crystal 16 MHz Parallel Resonant 8409038 Low Cost Model 4P PC Board Sub 8858011 Assy Low Cost Model 4P Board Rev 8709524 141 5 3 MINI DISK DRIVES The Model 4P utilizes two 5 1 4 Flexible Disk Drive assem blies These drives are internally mounted with Drive 0 at the left and Drive 1 at the right when facing the CRT disp
91. 9 51 Transducer Sound 8499993 cl Capacitor 1 mfd 5 V Mono Axial 8374184 cll 13 Capacitor 1 mfd 5fV Mono Axial 8374194 15 Capacitor 1 5 V Mono 1 8374104 thru 2 22 Capacitor 1 mfd 5 V Mono 1 8374104 thru 48 5 Capacitor 1 mfd 5 V Mono Axial 8374184 thru C64 C66 Capacitor 1 mfd 5 V Mono Axial 8374194 thru 88 cog Capacitor 1 mfd 5 V Mono Axial 8374104 thru 2130 Parts List Main PCB Assembly Model 4P Computer 131 Capacitor 22 mfd 16V Elec Radial 8326221 C139 Capacitor 1808 59V Cer Disk 83 21 4 C14 Capacitor 22 mfd 5 Cer Disk 83 3224 141 Capacitor 22 mfd 59V Cer Disk 8393224 C142 Capacitor 33 5fV Cer Disk 8300334 C143 Capacitor 1599 5 Cer Disk Cl44 Capacitor 1500 SAV Cer Disk C145 Capacitor 1 mfd 59V Mono Axial 8374184 Cl46 Capacitor 1 mfd 5 V Mono Axial 8374104 C148 Capacitor 9 35 mfd Trimmer C149 Capacitor 1 mfd 59V Mono Axial 8374194 C15 Capacitor 189 59V C Disk 250 8301184 C153 Capacitor 199 pfd Cer Disk 8301104 154 Capacitor 470 pfd 5 V Cer Disk 83 1474 155 Capacitor 188 pfd 5 V Cer Disk 250 8301184 C156 Capacitor 199 SAV Cer Disk 8391184 C157 Capacitor 33 16V Elec Radial 8326331 C158 Capacitor 2 pfd 59V Cer Disk 250 8391223 C159 Capacitor 1 mfd 5 V Mono Axial 8374104 161 Capacitor 10 mfd 167
92. 990 con TVDD EVDD 1 TVYS VES zen Figure 5 14 Video Blanking Timing 55 20 404 8 6 gl tvin ST T8N iming 217180 5 ST 9N OT L4HS L3IHS Figure 5 15 Inverse Video Ti LADI ADI 2 2 zea TYYS YES CHES 048 025 oos oaov HED sexo 009 045 HER 008 042 CERTI GEGEN 5 1 12 Graphics The Graphics J7 on the Model is provided to attach the optional Graphics Board The port provides 00 07 Data Lines AO A3 Address Lines and RESET for the necessary interface signals for the Graphics Board is generated by negative ORing Port selects GSELO 8 8 and GSELI 80 83H together by 1 4 of 74LS08 U23 The re sulting signal is negative ANDed with by 1 4 of 74532 062 Seven timing signals are provided to allow synchroniza tion of Main Logic Board Video and Graphics Board Video These timing signals are HSYNC DISPEN DCLK and J Three control signals from the Graphics Board are used to sync to CPU access and select different video modes WAIT controls the CPU access by causing the CPU to WAIT till video is in retrace area before allowing any writes o
93. Board Sym Description Part Number Resistor Pak 27 ohm 16 8290027 2 Resistor Pak 1 5 kohm SIP 10 8290015 4 Resistor 150 ohm SIP 10 8290013 51 Speaker 8 ohm 8490008 Ul 7415123 Multivibrator 8020123 U2 7415374 Flip Flop 8020374 U3 7415244 Octal Buffer 8020244 4 741 508 Quad 2 In AND 8020008 05 741504 Inverter 8020004 06 7415245 Tranceiver 8020245 09 7415244 Octal Buffer 8020244 010 7415367 Driver 8020367 011 1489 Receiver 8050189 012 1488 Driver 8050188 013 1489 Receiver 8050189 014 7416 Inverter 8000016 015 7416 Inverter 8000016 016 7415367 Driver 8020367 017 401773 8040773 018 IC 4 4 Floppy Support Array 8040544 022 745802 2 NOR 8020002 023 741574 Flip Flop 8020074 024 745632 Quad 2 OR 8020032 027 7415244 Octal Buffer 8020244 028 30 7415138 Quad 2 NAND 8020138 031 4 5 RS232C Support Array 8040545 033 IC TR1865 UART 8040865 U34 7415174 Hex Flip Flop 8020174 U36 7415245 Tranceiver 8020245 041 7415157 Multiplexer 8020157 042 68 045 8040045 045 280 CPU 8047880 050 741521 Dual 4 AND 8020021 055 741508 Quad 2 In AND 8020008 U56 IC 74LS123 Multivibrator 8020123 057 7416 Inverter 8000016 061 7415157 Multiplexer 8020157 067 7415244 Octal Buffer 8020244 069
94. CB and voltage at TP2 Supply should start in two to four seconds 3 Observethe 5 05 olt output and adjust R15 until the out put is exactly 5 05 volts DC 4 Measure 12V and 12V outputs 5 Check all outputs at Vin 90 VAC and 135 VAC at minimum and maximum loads b check 12V CRT when 12V DISK varies in transient test 6 Measure ripple See Measurement Techniques below 7 Measure efficiency See Measurement Techniques below 8 Testoperation of current limit and over voltage protection circuits by applying 7 0 volts to the 5 volt output 159 M Measurement Techniques Ripple Unit connected to full load at low line One end of 50 ohm coaxial cable connected to output terminals Other end of cable terminated with 0 01uF ceramic cap in series with 51 ohm resistor connected to scope using BNC T fit ting Two components at 120 Hz and 40 kHz 2 Efficiency Use Diego Systems Series 200 power monitor Power Out Efficiency Power In 60 435 084 1300 83 0 gt 2119 8335 pon EM 3804 160 WAVEFORMS See schematic notations 0 reference 50 vert 5 u d horiz AC
95. Elec Radial 8326101 Cl62 Capacitor 1 mfd 16V Elec Radial 8326101 C166 Capacitor 1 mfd 5 V Mono Axial 8374104 Cl72 Capacitor 1 mfd 5 V Mono Axial 8374104 C176 Capacitor 1 mfd 5 V Mono Axial 8374194 C181 Capacitor 1 mfd 5 V Mono Axial 8374184 C2 Capacitor 1 mfd S V Mono Axial 8374184 2 1 Capacitor 22 mfd 16V Elec Radial 8326221 282 Capacitor 19 mfd 16V Elec Radial 83261 1 C283 Capacitor 1 mfd 5 V Mono Axial 8374194 C284 Capacitor 18 mfd 16V Elec Radial 8326101 C285 Capacitor 199 pfd 58V Cer Disk 8381184 Diode 134148 8159148 01 Transistor 2N3996 8100906 02 Transistor 2N39 6 8100906 80 Parts List Main PCB Assembly Model 4P Computer Item Description Part Number 1 Resistor 750 ohm 1 4W 5 8207175 2 Resistor 108 kohm 1 4W 5 8297410 R3 Resistor 4 7 kohm 1 4W 5 8207247 thru R5 R6 Resistor 22 ohm 1 4 5 8287822 R7 Resistor 220 ohm 1 4 5 8287122 R8 Resistor 1 2 kohm 1 4 5 8277212 9 Resistor 2 2 1 4W 5 8207222 RIL Resistor 1 ohm 1 4W 5 8207110 R12 Resistor 13f ohm 1 4W 5 8287113 R13 Resistor 13 ohm 1 4W 5 8207113 14 Resistor 1 kohm 1 4W 5 8207210 R15 Resistor 1 1 4W 5 820721 R16 Resistor 3 kohm 1 4W 5 8207230 R17 Resistor 829 1 4W 5 8207182 18 Resistor 200 ohm 1 4W 5 8207120 R19 Resistor 160 1 4W 5 8207416 2 Resistor 27 ohm 13 48 5 8207927 thru 23 R24 Resistor
96. H 3600 57 6 kHz Yes CH 4800 76 8 kHz Yes DH 7200 115 2 kHz Yes EH 9600 153 6 kHz Yes FH 19200 307 2 kHz Yes The RS 232C circuit is port mapped and the ports used are E8 to EB Following is a description of each port on both input and output Port Input Output E8 Modem status Master Reset enables UART control register load EA UART status UART control register load and modem control E9 Not Used Baud rate register load enable bit EB Receiver Holding Transmitter Holding register register Interrupts are supported in the RS 232C circuit by the Interrupt mask register and the Status register internal to GA 4 5 U31 which allow the CPU to see which kind of interrupt has curred Interrupts can be generated on receiver data register full transmitter register empty and any one of the errors par ity framing or data overrun This allows a minimum of CPU overhead in transferring data to or from the UART The interrupt mask register is port EO write and the interrupt status register is port EO read Refer to the IO Port description for a full break down of all interrupts and their bit positions All Model I and 4 software written for the RS 232 C interface is compatible with the Model RS 232 C circuit provided the software does not use the sense switches to configure the in terface The programmer can get around this problem by di rectly programming the BRG and UART for the desired configuration or by using the
97. HI W y gt RA BRIN 5 255 iH 5 14 n Y Y Y Y 9 LJ 14 Toe 3 pes 2 Mer 4 2 ver Ain i poi Os Er 4 4 5 E H H 2 sr lt gt gt A m vs 5 gt MS IA 31 5 55 Stone gt Da bsg paca 22 a s 25 RR E 4 xar 4 ato jas 52 146 m pole 0 0000 i ie Y pe z Mn 21 gt 3 77 ea rcu Fe fn e pec 2200 pu L us ty 2309 JL 1 n s im gt ua Ben 2580 ES n OOO Ce H 2 1894 TOBUSINT ZOBUSINT gt 39 s se r even PROPRIETARY INFOREAT S T ott tea C POPE TAR 30 P NY W eto DDE TM 131 AUD TX W T 100 PORT LOGIC TARDY CENTER FORT 76102 805 807 2 53 Ts 1 RESET e uss CoD Pons 4 3 gt SUPPORT FLOPPY DISK CONTROLLER BREWING NG 8000233 sr TE GET 804 605 605
98. Hz output at pin 12 The 2 MHz is NANDed with 4MHz by 1 4 of 019 and the output is used to clock the divide by 8 section of U37 1 MHz clock is gener ated at pin 9 of U37 which is 90 phase shifted from the 2 MHz clock This phase relationship is used to gate the guaranteed Write Data Pulse WD to the Write precompensation circuit The 4 MHz is used to clock the digital data separator U18 and the Write precompensation shift register U55 The 1 MHz clock is used to drive the clock input of the FDC chip U13 and the clock input of the watchdog timer U99 Disk Bus Output Drivers High current open collector drivers U20 and 056 are used to buffer the output signals from the FDC circuit to the disk drives Write Precompensation and Write Data Pulse Shap ing Logic The Write Precompensation logic is comprised of U55 74LS195 1 4 of U19 741500 1 4 of 074 741504 and 1 2 of U77 74LS260 U55 is a parallel in serial out shift reg ister and is clocked by 4 MHz which generates a precompen sation value of 250 nsec The output signals EARLY and LATE of the FOC chip U13 are input to PO and P2 of the shift reg ister A third signal is generated by 1 4 of U75 when neither EARLY nor LATE is active low and is input to P1 of U55 WD of the chip is NANDed with 2 MHz to gate the guaranteed Write Data Pulse to U55 for the parallel load signal SHFT LD When U55 pin 9 is active low the signals preset at P1 P3 are clocked in on the risi
99. OM image to be loaded by coding a CDxx00 somewhere in the boot sector It does not have to be executable At the same time Model 4 packages must take care that there is no sequence of bytes in the boot sector that could be mis interpreted to be areference to the Boot ROM An example of this would be sequence 06 00 00 which is LD B OCDH and LD C 0 If the boot sector cannot be changed then the user must press the lt F3 gt key each time the system is started to inform the ROM that the disk contains a Model pack age which needs the Model Ill ROM image 2 If you are loading a Model 4 operating system then the boot ROM will always transfer control to the first byte of the boot sector which is at 4300H If you are loading a Model III operating system or about to use Model ROM BASIC then the transfer address is 3015H This is the address of a jump vector in the ROM of the Model III ROM image and this will cause the system to behave exactly like a Model the ROM image file that is loaded has differ ent transfer address then that address will be used when loading is complete If the image is already present it will use 3015H 3 Two different tests are done to insure that the Model ill ROM image is present The first test is to check ever third location starting at 3000H for a C3H This is done for 10 lo cations If any of these locations does not contain a C3H then the ROM image is considered to be not
100. R7 LOAD LOADS DCLK If okay then go to 4 if one or more bad replace U127 or U128 4 Checkif 68046 085 is working properly and has correct in put signals If all okay then go to 5 If bad replace U85 or check for in put signals where they originate 5 Check for timing and proper signals at U82 and U42 If bad replace as necessary if okay go to 6 6 Check shift register and repair 7 Check for 20M output of Y1 pin 8 If okay go to 8 if bad replace 1 8 Check for outputs of U126 PCLK RS232CLK and 10M If okay then go to 9 if any bad replace U126 9 Check for 12M at output of U148 pin 9 If okay then video should work if bad check U147 U148 and U149 and replace if necessary 10 Run Memory Test in Boot ROM by holding down period and toggling Reset If memory checks okay then go to 11 not check mem ory circuit and or replace RAM chips 11 Check Clock circuit of Floppy Disk Controller If 2 2MH and 1MHz okay go to 12 if bad repair or replace necessary components 12 Check for all incoming signals to the FDC chip U13 If any bad repair as necessary if okay go to 13 66
101. RD 1 3 SYSTEM BLOCK DIAGRAM The System Block Diagram Figure 1 2 shows the various internal components and connections of the Model 4P Microcomputer POWER CORD 8709475 D LINE 1 0 RS 232 C FDC CABLE PRINTER BUS SERIAL 88709457 POWER SWITCH 8489073 4 64K OR 128 RAM AC HARNESS 8709455 REAL TIME CLOCK VIDEO INTERFACE FLOPPY FLOPPY HI RES KEYBOARD INT DISK DISK GRAPHICS LINE PRINTER INT DRIVE BOARD I O PORT INT POWER OPTIONAL RS232 C SERIAL 1 INT FLOPPY SUELE DRIVE INT 8790121 88790049 HI RES GRAPHICS a BOARD INT 8709427 i VIDEO HARNESS REET ECE EEE 8709457 DC HARNESS 8709456 KEYBOARD CABLE 4 8709460 CRT PC MODEM BOARD BOARD 8790612 OPTIONAL 70 KEYBOARD 8790530 RS 232 C O SERIAL PORT BRIGHTNESS CONTRAST CONTROL CONTROL 8262450 8261150 DC FAN 8790406 99 28790612 1 2 Model Block Diagram SECTION II SPECIFICATIONS SPECIFICATIONS 2 1 MICROPROCESSOR 4 MHz Z80A 8 bit CPU Memory Keyboard Video Display Floppy Disk Drives 64K RAM bytes expandable to 128K bytes 4K boot ROM 2K video memory 70 key standard typewriter keyboard including 12 key numeric entry keypad Special keys include BREAK CTRL CAPS CLEAR plus three programmable special function keys F1 F2 and F3 High res
102. Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor ead 25 Pin RS232 DB25 34 Pin Floppy Disk Dual 8 Keyboard Rt Angle 34 Pin Graphics Header 3 Pin Reset Header 6 Pin Video Header 4 Pin Power Header 2N3906 20 kohm 1 4W 5 160 kohm 1 4W 5 4 7 kohm 1 4W 5 4 7 Meg ohm 1 4W 5 4 7 kohm 1 4W 5 22 ohm 1 4W 5 47 ohm 1 4W 5 56 ohm 1 4W 5 4 7 kohm 1 4W 5 27 ohm 1 4W 5 47 ohm 1 4W 5 150 ohm 1 4W 5 3 6 kohm 1 4W 5 22 ohm 1 2W 5 4 7 kohm 1 4W 5 27 ohm 1 4W 5 2 2 kohm 1 4W 53 100 kohm 1 4W 55 750 ohm 1 4W 5 4 7 kohm 1 4W 5 10 kohm 1 4W 5 10 kohm 1 4W 5 150 ohm 1 4W 5 138 8300224 8301104 8301104 8374104 8301104 8301104 8374104 8150148 8529014 Description Capacitor 22 pfd 50V C Disk NPO Ax Capacitor 100 pfd 50V C Disk Capacitor 100 pfd 50V C Disk Ax Capacitor 1 mfd 50V Mono Axial Capacitor 100 pfd 50V C Disk Ax Capacitor 100 pfd 50V C Disk Ax Capacitor 1 mfd 50V Mono Axial Diode 1N4148 Staking Pins 8419014 8519109 8519120 8519184 8519120 8519215 8519211 8519210 8100906 8207320 8207416 8207247 8207457 8207247 8207022 8207047 8207056 8207247 8207027 8207047 8207115 8207236 8217022 8207247 8207027 8207222 8207410 8207175 8207247 8207310 8207310 8207115 Parts List Model 4P Gate Array PC
103. S123 Multivibrator 74L5157 Multiplexer 74LS157 Multiplexer 74LS245 Transceiver 74564 AND OR Inverter 74532 Quad 2 Input OR 745112 J K Flip Flop 74208 Quad 2 Input AND MCM6665 64K DRAM 288 nsec 7415283 Binary Adder 741511 Triple 3 Input AND Crystal 20 2752 MHz Crystal 4 MHz 8020004 8020000 8020074 8020000 8920195 8020240 8020032 8020074 8429020 8020074 89309048 8828123 8929157 8428157 8020245 8012064 8919932 8919112 8015008 8949665 8020293 8228911 84709932 8409010 4P GATE ARRAY THEORY OF OPERATION 5 2 CPU THEORY OF OPERATION 5 2 1 Introduction Contained in the following paragraphs is description of the component parts of the Model 4P CPU Gate Array It is divided into the logical operational functions of the computer All ponents are located on the Main CPU board inside the case housing Refer to Section 3 for disassembly assembly procedures 5 2 2 Reset Circuit The Model 4P reset circuit provides the neccessary reset pulses to all circuits during power up and reset operations R25 and C214 provide time constant which holds the input of U121 low during power up This allows power to be stable to all cir cuits before the RESET and RESET signals are applied When 214 charges to logic high the output of 0121 triggers the input of a retriggerable one shot multivibrator U1 U1 outputs pulse with an approximate width of 70 microsecs When the reset switch is pressed
104. SETCOM command of the disk operating system to configure the interface The TRS 80 RS 2320 Interface hardware manual has a good discussion of the 5 232 standard and specific programming examples Cat alog Number 26 1145 Pinout Listing The following list is pinout description of the DB 25 connector P1 Pin No Signal 1 PGNO Protective Ground TD Transmit Data Receive Data RTS Request to Send CTS Clear To Send DSR Data Set Ready SGND Signal Ground CD Carrier Detect SATS Spare Request to Send DTR Data Terminal Ready RI Ring Indicate 0 100 N 125 5 2 17 CPU Board Troubleshooting Guide This section is general guide for service personnel to check out and troubleshoot the Model 4P Main Logic CPU Board Pro cedures in section 4 Troubleshooting should be followed before proceeding to following steps This guide will provide step by step procedures to help isolate the faulty area on the CPU board Knowledge of each area of the CPU board is necessary to determine exact component failure Refer of CPU Board Schematics and Theory of Operation during troubleshooting for specific check points and testing 1 No video messages are displayed and correct data does not appear at video output connector J9 If above condition exists go to 2 if video okay but Model 4P does not boot properly go to 10 If video and boot up is okay go to 15 2 Check for video timing s
105. TIN COMED PLVS POPE av DUN f TAMO NO KAD At BE TT PACS MATEN 07 CORPO MER 128 BT aon RELEASU FOR PRODUCTION REF DRILL PLAN 1700254 REV A CPU AND TIMING SCHEMATIC se MAIN LOGIC Em MODEL 4 GATE ARRAY 0059 0067 544 s cios PROPRIETARY E 36 15 P OF Th OF ANY ius MADE THE OF TWO CENTES FORT 1510 128 G 5835 pespane visa r e gasos 659 is CED 5 ENPAGE SRCEAGE 25 vise 05 785852 o gt 23 awari ud 5 EE pl avoress Cars ruse fo 6 Ss VE Miei en 2 BUSOIR E D E FTP 3 sv seu voeon 2509 Bed D 22 pr GMN 1 use i mm 1 20 80 E 2 m um 4 1527 usi if 13 19 874 e ss 5 i 5 wE RESET Cx 4 7 ED P 0 F3 Ls 2 ENE
106. VIDEO low This is inverted by U74 1 6 of 74LS04 which pulls one input of U96 1 4 of 74LS00 and in turn asserts VWAIT low to the CPU RD is high at this time and is latched into 095 1 2 of 741574 on the rising edge of XADR7 XADR7 is inverse of CRTCLK which drives the CRTC 68045 and the address multiplexers UB3 U84 and U104 51 When RD is latched by U95 the Q output goes low releasing WAIT from the CPU The same signal also is sent to the Delay Line 097 through 0116 1 4 of 74F08 The Delay line delays the falling edge 240 ns for VLATCH which latches the read data from the video RAM at U102 The data is latched so the CRTC can refresh the next address location and prevent any hashing MRD decoded by U108 and a memory read is ORed with VIDEO which enables the data from U102 to the data bus The CPU then reads the data and completes the cycle A CPU write is slightly more complex in operation As in the RD cycle VIDEO is asserted low which asserts VWAIT low to the CPU WR is high at this time which is NANDed with VIDEO and synced with CRTCLK to create VRAMDIS that disables the video RAM output On the rising edge of XADR7 WR is latched into U95 1 2 of 74LS74 which releases VWAIT and starts cycle through the Delay Line After 30ns DLYVWR De layed video write is asserted low which also asserts VBUFEN Video Buffer Enable low VBUFEN enabled data from the Data bus to the video RAM Approximately 120ns later DLY
107. VWR is negated high which writes the data to the video RAM and negates VBUFEN turning off buffer The CPU then completes WR cycle to the video RAM Refer to Video CPU Access Timing Figure 5 12 for timing of above RD or WR cycles During screen refresh CRTCLK is high allowing the CRTC to address Video RAM The data out of the video RAM is latched by LOAD into 7415273 0101 D7 is generated by IN VERSE through U125 1 6 of 74504 0123 1 4 of 74LS08 This decoding determines if character should be al pha numeric only if inverse high or unchanged INVERSE low The outputs of U101 are used as address inputs the char acter generator ROM U42 A9 is decoded with ENALTSET Enable Aiternate Set and Q7 of U101 which resets A9 to a low if Q7 and ENALTSET are high See ENALTSET Control Ta ble below C C r T z rn S N HOLYTA f NEANEA 1 sh OO rm O_O 1 ue T_T 1 com J 777 uh a re NE uM S zx 02394 M FIGURE 5 12 Video CPU Access Timing 52 row addresses from the used to control which scan line is being displayed The Model 4P has 4 bit full adder 7415283
108. ached to terminals or connectors from the rear of the module 2 ifthe module is to be removed tag all wiring so that proper reassembly is assured FRONT BRIGHTNESS CONTRAST POWER ON OFF RESET VIO GRY 2 BLK WHT VIO BRN BRN BLU CRT BOARD REAR Figure 3 4 Control Module 16 SECTION IV MAINTENANCE TROUBLESHOOTING MAINTENANCE TROUBLESHOOTING 4 1 INTRODUCTION This section is general guide for use by service personnel It contains the Maintenance and Troubleshooting procedures necessary to help isolate the problem area to a faulty board or subsystem After board or subsystem has been identified refer to specific section for more detailed troubleshooting information Refer to the schematics and the theory of operation during maintenance and troubleshooting for specific checkpoints and testing 4 2 MAINTENANCE The only part of the Model 4P that requires maintenance is the two Floppy Disk Drives cleaning of the Read Write Heads are recommended to assure error free operation For all other maintenance or alignments required refer to Section 5 3 Mini Disk Drives Maintenance Checks and Adjustments 4 3 TROUBLESHOOTING Please be sure that the power cord is properly connected to AC power before starting troubleshooting 1 Turn Model 4P by toggling power switch If power light indicator is on then to 4 if not go to 2 2 Recheck AC power and
109. ad Cycle Timing 104 LAN AN K YT 1880 0884 5 5 4 x NJ SVN ffNNSVH 5 NAUMNVA gt gt LE 08594 e Figure 5 28 Memory Write Cycle Timing 105 Mode 0 0000 OFFF 1000 37FF 3768 37 9 3800 3BFF 30 00 4000 FFFF Mode 0 0000 37FF 3728 3759 3800 3000 3FFF 4000 1 0000 OFFF 0000 OFFF 1000 37FF 3800 3000 3FFF 4000 FFFF 4 SELO 0 0 5511 0 0V ROM 1 OV Boot ROM RAM Read Only Printer Status Read Only Keyboard Video RAM SELO 0 OV SEL1 0 0 0 5V Printer Status Read Only Keyboard Video RAM SELO 1 5V 5511 0 OV ROM 1 0V Boot ROM RAM Write Only RAM Keyboard Video RAM 4K 10K 1K 1 48 14 1 1K 48K 4K 4 10K 1 1 48 106 1 0000 37FF 3800 3BFF 3000 3FFF 4000 2 0000 F3FF F400 F7FF F800 FFFF Mode 3 0000 FFFF SELO 1 5 0 0 5V Keyboard Video RAM SELO 0 OV 1 5 ROM X Dont Care RAM Keyboard Video SELO 1 5V SELI 1
110. age Protection The 5 05 VDC circuit is protected with a crowbar circuit with a trip range of 5 8 to 6 8 VDC Hold Up Time at Continuous Max Load Nominal Line 16 mSec minimum Low Line 10 mSec minimum 5 4 3 Theory of Operation The basic operating principles of a flyback converter and the necessary functional blocks to form complete power supply were reviewed in the System Description section In this part the operation of each section of the circuit will be analyzed and later these sections will be connected to illustrate the signal flow in the power supply AC Input conventional bridge rectifier and filter capacitor are con nected directly across the line to provide the DC input volt age to the power supply 90 to 135 VAC 50 60 Hz 160 VDC Figure 5 38 Input AC Supply 148 filter consisting of capacitors C30 C33 and choke 2 are inserted at the input to the rectifier This filter circuit keeps the high frequency signals generated in the power supply from being conducted into the AC power line C30 and C31 provide a low impedance to the earth ground terminal for signals mon to both hot and neutral sides of the AC line C32 provides a low impedance dissipative path for the RF signal energy which appears across the line T2 blocks RF signals common to both sides of the line and reflects them back toward the lower impedance elements near the rectifier T2 also helps block dif
111. akage inductance is transferred to the electric field of the total capacitance of C37 plus stray capacitance Since C37 capacitance is much larger than the strays it dominates in this action and tends to limit the peak value of the Q7 turn off voltage If there were no resist ance in this series connection of C37 plus parasitics and leak age inductance they would exchange this energy back and forth indefinitely R40 is used to damp this oscillation without excessively slowing the turn off voltage spike at the collector of Qr Current Limit Circuit and the Shut Down Sequence The current limit circuit forces the voltage level at a control pin of U1 to change to a near zero value very quickly when the cur rent in the transistor switch exceeds a predetermined point It also removes the supply voltage from the control circuit and re sets the kick start latch and soft start circuits The current limit circuit shown in Figure 5 44 c has three parts a control bus a detector and a latch The control bus supplies the operating DC voltage to the current limit circuit It also con ducts the current limit signal to control pin 13 and to the reset point in the kick start latch circuit Diodes CR2 and CR3 steer this signal The normal maximum peak current in switching transistor Q7 is 3 amps The detector transistor 8 is biased to turn on by the divider action of R35 and R36 whenever the Q7 peak current through R37 exceeds 4 amps A low pass f
112. and acts upon two types 01 Data Load 1 byte with length of block including address 1 word with address to load the data n bytes of data where n 2 equals the length specified 02 Transfer Address 1 byte with the value of 02 1 word with the address to start execution at Any other loader code is treated as a comment block and is ig nored Once an 02 record has been found the loader stops reading even if there is additional data so be sure to place the 02 record at the end of the file 95 Floppy and Hard Disk Driver The disk drivers are entered via RST 8H and will read a sector anywhere on a floppy disk and anywhere on head 1 top head in a hard disk drive Either 256 or 512 byte sectors are readable by these routines and they make the determination of the sector size The hard disk driver is compatible with both the WD1000 andthe WD1010 controllers The floppy disk driver is written for the WD1793 controller Serial Loader Invoking the serial loader is similar to forcing a boot from hard disk or floppy In this case the right shift key must be pressed at some time during the first three seconds after reset The pro gram does not care if the key is pressed forever making it con venient to connect pins 8 and 10 of the keyboard connector with a shorting plug for bench testing of boards This assumes that the object program being loaded does not care about the key closure Upon entry the program first asserts DTR J4
113. and control lines If okay then problem still exists in Floppy Disk Circuit or Floppy Disk Drive Refer to each section accordingly If bad replace as necessary 15 If unit boots okay then boot Model Diagnostics Diskette and execute each diagnostic to isolate any minor problems on CPU Board RESET HEADER uer Pan as Reset ves raL 2a5 48 45 54254557 C emn sv p Enti 3 m E E T 38 TORE 20 ses 3 S 22 piei RESA 28 5 6 RESH uox 5 52 Jeu 5 e 2 5 5 m Ba a GD m ES D icone gt SHIFT Ep CEDE 9 1 ALL RESISTANCE VALUES ARE IN OHMS Ks 1902 NOTE UNLESS OTHERWISE SPECIFIED 127 65858 LATCH PI Iu T gol 5 541254557 TI
114. at 50 baud so there is no need to be extra careful here If the sync byte is received without error then the Loading message is transmitted and the program is ready to receive the command file After receiving the Loading message the host can transmit the file without nulls or delays between bytes 35 Since the file represents 280 machine code and all 256 combinations are meaningful it would be disastrous to transmit nulls or other ASCII contro codes as fillers ac knowledgement or start stop bytes The only control codes needed are the standard command file control bytes Data can be transmitted to the loader at 19200 baud with no de lays inserted Two stop bits are recommended at high baud rates See the File Loader description for more information on file loading a receive error should occur during file loading the abort pro cedure described above will take place so when attempting re mote control it is wise to monitor the host receiver during transmission of the file When the host is near the object board as is the case in the factory application or when more than one board is being loaded it may be advantageous or even nec essary to ignore the transmitted responses of the object board s and to manually pace the test byte sync byte and command file phases of the transmission process using the video display for handshaking System Programmers Information The Model 4P Boot ROM uses two areas of RAM
115. ata to be read from memory during each RAS cycle The only change from the first CAS clock to the second CAS is the XADR7 signal This signal is used a column address to allow double access of RAM during each RAS cycle The other signals provided by the timing logic are STROBE1 STROBE2 and CLK STROBE1 latches data from the RAM STROBE is the shift register shift load signal CLK is a de layed version of DCLK To minimize the amount of logic on the board the gate array performs the bulk of the work During a CPU read or write eration the gate array timing logic forces the CPU to wait until horizontal or vertical sync This prevents hashing on the screen The graphics board does have mode of operation with no waits however this mode is not recommended due to the possibility of memory loss During a read the first 4 bits of data are latched then all 8 bits are latched and placed on the CPU data bus During 8 CPU write cycle 4 bits are written by the first CAS and the last 4 are written by the second CAS The Model 4 video logic provides the dot clock horizontal sync vertical sync and display enable Using these signals the gate array generates X and Y video addresses The start address for the X or Y counter may be changed from 0 by loading the ap propriate offset register This allows scrolling of the picture and display of all of the 32 K of memory The gate array also provides X and Y address cou
116. ate message it reads from the UART data register in order to clear any overrun error that may have occurred due to the test bytes coming in during the transmission of the message This is because the re must be made ready to receive a sync byte signalling the beginning of the command file For this reason it is important that the host wait until the entire baud rate message 16 char acters is received before transmitting the sync byte which is equal to FF hex When the loader receives the sync byte the message Loading is displayed on the screen Again the same message is trans mitted to the host and again the host must wait for the entire transmission before starting into the command file If the receiver should intercept a receive error while waiting for the sync byte the entire operation up to this point is aborted The video display is cleared and the message Error x is displayed near the bottom of the screen where x is a letter from B to H meaning B parity error C framing error D parity amp framing errors overrun error parity amp overrun errors G framing amp overrun errors H parity amp framing amp overrun errors The message Error is then transmitted to the host The entire process is then re peated from the Not Ready message six second delay is inserted before reinitialization This is longer than the time re quired to transmit five bytes
117. been found the loader stops reading even if there is additional data so be sure to place the 02 record at the end of the file 34 Floppy and Hard Disk Driver The disk drivers are entered via RST 8H and will read a sector anywhere on a floppy disk and anywhere on head 1 top head in a hard disk drive Either 256 or 512 byte sectors are readable by these routines and they make the determination of the sector size The hard disk driver is compatible with both the WD1000 andthe WD1010 controllers The floppy disk driver is written for the WD1793 controller Serial Loader Invoking the serial loader is similar to forcing a boot from hard disk or floppy In this case the right shift key must be pressed at some time during the first three seconds after reset The pro gram does not care if the key is pressed forever making it con venient to connect pins 8 and 10 of the keyboard connector with a shorting plug for bench testing of boards This assumes that the object program being loaded does not care about the key closure Upon entry the program first asserts DTR J4 pin 20 and RTS J4 pin 4 true Next Not Ready is printed on the topmost line of the video display Modem status line CD J4 pin 8 is then sampled The program loops until it finds CD asserted true At that time the message Ready is displayed Then the program sets about determining the baud rate from the host computer To determine the baud rate the program compares
118. ccess Always A Altered DE Points to next position on video HL Points to the null 0 Display Block RST 18H Accepts HL Points to control vector in the format 0 Screen Offset 2 Pointer to text terminated with null 4 Pointer to text terminated with null n word FFFFH End of control vector or n word FFFEH Next word is new Screen Offset 2 flag is set on entry then the first screen offset is read from DE instead of from the control vector Each string is positioned after the previous string unless entry is found This is used heavily in the ROM to re duce duplication of words in error messages Returns Success Always DE Points to next position on video Byte Fetch RST 20H Accepts None Returns 2 Success byte Failure error code Errors Any errors from the disk call and 2 ROM Image can t be loaded Too many extents 10 ROM Image can t be loaded Disk drive is not ready Flle Loader RST 28H Accepts None Returns 2 Success NZ Failure error code in Errors Any errors from the disk call of the byte fetch call and 0 The ROM image was not found on drive 0 There are several pieces of information left in memory by the boot ROM which are useful to system programmers These are shown below RAM Location Description 401DH ROM Image Selected for none selected or A G 4055H Boot type 1 Floppy 2 Hard disk 3 ARCNET 4 RS 232C 5 7 Reserved 4056H
119. cription of how this LSI circuit performs these functions refer to the TR1865 data sheets and application notes The transmit and receive clock rates that the TR1865 needs are supplied by the Baud Rate Generator U52 BR1941L or BR1943 This circuit takes the 5 0688 MHz supplied by the system timing circuit and the pro grammed information received from the CPU over the data bus and divides the basic clock rate to provide two clocks The rates available from the BRG go from 50 Baud to 19200 Baud See the BRG table for the complete list 64 BRG Programming Table Transmit Receive Supported Nibble Baud 16X by Loaded Rate Clock SETCOM OH 50 0 8 kHz Yes 1H 75 1 2 kHz Yes 2H 110 1 76 kHz Yes 3H 134 5 2 1523 kHz Yes 4H 150 2 4 kHz Yes 5H 300 4 8 kHz Yes 6H 600 9 6 kHz Yes 7H 1200 19 2 kHz Yes 8H 1800 28 8 kHz Yes 9H 2000 32 081 kHz Yes AH 2400 38 4 kHz Yes BH 3600 57 6 kHz Yes CH 4800 76 8 kHz Yes DH 7200 115 2 kHz Yes EH 9600 153 6 kHz Yes FH 19200 307 2 kHz Yes The 5 232 circuit is port mapped and the ports used are E8 to Following is description of each port on both input and output Port Input Output 8 Modem status Master Reset enables UART control register load EA UART status UART control register load and modem control 9 Not Used Baud rate register load enable bit Receiver Holding Transmitter Holding register register Interrupts are supported in the RS 232C circuit by the Interrupt mask reg
120. ction to prevent violating any Dynamic RAM parameters NOTE This automatic WAIT will cause a 5 1 wait each time an out to Drive Select Latch is pertormed Clock Generation Logic 16 MHz crystal oscillator and a Gate Array 4 4 018 are used to generate the clock signals required by the FDC board The 6 MHz oscillator is implemented internal to U18 and quartz crystal Y2 The output of the osciliator is divided by 2 to gen erate an 8 MHz clock This is used by the FDC 1773 for all in ternal timing and data separation U18 further divides the 16 MHz clock to drive the watchdog timer circuit Disk Bus Output Drivers High current open collector drivers U15 and U34 are used to buffer the output signals from the FDC circuit to the disk drives Write Precompensation and Write Data Pulse Shap ing Logic All Write Precompensation is generated internai to the FDC chip 1773 U17 Write Precompensation is enabled when W6 goes high and Write Precompensation is enabled from software This signal is multiplexed with by W6 is fed into pin 20 of U17 Write Data is output pin 22 of U17 and is shaped by one shot 1 2 of 056 which stretches the data pulses to approximately 500 nsec 123 Floppy Disk Controller Chip The 1773 is an MOS LSI device which performs the functions of a floppy disk formatter controller in a single chip implemen tation The following port addresses are assigned to the internal registers of the
121. ctors and a grounding wire 3 Nine screws attach the main logic PCB to the metal pan The board is spaced away from the pan with raised bosses stamped into the pan 3 8 KEYBOARD ASSEMBLY 1 The keyboard assembly is attached to the Main Logic PCB with connector located at the right rear of the board The PCB must be removed from the pan to allow this connector to be removed Therefore disassembly procedures for the main PCB must be followed 2 The keyboard assembly is disassembled by removing the 7 mounting screws from the underside of the assembly One of these screws is under a cork non skid strip and care should be taken in removing this strip that it is not or punctured 3 Remove the top cover lift the keyboard PCB from its po sitioning bosses and then remove the keyboard connector the cable assembly requires replacement feed the nector through the opening in the keyboard base then in stall tiewrap around the cable just before the insulation Sleeve This serves as a strain relief for the cable when the keyboard is reassembled Ensure that this tiewrap is in the recess between the opening in the case and the clamping bosses on the bottom of the case Also ensure that on reassembly the PCB is properly posi tioned on the bosses of the base before attaching the top cover KEYBOARD CABLE ASSEMBLY Figure 3 2 Keyboard Cable Strain Relief 3 9 DISK DRIVE ASSEMBLY The disk d
122. d sys tem program called MODEL is supplied with the Model 4P to provide the ROM image for proper operation On power up the Boot ROM is selected and mapped into location 0000 0FFFH If the Boot ROM is not required after boot up the Boot ROM must be mapped out by OUTing to port 9CH with DO set or by selecting Memory Map modes 2 or 3 In Mode 1 the RAM is write enabled for the full 14K This allows the RAM area mapped where Boot ROM is located to be written to while ex ecuting out of the Boot ROM Refer to Memory Maps The Model 4P Boot ROM contains all the code necessary to initialize hardware detect options selected from the keyboard read a sector from a hard disk or floppy and load a copy of the Model III ROM image as mentioned into the lower 14K of RAM The firmware is divided into the foliowing routines Hardware Initialization Keyboard Scanner Control Floppy and Hard Disk Driver Disk Directory Searcher File Loader Error Handler and Displayer RS 232 Boot Diagnostic Package Theory of Operation This section describes the operation of various routines in the ROM Normally the ROM is not addressable by normal use However there are several routines that are available through fixed calling locations and these may be used by operating sys tems that are booting On a power up or RESET condition the Z80 s program counter is set to address 0 and the boot ROM is switched in The
123. d at time and compare is made against the pattern MODEL for the filename and for the extension The means that any character will match this position the user pressed one of the selection keys A G during the keyboard scan then that character is substituted in place of the 96 character For example if you pressed D then the search would be for the MODELD with the extension Ill The searching algorithm searches until it finds the entry or it reaches the end of the directory Once the entry has been found the extent information for that file is copied into a control block for later use File Loader The file loader is actually two modules the actual loader and a set of routines to fetch bytes from the file on disk The loader is invoked a RST 28H The byte fetcher is called by the loader using RST 20H Since restart vectors can be re directed the same loader is used by the RS 232 boot The difference is that the RST 20H is redirected to point to the RS 232 data re ceiving routine The loader reads standard loader records and acts upon two types 01 Data Load 1 byte with length of block including address 1 word with address to load the data n bytes of data where n 2 equals the length specified 02 Transfer Address 1 byte with the value of 02 1 word with the address 10 start execution at Any other loader code is treated as a comment block and is ig nored Once an 02 record has
124. d is AC cou pled by C209 Part of the output power at R206 is returned to a vertical drive by the NF loop which is made up of C205 C206 R207 and VR202 providing lineality compensation to the elec tric current which passes across the deflection yoke Flyback Generator A pulse that exceeds the source voltage 20V is generated at the vertical output terminal Pin 8 of 201 during retrace The Flyback pulse generator which consists of D201 C211 and a part of IC201 boosts the source voltage for that period accordingly Horizontal Sync Amp ATTL compatible positive going horizontal drive signal from P 6 is wave shaped by C301 and R301 amplified by Q301 and applied to the Pin 1 of IC301 174 Phase Detector The negative going horizontal pulse is applied to a filter that consists of R306 C306 and C310 used as a sawtooth wave for comparison and is AC coupled via C305 and flows to Pin 3 of 1C301 The retrace part of horizontal sawtooth wave and the horizontal sync signal are applied to a phase detector and exist on Pin 4 of the phase detector This output is used for the phase control of DC through the filler consisting of C307 C308 and R305 Horizontal Oscillator A horizontal pulse is provided through the horizontal oscillator circuit consisting of C311 and 12301 This oscillator signal is phase controlled according to the signal from the phase detec tor out Pin 4 of 1 301 The horizontal oscillator frequency is adjust
125. del 4P routes the cassette latch to the sound board through U109 When the CASSMOTORON signal is a logic low the cassette motor is off then the cassette output is sent to the sound circuit 5 2 14 VO Bus Port The Model 4P Bus is designed to allow easy and convenient in terfacing of I O devices to the Model The I O Bus supports all the signals necessary to implement a device compatible with the 2805 I O structure 118 Addresses AO to A7 allow selection of up to 256 input and 256 output devices if external 1 is enabled Ports 80H to OFFH are reserved for System use Data 080 to DB7 allow transfer of 8 bit data onto the processor data bus is external is enabled Control Lines 1 1 Z80A signal specifying an M1 or Operation Code Fetch Cycle or with it specifies an Interrupt acknowledge 2 IN Z80A signal specifying than an input is in progress Logic AND of IOREQ and WR 3 OUT Z80A signal specifying that an output is in prog ress Logic AND of IOREQ and WR 4 Z80A signal specifying that an input or output is in progress or with M1 it specifies an interrupt acknowledge 5 system reset signal 6 IOBUSINT input to the CPU signaling an interrupt from an VO Bus device if I O Bus interrupts are enabled 7 IOBUSWAIT input to the CPU line allowing I O Bus device to force wait states on the 280 if external is enab
126. divided into the following routines Hardware Initialization Keyboard Scanner Control Floppy and Hard Disk Driver Disk Directory Searcher File Loader ErrorHandler and Displayer RS 232 Boot Diagnostic Package Theory of Operation This section describes the operation of various routines in the ROM Normally the ROM is not addressable by normal use However there are several routines that are available through fixed calling locations and these may be used by operating sys tems that are booting On power up or RESET condition the Z80 s program counter is set to address 0 and the boot ROM is switched in The mem ory map of the system is set to Mode 0 See Memory Map for details This will cause the 780 to fetch instructions from the boot ROM The Initialization section of the Boot ROM now performs these functions Disables maskable and non maskable interrupts Interrupt mode 1 is selected Programs the CRT Controller Initializes the boot ROM control areas in RAM Sets up a stack pointer Issues a Force Interrupt to the Floppy Disk Controller to abort any current activity Sets the system clock to 4mhz Sets the screen to 64 x 16 9 Disables reverse video and the alternate character sets Tests for lt gt key being pressed Clears all 2K of video memory Q O N 10 11 This is a special test If the lt gt is being pressed then control is trans
127. dress then that address will be used when loading is complete If the image is already present it will use 3015H 3 Two different tests are done to insure that the Model ROM image is present The first test is to check ever third location starting at 3000H for a C3H This is done for 1010 cations If any of these locations does not contain a C3H then the ROM image is considered to be not present The next test is to check two bytes at location 000 If these addresses contain E9E1H then the ROM image is considered to be present 4 See Disk Director Searcher for more information 5 See File Loader for more information 6 The RS 232 loader is described under RS 232 Boot Disk Directory Searcher When the Model III ROM image is to be loaded it is always read from the floppy in drive 0 Before the operation begins some checks are made First the boot sector is read in from the floppy and the first byte is checked to make sure it is either a or a FEH If the byte contains some other value no attempt will be made to read the ROM image from that disk The location of the directory cylinder is then taken from the boot sector and the type of disk is deter mined This is done by examining the Data Address Mark that was picked up by the Floppy Disk Controller FDC during the read of the sector If the DAM equals 1 the disk TRSDOS 1 x style disk the DAM equals 0 then the disk is LDOS 5 1 TRSDOS 6
128. e Break Pressing this key is simply re corded by setting location 405BH non zero It is up to an operating system to use this flag if desired Terminates the Keyboard rou tine Any other keys pressed up to that time will be acted upon lt Enter gt is useful for experi enced users who do not want to wait until the keyboard timer expires Enter The Control section now takes over and follows the following flowchart Begin or 1 Goto 1 lt F2 gt lt 2 gt pressed 3 pressed Goto 3 Goto 41 RS 232 Boot lt Right Shift pressed At this point no valid Function have been Display an error message ARCNET Boot ROM required for ARCNET Boot Hard Disk Boot Goto 2 Floppy Disk Boot Model III Boot 91 Hard Disk Drive Present lt F1 gt or lt 1 gt pressed Floppy Disk Drive Present Attempt to read boot sector Display Hard Disk Error Message Attempt to read boot sector Set Transfer Address to 3 15H Note 2 lt F2 gt or lt 2 gt pressed Yes Attempt to locate ROM Image on Floppy Disk Note 4 Write enable 37FFH Mode 1 pressed Note 1 Load ROM Image Note 5
129. e DRVSEL Port Address 4 F7 Access WRITE ONLY Description Output Configuration Note Output to this port will ALWAYS cause a 1 2 mscc DO 01 02 03 04 05 Note D7 Microsecond wait to the Z80 DRIVE SELECT 0 DRIVE SELECT 1 RESERVED RESERVED SDSEL 0 SIDE 0 1 SIDE 1 PRECOMPEN 0 No write precompensation 1 Write Precompensation enabled WSGEN 0 No wait state generated 1 wait state generated This wait state is to sync Z80 with FDC chip during FDC operation 0 Single Density enabled FM Double Density enabled DISKOUT Port Address FO F3 Access WRITE ONLY Description Output to FDC Control Registers Port FO FDC Command Register Port F1 Track Register Port F2 FDC Sector Register Port F3 FDC Data Register Refer to FDC Manual for Bit Assignments Name DISKIN Port Address FO Access READ ONLY Description Input FDC Control Registers Port FO FDC Status Register Port F1 FDC Track Register Port F2 FDC Sector Register Port FDC Data Register Refer to FDC Manual for Bit Assignment Name MODOUT Port Address EC EF Access WRITE ONLY Description Output to Configuration Latch DO RESERVED D1 CASSMOTORON Sound enable 0 Cassette Motor Off Sound enabled 1 Cassette Motor On Sound disabled D2 MODSEL 0 64 or 80 character mode
130. e 64 by 16 format When updates to the video RAM are performed by the CPU the CPU is held in a WAIT state until the CRTC is not addressing the video RAM This operation allows reads and writes to video RAM without causing hashing on the screen The circuit that performs this function is 74LS244 buffer U84 an 8 bit transparent latch 74LS373 U83 and a Delay line circuit shared with Dynamic RAM timing circuit consisting of 741574 098 74LS32 096 741504 095 74LS00 092 74LS02 069 and Delay Line 094 During a CPU Read Access to the Video RAM the address is decoded by the GA 4 2 and asserts VIDEO low This is inverted by U95 1 6 of 74LS04 which pulls one input of U92 1 4 of 74LS00 and in turn asserts VWAIT low to the CPU RD is high at this time and is latched into U98 1 2 of 74LS74 on the rising edge of XADR7 inverse of CRTCLK 112 When RD is latched by U98 the Q output goes low releasing WAIT from the CPU The same signal also is sent to the Delay Line U94 through 0117 1 4 of 74F08 The Delay line delays the falling edge 240 ns for VLATCH which latches the read data from the video RAM at U83 The data is latched so the CRTC can refresh the next address location and prevent any hashing MRD decoded by U106 and a memory read is ORed with VIDEO which enables the data from U83 to the data bus The CPU then reads the data and completes the cycle CPU write is slightly more complex in operation As in
131. e Array 4 2 0106 The proper timing signals RASO RAS1 and CAS are generated by a delay line circuit U94 U116 1 2 of a 748112 and U117 1 4 of a 74F08 are used to generate a precharge circuit During M1 cycles of the Z80A in 4 MHz mode the high time in has a minimum time of 110 nanosecs The spec ification of 6665 DRAM requires a minimum of 120 nanosecs so this circuit will shorten the MREQ signal during the M1 cycle The resulting signal PMREQ is used to start a RAM memory cycle through U114 a 74S64 Each different cycle is controlled at U114 to maintain a fast M1 cycle so no wait states are re quired The output of 0114 PRAS is ANDed with RFSH to not allow MUX and CAS to be generated during a REFRESH cycle PRAS also generates either RASO or RAS1 depend ing on which bank of RAM the CPU is selecting GCAS gen erated by the delay line U94 is latched by U116 1 2 of a 745112 and held to the end of the memory cycle The output of U116 is ANDed with VIDEO signal to disable the CAS signal from occurring if the cycle is a video memory access Refer to M1 Cycle Timing Figure 5 8 and 5 9 Memory Read and Memory Write Cycle Timing Figure 5 10 and Figure 5 11 WVY AZE AS g Ag gi YLVIS ass 9594045 g 8008 wou 38 1146 OSGIA XI ATNO NPT Wa
132. e circuit of Figure 5 45 has three parts In a the IC s 02 and are biased ON by resistors R11 and R22 These re sistors also sense the changes in AC line input voltage to pro vide line regulation U2A is the LED half of an optocoupler which serves to isolate the DC ground circuits of primary and secondary while coupling the AC feedback signal via optical coupling U3 serves as both a stable DC reference voltage which the output voltages are compared against and as an er ror amplifier which provides the gain necessary for adequate sensitivity of the control IC to load changes 12V Output 12V 5 Volt Output c Load Sense Figure 5 45 Feedback Signal Development Each of the passive components the load sensing network is Power Chain a high stability 100ppm part to assure stability of the net work over the operating temperature range of the power supply In sense we have already analyzed the power chain in the section on basic principle of operation The base drive causes Part b of Figure 5 45 includes the network which tailors the the switching transistor to turn on and off at prescribed rate frequency response of the error amplifier so that it responds to This action alternately stores energy from the DC input in the low frequency change only This network consisting of R14 C5 primary inductance and releases it into the secondary through and R13 C4 also determines the stability of the power supp
133. e sec ondary voltage Vsec is a replica of the primary voltage Vsw Diode D is now forward biased due to the polarity of the inductor windings and because the turns ratio n is such that Vsec x n gt Vo This biasing replenishes the charge in capacitor C that was de livered to the load R during the ta tb interval This is the back interval and is so named because the inductor releases the energy stored in its magnetic field while the switch is OFF Several other facts are illustrated by the waveforms of Figure 5 36 First the voltage across the switch Vsw decays exponen tially from 2Vin to Vin during the OFF interval This is because the inductor and the switch timing are adjusted to transfer all of the energy that was stored in the inductor while the switch was ON into the secondary while the switch is OFF Observe that Isec DECREASES linearly with time to zero at the end of the OFF time period This is known as resetting the core Thus at time tc when the switch is ready to turn on again the DC input voltage Vin is again available to charge the inductor Also at this time all currents in the inductor are zero Second since we have assumed that Isw increases linearly with time and that the ON and OFF time periods are equal 50 duty cycle the average current in the primary Isw av is 1 4 the peak current Isw Also the average current in the second which is equal to the load current is 1
134. e system software enables write precompensation for all tracks greater than twenty one The amount of write precompensation is 125 nsec and is not adjustable One or two drives may be controlled by the inter face All data transfers are accomplished by CPU data re quests In double density operation data transfers are synchronized to the CPU by forcing a wait to the CPU and clear ing the wait by a data request from the FDC chip The end of the data transfer is indicated by generation of a non maskable in terrupt from the interrupt request output of the FDC chip hardware watchdog timer insures that any error condition will not hang the wait line to the CPU for a period long enough to destroy RAM contents 120 input or Output Cycles READ CYCLE DATA BUS WAIT WRITE CYCLE DATA BUS inserted by Z80 CPU Input or Output Cycles with Wait States DATA BUS READ CYCLE RD DATA BUS WRITE CYCLE EXTIOSEL Inserted by 280 CPU tCoincident with only on INPUT cycle Figure 5 34 Bus Timing Diagram 121 Control and Data Buffering The Floppy Disk Controller Board is an port mapped device which utilizes ports E4H F H F1H F2H F3H and F4H The decoding logic is implemented on the CPU board Refer to Par agraph 5 1 5 Address Decoding for more information on Port Map U70 is a bi directional 8 bit
135. ed VR301 Horizontal Drive The horizontal oscillator output which is phase controlled as stated above is applied to the horizontal drive buffer for am plification through 12301 and goes out on Pin 7 of IC301 X Ray Protection When supplied with excessive source voltage more than about 14V the X ray protection of IC301 works to terminate the hor izontal oscillator to prevent the CRT from emiting X rays over the regulated amount High voltage causes CRT s to emit more X ray radiation than allowed Horizontal Out Output power at Pin 7 of the horizontal control process IC is ap plied to Q303 through T301 0303 operates a switching func tion with about 21p sec OFF and 42 sec ON An electrical current of sawtooth waves comes to DY501 through Q303 ac tuating a switching function and a dumper diode which helps to deflect the electron beams Electrical current passes across DY501 This pulse voltage is enhanced by the FBT rectified and used as the anode voltage 11KV focus voltage 450V or video voltage 60V The output pulse at the collector of Q303 is rectified to be dou bled 160V and provided as the voltage for internal bright ness and focus TVLNOZIHOH 301534083 40193130 INAS 10231 525 301949435 YOLVHINID MOVE AVIA 110 TVOILH3A 483 2018 10221 4344na 925 304911550
136. emory map and port map decode In Model mode only the status can be read from memory location 37E8 or 37E9 The status can be read in all modes by an input from ports F8 FB For a listing of the bit status refer to Port Map section After the printer driver software determines that the printer is ready for printing by reading the correct status the characters to be printed are output to Port F8 FB 02 74LS374 eight bit latch latches the character byte and outputs to the line printer One half of U1 74LS123 a one shot is then triggered which generates an appropriate strobe signal to the printer which sig nifies a valid character is ready The output of the one shot is buffered by 1 6th of the U51 74LS04 to prevent noise from the printer cable from false triggering the one shot CTI WW zw Oj 6t z tn OL TVNESINI OT L4IES TVNNSINI 52 8 89 77 ara ee 490 oO Y Y XX ei tee he 0 53 93 2 10 1 era gm um EN 312182 LS gaus 280 viva 85 85 cen Figure 5 30 Video Circuit Timing 115
137. ence of the microcomputer with the ex ception of the FDC circuit comes from a 20 2752 MHz Crystal Oscillator Y1 This reference is divided and used for gener ating all necessary timing for the CPU video circuit and RS 232 C circuit The output of the crystal oscillator is filtered by a ferritte bead FB5 470 ohm resistor R46 and a 68 pf ca pacitor C242 After being filtered is fed into 0126 a 16R6A PAL Programmable Array Logic where it is divided by 2 to generate a 10 1376 MHz signal 10M for the 64 X 16 video dis play U126 divides the 20 2752 MHz by 4 to generate a 5 0688 MHz signal RS232CLK for the baud rate generator in the RS 232 C circuit The CPU clock is also generated by U126 which can be either 2 or 4 MHz depending on the state of FAST input 23 pin 9 of U126 If FAST is a logic low the 20 2752 MHz is di vided by 10 which generates a 2 2752 MHz signal If FAST isa logic high the 20 2752 MHz is divided by 5 which generates a 4 05504 MHz signal The CPU clock PCLK is fed through an active pull up circuit which generates a full 5 volt swing with fast rise and fall times required by the 2804 1126 16R6A PAL generates all symmetrical output signals and also does not al low the PCLK output to short cycle or generate a low or high pulse under 110 nanoseconds which the Z80A also requires Refer to System Timing Fig 5 2 5 1 4 1 Video Timing The video timing is controlled by a 10L8 PAL U127 and
138. er Status Read Only 2 3800 3BFF Keyboard 1K Mode 2 SELO 0 3000 3FFF Video 1K SEL1 1 5 4000 FFFF 48 X Don t Care 0000 F3FF RAM 61K Mode 0 SELO 0 OV F400 F7FF Keyboard 1K SELI 0 OV F800 FFFF Video 2 0 5 0000 37FF RAM Read Only 14K Mode 3 5510 1 5V 3758 3729 Printer Status Read Only 2 5511 1 5V 3800 3BFF Keyboard 1K ROM X Don t Care 3C00 3FFF Video 1K 4000 FFFF RAM 48K 0000 FFFF RAM 64K Mode 1 5510 1 5V 5511 0 ROM 1 0V 0000 OFFF Boot ROM 4K 0000 OFFF RAM Write Only 4K 1000 37FF RAM 10K 3800 3BFF Keyboard 1K 3000 3FFF Video 1K 4000 FFFF RAM 48K 45 10 Port Assignment Normally Port Used FC FF FF F8 FB F8 F4 F7 F4 FO FO FI F1 F2 F2 F3 F3 EC EF EC 8 EB E8 E8 E9 E9 EA EA E4 E7 4 E0 EO A0 DF 9 9 9C 94 9B 90 93 90 8C 8F 88 8 88 88 89 88 89 84 87 84 80 83 CASSOUT LPOUT DRVSEL DISKOUT FDC COMMAND REG FDC TRACK REG FDC SECTOR REG FDC DATA REG MODOUT RS2320UT UART MASTER RESET BAUD RATE GEN REG UART CONTROL AND MODEM CONTROL REG UART TRANSMIT HOLDING REG WR NMI MASK REG WR INT MASK REG RESERVED BOOT RESERVED GSELO CRTCCS CRCT ADD REG CRCT DATA REG OPREG 65511
139. errors from the disk call of the byte fetch call and 0 The ROM image was not found on drive 0 There are several pieces of information left in memory by the boot ROM which are useful to system programmers These are shown below RAM Location Description 401DH ROM Image Selected for none selected or A G 4055H Boot type 1 Floppy 2 Hard disk 3 4 5 232 5 7 Reserved 4056 Boot Sector Size 1 for 256 2 for 512 4057H RS 232 Baud Rate only valid on RS 232 boot 4059H Function Key Selected 0 function key selected lt 1 gt or lt 1 gt 86 lt F2 gt or lt 2 gt 87 lt F3 gt or lt 3 gt 88 lt Caps gt 85 84 lt Left Shift gt 82 lt Right Shift gt 83 Reserved 80 81 and 89 90 405BH Break Key Indication non zero if lt Break gt pressed 405CH Disk type 0 for LDOS TRSDOS 6 1 for TRSDOS 1 x Keep in mind that Model ROM image will initialize these areas so this information is useful only to the Model 4 mode programmer 5 2 7 RAM Two configurations of Random Access Memory RAM are available on the Model 4P 64K and 128K The 64K and 128K option use the 6665 type 64K x 1 200NS Dynamic RAM which requires only a single 5 supply voltage 98 The require multiplexed incoming address lines This is accomplished by ICs 0110 and 0111 which 74LS157 multiplexers Data to and from the DRAMs are buffered by a 7418245 U118 which is controlled by Gat
140. etermine the source of the non maskable interrupt Data bit 7 indicates the status of FDC in terrupt request INTRQ 0 true 1 false Data bit 6 indicates the status of Motor Time Out 0 true 1 false Data bit 5 in dicates the status of the Reset signal 0 true 1 false The control signal gates this status onto the CPU data bus when active logic low Drive Select Latch and Motor ON Logic Selecting a drive prior to disk operation is accomplished by doing an OUT instruction to port F4H with the proper bit set The following table describes the bit allocation of the Drive Select Latch Data Bit Function DO Selects Drive 0 when set D1 Selects Drive 1 when 86 D2 Selects Drive 2 when set D3 Selects Drive 3 when set D4 Selects Side 0 when reset Selects Side 1 when set D5 Write precompensation enabled when set disabled when reset D6 Generates WAIT if set D7 Selects MFM mode if set Selects FM mode if reset Only one of these bits should be set per output Hex D flip flop U54 74L174 latches the drive select bits side select and FM MFM bits on the rising edge of the control signal DRVSEL Gate Array 4 4 018 is used to latch the Wait Ena ble and Write precompensation enable bits on the rising edge of DRVSEL The rising edge of DRVSEL also triggers a one shot 1 2 of U54 74LS123 which produces a Motor On to the disk drives The duration of the Motor On signal is approxi mately
141. fd 50V Mono Axial 8374104 C101 106 Capacitor 1 mfd 50V Mono Axial 8374104 C108 111 Capacitor 1 mfd 50V Mono Axial 8374104 114 118 Capacitor 1 mfd 50V Mono 1 8374104 121 Capacitor 1 mfd 50V Mono Axial 8374104 C124 Capacitor 1 mfd 50V Mono Axial 8374104 C125 Capacitor 1 mfd 50V Mono Axial 8374104 C129 Capacitor 1 mfd 50V Mono Axial 8374104 C133 140 Capacitor l mfd 50V Mono Axial 8374104 C142 Capacitor 1 mfd 50V Mono Axial 8374104 C143 Capacitor 1 mfd 50V Mono Axial 8374104 C146 Capacitor 1 mfd 50V Mono Axial 8374104 C148 Capacitor 1 mfd 50V Mono Axial 8374104 C153 160 Capacitor 1 mfd 50V Mono Axial 8374104 C201 211 Capacitor 22 mfd 16V Elec Rad 8326221 C212 Capacitor 1000 50V C Disk Rad 8302104 C213 Capacitor 022 mfd 50V C Disk 8303224 C214 Capacitor 022 mfd 50V C Disk 8303224 C215 Capacitor 10 mfd 16V Elec Rad 8326101 C216 Capacitor 33 pfd 50V C Disk Npo Ax 8300334 C217 Capacitor 22 pfd 50V C Disk NPO Ax 8300224 C218 Capacitor 1 mfd 50V Mono Axial 8374104 C219 Capacitor 200 pfd 50V C Disk Z5U 8301223 Rad C220 Capacitor 22 pfd 50V C Disk NPO Ax 8300224 137 Parts List Model 4P Gate Array PC Board 210 01 RI R3 5 R6 R8 R9 R10 11 12 R13 R14 R15 17 R18 R19 R20 R21 23 R24 R25 R26 R27 R28 R29 R30 Ferrite B Connector Connector Header Connector Header Connector Connector Connector Connector Transisto Resistor Resistor Resistor Resistor Resistor Resistor
142. ferred to the diagnostic package in the ROM All other keys are scanned via the Keyboard Scanner nn Tl WIOLYO f 1 1 x QVO I f SAVO T EEE nn d Og 1 11 Uu uuvuuuuuuuuuuuuuuuuuu utes 80 x 24 Mode 64 x 16 Mode Figure 5 20 Video Timing x Luqvx ag Y ps gt RESTA ru n Taris Er RAM UUUUUUUVUUVUUUUUUVUUUUUVUUWUUN 40 24 32 16 Figure 5 21 Video Timing 89 Keyboard scanner is now called It scans the keyboard for a set period of time and returns several parameters based on which if any keys were pressed The keyboard scanner checks for several different groups of keys These are shown below Function Group Selection Group F2 1 2 lt 3 gt lt Left Shift gt lt Right Shift gt lt Ctrl gt lt Caps gt gt Special Keys Misc Keys lt P gt lt Enter gt lt L gt lt Break gt When any key the Function Group is pressed it is recorded in RAM and will be used by the Control routine in directing the action of the boot more than one of these pressed during the keyboard scan the last one detected will be the one that is used The Function group keys are currently defined as Will cause
143. gradually by the soft start circuit Vosc volts Ul 5 Vlogic Vreg vdt 0 time Vout volts 01 pin 8 time 25 microsec Figure 5 40 Oscillator Pulse Generator Waveforms 7 01 MC34060 Regulator Section 5 volt Reference Regulator R23 Pulse er Section 22 Pulse width 03 Comparator To Shut down Modulator Error R19 Vrek Base Drive Feedback R10 v from current limit 87 Figure 5 41 Control Sectlon 151 Frequency stability of the sawtooth oscillator is provided by 2 tolerance and polyester construction of the timing capaci tor C7 and the 100 parts per million temperature stability and 1 tolerance of R3 Voltage stability of the DC control voltages is provided by the 2 1 2 percent stability of the 5 0 volt reference The control section consists of two error amplifiers in U1 the primary half of U2 and associated circuitry shown in Figure 5 41 One of the error amplifiers serves as a regulator or pulse width modulator which derives the DC control voltage Vreg from the signal voltage developed across R7 by the current U2 This current is a replica of the current developed by U3 in response to the condition of the output voltage at the 5 1v and 12v outputs This amplifier has a gain of about 10 deter mined by R8 22k ohm
144. gure 5 48 is known as the control chain To see how the regulation action occurs assume small negative voltage change at the input of the feedback network and follow it through the control chain This negative voltage change which would correspond to a slightly heavier load current appears at pin 1 of 03 as a de creasing voltage The error amplifier U3 inverts and amplifies this signal The positive going output voltage of 03 at pin 3 causes less current to flow in the internal LED of U2A A replica ofthis smaller current optically coupled and induced in the pho totransistor of U2B develops a reduced voltage across R7 at the non inverting input of the regulator error amplifier in U1 5 1V Output from oscillator Pulse width Comparator Modulator Error Amp The regulator error amplifier in U1 does not invert the signal but further amplifies it improving the sensitivity of the control chain to small changes at the power supply output The regulator er ror amplifier output is Vreg Since we established earlier that a negative going Vreg increases the length of the base drive pulse Q7 is turned on a little sooner so that it can store more energy from the AC line in the primary inductance Finaily this increased energy is stored in the filter capacitor C10 C11 dur ing the flyback interval and supplies the increased demand for current that resulted in the original reduction in the output voltage
145. hard disk boot Will cause floppy disk boot Will force Model III mode Reserved for future use Boot from RS 232 port Reserved for future use Reserved for future use lt 1 gt or lt 1 gt lt F2 gt or lt 2 gt lt F3 gt or lt 3 gt lt Left Shift gt lt Right Shift gt Ctrl Caps The Special keys are commands to the Control routine which direct handling of the Model ROM image Each key is de tected individually lt P gt When loading the Model Ill ROM image the user will be prompted when the disks can be switched or when ROM BASIC can be entered by pressing lt Break gt lt N gt Instructs the Control routine to not load the Model ROM image even if it appears that the operating system being booted requires it lt gt Instructs the Control routine to load the Model ROM image even if itis already loaded This is useful if the ROM image has been corrupted or when switch ing ROM images Note that this will not cause the ROM image to be loaded if the boot sector check indicates that the Model ROM image is needed Press F3 or F3 and lt L gt to accomplish that The Selection group keys are used in determining which file will be read from disk when the ROM image is loaded For details of this operation see the Disk Directory Searcher If more than one of the Selection group keys are pressed the last one de tected will be the one that is used The Miscellaneous keys ar
146. ic low U78 inverts the signal to a logic high which is read by the CPU 114 5 2 10 Real Time Clock The Real Time Clock circuit in the Model 4P provides a 30 Hz in the 2 MHz CPU mode or 60 Hz in the 4 MHz CPU mode interrupt to the CPU By counting the number of interrupts that have occurred the CPU can keep track of the time The 60 Hz vertical sync signal VSYNC from the video circuitry is used for the Real Time Clock s reference In the 2 MHz mode FAST is a logic low which sets the Preset input pin 4 of 023 741574 to a logic high This allows the 60 Hz VSYNC to be divided by 2 to 30 Hz The output of 1 2 of U23 is ORed with the original 60 Hz and then clocks another 741574 1 2 of U23 If the real time clock is enabled ENRTC at a logic high the interrupt is latched and pulls the INT line low to the CPU When the CPU recognizes the interrupt the pulse is counted and the latch re set by pulling low In the 4 MHz mode FAST is a logic high which keeps the first half of 023 in a preset state Q output at a logic low The 60 Hz is used to clock the interrupts NOTE interrupts are disabled the accuracy of the real time clock will suffer 5 2 11 Line Printer Port The Line Printer Port Interface consists of a pulse generator an eight bit latch and a status line buffer The status of the line printer is read by the CPU by enabling buffer 03 7415244 This buffer is enabled by LPRD which is a m
147. icate ON gt mo 65 5 1 17 CPU Board Troubleshooting Guide 13 Check all handshaking signals to FDC chip from CPU If okay go to 14 if bad repair as necessary This section is general guide for service personnel to check out and troubleshoot the Model 4P Main Logic CPU Board Pro 14 Check Data Bus and control lines cedures in section 4 Troubleshooting should be followed before If okay then problem still exists in Floppy Disk Circuit or proceeding to following steps This guide will provide step by Fioppy Disk Drive Refer to each section accordingly If step procedures to help isolate the faulty area on the CPU bad replace as necessary board Knowledge of each area of the CPU board is necessary to determine exact component failure Refer of CPU Board 15 If unit boots okay then boot Model Diagnostics Diskette Schematics and Theory of Operation during troubleshooting for and execute each diagnostic to isolate any minor problems specific check points and testing on CPU Board 1 No video messages are displayed and correct data does not appear at video output connector J If above condition exists to 2 if video okay but Model 4P does not boot properly go to 10 If video and boot up is okay go to 15 2 Check for video timing signals 12M and 10M and input of U127 If okay go to 3 if one or both bad go to 7 3 Check for proper timing signals output from 0127 SHIFT XAD
148. ient circuitry to satisfy performance and reliability specifications The complete block diagram is shown in Figure 5 37 12 disk output filters secondary 12v CRT overvoltage crowbar conductor output filter output filter 5 secondary 12v secondary 0 12v sense T load sense 5V adj feedback signal compensation Figure 5 37 Power Supply Block Diagram feedback isolation 145 The other blocks provide additional output voltages add safety or protective features reduce circuit noise and develop signals for use by the control section The control section continuously operates the bipolar transistor switch and varies the proportion of ON time to OFF time in response to changes in AC input line voltage or output load current This is accomplished by feeding back signal from the output terminals and instructs the control section to increase or decrease the ON time to compensate for a change in the output voltage The DC voltage supply to the control section is controlled by the latch circuit when AC power is first applied to the power supply A built in timing circuit allows the input DC supply filter capaci tor to become fully charged before power is applied to the con trol section After the control section circuit starts and secondary voltages reach their regulated output
149. ignal DCLK from Gate Array 4 1 0148 in 64 x 16 and 80 x 24 If okay go to 3 if one or both modes bad to 7 3 Check for proper timing signals output from 9148 SHIFT XADR7 LOAD LOADS If okay then go to 4 if one or more bad replace U148 or 0128 4 Check if 68046 1 42 is working properly and has correct in put signals If all okay then go to 5 If bad replace U42 or check for in put signals where they originate 5 Check for timing and proper signals U102 If bad replace as necessary if okay go to 6 6 Check output of pin 4 of U142 and repair as necessary 7 Check for 20M clock at pin 2 of U148 If okay to 8 if bad replace 1 or 0148 8 Check for outputs of U148 PCLK RS232CLK okay then go to 9 if any bad replace 0148 9 Check for 12M at output of U146 pin 8 If okay then video should work if bad replace 146 10 Run Memory Test in Boot ROM by holding down period and toggling Reset If memory checks okay then to 11 if not check mem ory circuit and or replace RAM chips 11 Check Clock circuit of Floppy Disk Controller If 18MHz and 8 MHz okay go to 12 if bad repair or replace necessary components 12 Check for all incoming signals to the chip 017 any bad repair as necessary if okay go to 13 13 Check all handshaking signals to FDC chip from CPU If okay to 14 if bad repair as necessary 14 Check Data Bus
150. ilter formed by R35 and C22 prevents false detections on transient signals that don t represent an over current condition 154 As soon as 09 turns on its collector current develops the turn on bias for Q8 across R33 and the Q8 Q9 pair latches in the ON state until the DC source for the latch is removed Re moval of this DC source occurs when C1 discharges through thus removing DC voltage from the control IC Notice also that the kick start latch Q4 and Q5 is still in the ON state and thus provides a discharge path for C14 When the decreasing voltage across C14 is less than approximately one volt the Q4 Q5 latch also switches off At this point in time all circuits are in an OFF condition except the input DC supply C14 now begins to re charge toward the input DC supply to restart the power supply If a fault remains the kick start and current limit circuits will continue to shut down and re start the power supply several times per second until the fault is removed or AC power to the supply is turned off Under Voltage Lockout The Under Voltage Lockout UVL shuts down the supply whenever the AC input voltage drops below about 90 volts This occurs when the voltage at pin 13 set by the divider action of R27 and R25 diminishes to a level below the internal reference supply of the control IC Pulses are inhibited immediately and because the DC supply to the Control IC is no longer replen ished by the auxiliary
151. ine Printer Port done ie ed be repre ere ped eee e eT EI Graphics Lex osa ERR aS RAUS dyst dar CREEK EG Sound ies nene pem er ee eh VOBUS Port 22222 unen eru rele Rhe FDC Circuit a s bosse Ste e m Sad e ta RENS ER TOR RN DN E H9 232C Circuit psi ee ae ea e NE Troubleshooting specific Schematic8000192 5 o ry eU ra S dd do Diet 1700254 euer nu up Parts List PCB Assembly 4P Gate Array Theory of Operation 85 CPU Theory of Operation 222522220555 Ht OR e eie 85 Introduction o E Ones CoA ales po 85 Reset Circilits SES ea aede ng n babak 85 CPU i Sd aqu 85 5 2 4 5 2 5 5 2 6 5 2 8 529 5 2 10 5 2 11 5 2 12 5 2 13 5 2 14 5 2 15 5 2 16 5 2 17 5 3 5 4 1 5 4 2 5 4 3 5 4 4 5 4 5 5 4 6 SECTION Vi ADDENDA 0 2 Address Decode aa be wet Deaton RAM VideoCircuit Keyboard
152. ing the M1 cycle The resulting signal PMREQ is used to start RAM memory cycle through U113 a 74564 Each different cycle is controlled at U113 to maintain a fast M1 cycle so no wait states are re quired The output of U113 PRAS is ANDed with RFSH to not allow and CAS to be generated during a REFRESH cycle PRAS also generates either RASO or RAS1 depend ing on which bank of RAM the CPU is selecting GCAS gen erated by the delay line U97 is latched by U115 1 2 of a 748112 and held to the end of the memory cycle The output of 0115 is ANDed with VIDEO signal to disable the CAS signal from occurring if the cycle is a video memory access Refer to M1 Cycle Timing Figure 5 8 and 5 9 Memory Read and Memory Write Cycle Timing Figure 5 10 and Figure 5 11 AS g 1745 398 ALVIS OSGIA AJAYA 89 4 388 NINO WEN f 8008 Ag I WON Ag 1195 Af g g1as TIYIS T T 87170 a WT AL MI GddASN RINO M T WON 1004 B Ag 1 AB g 8 AS T 914 TALI ALVIS AZE WWE waa WWE AZE UTD NI cara 9 HOVANE NPT
153. ircuit in the Model 4P is the 68045 Cathode Ray Tube Controller U42 The CRTC 15 preprogrammed video controller that provides two screen formats 64 by 16 and 80 by 24 The format is controlled by pin 3 of the CRTC 8064 The generates of the neces sary signals required for the video display These signals are VSYNC Vertical Sync HSYNC Horizontal Sync for proper sync of the monitor DISPEN Display Enable which indicates when video data should be output to the monitor the refresh memory addresses 0 13 which addresses the video RAM and the row addresses RA0 RA4 which indicates which scan line row is being displayed The CRTC also provides hard ware scrolling by writing to the internal Memory Start Address Register by OUTing to Port 88H The internal cursor control of the 68045 is not used in the Model 4P video circuit Since the 80 by 24 screen requires 1 920 screen memory lo cations a 2K by 8 static RAM U82 is used for the video RAM Addressing to the video RAM U82 is provided by the 68045 when refreshing the screen and by the CPU when updating of the data is performed These two sets of address lines are mul tiplexed by three 74151575 041 061 and 081 The multi plexers are switched by CRTCLK which allows the CRTC to address the video RAM during the high state of CRTCLK and the CPU access during the low state A10 from the CPU is con trolled by PAGE which allows two display pages in th
154. is a logic low the cassette motor is off then the cassette output is sent to the sound circuit 5 1 14 I O Bus Port The Model 4P Bus is designed to allow easy and convenient in terfacing of I O devices to the Model The I O Bus supports all the signals necessary to implement a device compatible with the 280 I O structure 57 Addresses AO to A7 allow selection of up to 256 input and 256 output devices if external I O is enabled Ports to OFFH are reserved for System use Data DBO to DB7 allow transfer of 8 bit data onto the processor data bus is external I O is enabled Control Lines 1 1 280 signal specifying an 1 or Operation Code Fetch Cycle or with IOREQ it specifies an Interrupt acknowledge 2 IN 280 signal specifying than an input is in progress Logic AND of IOREQ and WR 3 OUT 2804 signal specifying that an output is in prog ress Logic AND of IOREQ and WR 4 IOREQ Z80A signal specifying that an input or output is in progress or with 1 it specifies an interrupt acknowledge 5 system reset signal 6 IOBUSINT input to the CPU signaling an interrupt from an I O Bus device if I O Bus interrupts are enabled 7 IOBUSWAIT input to the CPU wait line allowing Bus device to force wait states on the 280 if external 1 is enabled 8 EXTIOSEL input to Bus Port circuit which switches the Bus data bus
155. is enabled by LPRD which is a memory map and port map decode In Model mode only the status can be read from memory location 37 8 or 37E9 The status can be read in all modes by an input from ports F8 FB For a listing of the bit status refer to Port Map section After the printer driver software determines that the printer is ready for printing by reading the correct status the characters to be printed are output to Port F8 FB U2 a 74LS374 eight bit latch latches the character byte and outputs to the line printer One half of U1 74LS123 a one shot is then triggered which generates an appropriate strobe signal to the printer which sig nifies a valid character is ready The output of the one shot is buffered by 1 6th of the U21 74LS04 to prevent noise from the printer cable from flase triggering the one shot LILII CITE ub O 26 943 hor 200000000 men Bukse aeg 1990 58 ag indu 10945 indui oye VIO AR MA SNUOSIAVM 517690 1 QI LAHS DO Y Y KAY arava RAAAXAAAAWYY Pas viva arva 280 TVUS VES Figure 5 13 Video Circuit Timing 61 90 0 5488 Svaka S SAVOT 441 9 1
156. ister U92 and the Status register U44 which allow the CPU to see which kind of interrupt has occurred Interrupts can be generated on receiver data register full transmitter reg ister empty and any one of the errors parity framing or data overrun This allows minimum of CPU overhead in transfer ring data to or from the UART The interrupt mask register is port EO write and the interrupt status register is port EO read Refer to the IO Port description for a full breakdown of all inter rupts and their bit positions All Model I and 4 software written for the RS 232 C interface is compatible with the Model RS 232 C circuit provided the software does not use the sense switches to configure the in terface The programmer can get around this problem by di rectly programming the and for the desired configuration or by using the SETCOM command of the disk operating system to configure the interface The TRS 80 RS 232C Interface hardware manual has a good discussion of the 5 232 standard and specific programming examples Cat alog Number 26 1145 Pinout Listing The following list is a pinout description of the DB 25 connector P1 Pin No Signal 1 PGND Protective Ground TD Transmit Data RD Receive Data RTS Request to Send CTS Clear To Send DSR Data Set Ready SGND Signal Ground CD Carrier Detect SRTS Spare Request to Send DTR Data Terminal Ready RI Ring Ind
157. istic the duty cycle is also equal to Vosc pk Vreg ton duty cycle d Vosc pk T period There are three possible conditions of the duty cycle d 0 which occurs when either control voltage Vreg or Vdt exceeds the peak value of the sawtooth waveform Vosc d 50 which occurs when Vreg is less than V t This happens when the loading on the output of the suppiy is heaviest and the AC input voltage is at its lowest permitted level see specifications 0 lt d lt 50 which occurs during normal operation The dead time control voltage is used in one other important way Notice the 4 7 ufd capacitor C2 connected across R4 in Figure 5 41 When power is first applied to the supply the age across the capacitor is zero Therefore Vdt Vref 5 0 volts and no pulses appear at the output because is greater than Vosc pk As C2 charges Vdt decreases toward 1 2 Vosc pk in a time determined by R5 and C2 ast 5x15k ohm X 4 7 ufd 1 3 second Vdt decreases past Vosc pk very narrow pulses begin appearing at pin 8 of U1 The pulses be come successively wider until Vdt is less than Vreg C2 contin ues charging until Vdt reaches the final correct value of about 1 5 volts This action provides the soft start feature of the power supply and allows sufficient time for the DC input supply and latch to reach normal operating conditions before the supply is started In effect the load is connected to the supply
158. it Holding Reg Refer to Model IIl or 4 Manual for Bit Assignments Name RS232lN Port Address E8 Access READ ONLY Description Input UART and Modem Status Port 8 MODEM STATUS Port 9 RESERVED Port EA UART Status Register Port UART Receive Holding Register Resets DR Refer to Model or 4 Manual for Bit Assignments WRNMIMASKREG Port Address E4 Access WRITE ONLY Description Output NMI Latch 00 05 RESERVED D6 ENMOTOROFFINT 0 Disables Motoroff 1 Enables Motoroff D7 0 Disables INTRQ 1 Enables RDNMISTATUS Port Address 4 57 Access READ ONLY Description Input Status DO 0 D2 D4 RESERVED D5 RESET not needed 0 Reset Asserted Problem 1 Reset Negated D6 MOTOROFF 0 Motoroff Asserted 1 Negated D7 INTRO 0 INTRQ Asserted 1 INTRQ Negated Name WRINTMASKREG Port Address Access WRITE ONLY Description Output INT Latch 50 01 RESERVED 02 0 Real time clock interrupt disabled 1 Real time clock interrupt enabled D3 ENIOBUSINT 0 External IO Bus interrupt disabled 1 External IO Bus interrupt enabled 04 0 85232 Xmit Holding Reg empty int disabled 1 5232 Xmit Holding Reg empty int enabled D5 ENRECINT 0 232 Rec Data Reg full int disabled 1 232 Rec
159. it provides the neccessary reset pulses to circuits during power up and reset operations R25 and C218 provide a time constant which holds the input of U121 low during power up This allows power to be stable to all cir cuits before the and RESET signals are applied When C218 charges to a logic high the output of U121 triggers the input of a retriggerable one shot multivibrator U1 U1 outputs a pulse with an approximate width of 70 microsecs When the reset switch is pressed on the front panel this discharges C218 and holds the input of U121 low until the switch is released On release of the switch C218 again charges up triggering U121 and 01 to reset the microcomputer 5 1 3 CPU The central processing unit CPU of the Model 4P microcom puter is a Z80A microprocessor The Z80A is capable of run ning in either 2 MHz or 4 MHz mode The CPU controls all functions of the microcomputer through use of its address lines 0 15 data lines DO D7 and control lines M1 RD MREQ and RFSH The address lines A0 A15 are buffered to other ICs through two 74LS244s U68 and U26 which are enabled all the time with their enables pulled to GND The control lines are buffered to other ICs through a 74F04 U86 The data lines 00 07 are buffered through a bi direc tional 7415245 U71 which is enabled by BUSEN and the di rection is controlled by BUSDIR 5 1 4 System Timing The main timing refer
160. ity amp overrun errors framing amp overrun errors parity amp framing amp overrun errors B D E F G H The message Error is then transmitted to the host The entire process is then re peated from the Not Ready message A six second delay is inserted before reinitialization This is longer than the time re quired to transmit five bytes at 50 baud so there is no need to be extra careful here If the sync byte is received without error then the Loading message is transmitted and the program is ready to receive the command file After receiving the Loading message the host can transmit the file without nulls or delays between bytes 96 Since the file represents Z80 machine code and all 256 combinations are meaningful it would be disastrous to transmit nulls or other ASCII control codes as fillers knowledgement or start stop bytes The only control codes needed are the standard command file control bytes Data can be transmitted to the loader at 19200 baud with no de lays inserted Two stop bits are recommended at high baud rates See the File Loader description for more information on file loading receive error should occur during file loading the abort pro cedure described above will take place so when attempting re mote control it is wise monitor the host receiver during transmission of the file When the host is near the object board as is the ca
161. lay They are compact low profile drives that require only half the space normally required The drives use an ANSI compatible Indus try Standard 5 1 4 inch diskette and contain 48 tracks per inch Two different types of drives are used in the Model 4P One is double sided recording device Both are capable of reading and writing in single density format on a diskette The drives have double density capability when a Modified Frequency Modulated MFM or other appropriate recording technique is used Encoding and decoding of the data is done by the user s controller Service information and schematics for the Mini Disk Drive are contained in the Manufacturer s Operating and Service Manual at the rear of this manual 5 4 POWER SUPPLY ASSEMBLY 5 4 1 Power Supply Basic Principle switching power supply circuit employs high speed semi conductor switch to control the storage and release of electrical energy in an inductor and provide regulated output voltages with a minimum loss of energy in heat dissipating elements There are several schemes for achieving this result which differ primarily in the arrangement of the basic circuit elements These elements include switch an inductor rectifier ca pacitor and a DC voltage source An arrangement well suited for economical power supplies with rated power outputs under 100 watts is the FLYBACK CON VERTER shown in Figure 5 35 The waveforms in Figure 5 36 are used to
162. led 8 EXTIOSEL input to Bus Port circuit which switches the I O Bus data bus transceiver and allows and INPUT in struction to read I O Bus data The address line data line and all control lines except RESET are enabled only when the ENEXIO bit in port EC is set to one To enable interrupts the ENIOBUSINT bit in the PORT EO output port must be a one However even if itis disabled from generating interrupts the status of the IOBUSINT line can still the appropriate bit of CPU IOPORT input port See Model Port Bit assignments for port OFF OEC and LOG a ee 5 33 Graphic Board Video Timing 119 The Model CPU boardis fully protected from foreign de vices in that all the I O Bus signals are buffered and can be dis abled under software control To attach and use and I O device on the Bus certain requirements both hardware and soft ware must be met For input port device use you must enable external I O devices by writing to port OECH with bit 4 on in the user software This will enable the data bus address lines and control signals to the Bus edge connector When the input device is selected the hardware should acknowledge by asserting EXTIOSEL low This switches the data bus transceiver and allows the CPU to read the contents of the 1 Bus data lines See Figure 5 17 for the timing EXTIOSEL
163. lt F3 gt or lt 3 gt pressed Goto 3 Model III Boot Goto 4 lt Right Shift RS 232 Boot pressed At this point no valid Function keys have been pressed ARCNET Controller Board Present 2 Display an error message ARCNET Boot ROM required for ARCNET Boot 30 Hard Disk Drive Present Attempt to read boot sector Display Hard Disk Error Message F1 or 1 pressed Floppy Disk Drive Present Attempt to read boot sector Model IIT ROM Image Present F2 or 2 pressed Yes Display Floppy Disk Error Message lt N gt pressed 256 bytes and no ref s Note 1 Set Transfer Address to 43778 Note 2 lt I gt pressed Note 3 31 Set Transfer Address to 37158 Note 2 Attempt to locate ROM Image on Floppy Disk Note 4 ROM Image Found Note 4 Write enable 37 Mode 1 Load ROM Image Note 5 Errors while loading ROM Image Display Error Message Set Transfer Address at end of ROM Image Normally 37158 Note 2 ROM Image Present pressed Display ROM Image is loaded message Wait for lt ENTER gt or lt BREAK gt to
164. ltiplexer 74LS14 Hex Inverter 74 502 2 Input NOR 741508 Quad 2 Input AND 741588 Quad 2 Input NAND 74LS157 Multiplexer 74LS51 AND OR Inverter 741 308 Quad 2 Input 74LS86 Quad 2 Input OR 7415368 Hex Driver 741 5244 Octal Buffer 74LS245 Transceiver 74LS244 Octal Buffer 74 4 Hex Inverter Z8 A CPU MCM68A322 Boot ROM 74LS138 1 of 8 Demultiplexer 7419138 1 of 8 Demultiplexer 82 8929123 8020374 8020244 8020038 8020008 8020004 8020245 8020244 8020367 8020004 8020074 8727002 8010032 8049007 8020244 8020166 8929175 8819884 8020153 8020244 8949116 8828157 8040045 8020273 8020373 8020157 8020014 8020002 8020008 8020000 8020157 8929951 8929999 8020086 8020368 8020244 8020245 8020244 8015004 804788 8929138 8020138 Parts List Main PCB Assembly Model 4P Computer Item Description Part Number U47 PAL1gL8 Control Decode 8875698 048 741590 Counter 8020090 959 PALL6R6A System Timing 8 75 66 051 IC PAL19L8 Video Timing 8875788 052 564 PLL VCO 8849564 053 741504 Binary Counter 8020904 054 7415161 Counter 8828161 055 7415138 1 of 8 Demultiplexer 8929138 056 7415244 Octal Buffer 8929244 057 IC 7415174 Flip Flop 8020174 058 7415273 Flip Flop 8020273 059 IC 7418174 Flip Flop 8 2 174 U6 741574 Flip Flop 8828874 U62 PAL16L8 Memory 8075668 U63 PAL16L8 Page 8875568 0
165. ly the flyback transformer action The energy is then stored in the by ensuring that the power supply control circuit has no tend input filter capacitor at a voltage determined by the transformer to oscillate turns ratio Notice that the turns ratio determines the ratio of col lector voltage to secondary voltage both of which are alternat Part c illustrates the load sensing network Equal currents ing voltages The ratio of input to output DC voltage is through R15 are supplied from the 12V DISK and 5 05V determined by the duty and the turns ratio together outputs by R29 and R30 In addition portion of the transient signal occurring on the 12V CRT output when the motors For example let s look at the 5 volt output of Figure 5 31 at turn on or off is fed to R15 by 17 The wiper of R15 feeds normal loading and approximtely 120 input Under these control signal which represents the status of the current loads conditions the DC input voltage is 168 and the duty cycle to the error amplifier 03 03 amplifies and compensates it then 15 approximately 40 Thus our average DC voltage at the U2 couples that control signal to U1 where it is used to vary the switching transistor collector or across the primary is 40 of switching transistor Q7 ON time to adjust the output voltages 168 or 67 5 volts Dividing this average voltage by the turns as necessary R15 is adjustable to provide the initial se
166. me comparator Fig ure 5 40 illustrates the sawtooth oscillator and output circuit waveforms and the approximate levels of the DC control volt ages applied by the comparators to the wave shaping logic The oscillator frequency is set by the values of R3 and C7 shown in Figure 5 41 The amplitude of the sawtooth is set at 3 0 volts approximately 60 of the 5 0 volt reference voltage Whenever the sawtooth voltage Vosc exceeds both of the DC control voltages Vreg and the output circuit will be in the ON condition The DC control voltage Vreg set at a quiescent value by R6 and 89 varies in response to changes in the supply s DC out put voltages as sensed by U3 and coupled through U2 Notice that these voltages will vary because of changes in output load ing AC input voltage and also because of the residual 120 Hz ripple component from the main DC supply The dead time control voltage Vdt is set at a constant value by R4 and R5 and ensures that the pulse generator OFF time will be at least 5096 of the sawtooth period This allows ade quate time for the complete transfer of stored energy from the primary to the secondary of transformer T1 as discussed in the section on basic principles 150 A concept known as duty cycle was introduced in earlier para graphs Duty cycle is defined as the ratio of the ON time of the sawtooth cycle to the total length of the sawtooth period Since the sawtooth has a linear ramp character
167. mined by the inductance of the transformer primary winding When the output transistor of U1 turns off the emitters of Q1 and 02 are initially at the 6 volt level determined by the charge on C8 the Vbe drop of Q7 and the drop across R37 Both base emitter junctions of the Q1 Q2 Darlington pair are biased ON and the positive terminal of C8 is clamped to near ground by the saturating Q1 At this point C8 Still has most of its charge and the base voltage of Q7 is approximately 4 5 volts with respect to ground 160V 5 6 07 Turn 07 ON 97 5 Turn 07 OFF 5 42 Base Drive Circuit 07 10 0 eee time 5 4 5 710 25 gt Figure 5 43 37 Base Voltage Waveform With the strong reverse polarity provided by C8 across the base emitter junction of Q7 the forward charge stored in the junc tion capacitance is quickly swept out and Q7 is turned off continues to discharge through R24 to prepare for the next ON cycle R19 limits the initial discharge of C8 while Q7 is turning off Notice the symmetry in the base drive circuit and the key role played by C8 in both the turn on and turn off sequences Be cause of this crucial role in the circuit this capacitor is specified as a high temperature low equivalent series resistance component a Primary b Snubber Primary Circuit and Current Limit Shutdown The Primary Circuit The Primary circuit shown
168. n is at address 0005 The hardware must be in memory mode 0 or else the boot ROM will not be switched in This operation can be done with an OUT instruction and then a RST 0 can be executed to have the ROM switched in Restarts redirected at any time while the ROM is switched in All restarts jump to fixed locations in RAM and these areas may be changed to point to the routine that is to be executed Restart RAM Location Default Use 0 Cold Start Boot 8 4000H Disk I O Request 10 4003H Display string 18 4006H Display block 20 4009H Byte Fetch Called by Loader 28 400CH File Loader 30 400FH Keyboard scanner 38 4012H Reserved for future use 66 4015H NMI Floppy 1 0 Command Complete The above routines have fixed entry parameters These are de scribed here Disk Request RST 8H Accepts 1 for floppy 2 for hard disk B Command Initialize 1 Restore 4 Seek 6 Read 12 All reads have an im plied seek Sector number to read The contents of the location disktype 405CH are added to this value before an actual read If the disk is a two sided floppy just add 18 to the sector number DE Cylinder number Only is used in floppy operations HL Address where data from read opera tion is to be stored Returns 2 Success Operation Completed NZ Error Error code in Error Codes 3 Hard Disk drive is not ready 4 Floppy disk drive is not ready 5 Hard Disk drive is not available 6 Floppy
169. ng edge of the 4 MHz clock After U55 pin 9 goes high the data is shifted out at a 250 nsec rate EARLY will generate a 250 nsec delay NOT EARLY AND NOT LATE will generate a 500 nsec delay and LATE will generate a 750 nsec delay This provides the necessary precompensation for the write data As mentioned previously Write Precompensa tion is enabled through software by an OUT to the Drive Select Latch with bit 5 set This sets the Q output of the 74LS74 U98 pin 9 which is ANDed with DDEN which disables the shift reg ister U55 DDEN disables Write Precompensation in the single density mode The resulting signal also enables U75 to allow the write data WD to bypass the Write Precompensation cir cuit The Write Data WD pulse is shaped by a one shot 1 2 of U54 which stretches the data pulses to approximately 500 nsec 62 4 MHZ 2 MHZ 1 MHZ 21 1 CP Figure 5 18 Write Precompensation Timing 63 419 9 SHFT LD Clock and Read Data Recovery Logic The Clock and Read Data Recovery Logic is comprised of one U18 FDC9216 The FDC9216 is a Floppy Disk Data arator FDDS which converts a single stream of pulses from the disk drive into separate clock and data pulses for input to the FDC chip The FDDS consists of a clock divider a long term timing corrector a short time timing corrector and reclocking circuitry The reference clock REFCLK is a 4 MHz and is di vided by the internal clock divider
170. nsformer winding The inductor and the output capacitor form low pass filter which removes the switching frequency ripple component The current output of the 12 volt supply is much smaller than that of the positive voltage outputs Because of this the current limit circuit response is not sufficiently effective to prevent dam to the 12 volt circuit Therefore three terminal regulator with its own current limiting circuit is used to protect the 12 volt output Alt of the 12 volt rectifiers are fast recovery types and the 5 volt rectifier is Schottky type These diodes feature high switching speeds during turn off Their low forward voltage drop minimizes dissipation resulting in maximum efficiency Each of the positive outputs has a bleeder resistor 5 Input a Feedback Signal Processor b Frequency Response The reason for two separate 12 volt outputs is to provide suf ficient isolation between different types of loads It is easier to regulate the 12 volts if the load which contains the DC motors in the disk drives is separated from the rest of the loads In ad dition the 12 volt Disk output V3 is included in the load sense network in order to minimize the load transients which occur when the disk drives turn on and off The supply is then better able to regulate the other 12 volt output V2 during the severe V3 transitions Load Sense and Feedback Signal Development Th
171. nters for the CPU These address counters may be loaded before each RAM access or they may be programmed to automatically in crement or decrement after each memory access The outputs from the CPU X and Y address counters are multiplexed with the X and Y video address counter outputs to generate the dy namic memory addresses The remaining logic on the graphics board is composed of 4 de vices A 74LS245 is used to buffer CPU data into and out of the gate array 74L5367 is used to strobe RAM read data into the gate array 74LS134 is used to synchronize data from the RAMS 7415166 transforms the parallel video data into serial video data which is mixed with the Model 4 CPU video 193 sn 93 521444 85 20 MHOMINV NIINISMTIS 6ETOOZI 338 4666048 0 08 4 9 SWALSAS AGNVL VSN NI 30 Lin 6n 286 803 AUNVL 3 MEE MEAE ID mer zn 12 in 52 2 338 00 000 9 194 Er RELEASED FOR PRODUCTION or ler et
172. olution 9 black and white display monitor with 64 or 32 characters per line by 16 lines in Model Ill mode and 80 or 40 characters per line by 24 lines in Model 4 4P mode Displays upper and lower case ASCII characters with descenders 96 special characters 64 alternate characters 64 graphics characters plus reverse video of all ASCII alpha numeric characters Two built in single sided double density 5 1 4 thin line floppy disk drives Each drive stores up to 184K bytes Data transfer rate is 250K bits per second 2 2 PERIPHERAL INTERFACES Standard Optionat BUS for connection of hard disk and other peripherals Serial Interface RS 232 C port One RS 232 C Serial Communications interface port which allows asynchronous and synchronous transmission Mates with DB 25 connector on back of the Model 4P Parallel Printer Interface Connection to a line printer via the 34 pin connector on the back of the Model 4P 640 x 240 High Resolution graphics board Auto answer Modem 300 baud 2 3 POWER REQUIREMENTS 105 130 Vac 60 Hz 240 Vac 50 Hz Australian 220 Vac 50 Hz European Grounded Outlet Maximum Current Drain 1 7 Amperes Typical Current Drain 1 5 Amperes 2 4 OPERATING TEMPERATURE 55 to 80 F 13 to 27 C 2 5 DIMENSIONS 9 3 x 16 5 W x 13 25 D 26 Ibs carrying weight SECTION III DISASSEMBLY ASSEMBLY DISASSEMBLY ASSEMBLY 3 1 OVERVIEW AND CASE The Model 4P is modular in construction
173. on 4 Schematic 23533 B W 23757 179 Parts list 8790612 B W 8790613 Green 181 Options E eie Goins 189 189 Exploded View Parts Lists Case Assembly ed quce Ede e an Mee Main Chassis 2 292 Disk Drive 416 enne Keyboard Assembly Tandon Operating and Service Manual TM50 1 and TM50 2 5 1 4 Flexible Disk Drives MODEL 4P 4P GATE ARRAY HARDWARE SECTION I INTRODUCTION INTRODUCTION 1 1 SYSTEM OVERVIEW The TRS 80 Model 4P Microcomputer is complete self con tained portable transportable version of the popular TRS 80 Model 4 Microcomputer It provides carrying protective case which has recessed carrying handle removable front cover which protects the CRT and disk drives and serves as base when in the portable configuration and self contained key board conveniently stowed away in a recess in the main case Power cord floppy disk and manual s
174. on 338 ohm 1 4W 5 Carbon 8 2 ohm 1 4W 5 Carbon 10 kohm 1 4W 5 Carbon 68 kohm 1 4W 5 Carbon l ohm 1 2W 5 Carbon 19 1 4W 5 Carbon 1 2 kohm 1 4W 5 Carbon 2 2 kohm 1 4W 5 Carbon 19 kohm 1 4W 5 Carbon 3 3 kohm 1 4W 5 Carbon 22 kohm 1 4W 5 Carbon 15 kohm 1 4W 5 Carbon 199 ohm 2W 5 Met Oxide 2 7 kohm 1 4W 5 Carbon 56 ohm 2W 5 Met Oxide 82 kohm 1 2W 5 Carbon 158 kohm 1 2W 5 Carbon 228 kohm 1 2W 5 Carbon 1 Mohm 1 4W 5 Carbon 220 1 4W 5 Carbon 228 kohm 1 4W 5 Carbon 158 kohm 1 4W 5 Carbon 159 ohm 1 4W 5 Carbon 159 ohm 1 4W 5 Carbon l ohm 2W 5 Metal Oxide 199 kohm 1 2W 10 Solid 479 ohm 1 2W 19 Solid 479 ohm 1 2W 19 Solid 56 kohm 1 2W 1 Solid 56 kohm 1 2W 19 Solid 56 kohm 6 8 ohm 1 2 ohm 4 7 kohm 229 kohm 15 75 15 75 KHz Drive KHz Flyback Signal Amp NPN Signal Amp NPN 187 1 4 5 5637 RD1 4MB S 6R8J RD1 2MB S 1R2J RD1 4MB S 4720 RD1 4MB S 224 7 1 4 5 3317 4 5 8627 1 4 5 1837 1 4 5 6837 1 2 5 1807 RD1 4MB S 1837 1 4 5 1220 RD1 4MB S 222J 1 4 8 131 RD1 4MB S 3327 1 4 5 223 4 5 1537 RSM2P1 1J RDL 4MB S 2727 RSM2P56 J RD1 2MB S 823J RD1 2MB S 154J RD1 2MB S 224J RD1 AMB S 185J RD1 4MB S 224J RD1 4MB S 224J RD1 4MB S 154J RD1 4MB S 151J RD1 4MB S 151J RSN2P1R J RC1 2GF1 4K RC1 2GF471K RC1 2GF471K RC1 2GF
175. on a sott surface to prevent damage to the CRT 3 The case is held in place with six screws Remove two Screws from either side of the case at the front of the unit To gain access to the last two screws press down on one end of the carrying handle and then lift the handle from its recess The final two case mounting screws are accessible under the handle assembly These two screws attach the handle assembly as well as the case to the internal rear mounting plate 4 After removing all six screws lift the cover off the computer and set it aside for reassembly Exercise care to prevent scratching or damaging the cover 3 2 INTERNAL REAR MOUNTING PLATE 1 Remove the case from the unit as noted in Paragraph 3 1 2 Therear mounting plate serves to provide mounting for the case carrying handle and protection for the CRT There are ten mounting screws which attach this plate to the main metal chassis of the computer Four screws Item 53 on exploded view p 144 two on each side mount the handle support Item 16 and are accessible from the LH and RH 13 side of the unit With the rear of the unit toward you two of these screws are located at the left just in front of the Disk Drive Assembly and accessible from the left side of the chassis assembly The two on the right are accessible from the rear of the chassis assembly 3 Sixother screws are located around the outside edges of the rear mounting plate Remove the plate and set it a
176. on for all tracks greater than twenty one The amount of write precompensation is 250 nsec and is not adjustable The data clock recovery logic incorporates a digital data separator which achieves state of the art reliability One or two drives may be controlled by the interface All data trans fers are accomplished by CPU data requests In double density operation data transfers are synchronized to the CPU by forc ing a wait to the CPU and clearing the wait by a data request from the FDC chip The end of the data transfer is indicated by generation of a non maskable interrupt from the interrupt re quest output of the FDC chip A hardware watchdog timer in sures that any error condition will not hang the wait line to the CPU for a period long enough to destroy RAM contents 59 Input or Output Cycles DATA BUS WAIT wre DATA BUS PORT ADDRESS Inserted 280 CPU Input or Output Cycles with Wait States A7 DATA BUS WAIT DATA BUS EXTIOSEL inserted by 280 CPU tCoincident with only on INPUT cycle T2 Figure 5 17 VO Bus Timing Diagram 60 READ CYCLE WRITE CYCLE READ WRITE CYCLE Control and Data Buffering The Floppy Disk Controller Board is an port mapped device which utilizes ports E4H F1H F2H decoding logic is implemented
177. on the CPU board Refer to Par agraph 5 1 5 Address Decoding for more information on Port 031 is bi directional 8 bit transceiver used to buffer data to and from the FDC and RS 232 circuits The direction of data transfer is controlled by the combination of control signals DISKIN and RS232IN If either signal is active logic low 031 is enabled to drive data onto the CPU data bus If both signals are inactive logic high U31 is enabled to receive data from the CPU board data bus A second buffer U12 is used to buffer the FOC chip data to the FDC RS232 Data Bus BDO BD7 U12 is enabled all the time and it s direction controlled by DISKIN Again if DISKIN is active logic low data is enabled to drive from the FDC chip to the Main Data Busses If DISKIN is in active logic high data is enabled to be transferred to the FDC chip Nonmaskable Interrupt Logic Dual D flip flop U100 74LS74 is used to latch data bits D6 and 07 on the rising edge of the control signal The outputs of U100 enable the conditions which will generate a non maskable interrupt to the CPU The NMI interrupt con ditions which are programmed by doing an OUT instruction to port E4H with the appropriate bits set If data bit 7 is set interrupt is enabled to generate an NMI interrupt If data bit 7 is reset interrupt requests request from the FDC are disabled If data bit 6 is set a Motor Time Out is enabled
178. on the front panel this discharges C214 and holds the input of U121 low until the switch is released On release of the switch C214 again charges up triggering U121 and U1 to reset the microcomputer Another signal POWRST is generated to clear drive select circuit immediately when reset switch is pressed 5 2 3 CPU The central processing unit CPU of the Model 4P microcom puter is a Z80A microprocessor The Z80A is capable of run ning in either 2 MHz or 4 MHz mode The CPU controls all functions of the microcomputer through use of its address lines 0 15 data lines 00 07 and control lines M1 WR MREQ and RFSH The address lines 0 15 are buffered to other ICs through two 74LS244s 067 and 027 which are enabled all the time with their enables pulled to GND The control lines are buffered to other ICs through 74F04 U87 The data lines D0 D7 are buffered through a bi direc tional 7418245 U86 which is enabled by BUSEN and the rection is controlled by BUSDIR 5 2 4 System Timing The main timing reference of the microcomputer with the exception of the FDC circuit is generated by a Gate Array U148 and a 20 2752 MHz Crystal This reference is inter nally divided in the Gate Array to generate all necessary tim ing for the CPU video circuit and RS 232 C circuit The CPU clock is generated U148 which can be either 2 or 4MHz depending on the logic state of FAST input pin 6 of U148
179. oot sector Most boot sectors will display a message if the system can not be loaded To save space these routines use the Model ROM calls to display the message Several ROM calls have their entry points in the first 256 bytes of mem and these references are detected by the boot ROM Packages that do not reference the Model ROM in the boot sector can still cause the Model ROM image to be loaded by coding a 00 somewhere in the boot sector It does not have to be executable At the same time Model 4 packages must take care that there is no sequence of bytes in the boot sector that could be mis interpreted to be a reference to the Boot ROM An example of this would be sequence 06CDOEOO0 which is a LD B OCDH and a LD C40 If the boot sector cannot be changed then the user must press the lt F3 gt key each time the system is started to inform the ROM that the disk contains a Model Ill pack age which needs the Model II ROM image 2 If you are loading a Model 4 operating system then the boot ROM will always transfer control to the first byte of the boot sector which is at 4300H If you are loading a Ill operating system or about to use Model ROM BASIC then the transfer address is 3015H This is the address of jump vector in the C ROM of the Model ROM image and this will cause the system to behave exactly like a Model III If the ROM image file that is loaded has a differ ent transfer ad
180. pesi s c Y 4 1 PROPRIETARY Mt EN Pag FT W nar PME NE REPRIOUCTION W ANT 00 Outs 0818 FORT WORTE 129 MEMORY CONTROL AND MEMORY DRAWING NG 8000233 RLE EET NA oF E E 1 er no ns PEN pur cpi t 5921448 3813 4443 3831 555 258 GE Gap ED vas NEC Pie 22 eno Ds ma 5 LT is E E PA 58849488 cp 6 PIN HEADER 5 555599 LM Gee pu BM 100pF T ur Str ENALTSET oe SRO poz seo ET woe p cm 45 os Snos tr or 2207 EDA SEA DR CS Motore DLYCHARK E or coi 02 E 8 05 sos og or ROT
181. pin 20 and RTS J4 pin 4 true Next Not Ready is printed on the topmost line of the video display Modem status line CD J4 pin 8 is then sampled The program loops until it finds CD asserted true At that time the message Ready is displayed Then the program sets about determining the baud rate from the host computer To determine the baud rate the program compares data re ceived by the UART to a test byte equal to 55 hex The receiver is first set to 19200 baud If ten bytes are received which are not equal to the test byte the baud rate is reduced This sequence is repeated until a valid test byte is received If ten failures occur at 50 baud the entire process begins again at 19200 baud If a valid test byte is received the program waits for ten more to ar rive before concluding that it has determined the correct baud rate If atthis time an improper byte is received or a receiver er ror overrun framing or parity is intercepted the task begins again at 19200 baud In order to get to this point the host or the modem must assert CD true The host must transmit a sequence of test bytes equal to 55 hex with 8 data bits odd parity and 1 or 2 stop bits The test bytes should be separated by approximately 0 1 second to avoid overrun errors When the program has determined the baud rate the message Found Baud Rate x is displayed on the screen where is a letter from A to P meaning A 50baud 150
182. plode To avoid this kind of accident carefully support the CRT when removing it from the chassis Do not handle the CRT by the neck as this may cause the tube to break and cause personal injury 14 6 Remove the four screws and washer from the front of the CRT which attach itto the metal chassis Carefully slide the CRT out of the chassis through the front 3 6 SWEEP BOARD The CRT Sweep Board is accessible after the CRT is removed from the unit It is mounted to the left side of the metal chassis with four screws An insulated plate is located between the PCB and the metal chassis Make sure this plate is in place on reassembly 3 7 MAIN LOGIC PCB The main logic PCB is a large board nested inside a metal pan atthe bottom of the main metal chassis To gain access to this assembly remove unit parts as noted in Paragraphs 3 1 and 3 2 It is not necessary to remove the power supply assembly or the CRT and associated PCB Remove all connectors at the rear of the unit These include the Modem connector port edge card connector printer edge card connector and floppy disk edge card connector 1 There are four screws on each side of the metal PCB mounting pan which attach the pan to the metal chassis Remove these screws and the board and pan can be re moved as subassembly from the chassis 2 Atthe front of the board remove the four connectors at the left front of the board These include the reset video and power conne
183. ponds to the affected area Step 1 Step 2 Rotate the magnet to obtain the desired video display labeled NORMAL in Figure 5 63 Step 3 If the desired video display cannot be obtained replace with proper magnet Figure 5 63 173 5 5 3 Theory of Operation Video Control The controlling voltage from P8 determines the level of TTL compatible positive and non composite video signal which is provided by the CPU Video Drive and Video Out Q102 and Q103 are connected in a cascade configuration The video signal of which the level is subject to the video control as stated above comes into the base of Q102 C102 and R105 compensate high frequency The video out signal with flat re sponse is amplified via Q103 and provided to the cathode of CRT501 The Vertical Control Process The vertical control process consists of four stages Vertical Oscillator Vertical Drive Vertical Out and Flyback Generator These four stages are processed by IC201 Vertical Oscillator A sawtooth wave pattern is generated through C204 R204 VR201 and an oscillator circuit and synchronized with the neg ative going vertical sync signal which is applied to pin 1 of IC201 Vertical Drive A vertical sawtooth wave is AC coupled to the vertical drive amp for linear amplification via C207 Vertical Out The vertical drive is linked to vertical out within IC 201 Vertical output from Pin 8 of IC201 is applied to DY501 an
184. pply Switching frequency components that could be con ducted out the AC input terminals are suppressed by the EMI filter to avoid interference with other equipment connected to the power line The overvoltage crowbar senses an abnormal rise in the 5 1 volt output and short circuits the voltage line to the common secondary ground thus tripping the current limiting circuit which finally shuts down the supply The surge limiter at the AC line input prevents the input filter ca pacitor in rush current surge from exceeding component rat ings or unnecessarily tripping external fuses 5 4 2 Technical Specifications Environment Temperature Operating Storage 01050 C 32 to 122 F 40 to 85 C 40 to 185 F Humidity Operating Storage 85 r h 35 95 95 r h 55 131 max Input Voltage 90 to 135 rms 47 to 63 Hz Input Surge Current 48 amps max Efficiency 70 min at full load with 115 rms input Output Voltages V1 5 05 VDC V2 12 VDC CRT V3 12 VDC DISK 12 VDC Output Power continuous 65 watts max Output Current Load Output Min Max V1 1 35 4 0 Condition 1 0 60 1 5 Model II use v3 0 40A 21 V4 0 005 A 0 10 Condition 2 v1 25A 5 0A Hard Disk use v3 0 75 2 0 V4 0 005 0 10 NOTE 2 connect in parallel to provide the output The output will support 5 0 peak load which deca
185. r If yes then refer to Ap pendix B Startup Error Messages in Introduction to Your Disk System TRS 80 Model 4 if not then go to 5 Insert Write Protected Diskette with TRSDOS 6 1 1 or later into Drive 0 close door and toggle RESET Switch Does 4P boot up to TRSDOS Logo and prompt for date If yes then go to 18 if not then go to 16 Does message The Floppy Disk Drive Is Not Ready still appear If yes then go to 17 if not then go to 10 Try to boot again or use another diskette If okay go to 18 If still same message then go to 19 If another message ap pears go to 9 This indicates that the problem area exists on the Main Logic CPU Board Refer to Section 5 1 17 or 5 2 17 CPU Board Troubleshooting for more detailed troubleshooting procedures This indicates a hardware failure of Floppy Disk interface or Floppy Disk Drive Refer to Section 5 1 17 or 5 2 17 CPU Board Troubleshooting or Section 5 3 Mini Disk Drive Maintenance Checks or Adjustments SECTION 4P THEORY OF OPERATION 4 5 1 CPU THEORY OPERATION 5 1 1 Introduction Contained in the following paragraphs is description of the component parts of the Model CPU It is divided into the log ical operational functions of the computer All components are located on the Main CPU board inside the case housing Refer to Section 3 for disassembly assembly procedures 5 1 2 Reset Circuit The Model 4P reset circu
186. r Springrip 17 2 Rivet Blind 203 Ve q lt lt On Boy 204 Chassis Assembly Parts List Chassis Assembly Model 4P Computer Assembly 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 18 1 11 8 12 1 13 1 14 1 15 1 16 1 17 1 18 2 19 2 27 2 21 1 22 1 23 1 24 1 25 1 26 1 27 1 50 22 51 4 52 4 53 4 54 6 55 2 56 2 57 2 58 8 59 28 68 2 61 2 Chassis Weldment Connector Power Cord Fan 12 VDC Bracket Switch Mount Potentiometer 5 ohm Contrast Potentiometer 5 kohm Brightness Power Switch 125V Reset Switch CRT Sweep PCB Assembly B W CRT Sweep PCB Assembly Green Insulator Sweep PCB Clip Standoff Mount Power Supply Insulator Power Supply Power Supply PCB Assembly Cover Back Support Handle Bezel Clawbolt Top Stiffener Bezel Case Knob Potentiometer Logo Model 4P Main PCB Assembly Pan Assembly PCB Support Cover Plate Blank Cover Plate I O Port Label FCC Part 15 Class A Label Part 15 Class B Screw 6 x 1 4 Rolok Screw 8 32 x 1 2 Washer Hd Washer 8 Internal Lock Screw 48 32 x 3 8 PH Screw 8 Hex Washer Head Thd Form Screw 4 4 x 3 4 PH Chrome Nut 4 4 Lock Screw 10 32 x 1 2 PPH Screw 46 32 x 3 8 PPH Screw 6 x 1 4 Hex Hd Torque Brk Screw 10 x 1 2 Hex Hd Form Screw 4 48 x 1 4 PPH Mach Noted on Case Assembly also 205 8859028 8519813 8790406 8719363 82611504 82624
187. r reads to Graphics Board RAM ENGRAF is asserted when Graphics video is displayed ENGRAF also disables inverse video mode on Main Logic Board Video CL166 Clear 74L166 is used to enable or disable mixing of Main Logic Board Video and Graph ics Board Video If CL166 is negated high then mixing is al lowed in all for video modes 80 x 24 40 x 24 64 x 16 and 32 16 If CL166 is asserted low this will clear the video shift reg ister U63 which allows no video from the Main Logic Board In this state 8064 is automatically asserted low to put screen in 80x24 video mode Refer to Figure 5 16 Graphic Board Video Timing for timing relationships Refer to the Model 4 4P Graph ics Board Service information for service or technical informa tion on the Graphics Board 5 1 13 Sound The sound circuit in the Model 4P is compatible with the Sound Board which was optional in the Model 4 Sound generated by alternately setting and clearing data bit DO during an OUT to port 90H The state of DO is latched by U130 1 2 of a 74LS74 and the output is amplified by Q2 which drives a piezoelectric sound transducer The speed of the software loop determines the frequency and thus the pitch of the resulting tone Since the Model 4P does not have a cassette circuit some existing software that used the cassette output for sound would have been lost The Model 4P routes the cassette latch to the sound board through U142 When the CASSMOTORON signal
188. r with four screws Remove the connectors attached to the power supply at the left and then four screws to remove the sup ply completely from the unit 4 Whenreassembling ensure that the mylar insulator is po sitioned between the power supply and the top cover to provide proper insulation 3 5 CATHODE RAY TUBE The CRT is mechanically attached to the metal chassis with four screws which are accessible from the front of the unit 1 Remove the case rear terminal cover and top cover power supply as noted in Paragraphs 3 1 3 2 3 3 and 3 4 This allows access to the connections on the CRT 2 Disconnect the deflection yoke cable from the CRT PC board 3 Disconnect the connector on the rear of the CRT neck which is attached to a small PC board WARNING The anode of the CRT may have a high voltage charge Before removing the high voltage anode lead discharge the CRT as follows to prevent a serious shock Connect one end of a wire to a known good ground and the other end of the wire to the metal shaft of an insulated handie screwdriver Insert the screwdriver blade under the suction cup and touch it to the clip holding the high voltage lead 4 Disconnect the high voltage lead by inserting a grounded screwdriver under the cup Use the screwdriver to com press the clip and pull the wire free 5 Disconnect the ground wire fastened at the splice to the CRT neck connector PCB CAUTION If the CRT is dropped it may im
189. re in the DC input supply or current limiting circuits Auxiliary Power Supply The auxiliary power supply is operational when the main supply is on and not in a shut down condition This power supply con sists of winding 2 3 on T1 half wave rectifier CR4 and filter ca pacitor C14 The voltage output is approximately 15 volts under normal conditions but momentarily reaches about 31 volts during start up Kick Start Latch Start up of the circuit is initiated by the kick start latch This latch is shown in simplified form in Figure 5 39 a along with the ac companying waveforms in Figure 5 39 b When power is ap plied C14 charges toward Vin 160 volts through R26 with a time constant of approximately RC or 37 5 seconds How ever as we ll see the kick start latch turns on in 2 or 3 seconds the time required for the voltage across C14 to reach 30 Vbe4 30 7 volts At this point Q4 turns on and develops bias across R21 which turns on Q5 Referring to Figure 5 39b as C14 dumps its charge into C1 be ginning at time t2 the voltage across C14 starts to decrease to ward a level that will be determined by the load composed of U1 and the base drive circuit Notice that the voltage across C1 momentarily approaches the full 31 volts at time t3 before it drops down under load to about 15 volts at time t4 b Waveforms ves lt vstart time time tl t2t3 4 tl Power applied 2 Latch turns
190. ress Output port device use is the same as the input port device in use in that the external I O devices must be enabled by writing to port OECH with bit 4 on in the user software in the same fashion For either input or output devices the IOBUSWAIT control line can be used in the normal way for synchronizing slow devices to the CPU Note that since dynamic memories are used in the Model 4P the wait line should be used with caution Holding the CPU in a wait state for 2 msec or more may cause loss of mem contents since refresh is inhibited during this time It is rec ommended that the IOBUSWAIT line be held active no more than 500 psec with 25 duty cycle The Model 4P will support Z80 Mode 1 interrupts A RAM jump table is supported by the LEVEL BASIC ROMs image and the user must supply the address of his interrupt service routine by writing this address to locations 403E and 403F When an in terrupt occurs the program will vectored to the user sup plied address if Bus interrupts have been enabled enable Bus interrupts the user must set bit of Port OEOH 5 1 15 FDC Circuit The TRS 80 Model 4P Floppy Disk Interface provices a stan dard 5 1 4 floppy disk controller The Floppy Disk Interface supports both single and double density encoding schemes Write precompensation can be software enabled or disabled beginning at any track although the system software enables write precompensati
191. rical 19631 1 Cord Terminal 31601015 1 Cord Terminal 3168101 48A C181 Capacitor 4 7 uF 5 V Elec 20 CE 4 475 5 C102 Capacitor 129 pF 59V Cer 10 CK45B1H121K 103 Capacitor 8 1 uF 59V Mylar 103 092 41181 4 C1 4 Capacitor 22 uF 199V Elec 20 CE 4C226M1 V C105 Capacitor 22 uF 5 v Cer CK45E2H222P 201 Capacitor 022 uF 5 Mylar 10 CQ92M1H223K 202 Capacitor 22 uF 5 Mylar 1 CQ92M1H223K 203 Capacitor 1 uF 5 V Mylar 10 CQ92M1H1 3K 204 Capacitor 33 uF 16 Tant 10 515 1 334 205 Capacitor 4 7 uF 16V Tant 10 515 1 475 C286 Capacitor 4 7 uF 16V Tant 10 CS15E1C475K C287 Capacitor 33 uF 16V Elec 20 4 336 16 208 Capacitor 33 uF 16 Elec 2 4 336 16 C2 9 Capacitor 338 uF 35V Elec 205 4 337 35 C210 Capacitor 33 uF 5 V Mylar 19 CQ92M1H333K C211 Capacitor 22 uF 16V Elec 20 4 227 16 C212 Capacitor 4 7 uF 5 Elec 29 8 4 47585 301 Capacitor 220 pF 5 Cer 10 CK45B1H221K C3 2 Capacitor 47 uF 5 V Elec 10 4 474K5 v C383 Capacitor 199 pF 5 V Cer 10 CK45B1H101K C3 4 Capacitor 022 uF 5 Mylar 10 CQ92M1H223K C385 Capacitor l8 uF 59V Mylar 10 CQ92M1H183K C3 6 Capacitor 018 uF 5 Mylar 10 CQ92M1H183K C387 Capacitor 4 7 uF SAV Elec 203 CE 4C475M5 v C388 Capacitor 1 uF 5 Mylar 10 CQ92M1H1 3K C3 9 Capacitor
192. rive assembly contains two floppy disk drives It must be removed as a subassembly to the main metal chassis before the mounting screws for the drives themselves are accessible 1 There are seven mounting screws which attach this subassembly to the main metal chassis all of which are accessible from the right side of the unit Four of these are located at the top of the assembly Two screws are located under the disk drive assembly at the front but accessible with a long shank screwdriver from the right side A sev enth screw mounts a tab to the metal chassis at the rear of the assembly After this subassembly is removed from the unit screws which mount the drives in the housing are accessible There are two screws at the top and one at the bottom NOTE Do not place a screw in the bottom rear mounting hole when reinstalling the disk drives into the metal housing In stallation of this screw can cause possible flexing of the drive and alignment problems 15 DISK DRIVE SUBASSEMBLY BOTTOM PAN Figure 3 3 Disk Drive Assembly RH Side View 3 10 CONTROL MODULE The control module is attached to the left front of the metal chassis with two screws Remove component parts as noted in Paragraphs 3 1 3 2 and 3 3 to allow access to the control module 1 The module contains the unit power switch reset switch and brightness contrast controls for the CRT display All wiring to the control module is the plug in kind att
193. s all of the dynamic memory timing signals and high speed timing for the other logic The large bulk of the work is provided by the gate array device As shown in Figure 5 66 this gate array interfaces to CU for memory read or write cycles The gate array also uses video timing signals from the Model 4 CPU board to gen erate X and Y video addresses and multiplexes the video addresses with the CPU X and Y counter addresses to drive the RAM address bus The remaining logic on the board is the dynamic RAM and the shift register logic The RAM is organized as 64K x 4 however this organization is translated to 32K x 8 by the gate array From the output at the RAM the video data is latched for time synchroni zation and then turned into serial video data by the shift The timing logic is composed of a PALIOL 8 and 74 574 dual flip flop This logic generates RAS CAS and for the dy namic RAM It also generates timing synchronization signals XADR7 STROBE1 and STROBE2 Figure 5 67 shows a tim ing diagram for these signals The input signals are provided by the Model 4 CPU board and change depending on the mode of operation DCLK is 10 MHz for 512 x 192 graphics H and J are the outputs from a counter clocked by DCLK Figure 5 68 shows the equations for the PALIOLB register CPU warm DATA BUFFER 0 CLEAR CPU SHIFT BUS register GRAPHICS CHIP SELECT d
194. s the keyboard for set period of time and returns several parameters based on which if any keys were pressed The keyboard scanner checks for several different groups of keys These are shown below Function Group lt F1 gt lt F2 gt lt F3 gt lt 1 gt lt 2 gt lt 3 gt lt Left Shift gt lt Right Shift gt Ctrl lt gt Selection Group 5 lt P gt lt L gt lt N gt Misc Keys lt Enter gt lt Break gt When any key in the Function Group is pressed it is recorded in RAM and will be used by the Control routine in directing the action of the boot If more than one of these keys are pressed during the keyboard scan the last one detected will be the one thatis used The Function group keys are currently defined as Will cause hard disk boot Will cause floppy disk boot Wil force Model mode Reserved for future use Boot from RS 232 port Reserved for future use Reserved for future use lt F1 gt or lt 1 gt lt F2 gt or lt 2 gt lt F3 gt or lt 3 gt lt Left Shift gt lt Right Shift gt Special keys commands to the Control routine which direct handling of the Model ROM image Each key is de tected individually lt P gt When loading the Model 111 ROM image the user will be prompted when the disks can be switched or when ROM BASIC can be entered by pressing lt Break gt Instructs the Contro
195. se in the factory application or when more than one board is being loaded it may be advantageous or even nec essary to ignore the transmitted responses of the object board s and to manually pace the test byte sync byte and command file phases of the transmission process using the video display for handshaking System Programmers Information The Model Boot ROM uses two areas of RAM while it is run ning These are 4000H to 40FFH and 4300H to 43FFH For 512 byte boot sectors the second area is 4300H to 44FFH the Model ROM Image is loaded additional areas used See the technical reference manual for the system you are ing for a list of these areas Operating systems that want to support software restart by re executing the contents of the boot ROM can accomplish this in one of two ways If the operating system relies on the Model ROM Image then jump to location O as you have in the past If the operating system is a Model 4 mode package a simple way is to code the following instructions in your assembly and load them before you want to reset Absolute Location Instruction 0000 DI 0001 LD 0003 OUT 9CH A These instructions cause the boot ROM to become address able After executing the OUT instruction the next instruction executed will be one in the boot ROM These instructions also exist in the Model ROM image at location 0 The boot ROM has been written so that the first instructio
196. sette port The Model 4P sends data to onboard sound circuit DO Cassette output level sound data output D1 Reserved 02 07 Undefined MODIN CASSIN Port Address FC FF Access READ ONLY Description Configuration Status DO 0 01 CASSMOTORON STATUS D2 MODSEL STATUS D3 ENALTSET STATUS D4 ENEXTIO STATUS D5 NOT USED D6 FAST STATUS D7 0 Name LPOUT Port Address F8 FB Access WRITE ONLY Description Output data to line printer 00 07 ASCII BYTE TO BE PRINTED Name LPIN Port Address F8 FB Access READ ONLY Description input line printer status 50 03 RESERVED 04 FAULT 1 TRUE 0 FALSE 05 UNIT SELECT 1 TRUE 0 FALSE 06 OUTPAPER 1 0 FALSE 07 BUSY 1 0 FALSE DRVSEL Port Address F4 F7 Access WRITE ONLY Description Output FDC Configuration Note Output to this port will ALWAYS cause a 1 2 mscc Microsecond wait to the Z80 DO DRIVE SELECT 0 01 DRIVE SELECT 1 02 RESERVED 03 RESERVED 04 SDSEL 0 SIDE 0 1 8105 1 05 PRECOMPEN 0 No write precompensation 1 Write Precompensation enabled D6 WSGEN 0 No wait state generated 1 wait state generated Note This wait state is to sync 280 with FDC chip during operation D7 DDEN 108 0 Single Density enabled FM 1 Double Density enabled MFM DISKOUT Port Address FO Access
197. side for reassembly 3 3 FRONT BEZEL 1 Thefrontbezel can be removed from the unit after the case and rear mounting plate have been removed as noted in Paragraphs 3 1 and 3 2 2 Pullthe brightness and contrast knobs off the pots from the front 3 The rear mounting plate removal allows access to the six bezel mounting screws Four screws attach to the outside flanges of the metal chassis The other two screws are lo cated to the right of the metal partition separating the Disk Drives from the CRT section of the unit Access to these two screws is with a long shank 1 4 nutdriver above and below the fan assembly 4 Oncethese six screws are removed remove the bezel and set it aside for reassembly Exercise care in handling to prevent scratching or marring the surface 3 4 TOP COVER POWER SUPPLY 1 The Power Supply for the Model 4P is located on the un derside of the top cover Remove the case and rear ter minal plate as noted in Paragraphs 3 1 and 3 2 SCREWS DISK DRIVE ASSEMBLY REAR VIEW Figure 3 1 Bezel Mounting Screws 2 cover is attached to the metal chassis with six screws Remove these screws and then flip the cover to the right A convenient arrangement for storing the cover power supply while working on other modules is to reattach the cover power supply to the chassis with two screws allow ing the assembly to rest above the disk drive assembly 3 The power supply is attached to the top cove
198. style disk This is important since TRSDOS 1 x disks number sectors starting with 1 and LDOS style disks number sectors starting with 0 Once the disk type has been determined an extra test is made if the disk is a LDOS style disk This test reads the Granule Al location Table GAT to determine if the disk is single sided or double sided The directory is then read one record at time and compare is made against the pattern MODEL for the filename and I for the extension The 92 means that any character will match this position If the user pressed one of the selection keys A G during the keyboard scan then that character is substituted in place of the character For example if you pressed D then the search would be for the file MODELD with the extension The searching algorithm searches until finds the entry or it reaches the end of the directory Once the entry has been found the extent information for that file is copied into a control block for later use File Loader The file loader is actually two modules the actual loader and a set of routines to fetch bytes from the file on disk The loader is invoked via a RST 28H The byte fetcher is called by the loader using RST 20H Since restart vectors can be re directed the same loader is used by the RS 232 boot The difference is that the RST 20H is redirected to point to the RS 232 data re ceiving routine The loader reads standard loader records
199. t up of for the 5 volt secondary 54 4 13 5 gives us 5 0 volts the 5 05V output when it is installed in computer 67 5V 5 13 5 5 volt Output 168 VDC CR5 4 5VDC 54t 4t 10 Figure 5 46 Overvoltage Crowbar 55 10 Overvoltage Crowbar FT Q7 base drive Some of the circuits supplied by the 5 volt output are quite sensitive to voltages in excess of 7 volts Since some circuits require both 5 and 12 volts a failure in those circuits could apply 12 volts to the 5 volt bus and thus damage some of the 5 volt circuits To prevent the 5 volt bus from exceeding safe level an SCR Q6 is used to crowbar or short circuit Figure 5 47 Power Chain the 5 05 volt output to the secondary ground bus This short circuit triggers the current limiting circuit and the supply shuts down until it tries to restart Referring to Figure 5 46 VR2 sets the turn on point of the SCR and R17 develops the gate signal when VR2 s Zener break down voltage of 5 6 volts is exceeded 6 and 817 provide cur rent limiting for VR2 and filter the gate signal so Q6 won t respond to transient signals 156 Control Chain Imagine the load end of the feedback path disconnected from the 5 05 volt output terminal and unfolded so that the load sense network is now at the input The secondary rectifier CR5 and filter 10 12 L1 remain as the output The circuit as it now appears redrawn in simplified form in Fi
200. ted by U142 and 83 is filtered by R14 47 ohm resistor and C227 100 pf Cap and output to video monitor and HSYNC are buffered by 1 2 of 74LS86 U143 and are also output to video monitor Refer to Video Circuit Timing Figure 5 30 and Inverse Video Timing Figure 5 19 for timing relationships of Video Circuit 5 2 9 Keyboard The keyboard interface of the Model 4P consists of open col lector drivers which drive an 8 by 8 key matrix keyboard and an inverting buffer which buffers the key or keys pressed on the data bus The open collector drivers U57 and U77 7416 are driven by address lines 0 7 which drive the column lines of the keyboard matrix The ROW lines of the keyboard are pulled up by a 1 5 kohm resistor pack RP2 The ROW lines are ered and inverted onto the data bus by U78 74LS240 which is enabled when is a logic low is a memory mapped decode of addresses 3800 3BFF in Model Mode and F400 F7FF in Model 4 4P mode Refer to the Memory Map under Address Decode for more information During real time operation the CPU will scan the keyboard periodically to check if any keys are pressed If no key is pressed the resistor pack RP2 keeps the inputs of U78 at a logic high U78 inverts the data to a logic low and buffers it to the data bus which is read by the CPU If a key is pressed when the CPU scans the correct column line the key pressed will pull the corresponding row to a log
201. tes which scan line row is being displayed The CRTC also provides hard ware scrolling by writing to the internal Memory Start Address Register by OUTing to Port 88H The internal cursor control of the 68045 is not used in the Model 4P video circuit Since the 80 by 24 screen requires 1 920 screen memory lo cations a 2K by 8 static RAM U82 is used for the video RAM Addressing to the video RAM 082 is provided by the 68045 when refreshing the screen and by the CPU when updating of the data is performed These two sets of address lines are mul tiplexed by three 74LS157s U83 U84 and U104 The multi plexers are switched by CRTCLK which allows the CRTC to address the video RAM during the high state of CRTCLK and the CPU access during the low state A10 from the CPU is con trolled by which allows two display pages in the 64 by 16 format When updates to the video RAM are performed by the CPU the CPU is held in a WAIT state until the CRTC is not addressing the video RAM This operation allows reads and writes to video RAM without causing hashing on the screen The circuit that performs this function is a 74LS244 buffer U103 an 8 bit transparent latch 74LS373 U102 and a Delay line circuit shared with Dynamic RAM timing circuit consisting of a 741574 U95 74LS32 U94 741504 074 741500 096 741502 075 and Delay Line 097 During CPU Read Access to the Video RAM the address is decoded by the PAL U109 and asserts
202. the RD cycle VIDEO is asserted low which asserts VWAIT low to the CPU WR is high at this time which is NANDed with VIDEO and synced with CRTCLK to create VRAMDIS that disables the video RAM output On the rising edge of XADR7 WR is latched into U98 1 2 of 74LS74 which releases VWAIT and starts cycle through the Delay Line After 30ns DLYVWR De layed video write is asserted low which also asserts VBUFEN Video Buffer Enable low VBUFEN enabled data from the Data bus to the video RAM Approximately 120ns later DLYVWR is negated high which writes the data to the video RAM and negates VBUFEN turning off buffer The CPU then completes WR cycle to the video RAM Refer to Video RAM CPU Access Timing Figure 5 12 for timing of above RD or WR cycles During screen refresh CRTCLK is high allowing the to address Video RAM The data out of the video RAM is latched by LOAD into Gate Array 4 3 0102 INVERSE determines if character should be alpha numeric only IN VERSE high or unchanged INVERSE low A9 is de coded with ENALTSET Enable Alternate Set and 7 which controls the alternate set in the character generator ROM See ENALTSET Control Table below ENALTSET xHMAA IG SAN FU 2 1 20487880 sf s I x gt i met in LYAVX iene
203. to generate an NMI interrupt If data bit 6 is reset interrupts on Motor Time Out are disabled An IN instruction from port E4H enables the CPU to determine the source of the non maskable interrupt Data bit 7 indicates the status of FDC interrupt request INTRQ 0 true 1 false Data bit 6 indicates the status of Motor Time Out 0 true 1 false Data bit 5 indicates the status of the Reset signal 0 true 1 false The control signal RDNMISTATUS gates this status onto the CPU data bus when active logic low Drive Select Latch and Motor ON Logic Selecting a drive prior to disk operation is accomplished by doing an OUT instruction to with the proper bit set The following table describes the bit allocation of the Drive Select Latch Data Bit Function 00 Selects Drive 0 when 01 Selects Drive 1 when D2 Selects Drive 2 when 58 D3 Selects Drive 3 when set D4 Selects Side 0 when reset Selects Side 1 when set D5 Write precompensation enabled when set disabled when reset D6 Generates WAIT if set D7 Selects MFM mode if set Selects FM mode if reset 61 one of these bits should be set per output flip flop 032 741174 latches the drive select bits side select and FM MFM bits on the rising edge of the control signal DRVSEL dual D flip flop 098 is used to latch the En able and Write precompensation enable bits on the rising edge of DRVSEL The
204. torage are provided in side the removable cover base All connections to peripheral equipment are made at the rear of the Model 4P and optionat feature connections are made by removing a rear cover plate Proper care and handling must be observed to prevent damage to the computer The Model is 100 compatible with all Model and Model 4 disk software System capability for Model Il compatibility in Cludes Z80A CPU 2 MHz operation programmable RAM to emulate ROM for BASIC operating system memory mapped keyboard memory mapped video with 64 character by 16 line display and full 48K Random Access Memory RAM Model 4 compatibility includes Z80A CPU 4 MHz operation memory mapped keyboard in upper memory memory mapped video in upper memory with 80 character by 24 line display standard 64K RAM expandable to 128K RAM Other standard features of the Model which were options on the Model and Model 4are built in FDC Circuit with two 184K Floppy Disk Drives and an RS 232 C Serial Communications Interface Circuit 1 2 OPTIONAL FEATURES Optional features available on the Model 4P include 640 by 240 pixel High Resolution graphics Board Direct connect auto dial auto answer 300 bps Modem Board The Model 4P does not support cassette operation or external Floppy Disk Drive COVER POWER SUPPLY REAR CONTROL MOUNTING MODULE PLATE Figure 1 1 PAN MAIN LOGIC PCB DRIVE ASSEMBLY COV R BASE KEYBOA
205. transceiver and allows and INPUT in struction to read Bus data The address line data line and all control lines except RESET are enabled only when the ENEXIO bit in port EC is set to one To enable O interrupts the ENIOBUSINT bit in the PORT EO output port must be a one However even if it is disabled from generating interrupts the status of the IOBUSINT line can still read on the appropriate bit of CPU IOPORT input port See Model 4P Port Bit assignments for port OFF OEC and OEO A UA diss 100 99112 T EPTN Figure 5 16 Graphic Board Video Timing 58 The Model CPU board is fully protected from foreign I O de vices in that all the I O Bus signals are buffered and can be dis abled under software control To attach and use and device on the I O Bus certain requirements both hardware and soft ware must be met For input port device use you must enable external O devices by writing to port OECH with bit 4 on in the user software This will enable the data bus address lines and control signals to the VO Bus edge connector When the input device is selected the hardware should acknowledge by asserting EXTIOSEL low This switches the data bus transceiver and allows the CPU to read the contents of the Bus data lines See Figure 5 17 for the timing EXTIOSEL be generated by NANDing IN and the I O port add
206. ts 9 Operating Temperature ura 9 Dimensions 15 GCA iple os Sf 9 Disassembly Assembly c Internal Rear Mounting Plate 2 vi cer la Se Top Coven Power Supply cs BY Cathode Ray Tube CRT Sweep Board sees ee e km VERE ER eed Keyboard Assembly ieri pes an EIS Cede ed a ad ey p Disk Drive Assembly na Control Module EE REX SEO Der e Maintenance Troubleshooting general suggestions reference to section below for specific troubleshooting 17 AP Theoty of Operation uu essa ex Ex i b ELE ERE CPU Theory of Operation Introduction het ar JR Q shaq Ie E CPU deco rir E OX Lt SystemTiming 5l Rie g Ren SAE AddressDecode RE Sieh ods bald ES Keyboard ae AA s gl Qasa uio a dre dore RON RealTime Clock be ARES L
207. ts The video information is filtered by 34 R45 47 ohm resistor and C241 100 pf Cap and out put to video monitor VSYNC and HSYNC are buffered by 1 2 of 741586 0143 and are also output to video monitor Refer to Video Circuit Timing Figure 5 13 Video Blanking Timing Figure 5 14 and Inverse Video Timing Figure 5 1 for timing relationships of Video Circuit 5 1 9 Keyboard The keyboard interface of the Model 4P consists of open col lector drivers which drive an 8 by 8 key matrix keyboard and an inverting buffer which buffers the key or keys pressed on the data bus The open collector drivers U56 and U57 7416 are driven by address lines which drive the column lines of the keyboard matrix The ROW lines of the keyboard are pulled up by a 1 5 kohm resistor pack RP2 The ROW lines are buff ered and inverted onto the data bus by U58 74LS240 which is enabled when KEYBD is a logic low is a memory mapped decode of addresses 3800 3BFF in Model Mode and F400 F7FF in Model 4 4P mode Refer to the Memory Map under Address Decode for more information During real time operation the CPU will scan the keyboard periodically to check if any keys are pressed If no key is pressed the resistor pack RP2 keeps the inputs of U58 at a logic high U58 inverts the data to a logic low and buffers it to the data bus which is read by the CPU If a key is pressed when the CPU scans the correct column line the key pressed
208. wait state U99 is a 12 bit binary counter which serves as a watchdog timer to insure that a wait condition will not persist long enough to destroy dynamic RAM contents The counter is clocked by a 1 MHz clock and is enabled to count when its reset pin is low U99 pin 11 A logic high on U99 pin 11 resets the counter outputs U99 pin 15 is a divide by 1024 output and is used to generate the signal WAITIMOUT This watchdog timer logic will limit the duration of a wait to 1024psec even if the FDC chip should fail to generate or an INTRQ If an OUT to Drive Select Latch is initiated with D6 reset logic low a WAIT is still generated The 12 bit binary counter will count to 2 which will output CLRWAIT and clear the WAIT state This allows the WAIT to occur only during the OUT instruction to prevent violating any Dynamic RAM parameters NOTE This automatic WAIT will cause a 1 2 wait each time an out to Drive Select Latch is performed Clock Generation Logic A 4 MHz crystal oscillator and a 4 bit binary counter are used to generate the clock signals required by the FDC board The 4 MHz oscillator is implemented with two inverters 1 3 of U39 and a quartz crystal Y2 The output of the oscillator is inverted and buffered by 1 6 of U39 to generate TTL level square wave signal U37 is 4 bit binary counter which is divided into di vide by 2 and a divide by 8 section The divide by 2 section is used to generate the 2 M
209. will pull the corresponding row to a logic low U58 inverts the signal to a logic high which is read by the CPU 53 5 1 10 Reai Time Clock The Real Time Clock circuit in the Model 4P provides a 30 Hz in the 2 MHz CPU mode or 60 Hz in the 4 MHz CPU mode interrupt to the CPU By counting the number of interrupts that have occurred the CPU can keep track of the time The 60 Hz vertical sync signal VSYNC from the video circuitry is used for the Real Time Clock s reference In the 2 MHz mode FAST is a logic low which sets the Preset input pin 4 U22 741574 to a logic high This allows the 60 Hz VSYNC to be divided by 2 to 30 Hz The output of 1 2 of U22 is ORed with the original 60 Hz and then clocks another 741874 1 2 of U22 If the real time clock is enabled ENRTC at a logic high the interrupt is latched and pulls the INT line low to the CPU When the CPU recognizes the interrupt the pulse is counted and the latch re set by pulling RTCIN low In the 4 MHz mode FAST is a logic high which keeps the first half of U22 in a preset state the Q output at a logic low The 60 Hz is used to clock the interrupts NOTE If interrupts are disabled the accuracy of the real time clock will suffer 5 1 11 Line Printer Port The Line Printer Port Interface consists of a pulse generator an eight bit latch and a status line buffer The status of the line printer is read by the CPU by enabling buffer U3 741 5244 This buffer
210. wnward as shown in Figure 5 53 By turning VR201 clock wise and counter clockwise the initial points of scrolling can be confirmed Consequently set VR201 at the center between the confirmed points Figure 5 53 V HOLD PULL IN RANGE I LJ 5 54 Vertical Size Adjustment Figure 5 55 Generate full white screen on the CRT and adjust the video s vertical size to be 4 5 VIDEO RASTER VERTICAL HEIGHT Figure 5 55 Horizontal Size Adjustment Figure 5 56 Generate full white screen on the CRT Adjust video s hori zontal size with L302 to be 6 0 VIDEO RASTER HORIZONTAL WIDTH Figure 5 56 Focus Adjustment Figure 5 57 Display full screen of the character and adjust VR303 so that allthe characters are the same size and shape and in sharp focus While adjusting observe both peripheral and central areas of the display Figure 5 57 172 Raster Tilt Adjustment Figures 5 58 5 59 Form series of characters along the horizontal center line as shown in Figure 5 58 Adjust the center line to make 1 2 by turning the deflection yoke left and right 11 5 58 Note Loosen the cramp screw the deflection yoke for tilt ad justment as shown in Figure 5 59 DEFLECTION YOKE CLAMP VIDEO CENTERING MAGNETS
211. ys to 1 0 in approx 8 seconds V1 and V3 must be within specified regulation when this surge decays to 4 0 A Output Ripple Voltage V1 5 05 50 V2 12 VDO 150 V3 12 150mV V4 12VDC 150 NOTE Ripple is the composite 100 120 Hz ripple due to the line plus the high frequency ripple due to the power oscillator Common mode noise which may be observed due to oscilloscope connections should be ignored 147 Output Voltage Regulation After initially setting V1 output voltage tolerances under all conditions of rated line load and temperature should re main within the following limits Vi 5 05 VDC 3 V2 12VDC see V3 12 0 5 V4 12VDC 25 8 3 The initial value of V2 must change by more than 100mV under the following load conditions of V3 step increase in output current from 0 4 A initial condition to 2 4 A decaying within 60 msec to 2 1 step decrease in output current from 2 1 A initial condition to 0 4 A V2 output voltage may vary 5 under all other conditions of rated line load and tem perature as defined in the specification b Over Current Protection Power supply will shut down before total power exceeds the point where damage would result No damage will re sult when any output is short circuited continuously with 100 milliohms or less Over Volt

Model 4P Service Manual (1984)(Tandy)

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