MAX 10 FPGA (10M0S, 144-EQFP) Evaluaion Kit User Guide
Contents
1. e Anangled arrow instructs youto press the Enter a b c and so on such as the steps listed in a procedure a Bullets indicate a list of tems when the sequence of the ems is not Important 2 The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation A A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or your work A A warning calls attention to a condition or possible situation that can cause you WARNING injury The envelope links to the Email Subscription Management Center page of the Altera by website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Additional Information Info 3 Compliance and Conformity Statements Compliance and Conformity Statements CE EMI Conformity Caution This evaluation kit is delivered conforming to relevant standards mandated by Directive 2004 108 EC Because of the nature of programmable logic devices it is possible for the user to modify the kit in such a way as to generate electromagnetic interference EMI that exceeds the limits established for this equipment Any EMI2. Evaluation Kit User Guide Chapter 1 Overview Supported Items Not Included with the Kit September 2015 Altera Corporation N DEAN 2 Getting Started Powering the Kit You can apply power the MAX 10 FPGA Evaluation Kit by plugging in the USB cable J1 to your PC or wall jack When powered correctly a pre programmed design blinks LEDs DI through D5 ON half a second then OFF half a second Installing the USB Blaster Driver You can configure the evaluation kit by programming on chip flash memory using a USB Blaster USB Blaster II or Ethernet Blaster download cable However for the host computer and board to communicate you must install the appropriate USB Blaster USB Blaster IL or Ethernet Blaster driver on the host computer Installation instructions for the Blaster driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions lt You can download the Blaster drivers from the Download Cables page Handling the Kit When handling the board it is important to observe the following static discharge precaution Without proper anti static handling the board can be damaged Therefore use anti static handling precautions when touching the board CAUTION The MAX 10 Evaluation Kit must be stored between 40 C and 100 C The recommen
3. caused as the result of modifications to the delivered material is the responsibility of the user September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide Info 4 Additional Information Compliance and Conformity Statements MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide
4. Programmer 2 Click Auto Detect to display the devices in the JTAG chain September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 3 4 Chapter 3 Board Components Configuration Click Add File and select the path to the desired sof Turn on the Program Configure option for the added file Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 The Quartus II Convert Programming File CPF GUI can be used to generate a pof file that can use for internal configuration You can directly program the MAX 10 device s flash which included Configuration Flash Memory CFM and User Flash Memory UFM by using a download cable with the Quartus II software programmer Selecting Internal Configuration Scheme For all MAX 10 devices except 10M02 device there are total of 5 different modes can be selected when using Internal Configuration The internal configuration scheme needs to be selected before design compilation To select the configuration mode follow these steps So ME 5 gt dq de Open the Quartus II software and load a project using MAX 10 device family On the Assignments menu click Settings The Settings dialog box appears In the Category list select Device The Device page appears Click Device and Pin Options In the Device and Pin Options dialog box click the Configuration tab In the Configuration Scheme list se
5. register push button Toggling this button resets all registers in the FPGA Polentonmster You must purchase and install this device to provide analog inputs signals to the MAX 10 ADC IP block analog input channel 8 You can purchase Arduino Uno R3 compatible Shields i e J2 J3 J4 J5 Arduino UNO R3 connectors daughtercards to connect to the Arduino headers installed on the board Connects an Altera USB Blaster USB Blaster Il or Ethernet Blaster to J10 JTAG header program or configure the FPGA This through hole area is not connected to the FPGA You can use this Prototype Area Wi area to connect or solder additional components Power Supply USB connector Connects a USB cable to a power source Jumper for analog input channel 7 MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Chapter 3 Board Components 3 3 Featured Device MAX 10 FPGA Featured Device MAX 10 FPGA The evaluation kit features the MAX 10 FPGA 10M08SAE144C38G device U2 in a 144 pin Plastic Enhanced Quad Flat Pack EQFP package e For more detailed information about the MAX 10 FPGA device family refer to the MAX 10 FPGA Device Overview Table 3 2 MAX 10 FPGA Component Reference and Manufacturing Information Board Manufacturing Manufacturer 1OMO8SAE144C8G or ES variant Plastic ta Quad Flat Pack EQFP 144 pins 20 mm x 20mm Altera Corporation 10M08SAE144C8GES www altera c
6. 8 Connector Table 3 1 describes the components and lists their corresponding board references September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 3 2 Chapter 3 Board Components Board Overview Table 3 1 MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit Components Board Reference BEEN Description Featured Device 10MO8SAE144C8G or ES variant Plastic Enhanced Quad Flat Pack EQFP 144 pins 22 mm x 22 mm U2 FPGA For package details refer to the Altera Device Package Information page Configuration Status and Setup Elements Jumper for analog input Default connection is to GND Change jumper to pins 1 and 2 to switch channel 8 analog source to Arduino header Default connection is to potentiometer customer option to purchase and install Change jumper to pins 1 and 2 to switch analog source to Arduino header SW3 User defined DIP switch 6 position switch SW3 1 through SW3 5 are user defined SW3 6 is predefined for dual image configuration at A LED red These LEDs cycle off and on when the kit is powered on D6 Power LED green Illuminates when USB power is present E reconfiguration push Toggling this button causes the FPGA to reconfigure from on die button Configuration Flash Memory CFM 50 MHz oscillator 50 MHz crystal oscillator for general purpose logic General User Input and Output JA v it User defined LEDS red User defined LEDs Swi FPGA
7. AX 10 FPGA Device Pin Number Ce o ee oOo 3 was sv 4 jea 39 o User Defined LEDs The development board includes five user defined LEDs Board references D1 through D5 are user LEDs that allow status and debugging signals to be driven to the LEDs from the designs loaded into the MAX 10 FPGA device The LEDs illuminate when a logic 0 is driven and turns off when a logic 1 is driven There is no board specific function for these LEDs Table 3 5 lists the user defined LED schematic signal names and their corresponding MAX 10 FPGA pin numbers Table 3 5 User Defined LED Schematic Signal Names and Functions Board Reference Schematic Signal Name 1 0 Standard MAX 10 FPGA Device Pin Number Power Supply The development board is powered up through a USB cable The green LED illuminates when the board is powered up Power Measurement In order to measure the actual power of the FPGA there are test pads on the board to be used as probe points for multi meter probes The user can measure the current and using the equation P R x I Power Resistance x Current Squared calculate the power dissipation September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 3 10 Chapter 3 Board Components Power Supply Test pads TP2 and TP3 are used to measure the current consumed by the FPGA core Test pads TP4 and TP5 are used to measure the current consumed by all of the FP
8. GA s I O banks All the other test pads are used to verify the voltage levels of various nodes on the board Table 3 6 Power Measurement Details Power calculation for FPGA Vcc core power consumption TP TP3 FPGA core p SN mWatts current Resistor R1 0 1 ohms Current measured by user s multi meter Power calculation for FPGA Vcc io power consumption TPA TP5 FPGA 1 0 p p mWatts current Resistor R4 0 1 ohms Current measured by user s multi meter TP Board input verify the USB input voltage 5 0 volts voltage Analog TP6 voltage Verify the proper voltage required by the FPGA Vcca inputs 3 3 Volts Analog GND Verity the proper voltage required by the FPGA ADC IP block GND Inputs TP8 Digital GND Verify the proper voltage required by the FPGA digital GND inputs Digital GND Verify the proper voltage required by the FPGA digital GND inputs 0 volts Digital GND Verify the proper voltage reguired by the FPGA digital GND inputs 0 volts Power Distribution System Figure 3 4 shows the power distribution system on the development board Figure 3 4 Power Distribution System EP5388QI Temperature Sense The ADCs provide the devices with built in capability for on die temperature monitoring and external analog signal conversion Temperature sensing mode monitors external temperature data input with a sampling rate of up to 50 kilosamples per second In dual ADC devices only the first ADC block co
9. II Programmer to program a pof file into MAX 10 devices 1 For Device 2 the Programmer will just erase and configure CFM and UFM sector in the internal flash memory but the ICB setting will be preserved However before starting the programming the makes sure the ICB setting in the device and the ICB setting in the pof file are the same If both ICB settings are different the Programmer still erases and programs the full internal memory including the ICB setting even though only CFM and UFM are selected in the Programmer 2 For Device 3 the Programmer will erase and program full internal memory which includes the ICB setting CFM and UFM Before enabling real time ISP for internal flash memory programming you need to ensure the MAX 10 FPGA is in user mode otherwise the programming process will fail Clock Circuitry General Purpose Clock One general purpose clock is provided to the FPGA global clock inputs for general FPGA design The clock source is from the following component m A50 MHz oscillator to the clock input CLKOp of bank 2 MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Chapter 3 Board Components 3 7 Arduino Connectors Figure 3 3 shows the general purpose clock going in to the evaluation kit Figure 3 3 MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit General Purpose Clock ICS8304 CLKBUF 50 MHz Arduino Connectors Arduino connectors J3 J4 and J5 co
10. MAX 10 FPGA 10MO8S 144 EQFP Evaluation Kit User Guide JNO S RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG 01158 1 2 aat Feedback Subscribe 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as I agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide N DTE SYN Contents Chapter 1 Overview B ard Component DIOCKS sire sas SK sked seine ssk KETI RR ded EAEAN EREE 1 1 Supported Items Not Included with t
11. Signal Names and Functions Part 2 of 2 Board MAX 10 FPGA Arduino analog channel input through the op amp ARDUINO A4 filter circuit to the FPGA ADC IP input channel ADC1IN5 Arduino analog channel input through the op amp J4 6 ARDUINO A5 filter circuit to the FPGA ADC IP input channel ADC1IN6 Arduino analog channel input through the op amp J4 7 ARDUINO A6 filter circuit to the FPGA ADC IP input channel ADC1IN7 Arduino analog channel input through the op amp J4 8 ARDUINO A7 filter circuit to the FPGA ADC IP input channel ADC1IN8 st jm amp Arduino digital VD inputto FBR General User Input Output This section describes the user I O interface to the FPGA m User defined DIP switch m User defined LEDs User Defined DIP Switch Board reference SW3 is a 6 pin DIP switch Switches 1 through 5 are user defined and provide additional FPGA input control When the switch is in the OPEN or OFF position a logic 1 is selected When the switch is in the CLOSED or ON position a logic 0 is selected There is no board specific function for these switches MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Chapter 3 Board Components 3 9 Power Supply Table 3 4 lists the user defined DIP switch schematic signal names and their corresponding MAX 10 FPGA pin numbers Table 3 4 User Defined DIP Switch Schematic Signal Names and Functions soarg _ kummasti Schematic Signal Name 1 0 Standard M
12. ate Memory Map File Auto generate output_file map In the map file not only will show the address of the CFM and UFM but also will contain the information of the ICB setting that user set through the Option Boot Info dialog box You can add an SRAM Object File sof through Input files to convert list The maximum sof page is two After set all the desirable settings click Generate to generate related programming file September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 3 6 Chapter 3 Board Components Clock Circuitry Programming Internal Flash Memory After generating the pof file Quartus II Programmer can be used to program the internal flash memory through JTAG connection The following shows an example of the Quartus II Programmer Figure 3 2 Quartus II Programmer File Edit View Processing Tools Window Help Y t Hardware Setup Hardware Mode rac Progress N Enable real time ISP to allow background programming for MAX II and MAX V devices Device 2 i ER Mataicschauzb bringupizbH no cmp no eram sof 10MOSDAFABACBGES 000C4737 000C4737 idatalcschal zb bringup abc por JAFABAE JEDF dA W Auta Detect CFH Device 3 UPM idatafeschai zb bringup abc pol 10MOSDAFABA4ES O3EDF407 00000000 UFM LOMOSDAFSE4E5 10M0SDAF484E5 10M08DAF484ES O There are 2 scenarios when using the Ouartus
13. converter embedded block to measure incoming analog signals Interface to external functions or devices via Arduino UNO R3 connectors or through hole vias Reuse the kit s PCB board and schematic as a model for your design Board Component Blocks This evaluation kit features the following major component blocks For a detailed description of the board components see Board Components on page 3 1 Altera MAX 10 FPGA 1OMO8SAE144C8G or ES variant m 8 000 logic elements LE m 378 kilobits Kb M9K memory m 32 172 KB user flash memory m Oneanalog to digital ADC converter 1 million samples per second MSPS 12 bit FPGA configuration circuitry m JTAG header for external USB Blaster USB Blaster IT or Ethernet Blaster download cable m Flash storage for two configuration images factory and user m Dual image self configuration via Programmer Object File pof m Temporary engineering debug of FPGA design via SRAM Object File sof On Board clocking circuitry m 50 MHz oscillator connected to FPGA global clock input General user I O m 8analog input I O 14 Arduino I O 40 general purpose I O m bred user defined LEDs m One green LED to show power from USB cable September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 1 2 Chapter 1 Overview Board Component Blocks m Push button and DIP switches m One reconfiguration push button SW2 m One device wide reset of all reg
14. d Jumper Settings September 2015 Altera Corporation 7E 3 Board Components This chapter introduces all the important components on the evaluation kit Figure 3 1 illustrates major component locations and Table 3 1 provides a brief description of all features of the board Board Overview This section provides an overview of the evaluation kit including an annotated board image and component descriptions Figure 3 1 Overview of the MAX 10 FPGA Evaluation Kit Features Arduino 2x20 GPIO Arduino Connector Through Hole Vias J9 Connector LEDs KK cN N N N N NCE N KSK KTT W 3 lines AM PeletekelleBotelekee oko ooo efe efe ke i R57 6 SMD NDT 108 NC NCIGNDILEIIQGNDIO7 I06 105101 99 93 92 89 88 GND 106 LL ALLL PK e gt R60 3 4 ri ar R61 SDS i C93 7 ba 3 R2 98g D6 t2 A a i ole USB p E e NE DD Lada Nw n aa SNES e 5 8 rea Connector J m Es A TUNE AS Se J1 LS y Da ee eee 1983 i e MAX 10 ERIL 32 O TTY 3 FPGA U2 T8 neun ATER mime 56 De IUE Man we Jumper rm ir wi JE ndi J6 3 Zh CHEESE ES E 2 SW1 oS ELULOO TTE O 72 NE i MOKKA LTI HT EY Ges R34 RIS www axelsys com Os 09 R36 3 R32 R37 SW3 AI OR W 90 0o 0 9j X M RBI R30 RS OR R39 OIMAX R 10 rat SiKit Boord REV A J PJN 1100 0991402 A1 JTAG KI SINI 52157 58 GND 4B a J10 Jumper s 7 Arduino 2x20 GPIO Arduino Connector Through Hole Vias J
15. ded operating temperature is between 0 C and 85 C September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 2 2 Chapter 2 Getting Started Factory Default Switch and Jumper Settings Factory Default Switch and Jumper Settings Figure 2 1 Switch Locations and Default Settings Board Top O O O O O O O O O O O O OO O O O o o000O00 00000 00000000009 MAX 10 FPGA Table 2 1 Default SW3 DIP Switch Settings Part 1 of 2 Default Position MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Chapter 2 Getting Started 2 3 Factory Default Switch and Jumper Settings Table 2 1 Default SW3 DIP Switch Settings Part 2 of 2 Default Position BOOT SEL Use this switch to choose CFMO CFM1 or CFM2 image as the first image in a dual image configuration If BOOT SEL is set to low the first boot image is CFMO image If set to high the first boot image is the CFM1 or CFM2 image By default the FPGA setting for this pin is tri stated Table 2 2 Default Jumper Settings ae analog input channel 8 Default connection is to Pins 2 and 3 Jumper for analog input channel 7 Default connection Is to Pins 2 and 3 potentiometer September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 2 4 MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide Chapter 2 Getting Started Factory Default Switch an
16. he Kit 2 eee eee ee 1 3 Chapter 2 Getting Started POS Wie KE Kasa EVI TI sd nad ete redd A RR TET Re Sud UE dag gd 2 1 Installing the USB Bl ster Driver ss m t s TIES eights dat RR KAN hada tee RR dane e dox 2 1 RIN Me dd Fr PH ay 134 steps cues 1 ht se 4a ene fr RR cam aes 2 1 Factory Default Switch and Jumper Settings lt a ss ss pbs Ep P oe cet pir eR ch 9 358 ee es 2 2 Chapter 3 Board Components DOS C Very lew 2920 688 vt de SUT RR USES MN bam EAM PU ey oe OR eS ISSN ee ETS ee ee 3 1 Featured Device MAX 10 FPGA 0 RR RR RR RR hh 3 3 COME UT DIOR TUER 3 3 FPGA Programming over External USB Blaster 0 0 0 cece eee eee 3 3 Configuring the FPGA Using the Quartus II Programmer 0 00 00 knee 3 3 Selecting Internal Configuration Scheme avaa vaa s s an eer deren KANA BRA CR wana EKKE SA 34 Generating pot File with IC B Settings x 6aesor aki ues poet op Pete tys rer rr rr res rss cem 3 4 Programming Internal Flash Memory oloon nn 3 6 Sidera ys on K ho ee ee tad Get SESE NONI san peneseeeeatens ees 004008 MO 6 3 6 Genera DOrpose ClOCK prespati riie ough ane food ITI utan oo quini Dd uasa hal dh Ena RR erent 3 6 POI ONMCCIONS oo 45 eic r ou as oe st eheu da aw aa t dadas dude lt Gane satan ates 3 7 General User loput OUUTE serris ses teeter fee NONIIN enya tee dira ni eee ER dee 3 8 serene DIE SUIN seese ccs sane bosses nana soe r RR d ATA ERES AU een Vadis 3 8 User Del
17. ined LEDS 4 este a entre as sarki Ante ere wis Pe Bl oa tn de ae Se hea Ge wee 3 9 POWEr SUPP P AA A K E H IA KE STINA ST AAKE EN TEET PT Joss 3 9 Power Measurement eiri sms esse hr 8 dO E e Ro he op nee haa oh RSA RN RAR 3 9 Power DistibUtlon Syste 511050030 53 coe adque adque sd ee EGR SES RANA ines UA 3 10 TEM Petras else 46 nate kumea A sset wae Lens pan Va epar org Leone reci ad pP ae MAKS Rd dr 3 10 Additional Information Document Revision ELISEOEY s dise ssis s0 535501080 8145 00 sees EE Osk b rd cis otis eee Info 1 EO O OMA etd saamassa at segs ese bee PEI EE TN E PAE NOI s0t aset 96 4 Info 1 Dro PE OI EOS assetto eC PRESTA TRUE HERES IEEE RES dE TISSI Info 1 Compliance and Conformity Stalementssa 5 voissa beck AS edad etti tenente es Info 3 CE EMI OON OMT qUBOD iirosie152522e07QrepEPPePERPPPSSPadORERP RC UATESE SOUPE SS Info 3 September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide iv Contents MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide N DEN 1 Overview The MAX 10 Evaluation Kit allows is an entry level board for evaluating the MAX 10 FPGA technology and Enpirion PowerSoC regulators You can use this kit to do the following Develop designs for the 10M08S 144 EOFP FPGA Measure FPGA power VCC CORE and VCC 10 Bridge between different I O voltages Read and write to the FPGA s NOR flash memory Use the FPGA s analog to digital
18. isters push button SW1 m User DIP switch SW3 m Power m The board is powered by USB cable from PC or wall jack m One green power on LED D6 m Probe points for manual multi meter measurement of current to calculate power consumption TP2 TP5 or to verify voltages on the selected internal nodes TP1 TP6 TP9 Figure 1 1 Example MAX 10 Evaluation Kit Block Diagram To power source LEDs amp m Enpirion Mini USB Supplies m Push Button Push Button j DIP switch JTAG O Customer must purchase and install MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Chapter 1 Overview 1 3 Supported Items Not Included with the Kit Supported Items Not Included with the Kit The following items are not included in the kit but were designed to be used in conjunction with this kit Table 1 1 Additional Components Not Included with the Kit Board Manufacturing Manufacturer R94 Potentiometer Bourns 3362P 1 103TLF 1 103TLF WWW www bourns com com J8 J9 2x20 0 1 inch headers Sins ce c PPPC202LFBN RC Optional daughter www adafruit com J2 J3 J4 J5 cards Arduino UNO R3 Arduino www sainsmart com revision shields www_arduino com J1 Usb Blaster i Altera PL USB2 BLASTER Please call Download Cable September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide MAX 10 FPGA 10M08S 144 EQFP
19. ith Initial Capital Letters Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide Info 2 Additional Information Typographic Conventions Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets lt gt For example lt file name gt and lt project name gt pot file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu i Quotation marks indicate references to sections in a document and titles of Subheading Title Qm Quartus II Help topics For example Typographic Conventions Indicates signal port register bit block and primitive names For example data1 tdi and input he suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it Courier type appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI
20. lect Internal Configuration In the Configuration Mode list select 1 out of 5 configuration modes except 10M02 device which has only 2 modes available Turn on Generate compressed bitstreams if needed Click OK Generating a pof File with ICB Settings To generate a pof file from a sof file for internal configuration follow these steps 1 On the File menu click Convert Programming Files 2 Under Output programming file select Programmer Object File pof in the Programming file type list 3 In the Mode list select Internal Configuration MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide Chapter 3 Board Components Configuration 3 5 To set the ICB settings click Option Boot Info button An ICB setting dialog box will appear Several ICB settings can be set through the ICB setting dialog box including m Power on Reset Scheme Instant On Fast POR Delay or Slow POR Delay m Enable user IOs week pull up during configuration check box m Enable the JTAG Security check box m Verify Protect check box m Enable watchdog for dual boot and watching value initially grayed out after add 2 sof page with 2 design that compiled with Dual Compressed Internal Images the watchdog setting will then be enable m User Flash Memory settings In the File name box specify the file name for the programming file you want to create To generate a Memory Map File map turn on Cre
21. nnect to the MAX 10 FPGA Any analog inputs signals sourced through the Arduino header J4 are first filtered by the evaluation boards op amp based circuit This circuit scales the maximum allowable voltage per the Arduino specification 5 0V to the maximum allowable voltage per the MAX 10 FPGA ADC IP block 2 5V o You can download an example design with pin locations and assignments completed according to the following table from the Altera Design Store In the MAX 10 FPGA Evaluation Kit under Design Examples click MAX 10 Evaluation Kit Baseline Pinout Table 3 3 Arduino Connector Pin Assignments Signal Names and Functions Part 1 of 2 2 a KE Mmi 84 jams 88 runo digital VD input to FPA 88 acorn e Arumo digital VD input to FPA Arduino analog channel input through the op amp J4 1 ARDUINO A0 filter circuit to the FPGA ADC IP input channel ADCIN1 Arduino analog channel input through the op amp J4 2 ARDUINO A1 filter circuit to the FPGA ADC IP input channel ADC1IN2 Arduino analog channel input through the op amp J4 3 ARDUINO A2 filter circuit to the FPGA ADC IP input channel ADC1IN3 Arduino analog channel input through the op amp J4 4 ARDUINO A3 10 filter circuit to the FPGA ADC IP input channel ADC1IN4 September 2015 Altera Corporation MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit User Guide 3 8 Chapter 3 Board Components General User Input Output Table 3 3 Arduino Connector Pin Assignments
22. ntains the temperature sensing diode For more information on the ADC refer to the MAX 10 FPGA Device Overview MAX 10 FPGA 10M08S 144 EQFP Evaluation Kit September 2015 Altera Corporation User Guide N DTE SYN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document m Corrected sense of switches in User Defined DIP Switch on page 3 8 september 2015 1 2 l GC m Added link to Altera Design Store in Arduino Connectors on page 3 7 October 2014 Corrected FPGA pin number for SW3 2 from 121 to 124 september 2014 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Technical support www altera com support jl www altera com training Technical training custrain altera com Product literature www altera com literature Nontechnical support general nacomp altera com software licensing authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI Bold Type w
23. om max10 Configuration The evaluation Kit supports two configuration methods m JTAG header J10 for configuration by downloading a sof file to the FPGA Any power cycling of the FPGA or reconfiguration will power up the FPGA to a blank state m JTAG header J10 for programming of the on die FPGA Configuration Flash Memory CFM via a pof file Any power cycling of the FPGA or reconfiguration will power up the FPGA in self configuration mode using the files stored in the CFM FPGA Programming over External USB Blaster The JTAG header provides a method for configuring the FPGA U2 using an external USB Blaster USB Blaster II or Ethernet Blaster download cable with the Quartus II Programmer running on a PC The external download cable connects to the board through the JTAG header J10 Configuring the FPGA Using the Quartus II Programmer You can use the Quartus II Programmer to configure the FPGA with a sof Before configuring the FPGA ensure that the Ouartus II Programmer and the USB Blaster driver are installed on the host computer the USB cable is connected to the evaluation kit power to the board is on and no other applications that use the JTAG chain are running L To successfully use the USB Blaster cable disconnect it before power cycling the board After you power cycled the board then reconnect the USB Blaster cable To configure the MAX 10 FPGA FPGA perform the following steps 1 Start the Quartus II
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