IRPLDIM3 User Manual - International Rectifier
Contents
1. ANNSO Ldoa 4 ta Anoa 09 i EE Er 0 AAS I FL S341 909 desa ODA Heli I SIYI LLNOO pa Ss Au A SICH SA NIN ZNdu I SHA VW HH cx Hao H SCH OHJ LASO HdO via HdOu LSY NaO O NLY AOL 010 F sus NI AOL 010 XNY Odd1 9d H Odd1 Fig 2 Schematic Diagram IRS2158D Single Lamp Voltage Mode Heating www irf com International T R Rectifier 6 PCB Component Placement Diagram and Board Fabrication LI LI D 1 ATEN A A Tro J SA e www irf com _5 Internationa T R Rectifier www irf com 6 Intemational TOR Rectitier Bottom Layers Fig 3 PCB Component Placement Diagram www irf com ae International REFERENCE DESIGN TOR Rectifier 7 Bill of Material and Inductor Specification L6562N IRS2158D LM393N CNCIS101 1 ON Semiconductor 2N6027RLRAG Programmable Unijunction vi Transistor IRFBC30 7 DF10S Diodes Inc LL4148 13 Diode DCP1 DOUT ZMM5236B 7 DEOLI ZMM5231B 7 DEOL2 ZMM5248B 7 D3 DCP2 1 Diodes Inc ZMM5242B 7 DSD2 US1J 13 F DS1 DS2 DI 1 Panasonic ECG ELF 15N007A C2. Reference The isolated 0 to 10 V control interface operates by means of a simple circuit described in Design Tip DT 02 This operates in the same way as many other commercially available 0 to 10 V dimming ballasts The input internally biased at 10 V if nothing is connected and can be reduced to 0 V by sinking current only Isolation between the dimming input and the ballast circuitry 1s provided by means of an opto isolator IC4 and an additional isolated winding of the PFC boost inductor LPFC This winding must be isolated from the other two windings and from the ferrite cores and should be flash tested to 4 kV In order to obtain sufficient voltage this winding will need to have several more turns than the zero current detection winding It is necessary to ensure that the voltage across the 18 V zener diode D3 never falls below 18 V when the ballast output is dimmed and also over the range of line supply voltage The next part of the circuit centered around the programmable unijunction transistor Ol generates an approximate ramp waveform across capacitor C7 which peaks at approximately 10 V guaranteeing maximum output when 10 V input is applied at the dimming input A trigger voltage provided by a potential divider of 9 V is applied to the gate of O1 C7 charges through R15 until the voltage reaches a point one diode drop above the 9 V trigger voltage O1 then fires and remains switched on until the current drops below the valley current of th
3. broken or cracked but the filament is still intact the SD pin will not detect a fault However the ballast will still shut down because the CS pin will detect the transients caused by hard switching of the half bridge MOSFETs In this case the fault counter will be active so that approximately 60 consecutive transients need to be detected by the CS pin before shut down The broken lamp test is easily simulated by disconnecting the high voltage end of the lamp during running which is the end that is not connected to the SD pin lamp out detection circuit www irf com 26 ternational T R Rectifier 11 Feb 08 17 00 36 5 ms 0 50 A D ms 2 00 Y EJE HAHAHAHA Wu 3 U CD E m OONO 2 5 MS s 5 ms 1 00 ky 2 DC 3 48 Y DC ito STOPPED EZ no Ol lt lt O CI x Sx Ex Ex Fig 20 Broken Lamp Test Signal Red CS Pin Voltage Ee ri Guns Lamp Voltage The above waveforms illustrate the delay of approximately Ims introduced by the fault counter This avoids any possibility of false tripping occurring if random transients occur Disclaimer This reference design kit is intended for evaluation purposes only and has not been submitted or approved by any external test house for conformance with UL or international safety or performance standards International Rectifier does not guarantee that this reference design will conform to any such
4. V zener diode DSD2 has been added so that any voltage at the lower cathode produced during preheat which can contain some DC offset will never be sufficient to falsely trip the lamp removal shut down circuit In addition to this pulling up through resistors to the DC bus provides a more rapid response without draining current from VCC and maintains the SD pin voltage firmly above the 5 V threshold when no lamp is present under all conditions of line input voltage During preheat and ignition modes the end of life protection function which monitors the lamp voltage through the SD pin is not enabled therefore the ballast will operate as long as the SD pin remains below 5 V The SD pin is normally biased at 2 V from an internal voltage source within the IRS2158D www irf com ss VA Internationa ISR Rectifier 11 Feb 08 Reading Floppy Disk Drive 200 Y 0 los BWL 110 Y DCX S 2 V C5 25 k5 s 20 mV DC a 2 DC 3 48 Y d 2 Y DC jo STOPPED Fig 18 Lamp removal and replacement Signal Lamp Are Current Lamp Voltage The VDC pin of the IRS2158D IC2 is also connected to the DC bus through the divider formed by R23 and R24 with CVDC to COM to remove ripple and noise This provides brown out protection for the ballast which works by sensing the rectified AC line voltage at the positive output of BR1 When the VDC voltage falls below 3 V the IRS2158D shuts down The values of R23 and R24 are
5. in turn is determined by the preheat frequency through RPH and the preheat time set by CCPH Cathode heating after ignition Run mode The lamp filament Cathode resistance over the range of dimming levels should be between 3 and 5 5 times the resistance when cold A simple method for determining the hot resistance is to first connect one cathode to a DC power supply via an ammeter and slowly increase the voltage from zero noting the current at 1 V intervals This should be done until the cathode can be seen to be glowing red When this occurs the voltage should not be increased further or the cathode is likely to overheat and become open circuit With these results the resistance can be calculated for each voltage and hence the acceptable www irf com Ce e nternationa TOR Rectifier voltage range can be found to comply within the 3 to 5 5 times cold resistance limits The cold resistance can be easily measured with a digital multi meter DMM When the ballast is running a true RMS digital voltmeter or differential oscilloscope probe can be connected across the lower cathode and the voltage can be observed at maximum and minimum brightness The cathode voltage normally increases as the ballast is dimmed The values of COUT1 and COUT2 plus the resonant output inductor heater windings will control how much Reducing the capacitance will reduce the amount by which the voltage rises The COUT1 and COUT2 values should be chosen to prevent the volt
6. it is at maximum providing a reasonably linear change in the duty cycle at intermediate levels It is important in production to ensure that the opto isolator used is rated to the correct voltage and has been certified to the necessary safety standards The transistor side of the opto isolator has the emitter connected to 0 V COM and the collector connected to the IRS2158D VCC supply of 15 6 V via a pull up resistor R22 The www irf com e ld nternationa TOR Rectifier collector node is then connected via R18 to CDIV and R19 to 0 V COM This averages the PWM signal and provides a DC reference to connect to the IRS2158D which varies between OV and the maximum voltage set The range can be changed if necessary by adjusting the value of R19 The value of the lamp current sensing resistor RLS will determine the feedback voltage provided to the op amp feedback circuit of the IRS2158D The value of RLS should be selected to provide as large a feedback as possible without dissipating too much power at maximum light output It is recommended to keep the power dissipation in RLS below 0 25 W A delay is usually incorporated into dimming ballasts to provide a smooth fade from one dimming level to the next For example if the control inputs were to be shorted together the lamp would fade down to minimum brightness over a period determined by the values used This neatly avoids any flicker that may be caused by sudden changes in load in the PFC boost r
7. 5W 1206 0 25W 1206 0 25W 1206 0 25W 1206 FXBC Axial 0 25W 1206 0 25W 1206 REOL3 R15 pie R Gand A 0 25W 1206 AAA AA A A 0 25W 1206 57 1 Panasonic ECG ERO S2PHF22R0 Resistor 22 Q www irf com 9 International REFERENCE DESIGN TOR Rectifier SW Aa 0 25W 1206 0 25W 1206 1 Panasonic ECG ERJ P08J471V Resistor 470 Q R8 IT IT oct O 0 25W 1206 0 25W 1206 0 25W 1206 64 Panasonic ECG ERO S2PHF2203 Resistor 220 kO 0 25W Axial k Copal Electronics CT 94EW203 Potentiometer VRI 1 1 20 kQ top adjust 1 Panasonic ECG ERZ V10D431 Varistor 275VAC RVI 10mm 1 1 bi kasa i 5063FMIR000J12AF Fusible Resistor 1Q Fl X 235 Series Connector 5 Way P1 Table 1 Bill of Materials Lamp type TL5 28W Line Input Voltage 90 305 VAC www irf com 10 Internationa ISR Rectifier mernatior INDUCTOR SPECIFICATION Teak TITI e1 TYPE LPFC CORESIZEL V GAP LENGTH mm NOMINAL INDUCTANCE 27 mH MAXIMUM CURRENT 1 Apk MAXIMUM CORE TEMPERATURE OC FINISH PIN 1 MAIN 6 zg of AWG a E 4 EA Insulated single strand PHYSICAL LAYOUT PTT TOP VIEW TEST TEST FREOUENCY 50kHz MAIN WINDING INDUCTANCE MIN 2 6 mH MAX 2 8 mH MAIN WINDING RESISTANCE MAX 1 5 Ohms NOTE Inductor must not saturate at maximum current and maximum core temperature at given test frequency Fig 4 Power Factor Inductor Specification www irf com e 11 Internationa I
8. 8D l l perad Half Bridge Driver Dim Dimming Feedback Input PYFK BP Preheat Feedback Lamp Fault Fig 1 IRPLDIM3 Block Diagram www irf com ae International REFERENCE DESIGN TOR Rectifier 3 Electrical Characteristics Parameter Lamp Type WTS Input Power T E Lamp running voltage Run Mode Frequency W Preheat Mode Frequency kHz s Preheat Time PE 5 E Lamp Preheat Voltage Vpp Lamp Ignition Voltage kVpp Input AC Voltage Range 90 305VAC Seen 0 995 at 120VAC SE 0 98 at 220 VAC 4 Fault Protection Characteristics Fault Protection Ballast Restart Operation VDC Brown out detect Upper filament broken CS Over Current detect Lamp exchange Lower filament broken SD Open filament detect on Deactivates Lamp exchange SD EOL pin Failure to ignite CS Ignition detection timeout Deactivates Lamp exchange SD EOL pin SD EOL pin www irf com 3 o Y Lu a LLJ O LLJ cc LLJ LL LLJ cc onal R Rectifier Internati I Y 5 IRPLDIM3 Schematics sTe zsa em coud S zsngo NW e z sou zaso Laso soo NI isa zs341Z1N09 WA WM Re z90 3 sana sano ro 1039 asu zasa Lasa L aus Wiau e o ke 6 O i gt f 7103 08 ANI 1O3a z103d 199 Se1038 d at O WII so ANN A L aid SIN AAA UI 00 sayo ow 01 l O ino SINOY Y zaoa K E 311038 LIDAD SEN q OGA SS pra He p wmit al N 4 MW II 22A KO
9. Intemationa ISR Rectifier IRPLDIM3 IRPLDIM3 Wide Range Input Linear Dimming Fluorescent Ballast using the IRS2158D Table of Contents Page A NN 2 o IP 2 3 Electrical wg Tei Ee 3 4 Fault Protection Characteristics Xa 3 2 IRPLEDIM eo AMA PA 4 6 PCB Component Placement Diagram and Board Fabrication 5 7 Bill of Material and Inductor Specification a G FUNCUOJSD SCFDIOI a nn 13 www irf com _l nternationa T R Rectifier 1 Features Drives 1 x 28W TL5 Lamp Input Voltage 90 305 Vac High Power Factor Low THD High Freguency Operation Lamp Filament Preheating Lamp Fault Protection with Auto Restart Low AC Line Brownout Protection End of Lamp Life Shutdown IRS2158D HVIC Ballast Controller 2 Description The IRPLDIM3 reference design kit consists of a high power factor wide input voltage range dimming Fluorescent ballast with a fully isolated 0 to 10V control interface driving a single T5 28 W rapid start linear lamp The design contains an EMI filter active power factor correction and a dimming ballast control circuit using the PDIP16 version of IRS2158D This demo board is intended to help with the evaluation of the IRS2158D dimming ballast control IC demonstrate PCB layout techniques and serve as an aid in the development of production ballasts using the IRS2158D EMI Filter Rectifier PFC Output Stage Line iy le gt TH ie IRS215
10. SR Rectifier IMEernario INDUCTOR SPECIFICATION TR ect TYPE LRES VOLTAGE MODE CORE SIZE GAP LENGTH mm BOBBIN PINS CORE MATERIAL NOMINAL INDUCTANCE mH MAXIMUM CURRENT Apk MAXIMUM CORE TEMPERATURE 100 G WINDING ISTART PIN FINISH PIN TURNS WIRE DIAMETER mm MAIN 1 8 250 4strands of AWG 32 _ maen 6 7 10 strands of AWG 32 ce 4 5 1 10 strands of AWG 32 PHYSICAL LAYOUT 20 05mm TOP VIEW TEST TEST FREQUENCY 50kHz MAIN WINDING INDUCTANCE mH MAX 4 1 mH MAIN WINDING RESISTANCE MAX 2 Ohms NOTE Inductor must not saturate at maximum current and maximum core temperature at given test frequency Fig 5 Resonant Inductor Specification www irf com a 12 5 Intemationa TOR Rectifier 8 Functional Description The design of a dimmable ballast for linear lamps requires that the lamp power can be reduced smoothly to a low output level less than 5 of nominal lumen output It is necessary that the lamp output 1s able to be held at any level and that there will be no discernable flicker or instability at any level In order to accomplish this a closed loop control scheme is required The fluorescent lamp represents a complex load the impedance of which changes depending on the arc current and temperature of the gasses within the lamp Like all discharge lamps the fluorescent lamp displays a negative resistance behavior meaning that as the current in the lamp increases the effective resistan
11. The following inputs were selected IRS2158D 90 to 265VAC 500VDC T5 28W Single lamp Voltage mode heating Table 2 Initial BDA inputs Lamp type TL5 28W Line Input Voltage 90 305 VAC The next step is to click Calculate This displays the operating point for the ballast and calculates the values of the tank components i e LRES 5 9 mH and CRES 3 3 nF www irf com 15 2 International IGR Rectifier Operating Points Graph Graph Single lampAvotage mode heating 30 to 26S VACSOOYDC TS 201 R521550 L 5 90mH 3 30 nF Fig 8 Ideal Ballast Operating Points The operating points here display an ideal condition where the ignition frequency is above the run frequency and the preheat frequency is somewhat higher than the ignition frequency The run frequency also meets the target of 40 kHz In general it is preferable to keep the run frequency or minimum frequency at 40 kHz or above to avoid possible interference with infra red remote controls some of which operate at around 35 kHz In order to use a more practical value it was decided to fix LRES at 4 mH for this design which is more easily available In the BDA Tank Components section the Fix L box should be checked and the value of 4 mH entered in place of 5 9 mH After the Calculate button has been clicked a message will appear stating that the ballast run frequency is now higher than the ignition frequency Although many other ballast
12. age exceeding the upper limit at minimum output to prevent premature end blackening of the lamps and reduced life Note that utilizing additional windings on the inductor to provide cathode heating means that power is transferred through the core and consequently the core losses will increase and hence the core operating temperature The core will reach its highest operating temperature when the ballast is running at minimum brightness The component values in this design have been selected for a 28W T5 linear lamp The circuit will need to be optimized for the particular lamp used to obtain best performance Ignition The IRS2158D incorporates regulated ignition control 11 Feb 08 16 41 28 15 0 50 ky los DM 1 110 Y DCX y 5 V DOX 258 kS s 10 m OC x ES 4 DC 1 02ky 4 5 V DC A STOPPED Fig 16 Lamp Voltage and CPH pin voltage No Ignition At the end of the preheat period the IRS2158D VCO pin voltage increases and so the frequency decreases until the voltage at the CS pin reaches the internal threshold of 1 25 V At this point the IRS2158D internally pulls down the VCO pin voltage and therefore regulates the circulating current in the resonant output circuit of the ballast and maintains a constant voltage across the lamp green trace This voltage will remain while the CPH pin voltage red trace charges from 1 3VCC to 1 2 VCC If the lamp has not ignit
13. both the half bridge MOSFETs and the lamp current feedback both meet 3 The VCC decoupling capacitor should be placed as close to the IRS2158D VCC pin 13 and COM pin 12 as possible with the shortest possible traces 4 The devices CPH RMIN CVCO CT and CCS should all be located as close to the IRS2158D as possible with traces to the relevant pins being as short as possible 5 The ground connections from the devices listed in 4 should be connected back to the COM pin of the IRS2158D through the shortest possible traces These should be connected back to the COM pin of the IC without joining the power ground trace at any point In the example shown above the power ground trace runs along the lower side of the board on the bottom Copper layer 6 The charge pump diode connection to ground should be made to the power ground not the signal ground 7 The power factor correction section if used should be kept apart from the ballast control as shown in the example above the power factor correction section is at the left side of the PCB Output Inductor Design The output inductor LRES should be designed to allow a sufficient peak ignition current without saturating This is important as the ballast will be unable to ignite if unable to deliver sufficient voltage at the lamp The ignition current depends on the type of lamp being used and must be kept to a minimum by ensuring that the cathodes are sufficiently preheated To minimize eddy curr
14. ce of the lamp will reduce The lamp impedance is strongly dependent on the arc current however the relationship 1s not linear and temperature 1s also a factor The IRPLDIM3 ballast as shown in the block diagram of Fig 1 supplies the lamp through a resonant output circuit In this design the lamp power 1s adjusted by changing the oscillation frequency of the MOSFET half bridge which is driven by the IRS2158D In this system the lamp current against ballast frequency characteristic of the system exhibits a sharp knee characteristic such that as the frequency increases the lamp current is gradually reduced up to a point at which a small increase of frequency will result in a large reduction in the lamp current Ballast Lamp Operating Characteristic Lamp Current Ballast Running Frequency Fig 6 Lamp Current against Ballast Frequency Consequently 1t becomes necessary to include a stabilized closed loop feedback system to control the lamp current by adjusting the ballast frequency by means of a voltage controlled oscillator VCO In this example the VCO within the IRS2158D is driven by the output of an error amplifier and compensation network that senses the lamp arc current directly and compares 1t with a reference www irf com 13 Intemationa TOR Rectifier Regulated Lamp Current Control System VCO amp DRIVER o Error Amplifier and Compensation O 63 Lamp Arc Current Fig 7 Closed Loop Dimming Control
15. control IC s are not capable of operating under this set of conditions the IRS2158D may be used without problems The graph for the operating points now looks like this www irf com 16 International IGR Rectifier Operating Points Graph Graph Single lampuvoltage mode heating 30 to ADAC S00 V DE TS 20 IR52158D L 400mH 3 50 nF Fig 9 Ballast Operating Points for IRPLDIM3 The operating points are as follows Preheat Frequency 56 4 kHz Ignition Frequency 52 3 kHz Resonance Frequency 43 8 kHz Run Frequency 54 3 kHz Table 3 Practical Operating Points Lamp type TL5 28 W Line Input Voltage 90 305 VAC In order to guarantee that the ballast is always capable of producing a high enough output voltage to ignite the lamp the minimum frequency set by CT and RFMIN should be set close to the resonance frequency If the minimum frequency is set too far above the resonance frequency then during ignition the frequency will ramp down to the minimum frequency and remain there indefinitely The ballast would not be able to operate correctly as it would never reach a low enough frequency to enable the ignition regulation to function and would never produce enough voltage at the output to ignite the lamp In this design CT 1s 1 nF and RFMIN is 15 kQ giving a minimum frequency of approximately 40 kHz and a dead time of 1 5 us which are acceptable values The value of RPH sets the preheat frequency and has bee
16. e device which is small discharging C7 again This produces a continuously oscillating ramp waveform It is important that R15 is sufficiently large that it does not supply a current larger than the valley current otherwise Q1 remains on indefinitely and the circuit does not oscillate It necessary for this oscillator to run at a frequency of several hundred Hz to prevent it from being a source of visible flicker This sawtooth signal is fed into the inverting input of a comparator Note that this circuit makes use of a dual comparator IC by placing both comparators in parallel so as to provide greater current sinking capability to drive the input of IC4 However there is no need for this provided the comparator used is capable of sinking the opto isolator diode current which in this case is around 13 mA The opto isolator diode current should be chosen to be as low as possible to guarantee saturation of the transistor when it sinks 1mA and consequently R14 is as large as possible The non inverting input is connected to the control input and pulled high via R20 which provides a sink current of 1 mA C8 removes any noise that may be picked up at the comparator input The comparator output is open collector providing current to the input of IC4 when low The diode will be continuously off when the input is at maximum and on when it is zero Hence the opto isolator output transistor will be fully on when the control voltage is at minimum and fully off when
17. ectively limits the maximum lamp power because the error amplifier will regulate the frequency in order to maintain equal voltage at RLS to the input voltage at RDIM The run frequency will therefore be above the ignition frequency The minimum dimming level can be set by R19 and adjusted by RV1 which prevents the opto isolator transistor from pulling the error amplifier input voltage all the way to zero If the opto isolator were on continuously the input voltage to the error amplifier would be so low that the lamp would extinguish or enter an unstable state of partial ignition Tests have indicated that the T5 lamp behaves differently when cold and hot at very low light levels When the lamp is cold the arc tends to become unstable as the lamp repeatedly extinguishes and re ignites however when the lamp is hot it is possible to dim all the way down to virtually zero output and a state can be observed where the lamp is in a stable state of semi ignition characterized by an faint emission of light along only part of the length of the tube In a practical design it is desirable to limit the minimum output level to the minimum current at which the lamp can maintain stable operation when cold www irf com 5 Jg Intemationa ISR Rectifier The ballast was measured over the input dimming range Control Frequency Ballast Lamp Arc Current Arc Power RES Input V kHz Power W Voltage mA rms W rms Feedback V rms Voltage Table 4 Dimm
18. ed at this point the IRS2158D will shut down If preheat is insufficient the ballast will fail to ignite and shut down at the end of the ignition phase as shown in Fig 6 In this design the ignition voltage has been set at 1 25 kV peak and 2 kV peak to peak This ignition voltage is correct for worst case conditions in a 28W TL5 lamp and can be set by using an RCS value of 1 5R A good lamp normally ignites as the output voltage ramps up to the ignition regulation level as shown in Fig 17 www irf com 23 Internationa ISR Rectifier 11 Feb 08 16 40 21 3 LeCroy 2 S 200 mA a a 9 50 ky 2 a BWL 110 V OC x 5 V DCs 100 kS s 28m DOH 7 30c OG 108 A 4 5 V OC STOPPED Fig 17 Lamp Voltage and Current Correct Ignition Protection Circuits The SD pin of the IRS2158D is used for lamp removal protection If there is no lamp present the voltage at SD pin will be pulled above the 5 V threshold via RPUI and RPU2 and RSD charging CSD1 and CSD2 through DSD1 and DSD2 When a lamp is in circuit the voltage at the junction of RPU2 and RSD will be held low via DS1 and RLS In this way when a lamp is removed the ballast shuts down and the lamp is replaced with a good one the ballast starts up again In the IRPLDIM3 design the pull up of the SD pin for lamp removal detection is connected to the DC bus instead of VCC as in some other designs This is because an additional 12
19. egulator section In this case delay 1s provided via the time constant of R18 and CDIV As the frequency of the PWM signal from the opto isolator 1s of the order of tens of Hz the delay has been designed to be long enough to ensure minimal ripple on the DC control voltage input to the IC This can be increased if a longer fade time is desired by making CDIV larger Since the lamp arc current is being sensed with a resistor it 1s necessary to use voltage mode preheating to avoid detecting the sum of the current in the arc added to the resonant output capacitor CRES current This has an additional advantage that during preheat and prior to ignition of the lamp the arc current will always be zero and consequently the feedback circuit will not influence the oscillator frequency at all until the lamp is running This means that by setting the value of RPH the preheat will occur in exactly the same way independent of the dimming control voltage achieving optimum preheat and ignition under all conditions Design of the Ballast The initial step in designing the ballast 1s to determine values required for the resonant output inductor LRES and capacitor CRES The Ballast Design Assistant BDA software which can be downloaded from the International Rectifier web site 1s an extremely useful tool in doing this The BDA software used should be Version 4 2 x or above this can be determined by clicking the Help button and clicking About Ballast Designer
20. ent losses in the inductor windings multi stranded wire should be used Ferrite cores of sufficiently good quality should also be used to allow a high peak flux density at increased temperature and low core losses It is important to have a large enough air gap to produce the highest available peak current before allowing the inductor to saturate If the air gap is too large however losses can occur because the magnetic field emanating from the gap extends far enough to induce eddy currents in the windings When the cores are hot the saturation point and hence the peak current for the inductor will be lower therefore a poorly designed inductor may result in the ballast failing to ignite the lamp during an attempted hot re strike The inductor design process can be greatly simplified by using the Ballast Designer software For this application it is recommended to fix the core size to EF25 and gap size at 1mm Lamp Preheating It is essential that the lamp be sufficiently preheated before ignition The correct preheat current can be determined from published data or from International Rectifier s Ballast Designer software It is necessary in order to achieve the maximum possible lamp life to heat the cathodes to the correct temperature before ignition Accelerated deterioration occurs if lamps are ignited when the cathodes are either not sufficiently heated or over heated The cathode temperature at ignition is determined by the preheat current which
21. ference and ground loop issues that can occur in the ballast circuit These connection techniques also prevent high current ground loops from interfering with sensitive timing component operation and allows the entire control circuit to reject common mode noise due to output switching Figure 14 and Figure 15 show the control section of a typical ballast designed around the IRS2158D where the IC is located in the center In this design all SMD devices are mounted under the PCB with discrete devices on top 6 t930 HALF BRIDGE 2303 CURRENT SENSE RESISTOR FAIS SENSITIVE TIMING IRS2158D COMPONENTS VCC DECOUPLING CAPACITOR EREM Java KO teg Wed CHARGE PUMP WITH FIRST FILTER RESISTOR Fe eee Ae ok SII 5 ma Jt AS LE L d E M CaN fag ba e Y JR ar MR I Mo LAMP CURRENT E SENSE RESISTOR e SIGNAL AND POWER GROUNDS JOIN HERE SUGA SIGNAL GROUND STAR POINT AT IC COM SECOND FILTER RESISTOR AND CVCC Fig 14 Critical traces on the bottom side of the PCB IMA og ss r lo 0 A C SINGLE TRACE JOINING SIGNAL AND POWER GROUNDS Fig 15 Critical traces on the top side of the PCB www irf com e SL Intemationa T R Rectifier 1 The signal ground pin 12 should only be connected to the power ground at one single point to prevent ground loops from forming 2 The point described in 1 should be where the grounds of the current sense resistors for
22. g 19 Brownout shutdown and restart Signal Gang An Guns Lamp Voltage The IRPLDIM3 ballast also includes end of life protection which is enabled only after successful ignition when the ballast is in run mode The lamp voltage is divided down through REOL1 REOL2 REOL3 and REOL4 This divided voltage is fed to two back to back zener diodes DEOL1 7 5 V and DEOL2 5 1 V The SD pin is internally biased at 2 V with a window comparator that has 1 V and 3 V thresholds If the positive peak of the lamp voltage becomes large enough to allow DEOL1 to reverse breakdown then the SD pin voltage will rise above 3 V A delay is incorporated by clocking the oscillator pulses with the fault counter so that after a number of cycles the IRS2158D will shut down The delay is normally around Ims and was added to provide some immunity to transients and false shutting down of the end of life circuit In the same way if the negative peak of the lamp voltage drops low enough for DEOL2 to reverse breakdown then the SD pin will fall below 1 V After the same delay period the IRS2158D will also shut down This end of life circuit will therefore cause the ballast to shut down if an aging lamp is connected if 1t produces an asymmetric voltage in either direction due to the rectifying effect End of lamp life shutdown is often a mandatory requirement for electronic ballasts In the event of a ballast output becoming open circuit during running for example if the lamp 1s
23. ing Test Results These are average values as there is some frequency modulation occurring at all times as the system regulates and compensates for impedance changes in the lamp The measured results show that the lamp arc current and power are reasonably linear with respect to the input control voltage Arc Current o Arc Current Fig 11 Graph of lamp arc current against control voltage input www irf com 19 International T R Rectifier Arc Power 4 Arc Power Fig 12 Graph of lamp arc power against control voltage input 11 Feb 08 16 35 04 1 leCroy F 5 pa leCroy 100 V T T 5 ps T 1 00 V 3 3 bala eg j 5 ys Ka Rap En el 108 mA ku 1 4 8 t 8 5 ps 0 50 ky Fregi mi 62 0733 kHz rms 4 220 4 V rms 3 4 2 mA crmstA Y 9 9 W 5 ps BWL 118 Y DEA I DEJ 500 MS s 18 m DC DC 204 V 4 5 Y DC STOPPED Fig 13 Ballast Waveforms at Minimum Brightness Power Factor Correction Section The power factor correction stage at the front end of the ballast is based on a standard critical conduction mode circuit using an industry standard control IC This stage has been designed to provide a DC bus of 480 V and operates with the AC line input voltage from 90 Vrms up to 305 Vrms which is the maximum voltage that may occur on a 277 VAC line allowing virtually w
24. n selected at 36 kQ Since the minimum frequency is now below the run frequency in order to prevent over driving the lamp it is important to set the maximum lamp output The operating range is defined by the values of RLS R18 and R19 RLS is chosen to be as large as possible to produce a sufficient feedback voltage without dissipating too much power A value of 22 Q has been calculated to produce an average feedback voltage of 1 5 V when the lamp current is at its maximum value of 140 mA RMS with a power dissipation of 100 mW www irf com 17 Intemationa ISR Rectifier 11 Feb 08 Reading Floppy Disk Drive 16 34 08 1 5 ps 100 Y 5 ps 1 00 V eis A mA h Freq 0 nn 51 4562 kHz rms 4 215 6 V rms 3 127 4 mA crms Y 32 9 W 5 ps BWL 110 V DC cL YG SG 500 MS s 19 mV DEA j DE 284 V 4 5 Y DC STOPPED Fig 10 Ballast Waveforms at Maximum Brightness Signal Half Bridge Voltage VS Feedback Voltage at RLS and DS1 Cathode Lamp Are Current Lamp Voltage Lamp Power 3 multiplied by 4 The values of R18 and R19 have been selected so that when the opto isolator IC4 is completely off the voltage at the input of the error amplifier at RDIM connection with the wiper of VR1 will be 1 5 V This will set the error amplifier input voltage to 1 5 V when the 0 to 10 V dimming control voltage is a 10 V and maximum output is required This eff
25. ommon mode Choke Vogt Electronics IL 070 118 11 PFC Inductor LPFC Vogt Electronics IL 070 118 21 LRES l Epcos B32922A2224M l a E 1 BC Components 2222 338 14104 Capacitor 100 nF VR pomes Panasonic ECG ECU V1H103KBM 1206 Panasonic ECG ECJ 3YX1C106K C4 C6 1206 Panasonic ECG ECJ 3VB1C684K Capacitor 0 68 uF C5 1206 CC2 CSD2 16V 1206 5 Panasonic ECG ECJ 3VB1C104K CVCC2 Panasonic ECG ECU V1H333KBM Capacitor 33nF 50V C7 1206 C C2 C3 Capacitor 100n 16V C11 CBOOT Panasonic ECG ECJ 3YB1C105K C8 CDIV CVDC 1206 Panasonic ECG ECA 2EHG330 CBUS1 CBUS2 250V 105C Panasonic ECG ECJ 3YB1C225K CVCCI 16V 1206 l Panasonic ECG EEU FC1H470 l 50V 105C Panasonic ECG ECU V1H471KBM 50V 1206 Panasonic ECG ECO E6104KF CD 630V 3 Panasonic ECG ECJ 3VB1C474K Capacitor 0 47 uF CEOL CSD1 16V 1206 CCPH 9 C C pt po put N B Go ho Nin E V NO O 2 2 2 2 2 2 2 2 2 CS C 17 18 19 0 1 2 3 A 5 6 7 8 9 2 www irf com 8 International REFERENCE DESIGN T R Rectifier a V E S 6 3V dl 50V Radial 1600V 1 kV Radial 200V 1206 NPO 100V 1206 AR RR AS if kA 100V 1206 NPO A L E2GA332MYGS Pe A HP 0 25W 1206 0 25W 1206 0 25W 1206 0 25W 1206 A IT Loch In 0 25W 1206 S p pman O TTT st 8 0 25W 1206 a o Sin fa 0 25W 1206 0 25W 1206 E pp ee aag e 0 25W 1206 eem a it A 0 25W 1206 RFB RIN ROUT 0 2
26. orld wide operation The value of LPFC given by the BDA software is 2 7 mH In a dimming design with a wide voltage input range it is necessary to select the optimum value for the PFC inductor www irf com 20 nternationa TOR Rectifier The inductance must be sufficiently large to allow the PFC controller IC1 to maintain stable operation when the line input at maximum and the dimming level is at minimum Under these conditions the COMP voltage at pin 2 will be very low and the PWM on time will be very short If the inductor value is too small the on time will become too small for the control IC to be able to maintain a stable DC bus The result of an unstable DC bus is a slight but visible flicker seen when the lamp is dimmed Such instability is usually caused by instability of the power factor correction section rather than the lamp current regulation loop incorporated within the IRS2158D IC2 The trade off is that if the value of LPFC is too high the bus voltage will start to drop at low line input and maximum load since the COMP pin voltage has reached maximum and therefore the maximum on time limit has been reached The lamp current control loop is however able to lower the ballast frequency in order to compensate for this to some degree if necessary PCB Layout Considerations In order to successfully utilize the IRS2158D in a ballast design it is necessary to follow the following PCB layout guidelines This can avoid possible inter
27. selected so that this condition occurs when the AC line input drops below the minimum level at which the ballast can maintain sufficient DC bus voltage for the lamp to remain ignited and run at the correct power When the ballast has shut down the voltage at the VDC pin will rise because the voltage at BR1 will no longer be full wave rectified as there is no load and C2 is sufficient to maintain a DC level To prevent the ballast from immediately re starting there is a 2 V hysteresis such that the VDC pin must rise above 5 V in order for the IRS2158D to restart This will only happen after the AC line has been restored to a sufficient level Without the brownout protection provided by the VDC pin if a brownout did occur the ballast would shut down in the event of any hard switching at VS because voltage spikes would appear at the CS pin This would cause the fault counter to count up until the ballast shut down In that event the ballast would shut down and remain off until the line is switched off and then back on again This is undesirable and with the implementation of the VDC pin of the IR2158D can easily be avoided so that the ballast will automatically recover from a Brownout event and switch the light back on www irf com Se Internationa ISR Rectifier 11 Feb 08 16 54 38 3 5s 200 mA 5 s BWL 110 Y ocx 2 5 V OC x 50 kS s 20 mV OC i 3 DC 0 108 A A EV DE L STOPPED Fi
28. standards Ballast Designer software may be downloaded free of charge from www irf com whats new nr051026 html IR WORLD HEADQUARTERS 233 Kansas St El Segundo California 90245 Tel 310 252 7105 Data and specifications subject to change without notice 3 13 2008 www irf com A ee
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