GPIO-MM-12 User Manual - Diamond Systems Corporation
Contents
1. nennen nnne nnn 24 Diamond Systems Corporation GPIO MM 12 User Manual Page 2 OVervieW xa eto Peed 24 Accessing the Counter Timer Internal 24 Master Mode Register visas sos es Sa eee ee eee eee 24 Courter Mode Register ioa b serach eRe eee 24 Counter MOGOS eb desde et Sin M electus 24 FOUT Frequency erdt cud an rerom 24 Command Moa decet Mo een ee ot eae bids 24 Counter Programming IR tent ona adel sp eed 25 Programming Digital titt hemos 26 48 bit Programmable Direction 8255 cene 26 16 bit Fixed Directo 95139 ipia qe p patet ate ing eerie 27 Programming Enhanced 28 EEPROM Programimitig I id ERE o Counc sare vedere sesta que 28 Specilicatiols 29 General e ET 29 Additional Information oer ned id nes cue inte Fea LA 30 BEI c 30 D eile iEsjlsepmPsu IL 31 Figures Figure 1 GPIO MM 12 Board 6 Figure 2 Set DIO2. Optional Load initial data into the Hold Register Issue a Load and Arm command for the counter ARWN To read counter contents 1 Issue a Save or Disarm and Save command 2 Read the Hold Register Diamond Systems Corporation GPIO MM 12 User Manual Page 25 Programming Digital I O 48 bit Programmable Direction 8255 GPIO MM 12 provides 48 DIO lines using an FPGA core implementation of two 82C55A devices 82C55A 1 and 82C55A 2 The DIO functionality includes 48 programmable direction lines and 8 fixed inputs and 8 fixed outputs The 48 programmable I O lines are buffered for enhanced output current while the fixed I O and the counter timer signals feature ESD protective circuitry All I O lines contain jumper selectable 10Kohm pull up pull down resistors Operation of the 82C55A FPGA core should be as described in the 82C55A PPI datasheet Refer to the 82C55A datasheet Additional Information for detailed register and programming information The 82C554 has three parallel I O ports Ports A and B are 8 bit bi directional I O ports Port C is divided into two 4 bit bi directional I O ports For programming the ports are arranged into two groups as shown below Port Group Description A 8 bits of Port A and upper 4 bits 4 7 of port C B 8 bits of Port B and lower 4 bits 0 3 of port C NOTE The port groups can be separately configured for different operating modes However GPIO MM 12 onl
3. 1 high level If the line is currently set to output mode according to the AUXnDIR bit below the read value corresponds to the current output level Write the low level or high level value to the AUXnOUT bit to set the respective auxiliary DIO line level The level applies even if the line direction AUXnDIR is set to input mode The value will be applied when the line direction is set to output mode Auxiliary line I O direction and state Write the following values to the AUXnDIR bit to set the I O direction output input for the respective auxiliary DIO line 0 output mode 1 input mode Read the bit to determine the current I O mode Diamond Systems Corporation GPIO MM 12 User Manual Page 20 Board Reset and ID Register Counter timer Base OFh Bit id 6 5 4 3 2 1 0 Name ID7 ID6 ID5 104 ID3 ID2 ID1 IDO BRDRST IDO ID7 FPGA personality ID Indicates the personality of the onboard FPGA the value for the GPIO MM 12 board type is 11h BRDRST Board reset Write 1 to this bit to reset the board which has the same affect as an external reset pulse 8255 Data Registers DIO Base 00h 8255 1 Port A DIO Base 04h 8255 2 Port A DIO Base 01h 8255 1 Port B DIO Base 05h 8255 2 Port B DIO Base 02h 8255 1 Port C DIO Base 06h 8255 2 Port C Bit 7 6 5 4 3 2 1 0 Name DATA DATA 8 bit parallel data On reset the port is set to input
4. DIAMOND SYSTEMS CORPORATION GPIO MM 12 User Manual FPGA based PC 104 Counter Timer and Digital Module User Manual v1 00 Copyright 2006 Diamond Systems Corporation 1255 Terra Bella Ave Mountain View CA 94043 Tel 650 810 2500 Fax 650 810 2525 www diamondsystems com Table of Contents A VS ES ccs G 4 Digital l O Features eo pit Reni a du 4 Counter Timer Features et REL o ie not en os etes de 4 Enhanced Featufes c Accs ate a gh ted A netu uides uento Let adele 5 Ip mE OU e MI 6 Deb ibd a eec o pa ceder iL aud 6 VO Connector nci seo 7 Digital WO Header Pinout iere ae evened ua eq a Ra Maem eae 7 Counter timer Header oe op lei too hed e bebe du UD ee ec 9 Auxiliary Header Plots ostenta Re On page ea vi ER pete rai ean 10 Board Configiralion erri oe EE Ioa 11 Base Address Selgctloft eerte eo i dote bg itle ed tabo iq 11 Interrupt Level nennen 12 I O Line Pull up Pull down 13 AO CR 14 OVELVIGW ceci og Dade
5. PB8H and the PB24HQ These racks and I O modules allow up to 3000 VRMS isolation between the computer and the user s signals All control signals power and ground on the DIO header match the corresponding signals on these I O racks so a single 50 pin ribbon cable such as Diamond Systems C50 18 is all that is needed to make the connection The FPGA counter timer cores provide an additional 8 bit TTL output port with up to 4 mA per bit and a separate 8 bit TTL input port Both ports can be operated in bit or byte mode The counter timer provides ten extremely versatile counters with a wide variety of features including up or down counting binary or BCD counting single or repetitive counting edge or level gating output pulse or toggle capability alarm comparator circuitry and software or hardware retriggering All counter features are programmable through software In addition an internal series of frequencies is provided which may be used as internal count sources The counter timers can be used to generate retriggerable one shots timed pulses and square waves of variable duty cycle and to count pulses measure time intervals between pulses and measure the frequency and period of a periodic waveform The GPIO MM 12 provides access to interrupt levels 3 7 10 12 and 15 on the PC bus for real time background applications Interrupts provide a means for transferring data into or out of PC memory under external control Using interru
6. Set bit to 1 to initiate an EEPROM byte transfer in the direction indicated by the EE RW bit FPGA Revision Code Register Counter timer Base 0Bh Bit 7 6 5 4 3 2 1 0 Name FPGA Revision Code FPGA This register contains a hexadecimal FPGA revision code The initial value is 12h Revision Code Diamond Systems Corporation GPIO MM 12 User Manual Page 18 Interrupt Source Register Counter timer Base 0Ch Bit Name IRQB IRQA IRQA IRQB Select the IRQA interrupt source 00h Counter timer 1 output 01h Counter timer 2 output 02h Counter timer 3 output 03h Counter timer 4 output 04h Counter timer 5 output 05h Counter timer 6 output 06h Counter timer 7 output 07h Counter timer 8 output 08h Counter timer 9 output 09h Counter timer 10 output OAh dedicated interrupt input pin lt Reset value DIO input 0 8255 1 CO 8255 1 OEh 8255 2 CO OFh 8255 2 C3 Select the IRQB interrupt source using the same values as for IRQA above The reset value for IRQB is Diamond Systems Corporation GPIO MM 12 User Manual Page 19 Interrupt Control and Status Register Counter timer Base 0Dh Bit 7 6 5 4 3 2 1 0 Name IRQBEN IRQBDIS IRQBSTS IRQAEN IRQADIS IRQASTS IRQBCLR IRQACLR IRQASTS IRQA interrupt status
7. a valid data byte is available and the next byte may be read m Ts Diamond Systems Corporation GPIO MM 12 User Manual Page 28 Specifications General Specifications Base FPGA Xilinx Spartan II 200 000 gates 40K RAM bits Input clock 40MHz FPGA code storage Flash memory field upgradeable via e ID indicator 8 bit LED display indicates FPGA code personality field upgradeable via JTAG e Counter timers 10 16 bits using 2 CTS9513 cores Maximum counting frequency 40MHz Counter modes Counter rate square wave generator pulse width modulator programmable one shot hardware software triggered strobe e Programmable 48 using 2 82C55A cores Fixed direction I O 8 fixed inputs 8 fixed outputs e Output current buffered I O Logic 0 64mA max per line buffered I O Logic 1 15mA max per line e Output current fixed I O and counter timers 24mA max Dimensions 3 55 x 3 775 PC 104 form factor e PC 104 bus 16 bit stackthrough ISA bus e Power supply 5VDC 5 Operating temperature 40 to 85 C e Weight 2 207 Diamond Systems Corporation GPIO MM 12 User Manual Page 29 Additional Information Datasheets Datasheets provide programming reference information for the counter timer and DIO functions 1 CTS9513 2 5Chan 16 bit 20MHz Counter Timer Celeritous Technical Services Corp September 2000 2 82C55A CMOS Programmable Peripheral Interface Harris Semiconduc
8. D du omar 14 Counter Timer and Enhanced Feature 14 DOs PROGRAMING eee ec Tm 15 Register Bit Descriptions nieder n desit leder cedo et 16 9513 Command and Status Data scoop eo 16 9513 Command and Status Data Pointer 16 9513 DIO Data Regis els cote er ette bebe tee shes es edepol etn 16 9513 Interrupt Control ISeglslels c ore oc ope ee Ceo il ee eese Come tote Phe 17 EEPROM D lta Reglsler cii teo sepu eet 17 EEPROM Address Register eese cesses tenen cuna n 17 EEPROM Control and Status 18 FPGA Revision Code Register ee 18 Interr pt SOURCE e bie reperto eee ee ese 19 Interrupt Control and Status 15 20 Auxiliary DIO Control and Status 20 Board Reset and ID eo bead oes een desee diee t epus dca o p 21 8255 Dala Registers iue o pee pte s IU ULIS UN icr 21 8255 Control and Status Registers Basic Mode Definition MSFLAG 1 22 8255 Control and Status Registers Bit SET RESET Mode MSFLAG2 0O 23 Programming the
9. as shown to set the 8255 and 9513 base addresses VO 2 3 4 5 44 DIO Pins Address 6 7 8 9 lt Pins 0040h Out In In In 0080h In Out In In 00COh Out Out In In 0100h In In Out In 0140h Out In Out In 0180h In Out Out In 01COh Out Out Out In 0200h In In In Out 0240h Out In In Out 0280h In Out In Out 02COh Out Out In Out 0300h In In Out Out 0340h Out In Out Out 0380h In Out Out Out 03COh Out Out Out Out NOTE Different address must be selected for the DIO and counter timer functions The example below selects a DIO base address of 0040h Figure 2 Set DIO Base Address to 0040h crc 9876543210 The following example selects a counter timer base address of 0100h Figure 3 Set Counter Timer Base Address to 0100h crc 91 19011 e efle e e e eje Diamond Systems Corporation GPIO MM 12 User Manual Page 11 Interrupt Level Selection Jumper J7 is used to switch the IRQA interrupt and jumper J9 is used to switch the IRQB interrupt PC 104 lines that can be selected are IRQ3 to IRQ7 IRQIO to IRQ12 and IRQ15 The examples shown below also apply to the J9 jumper block for IRQB The example below shows J7 jumpered to route IRQA to PC 104 IRQS Figure 4 Route IRQA to PC 104 IRQ5 1 91 e 345 6 7 101
10. for the 9513 This register points to the 9513 command and status register location to write the data contained in the Command and Status Data Register base 00h Refer to the 9513 datasheet Additional Information for a description of the command and status register 9513 DIO Data Registers Bit 7 6 5 4 3 2 1 0 Name DIO7IN DIO6IN DIOSIN DIO4IN DIO3IN DIO2IN DIOIIN DIOOIN DIO7OUT DIO6OUT DIOSOUT DIO4OUT DIO3OUT DIO20UT DIOIOUT DIOOOUT DIOOIN DIO input line state Reading the bit corresponding to the DIO line returns the line state DIO7IN 0 low level line state 1 high level line state DIOOOUT DIO output line state Writing the bit corresponding to the DIO line sets the line state DIO7OUT 0 set line state to low level 1 set line state to high level Diamond Systems Corporation GPIO MM 12 User Manual Page 16 9513 Interrupt Control Registers Counter timer Base 06h Base 07h shadow register Bit T 6 5 4 3 2 1 0 Name INTE INTE Interrupt enable Write to this bit to enable or disable counter timer interrupts 0 disable interrupts 1 enable interrupts If IRQA and IRQB are both counter timer interrupts both interrupts are enabled or disabled by writing to this register IRQA and IRQB are considered counter timer interrupts if the interrupt source is the counter timer output 1 10 dedicated interrupt input or DIO in
11. mode and the port is held at a logic level 1 until the reset signal is removed The port remains in input mode until changed using the control register Following a reset all lines are set to input mode Diamond Systems Corporation GPIO MM 12 User Manual Page 21 8255 Control and Status Registers Basic Mode Definition MSFLAG 1 DIO Base 03h 8255 1 DIO Base 07h 8255 2 Bit 7 6 5 4 3 2 1 0 Name MSFLAG MSELA PADIR PCUDIR MSELB PBDIR PCLDIR PCLDIR PBDIR MSELB PCUDIR PADIR MSELA MSFLAG Port C lower direction Sets the direction of the port C I O signals 0 3 0 output 1 input Reset value Port B direction Sets the direction of the port B I O signals 0 output 1 input Reset value Group B mode selection Sets the mode of operation for the group B signals 0 mode 0 lt Reset value 1 mode 1 NOTE 1 Only mode 0 is currently implemented 2 All output registers are reset when the mode is changed Port C upper direction Sets the direction of the port C I O signals 4 7 0 output 1 input Reset value Port A direction Sets the direction of the port A I O signals 0 output 1 input Reset value Group A mode selection Sets the mode of operation for the group B signals 00h mode 0 lt Reset value 01h mode 1 Ixh mode NOTE 1 Only mode 0 is currently implemented 2 All output registers are reset when the mode is c
12. 112156 Jumper blocks J7 and J9 are also used to enable interrupt sharing for each IRQ signal enabling a 1KQ pull down resistor When an I O module drives an IRQ line its output signal must either drive logic high or become a tri state input This allows more than one device to be on a single IRQ line To facilitate this a pull down resistor is used on the IRQ line to bring the logic low when no device is signaling an interrupt Shorting the R resistor jumper connects a 1K pull down resistor between the IRQ line and ground The following example shows IRQA connected to a 1K pull down resistor and routed to IRQ5 which is shared Figure 5 Connect IRQA to Pull down Resistor Route to Shared IRQ5 CBee 1511 11 11 16 345 6 7 10111215R NOTE There can only be one pull down resistor IRQ line If jumper blocks J7 and J9 both select IRQS only one jumper block should have the R jumper inserted Likewise there should only be one R jumper in a configuration of multiple GPIO MM 12 boards NOTE All positions are paralleled with zero ohm resistor locations for hard wire configuration IRQA and IRQB interrupts sources are selected by configuring the enhanced feature register OCh as described in the Section 6 Register Bit Descriptions Interrupt Source Register NOTE All positions are paralleled with zero ohm resistor locations for hard wire configuration line pull up pull down selection Diamond Systems Corp
13. Base Address to 11 Figure 3 Set Counter Timer Base Address to 1 11 Figure 4 Route IRQA to PC 104 1605 iT oet ot oue p rad er ea cut Dro e 12 Figure 5 Connect IRQA to Pull down Resistor Route to Shared IRQ 5 12 Figure 6 Pull I O Pins Up to FOV DC ot bb e oben bo senes ots 13 Figure 7 Pull I O Pins Down to Ground iret cn etr e o redes 13 Diamond Systems Corporation GPIO MM 12 User Manual Page 3 General Description Overview The GPIO MM 12 is a PC 104 board featuring 48 Digital I O DIO lines 10 16 bit counter timers 8 bits of TTL input 8 bits of TTL output and software controlled interrupt capability The DIO and counter timer functions are implemented in FPGA cores emulating dual 82C55A PPI and dual CTS9513 counter timer chips A 50 pin I O header provides for external DIO connections Direction on all ports is selected by programming control registers in the FPGA All I O lines are buffered with transceivers whose directions are controlled by logic that responds to the direction control values written to the registers Each line is capable of sinking 64mA in a logic low state or sourcing 15mA in a logic high state The board requires only 5V for operation DIO headers are organized to allow direct interfacing to OPTO 22s isolated I O racks including the G4 series the PB16 H J K L
14. MM 12 User Manual Page 24 Counter Programming Before programming any individual counter the 9513 Master Mode Register must be programmed Programming an individual counter requires several steps First the Counter Mode Register must be set to indicate the desired operating characteristics of the counter such as gating level and type count direction and type and output type After the Counter Mode Register is programmed load the appropriate data into the Load and or Hold register s The Load register is used to set the divide by n and initial count values The Hold register may also be required for certain counter modes such as variable duty cycle square wave functions You may optionally want to set the initial output level If you are using counters or 2 in alarm mode the alarm register must also be programmed Next load the initial count into the Count register using the Load command Finally arm or enable the counter using the Arm command To read a counter issue a Save command This stores the counter s current contents in the Hold register Then read the Hold register A counter can be armed or disarmed and its current contents can be saved at any time under software control through these commands The information below summarizes the procedure for programming a counter To set up counter operation Program the Master Mode Register Program the Counter Mode Register Load initial data into the Load Register
15. and reset A value of 1 when reading this register bit IRQASTS indicates IRQACLR IRQA interrupt occurred Write a value of 1 to this bit IRQACLR to clear the interrupt IRQADIS IRQA interrupt disable Write a value of 1 to this bit to disable the IRQA interrupt This is equivalent to the INTE bit of the Interrupt Control Register base 0Dh IRQAEN IRQA interrupt enable Write a value of 1 to this bit to enable the IRQA interrupt This is equivalent to the INTE bit of the Interrupt Control Register base 0Dh IRQBSTS IRQB interrupt status and reset A value of 1 when reading this register bit IRQBSTS indicates an IRQBCLR IRQB interrupt occurred Write a value of 1 to this bit IROBCLR to clear the interrupt IRQBDIS IRQB interrupt disable Write a value of 1 to this bit to disable the IRQB interrupt This is equivalent to the INTE bit of the Interrupt Control Register base 0Dh IRQBEN IRQB interrupt enable Write a value of 1 to this bit to enable the IRQB interrupt This is equivalent to the INTE bit of the Interrupt Control Register base 0Dh Auxiliary DIO Control and Status Register Counter timer Base OEh Bit 7 6 5 4 3 2 1 0 AUX3DIR AUX2DIR AUXIDIR AUXODIR AUX3IN AUX2IN AUXIIN AUXOIN AUX30UT AUX20UT AUXIOUT AUXOOUT AUXnIN Auxiliary DIO line Read the respective AUXnIN bit to determine the auxiliary DIO line state AUXnOUT 0 low level AUXnDIR
16. antage of its myriad features requires an understanding of its structure and operation A datasheet on the 9513 is included at the end of this manual Review pages four starting with Functional Description through 11 to understand the structure of the 9513 chip and its capabilities The various counter operating modes are described starting on page 13 A few explanatory notes are given below Accessing the Counter Timer Internal Registers The chip contains many internal registers To minimize the I O memory footprint a data pointer scheme is used to access these registers This scheme is reflected in the GPIO MM 12 board s I O map Section 5 I O Map The data pointer values are shown in the 9513 datasheet on page 8 Table 4 The appropriate data pointer value is written to the data pointer register for the chip Base 1 for chip no 1 and Base 5 for chip no 2 Then the register is accessed through the data register Base 0 for chip no and Base 4 for chip no 2 Master Mode Register Each chip contains a Master Mode Register that defines global characteristics for the chip Note the bit that controls the data bus width This should always be set to 0 for 8 bit bus access on GPIO MM 12 Counter Mode Register Each chip contains five Counter Mode Registers one for each counter This register is used to program the operating mode of the counter including input source gating method output type load reload behavior and count
17. counter behavior These may also be used as clock or count input sources for the internal counters or the FOUT divider FOUT FOUT is a general purpose auxiliary clock output derived from the 9513 input clock using a programmable divider Interrupt In External interrupt for external PC 104 bus hardware interrupt operation DOUTO0 DOUT7 Eight general purpose digital output lines DINO DIN7 Eight general purpose digital input lines 5V 5 volt DC from the PC 104 bus Ground Digital ground from the PC 104 bus Auxiliary Header Pinout The auxiliary I O header J5 is provided for bidirectional TTL level general purpose I O 1 AUXIO 0 2 AUXIO 1 3 AUXIO 2 4 AUXIO 3 5 GND Card Voltage Type Pin Configuration AUXIO 0 AUXIO 3 Four bidirectional TTL level general purpose I O signals GND Ground Diamond Systems Corporation GPIO MM 12 User Manual Page 10 Board Configuration Base Address Selection Jumper J10 positions 2 5 is used to configure the base address of the DIO 8255 registers The 8255 register map occupies 8 bytes of I O address space as described in Section 5 I O Map Jumper positions 6 9 is used to configure the base address of the counter timer I O 9513 registers and the enhanced features registers The 9513 register map occupies 16 bytes of I O address space as described in Section 5 I O Map Jumper the locations
18. d and status data register Transfers command and status data to from the register pointed to at base 01h Olh 9513 1 command and status data register pointer Address of the command and status registers for transferring the 8 bit data located at base 00h 02h 8 bit DIO data Set or read the 9513 DIO lines 03h Shadow register of base 02h 04h 9513 2 command and status data register Transfers command and status data to from the register pointed to at base 05h 05h 9513 2 command and status data register pointer Address of the command and status registers for transferring the 8 bit data located at base 04h 06h Interrupt control Enable and reset counter timer interrupts 07h Shadow register of base 06h 08h EEPROM data Data written to and read from the EEPROM 09h EEPROM address The EEPROM location for reading or writing data EEPROM control and status register Initiate EEPROM data transfer and set the data transfer direction Also indicates when valid data is available from EEPROM during a read operation OBh FPGA revision code Get the on board FPGA program revision level OCh Interrupt source selection Specify the interrupt source for IRQA IRQB Interrupt control and status Enable disable and clear IRQA IRQB interrupts and gets the IRQA IRQB interrupt status OEh Auxiliary DIO control and status Set the state of the auxiliary DIO lines and read the current DIO line s
19. direction Note that in the Gate description Gate N means the gate for the counter being programmed and Gate N 1 means the gate for the previous counter Gate N 1 is not valid for counter 1 or counter 6 on GPIO MM 12 since that corresponds to counter 1 on the second chip Counter Modes Each combination of Gate control Repetition Reload source and Special gate are given a letter mode name See the counter mode tables on page 13 of the datasheet The behavior of these modes as well as their timing diagrams are given starting on page 14 of the datasheet Please note the errata on page 12 of the datasheet FOUT Frequency Output A programmable frequency generator circuit is provided for the counter timer and is described in the 9513 datasheet It has an input source a multi stage decimal or BCD divider and a user programmable divider All options are programmed through the Master Mode Register The FOUT circuit of the 9513 1 is available on the FOUT pin on the GPIO MM 12 board s I O header Its source can be the input or gate from counters 1 5 or any of the five internal frequency dividers built into the chip and driven by the clock The FOUT circuit of the 9513 2 is not available externally Counter Commands A set of commands is used to control the counters These are described in the 9513 datasheet The Diamond Systems Universal Driver software provides full support for the various 9513 functions Diamond Systems Corporation GPIO
20. hanged Mode set flag Selects the port configuration mode 0 Bit set reset control register mode When MSFLAG is reset this register is used to set reset individual Port C bits 1 Basic mode definition control register mode Reset value When MSFLAG is set this register is used for direction and mode selection NOTE When the control word is read the value of MSFLAG is always 1 implying basic control word information is being read Diamond Systems Corporation GPIO MM 12 User Manual Page 22 8255 Control and Status Registers Bit SET RESET Mode MSFLAG 0 DIO Base 03h 8255 1 DIO Base 07h 8255 2 Bit 7 6 5 4 3 2 1 0 Name MSFLAG BSEL SET SET Bit set reset individual command 0 reset 1 BSEL Port C bit select 0 bit 0 1 bit 1 2 bit 2 3 bit 3 4 bit 4 5 bit 5 6 bit 6 7 017 MSFLAG Mode set flag Selects the port configuration mode 0 Bit set reset control register mode When MSFLAG is reset this register is used to set reset individual Port C Bits 1 Basic mode definition control register mode When MSFLAG is set this register is used for direction and mode selection NOTE When the control word is read the value of MSFLAG is always 1 implying basic control word information is being read Diamond Systems Corporation GPIO MM 12 User Manual Page 23 Programming the Counter Timer Overview To program the 9513 effectively and take adv
21. it value to the register at baset 2 or base 3 to immediately output the value to the 8 output lines When reading register base 2 or base 3 the FPGA returns the logic state of the 8 input lines Diamond Systems Corporation GPIO MM 12 User Manual Page 27 Programming Enhanced Features EEPROM Programming The EEPROM provides non volatile memory for storing application data Program the EEPROM using the following steps Repeat these steps for each data byte 1 Write the data byte to the EEPROM Data Register 08h Specify the EEPROM address 0 256 where the data is to be written by writing the address to the EEPROM Address Register 09h Set the data transfer direction to write by resetting the EE RW bit in the EEPROM Control and Status Register OAh 4 Set the EE EN bit in the EEPROM Control and Status Register 0Ah to initiate the write operation N UJ To read stored EEPROM data use the following steps Repeat these steps for each data byte 1 Specify the EEPROM address 0 256 where the data is to be read from by writing the address to the EEPROM Address Register 09h Set the data transfer direction to read by setting the RW bit in the EEPROM Control and Status Register 0Ah Reset the EN bit in the EEPROM Control and Status Register 0Ah to initiate the read operation Test the EEPROM Control and Status Register EEBUSY bit to determine that the data transfer has completed When EEBUSY is zero
22. or byte mode e interrupt line for generating interrupts to the CPU e An external 50 pin header for connecting to the counter timer features Enhanced Features e On board EEPROM for user configuration data storage e AnLED display for easy identification of FPGA personality which can also be read in a register e Interrupt source selection with counter timer DIO or external line options e Four channel auxiliary DIO for additional general purpose I O e Aregister accessible FPGA revision code for version control Software controlled board reset Diamond Systems Corporation GPIO MM 12 User Manual Page 5 Board Layout Board Drawing Figure 1 GPIO MM 12 Board Layout 3775 HEEBHHHHHHHHHHHBHHHHHHHHHHHHHHHH o HHHHHHHHHHHHHHHHHHEH es 3 550 d Diamond Systems Corporation GPIO MM 12 User Manual Page 6 I O Connector Pinout Digital I O Header Pinout Connector J4 is the 50 pin general purpose DIO interface The connector connects directly to the FPGA which implements the functionality of a 82C55A PPI chips This gives a total of 48 bidirectional DIO lines The J4 pins can be configured to pull up to 5V or pull down to ground using jumper J11 as described in Section 4 Board Configuration Line Pull up pull down Selection Port 1A7 Port 1A6 Port 1A5 Port 1A4 Port 1A3 Port 1A2 Port 1A1 Port 1A0 Port 1B7 Port 1B6 Port 1B5 Port 1B4 Port 1B3 Port 1B2 Port 1B1 Port 1BO Por
23. oration GPIO MM 12 User Manual Page 12 I O Line Pull up Pull down Selection Use jumper J8 to configure the pull up and pull down state of the counter timer header pins J3 Use jumper J11 to configure the pull up and pull down state of the DIO header pins J4 DIO pin pull up and pull down state is configured as shown in the following examples Jumper the position marked 5 to pull the J3 I O pins up to 5 VDC Figure 6 Pull I O Pins Up to 5 VDC oma IIT TT TT I gog gt 5 5 LONG gt oz AD Jumper the position marked to pull the J3 I O pins down to ground Figure 7 Pull I O Pins Down to Ground 1 e e 5 Lov e Loud Loud Lov e Loud LOY e LONO o LMOV NOTE Placing a jumper on both 5 and G simultaneously will short the 5 power plane to ground Diamond Systems Corporation GPIO MM 12 User Manual Page 13 Map Overview The register base address is determined by setting jumper J10 as described in Section 4 Board Configuration Base Address Selection Jumper pins 2 5 set the DIO base address and pins 6 9 set the counter timer base address Counter Timer and Enhanced Feature Programming Sixteen registers are used for counter timer and enhanced feature programming Offset Description 00h 9513 1 comman
24. ps e input and ten output counter timer signals Eight input and eight output TTL level signals Ten gates e Power and ground The J3 pins may be configured to pull up to 5V or pull down to ground using jumper J8 as describe in Section 4 Board Configuration Line Pull up pull down Selection In1 Gate1 Out1 In3 Gate3 Out3 In5 Gate5 In6 Gate6 Out6 In8 Gate8 Out8 In10 Gate10 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUTO 5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 112 Gate2 Out2 In4 Gate4 Out4 Out5 FOUT In7 Gate7 Out7 In9 Gate9 Out9 Out10 Interrupt In DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DINO Ground NOTE The connector is labeled Port 1 which should not be confused with DIO ports A B and C and the fixed direction TTL ports Diamond Systems Corporation GPIO MM 12 User Manual Page 9 Signal Description 11 1510 Ten external clock source lines that may be associated with one of the ten internal counters or FOUT Outl Out10 Ten tri state outputs lines associated with one of the ten internal counters These may be programmed for pulse wave or complex duty cycle waveforms Gatel GatelO Ten input lines used to control
25. pts allows background operation where I O can be performed while the PC is executing another task such as running an unrelated applications program This feature is useful for performing I O at a controlled rate since a counter output can be used to drive the interrupt request pin on the I O header at a periodic rate for a user supplied interrupt service routine that performs whatever function is necessary in response to the interrupt Digital I O Features Dual 82C55A Parallel Peripheral Interfaces PPI logic implemented in FPGA cores e Each 82 55 has three 8 bit I O ports for a total of 48 DIO lines which connect to a 50 pin header for external connections e Port direction and operation is selected through software programmable control registers All lines are buffered with transceivers Counter Timer Features e Dual CTS9513 counter timers logic implemented in FPGA cores e A 40MHz clock input providing higher precision timer functions e Ten 16 bit programmable up down counters with sophisticated timing logic e Up or down counting e Binary or BCD counting e Single or repetitive counting e Edge or level gating Output pulse or toggle capability Diamond Systems Corporation GPIO MM 12 User Manual Page 4 e Alarm comparator circuitry e Software or hardware retriggering Timing functions are software programmable using control registers e 8 6 TTL input and 8 bit TTL output ports which can operate in bit
26. put 0 This is equivalent to the IRQAEN IRQBEN and IRQADIS IRQBDIS bits of the Interrupt Control Status Register base 0Dh EEPROM Data Register Counter timer Base 08h Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 DO D7 D0 Writing to this register writes data to the EEPROM at the address specified by the EEPROM Address Register base 09h Reading from this register returns the EEPROM data at the EEPROM Address Register base 09h location read data is valid when EEBUSY 0 in the EEPROM Status Register base 0Ah EEPROM Address Register Counter timer Base 09h Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 Al AO A0 A7 EEPROM address This register specifies the EEPROM address to read write the data in the EEPROM Data Register baset 08h The address range 15 0 to 256 Diamond Systems Corporation GPIO MM 12 User Manual Page 17 EEPROM Control and Status Register Counter timer BasetOAh Bit 7 6 5 4 3 2 1 0 Name EE EN EE RW EEBUSY EEBUSY EEPROM busy status indicator When reading data from the EEPROM the data is valid when this bit indicates the EEPROM is not busy 0 EEPROM is not busy 1 EEPROM is busy Wait before accessing EEPROM EE RW EEPROM data transfer direction Read or write the EEPROM at the EEPROM address in the Address Register base 09h 0 Write 1 Read EE EN EEPROM enable
27. t 1C7 Port 1C6 Port 1C5 Port 1C4 Port 1C3 Port 1C2 Port 1C1 Port 1CO 5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Port 2A7 Port 2A6 Port 2A5 Port 2A4 Port 2A3 Port 2A2 Port 2A1 Port 2A0 Port 2B7 Port 2B6 Port 2B5 Port 2B4 Port 2B3 Port 2B2 Port 2B1 Port 280 Port 2C7 Port 2C6 Port 2C5 Port 2C4 Port 2C3 Port 2C2 Port 2C1 Port 2 Ground NOTE The connector is labeled Port 2 which should not be confused with DIO ports A B and C and the fixed direction TTL ports Diamond Systems Corporation GPIO MM 12 User Manual Page 7 Signal Description Port 1A0 Port 1A7 8255 1 Port A bits 0 7 Port 1B0 Port 1B7 8255 1 Port B bits 0 7 Port 1C0 Port 1C7 8255 1 Port C bits 0 7 Port 2A0 Port 2A7 8255 2 Port A bits 0 7 Port 2B0 Port 2B7 8255 2 Port B bits 0 7 Port 2C0 Port 2C7 8255 2 Port C bits 0 7 5V 5 volt DC from the PC 104 bus Ground Digital ground from the PC 104 bus Diamond Systems Corporation GPIO MM 12 User Manual Page 8 Counter timer Header Pinout Connector J3 is the 50 pin counter timer interface The connector connects directly to the FPGA which implements the functionality of two CTS9513 counter timer chi
28. tate OFh Board reset and board ID code Reset the board or get the FPGA personality ID code Diamond Systems Corporation GPIO MM 12 User Manual Page 14 DIO Programming Eight registers are used for DIO programming Offset Description 00h 8255 1 port A DIO register Olh 8255 1 port B DIO register 02h 8255 1 port C DIO register 03h 8255 1 control and status register 04h 8255 2 port A DIO register 05h 8255 2 port B DIO register 06h 8255 2 port C DIO register 07h 8255 2 control and status register Diamond Systems Corporation GPIO MM 12 User Manual Page 15 Register Bit Descriptions Refer to the I O Map for counter timer and DIO register sets 9513 Command and Status Data Counter timer Base 00h 9513 1 Base 04h 9513 2 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 DI DO D7 DO Counter timer command and status data for the 9513 These data are written to or read from the counter timer command and status register at the location specified by the command and status register pointer base 01h Refer to the 9513 data sheet Additional Information for a description of the command and status registers 9513 Command and Status Data Pointer Registers Counter timer Base 01h 9513 1 Base 05h 9513 2 Bit 7 6 5 4 3 2 1 0 Name PTR PTR Counter timer command and status register pointer
29. tor March 1997 Diamond Systems Corporation GPIO MM 12 User Manual Page 30 Technical Support For technical support please email support diamondsystems com or contact Diamond Systems Corporation technical support at 1 650 810 2500 Diamond Systems Corporation GPIO MM 12 User Manual Page 31
30. y implements operating mode 0 which provides simple bidirectional I O without handshaking Port C bits may be individually set and reset by setting the MSFLAG in the 8255 Control and Status Register and programming the remaining register bits for the desired bit state Setting the 8255 Control and Status Register to the following values gives 16 possible I O configurations Status and Control Register Bits Group A Group B PADIR PCUDIR PBDIR PCLDIR Port A PortB Port C upper lower 0 0 0 0 Output Output Output Output 0 0 0 1 Output Output Output Input 0 0 1 0 Output Output Input Output 0 0 1 1 Output Output Input Input 0 1 0 0 Output Input Output Output 0 1 0 1 Output Input Output Input 0 1 1 0 Output Input Input Output 0 1 1 1 Output Input Input Input 1 0 0 0 Input Output Output Output 1 0 0 1 Input Output Output Input 1 0 1 0 Input Output Input Output 1 0 1 1 Input Output Input Input 1 1 0 0 Input Input Output Output 1 1 0 1 Input Input Output Input 1 1 1 0 Input Input Input Output 1 1 1 1 Input Input Input Input Diamond Systems Corporation GPIO MM 12 User Manual Page 26 16 bit Fixed Direction 9513 Connector J3 has 8 fixed TTL inputs and 8 fixed TTL outputs The outputs are set by writing to base 2 or 3 See 9513 DIO Data Registers Write an 8 b
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