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1. Selected Devic 2v40cs144 6 Number of Slices 23 out of 256 8 Number of Slice Flip Flops 14 out of 512 25 Number of 4 input LUTs 42 out of 512 8 Number of bonded IOBs 26 out of 88 29 Number of GCLKs 1 out of 16 6 TIMING REPOR NOTE THESE IMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO HE TRACE REPORT GENERATED AFTER PLACE and ROUTE Clock Information Clock Signal Clock buffer FF name Load CLK BUFGP 14 Timing Summary Speed Grade 6 XST User Guide www xilinx com 1 800 255 7778 341 7 XILINX Chapter 9 Log File Analysis Minimum period 2 657ns Maximum Frequency 376 364MHz Minimum input arrival time before clock 2 055ns Maximum output required time after clock 6 697ns Maximum combinational path delay 6 214ns Timing Detail All values displayed in nanoseconds ns Timing constraint Default period analysis for Clock CLK Delay 2 657ns Levels of Logic 2 Source sixty lsbcount qoutsig 1 FF Destination sixty msbcount qoutsig 3 FF Source Clock CLK rising Destination Clock CLK rising Data Path sixty lsbcount qoutsig 1 to sixty msbcount qoutsig 3 Gate Net Cell in out fanout Delay Delay Logical Name Net Name FDCE C gt Q 11 0 449 0 671 sixty_lsbcount_qoutsig_1 si
2. read through IO Pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Write Address Primary Read Address dpra Dual Read Address di Data Input spo Primary Output Port dpo Dual Output Port VHDL Following is the VHDL code for a dual port RAM with synchronous read read through library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk we a dpra di spo dpo i end raminfr 140 in std_logic std_logic std_logic_vector 4 downto 0 std_logic_vector 4 downto 0 std_logic_vector 3 downto 0 out std logic vector 3 downto 0 out std logic vector 3 downto 0 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_a std_logic_vector 4 downto 0 signal read_dpra std_logic_vector 4 downto 0 begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if read_a lt a read_dpra lt dpra end if end process spo lt RAM conv_integer read_a dpo lt RAM conv_integer read_dpra end syn Verilog Following is the Verilog code for a dual port RAM with synchronous read read through module raminfr clk we a dpra di spo dpo input clk
3. always G8 posedge C or posedge PRE begin if PRE Q 4 b1111 else if CE Q D end endmodule Latches XST can recognize latches with the asynchronous set clear control signals Latches can be described using e Process VHDL and always block Verilog e Concurrent state assignment 46 www xilinx com XST User Guide 1 800 255 7778 Registers 7 XILINX Log File The XST log file reports the type and size of recognized latches during the Macro Recognition step Synthesizing Unit lt latch gt Related source file is latch l vhd WARNING Xst 737 Found 1 bit latch for signal lt q gt Summary inferred 1 Latch s Unit latch synthesized HDL Synthesis Report Macro Statistics Latches 1 bit latch Related Constraints A related constraint is IOB Latch with Positive Gate The following figure shows a latch with a positive gate D LD X3740 The following table shows pin definitions for a latch with a positive gate 10 Pins Description D Data Input G Positive Gate Q Data Output XST User Guide www xilinx com 47 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the equivalent VHDL code for a latch with a positive gate library ieee use ieee std logic 1164 a11 entity latch is port G D in std logic Q out std logic 3 end latch architecture archi
4. 344 www xilinx com XST User Guide 1 800 255 7778 CPLD Log File Z XILINX Compiling vhdl file c users doc granite timer ise stopwatch vhd in Library work Entity lt stopwatch gt Architecture lt inside gt compiled HDL Analysis Analyzing Entity lt stopwatch gt Architecture lt inside gt WARNING Xst 766 c users doc granite timer ise stopwatch vhd line 68 Generating a Black Box for component lt tenths gt Entity stopwatch analyzed Unit stopwatch generated Analyzing Entity lt statmach gt Architecture lt inside gt Entity statmach analyzed Unit statmach generated Analyzing Entity decode Architecture lt behavioral gt Entity decode analyzed Unit decode generated Analyzing Entity lt cnt60 gt Architecture lt inside gt Entity lt cnt60 gt analyzed Unit lt cnt60 gt generated Analyzing Entity lt smallcntr gt Architecture lt inside gt Entity lt smallcntr gt analyzed Unit lt smallcntr gt generated Analyzing Entity hex2led Architecture lt hex2led_arch gt Entity lt hex2led gt analyzed Unit lt hex2led gt generated HDL Synthesis Synthesizing Unit lt smallcntr gt Related source file is c users doc granite timer ise smallcntr vhd Found 4 bit up counter for signal lt qoutsig gt Summary inferred 1 Counter s Unit lt smallcntr gt synthesized
5. IO Pins Description D Data Input C Positive Edge Clock Q Data Output VHDL Code Following is the equivalent VHDL code sample for the flip flop with a positive edge clock library ieee use ieee std logic 1164 all entity flop is port C D in std logic Q out std logic end flop architecture archi of flop is begin process C begin if C event and C 1 then Q lt D end if end process end archi When using VHDL for a positive edge clock instead of using if C event and C 1 then you can also use if rising edge C then 40 www xilinx com XST User Guide 1 800 255 7778 Registers 7 XILINX Verilog Code Following is the equivalent Verilog code sample for the flip flop with a positive edge clock module flop C D Q input C D output 0 reg Q always posedge C begin Q D end endmodule Flip flop with Negative Edge Clock and Asynchronous Clear The following figure shows a flip flop with negative edge clock and asynchronous clear The following table shows pin definitions for a flip flop with negative edge clock and asynchronous clear IO Pins Description D Data Input C Negative Edge Clock CLR Asynchronous Clear active High Q Data Output XST User Guide www Xilinx com 41 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the equivalent VHDL code for a flip flop with a negative
6. IO pins Description A 7 0 B 7 0 Add Operands SUM 7 0 Add Result CO Carry Out VHDL Following is the VHDL code for an unsigned 8 bit adder with carry out library ieee use ieee std_logic_1164 all use ieee std logic arith all use ieee std logic unsigned all 104 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations entity adder is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 CO out std logic end adder architecture archi of adder is signal tmp std logic vector 8 downto 0 begin tmp lt conv std logic vector conv integer A SUM tmp 7 downto 0 CO lt tmp 8 end archi In the preceding example two arithmetic packages are used conv integer B 9 7 XILINX e std logic arith This package contains the integer to std logic conversion function that is conv std logic vector e std logic unsigned This package contains the unsigned Verilog Following is the Verilog code for an unsigned 8 bit adder with carry out module adder A B SUM CO input 7 0 A input 7 0 B output 7 0 SUM output CO wire 8 0 tmp assign tmp A B assign SUM tmp 7 0 assign CO tmp 8 endmodule Unsigned 8 bit Adder with Carry In and Carry Out operation The following table shows pin descriptions for an unsigned 8 bit adder with carry in and carry out 10 pin
7. library ieee use ieee std_logic_1164 all entity and_two is port A B in std logic REZ out std logic attribute LUT MAP string attribute LUT MAP of and two entity is yes end and two architecture beh of and two is begin REZ A or B end beh library ieee use leee std_logic_1164 all entity top is port A B C in std logic REZ out std logic end top www xilinx com XST User Guide 1 800 255 7778 Specifying INITs and RLOCs in HDL Code 7 XILINX architecture beh of top is component and_one port A B in std logic REZ out std logic end component component and two port A B in std logic REZ out std logic i end component signal tmp std_logic begin inst_and_one and_one port map A gt A B gt B REZ gt tmp inst_and_two and_two port map A gt tmp gt C REZ gt REZ end beh If a function cannot be mapped on a single LUT XST issues an Error and interrupts the synthesis process If you would like to define an INIT value for a flip flop described at RTL level you can assign its initial value in the signal declaration stage This value is not ignored during synthesis and is propagated to the final netlist as an INIT constraint attached to the flip flop This feature is supported for registers only It is not supported for RAM descriptions In the following VHDL example a 4 bit register is inferred
8. www xilinx com 1 800 255 7778 297 XILINX 298 Blocks Modules Chapter 7 Verilog Language Support Block statements are used to group statements together XST only supports sequential blocks Within these blocks the statements are executed in the order listed Parallel blocks are not supported by XST Block statements are designated by begin and end keywords and are discussed within examples later in this chapter In Verilog a design component is represented by a module The connections between components are specified within module instantiation statements Such a statement specifies an instance of a module Each module instantiation statement must be given a name instance name In addition to the name a module instantiation statement contains an association list that specifies which actual nets or ports are associated with which local ports formals of the module declaration All procedural statements occur in blocks that are defined inside modules There are two kinds of procedural blocks the initial block and the always block Within each block Verilog uses a begin and end to enclose the statements Since initial blocks are ignored during synthesis only always blocks are discussed Always blocks usually take the following format always begin statement end where each statement is a procedural assignment line terminated by a semicolon Module Declaration In the module declaration the I O ports of
9. 00 coco 174 Macro Generation 175 Arithmetic Functions 0 000000 ccc e es 175 Loadable Functions ssi ccc caine tad annedir actin e it eu ev alacer 175 Multiplexers laos S ek PAR a Hk eed thee eee igi a ed a let 176 Priority Encoder v hae oh E tau eU d ug uu MCN 176 Decoder urticaria orita e ee iaee e ea aie alcatel al ees etes 176 Shift Rep ister suse pu epean Eva c der UU Lese quet 177 RAMIS eon hU centem Seton ii Ben aes UR Sn E E add uM E 177 ROMS oia di a a a dd aii da a 178 Mapping Logic onto Block RAM sssss sse 179 ipM cc 180 14 www xilinx com XST User Guide 1 800 255 7778 XILINX VENDO Guiso A a Me Soe 180 LOG cede eee AA A AA a 181 VAD Escondida daba ala Eu Ea 181 VERILOG ida ide a ita ie ls dia 182 LOGS a cet eae a EM IM Mf do 182 A A E FIL Tua 183 Incremental Synthesis Flow suus eee 183 INCREMENTAL SYNTHESIS lesse RR RR e es 184 Example crede Ee A datei ee dee apodo 184 RESYNTHESIZE uitae hene et ure RS daa cia 185 VHIOL ElOW bid dr xr eed dedu e Deed bec dr oe dest 185 Merlo duc d 185 Speed Optimization Under Area Constraint usuueueuuusuuueuuueue 187 Log File A alysiS iii eH CORR d eer A Eb ec ao d 189 Design Optimization i e cem cee a ere Re eee pm ERR ERE ER EE Yers 189 Resource Usage iue ii res v eee he ee bete n eed pesos 190 Device Utilization summary sssslsseess n 191 Clock Information mii n od 191 Tuning Report
10. Target Parameters Output File Name stopwatch Output Format NGC Target Device xbr Source Options Top Module Name stopwatch Automatic FSM Extraction YES FSM Encoding Algorithm Auto Mux Extraction YES Resource Sharing YES Target Options Add IO Buffers YES Equivalent register Removal YES MACRO Preserve YES XOR Preserve YES General Options Optimization Goal Speed Optimization Effort 1 Keep Hierarchy YES RTL Output Yes Hierarchy Separator M Bus Delimiter lt gt Case Specifier maintain Other Options lso stopwatch lso verilog2001 YES Clock Enable YES wysiwyg NO ji HDL Compilation Compiling vhdl file c users doc granite timer ise smallcntr vhd in Library work Entity lt smallcntr gt Architecture lt inside gt compiled Compiling vhdl file c users doc granite timer ise statmach vhd in Library work Entity lt statmach gt Architecture lt inside gt compiled Compiling vhdl file c users doc granite timer ise decode vhd in Library work Entity lt decode gt Architecture lt behavioral gt compiled Compiling vhdl file c users doc granite timer ise cnt60 vhd in Library work Entity cnt60 Architecture inside compiled Compiling vhdl file c users doc granite timer ise hex2led vhd in Library work ntity lt HEX2LED gt Architecture HEX2LED arch compiled E
11. This is shown in the following example define myzero 0 assign mysig myzero Verilog provides the ifdef and endif constructs to determine whether a macro is defined or not These constructs are used to define conditional compilation If the macro called out by the ifdef command has been defined that code is compiled If not the code following the else command is compiled The else is not required but the endif must complete the conditional statement The ifdef and endif constructs are shown in the following example ifdef MYVAR module if MYVAR is declared endmodule else module if MYVAR is not declared endmodule endif Include Files Verilog allows separating source code into more than one file To use the code contained in another file the current file has the following syntax include path file name to be included Note The path can be relative or absolute 308 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features Z XILINX Multiple include statements are allowed in a single Verilog file This is a great feature to make code modular and manageable in a team design environment where different files describe different modules of the design If files are referenced by an include statement they must not be manually added to the project For example at the top of a Verilog file you might see this timescale 1ns lps include modules v I
12. begin if sel 1 if sel 0 outmux d else outmux c else if sel 0 outmux b else outmux a end endmodule Case Statement Case statements perform a comparison to an expression to evaluate one of a number of parallel branches The Case statement evaluates the branches in the order they are written The first branch that evaluates to true is executed If none of the branches match the default branch is executed Note Do not use unsized integers in case statements Always size integers to a specific number of bits or results can be unpredictable Casez treats all z values in any bit position of the branch alternative as a don t care Casex treats all x and z values in any bit position of the branch alternative as a don t care The question mark can be used as a don t care in any of the preceding case statements The following example shows how a MUX can be described using a Case statement www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features 7 XILINX Example 7 3 MUX Description Using Case Statement module mux4 sel a b C d outmux input 1 0 sel input L70 a Dye d output 1 0 outmux reg 1 0 outmux always sel or a or b or c or d begin case sel 2 b00 outmux a 2 b01 outmux b 2 b10 outmux c default outmux d endcase end endmodule The preceding Case statement evaluates the values of the input sel in priority order To avoid pr
13. Selecting encoding for FSM_0 Encoding for FSM 0 is Gray flip flop D Low Level Synthesis Optimizing unit stopwatch Optimizing unit lt statmach gt Optimizing unit decode Optimizing unit lt hex2led gt Optimizing unit lt smallcntr gt Optimizing unit lt cnt60 gt 346 www xilinx com XST User Guide 1 800 255 7778 CPLD Log File Z XILINX Final Report id Final Results RTL Top Level Output File Name stopwatch ngr Top Level Output File Name stopwatch Output Format NGC Optimization Goal Speed Keep Hierarchy YES Target Technology xbr Macro Preserve YES XOR Preserve YES Clock Enable YES wysiwyg NO Design Statistics IOs o24 Macro Statistics Registers 8 1 bit register 8 Xors 6 1 bit xor2 6 Cell Usage BELS 361 AND2 135 AND3 25 INV 143 OR2 52 XOR2 6 FlipFlops Latches 11 FDC 3 FDCE 8 IO Buffers So md IBUF s OBUF 24 Others sod tenths gt a CPU 7 50 9 66 s Elapsed 7 00 9 00 s Total memory usage is 62936 kilobytes XST User Guide www xilinx com 347 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis 348 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode This chapter describes how to run XST using the command line The chapter contains the following sections Introduction Introduction Launching XST Setting Up an
14. Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xlnx xil tt home jsp Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold Total command men dd ngdbuild design_name enter in a syntactical statement Sided that you select File gt Open Helvetica bold alee Keyboard shortcuts Ctrl C 6 www xilinx com XST User Guide 1 800 255 7778 Conventions XILINX Convention Italic font Meaning or Use Variables in a syntax statement for which you must supply values Example ngdbuild design name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option name design name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on
15. always posedge C begin if CE Q D end endmodule 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable The following figure shows a 4 bit register with positive edge clock asynchronous set and clock enable PRE 8 FDPE CE y The following table shows pin definitions for a 4 bit register with positive edge clock asynchronous set and clock enable IO Pins Description D 3 0 Data Input C Positive Edge Clock PRE Asynchronous Set active High CE Clock Enable active High Q 3 0 Data Output XST User Guide www xilinx com 45 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the equivalent VHDL code for a 4 bit register with a positive edge clock asynchronous set and clock enable library ieee use ieee std logic 1164 all entity flop is port C CE PRE in std logic D in std logic vector 3 downto 0 O out std_logic_vector 3 downto 0 end flop architecture archi of flop is begin process C PRE begin if PRE 1 then Q lt II elsif C event and C 1 then if CE 1 then Q lt D end if end if end process end archi Verilog Code Following is the equivalent Verilog code for a 4 bit register with a positive edge clock asynchronous set and clock enable module flop C D CE PRE OQ input C CE PRE input 3 0 D output 3 0 Q reg 3 0 Q
16. IT IIE 3 Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS XST User Guide www xilinx com 245 1 800 255 7778 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options Command Command XCF XCF Line Line Constraint Constraint Constraint cmd i Technology Name Suntax Suntax Line Old XST Old XST aac zd et Constraint Constraint 9 Syntax Syntax Value Target vlgcase na na yes full parallel na Spartan IT TIE 3 full parallel Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 ITI IIS vlgincdir na na yes dir path na Spartan I IIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 ITI IIS vlgpath na na yes dir path na Spartan I IIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 ITI IIS wysiwyg na na yes yes no na XC9500 CoolRunner XPLA3 II IIS xsthdpdir directory_path na yes directory_path na Spartan IT IIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 ITI IIS xsthdpini file name na yes file name na Spartan I IIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 ITI IIS 246 www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX The following table shows the timing constraints supported by XST that you can invoke only from the command line or the Process Properties dialog box i
17. Introduction XST User Guide This chapter explains how VHDL is supported for XST The chapter provides details on the VHDL language supported constructs and synthesis options in relationship to XST The sections in this chapter are as follows e Introduction e Data Types in VHDL e Record Types e Tnitial Values e Objects in VHDL e Operators e Entity and Architecture Descriptions e Combinatorial Circuits e Sequential Circuits e Functions and Procedures e Assert Statement e Packages e VHDL Language Support e VHDL Reserved Words For a complete specification of the VHDL hardware description language refer to the IEEE VHDL Language Reference Manual For a detailed description of supported design constraints refer to Chapter 5 Design Constraints For a description of VHDL attribute syntax see the VHDL Attribute Syntax in Chapter 5 VHDL is a hardware description language that offers a broad set of constructs for describing even the most complicated logic in a compact fashion The VHDL language is designed to fill a number of requirements throughout the design process e Allows the description of the structure of a system how it is decomposed into subsystems and how those subsystems are interconnected e Allows the specification of the function of a system using familiar programming language forms www xilinx com 255 1 80
18. Language Templates Multiplexers 4 to 1 1 bit MUX using IF Statement 4 to 1 MUX Using CASE 4 to 1 MUX Design with CASE Statement Statement 4 to 1 MUX Using Tristate 4 to 1 MUX Design with Tristate Buffers Construct No 4 to 1 MUX Decoders VHDL One Hot 1 of 8 Decoder Synchronous Verilog One Hot VHDL One Cold Verilog One Cold with Reset Priority Encoders 3 Bit 1 of 9 Priority Encoder 8 to 3 encoder Synchronous with Reset Logical Shifters Example 1 None Example 2 Example 3 Dynamic Shifters 16 bit Dynamic Shift None Register with Positive Edge Clock Serial In and Serial Out www xilinx com 1 800 255 7778 XST User Guide Introduction XST User Guide lt XILINX Table 2 1 VHDL and Verilog Examples and Templates Macro Blocks Arithmetic Operators Chapter Examples Unsigned 8 bit Adder Unsigned 8 bit Adder with Carry In Unsigned 8 bit Adder with Carry Out Unsigned 8 bit Adder with Carry In and Carry Out Simple Signed 8 bit Adder Unsigned 8 bit Subtractor Unsigned 8 bit Adder Subtractor Unsigned 8 bit Greater or Equal Comparator Unsigned 8x4 bit Multiplier Division By Constant 2 Resource Sharing Language Templates N Bit Comparator Synchronous with Reset www xilinx com 1 800 255 7778 37 7 XILINX Chapter 2 HDL Coding Techniques Table 2 1 WHDL and Verilog Examples and Templates Macro Bloc
19. Moreover you must adhere to the following conditions when writing your HDL code e Use only logical arithmetic and rotate shift operations Shift operations that fill vacated positions with values from another signal are not recognized e For VHDL you can only use predefined shift sll srl rol etc or concatenation operations Please refer to the IEEE VHDL language reference manual for more information on predefined shift operations e Use only one type of shift operation e Then value in the shift operation must be incremented or decremented only by 1 for each consequent binary value of the selector XST User Guide www xilinx com 97 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques e Then value can be only positive e All values of the selector must be presented Log File The XST log file reports the type and size of a recognized logical shifter during the Macro Recognition step Synthesizing Unit lt lshift gt Related source file is Logical Shifters l vhd Found 8 bit shifter logical left for signal so Summary inferred 1 Combinational logic shifter s Unit lt lshift gt synthesized HDL Synthesis Report Macro Statistics Logic shifters 8 bit shifter logical left zd Related Constraints A related constraint is SHIFT EXTRACT Example 1 The following table shows pin descriptions for a logical shifter IO pins Description D 7 0 Dat
20. Timing Constraints vs Non timing Constraints From a UCF syntax point of view all constraints supported by XST can be divided into two groups timing constraints and non timing constraints For all non timing constraints use the MODEL or BEGIN MODEL END constructs This is true for pure XST constraints such as F5M EXTRACT or RAM STYLE as well as for implementation non timing constraints such as RLOC or KEEP For timing constraints such as PERIOD OFFSET TNM NET TIMEGRP TIG FROM TO etc use native UCF syntax which includes the use of wildcards and hierarchical names Do not use these constraints inside the BEGIN MODEL END construct otherwise XST issues an error IMPORTANT If you specify timing constraints in the XCF file Xilinx strongly suggests that you use character as a hierarchy separator instead of Please refer to Hierarchy Separator for details on its usage www xilinx com XST User Guide 1 800 255 7778 Old XST Constraint Syntax Z XILINX Limitations XCF syntax has the following limitations Nested model statements are not supported in the current release Instance or signal names listed between the BEGIN MODEL statement and the END statement are only the ones visible inside the entity Hierarchical instance or signal names are not supported Wildcards in instance and signal names are not supported except in timing constraints Not all timing constraints are supported in the cu
21. always posedge clk begin if en begin if we ram a lt di read a lt a end end assign do ram read a endmodule Dual Port RAM with Asynchronous Read The following example shows where the two output ports are used It is directly mappable onto Distributed RAM only Distributed SPO DPO X8980 136 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Z XILINX The following table shows pin descriptions for a dual port RAM with asynchronous read 10 pins Description clk Positive Edge Clock we Synchronous Write Enable active High a Write Address Primary Read Address dpra Dual Read Address di Data Input spo Primary Output Port dpo Dual Output Port VHDL Following is the VHDL code for a dual port RAM with asynchronous read library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std logic we in std logic a in std logic vector 4 downto 0 dpra in std logic vector 4 downto 0 di in std logic vector 3 downto 0 spo out std logic vector 3 downto 0 dpo out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if end if end process Sp
22. 1 then outmux lt c else outmux d end if end if end process end behavior Case Statement Case statements perform a comparison to an expression to evaluate one of a number of parallel branches The case statement evaluates the branches in the order they are written the first branch that evaluates to true is executed If none of the branches match the default branch is executed Example 6 13 shows the use of a Case statement Example 6 13 MUX Description Using the Case Statement library IEEE use IEEE std logic 1164 a11 entity mux4 is port a b c d in std logic vector 7 downto 0 sel in std logic vector 1 downto 0 outmux out std logic vector 7 downto 0 end mux4 XST User Guide www xilinx com 271 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support architecture behavior of mux4 is begin process a b C d sel begin case sel is when 00 gt outmux lt a when 01 gt outmux lt b when 10 gt outmux lt c when others gt outmux lt d case statement must be complete end Case end process end behavior For Loop Statement The for statement is supported for Constant bounds Stop test condition using operators lt lt gt or gt Next step computation falling in one of the following specifications var var step var var step where var is the loop variable and step is
23. 218 Chapter 5 Design Constraints to define the entity module that the constraint is applied to If a constraint is applied to an entity module the constraint is applied to each instance of the entity module In general users should define constraints within the ISE process properties dialog box or the XST run script if running on the command line then use the XCF file to specify exceptions to these general constraints The constraints specified in the XCF file are applied ONLY to the module listed and not to any submodules below it To apply a constraint to the entire entity module use the following syntax MODEL entityname constraintname constraintvalue Examples MODEL top mux extract false MODEL my design max fanout 256 Note f the entity my design is instantiated several times in the design the max_fanout 256 constraint is applied to each instance of my design To apply constraints to specific instances or signals within an entity module use the INST or NET keywords BEGIN MODEL entityname INST instancename constraintname constraintvalue NET signalname constraintname constraintvalue END Examples BEGIN MODEL crc32 INST stopwatch opt mode area NST U2 ram style block ET myclock clock buffer true ET data in iob true I N N END See Constraints Summary for the complete list of synthesis constraints that you can apply for XST
24. 2d ali de Ue Oe rj RN PAR Re Gowen eRe uh 191 Timing Summary 2 42e bee A e dee E peel dd t eerta 192 Timing Detail usse dre eei petes dto eden ded teed et ceti tts 2 193 Implementation Constraints 0 193 Virtex Primitive Support iris its sees 193 VAD ereire r a Herds bake des eae oe a 195 VOTO puro hber a E abe dK ESN Eble okt Poe DEE 196 Log FUNG PD 196 Related Constraints ii A ae ME C d i eed 196 Cures Process asis id ober DAE do Ee ee ARA 196 Specifying INITs and RLOCs in HDL Code ssussus 198 ANA A E 200 Chapter 4 CPLD Optimization CPLD Synthesis Opens reed ra datae e ede na Ra o B Dedi di 203 Introduction iia eeR OI neret ada det et deese A AA 203 Global CPLD Synthesis Options sssssssesssssss e 203 Familjes ea tt Eia tton dete ee da tete e oed 203 bist of OpLODS 3 24 roster oo ew acd sete a use Grade Gents ats 204 Implementation Details for Macro Generati0N oooooooccocccccccncccoo 204 Log File Analysis s cio aca sue kbdrecata er khe ea Katar edet aR bd ars 205 Constraints e Ur 207 Improving Results crecer ke eR ek Pe o RR d n n 207 How to Obtain Better Frequency sssssssesseseeee eee 207 How to Fit a Large Design ooooooocoocccccorcran rr 208 Chapter 5 Design Constraints Inftod ctlion occis Ai a 209 Setting Global Constraints and Options 0 0c cee e eee 210 Synthesis Options sig eret
25. Design Constraints for more information Arithmetic Functions For Arithmetic functions XST provides the following elements e Adders Subtracters and Adder Subtracters e Cascadable Binary Counters e Accumulators e ncrementers Decrementers and Incrementer Decrementers e Signed and Unsigned Multipliers XST uses fast carry logic MUXCY to provide fast arithmetic carry capability for high speed arithmetic functions The sum logic formed from two XOR gates is implemented using LUTs and the dedicated carry XORs XORCY In addition XST benefits from a dedicated carry ANDs MULTAND resource for high speed multiplier implementation Loadable Functions XST User Guide For Loadable functions XST provides the following elements e Loadable Up Down and Up Down Binary Counters e Loadable Up Down and Up Down Accumulators XST can provide synchronously loadable cascadable binary counters and accumulators inferred in the HDL flow Fast carry logic is used to cascade the different stages of the www xilinx com 175 1 800 255 7778 XILINX 176 Chapter 3 FPGA Optimization macros Synchronous loading and count functions are packed in the same LUT primitive for optimal implementation For Up Down counters and accumulators XST uses the dedicated carry ANDs to improve the performance Multiplexers For multiplexers the Macro Generator provides the following two architectures e MUXFx based multiplexers e Ded
26. Flip flop with Positive Edge Clock and Clock Enable oooooooooommmoo 44 bus rr 44 Verilog Codes seais bases cibi teen tees 45 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable 45 VEDE Code tarda btt a di epa 46 Verilog Codes za ia tete ates A A A petto grate 46 XST User Guide www xilinx com 1 800 255 7778 lt XILINX DatcheSs sche a reenact edi U de oe ove ote ira 46 Log lA em 47 Related Constraints se rsss e240 resgate a Uu RAE RAE dA es 47 Latch with Positive Gate o o ooooooo ehh hrs 47 Latch with Positive Gate and Asynchronous Clear sees 48 4 bit Latch with Inverted Gate and Asynchronous Preset oooooooocooommoom 50 VHDL Cod eses asada ams REGAT ri keane ban sedan CEN EAS 50 Verilog Code std di id ii ia 50 Tristates iii iii di ed dis lr iii 51 LOS FIle ia 51 Related Constraints it ee oe ee 51 Description Using Combinatorial Process and Always Block 52 VADL Code iio db eck Sl Ee do ha be eoe hE dee aro ee 52 Verilog COG aii a 53 Description Using Concurrent AssignMenNt oooococccccoccnorrrrcro 53 VIDE Code dida 53 Verilog Codi id irap asd 53 Co nletS c voe FERRO Yee E onda ob eae eae UR REY PRESS art 54 Log Pie is O Acte 54 Related Constraimmts Vias Ee A va PRA EE NS 54 4 bit Unsigned Up Counter with Asynchronous Clear oooooocococococcccc o 55 VADC Code 4 rt dt EA a rel ia 55 Verilog Code i sud odor
27. Following is the Verilog code for an 8 bit shift left register with a positive edge clock a synchronous parallel load a serial in and a serial out module shift C SLOAD SI D SO input C SI SLOAD input 7 0 D output S0 reg 7 0 tmp always G posedge C begin if SLOAD tmp D else begin tmp tmp 6 0 SI end end assign SO tmp 7 endmodule 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out Note For this example XST does not infer an SRL16 The following table shows pin definitions for an 8 bit shift left shift right register with a positive edge clock a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In LEFT RIGHT Left right shift mode selector PO 7 0 Parallel Output XST User Guide www xilinx com 79 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for an 8 bit shift left shift right register with a positive edge clock a serial in and a serial out library ieee use ieee std logic 1164 all entity shift is port C SI LEFT RIGHT in std logic PO out std logic vector 7 downto 0 end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then if LEFT RIGHT 0 then tmp lt tmp 6 downto 0 SI else tmp lt SI tmp 7 do
28. Synthesizing Unit lt hex2led gt Related source file is c users doc granite timer ise hex2led vhd Found 16x7 bit ROM for signal lt LED gt Summary inferred 1 ROM s Unit lt hex2led gt synthesized Synthesizing Unit lt cnt60 gt Related source file is c users doc granite timer ise cnt60 vhd Unit lt cnt60 gt synthesized Synthesizing Unit decode Related source file is c users doc granite timer ise decode vhd Found 16x10 bit ROM for signal one hot Summary inferred 1 ROM s Unit lt decode gt synthesized XST User Guide www xilinx com 345 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis Synthesizing Unit lt statmach gt Related source file is c users doc granite timer ise statmach vhd Found finite state machine FSM 0 for signal current state States 6 Transitions 11 Inputs di Outputs 2 Reset type asynchronous Encoding automatic State register d flip flops Summary inferred 1 Finite State Machine s Unit lt statmach gt synthesized Synthesizing Unit lt stopwatch gt Related source file is c users doc granite timer ise stopwatch vhd WARNING Xst 646 Signal lt strtstopinv gt is assigned but never used Unit lt stopwatch gt synthesized HDL Synthesis Report Macro Statistics FSMs ROMs 16x7 bit ROM 16x10 bit ROM Counters 4 bit up counter NN e m w e Advanced HDL Synthesis K
29. Verilog Reserved Keywords The following table shows the Verilog reserved keywords 322 Chapter 7 Verilog Language Support Table 7 11 Verilog Reserved Keywords always end ifnone not rnmos tri and endcase incdir notifO rpmos tri0 assign endconfig include notif1 rtran tril automatic endfunction initial Or rtranif0 triand begin endgenerate inout output rtranif1 trior buf endmodule input parameter scalared trireg bufif0 endprimitive instance pmos show use cancelled bufif1 endspecify integer posedge signed vectored case endtable join primitive small wait casex endtask large pullo specify wand casez event liblist pulli specparam weak0 cell for library pullup strong weak1 cmos force localparam pulldown strong while config forever macromodule pulsestyle supply0 wire _ondetect deassign fork medium pulsestyle supply1 wor _onevent default function module rcmos table xnor defparam generate nand real task xor design genvar negedge realtime time disable highz0 nmos reg tran edge highz1 nor release tranif0 else if noshow repeat tranif1 cancelled These keywords are reserved by Verilog but not supported by XST www xilinx com XST User Guide 1 800 255 7778 Verilog 2001 Support in XST Z XILINX Verilog 2001 Support in XST XST 6 1i supports the following Verilog 2001 features For details on Verilog
30. in std logic a in std logic vector 4 downto 0 dpra in std logic vector 4 downto 0 di in std logic vector 3 downto 0 Spo out std logic vector 3 downto 0 dpo out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if spo lt RAM conv_integer a dpo lt RAM conv_integer dpra end if end process end syn Verilog Following is the Verilog code for a dual port RAM with false synchronous read module raminfr clk we a dpra di spo dpo input clk input we input 4 0 a input 4 0 dpra input 3 0 di output 3 0 spo output 3 0 dpo reg 3 0 ram 31 0 reg 3 0 spo reg 3 0 dpo always posedge clk begin if we ram a lt di spo ramla dpo ram dpra end endmodule XST User Guide www xilinx com 139 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Dual Port RAM with Synchronous Read Read Through The following descriptions are directly mappable onto Block RAM as shown in the following figure They may also be implemented with Distributed RAM DPRA WE Di Block SPO RAM DPO A CLK gt X8982 The following table shows pin descriptions for a dual port RAM with synchronous read
31. input we input 4 0 a input 4 0 dpra input 3 0 di output 3 0 spo output 3 0 dpo reg 3 0 ram 31 0 reg 4 0 read a reg 4 0 read dpra always posedge clk begin if we ram a lt di read a lt a read dpra lt dpra end assign spo ram read a assign dpo ram read dpra endmodule Using More than One Clock The two RAM ports may be synchronized on distinct clocks as shown in the following description In this case only a Block RAM implementation is applicable The following table shows pin descriptions for a dual port RAM with synchronous read read through and two clocks IO pins Description clk1 Positive Edge Write Primary Read Clock clk2 Positive Edge Dual Read Clock XST User Guide www xilinx com 141 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 10 pins Description we Synchronous Write Enable Active High add1 Write Primary Read Address add2 Dual Read Address di Data Input dol Primary Output Port do2 Dual Output Port VHDL Following is the VHDL code library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity raminfr is port elki in std logic Clk2 in std logic we in std logic addl in std logic vector 4 downto 0 add2 in std logic vector 4 downto 0 di in std logic vector 3 downto 0 dol out std logic vector 3 downto 0 do2 out std logic vec
32. out std logic end entity single stage architecture recursive of single stage is component single stage generic sh st integer port CLK in std logic DI in std logic DO out std logic end component signal tmp std logic 264 www xilinx com XST User Guide 1 800 255 7778 Entity and Architecture Descriptions XILINX begin GEN FD LAST if sh st 1 generate inst fd FD port map D gt DI C gt CLK Q gt DO end generate GEN FD INTERM if sh st 1 generate inst fd FD port map D gt DI C gt CLK Q 5tmp inst sstage single stage generic map sh st gt sh st 1 port map DI gt tmp CLK gt CLK DO 2DO end generate end recursive Component Configuration Associating an entity architecture pair to a component instance provides the means of linking components with the appropriate model entity architecture pair XST supports component configuration in the declarative part of the architecture for instantiation_list component_name use LibName entity_Name Architecture_Name Example 6 2 Structural Description of a Half Adder shows how to use a configuration clause for component instantiation The example contains the following for all statement for all NAND2 use entity work NAND2 ARCHI This statement indicates that all NAND2 components use the entity NAND2 and Architecture ARCHI Note When the configuration clause is missing for a
33. 0 1 gt a synchronous part may be specified here end process Note that XST does not support clock and clock enable descriptions within the same wait statement Instead code these descriptions as in Example 6 17 XST User Guide www xilinx com 273 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Example 6 17 Clock and Clock Enable Not supported ENABLE 1 ll o w a Q wait until CLOCK event and CLOCK Supported wait until CLOCK event and CLOCK if ENABLE 1 then ll o Examples of Register and Counter Descriptions Example 6 18 describes an 8 bit register using a process with a sensitivity list Example 6 19 describes the same example using a process without a sensitivity list containing a wait statement Example 6 18 8 bit Register Description Using a Process with a Sensitivity List entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK begin if CLK EVENT and CLK 1 then DO DI end if end process end ARCHI Example 6 19 8 bit Register Description Using a Process without a Sensitivity List entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT DO out BIT VECTOR
34. Chapter 5 Design Constraints Constraint Name translate_on XCF Constraint Syntax Value na XCF Constraint Syntax Target na Command Line Cmd Line Old XST Constraint Syntax Value no no value Command Line Old XST Constraint Syntax Target local no target Technology Spartan TI TIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS use_carry _chain yes no true false model net in model yes yes no entity signal Spartan I IIE 3 Virtex TI II Pro II Pro X E Uselowskew lines yes true net in model no yes signal Spartan IT IIE 3 Virtex M TI II Pro II Pro X E xor collapse yes no true false model net in model yes yes no entity signal Spartan IT TIE 3 Virtex TI II Pro II Pro X E XST Com mand Line Only Options bufg na na yes integer na XC9500 CoolRunner XPLA3 II IIS bus delimiter na na lt gt Lh yes na Spartan II TIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS case na na yes upper lower maintain na Spartan TI TIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS hierarchy _separator na na yes _ default is _ na Spartan II TIE 3 Virtex TI II Pro II Pro X E XC9500 Coo
35. Macro Generation lt XILINX e Slice Packing e Use Carry Chain e Write Timing Constraints e XOR Collapsing Macro Generation The Virtex Macro Generator module provides the XST HDL Flow with a catalog of functions These functions are identified by the inference engine from the HDL description their characteristics are handed to the Macro Generator for optimal implementation The set of inferred functions ranges in complexity from simple arithmetic operators such as adders accumulators counters and multiplexers to more complex building blocks such as multipliers shift registers and memories Inferred functions are optimized to deliver the highest levels of performance and efficiency for Virtex architectures and then integrated into the rest of the design In addition the generated functions are optimized through their borders depending on the design context This section categorizes by function all available macros and briefly describes technology resources used in the building and optimization phase Macro Generation can be controlled through attributes These attributes are listed in each subsection For general information on attributes see Chapter 5 Design Constraints XST uses dedicated carry chain logic to implement many macros In some situations carry chain logic may lead to sub optimal optimization results Use the USE CARRY CHAIN constraint to direct XST to deactivate this feature Please refer to Chapter 5
36. Note During synthesis XST decomposes Accumulators on Adders and Registers if they do not contain synchronous load signals This is done to create additional opportunities for timing optimization Because of this Accumulators reported during the Macro Recognition step and in the overall statistics of recognized macros may not appear in the final report Adders registers are reported instead Related Constraints There are no related constraints available 4 bit Unsigned Up Accumulator with Asynchronous Clear The following table shows pin definitions for a 4 bit unsigned up accumulator with an asynchronous clear IO Pins Description C Positive Edge Clock CLR Asynchronous Clear active High D 3 0 Data Input Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned up accumulator with an asynchronous clear library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all 66 www xilinx com XST User Guide 1 800 255 7778 Accumulators Z XILINX entity accum is port C CLR in std logic D in std logic vector 3 downto 0 Q out std logic vector 3 downto 0 end accum architecture archi of accum is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp lt tmp D end if end process Q lt tmp end archi Verilog Code Following is the Verilog cod
37. See the DATA GATE in the Constraints Guide for details Keep Hierarchy This option is related to the hierarchical blocks VHDL entities Verilog modules specified in the HDL design and does not concern the macros inferred by the HDL synthesizer The Keep Hierarchy KEEP HIERARCHY constraint enables or disables hierarchical flattening of user defined design units and controls whether it is passed on as an implementation constraint See KEEP HIERARCHY in the Constraints Guide for details Macro Preserve The Macro Preserve pld mp option is useful for making the macro handling independent of design hierarchy processing This allows you to merge all hierarchical blocks in the top module while still keeping the macros as hierarchical modules You can also keep the design hierarchy except for the macros which are merged with the surrounded logic Merging the macros sometimes gives better results for design fitting Two values are available for this option yes check box is checked macros are preserved and generated by Macro no check box is not checked macros are rejected and generated by HDL synthesizer Depending on the Flatten Hierarchy value a rejected macro becomes a hierarchical block Flatten Hierarchy no or is merged in the design logic Flatten Hierarchy yes Very small macros 2 bit adders 4 bit multiplexers are always merged independent of the Macro Preserve or Flatten Hierarchy options Define this opt
38. The Map Logic on BRAM BRAM_MAP constraint is used to map an entire hierarchical block on the block RAM resources available in Virtex and later technologies See Mapping Logic onto Block RAM in Chapter 3 and also BRAM MAP in the Constraints Guide for details e Max Fanout The Max Fanout MAX_FANOUT constraint limits the fanout of nets or signals See MAX_FANOUT in the Constraints Guide for details e Move Last Stage The Move Last Stage MOVE_LAST_STAGE constraint controls the retiming of registers with paths going to primary outputs See MOVE_LAST_STAGE in the Constraints Guide for details e Move First Stage The Move First Stage MOVE_FIRST_STAGE constraint controls the retiming of registers with paths coming from primary inputs See MOVE_FIRST_STAGE in the Constraints Guide for details e Multiplier Style The Multiplier Style MULT_STYLE constraint controls the way the macro generator implements the multiplier macros Allowed values are auto block lut pipe_lut and kcm The default is auto meaning that XST looks for the best implementation for each considered macro The pipe_lut option is for pipeline multipliers The implementation style can be manually forced to use block multiplier or LUT resources available in the Spartan 3 Virtex II Virtex II Pro and Virtex II Pro X devices See MULT_STYLE in the Constraints Guide for details 228 www xilinx com XST User Guide 1
39. The file containing the RTL view has an NGR file extension Generate RTL Schematic is defined globally with the tlview command line option of the run command Following is the basic syntax rtlview yes no only From the command line the default is no From Project Navigator the default is yes In Project Navigator specify tlview globally with the Generate RTL Schematic option in the Synthesis Options tab of the Process Properties dialog box Hierarchy Separator The Hierarchy Separator hierarchy separator command line option defines the hierarchy separator character that is used in name generation when the design hierarchy is flattened There are two supported characters and The default is _ If a design contains a sub block with instance INST1 and this sub block contains a net called TMP NET then the hierarchy is flattened and the hierarchy separator character is The name of TMP NET becomes INST1_TMP_NET If the hierarchy separator character is then the name of the net will be INST1 TMP NET Using as a hierarchy separator is very useful in the design debugging process because this separator makes it much easier to identify a name if it is hierarchical Define this option globally with the hierarchy separator command line option of the run command Following is the basic syntax hierarchy separator _ The default is _ In Project Navigator specify hierarchy separator globally with the H
40. begin scope is printed and similarly end scope is printed when exiting a block The preceding report corresponds to the following schematic e p Q O 1 372ns 2 970ns 0 738ns 1 265ns 0 738ns 0 000ns 0 440ns state_FFD1 LUT_54 next state 2 X9554 Implementation Constraints XST writes all implementation constraints generated from HDL or constraint file attributes LOC into the output NGC file KEEP properties are generated by the buffer insertion process for maximum fanout control or for optimization purposes Virtex Primitive Support XST allows you to instantiate Virtex primitives directly in your VHDL Verilog code Virtex primitives such as MUXCY L LUT4 L CLKDLL RAMBA S1 516 IBUFG PCI33 5 and NAND3b2 can be manually inserted in your HDL design through instantiation These primitives are not by default optimized by XST and are available in the final NGC file Use the Optimize Instantiated Primitives synthesis option to optimize instantiated primitives and obtain better results Timing information is available for most of the primitives allowing XST to perform efficient timing driven optimization Some of these primitives can be generated through attributes e CLOCK BUFFER can be assigned to the primary input to force the use of BUFGDLL IBUFG or BUFGP XST User Guide www xilinx com 193 1 800 255 7778 2 XILINX 194 Chapter 3 FPGA Optimization e
41. but by using the BOX TYPE constraint you can direct XST to skip synthesis of this RTL code and create a black box The EDIF netlist is linked to the synthesized design during NGDBuild Please see General Constraints in Chapter 5 for more information Also see the Constraints Guide for details Note Remember that once you make a design a black box each instance of that design is a black box While you can attach constraints to the instance XST ignores any constraint attached to the original design From the flow point of view the recognition of black boxes in XST is done before the macro inference process Therefore the LOG file differs from the one generated for other macros Analyzing Entity black b Architecture lt archi gt WARNING Xst 766 black box l vhd Line 15 Generating a Black Box for component my block Entity black b analyzed Unit black b generated www xilinx com XST User Guide 1 800 255 7778 Black Box Support Z XILINX Related Constraints XST has a BOX_TYPE constraint that can be applied to black boxes However it was introduced essentially for Virtex Primitive instantiation in XST Please read Virtex Primitive Support in Chapter 3 in before using this constraint VHDL Following is the VHDL code for a black box library ieee use ieee std_logic_1164 all entity black_b is port DI_1 DI_2 in std logic DOUT out std logic end black b
42. can also use don t cares to describe selector values During the Macro Inference step XST makes a decision to infer or not infer the MUXs For example if the MUX has several inputs that are the same then XST can decide not to infer it If you do want to infer the MUX you can force XST by using the design constraint called MUX_EXTRACT If you use Verilog then you must be aware that Verilog Case statements can be full or not full and they can also be parallel or not parallel A Case statement is e FULL if all possible branches are specified e PARALLEL if it does not contain branches that can be executed simultaneously www xilinx com 83 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The following tables gives three examples of Case statements with different characteristics Full and Parallel Case module full sel il 12 i3 14 ol input 1 0 sel input 1 0 i1 i2 i3 14 output 1 0 o1 reg 1 0 o1 always G sel or il or i2 or i3 or i4 begin case sel 2 b00 ol 2 b01 o1 2 b10 ol 2 b11 ol endcase end endmodule 11 12 13 14 Not Full but Parallel module notfull sel Xl i2 13 ol input 1 0 sel input 1 0 i1 output 1 0 o1 reg 1 0 o1 always ft sel or begin Case sel 2 b00 ol 2 b01 ol 2 b10 ol endcase end endmodule 12 13 il or 12 or 13 il i2 33 84 www xi
43. constraint See RESYNTHESIZE and INCREMENTAL_SYNTHESIS in the Constraints Guide for details www xilinx com 227 1 800 255 7778 7 XILINX Chapter 5 Design Constraints e Incremental Synthesis The Incremental Synthesis INCREMENTAL_SYNTHESIS constraint controls the decomposition of a design into several subgroups This can be applied on a VHDL entity or Verilog module so that XST generates a single and separate NGC file for it and its descendents See the Incremental Synthesis Flow section in this guide as well as INCREMENTAL SYNTHESIS in the Constraints Guide for details Note The INCREMENTAL_SYNTHESIS switch is not accessible via the Synthesize XST Process Properties dialog box This directive is only available via VHDL attributes or Verilog meta comments or via an XST constraint file e Keep Hierarchy XST may automatically flatten the design to get better results by optimizing entity module boundaries You can use the Keep Hierarchy KEEP_HIERARCHY constraint to preserve the hierarchy of your design In addition this constraint may be propagated to the NGC file as an implementation constraint depending on its value See KEEP HIERARCHY in the Constraints Guide for details e Logical Shifter Extraction The Logical Shifter Extraction SHIFT EXTRACT constraint enables or disables logical shifter macro inference See SHIFT EXTRACT in the Constraints Guide for details e Map Logic on BRAM
44. else cnt lt cnt 1 MAX end assign Q cnt endmodule Related Constraints There are no related constraints available Accumulators An accumulator differs from a counter in the nature of the operands of the add and subtract operation e Jna counter the destination and first operand is a signal or variable and the other operand is a constant equal to 1 A lt A 1 e Inan accumulator the destination and first operand is a signal or variable and the second operand is either asignal or variable A lt A B aconstant not equal to 1 A lt A Constant An inferred accumulator can be up down or updown For an updown accumulator the accumulated data may differ between the up and down mode if updown 1 then a lt a b else a lt a c XST can infer an accumulator with the same set of control signals available for counters Refer to Counters in this chapter for more details XST User Guide www xilinx com 65 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Log File The XST log file reports the type and size of recognized accumulators during the Macro Recognition step Synthesizing Unit lt accum gt Related source file is accumulators 1l vhd Found 4 bit up accumulator for signal tmp Summary inferred 1 Accumulator s Unit accum synthesized HDL Synthesis Report Macro Statistics 4 Accumulators sU 4 bit up accumulator fo
45. reset initial value to a register via your behavioral VHDL code Do this by assigning a value to a register when the register s reset line goes to the appropriate value as in the following example Example process clk rst begin if rst 1 then arb onebit 0 end if end process When you set the initial value of a variable in the behavioral code it is implemented in the design as a flip flop whose output can be controlled by a local reset as such it is carried in the NGC file as an FDP or FDC flip flop Local Reset z Global Reset 260 Note that local reset is independent of global reset Registers controlled by a local reset may be set to a different value than ones whose value is only reset at global reset power up In the following example the register arb onebit is set to 0 at global reset but a pulse on the local reset rst can change its value to 1 Example entity top is Port Clk rst in std logic a in in std logic dout out std logic end top www xilinx com XST User Guide 1 800 255 7778 Objects in VHDL 7 XILINX architecture Behavioral of top is signal arb_onebit std_logic 1 begin process clk rst begin if rst 1 then arb onebit lt 0 elsif clk event and clk 1 then arb onebit lt a in end if end process dout arb onebit end Behavioral This sets the initial value on the register s output to 1 at initial power up but si
46. resources means the functionality For example if you code the Case statement neither full nor parallel with Case Implementation Style set to none from the functionality point of view XST implements a priority encoder latch But it does not inevitably mean that XST infers the priority encoder during the Macro Recognition step Case Implementation Parameter Value Full Not Full Neither Full nor Parallel none MUX Latch Priority Encoder Latch parallel MUX Latch Latch full MUX MUX Priority Encoder full parallel MUX MUX MUX www xilinx com 85 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Note Specifying full parallel or full parallel may result in an implementation with a behavior that may differ from the behavior of the initial model Log File The XST log file reports the type and size of recognized MUXs during the Macro Recognition step Synthesizing Unit lt mux gt Related source file is multiplexers_1 vhd Found 1 bit 4 to 1 multiplexer for signal o Summary inferred 1 Multiplexer s Unit lt mux gt synthesized HDL Synthesis Report Macro Statistics Multiplexers a Ob 1 bit 4 to 1 multiplexer al Related Constraints Related constraints are MUX_EXTRACT and MUX_STYLE 4 to 1 1 bit MUX using IF Statement The following table shows pin definitions for a 4 to 1 1 bit MUX using an If statement IO Pins Description a b c d Data
47. strongly suggest that you use this new name See BUFFER_TYPE in the Constraints Guide for details Cores Search Directories The Cores Search Directories command line switch sd tells XST to look for cores in directories other than the default one by default XST searches for cores in the directory specified in the ifn switch Define this option globally with the sd command line option of the run command Allowed values are names of directories sd directory path directory path There is no default In Project Navigator specify this option with the Cores Search Directories option of the Synthesis Options tab in the Process Properties dialog box Allowed values are names of directories There is no default Decoder Extraction The Decoder Extraction DECODER EXTRACT constraint enables or disables decoder macro inference See DECODER EXTRACT in the Constraints Guide for details FSM Style The FSM Style constraint can be used to make large FSMs more compact and faster by implementing them in the block RAM resources provided in Virtex and later technologies You can direct XST to use block RAM resources rather than LUTs the default to implement FSMs by using the F5M STYLE design constraint See FSM STYLE in the Constraints Guide for details Resynthesize The RESYNTHESIZE constraint is related to Incremental Synthesis Flow It forces or prevents resynthesis of groups created via the INCREMENTAL_SYNTHESIS
48. when sel 000 else 00000010 when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 01000000 when sel 110 else 10000000 end archi Verilog One Hot Following is the Verilog code for a 1 of 8 decoder module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always 8 sel or res begin case sel 3 b000 res 8 b00000001 3 b001 res 8 b00000010 3 b010 res 8 b00000100 3 b011 res 8 b00001000 3 b100 res 8 b00010000 3 b101 res 8 b00100000 3 b110 res 8 b01000000 default res 8 b10000000 endcase end endmodule VHDL One Cold Following is the VHDL code for a 1 of 8 decoder library ieee use ieee std_logic_1164 all entity dec is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end dec 92 www xilinx com XST User Guide 1 800 255 7778 Decoders 7 XILINX architecture archi of dec begin res lt 11111110 UIITIITOQI 11111011 PALITO TA 11101111 ETOTITTIT 10111111 WOU A LL end archi Verilog One Cold Following is the Verilog code for a 1 of 8 decoder module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always sel begin case sel 3 b000 default res endcase end endmodule when when when when
49. when sl gt if x1 1 then state lt s2 else state lt s3 end if when s2 gt state lt s4 when s3 gt state lt s4 when s4 gt state lt sl end Case end if end process processl XST User Guide www xilinx com 163 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques process2 process state begin Case state is when sl gt outp lt 1 when s2 gt outp lt 1 when s3 gt outp lt 0 when s4 gt outp lt 0 end case end process process2 end behl Verilog Following is the Verilog code for an FSM with two processes module fsm clk reset xl outp input clk reset xl output outp reg outp reg 1 0 state parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 always G8 posedge clk or posedge reset begin if reset state sl else begin case state sl if xl 1 b1 state s2 else state s3 s2 state s4 s3 state s4 s4 state sl endcase end end always Q8 state begin Case state Sl outp 1 b1 S2 outp 1 b1 s3 outp 1 b0 s4 outp 1 b0 endcase end endmodule 164 www xilinx com 1 800 255 7778 XST User Guide State Machine XILINX FSM with 3 Processes You can also separate the NEXT State function from the state register State Output Fredis Funct Outputs egister unction Inputs Function E Only for Mealy Machine
50. 0 end adder architecture archi of adder is begin SUM lt A B CI end archi XST User Guide www xilinx com 103 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Following is the Verilog code for an unsigned 8 bit adder with carry in module adder A B CI SUM input 7 0 A input 7 0 B input CI output 7 0 SUM assign SUM A B CI endmodule Unsigned 8 bit Adder with Carry Out This section contains VHDL and Verilog descriptions of an unsigned 8 bit adder with carry out an If you use VHDL then before writing a operation with carry out please examine the arithmetic package you are going to use For example std logic unsigned does not allow man you to write in the following form to obtain Carry Out Res 9 bit A 8 bit B 8 bit The reason is that the size of the result for in this package is equal to the size of the longest argument that is 8 bits e One solution for the example is to adjust the size of operands A and B to 9 bits using concatenation Res lt 0 amp A O amp B In this case XST recognizes that this 9 bit adder can be implemented as an 8 bit adder with carry out e Another solution is to convert A and B to integers and then convert the result back to the std logic vector specifying the size of the vector equal to 9 The following table shows pin descriptions for an unsigned 8 bit adder with carry out
51. 0 0 eee te eee 111 Iscr ETE 111 Related Constraints i vili od Ore iG A EXE C EST HE Need 111 Unsigned 8x4 bit Multiplier lisse 111 Pipelined Multipliers ek eee pega rre ias ads FESSES epe eS 112 Dividets2 imzdeco ku ee Arq DTE CE YRU RERO ERR E RARE ERR RE Ex Ra 117 12 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Log File 55ism ra ds cda 117 Related ConstraidtS ooooorr eee rn 117 Divisi n By Constant 2 6 esse zia bres RA ree ir rs a 117 Resource Daring cies cease its at LEE 118 Log Files 2 832 iees ERE p de heb rs are iia 119 Related Constraint o 119 Example rs 4 0 cs repeiees rupe bbs citada iba ire a 119 RAMS ROMS sssssse e RR here 121 Log File DUIS 122 Related Constraints o o oooo teiseni oas s 122 Virtex II Spartan 3 RAM Read Write Modes oooccccoccocccccccccccs 123 Read FEirst MOde e AE EA aos 123 Write First Mode 124 No Change Mode nee re pee peor e e Quad leek ede E ee di eee PET ed 126 Single Port RAM with Asynchronous Read 6 06 cece cece eee ee 128 VADE a RR Meike eine ee aaa tae ciate liudee dea eed 129 Verla ee ee 129 Single Port RAM with False Synchronous Read 0 0 c eee eee 130 ba 130 Verilog P 131 VAD Dowie see eset eck ett beh edict Dek CEE ee bd be aa a eee ae 132 Verlo RR 133 Single Port RAM with Synchronous Read Read Through 133 UT 134 MS c EOD 134 Single Port RAM with Enab
52. 005 328 Library Search Order File 0 000s 329 Project Navigator eese pete Ig ae dale Ge reeni e e eai a 329 Command LANE ori A Ee PE Re Ii ade 329 Search Order Rules o oooooooooo RR 329 Examples te A HP A A A AA 330 Example diia o pee state iq Do odeur odi ia Qus 330 Example 2 eds ob dd id 330 EXA DAP IOS n 331 Example Lit et ih eae a thee eh Ue vbt dee ee es E ah dese da 331 Chapter 9 Log File Analysis Introduction 0 0c cc eee cece nen e e 333 Reducing the Size of the LOG File 00 0 0 cece eee 334 Quiet Mode iio rs ERE eae a Rene Y Cea RET RIESRRES CRI 334 18 www xilinx com XST User Guide 1 800 255 7778 XILINX Sillentmodes Laia a cs rev 335 Hiding specific messages isses en 335 Timing Report sere ree RAEI be e Ec PCIe AURORA AIC ES 336 FPGA AAA 336 CPLD Log Wile sarria edat ok cR eer nich de dead ea 343 Chapter 10 Command Line Mode Introduction 12g csses ARE RO Hd ER a OR Re oa E 349 Launching AS DaacgquosVedutessa sbpdo rep En AAN a eke 350 Setting Upan AST SEPIDE sede p tae d eb patct og rica tech es 351 Run Command dd ai 351 Getting Help ackasxokbeuikencokka sched rra dob bd phia rides 356 Set Command L2 cn cde poen eos SOLO AAA a Rear add Ro Rb e a 357 Elaborate Comanand onse dr A C FR HR raa 358 Example 1 How to Synthesize VHDL Designs Using Command Line Mode 358 Example lisis a p EX SEHR RA RUN es ra rele eed 359 PICU E MO m 360
53. 18 bit register for signal b in Found 18x18 bit multiplier for signal mult res Found 36 bit register for signal pipe 1 Summary inferred 108 D type flip flop s inferred 1 Multiplier s Unit lt my_mult gt synthesized Advanced HDL Synthesis Found pipelined multiplier on the signal mult res with 1 pipeline level s INFO Xst HDL ADVISOR You can improve the performance of this multiplier by adding 3 register level s VHDL Use the following templates to implement pipelined multipliers in VHDL The following VHDL template shows the multiplication operation placed outside the process block and the pipeline stages represented as single registers library ieee use ieee std logic 1164 all use ieee numeric std all entity mult is generic A port siz integer 18 B port siz integer 18 i port clk in std_logic A in unsigned A_port_size 1 downto 0 B in unsigned B_port_size 1 downto 0 MULT out unsigned A_port_size B_port_size 1 downto 0 end mult XST User Guide www xilinx com 113 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture beh of mult is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 signal pipe 1 pipe 2 pipe 3 unsigned A port size B port size 1 downto 0 begin mult res lt a in b in
54. 2001 see Verilog 2001 A Guide to the New Features by Stuart Sutherland or IEEE Standard Verilog Hardware Description Language manual IEEE Standard 1364 2001 XST User Guide Generate statements Combined port data type declarations ANSI style port lists Module parameter port lists ANSI C style task function declarations Comma separated sensitivity list Combinatorial logic sensitivity Default nets with continuous assigns Disable default net declarations Indexed vector part selects Multi dimensional arrays Arrays of net and real data types Array bit and part selects Signed reg net and port declarations Signed based integer numbers Signed arithmetic expressions Arithmetic shift operators Automatic width extension past 32 bits Power operator N sized parameters Explicit in line parameter passing Fixed local parameters Enhanced conditional compilation File and line compiler directives www xilinx com 323 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support 324 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 8 Mixed Language Support Introduction XST User Guide This chapter contains the following sections Introduction Mixed Language Project File VHDL Verilog Boundary Rules Port Mapping Generics Support in Mixed Language Projects Library Search Order File XST supports mixed VHDL Verilog projects This chapter explains how t
55. 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if if rst 1 then do lt others gt 0 else do lt RAM conv_integer a end if end if end process end syn 132 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX Verilog Following is the Verilog code module raminfr clk we rst a di do input clk input we input rst input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 3 0 do always posedge clk begin if we ram a lt di 4t Est do lt 4 b0 else do lt ram a end endmodule Single Port RAM with Synchronous Read Read Through XST User Guide The following description implements a true synchronous read A true synchronous read is the synchronization mechanism available in Virtex block RAMs where the read address is registered on the RAM clock edge Such descriptions are directly mappable onto Block RAM as shown below The same descriptions can also be mapped onto Distributed RAM WE _ DI _ Block DO A RAM cLK gt X8979 The following table shows pin descriptions for a single port RAM with synchronous read read through IO pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Read Write Ad
56. 52 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Tristates Verilog Code Following is Verilog code for a tristate element using a combinatorial process and always block module three_st T input T 1 output 0 reg O I O always T or I begin if T O I else O 1 bZ end endmodule Description Using Concurrent Assignment In the following two examples note that comparing to 0 instead of 1 infers a BUFT primitive instead of a BUFE macro The BUFE macro has an inverter on the E pin VHDL Code Following is VHDL code for a tristate element using a concurrent assignment library ieee use ieee std_logic_1164 all entity three_st is port in std_logic T I in std logic O out std_logic end three st architecture archi of three st is begin O lt I when T 0 lse Z end archi Verilog Code Following is the Verilog code for a tristate element using a concurrent assignment module three_st T 1 0 input T 1 output O0 assign O T I 1 bZ endmodule XST User Guide www xilinx com 53 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Counters XST is able to recognize counters with the following control signals e Asynchronous Set Clear e Synchronous Set Clear e Asynchronous Synchronous Load signal and or constant e Clock Enable e Modes Up Down Up Down e Mixture of all of the above HDL coding styles for the followin
57. 6 0 SI end assign PO tmp endmodule 76 www xilinx com XST User Guide 1 800 255 7778 Shift Registers lt XILINX 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out Note For this example XST does not infer SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock an asynchronous parallel load a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In ALOAD Asynchronous Parallel Load active High D 7 0 Data Input SO Serial Output VHDL Code Following is VHDL code for an 8 bit shift left register with a positive edge clock an asynchronous parallel load a serial in and a serial out library ieee use ieee std_logic_1164 all entity shift is port C SI ALOAD in std logic D in std logic vector 7 downto 0 SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C ALOAD D begin if ALOAD 1 then tmp lt D elsif C event and C 1 then tmp lt tmp 6 downto 0 SI end if end process SO lt tmp 7 end archi XST User Guide www xilinx com 77 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock an asynchronous parallel load a
58. E bufgce yes no net in model no yes no primary clock Virtex II TI Pro true false signal II Pro X bram map yes no model yes yes no VHDL Spartan I IIE 3 true false entity Virtex M TI II Pro Verilog II Pro XE module clock buffer bufgdll net in model no bufgdll signal Spartan IT IIE 3 ibufg bufgp ibufg bufgp Virtex M TI II Pro ibuf none ibuf none II Pro X E clock signal yes no primary clock no yes no primary clock Spartan I IIE 3 true false signal signal Virtex M TI II Pro net in model II Pro X E decoder yes no model yes yes no entity signal Spartan IT IIE 3 extract true false net in model Virtex M TI II Pro II Pro X E enum string net in model no string type in Spartan IT TE 3 _encoding containing containing VHDL only Virtex M TI II Pro space space II Pro X E XC9500 separated separated CoolRunner binary codes binary codes XPLA3 II IIS equivalent yes no model yes yes no entity signal Spartan IT IIE 3 _register true false net in model Virtex M TI II Pro removal II Pro X E XC9500 CoolRunner XPLA3 II IIS XST User Guide www xilinx com 239 1 800 255 7778 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options Command Command XCF XCF Line Line Constraint Constraint Constraint cma Technology Line Old XST Old XST Name Synta
59. Example 2 How to Synthesize Verilog Designs Using Command Line Mode 361 Example 2 vs asuct aac eye ad eee pecan tans babes labs 362 Script Mode ok e tees a A eed eae P ECCME E Rd 362 Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Ling Mode curia ada piede 1S dried de qii i a dede Ip E c pads e 363 Script Mode e yrs t crastino b Mer ERREUR E eee vena hr Ru REY ae rues 364 Appendix A XST Naming Conventions Net Naming Conventions ssssssssssssssss en 367 Instance Naming Conventions 23 06 26 cce ken the e 367 XST User Guide www xilinx com 19 1 800 255 7778 7 XILINX 20 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 1 Introduction This chapter contains the following sections Architecture Support XST Flow Architecture Support The software supports the following architecture families in this release XST Flow Virtex E II II Pro II Pro X Spartan II IIE 3 CoolRunner XPLA3 II IIS XC9500 XL XV XST is a Xilinx tool that synthesizes HDL designs to create Xilinx specific netlist files called NGC files The NGC file is a netlist that contains both logical design data and constraints that takes the place of both EDIF and NCF files This manual describes XST support for Xilinx devices HDL languages and design constraints The manual also explains how to use various design optimization and coding techniques when creating desig
60. Full Parallel Full Parallel Set Command In addition to the run command XST also recognizes the set command This command accepts the options shown in the following table Table 10 8 Set Command Options Set Commang Description Values Options generated by XST during a session dumpdir Location of all files resulting Any valid path to a directory from VHDL compilation xsthdpdir Work Directory location of Any valid path to a directory all files resulting from VHDL Verilog compilation xsthdpini HDL Library Mapping File file_name INI File XST User Guide www xilinx com 357 1 800 255 7778 7 XILINX Elaborate Command The goal of this command is to pre compile VHDL Verilog files in a specific library or to verify Verilog files without synthesizing the design Taking into account that the compilation process is included in the run this command remains optional Chapter 10 Command Line Mode The elaborate command accepts the options shown in the following table Table 10 9 Elaborate Command Options Elaborate Command Options Description Values ifn Project File file name ifmt Format vhdl verilog mixed lso Library Search Order file_name lso work lib Work Library for name work Compilation directory where the top level block was compiled Compilation verilog2001 Verilog 2001 Yes No vlgpath Verilog Search Paths Any valid path to director
61. HDL design file e The first column specifies whether the HDL file is VHDL or Verilog e The second column specifies the logic library where the HDL is compiled By default the logic library is work e The third column specifies the name of the HDL file VHDL Verilog Boundary Rules The boundary between VHDL and Verilog is enforced at the design unit level A VHDL design can instantiate a Verilog module A Verilog design can instantiate a VHDL entity Instantiating a Verilog Module in a VHDL Design 326 To instantiate a Verilog module in your VHDL design do the following 1 Declarea VHDL component with the same name respecting case sensitivity as the Verilog module you want to instantiate If the Verilog module name is not all lower case use the Case property to preserve the case of your Verilog module In Project Navigator select Maintain for the Case option under the Synthesis Options tab in the Process Properties dialog box or set the case command line option to maintain at the command line 2 Instantiate your Verilog component as if you were instantiating a VHDL component www xilinx com XST User Guide 1 800 255 7778 VHDL Verilog Boundary Rules 7 XILINX Note Using a VHDL configuration declaration one could attempt to bind this component to a particular design unit from a particular library Please note that such binding is not supported Only default Verilog module binding is supported The only Verilo
62. In Project Navigator specify this option globally with the Cross Clock Analysis option in the Synthesis Options tab of the Process Properties dialog box www xilinx com XST User Guide 1 800 255 7778 Timing Constraints XILINX Write Timing Constraints The Write Timing Constraints option write timing constraints in one of your status reports enables or disables propagation of timing constraints to the NGC file that are specified in HDL code These timing constraints in the NCG file will be used during place and route as well as synthesis optimization Define Write Timing Constraints globally with the write timing constraints command line option of the run command Following is the basic syntax write timing constraints yes no The default is no not to write timing constraints to the NGC file In Project Navigator specify this option globally with the Write Timing Constraints option in the Synthesis Options tab of the Process Properties dialog box Clock Signal If a clock signal goes through combinatorial logic before being connected to the clock input of a flip flop XST cannot identify what input pin is the real clock pin The CLOCK SIGNAL constraint allows you to define the clock pin See CLOCK SIGNAL in the Constraints Guide for details Global Timing Constraints Support XST supports the following global timing constraints XST User Guide Global Optimization Goal XST can optimize different regi
63. Line Mode describes how to run XST using the command line The chapter describes the xst run and set commands and their options e Appendix A XST Naming Conventions discusses net naming and instance naming conventions XST User Guide www xilinx com 5 1 800 255 7778 7 XILINX Preface About This Guide Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL Tutorials Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xInx xil_ans_browser jsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data Sheets Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http www support xilinx com xlnx xweb xil publications in dex jsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm
64. Options ES Property Name Value AO as mana Equivalent Register Removal I Clock Enable Macro Preserve Figure 5 6 Xilinx amp Specific Options CPLDs Following is a list of the Xilinx Specific Options e Add I O Buffers e Equivalent Register Removal e Clock Enable e Macro Preserve e XOR Preserve e WYSIWYG XST User Guide www xilinx com 215 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Other Command Line Options Any XST command line option can be set via the Other Command Line Options property in the Process Properties dialog box This is an advanced property Use the syntax described in Chapter 10 Command Line Mode Separate multiple options with a space While the Other Command Line Options property is intended for XST options not listed in the Process Properties dialog box if an option already listed as a dialog box property is entered precedence is given to the option entered here Illegal or unrecognized options cause XST to stop processing and generate a message like the following one ERROR Xst 1363 Option verilog2002 is not available for command run Custom Compile File List By using the Custom Compile File List property you can change the order in which source files are processed by XST With this property you select a user defined compile list file that XST uses to determine the order in which it processes libraries and design files Otherwise XST u
65. PROCESS 1 PROCESS 2 PROCESS 3 X8987 Separating the NEXT State function from the state register provides the following description VHDL Following is the VHDL code for an FSM with three processes library IEEE use IEEE std logic 1164 a11 entity fsm is port Clk reset x1 IN std logic outp OUT std logic i end entity architecture behl of fsm is type state type is s1 s2 s3 s4 signal state next state state type begin processl process clk reset begin if reset 1 then state lt sl elsif clk 1 and clk Event then State next state end if end process processl XST User Guide www xilinx com 165 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques process2 process state xl begin case state is when sl gt if x1 1 then next state lt s2 else next state lt s3 end if when s2 gt next state lt s4 when s3 gt next state lt s4 when s4 gt next state lt sl end case end process process2 process3 process state begin case state is when sl gt outp lt 1 when s2 gt outp lt 1 when s3 gt outp lt 0 when s4 gt outp lt 0 end Case end process process3 end behl Verilog Following is the Verilog code for an FSM with three processes module fsm clk reset x1 outp input clk reset xl output outp reg outp reg 1 0 state reg 1 0 next st
66. Pascal and is supported by XST as IEEE 1364 The Verilog support in XST provides an efficient way to describe both the global circuit and each block according to the most efficient style Synthesis is then performed with the best synthesis flow for each block Synthesis in this context is the compilation of high level behavioral and structural Verilog HDL statements into a flattened gate level netlist which www xilinx com 291 1 800 255 7778 XILINX Chapter 7 Verilog Language Support can then be used to custom program a programmable logic device such as the Virtex FPGA family Different synthesis methods are used for arithmetic blocks glue logic and finite state machines This manual assumes that you are familiar with the basic notions of Verilog Please refer to the IEEE Verilog HDL Reference Manual for a complete specification Behavioral Verilog Features This section contains descriptions of the behavioral features of Verilog Variable Declaration 292 Variables in Verilog may be declared as integers or real These declarations are intended only for use in test code Verilog provides data types such as reg and wire for actual hardware description The difference between reg and wire is whether the variable is given its value in a procedural block reg or in a continuous assignment wire Verilog code Both reg and wire have a default width being one bit wide scalar To specify an N bit width vectors for a
67. Recognition step Moreover if you allow XST to choose the best encoding algorithm for your FSMs it reports the one it chose for each FSM Synthesizing Unit lt fsm gt Related source file is state machines l vhd Found finite state machine FSM 0 for signal state States 4 Transitions 5 Inputs 1 Outputs 1 Reset type asynchronous Encoding automatic State register D flip flops Summary inferred 1 Finite State Machine s Unit lt fsm gt synthesized HDL Synthesis Report Macro Statistics FSMs tod Registers o 1 bit register tol Optimizing FSM FSM 0 with One Hot encoding and D flip flops RAM based FSM Synthesis Large FSMs can be made more compact and faster by implementing them in the block RAM resources provided in Virtex and later technologies You can direct XST to use block RAM resources for FSMs by using the F5M STYLE constraint Values for FSM STYLE are lut and bram The lut option is the default and it causes XST to map the FSM using LUTs The bram option directs XST to map the FSM onto block RAM In Project Navigator invoke this constraint by choosing either LUT or Bram from the drop down list to the right of FSM Style under the HDL Options tab of the Process Properties dialog box From the command line use the fsm style command line switch You can also use the F5M STYLE constraint in your HDL code See the Constraints Guide for more inf
68. Removal Slice Packing Pack IO Registers into IOBs General Options Optimization Goal Optimization Effort Keep Hierarchy Global Optimization RTL Output Write Timing Constraints Hierarchy Separator Bus Delimiter Case Specifier Slice Utilization Ratio Slice Utilization Ratio Delta XST User Guide stopwatch prj mixed NO stopwatch NGC xc2v40 6cs144 n topwatch YES Auto G nana wan t O KKK KKK OD OK wn w p Ed Ed bd bd Zo oc tw O on nn AeA Ed oO O tH n Speed 1 NO AllClockNets Yes NO lt gt maintain 100 5 www xilinx com 1 800 255 7778 XILINX 337 7 XILINX Chapter 9 Log File Analysis Other Options lso stopwatch lso Read Cores YES cross clock analysis NO verilog2001 YES Optimize Instantiated Primitives NO E HDL Compilation ul Compiling vhdl file c users doc granite timer ise smallcntr vhd in Library work Architecture inside of Entity smallcntr is up to date Compiling vhdl file c users doc granite timer ise statmach vhd in Library work Architecture inside of Entity statmach is up to date Compiling vhdl file c users doc granite timer ise decode vhd in Library work Architecture behavioral of Entity decode is up to date Compiling vhdl file c users doc granite timer ise cnt60 vhd in Library work Architecture inside of Entity cnt60 is up to date Compiling vhdl file
69. SEARCH ORDER keyword XST ignores the library See Example 4 Examples Example 1 For a project file my proj prj with the following contents vhdl vhlibl fl vhd verilog rtfllib l v vhdl vhlib2 f3 vhd LSO file Created by ProjNav and an LSO file my proj 1so created by Project Navigator with the following contents DEFAULT SEARCH ORDER XST uses the following search order vhlibl rtfllib vhlib2 After processing the contents of my proj 1so will be vhlibl rtfllib vhlib2 Example 2 For a project file my proj prj with the following contents vhdl vhlibl f1 vhd verilog rtfllib fl v vhdl vhlib2 f 3 vhd and an LSO file my_proj 1so created with the following contents rtfllib vhlib2 vhlibl DEFAULT_SEARCH_ORDER 330 www xilinx com XST User Guide 1 800 255 7778 Library Search Order File Z XILINX XST uses the following search order vhlibl rtfllib vhlib2 After processing the contents of my proj 1so will be rtfllib vhlib2 vhlib1 DEFAULT SEARCH ORDER Example 3 For a project file my proj prj with the following contents vhdl vhlibl f1 vhd verilog rtfllib fl v vhdl vhlib2 f3 vhd and an LSO file my proj 1so created with the following contents rtfllib vhlib2 vhlib1 XST uses the following search order rtfllib vhlib2 vhlibl After processing the contents of my_proj 1so will be rtfllib vhlib2 vhlibl Example 4 For a proje
70. SRL WIDTH 1 end beh XST User Guide www xilinx com 279 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support library ieee use ieee std logic 1164 a1 entity TOP is port Clk in std logic inpl inp2 in std logic outpl outp2 out std logic i end TOP architecture beh of TOP is component SINGE_SRL is generic SRL_WIDTH integer 16 port clk in std_logic inp in std_logic outp out std logic end component begin instl SINGE SRL generic map SRL WIDTH gt 13 port map clk gt clk inp gt inpl outp gt outpl i inst2 SINGE_SRL generic map SRL_WIDTH gt 18 port map clk gt clk inp gt inp2 outp gt outp2 i end beh Running this example through XST results in the following error message generated by the Assert statement HDL Analysis Analyzing Entity top Architecture lt beh gt Entity top analyzed Unit top generated Analyzing generic Entity singe srl Architecture lt beh gt SRL WIDTH 13 Entity singe srl analyzed Unit singe srl generated Analyzing generic Entity singe srl Architecture lt beh gt SRL WIDTH 18 ERROR Xst assert l vhd line 15 FAILURE The size of Shift Register xceeds the size of a single SRL www xilinx com XST User Guide 1 800 255 7778 280 Packages Packages XILINX VHDL models may be def
71. Unit timecore synthesized Synthesizing Unit divider Related source file is divider vhd Found 18 bit up counter for signal counter Found 1 1 bit 2 to 1 multiplexers Summary inferred 1 Counter s inferred 1 Multiplexer s Unit divider synthesized The following log sample displays the additional macro processing done during the Advanced HDL Synthesis step Advanced HDL Synthesis E Implementing FSM lt FSM_0 gt on signal lt current_state gt on BRAM INFO Xst Data output of ROM lt Mrom_tmp_one_hot gt in block decode is tied to register one hot in block decode INFO Xst The register is removed and the ROM is implemented as read only block RAM 30 www xilinx com XST User Guide 1 800 255 7778 Introduction 7 XILINX The following log sample displays the overall statistics of recognized macros HDL Synthesis Report Macro Statistics FSMs ROMs 16x7 bit ROM Registers 7 bit register 4 bit register Counters 18 bit up counter Multiplexers 2 to 1 multiplexer Adders Subtractors 7 bit adder 7 bit subtractor DW ds a The following log sample displays the number and type of macros preserved by low level optimization Final Results Macro Statistics FSMs ROMs 16x7 bit ROM Registers 7 bit register 1 bit register 18 bit register Adders Subtractors 7 bit adder 7
72. Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with a synchronous load with a constant module counter C SLOAD Q input C SLOAD output 3 0 Q reg 3 0 tmp always posedge C begin if SLOAD tmp 4 b1010 else tmp tmp 1 b1 end assign Q tmp endmodule XST User Guide www xilinx com 59 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Unsigned Up Counter with Asynchronous Clear and Clock Enable The following table shows pin definitions for a 4 bit unsigned up counter with an asynchronous clear and a clock enable IO Pins Description C Positive Edge Clock CLR Asynchronous Clear active High CE Clock Enable Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned up counter with an asynchronous clear and a clock enable library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity counter is port C CLR CE in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then if CE 1 then tmp lt tmp 1 end if end if end process Q lt tmp end archi 60 www xilinx com XST User Guide 1 800 255 7778 Counters 7 XILINX Verilog Code Following is the Verilog code for a 4 b
73. a constant value Next and Exit statements are supported Example 6 14 shows the use of a For loop statement Example 6 14 For Loop Description library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all entity countzeros is port a in std logic vector 7 downto 0 Count out std logic vector 2 downto 0 end mux4 architecture behavior of mux4 is signal Count Aux std logic vector 2 downto 0 begin process a begin Count Aux 000 for i in a range loop if a i 0 then Count Aux lt Count Aux 1 operator defined in std logic unsigned end if end loop Count Count Aux end process end behavior 272 www xilinx com XST User Guide 1 800 255 7778 Sequential Circuits 7 XILINX Sequential Circuits Sequential circuits can be described using sequential processes The following two types of descriptions are allowed by XST e sequential processes with a sensitivity list e sequential processes without a sensitivity list Sequential Process with a Sensitivity List A process is sequential when it is not a combinatorial process In other words a process is sequential when some assigned signals are not explicitly assigned in all paths of the statements In this case the hardware generated has an internal state or memory flip flops or latches Example 6 15 provides a template for describing sequential circuits
74. aid ia o ltda 55 4 bit Unsigned Down Counter with Synchronous Set 2 2 0 6 eee eee eee 56 VAD Code a p rag 56 Verilog Code sos iue be ie bb te edna bie teh dara 57 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input 57 VHDL Code 505 6 oie cuu tr gai REESE RV uu pda AA As 57 Verilog Codes c ci once oen A A A eects 58 4 bit Unsigned Up Counter with Synchronous Load with a Constant 58 VADL C de iia dd a a ia E EET a eei 59 Menlog Code o5 lesu thin bite RE Ep Pe e pde erbe 59 4 bit Unsigned Up Counter with Asynchronous Clear and Clock Enable 60 VHDL Code esc bean ches tds waka ri ELEM HEN PETRA gana 60 Verilog Codecs cos scs udo sube ius detiene aere ate 61 4 bit Unsigned Up Down counter with Asynchronous Clear suse 61 VHDL Code i25 these e ROI eR e aU AA RARA AAA iR 61 Verllog Code i scc tuae be echhe sete tire nee eds up Nd pas barsa 62 4 bit Signed Up Counter with Asynchronous Reset sees 62 VHDL Coder ueri tae e EY ES XN evo eed ARS E Ere eut 63 Verilog Codes viv oes xbeperc A esc tirer be dE AS 63 4 bit Signed Up Counter with Asynchronous Reset and Modulo Maximum 64 VEIDLE Code ash nsi a a RA ETRA RETI AER EE aod Role 64 Verilog Code zs cedet oet uet Ups beste vies Tre ve y OP er Yee 65 Related Constraidts eee hr hrs 65 Accumulatotrs 2 tomes tud esta ec Son e Tee Sa 65 Lop Ple dens edes ond DIUI ies 66 Related Constraitits nosse oc
75. architecture archi of black b is component my block port Il in std logic I2 in std logic O out std logic end component begin inst my block port map Il1 DI 1 I2 2 DI 2 O gt DOUT i end archi Verilog Following is the Verilog code for a black box module my_block inl in2 dout input inl in2 output dout endmodule module black_b DI_1 DI_2 DOUT input DI_1 DI_2 output DOUT my_block inst inl DI 1 in2 DI 2 dout DOUT i endmodule Note Please refer to the VHDL Verilog language reference manuals for more information on component instantiation XST User Guide www xilinx com 171 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 172 www xilinx com XST User Guide 1 800 255 7778 XILINX Chapter 3 FPGA Optimization Introduction XST User Guide This chapter contains the following sections Introduction Virtex Specific Synthesis Options Macro Generation Mapping Logic onto Block RAM Flip Flop Retiming Incremental Synthesis Flow Speed Optimization Under Area Constraint Log File Analysis Implementation Constraints Virtex Primitive Support Cores Processing Specifying INITs and RLOCs in HDL Code PCI Flow XST performs the following steps during FPGA synthesis and optimization Mapping and optimization on an entity module by entity module basis Global
76. bit MUX using tristate buffers module mux a b C input a b C d input 3 0 s output o assign o s 3 a assign o s 2 b assign o s 1 c assign o s 0 d endmodule No 4 to 1 MUX XST User Guide d s o He 5zs sI pa 1 Dz 1 bz The following example does not generate a 4 to 1 1 bit MUX but a 3 to 1 MUX with 1 bit latch The reason is that not all selector values were described in the If statement It is supposed that for the s 11 case O keeps its old value and therefore a memory element is needed www xilinx com 89 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The following table shows pin definitions for a 3 to 1 1 bit MUX with a 1 bit latch IO Pins Description a b c d Data Inputs s 1 0 Selector O Data Output VHDL Code Following is the VHDL code for a 3 to 1 1 bit MUX with a 1 bit latch library ieee use ieee std logic 1164 all entity mux is port a b c d in std logic S in std logic vector 1 downto 0 o out std logic end mux architecture archi of mux is begin process a b C d s begin if s 00 then o lt a elsif s 01 then o lt b elsif s 10 then o lt Cc end if end process end archi Verilog Code Following is the Verilog code for a 3 to 1 1 bit MUX with a 1 bit latch module mux a b c d S O input a b c Gd input 1 0 s output o reg o a
77. bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Seral Out oo derer to de gott eb a CU P SOR was ie era E qol TRE e MER gs 77 VADE Code recie id td REPE TV ER dap wie T7 Verilog Code za oed td ut ede galt ee cast p teen A o a 78 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and Seral OE asec oer dias 78 VHDL Code 3245 pai ii ed ade is A epa ideo 78 Verilog Codes diia 79 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out ccc 79 VADE Code 53533 ies bi de aderit e enbu eii e qa EE EIS 80 Verilog Code a naa aai e doe re dienen derit eines 80 Dynamic Shift Register coi des ds dd rd DELE Ee Ie rds 81 16 bit Dynamic Shift Register with Positive Edge Clock Serial In and Serial Out 81 LOG Bile 2224 oie Ede ehm vei pes teu ra uer RE ER tae d ia 81 Related CONSTE ore eere ce Ce esaet debere ud Rid nase hows eii 82 VEIDE Code iii dtt eee Eae di dd 82 Verilog Code viruta dai d estu blades Quis ask leant Manes echt tuper ciu s 83 MultplexerS cies ipi pai ii dd edid ion dot et 83 Los File iter bt exter UE Ada 86 Related Constraints o 86 4 to 1 1 bit MUX using IF Statement n nanunua nananana rarnana rarena 86 VHDL Cod 1 6 sis aetna oe aee GER RR ERR E RE a ERE 86 Verilog Codes si i bau als Esto bedeutet eoe e ees 87 4 to 1 MUX Using CASE Statement ssssssss ee 87 VEIDE Codec 4a abra dara ber ke
78. bit subtractor 18 bit adder POBRFPP ANY A BR XST User Guide www xilinx com 1 800 255 7778 31 XILINX 32 Chapter 2 HDL Coding Techniques This chapter discusses the following Macro Blocks Registers Tristates Counters Accumulators Shift Registers Dynamic Shift Registers Multiplexers Decoders Priority Encoders Logical Shifters Arithmetic Operators Adders Subtractors Adders Subtractors Comparators Multipliers Dividers RAMs State Machines Black Boxes For each macro both VHDL and Verilog examples are given There is also a list of constraints you can use to control the macro processing in XST Note For macro implementation details please refer to Chapter 3 FPGA Optimization and Chapter 4 CPLD Optimization Table 2 1 provides a list of all the examples in this chapter as well as a list of VHDL and Verilog synthesis templates available from the Language Templates in Project Navigator To access the synthesis templates from Project Navigator 1 Select Edit gt Language Templates 2 Click the sign for either VHDL or Verilog 3 Click the sign next to Synthesis Templates www xilinx com XST User Guide 1 800 255 7778 Introduction 7 XILINX Table 2 1 WHDL and Verilog Examples and Templates Macro Blocks Chapter Examples Language Templates Registers Flip flop with Positive Edge D Flip Flop Clock Flip flop with Negative
79. c users doc granite timer ise hex2led vhd in Library work Architecture hex21led arch of Entity HEX2LED is up to date Compiling vhdl file c users doc granite timer ise stopwatch vhd in Library work Architecture inside of Entity stopwatch is up to date HDL Analysis ki Analyzing Entity lt stopwatch gt Architecture lt inside gt WARNING Xst 766 c users doc granite timer ise stopwatch vhd line 68 Generating a Black Box for component lt tenths gt Entity stopwatch analyzed Unit stopwatch generated Analyzing Entity lt statmach gt Architecture lt inside gt Entity statmach analyzed Unit statmach generated Analyzing Entity decode Architecture lt behavioral gt Entity decode analyzed Unit decode generated Analyzing Entity lt cnt60 gt Architecture lt inside gt Entity lt cnt60 gt analyzed Unit lt cnt60 gt generated Analyzing Entity lt smallcntr gt Architecture lt inside gt Entity lt smallcntr gt analyzed Unit lt smallcntr gt generated Analyzing Entity lt hex2led gt Architecture lt hex2led_arch gt Entity lt hex2led gt analyzed Unit lt hex2led gt generated 338 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File Z XILINX HDL Synthesis Synthesizing Unit lt smallcntr gt Related source file is c users doc granite
80. ce Clock Enable Yes No pld ffopt Flip Flop Optimization Yes No wysiwyg What You See Is What You Get Yes No equivalent Equivalent Register Removal Yes No register removal Table 10 6 Target Options Virtex Virtex E Virtex II Virtex Il Pro Virtex Il Pro X Spartan II Spartan IIETV Run Command Options bufg Description Maximum Number of BUFGs created by XST Values integer Default 4 Virtex E Spartan II E Default 8 Virtex E Spartan 3 Default 16 Virtex II II Pro II Pro X cross clock analysis Enable cross clock domain Yes No optimization equivalent register removal Equivalent Register Yes No Removal glob opt Global Optimization Goal allclocknets inpad to outpad offset in before Offset out after max delay iob Pack I O Registers into True False Auto IOBs iobuf Add I O Buffers Yes No keep hierarchy Keep Hierarchy Yes Soft No www xilinx com 1 800 255 7778 XST User Guide Run Command Z XILINX Table 10 6 Target Options Virtex Virtex E Virtex II Virtex Il Pro Virtex Il Pro X Spartan II Spartan IIETV Run Command Options Description Values max_fanout Maximum Fanout integer Default 500 for Virtex II II Pro II Pro X Spartan 3 Default 100 for Virtex Virtex E Spartan II and Spartan IIE optimize_primitives O
81. circuits can be described with multiple wait statements in a process When using XST several rules must be respected to use multiple wait statements These rules are as follows XST User Guide www xilinx com 275 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support e The process must only contain one loop statement e The first statement in the loop must be a wait statement e After each wait statement a next or exit statement must be defined e The condition in the wait statements must be the same for each wait statement e This condition must use only one signal the clock signal e This condition must have the following form wait on clock signal until clock signal EVENT not clock signal STABLE and clock signal 0O 1 Example 6 22 uses multiple wait statements This example describes a sequential circuit performing four different operations in sequence The design cycle is delimited by two successive rising edges of the clock signal A synchronous reset is defined providing a way to restart the sequence of operations at the beginning The sequence of operations consists of assigning each of the four inputs DATA1 DATA2 DATA3 and DATA4 to the output RESULT Example 6 22 Sequential Circuit Using Multiple Wait Statements library IEEE use IEEE STD LOGIC 1164 all entity EXAMPLE is port DATA1 DATA2 DATA3 DATA4 in STD L
82. command Following is the basic syntax bus delimiter lt gt 111 1 The default is lt gt In Project Navigator set bus delimiter globally with the Bus Delimiter option in the Synthesis Options tab of the Process Properties dialog box in the Project Navigator Case The Case command line option case determines if instance and net names are written in the final netlist using all lower or upper case letters or if the case is maintained from the source Note that the case can be maintained for either Verilog or VHDL synthesis flow Define this option globally with the case command line option of the run command Following is the basic syntax case upper lower maintain The default is maintain In Project Navigator specify case globally with the Case option in the Synthesis Options tab of the Process Properties dialog box Case Implementation Style The Case Implementation Style option vlgcase command line option instructs XST how to interpret Verilog Case statements It has three possible values full parallel and full parallel Ifthe option is not specified then XST implements the exact behavior of the case statements Iffull is used XST assumes that the case statements are complete and avoids latch creation Ifparallel is used XST assumes that the branches cannot occur in parallel and does not use a priority encoder If full parallel is used XST assumes that the case statements are complete and t
83. components Example 6 2 Structural Description of a Half Adder entity NAND2 is port A B in BIT Y out Bit end NAND2 architecture ARCHI of NAND2 is begin Y lt A nand B end ARCHI entity HALFADDER is port X Y E im BIT C S out BIT end HALFADDER architecture ARCHI of HALFADDER is component NAND2 port A B in BIT Y 3 out BIT end component for all NAND2 use entity work NAND2 ARCHI signal S1 S2 S3 BIT begin NANDA NAND2 port map X Y S3 NANDB NAND2 port map X S3 S1 NANDC NAND2 port map S3 Y S2 NANDD NAND2 port map S1 S2 S Cr lt 50 end ARCHI XST User Guide www xilinx com 263 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support The synthesized top level netlist is shown in the following figure X A O S1 NANDB Y B A A NANDA Y S3 NANDD Y Os B B A NANDC Y y 4 B 1c X8952 Figure 6 1 Synthesized Top Level Netlist Recursive Component Instantiation XST supports recursive component instantiation please note that direct instantiation is not supported for recursivity Example 6 3 shows a 4 bit shift register description Example 6 3 4 bit shift register with Recursive Component Instantiation library ieee use ieee std logic 1164 all library unisim use unisim vcomponents all entity single stage is generic sh st integer 4 port CLK in std logic DI in std logic DO
84. continuous assignments combine declaration and assignment Note Delays and strengths given to a continuous assignment are ignored by XST Example of an explicit continuous assignment wire par eq 1 assign par eq 1 select b a Example of an implicit continuous assignment wire temp hold a b Note Continuous assignments are only allowed on wire and tri data types Procedural Assignments Procedural assignments are used to assign values to variables declared as regs and are introduced by always blocks tasks and functions Procedural assignments are usually used to model registers and FSMs XST includes support for combinatorial functions combinatorial and sequential tasks and combinatorial and sequential always blocks Combinatorial Always Blocks Combinatorial logic can be modeled efficiently using two forms of time control the and Verilog time control statements The time control is ignored for synthesis and hence this section describes modeling combinatorial logic with the statement A combinatorial always block has a sensitivity list appearing within parentheses after the word always Q An always block is activated if an event value change or edge appears on one of the sensitivity list signals This sensitivity list can contain any signal that appears in conditions If Case for example and any signal appearing on the right hand side of an assignment By substituting a without parentheses for a
85. conv integer addra lt di end if read addra lt addra read addrb lt addrb end if end if end process doa lt RAM conv integer read addra dob lt RAM conv integer read addrb end syn Verilog Following is the Verilog code for a dual port RAM with one global enable controlling both ports module raminfr clk en we addra addrb di doa dob input clk input en input we input 4 0 addra input 4 0 addrb input 3 0 di output 3 0 doa output 3 0 dob reg 3 0 ram 31 0 reg 4 0 read addra reg 4 0 read addrb always posedge clk begin if ena begin if wea ram addra lt di read_aaddra lt addra read_aaddrb lt addrb end end assign doa ram read_addra assign dob ram read_addrb endmodule XST User Guide www xilinx com 145 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Dual Port RAM with Enable on Each Port The following descriptions are directly mappable onto Block RAM as shown in the following figure ADDRA DOA ADDRB ENA DOB Block ENB RAM WEA DIA CLK Ni X9476 The following table shows pin descriptions for a dual port RAM with enable on each port IO Pins Description clk Positive Edge Clock ena Primary Global Enable Active High enb Dual Global Enable Active High wea Primary Synchronous Write Enable Active High addra Write Address Primary Read Address add
86. dang eek Ye e x b ERN biden REG d babes a EY 66 4 bit Unsigned Up Accumulator with Asynchronous Clear ooooooooo 66 VHDL Code ie xed dr cbe RY bESG XG pee th dene Rx PPS DE eet 66 Verilog Code a ics cen bct debet etd eden ee tede bet A aed 67 Related Constraints ius siad ds Rus PER IU eE ER E ER ERE ERR AE EEG 67 Shift Registers EMT c dep acs 68 10 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Log File A A A E re dis 69 Related Constraints o 70 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out 70 VEDL Code soria a a px ER E RA Rag eek ln ce en aaa 71 Venlog Code o2 siet dls ds os 71 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial OUR pice iddars iets endian acre ea diria birds riada ba dada 72 VHDL Code 2235233 a ii id a GN be RR eR eae 72 Verilog Codes tat tee ile i ter a 73 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial QUE ibarra diaria dra Aa 73 VHDL Code 100 rie 73 Verilog Code vi ibs er VE ede E VRE ie E 74 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Obrint dei tios 74 VHDL Code A A een racer eed 75 Verlo COG isse sate tin e d esti rece pd ci pees ed 75 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out 76 VADE Cl voii a hee ead hae ae es 76 ASI Lr 76 8
87. directory is the xst subdirectory of the current directory Note Xilinx amp strongly suggests that you clean the XST temp directory regularly This directory contains the files resulting from the compilation of all VHDL and Verilog files during all XST sessions Eventually the number of files stored in the dump directory may severely impact CPU performances This directory is not automatically cleaned by XST Launching XST 350 You can run XST in two ways e XST Shell Type xst to enter directly into an XST shell Enter your commands and execute them To run synthesis specify a complete command with all required options before running XST does not accept a mode where you can first enter set option 1 then set option 2 and then enter run All of the options must be set up at once Therefore this method is very cumbersome and Xilinx suggests that you use the script file method e Script File You can store your commands in a separate script file and run all of them at once To execute your script file run the following workstation or PC command xst ifn in file name ofn out file name intstyle silent ise xflow Note The ofn option is not mandatory If you omit it XST automatically generates a log file with the file extension srp and all messages display on the screen Use the intstyle silent option and the XIL XST HIDEMESSAGES environment variable to limit the number of messages printed to the screen See
88. e Case Implementation Style e Mux Extraction e Resource Sharing Xilinx amp Specific Options From the Process Properties dialog box for the Synthesize process select the Xilinx amp Specific Options tab to display the options For FPGA device families the following dialog box displays 214 Synthesis Option HDL Option ilins Specific Options Property Name Add 1 0 Buffers Max Fanout Number of Clock Buffers Register Duplication Equivalent Register Removal Register Balancing Move First Flip Flop Stage Move Last Flip Flop Stage Pack 1 0 Registers into IDBs Slice Packing Optimize Instantiated Primitives Figure 5 5 Xilinx Specific Options FPGAs www xilinx com 1 800 255 7778 XST User Guide Setting Global Constraints and Options 7 XILINX Following is the list of the Xilinx Specific Options for FPGAs e Add I O Buffers e Max Fanout Number of Clock Buffers e Register Duplication e Equivalent Register Removal e Register Balancing e Move Last Stage e Move First Stage e Pack I O Registers into IOBs e Slice Packing e Optimize Instantiated Primitives To view this option go the Edit drop down menu click Preferences click the Processes tab and set the Property Display Level to Advanced For CPLD device families the following dialog box displays Synthesis Option HDL Option ilins Specific
89. e Optimization Goal speed e Keep Hierarchy no e Macro Preserve no Try 4 Apply the equation shaping algorithm Options to be selected e Optimization effort 2 e Macro Preserve no e Keep Hierarchy no The CPU time increases from Try 1 to Try 4 Obtaining the best frequency depends on the CPLD fitter optimization Xilinx recommends running the multi level optimization of the CPLD fitter with different values for the pterms options starting with 20 and finishing with 50 with a step of 5 Statistically the value 30 gives the best results for frequency How to Fit a Large Design 208 If a design does not fit in the selected device exceeding the number of device macrocells or device P Term capacity you must select an area optimization for XST Statistically the best area results are obtained with the following options e Optimization effort 1 or 2 e Optimization Goal area e Default values for other options Another option that you can try is wysiwyg yes This option may be useful when the design cannot be simplified by the optimization process and the complexity in number of P Terms is near the device capacity It may be that the optimization process trying to reduce the number of levels creates larger equations therefore increasing the number of P Terms and so preventing the design from fitting By validating this option the number of P Terms is not increased and the design fitting may be successful www x
90. ed ed ep a REA cane aus 88 Verilog Coderss varia ti td 88 4 to 1 MUX Using Tristate Buffers oooooocccocoorrrcccnnnrrrncc ne 89 VHDL Code visi ced ku ue eee ees Leta RA a a a eS 89 Verilog Code iss bu REPE RESI bine BRE LEE ikea cious sitee biden bod 89 No 4 to I MUX ii di a auk Rh EE ERE 89 VEIDE Codes us petes et ex e bate vales etel qat ad ace a He EG 90 Verilog Codes re coestuptss eoe te A oque ursi E ae neice petuo A 90 XST User Guide www xilinx com 11 1 800 255 7778 7 XILINX Decoder do oa D 91 Bog A d DI EU 91 Related Constraints o ooooooorr err hes 91 VHDL One EHot RE ER a EE EE Ep EE ERE UM E ERES 91 Verilog One Hot izescek ie e d vy e Pete Shed oi ye bear ede d 92 VHDL One Cold ssessssseeeeeseeeee e hr 92 Verilog On Cold 2 exec ioe eme ke RE A crea teen pA gr EE 93 Decoders with Unselected Outputs a 0666 93 VHDL No Decoder Inference 0 0 cece cette eee nen eens 94 Verilog No Decoder Inference 6 6 eee cette eee 94 VHDL Code Decoder Inference 1 0 0 cece tenet nh 95 Verilog Code Decoder Inference 2 6 cece cece tenes 95 Priority Encoders conil EE a es 96 Log File 3a e tee erint rete isla 96 3 Bit 1 of 9 Priority Encoder 0 cen eens 96 Related Constrainit e ci ed oda grade 96 VADE id a aida a hale 96 Verlo Sn ace cheng ee Pian tates athe ah hens iE ees ee Pas 97 Logical SBEEIEOTS iia ios cede ede deletae qp a adeo ioo a
91. edge clock and asynchronous clear library ieee use ieee std_logic_1164 all entity flop is port C D CLR in std logic Q out std logic end flop architecture archi of flop is begin process C CLR begin if CLR 1 then Q lt 0 elsif C event and C 0 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a flip flop with a negative edge clock and asynchronous clear module flop C D CLR Q input C D CLR output Q reg Q always negedge C or posedge CLR begin if CLR Q 1 b0 else Q D end endmodule Flip flop with Positive Edge Clock and Synchronous Set The following figure shows a flip flop with positive edge clock and synchronous set X3722 42 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Registers The following table shows pin definitions for a flip flop with positive edge clock and synchronous set IO Pins Description D Data Input C Positive Edge Clock S Synchronous Set active High Q Data Output VHDL Code Following is the equivalent VHDL code for the flip flop with a positive edge clock and synchronous set library ieee use ieee std logic 1164 al l entity flop is port C DS t im std Logic O out std logic end flop architecture archi of flop is begin process C begin if C event and C 1 then if S 1 then Q lt 1 else O lt D
92. endmodule XST User Guide www Xilinx com 49 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Latch with Inverted Gate and Asynchronous Preset The following figure shows a 4 bit latch with an inverted gate and an asynchronous preset PRE x8376 The following table shows pin definitions for a latch with an inverted gate and an asynchronous preset IO Pins Description D 3 0 Data Input G Inverted Gate PRE Asynchronous Preset active High Q 3 0 Data Output VHDL Code Following is the equivalent VHDL code for a 4 bit latch with an inverted gate and an asynchronous preset library ieee use ieee std logic 1164 a11 entity latch is port D in std logic vector 3 downto 0 G PRE in std logic Q out std logic vector 3 downto 0 end latch architecture archi of latch is begin process PRE G begin if PRE 1 then Q lt T1111 elsif G 0 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a 4 bit latch with an inverted gate and an asynchronous preset 50 www xilinx com XST User Guide 1 800 255 7778 Tristates Z XILINX module latch G D PRE Q input G PRE input 3 0 D output 3 0 O reg 3 0 Q always G or D or PRE begin if PRE Q 4 b1111 else if G Q D end endmodule Tristates Tristate elements can be described using the f
93. family name is a list of supported Xilinx families in the current version of XST command name is one of the following XST commands run set elaborate time To get a list of supported families type help at the command line prompt with no argument XST displays the following message gt help ERROR Xst 1356 Help Missing arch family Please specify what family you want to target available families spartan3 spartan2 spartan2e virtex virtex2 virtex2p virtexe xbr xc9500 xc9500x1 xpla3 cr2s To get a list of available commands for a specific family type the following at the command line prompt with no argument help arch family name For example help arch virtex Example Use the following command to get a list of available options and values for the run command for Virtex II help arch virtex2 command run www xilinx com XST User Guide 1 800 255 7778 Set Command 7 XILINX This command gives the following output mult style Multiplier Style block lut auto pipe lut bufg Maximum Global Buffers bufgce BUFGCE Extraction YES NO decoder extract Decoder Extraction YES NO ifn 4 ifmt Mixed VHDL Verilog Ofn ofmt NGC NCD p ent top z opt mode AREA SPEED opt level 1 2 keep hierarchy YES NO vlgpath vlgincdir verilog2001 YES NO vlgcase
94. for a 4 bit unsigned up counter with an asynchronous clear library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity counter is port C CLR in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp lt tmp 1 end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with asynchronous clear module counter C CLR O input C CLR output 3 0 Q reg 3 0 tmp always posedge C or posedge CLR begin if CLR tmp 4 50000 else tmp tmp 1 b1 end assign Q tmp endmodule XST User Guide www xilinx com 55 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Unsigned Down Counter with Synchronous Set The following table shows pin definitions for a 4 bit unsigned down counter with a synchronous set IO Pins Description C Positive Edge Clock S Synchronous Set active High Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned down counter with a synchronous set library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity counter is port C S in std logic Q out std logic vector 3 downto 0 end counter architecture ar
95. for signal tmp An INIT value equal 1011 is attached to the inferred register and propagated to the final netlist library ieee use ieee std_logic_1164 all entity test is port CLK in std_logic DO out std_logic_vector 3 downto 0 end test architecture beh of test is signal tmp std logic vector 3 downto 0 1011 begin process CLK begin if clk event and clk 1 then tmp lt DI end if end process DO tmp end beh XST User Guide www xilinx com 199 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization To infer a register in the previous example and place it in a specific location of a chip attach an RLOC constraint to the tmp signal as in the following VHDL example XST propagates it to the final netlist Please note that this feature is supported for registers only not for inferred RAMs PCI Flow library ieee use ieee std logic 1164 all entity test is port CLK in std logic DI in std logic vector 3 downto 0 DO out std logic vector 3 downto 0 end test architecture beh of test is signal tmp std logic vector 3 downto 0 1011 attribute RLOC string attribute RLOC of tmp signal is X3Y0 X2YO X1YO XOYO begin process CLK begin if clk event and clk 1 then tmp lt DI end if end process DO tmp end beh To successfully use PCI flow with XST i e to satisfy all placement constraints and meet timing requi
96. ieee std logic unsigned all entity raminfr is port Clk in std logic we in std logic en in std logic addr in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr 124 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Z XILINX architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv integer addr lt di do lt di else do lt RAM conv_integer addr end if end if end if end process end syn The following templates show an alternate configuration of a single port RAM in write first mode with a registered read address coded in VHDL library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity raminfr is port Clk in std logic we in std logic en in std logic addr in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addr std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then mem conv integer addr lt di end if
97. information about the number of clocks in the design how each clock is buffered and how many loads it has Timing report contains Timing Summary and Detailed Timing Report For more information see Log File Analysis in Chapter 3 Encrypted Modules if a design contains encrypted modules XST hides the information about these modules Reducing the Size of the LOG File There are several ways to reduce the size of the LOG file generated by XST They are as follows 334 Quiet Mode Quiet Mode Silent Mode Hiding specific messages Quiet mode allows you to limit the number of messages that are printed to the computer screen stdout This mode can be invoked by using the intstyle command line switch with its value set to either ise or xflow as appropriate You can also use the old quiet switch but Xilinx strongly recommends that you not use this method because it will become obsolete in coming releases Normally XST prints the entire log to stdout In quiet mode XST does not print the following portions of the log to stdout Copyright Message Table Of Contents Synthesis Options Summary The following portions of the Final Report Final Results header for CPLDs Final Results section for FPGAs The following note in the Timing Report www xilinx com XST User Guide 1 800 255 7778 Reducing the Size of the LOG File lt XILINX Silent mode NOTE THESE TIMING NUMBERS ARE ONL
98. is up to date Incremental synthesis Unit lt levb gt is up to date Incremental synthesis Unit lt top gt is up to date Optimizing unit lt my_sub gt Optimizing unit lt my_add gt Optimizing unit leva 1 Optimizing unit leva 2 Optimizing unit leva If you have e previously run XST in non incremental mode and then switched to incremental mode or e the decomposition of the design was changed you must delete all previously generated NGC files before continuing Otherwise XST issues an error If in the previous example adding incremental synthesis true to the block LEVA 1 XST gives the following error ERROR Xst 624 Could not find instance inst leva 1 of cell leva 1 in leva The problem most likely occurred because the design was previously run in non incremental synthesis mode To fix the problem remove the existing NGC files from the project directory Speed Optimization Under Area Constraint XST User Guide Starting from the 5 1i release XST performs timing optimization under area constraint This option Slice Utilization Ratio is available under the XST Synthesis Options in the Process Properties dialog box in Project Navigator By default this constraint is set to 10076 of selected device size This constraint has influence at low level synthesis only it does not control the inference process If this constraint is specified XST ma
99. main categories of incremental synthesis e Block Level The synthesis tool re synthesizes the entire block if at least one modification was made inside this block e Gate or LUT Level The synthesis tool tries to identify the exact changes made in the design and generates the final netlist with minimal changes XST supports block level incremental synthesis with some limitations Incremental Synthesis is implemented using two constraints INCREMENTAL SYNTHESIS and RESYNTHESIZE XST User Guide www xilinx com 183 1 800 255 7778 7 XILINX 184 Chapter 3 FPGA Optimization INCREMENTAL_SYNTHESIS Use the INCREMENTAL_SYNTHESIS constraint to control the decomposition of the design on several groups If this constraint is applied to a specific block this block with all its descendents are considered as one group until the next INCREMENTAL_SYNTHESIS constraint is found During synthesis XST generates a single NGC file for the group In the current release you cannot apply the INCREMENTAL_SYNTHESIS constraint to a block that is instantiated multiple times If this occurs XST issues the following error ERROR Xst 1344 Cannot support incremental synthesis on block my sub instantiate several times If a a single block is changed then the entire group is resynthesized and a new NGC file s is generated Please note that starting from the 5 2i release the INCREMENTAL SYNTHESIS switch is NO LONGER accessible via the X
100. no model no yes no entity Spartan I IIE 3 true false Virtex M TI II Pro II Pro X E rom extract yes no model yes yes no entity signal Spartan I IIE 3 true false net in model Virtex TI TII Pro II Pro X E rom_style auto block model yes auto block entity signal Spartan IT IIE 3 distributed net in model distributed Virtex TI II Pro II Pro X E shift_extract yes no model yes yes no entity signal Spartan IT IIE 3 true false net in model Virtex1M I II Pro II Pro X E shreg extract yes no model yes yes no entity signal Spartan IT IIE 3 true false net in model Virtex TI TII Pro II Pro X E signal auto one hot model yes auto one hot entity signal Spartan II ME 3 _encoding user net in model user Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS slice integer model yes integer entity Spartan IT TE 3 _utilization range 0 100 range 0 100 Virtex I II Pro _ratio II Pro X E slice integer model yes integer entity Spartan IT TE 3 _utilization range 0 100 range 0 100 Virtex M TI II Pro _ratio II Pro X E _maxmargin translate_off na na no no value local Spartan IT IIE 3 no target Virtex M 11 11 Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS XST User Guide www xilinx com 1 800 255 7778 243 7 XILINX Table 5 1 XST Specific Non timing Options
101. of the designs remains the same Only timing delays are modified Flip flop Retiming is part of global optimization and it respects the same constraints as all the other optimization techniques Retiming is an iterative process therefore a flip flop that is the result of a retiming can be moved again in the same direction forward or backward if it results in better timing The only limit for the retiming is when the timing constraints are satisfied or if no more improvements in timing can be obtained For each flip flop moved a message is printed specifying the original and new flip flop names and if itis a forward or backward retiming Note the following limitations e Hip flop retiming is not applied to flip flops that have the IOB TRUE property e Flip flops are not moved forward if the flip flop or the output signal has the KEEP property e Flip flops are not moved backward if the input signal has the KEEP property e Instantiated flip flops are not moved e Flip flops with both a set and a reset are not moved Flip flop retiming can be controlled by applying the REGISTER BALANCING MOVE FIRST STAGE and MOVE LAST STAGE constraints Incremental Synthesis Flow The main goal of Incremental Synthesis flow is to reduce the overall time that the designer spends in completing a project This can be achieved by allowing you to re synthesize only the modified portions of the design instead of the entire design We may consider two
102. one Verilog file create a project To create a project file place a list of VHDL files preceded by keyword vhdl and a list of Verilog files preceded by keyword verilog in a separate file The order of the files is not important XST is able to recognize the hierarchy and compile VHDL files in the correct order XST User Guide www xilinx com 363 1 800 255 7778 7 XILINX 364 Chapter 10 Command Line Mode For our example 1 2 Script Mode Open a new file called watchver prj Enter the names of the Verilog files into this file in any order and save it vhdl work decode vhd vhdl work statmach vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work tenths vhd verilog work hex2led v To synthesize the design execute the following command from the XST shell or via a script file run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 If you want to synthesize just HEX2LED and check its performance independently of the other blocks you can specify it as the top level module to synthesize on the command line by using the top option please refer to Table 10 3 page 352 for more information run ifn watchver prj ifmt mixed top hex2led ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 It can be very tedious work entering XST commands directly into the XST shell especially
103. overloaded arithmetic operators on these types It also defines conversion and extended functions for these types e numeric std supports types unsigned signed vectors based on type std logic This package is equivalent to std logic arith e math real supports the following Real number constants as shown in the following table Constant Value Constant Value math_e e math log of 2 1n2 math_1_over_e 1 e math log of 10 In10 math pi T math_log2_of_e log5e math 2 pi 2x math log10 of e log pe math_1_over_pi 1 7 math_sqrt_2 J2 math_pi_over_2 n 2 math_1_oversqrt 2 1 42 www xilinx com 281 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Constant Value Constant Value math_pi_over_3 1 3 math_sqrt_pi In math pi over 4 n 4 math deg to rad 21 360 math 3 pi over 2 3 2 math rad to deg 360 27 Real number functions as shown in the following table ceil x realmax xy exp x cos x cosh x floor x realmin xy log x tan x tanh x round x sqrt x log2 x arcsin x arcsinh x trunc x cbrt x log10 x arctan x arccosh x sign x ny log x y arctan yx arctanh x mod x y x y sin x sinh x The procedure uniform which generates successive values between 0 0 and 1 0 Note Functions and procedures in the math real package as well as the real type are for calculations only Th
104. res 8 b00000100 3 b011 res 8 b00001000 3 b100 res 8 b00010000 3 b101 res 8 b00100000 110 and 111 selector values are unused default res 8 bXxxxxxxxx endcase end endmodule XST User Guide www xilinx com 95 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Priority Encoders 96 Log File XST can recognize a priority encoder but in most cases XST does not infer it To force priority encoder inference use the PRIORITY_EXTRACT constraint with the value force Xilinx strongly suggests that you use this constraint on a signal by signal basis otherwise the constraint may guide you towards sub optimal results The XST log file reports the type and size of recognized priority encoders during the Macro Recognition step Synthesizing Unit priority Related source file is priority encoders l vhd Found 3 bit 1 of 9 priority encoder for signal code Summary inferred 3 Priority encoder s Unit priority synthesized HDL Synthesis Report Macro Statistics Priority Encoders dl 3 bit l of 9 priority encoder 1 3 Bit 1 of 9 Priority Encoder Note For this example XST may infer a priority encoder You must use the PRIORITY_EXTRACT constraint with a value force to force its inference Related Constraint VHDL A related constraint is PRIORITY_EXTRACT Following is the VHDL code for a 3 bit 1 of 9 Priority Encoder library ieee u
105. script file run ifn watchver v ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 If you want to synthesize just HEX2LED and check its performance independently of the other blocks you can specify the top level module to synthesize in the command line using the top option please refer to Table 10 3 page 352 for more information run ifn watchver v ifmt Verilog ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 top HEX2LED Script Mode 362 It can be very tedious work entering XST commands directly into the XST shell especially when you have to specify several options and execute the same command several times You can run XST in a script mode as follows 1 Open a new file called xst t xt in the current directory Put the previously executed XST shell command into this file and save it run ifn watchver prj ifmt mixed ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 2 From the tesh or other shell enter the following command to start synthesis xst ifn xst txt During this run XST creates the following files watchvhd ngc an NGC file ready for the implementation tools xst srp the xst script log file 3 Ifyou want to save XST messages in a different log file for example wat chvhd log you must execute the following command xst ifn xst txt ofn watchver log www xilinx com XST User Gu
106. signal or variable can be completely used ATRIX15 lt CNST_A Just an index of one row of the array can be specified ATRIX15 5 lt TAB_A Just indexes of the maximum number of dimensions can be specified ATRIX15 5 0 0 lt 1 Just a slice of one row can be specified ATRIX15 4 4 downto 1 lt TAB_B 3 downto 0 Note also that the indices may be variable XST supports record types An example of a record is shown below type REC1 is record fieldl std_logic field2 std_logic_vector 3 downto 0 end record e Record types can contain other record types e Constants can be record types e Record types cannot contain attributes e XST supports aggregate assignments to record signals www xilinx com 259 1 800 255 7778 XILINX Initial Values Chapter 6 VHDL Language Support In VHDL you can initialize registers when you declare them The value e Must be a constant e Cannot depend on earlier initial values e Cannot be a function or task call e Can be a parameter value propagated to a register When you give a register an initial value in a declaration XST sets this value on the output of the register at global reset or at power up A value assigned this way is carried in the NGC file as an INIT attribute on the register and is independent of any local reset Example signal arb onebit std logic 0 signal arb priority std logic vector 3 downto 0 1011 You can also assign a set
107. the genvar variable e The contents of the for loop must be enclosed by begin and end statements and the begin statement must be named with a unique qualifier www xilinx com 309 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support The following is an example of an 8 bit adder using a generate for loop generate genvar 1 for i20 i lt 7 i i 1 begin for name adder add a 8 i 7 8 i b 8 i 7 8 i ci i sum for 8 i 7 8 i cO or i 1 end endgenerate Generate If else A generate if statement can be used inside a generate block to conditionally control what objects get generated The following is an example of a generate If else statement The generate controls what type of multiplier is instantiated Please note that the contents of each branch of the if else statement must be enclosed by begin and end statements and the begin statement must be named with a unique qualifier generate if IF WIDTH 10 begin if name adder 4 IF WIDTH ul a b sum if end else begin else nam subtractor IF WIDTH u2 a b sum if end endgenerate Generate Case A generate case statement can be used inside a generate block to conditionally control what objects get generated Use a generate case statement when there are several conditions to be tested to determine what the generated code would be Please note that each test statement in a generate case statement must be enclosed by be
108. the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xilinx Inc does not represent that devices shown or products described herein are free from patent
109. timer ise smallcntr vhd Found 4 bit up counter for signal qgoutsig Summary inferred 1 Counter s Unit lt smallcntr gt synthesized Synthesizing Unit lt hex2led gt Related source file is c users doc granite timer ise hex2led vhd Found 16x7 bit ROM for signal lt LED gt Summary inferred 1 ROM s Unit lt hex2led gt synthesized Synthesizing Unit lt cnt60 gt Related source file is c users doc granite timer ise cnt60 vhd Unit lt cnt60 gt synthesized Synthesizing Unit decode Related source file is c users doc granite timer ise decode vhd Found 16x10 bit ROM for signal one hot Summary inferred 1 ROM s Unit lt decode gt synthesized Synthesizing Unit lt statmach gt Related source file is c users doc granite timer ise statmach vhd Found finite state machine FSM 0 for signal current state States 6 Transitions 11 Inputs 1 Outputs 6 Clock CLK rising edge Reset RESET positive Reset type asynchronous Reset State 000001 Power Up State 000001 Encoding automatic Implementation LUT Summary inferred 1 Finite State Machine s Unit lt statmach gt synthesized XST User Guide www xilinx com 339 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis Synthesizing Unit lt stopwatch gt Related source file is c users doc granite timer ise stopwatch vhd WARNING Xst 646 Signal lt strtstopinv gt is assigned but neve
110. to insert any I O Buffers set this option to no This option is useful to synthesize a part of a design to be instantiated later on When the yes value is selected IBUF and OBUF primitives are generated IBUF OBUF primitives are connected to I O ports of the top level module When XST is called to synthesize an internal module which will be instantiated later in a larger design you must select no for this option If I O buffers are added to a design this design cannot be used as a submodule of another design Define this option globally with the iobuf command line option of the run command Following is the basic syntax iobuf yes no The default is yes www xilinx com 219 1 800 255 7778 lt XILINX 220 Chapter 5 Design Constraints In Project Navigator specify iobuf globally with the Add IO Buffers option in the Xilinx Specific Options tab of the Process Properties dialog box Box Type The Box Type BOX_TYPE constraint instructs XST not to synthesize the behavior of a model and to use some predefined set of characteristics for that model s behavior See BOX_TYPE in the Constraints Guide for details Bus Delimiter The Bus Delimiter bus_delimiter command line option defines the format used to write the signal vectors in the result netlist The available possibilities are lt gt The default is lt gt Define this option globally with the bus delimiter command line option of the run
111. transport or guarded options no waveforms Component Instantiation Statement Supported For Generate Statement supported for constant bounds only Tf Generate Statement supported for static condition only VHDL Reserved Words XST User Guide The following table shows the VHDL reserved words abs configuration impure null rem type access constant in of report unaffected after disconnect inertial on return units alias downto inout open rol until all else is or ror use and elsif label others select variable architectur end library out severity wait e array entity linkage package signal when assert exit literal port shared while attribute file loop postponed sla with begin for map procedure sll xnor block function mod process sra xor body generate nand pure srl buffer generic new range subtype bus group next record then case guarded nor register to component if not reject transport www xilinx com 1 800 255 7778 289 7 XILINX Chapter 6 VHDL Language Support 290 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support Introduction XST User Guide This chapter contains the following sections e Introduction e Behavioral Verilog Features e Structural Verilog Features e Parameters e Verilog Li
112. value primitive is attached to each primitive in the UNISIM library Please note that if you instantiate a block non primitive in your design and e the block has no contents no logic description or e the block has a logic description but you attach a BOX TYPE constraint to it with a value of user_black_box then XST issues a warning message as in the following log file sample Analyzing Entity lt black_b gt Architecture lt archi gt WARNING VHDL 0103 c jm des vhd Line 23 Generating a Black Box for component my block Entity black b analyzed Unit black b generated Related Constraints Related constraints are BOX TYPE and the various PAR constraints that can be passed from HDL to NGC without processing Cores Processing If a design contains cores represented by an EDIF or an NGC file XST can automatically read them for timing estimation and area utilization control The Read Cores option in the Synthesis Options in the Process Properties dialog box in Project Navigator allows you to enable or disable this feature By default XST reads cores In the following VHDL example 196 www xilinx com XST User Guide 1 800 255 7778 Cores Processing 7 XILINX the block my_add is an adder which is represented as a black box in the design whose netlist was generated by CORE Generator library ieee use ieee std logic 1164 all use ieee std logic signed all entity read cores
113. we 1 then RAM conv integer wa lt di end if end if end process dol lt RAM conv integer ral do2 lt RAM conv integer ra2 end syn Verilog Following is the Verilog code for a multiple port RAM module raminfr clk we wa ral ra2 di dol input clk input we input 4 0 wa input 4 0 ral input 4 0 ra2 input 3 0 di output 3 0 dol output 3 0 do2 reg 3 0 ram 31 0 always posedge clk begin if we ram wa lt di end assign dol ram ral assign do2 ram ra2 endmodule Block RAM with Reset XST supports block RAM with reset on the data outputs as offered with Virtex Virtex II and related block RAM resources Optionally you can include a synchronously 152 controlled initialization of the RAM data outputs do2 Block RAM with the following synchronization modes can have resetable data ports e Read First Block RAM with Reset e Write First Block RAM with Reset e No Change Block RAM with Reset e Registered ROM with Reset e Supported Dual Port Templates Note Because XST does not support block RAMs with dual write in a dual read block RAM description both data outputs may be reset but the various read write synchronizations are only allowed for the primary data output The dual output may only be used in read first mode www xilinx com 1 800 255 7778 XST User Guide RAMS ROMs XST User Guide 7 XILINX The following example show
114. when you have to specify several options and execute the same command several times You can run XST in a script mode as follows 1 Open a new file called xst txt in the current directory Put the previously executed XST shell command into this file and save it run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 From the tcsh or other shell enter the following command to start synthesis xst ifn stopwatch xst During this run XST creates the following files watchvhd ngc an NGC file ready for the implementation tools xst srp the xst script log file If you want to save XST messages in a different log file for example watchvhd log execute the following command xst ifn stopwatch xst ofn watchver log You can improve the readability of the xst scr file especially if you use many options to run synthesis You can place each option with its value on a separate line respecting the following rules The first line must contain only the run command without any options There must be no blank lines in the middle of the command Each line except the first one must start with a dash www xilinx com XST User Guide 1 800 255 7778 Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode 7 XILINX For the previous command example the stopwatch xst file should look like the following run ifn watchver prj ifmt
115. yes yes no force entity signal Spartan II IIE 3 extract true false net in model Virtex II II Pro II Pro X E ram extract yes no model yes yes no entity signal Spartan IT IIE 3 true false net in model Virtex TI II Pro II Pro X E ram style auto block model yes auto block entity signal Spartan IT IIE 3 distributed net in model distributed Virtex II II Pro II Pro X E register yes no model yes yes no entity signal Spartan IT IIE 3 balancing forward net in model forward FF instance Virtex TI II Pro backward inst in model backward name II Pro X E true false primary clock signal register yes no model yes yes no entity signal Spartan IT IIE 3 duplication true false net in model Virtex TI II Pro II Pro X E register string net in model no string type in XC9500 _powerup VHDL only CoolRunner XPLA3 II IIS 242 www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX Table 5 1 XST Specific Non timing Options Command Command XCF XCF T E p Constraint Constraint Constraint Line Old XST Old XST Technology Name Syntax Syntax Value Target Constraint Constraint Syntax Syntax Value Target resource yes no model yes yes no entity signal Spartan II TIE 3 sharing true false net in model Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS resynthesize yes
116. you can use the following arithmetic packages and types that operate on unsigned values PACKAGE TYPE numeric_std unsigned std_logic_arith unsigned std_logic_unsigned std_logic_vector To create a signed adder you can use arithmetic packages and types that operate on signed values PACKAGE TYPE numeric_std signed std_logic_arith signed std_logic_signed std_logic_vector Please refer to the IEEE VHDL Manual for details on available types Registers XST recognizes flip flops with the following control signals e Asynchronous Set Clear e Synchronous Set Clear e Clock Enable Log File The XST log file reports the type and size of recognized flip flops during the Macro Recognition step Synthesizing Unit lt flop gt Related source file is ff_l vhd Found 1 bit register for signal lt q gt Summary inferred 1 D type flip flop s Unit lt flop gt synthesized HDL Synthesis Report Macro Statistics Registers 1 bit register XST User Guide www xilinx com 39 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Related Constraints Related constraints are IOB REGISTER_DUPLICATION EQUIVALENT REGISTER REMOVAL REGISTER_BALANCING Flip flop with Positive Edge Clock The following figure shows a flip flop with positive edge clock X3715 The following table shows pin definitions for a flip flop with positive edge clock
117. 0 255 7778 2 XILINX Chapter 6 VHDL Language Support Allows the design of a system to be simulated prior to being implemented and manufactured This feature allows you to test for correctness without the delay and expense of hardware prototyping Provides a mechanism for easily producing a detailed device dependent version of a design to be synthesized from a more abstract specification This feature allows you to concentrate on more strategic design decisions and reduce the overall time to market for the design Data Types in VHDL XST accepts the following VHDL basic types 256 Enumerated Types BIT 0 1 BOOLEAN false true REAL to STD LOGIC U X 0 1 ZW L H where U means uninitialized X means unknown 0 means low T means high Z means high impedance W means weak unknown L means weak low H means weak high means don t care For XST synthesis the 0 and L values are treated identically as are 1 and H The X and values are treated as don t care The U and W values are not accepted by XST The Z value is treated as high impedance User defined enumerated type type COLOR is RED GREEN YELLOW Bit Vector Types BIT VECTOR STD LOGIC VECTOR Unconstrained types types whose length is not defined are not accepted Integer Type INTEGER The following types are VHDL predefined types BIT BOOLEAN BIT VECTO
118. 00 RES2 lt 00000000 elsif CLK event and clk 1 then RES1 lt A B RES2 lt C D end if end process end beh VERILOG module no vlogic bram clk rst A B C D input clk rst input 7 0 A B C D output 7 0 RES1 RES2 reg 7 0 RES1 RES2 ESI ES2 synthesis attribute bram map of no vlogic bram is yes always posedge clk or posedge rst begin if rst RES1 8 b0000000 else RES1 A B end always 8 posedge clk or posedge rst begin if rst RES2 8 b0000000 else RES2 C D end endmodule LOG Advanced HDL Synthesis K INFO Xst Unable to map block lt no_logic_bram gt on BRAM Output FF lt RES1 gt must have a synchronous reset 182 www Xilinx com 1 800 255 7778 XST User Guide Flip Flop Retiming 7 XILINX Flip Flop Retiming Flip flop Retiming is a technique that consists of moving flip flops and latches across logic for the purpose of improving timing and so increasing clock frequency Flip flop retiming can be either forward or backward Forward retiming moves a set of flip flops that are the input of a LUT to a single flip flop at its output Backward retiming moves a flip flop that is at the output of a LUT to a set of flip flops at its input Flip flop retiming can significantly increase the number of flip flops in the design and it may remove some flip flops Nevertheless the behavior
119. 00 255 7778 25 7 XILINX Chapter 1 Introduction 5 When a design is ready to synthesize you can invoke XST in Project Navigator With the top level source file selected double click Synthesize XST in the Process window ES File Edi View Project Source Process Window six Sources in Project readme 4 cv50 6bg256 B stopwatch tb stopwatch tb tbw 5 ES stopwatch stopwatch sch E ent60 cntBO sch decode decode vhd hex2led hex2led vhd outs3 outs3 sch stmach v stmach_w vhd tenths tenths co I EG Module View Library View ix Processes for Source decode Ei Add Existing Source El Create New Source i2 Design Entry Utilities 3 Create Schematic Symbol E A View Command Line Log File B View VHDL Instantiation Template E User Constraints 3 fo Create Timing Constraints ES Assign Package Pins B Create Area Constraints le Edit Constraints Text 4655S D B ef View Synthesis Report BE View RTL Schematic oA Check Syntax SQ Y Implement Design E Go Translate BE Process View Note To run XST from the command line refer to Chapter 10 Command Line Mode for details 26 www xilinx com XST User Guide 1 800 255 7778 XST in Project Navigator 7 XILINX 6 When synthesis is complete view the results by double clicking View Synthesis Report Following is a portion of a sample r
120. 0011 data 4 b0010 4 b0100 data 4 b0100 4 50101 data 4 b1010 4 b0110 data 4 b1100 4 b0111 data 4 b0000 4 b1000 data 4 b1010 4 51001 data 4 b0010 4 51010 data 4 b1110 4 p1011 data 4 b0010 4 b1100 data 4 b0100 4 b1101 data 4 b1010 4 b1110 data 4 b1100 4 b1111 data 4 b0000 default data 4 bXXXX endcase end endmodule XST User Guide www xilinx com 159 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques State Machine XST proposes a large set of templates to describe Finite State Machines FSMs By default XST tries to distinguish FSMs from VHDL Verilog code and apply several state encoding techniques it can re encode the user s initial encoding to get better performance or less area However you can disable FSM extraction by using the F5M EXTRACT design constraint Please note that XST can handle only synchronous state machines There are many ways to describe FSMs A traditional FSM representation incorporates Mealy and Moore machines as in the following figure Please note that XST supports both of these models Output State Outputs Register Function Inputs Function 9 Only for Mealy Machine X8993 For HDL process VHDL and always blocks Verilog are the most suitable ways for describing FSMs For description convenience Xilinx uses process to refer to both VHDL processes and Verilog always blocks You may ha
121. 01 1010 1011 1100 1101 1110 1111 signal raddr std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then raddr lt addr end if end if end process data lt ROM conv integer raddr end syn Verilog Following is Verilog code for a ROM with registered output module rominfr clk en addr data input clk input en input 4 0 addr output 3 0 data 158 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Z XILINX always posedge clk begin if en case addr 4 b0000 data 4 b0010 4 b0001 data 4 b0010 4 50010 data 4 b1110 4 50011 data 4 b0010 4 b0100 data 4 b0100 4 50101 data 4 b1010 4 50110 data 4 b1100 4 b0111 data 4 b0000 4 b1000 data 4 b1010 4 b1001 data 4 b0010 4 b1010 data 4 b1110 4 b1011 data 4 b0010 4 b1100 data 4 b0100 4 b1101 data 4 b1010 4 b1110 data 4 b1100 4 b1111 data 4 b0000 default data 4 bXXXX endcase end endmodule Following is Verilog code for a ROM with registered address module rominfr clk en addr data input clk input en input 4 0 addr output 3 0 data reg 4 0 raddr always posedge clk begin if en raddr addr end always raddr begin if en case raddr 4 b0000 data 4 b0010 4 50001 data 4 b0010 4 50010 data 4 b1110 4 5
122. 1 gt 0 1 0 738 1 265 LUT 54 end scope blockl1 LUT3 10 gt 0 1 0 138 0 000 I next state 2 FDC D 0 440 I state 2 Total 7 523ns Timing Summary The Timing Summary section gives a summary of the timing paths for all 4 domains e The path from any clock to any clock in the design 7 523ns inimum period Maximum Frequency 132 926MHz e The maximum path from all primary inputs to the sequential elements The The inimum input arrival time before clock 8 945ns maximum path from the sequential elements to all primary outputs 14 220ns aximum output required time before clock maximum path from inputs to outputs aximum combinational path delay 10 899ns If there is no path in the domain concerned No path found is then printed instead of the value 192 www xilinx com XST User Guide 1 800 255 7778 Implementation Constraints 7 XILINX Timing Detail The Timing Detail section describes the most critical path in detail for each region The start point and end point of the path the maximum delay of this path and the slack The start and end points can be Clock with the phase rising falling or Port Path from Clock sysclk rising to Clock sysclk rising 7 523ns Slack 7 523ns The detailed path shows the cell type the input and output of this gate the fanout at the output the gate delay the net delay estimated and the name of the instance When entering a hierarchical block
123. 2 Finite State Machine FSM Processing See State Machine in Chapter 2 Improved FSM recognition See State Machine in Chapter 2 Support for Mealy FSMs See State Machine in Chapter 2 Detection of unreachable FSM states See Unreachable States in Chapter 2 FSM implementation on Block RAM via FSM Style FSM_STYLE constraint See FSM Style in Chapter 5 Design Constraints New Features Cores Search Directories switch sd See Cores Search Directories in Chapter 5 New value for Keep Hierarchy constraint KEEP_HIERARCHY soft See Keep Hierarchy in Chapter 5 New value for Netlist Case constraint CASE maintain for VHDL and mixed language projects See Case in Chapter 5 FSM Style constraint FSM_STYLE See FSM Style in Chapter 5 Signal Encoding Algorithm constraint SIGNAL_ENCODING See Signal Encoding in Chapter 5 New value for Multiplier Style constraint MULT_STYLE kcm See Multiplier Style in Chapter 5 Support for mapping of logic on Block RAM BRAM_MAP See Map Logic on BRAM in Chapter 5 Use Carry Chain constraint USE_CARRY_CHAIN See Use Carry Chain in Chapter 5 New values for Box Type constraint BOX TYPE primitive and user_black_box See Box Type in Chapter 5 www xilinx com XST User Guide 1 800 255 7778 XST in Project Navigator 7 XILINX e Optimize Instantiated Primitives switch optimize primitive
124. 3 MHz GHz kHZ Virtex TI II Pro II Pro X E offset_in_before integer ns ps us top entity module primary Spartan I IIE 3 clock signal Virtex TI II Pro II Pro X E offset_out_after integer ns ps ps top entity module primary Spartan TI TIE 3 clock signal Virtex TI II Pro II Pro X E inpad_to_outpad integer ns ps us top entity module Spartan I IIE 3 Virtex TI II Pro II Pro X E max_delay real ns ps us ms top entity module Spartan I IIE 3 MHz GHz kHZ Virtex TI II Pro II Pro X E duty_cycle integer primary clock signal Spartan TI TIE 3 Virtex TI II Pro II Pro X E tig string signal Spartan TI TIE 3 Virtex TI II Pro II Pro X E Also Supported in XCF format 248 www xilinx com XST User Guide 1 800 255 7778 Implementation Constraints 7 XILINX Implementation Constraints Handling XST User Guide This section explains how XST handles implementation constraints See the Constraints Guide for details on the implementation constraints supported by XST by XST Implementation constraints control placement and routing They are not directly useful to XST and are simply propagated and made available to the implementation tools When the write timing constraints switch is set to yes the constraints are written in the output NGC file Note TIG is propagated regardless of the setting In addition the object that an implementation constrain
125. 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process begin wait until CLK EVENT and CLK 1 DO lt DI end process end ARCHI 274 www xilinx com XST User Guide 1 800 255 7778 Sequential Circuits 7 XILINX Example 6 20 describes an 8 bit register with a clock signal and an asynchronous reset signal Example 6 20 8 bit Register Description Using a Process with a Sensitivity List entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT RST in BIT DO out BIT VECTOR 7 downto 0 y end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK RST begin if RST 1 then DO lt 00000000 elsif CLK EVENT and CLK 1 then DO lt DI end if end process end ARCHI Example 6 21 8 bit Counter Description Using a Process with a Sensitivity List library ASYL use ASYL PKG_ARITH all entity EXAMPLE is port CLK in BIT RST in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK RST variable COUNT BIT_VECTOR 7 downto 0 begin if RST 1 then COUNT 00000000 elsif CLK EVENT and CLK 1 then COUNT COUNT 00000001 end if DO lt COUNT end process end ARCHI Multiple Wait Statements Descriptions Sequential
126. 800 255 7778 Behavioral Verilog Features Z XILINX Example 7 6 8 Bit Register Using an Always Block module seql DI CLK DO input 7 0 DI input CLK output 7 0 DO reg 7 0 DO always posedge CLK DO DI endmodule The following example gives the description of an 8 bit register with a clock signal and an asynchronous reset signal Example 7 7 8 Bit Register with Asynchronous Reset high true Using an Always Block module EXAMPLE DI CLK RST DO input 7 0 DI input CLK RST output 7 0 DO reg 7 0 DO always posedge CLK or posedge RST if RST 1 b1 DO 8 b00000000 else DO DI endmodule The following example describes an 8 bit counter Example 7 8 8 Bit Counter with Asynchronous Reset low true Using an Always Block module seq2 CLK RST DO input CLK RST output 7 0 DO reg 7 0 DO always posedge CLK or posedge RST if RST 1 b1 DO 8 500000000 else DO DO 8 b00000001 endmodule Assign and Deassign Statements Assign and deassign statements are supported within simple templates The following is an example of the general template for assign deassign statements module assig RST SELECT STATE CLOCK DATA_IN input RST input SELECT input CLOCK input 0 3 DATA_IN output 0 3 STATE reg 0 3 STATE XST User Guide www xilinx com 303 1 800 255 7778 7 XILI
127. 800 255 7778 FPGA Constraints non timing XILINX XST User Guide Mux Style The Mux Style MUX_STYLE constraint controls the way the macrogenerator implements the multiplexer macros See MUX_STYLE in the Constraints Guide for details Number of Clock Buffers The Number of Clock Buffers bufg constraint controls the maximum number of BUFGs created by XST The constraint value is an integer and is equal to 4 by default Define this option globally with the bufg command line option of the run command Following is the basic syntax bufg integer The constraint value is an integer and is equal to 4 by default for Virtex Virtex E Spartan II Spartan IIE The defaults for selected architectures are 8 for Spartan 3 and 16 for Virtex II and Virtex II Pro The number of BUFGs cannot exceed the maximum number of BUFGs for the target part In Project Navigator specify bufg globally by selecting the Number of Clock Buffers option under the Xilinx Specific Options tab in the Process Properties dialog box Optimize Instantiated Primitives By default XST does not optimize instantiated primitives in HDL code The Optimize Instantiated Primitives OPTIMIZE PRIMITIVES constraint is used to deactivate the default See OPTIMIZE_PRIMITIVES in the Constraints Guide for details Pack I O Registers into IOBs The Pack I O Registers into IOBs IOB constraint packs flip flops in the I Os to improve input
128. Adder This subsection contains a VHDL and Verilog description of an unsigned 8 bit adder The following table shows pin descriptions for an unsigned 8 bit adder 10 pins Description A 7 0 B 7 0 Add Operands SUM 7 0 Add Result VHDL Following is the VHDL code for an unsigned 8 bit adder library ieee use ieee std logic 1164 all use ieee std logic unsigned all 102 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations lt XILINX entity adder is port A B in std_logic_vector 7 downto 0 SUM out std logic vector 7 downto 0 end adder architecture archi of adder is begin SUM lt A B end archi Verilog Following is the Verilog code for an unsigned 8 bit adder module adder A B SUM input 7 0 A input Pree By output 7 0 SUM assign SUM A B endmodule Unsigned 8 bit Adder with Carry In This section contains VHDL and Verilog descriptions of an unsigned 8 bit adder with carry in The following table shows pin descriptions for an unsigned 8 bit adder with carry in 10 pins Description A 7 0 B 7 0 Add Operands CI Carry In SUM 7 0 Add Result VHDL Following is the VHDL code for an unsigned 8 bit adder with carry in library ieee use ieee std logic 1164 a1 use ieee std logic unsigned all entity adder is port A B in std logic vector 7 downto 0 CI in std logic SUM out std logic vector 7 downto
129. Also refer to the chapter describing macro inference for additional details registers counters etc Example 6 15 Sequential Process with Asynchronous Synchronous Parts process CLK RST begin if RST lt 0 1 gt then an asynchronous part may appear here optional part elsif CLK EVENT not CLK STABLE gt and CLK lt 0 1 gt then synchronous part sequential statements may appear here end if end process Note Asynchronous signals must be declared in the sensitivity list Otherwise XST generates a warning and adds them to the sensitivity list In this case the behavior of the synthesis result may be different from the initial specification Sequential Process without a Sensitivity List Sequential processes without a sensitivity list must contain a wait statement The wait statement must be the first statement of the process The condition in the wait statement must be a condition on the clock signal Several wait statements in the same process are accepted but a set of specific conditions must be respected See Multiple Wait Statements Descriptions for details An asynchronous part cannot be specified within processes without a sensitivity list Example 6 16 shows the skeleton of such a process The clock condition may be a falling or a rising edge Example 6 16 Sequential Process Without a Sensitivity List process begin wait until CLK EVENT not CLK STABLE and CLK lt
130. C CE SI SO input C Sr CE output SO reg 7 0 tmp always 8 negedge C begin tmp tmp lt lt 1 tmp 0 SI end assign SO tmp 7 endmodule 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial Out Note Because this example includes an asynchronous clear XST does not infer an SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock an asynchronous clear a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In CLR Asynchronous Clear active High SO Serial Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock an asynchronous clear a serial in and a serial out library ieee use ieee std logic 1164 a1 entity shift is port C SI CLR in std logic SO out std logic end shift XST User Guide www xilinx com 73 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of shift is signal tmp std_logic_vector 7 downto 0 begin process C CLR begin if CLR 1 then tmp lt others gt 0 elsif C event and C 1 then tmp lt tmp 6 downto 0 SI end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock asynchronous clear serial in a
131. D Flip flop with Asynchronous Edge Clock and Reset Asynchronous Clear Flip flop with Positive Edge D Flip Flop with Synchronous Clock and Synchronous Set Reset Flip flop with Positive Edge D Flip Flop with Clock Enable Clock and Clock Enable Latch with Positive Gate D Latch Latch with Positive Gate D Latch with Reset and Asynchronous Clear Latch with Positive Gate and Asynchronous Clear 4 bit Latch with Inverted Gate and Asynchronous Preset 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable Tristates Description Using Process Method VHDL Combinatorial Process and Always Method Verilog Always Block Standalone Method VHDL and Verilog Description Using Concurrent Assignment XST User Guide www xilinx com 1 800 255 7778 33 7 XILINX 34 Chapter 2 HDL Coding Techniques Table 2 1 WHDL and Verilog Examples and Templates Macro Blocks Counters Chapter Examples 4 bit Unsigned Up Counter with Asynchronous Clear 4 bit Unsigned Down Counter with Synchronous Set 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input 4 bit Unsigned Up Counter with Synchronous Load with a Constant 4 bit Unsigned Up Counter with Asynchronous Clear and Clock Enable 4 bit Unsigned Up Down counter with Asynchronous Clear 4 bit Signed Up Counter with Asynchronous Reset Language Templates 4 bit asynchronous counter with count enable asynchronous reset and s
132. DI 2 b01 SO lt DI lt lt 1 2 b10 SO lt DI lt lt 3 default SO lt DI lt lt 2 endcase end endmodule Arithmetic Operations XST supports the following arithmetic operations Adders with Carry In Carry Out Carry In Out Subtractors Adders Subtractors Comparators lt lt gt gt Multipliers Dividers Adders subtractors comparators and multipliers are supported for signed and unsigned operations XST User Guide www xilinx com 1 800 255 7778 101 7 XILINX Chapter 2 HDL Coding Techniques Please refer to Signed Unsigned Support in this chapter for more information on the signed unsigned operations support in VHDL Moreover XST performs resource sharing for adders subtractors adders subtractors and multipliers Adders Subtractors Adders Subtractors This section provides HDL examples of adders and subtractors Log File The XST log file reports the type and size of recognized adder subtractor and adder subtractor during the Macro Recognition step Synthesizing Unit lt adder gt Related source file is arithmetic operations 1l vhd Found 8 bit adder for signal sum Summary inferred 1 Adder Subtracter s Unit lt adder gt synthesized HDL Synthesis Report Macro Statistics 4 Adders Subtractors sd 8 bit adder lt 1 Related Constraints There are no related constraints available Unsigned 8 bit
133. DL Statements Chapter 6 VHDL Language Support Wait Statement Wait on sensitivity_list until Boolean_expression See Sequential Circuits for details Supported with one signal in the sensitivity list and in the Boolean expression In case of multiple wait statements the sensitivity list and the Boolean expression must be the same for each wait statement Wait for time expression See Sequential Circuits for details Unsupported Assertion Statement Supported only for static conditions Signal Assignment Supported delay is ignored Statement Variable Assignment Supported Statement Procedure Call Statement Supported If Statement Supported Case Statement Supported Loop Statement for loop end loop Supported for constant bounds only while loop end loop Supported loop end loop Only supported in the particular case of multiple wait statements Next Statement Supported Exit Statement Supported Return Statement Supported Null Statement Supported www xilinx com 1 800 255 7778 XST User Guide VHDL Reserved Words Table 6 8 Supported VHDL Statements 7 XILINX Concurrent Statement Process Statement Supported Concurrent Procedure Supported Call Concurrent Assertion Ignored Statement Concurrent Signal Assignment Statement Supported no after clause no
134. EGRP PERIOD TIG FROM TO etc including wildcards and hierarchical names Old XST timing constraints which include ALLCLOCKNETS PERIOD OFFSET IN BEFORE OFFSET OUT AFTER INPAD TO OUTPAD and MAX DELAY Please note that these constraints are supported in the current release as they have been in the past without any further enhancements Xilinx strongly suggests that you use the newer XCF syntax constraint style for new devices If you choose to continue with the old constraint style please refer to Old Timing Constraint Support in release 5 1i of the XST User s Guide available on the Xilinx support website Note Timing constraints are only written to the NGC file when the Write Timing Constraints property is checked yes in the Process Properties dialog box in Project Navigator or the write timing constraints option is specified when using the command line By default they are not written to the NGC file Independent of the way timing constraints are specified there are three additional options that affect timing constraint processing 234 Cross Clock Analysis The Cross Clock Analysis command cross clock analysis allows inter clock domain analysis during timing optimization By default ro XST does not perform this analysis Define this option globally with the cross clock analysis command line option of the run command Following is the basic syntax cross clock analysis yes no The default is no
135. ENCODING in the Constraints Guide for details e Equivalent Register Removal The Equivalent Register Removal EQUIVALENT_REGISTER_REMOVAL constraint enables or disables removal of equivalent registers described at the RTL Level By default XST does not remove equivalent flip flops if they are instantiated from a Xilinx primitive library To allow optimization of instantiated flip flops and other primitives use the OPTIMIZE_PRIMITIVES constraint See EQUIVALENT_REGISTER_REMOVAL in the Constraints Guide for details e FSM Encoding Algorithm The FSM Encoding Algorithm FSM_ENCODING constraint selects the finite state machine coding technique to be used The Automatic FSM Extraction option must be enabled in order to select a value for the FSM Encoding Algorithm See FSM ENCODING in the Constraints Guide for details e Mux Extraction The Mux Extract MUX_EXTRACT constraint enables or disables multiplexer macro inference For each identified multiplexer description based on some internal decision rules XST actually creates a macro or optimizes it with the rest of the logic See MUX_EXTRACT in the Constraints Guide for details e Register Power Up XST does not automatically figure out and enforce register power up values You must explicitly specify them if needed with the Register Power Up REGISTER_POWERUP constraint See REGISTER_POWERUP in the Constraints Guide for details e Resource Sharing The R
136. Extraction Shi Register Extraction Logical Shifter Extraction zl OR Collapsing Resource Sharing Multiplier Style UP MEE PEN PEN Cancel Default Help Figure 5 3 HDL Options Tab FPGAs Following is a list of all HDL Options that can be set within the HDL Options tab of the Process Properties dialog box for FPGA devices e FSM Encoding Algorithm e Case Implementation Style e FSM Style e RAM Extraction e RAM Style e ROM Extraction e ROM Style e Mux Extraction e Mux Style e Decoder Extraction e Priority Encoder Extraction e Shift Register Extraction e Logical Shifter Extraction e XOR Collapsing e Resource Sharing e Multiplier Style To view this option go the Edit drop down menu click Preferences click the Processes tab and set the Property Display Level to Advanced XST User Guide www xilinx com 1 800 255 7778 213 7 XILINX Chapter 5 Design Constraints For CPLD device families the following dialog box displays Synthesis Option HDL Option Xilinx Specific Options Property Name FSM Encoding Algorithm Case Implementation Style Mus Extraction Cancel Default Help Figure 5 4 HDL Options Tab CPLDs Following is a list of all HDL Options that can be set within the HDL Options tab of the Process Properties dialog box for CPLD devices e FSM Encoding Algorithm
137. Guide www xilinx com 63 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Signed Up Counter with Asynchronous Reset and Modulo Maximum The following table shows pin definitions for a 4 bit signed up counter with an asynchronous reset and a modulo maximum IO Pins Description C Positive Edge Clock CLR Asynchronous Clear active High Q 7 0 Data Output VHDL Code Following is the VHDL code for a 4 bit signed up counter with an asynchronous reset and a maximum using the VHDL mod function library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all entity counter is generic MAX integer 4 port C CLR in std logic Q out integer range 0 to MAX 1 end counter architecture archi of counter is signal cnt integer range 0 to MAX 1 begin process C CLR begin if CLR 1 then cnt lt 0 elsif rising_edge C then ent lt cnt 1 mod MAX MAX end if end process Q lt cnt end archi 64 www xilinx com XST User Guide 1 800 255 7778 Accumulators Z XILINX Verilog Code Following is the Verilog code for a 4 bit signed up counter with an asynchronous reset and a modulo maximum module counter C CLR Q parameter MAX SORT 4 MAX MAX SORT MAX SORT input C CLR output MAX SQRT 1 0 Q reg MAX SQRT 1 0 cnt always posedge C or posedge CLR begin if CLR cnt lt 0
138. IN reg S COUT begin S A B CIN COUT A amp B A amp CIN B amp CIN ADD COUT S end endfunction assign SO ADD A 0 B 0 CIN S1 ADD A 1 B 1 SO 1 S2 ADD A 2 B 2 S1 1 S3 ADD A 3 B 3 S2 1 S S3 0 S2 0 S1 0 SO 0 COUT S3 1 endmodule 306 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features Z XILINX Example 7 10 Task Declaration and Task Enable module EXAMPLE A B CIN S COUT input 3 0 A B input CIN output 3 0 S output COUT reg 3 01 S reg COUT reg 1 0 SO S1 S2 S3 task ADD input A B CIN output 1 0 C reg 1 0 C reg S COUT begin S A B a CIN COUT A amp B A amp CIN B amp CIN C COUT S end endtask always A or B or CIN begin ADD A 0 B 0 CIN SO ADD A 1 B 1 SO 1 S1 ADD A 2 B 2 S1 1 S2 ADD A 3 B 3 S2 1 S3 S S3 0 S2 0 S1 0 SO 0 COUT S3 1 end endmodule Blocking Versus Non Blocking Procedural Assignments The and time control statements delay execution of the statement following them until the specified event is evaluated as true Use of blocking and non blocking procedural assignments have time control built into their respective assignment statement The delay is ignored for synthesis The syntax for a blocking procedural assignment is shown in the following example reg a a 10
139. If you make no changes to the design XST during Low Level synthesis reports that all blocks are up to date and the previously generated NGC files are kept unchanged as shown in the following log file segment Low Level Synthesis Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni lt my_and gt is up to date lt my_or gt is up to date lt my_sub gt is up to date lt my_add gt is up to date lt levb gt is up to date lt leva_1 gt is up to date lt leva_2 gt is up to date lt leva gt is up to date lt top gt is up to date eT Cr Cr Cr vr cr cv cT CT If you changed one timing constraint then XST cannot detect this modification To force XST to resynthesize the required blocks use the RESYNTHESIZE constraint For example if LEVA must be resynthesized then apply the RESYNTHESIZE constraint to this block 186 www xilinx com XST User Guide 1 800 255 7778 Speed Optimization Under Area Constraint 7 XILINX All blocks included in the lt leva gt group are re optimized and new NGC file are generated as shown in the following log file segment Low Level Synthesis Incremental synthesis Unit lt my_and gt is up to date Incremental synthesis Unit lt my_or gt
140. Inference For the following Verilog code XST does not infer a decoder module mux sel input 2 0 output 7 0 reg 7 0 res always G sel begin case sel 3 b000 3 b001 3 b010 3 b011 3 b100 3 b101 3 b110 default endcase end endmodule res sel res res 8 b00000001 res 8 bxxxxxxxx res 8 b00000100 res 8 b00001000 res 8 b00010000 res 8 b00100000 res 8 b01000000 res 8 b10000000 unused decoder output 94 www xilinx com 1 800 255 7778 XST User Guide 7 XILINX Decoders VHDL Code Decoder Inference The following VHDL code leads to the inference of a 1 of 8 decoder library ieee use ieee std logic 1164 a1l entity dec is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end dec architecture archi of dec is begin res lt 00000001 when sel 000 else 00000010 when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 110 and 111 selector values are unused XXXXXXXX end archi Verilog Code Decoder Inference The following Verilog code leads to the inference of a 1 of 8 decoder module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always sel or res begin case sel 3 b000 res 8 b00000001 3 b001 res 8 b00000010 3 b010
141. Inputs s 1 0 MUX selector O Data Output VHDL Code Following is the VHDL code for a 4 to 1 1 bit MUX using an If statement library ieee use ieee std logic 1164 a11 entity mux is port a b c d in std logic S in std logic vector 1 downto 0 o out std logic end mux 86 www xilinx com XST User Guide 1 800 255 7778 Multiplexers architecture archi of mux is begin process a b c d s begin if s 00 then o lt a elsif s 01 then o lt b elsif s 10 then o lt C else o lt d end if end process end archi Verilog Code Following is the Verilog code for a 4 to 1 1 bit MUX using an If statement module mux a b c d S O input a b c d input 1 0 s output o reg o always a or b or c or d or s begin if s 2 b00 o a else if s 2 b01 o b else if s 2 b10 Oo C else o d end endmodule 4 to 1 MUX Using CASE Statement 7 XILINX The following table shows pin definitions for a 4 to 1 1 bit MUX using a Case statement IO Pins Description a b c d Data Inputs s 1 0 MUX selector O Data Output XST User Guide www xilinx com 1 800 255 7778 87 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for a 4 to 1 1 bit MUX using a Case statement library ieee use ieee std logic 1164 a11 entity mux is port a b c d in std lo
142. JIOSTANDARD can be used to assign an I O standard to an I O primitive for example synthesis attribute IOSTANDARD of inl is PCI33 5 assigns PCI33 5 I O standard to the I O port The primitive support is based on the notion of the black box Refer to the Black Box Support in Chapter 2 for the basics of the black box support There is a significant difference between black box and primitive support Assume you have a design with a submodule called MUXES5 In general the MUXF5 can be your own functional block or a Virtex primitive So to avoid confusion about how XST interprets this module use a special constraint called BOX TYPE This attribute must be attached to the component declaration of MUXF5 If the BOX TYPE attribute e is attached to the MUXF5 with a value of primitive or black box XST tries to interpret this module as a Virtex primitive and use its parameters for instance in critical path estimation e user black box XST processes it as a regular user black box If the name of the user black box is the same as that of a Virtex primitive XST renames it to a unique name and generates a warning message with the reason for the warning For example MUX5 could be renamed to MUX51 as in the following log sample Low Level Synthesis E WARNING Xst 79 Model muxf5 has different characteristics in destination library WARNING Xst 80 Model name has been changed to muxf51 e isn
143. KG package body PKG is procedure ADD A B CIN in BIT C out BIT VECTOR 1 downto 0 is variable S COUT BIT begin S A xor B xor CIN COUT A and B or A and CIN or B and CIN C COUT amp S end ADD end PKG use work PKG all entity EXAMPLE is port A B in BIT VECTOR 3 downto 0 CIN in BIT S out BIT VECTOR 3 downto 0 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B CIN variable S0 S1 S2 S3 BIT VECTOR 1 downto 0 begin ADD A 0 B 0 CIN SO ADD A 1 B 1 SO 1 S1 ADD A 2 B 2 S1 1 S2 ADD A 3 B 3 S2 1 S3 S lt S3 0 S2 0 amp S1 0 amp SO 0 COUT lt S3 1 end process end ARCHI XST supports recursive functions as well Example 6 25 represents n function Example 6 25 Recursive Function function my_func x integer return integer is begin if x 1 then return x else return x my func x 1 end if end function my func 278 www xilinx com XST User Guide 1 800 255 7778 Assert Statement 7 XILINX Assert Statement XST supports the use of the Assert statement By using the Assert statement designers can detect undesirable conditions in their VHDL designs such as bad values for generics constants and generate conditions or bad values for parameters in called functions For any failed condition in an Assert statem
144. NG Xst 766 design vhd line 5 Generating a Black Box for component comp Instantiating component comp from Library lib Set user defined property LOC X1Y1 for instance inst in unit block Set user defined property RLOC X1Y1 for instance inst in unit block Set user defined property INIT 1 for instance inst in unit block Register regi equivalent to reg2 has been removed XST User Guide www xilinx com 335 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis The following messages are hidden when low_level and hdl_and_low_levels values are specified for the XIL_XST_HIDEMESSAGES environment variable ARNING Xst 382 Register regl is equivalent to reg2 e Register regi equivalent to reg2 has been removed ARNING Xst 1710 FF Latch reg without init value is constant in block block ARNING Xst 1293 FF Latch reg is constant in block block ARNING Xst 1291 FF Latch reg is unconnected in block block ARNING Xst 1426 The value init of the FF Latch reg hinders the constant cleaning in the block block You could achieve better results by setting this init to value Timing Report At the end of synthesis XST reports the timing information for the design The report moms shows the information for all four possible domains of a netlist register to register input Mo to register register to outpad and inpad to outpad S
145. NX Chapter 7 Verilog Language Support always RST if RST begin assign STATE 4 b0 end else begin deassign STATE end always posedge CLOCK begin STATE DATA_IN end endmodule The main limitations on support of the assign deassign statement in XST are as follows e Fora given signal there must be only one assign deassign statement For example XST rejects the following design module dflop RST SET STATE CLOCK DATA_ IN input RST input SET input CLOCK input DATA_IN output STATE reg STATE always RST block b1 if RST assign STATE 1 b0 else deassign STATE always SET block bi if SET assign STATE 1 b1 else deassign STATE always posedge CLOCK block b2 begin STATE DATA_IN end endmodule 304 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX The assign deassign statement must be performed in the same always block through an if else statement For example XST rejects the following design module dfl input RST op RS input SE P input CLOCK input DAT rA IN T output S reg STATE always case 2 b00 2 b01 2 b10 2 b11 endcase always begin STATE end ATE m En RST or SI RST SI ET S ET assig
146. OC of u123 label is R11C1 S0 attribute bufg of my signal signal is sr The object list is a comma separated list of identifiers Accepted object types are entity component label signal variable and type Verilog Meta Comment Syntax Constraints can be specified as follows in Verilog code synthesis attribute AttributeName of ObjectName is AttributeValue Example synthesis attribute RLOC of u123 is R11C1 S0 synthesis attribute HU SET ul MY SET synthesis attribute bufg of my clock is clk Note The parallel case full case translate on and translate off directives follow a different syntax described in Verilog Meta Comments in Chapter 7 XST Constraint File XCF Starting in the 5 1i release XST supports a new UCF style syntax to define synthesis and timing constraints Xilinx strongly suggests that you use the new syntax style for your new designs Xilinx continues to support the old constraint syntax without any further enhancements in the current release of XST but will eventually drop support The old constraints syntax is no longer documented in this guide Please refer to Old XST Constraint Syntax in release 5 1i of the XST User Guide available on the Xilinx Support web site for details on using the old constraint style Hereafter this document refers to the new syntax style as the Xilinx Constraint File XCF format The XCF must have an extension of xcf XST uses this ex
147. OGIC 1164 IEEE package This package is compiled in the library IEEE In order to use one of these types the following two lines must be added to the VHDL specification library IEEE use IEEE STD LOGIC 1164 a11 The types UNSIGNED and SIGNED defined as an array of STD LOGIC are declared in the STD LOGIC ARITH IEEE package This package is compiled in the library IEEE In order to use these types the following two lines must be added to the VHDL specification library IEEE use IEEE STD LOGIC ARITH all XST User Guide www xilinx com 257 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support Multi dimensional Array Types XST supports multi dimensional array types of up to three dimensions Arrays can be signals constants or VHDL variables You can do assignments and arithmetic operations with arrays You can also pass multi dimensional arrays to functions and use them in instantiations The array must be fully constrained in all dimensions An example is shown below subtype WORD8 is STD_LOGIC_VECTOR 7 downto 0 type TAB12 is array 11 downto 0 of WORD8 type TAB03 is array 2 downto 0 of TAB12 You can also declare an array as a matrix as in the following example subtype TAB13 is array 7 downto 0 4 downto 0 of STD LOGIC VECTOR 8 downto 0 The following examples demonstrate the various uses of multi dimensional array signals and va
148. OGIC VECTOR 3 downto 0 RESULT out STD LOGIC VECTOR 3 downto 0 CLK in STD LOGIC RST in STD LOGIC end EXAMPLE architecture ARCH of EXAMPLE is begin process begin SEQ LOOP loop wait until CLK EVENT and CLK 1 exit SEQ_LOOP when RST 1 RESULT lt DATA1 wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA2 until CLK EVENT and CLK 1 SEQ_LOOP when RST 1 RESULT lt DATA3 wait until CLK EVENT and CLK 1 exit SEQ_LOOP when RST 1 RESULT lt DATA4 end loop end process end ARCH 276 www xilinx com XST User Guide 1 800 255 7778 Functions and Procedures Z XILINX Functions and Procedures The declaration of a function or a procedure provides a mechanism for handling blocks used multiple times in a design Functions and procedures can be declared in the declarative part of an entity in an architecture or in packages The heading part contains the parameters input parameters for functions and input output and inout parameters for procedures These parameters can be unconstrained This means that they are not constrained to a given bound The content is similar to the combinatorial process content Resolution functions are not supported except the one defined in the IEFE std_logic_1164 package Example 6 23 shows a function declar
149. R INTEGER REAL www xilinx com XST User Guide 1 800 255 7778 Data Types in VHDL 7 XILINX The following types are declared in the STD_LOGIC_1164 IEEE package e STD LOGIC e STD LOGIC VECTOR This package is compiled in the IEEE library In order to use one of these types the following two lines must be added to the VHDL specification library IEEE use IEEE STD LOGIC 1164 a11 Overloaded Data Types The following basic types can be overloaded e Enumerated Types STD_ULOGIC contains the same nine values as the STD_LOGIC type but does not contain predefined resolution functions X01 subtype of STD_ULOGIC containing the X 0 and 1 values X01Z subtype of STD ULOGIC containing the X 0 1 and Z values UX01 subtype of STD_ULOGIC containing the U X 0 and 1 values UX01Z subtype of STD_ULOGIC containing the U X 0 1 and Z values e Bit Vector Types STD ULOGIC VECTOR UNSIGNED SIGNED Unconstrained types types whose length is not defined are not accepted e Integer Types NATURAL POSITIVE Any integer type within a user defined range As an example type MSB is range 8 to 15 means any integer greater than 7 or less than 16 The types NATURAL and POSITIVE are VHDL predefined types The types STD_ULOGIC and subtypes X01 X01Z UX01 UX01Z STD_LOGIC STD ULOGIC VECTOR and STD LOGIC VECTOR are declared in the STD L
150. RAM descriptions with two or more read ports that access the RAM contents at addresses different from the write address However there can only be one 150 www xilinx com 1 800 255 7778 XST User Guide RAMS ROMs Z XILINX write port XST implements the following descriptions by replicating the RAM contents for each output port as shown DO2 X8983 The following table shows pin descriptions for a multiple port RAM 10 pins Description clk Positive Edge Clock we Synchronous Write Enable Active High wa Write Address ral Read Address of the First RAM ra2 Read Address of the Second RAM di Data Input do1 First RAM Output Port do2 Second RAM Output Port VHDL Following is the VHDL code for a multiple port RAM library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port Clk in std logic we in std logic wa in std logic vector 4 downto 0 ral in std logic vector 4 downto 0 ra2 in std logic vector 4 downto 0 di in std logic vector 3 downto 0 dol out std logic vector 3 downto 0 do2 out std logic vector 3 downto 0 end raminfr XST User Guide www xilinx com 151 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if
151. Run Command Options Description Values case Case Upper Lower Maintain hierarchy_separator Hierarchy Separator UE opt mode Optimization Goal Area Speed opt level Optimization Effort 12 p Target Technology part package speed for example xcv50 fg456 5 xcv50 fg456 6 rtlview Generate RTL Schematic Yes No Only iuc Ignore User Constraints Yes No uc Synthesis Constraints File file name xcf bus delimiter Bus Delimiter L 0 0 Table 10 2 VHDL Source Options Run Command E Description Values Options ent Entity Name name Note Valid only when old VHDL project format is used ifmt VHDL Please use project format ifmt mixed and top switch to specify which top level block to synthesize arch Architecture name Table 10 3 Verilog Source Options Run command Description Values Options top Top Module name name Note Not Valid when old VHDL Project format is used ifmt VHDL vlgcase Case Implementation Style Full Parallel Full Parallel vlgpath Verilog Search Paths Any valid path to directories separated by spaces and enclosed in double quotes 352 www xilinx com XST User Guide 1 800 255 7778 Run Command XST User Guide Table 10 3 Verilog Source Options lt XILINX Run Command Description Values Options vlgincdir Verilog Include Directories Any valid path to directories separated by spaces and enc
152. Specifying INITs and RLOCs in HDL Code 198 Using the UNISIM library allows you to directly instantiate LUT components in your HDL code To specify a function that a particular LUT must execute apply an INIT constraint to the instance of the LUT If you want to place an instantiated LUT or register in a particular slice of the chip then attach an RLOC constraint to the same instance It is not always convenient to calculate INIT functions and different methods that can be used to achieve this Instead you can describe the function that you want to map onto a single LUT in your VHDL or Verilog code in a separate block Attaching a LUT MAP constraint XST is able to automatically recognize the XC_MAP constraint supported by Synplicity to this block indicates to XST that this block must be mapped on a single LUT XST automatically calculates the INIT value for the LUT and preserves this LUT during optimization In the following VHDL example the top block contains the instantiation of two AND gates described in and_one and and_two blocks XST generates two LUT2s and does not merge them Please refer to the LUT_MAP constraint description in the Constraints Guide for details library ieee use ieee std logic 1164 a1 entity and one is port A B in std logic REZ out std logic i attribute LUT_MAP string attribute LUT_MAP of and_one entity is yes end and_one architecture beh of and_one is begin REZ lt A and B end beh
153. TE HESE IMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE and ROUTE Clock Information Clock Signal Clock buffer FF name Load clk BUFGP 9 Timing Summary Speed Grade 6 Minimum period 7 523ns Maximum Frequency 132 926MHz Minimum input arrival time before clock 8 945ns Maximum output required time after clock 14 220ns Maximum combinational path delay 10 889ns XST User Guide www xilinx com 191 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization Timing Detail All values displayed in nanoseconds ns Timing constraint Default period analysis for Clock clk Delay 7 523ns Levels of Logic 2 Source sdstate_FFD1 Destination sdstate_FFD2 Source Clock Destination Clock clk rising clk rising Data Path sdstate_FFD1 to sdstate_FFD2 Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name FDC C gt Q 15 1 372 2 970 state_FFD1 state_FFD1 LUT3 11 gt 0 1 0 738 1 26 LUT_54 N39 LUT3 11 gt 0 1 0 738 0 000 I next state 2 N39 FDC D 0 440 state FFD2 Total 7 523ns 3 288ns logic 4 235ns route 43 7 logic 56 3 route Gate Net Cell in out fanout Delay Delay Logical Name FDO C 50 15 1 372 2 970 I state 2 begin scope blockl LUT3 1
154. Verilog equivalents for mixed language designs 328 integer real string boolean www xilinx com XST User Guide 1 800 255 7778 Library Search Order File 7 XILINX Library Search Order File The Library Search Order LSO file specifies the search order that XST uses to link the libraries used in VHDL Verilog mixed language designs By default XST searches the files specified in the project file in the order in which they appear in that file XST uses the default search order when either the DEFAULT_SEARCH_ORDER keyword is used in the LSO file or the LSO file is not specified Project Navigator In Project Navigator the default name for the LSO file is project_name 1so Ifa project name 1so file does not already exist Project Navigator automatically creates one If Project Navigator detects an existing project name 1so file this file is preserved and used as it is Please remember that in Project Navigator the name of the project is the name of the top level block In creating a default LSO file Project Navigator places the DEFAULT SEARCH ORDER keyword in the first line of the file Command Line When using XST from the command line specify the Library Search Order file by using the lso command line switch If the lso switch is omitted XST automatically uses the default library search order without using an LSO file Search Order Rules XST User Guide XST follows the following search order rules when processing
155. XILINX Chapter 8 Mixed Language Support e Mixed language projects accept a search order used for searching unified logical libraries in design units cells During elaboration XST follows this search order for picking and binding a VHDL entity or a Verilog module to the mixed language project Mixed Language Project File XST uses a dedicated mixed language project file to support mixed VHDL Verilog designs You can use this mixed language format not only for mixed projects but also for purely VHDL or Verilog projects If you use Project Navigator to run XST Project Navigator creates the project file and it is always a mixed language project file If you run XST from the command line you must create a mixed language project file for your mixed language projects To create a mixed language project file at the command line use the ifmt command line switch set to mixed or with its value is omitted Please note that you can still use the VHDL and Verilog formats for existing designs To use the VHDL format set ifmt to vhdl and to use the Verilog format set ifmt to verilog The syntax for invoking a library or any external file in a mixed language project is as follows language library file name ext The following is an example of how to invoke libraries in a mixed language project vhdl work my vhdll vhd verilog work my vlgl v vhdl my vhdl lib my vhdl2 vhd verilog my vlg lib my vlg2 v Each line specifies a single
156. XST Script Run Command Getting Help Set Command Elaborate Command Example 1 How to Synthesize VHDL Designs Using Command Line Mode Example 2 How to Synthesize Verilog Designs Using Command Line Mode Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode You can run synthesis with XST in command line mode instead of from the Process window in Project Navigator To run synthesis from the command line you must use the XST executable file If you work on a workstation the name of the executable is xst On a PC the name of the executable is xst exe XST generates the following types of files XST User Guide Design output file NGC ngc This file is generated in the current output directory see the ofn option If run in incremental synthesis mode XST generates multiple NGC files RIL netlist for RTL viewer ngr Synthesis LOG file srp Temporary files Temporary files are generated in the XST temp directory By default the XST temp directory is tmp on workstations and the directory specified by either the TEMP or TMP environment variables under Windows The XST temp directory can be changed by using the set tmpdir directory directive www xilinx com 349 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode e VHDL Verilog compilation files VHDL Verilog compilation files are generated in the dump directory The default dump
157. XST User Guide XILINX XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex Il Pro Virtex Il EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx XDTV Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Logic Company is a service mark of Xilinx Inc All other trademarks are
158. Y A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE AND ROUTE Timing Detail CPU XST run time Memory usage Note Device Utilization Summary Clock Information and Timing Summary are still available for FPGAs Silent mode allows you keep any messages from going to the computer screen stdout while XST continues to generate the entire LOG file Silent mode can be invoked using intstyle switch with value set to silent Hiding specific messages You can hide specific messages generated by XST at the HDL or Low Level Synthesis steps in specific situations by using the XIL XST HIDEMESSAGES environment variable This environment variable can have one of the following values none maximum verbosity All messages are printed out This is the default hdl level reduce verbosity during VHDL Verilog Analysis and HDL Basic and Advanced Synthesis low level reduce verbosity during Low level Synthesis hdl and low levels reduce verbosity at all stages The following messages are hidden when hdl_level and hdl and low levels values are specified for the XIL XST HIDEMESSAGES environment variable ARNING HDLCompilers 38 design v line 5 Macro my macro redefined Note this message is issued by the Verilog compiler only ARNING Xst 916 design vhd line 5 Delay is ignored for synthesis ARNI
159. _1 RAMI28XIS 1 www xilinx com 177 1 800 255 7778 7 XILINX 178 ROMs Chapter 3 FPGA Optimization e For Dual Port Synchronous Distributed RAM For Distributed Dual Port RAM with positive clock edge RAM16X1D RAM32X1D RAM64X1D For Distributed Dual Port RAM with negative clock edge RAM16X1D_1 RAM32XID 1 RAM64X1D_1 For Block RAM XST uses e RAMB4 Sn primitives for Single Port Synchronous Block RAM e RAMB4 Sm_Sn primitives for Dual Port Synchronous Block RAM In order to have better control of the implementation of the inferred RAM XST offers a way to control RAM inference and to select the generation of Distributed RAM or Block RAMs if possible The RAM_STYLE attribute specifies that an inferred RAM be generated using e Block RAM if the value is block e Distributed RAM if the value is distributed You can apply the RAM STYLE attribute either to a signal that defines the RAM or the instance name of the RAM This attribute can also be global If the RAM resources are limited XST can generate additional RAMs using registers To do this use the RAM EXTRACT attribute with the value set to no A ROM can be inferred when all assigned contexts in a Case or If else statement are constants Macro inference only considers ROMs of at least 16 words with no width restriction For example the following HDL equation can be implemented with a ROM of 16 words of 4 bits data if address 0000 then 0010 if addr
160. a Input SEL Shift Distance Selector SO 7 0 Data Output VHDL Following is the VHDL code for a logical shifter library ieee use ieee std logic 1164 all use ieee numeric std all 98 www xilinx com XST User Guide 1 800 255 7778 Logical Shifters Z XILINX entity lshift is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO out unsigned 7 downto 0 end lshift architecture archi of lshift is begin with SEL select SO lt DI when 00 DI sll 1 when 01 DI sll 2 when 10 DI sll 3 when others end archi Verilog Following is the Verilog code for a logical shifter module lshift DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always Q8 DI or SEL begin case SEL 2 b00 SO lt DI 2 b01 SO lt DI lt lt 1 2 b10 SO lt DI lt lt 2 default SO lt DI lt lt 3 endcase end endmodule Example 2 XST does not infer a logical shifter for this example as not all of the selector values are presented 10 pins Description D 7 0 Data Input SEL Shift Distance Selector SO 7 0 Data Output VHDL Following is the VHDL code library ieee use ieee std logic 1164 all use ieee numeric std all XST User Guide www xilinx com 99 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques entity lshift is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO o
161. a given template can be implemented using Block and Distributed RAM XST implements BLOCK ones You can use the RAM STYLE constraint to control RAM implementation and select a desirable RAM type Please refer to Chapter 5 Design Constraints for more details www xilinx com 121 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Please note that the following features specifically available with Block RAM are not yet supported e Dual write port e Parity bits e Different aspect ratios on each port Please refer to Chapter 3 FPGA Optimization for more details on RAM implementation Note Note that XST can implement State Machines see State Machine and map general logic see Mapping Logic onto Block RAM in Chapter 3 on Block RAMs Log File The XST log file reports the type and size of recognized RAM as well as complete information on its I O ports during the Macro Recognition step Synthesizing Unit lt raminfr gt Related source file is rams_1 vhd Found 128 bit single port distributed RAM for signal lt ram gt aspect ratio 32 word x 4 bit clock connected to signal clk rise write enable connected to signal we high address connected to signal a data in connected to signal di data out connected to signal do ram style Auto INFO Xst For optimized device usage and improved timings you may take advantage of available block RAM resources by reg
162. a mixed language project e When the LSO file contains only the DEFAULT SEARCH ORDER keyword XST searches the specified library files in the order in which they appear in the project file updates the LSO file by removing the DEFAULT SEARCH ORDER keyword adding the list of libraries to the LSO file in the order in which they appear in the project file See Example 1 e When the LSO file contains the DEFAULT SEARCH ORDER keyword and a list of the libraries XST searches the specified library files in the order in which they appear in the project file ignores the list of library files in the LSO file leaves the LSO file unchanged See Example 2 e When the LSO file contains a list of the libraries without the DEFAULT_SEARCH_ORDER keyword XST searches the library files in the order in which they appear in the LSO file leaves the LSO file unchanged See Example 3 www xilinx com 329 1 800 255 7778 7 XILINX Chapter 8 Mixed Language Support e When the LSO file is empty XST generates a warning message stating that the LSO file is empty searches the files specified in the project file using the default library search order updates the LSO file by adding the list of libraries in the order that they appear in the project file When the LSO file contains a library name that does not exist in the project or INI file and the LSO file does not contain the DEFAULT
163. aa 267 Combinatorial Process en 268 f Else Statem rit neri d Re b eer eee ra aiaa a REpSSOoE vad 270 Case Statement cerr rip doeet ta cue qoe tenuate edad ee ti A pter ture 271 Bot Loop Statement id a evt Vale Plu a e ee ua 272 SequenBal CIRCUS iso ok rotor gor aede Da nt d doo Go e onde ee ar edle di 273 Sequential Process with a Sensitivity List oooooococcccooornrroooonno o 273 Sequential Process without a Sensitivity List ooooooocooororommmmo 273 Examples of Register and Counter Descriptions 274 Multiple Wait Statements Descriptions 00066 275 Functions and Procedures vivir ce rre CREER sd 277 Assert Statements 2ddted kr E RES ERR ERES daba 279 nero MUR p 281 STANDARD Package Lise Horde eder dedere dee eee ebd 281 IEEE Packages add aee teet ded e Repas aestate eara 281 Synopsys Packages acer eR a Rb e a eas 282 VHDL Language SUPPORT UP KE RE CRI 283 VHDL Reserved Words orcas dada 289 Chapter 7 Verilog Language Support Introduction eor Eee esee E E e E e ce ds 291 Behavioral Verilog Features iic eben Ee VERRE e id Vio doe oae 292 Variable Declaration o oooooooornrnr an 292 Initial Values iure ERR REA RERAM LAUD PR AA Dep eee tas PLANA GG 292 Ss piscis ers ive Cu Re LIEU Ad pdt Me Etpe E 293 Multi dimensional Arrays lesse hen 293 Data Ly Pes ui AA A ains 294 Legal Statements mentiras da etd e tale Pepe 295 EXpreSSIOrlS is ecd neis pbrde tir eit tages need d eee d
164. adds them to the sensitivity list In this case the result of the synthesis may be different from the initial design specification A process may contain local variables The variables are handled in a similar manner as signals but are not of course outputs to the design In Example 6 10 a variable named AUX is declared in the declarative part of the process and is assigned to a value with in the statement part of the process Examples 6 10 and 6 11 are two examples of a VHDL design using combinatorial processes Example 6 10 Combinatorial Process library ASYL use ASYL ARITH all entity ADDSUB is port A B in BIT VECTOR 3 downto 0 ADD SUB in BIT S out BIT VECTOR 3 downto 0 end ADDSUB www xilinx com 269 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support architecture ARCHI of ADDSUB is begin process A B ADD_SUB variable AUX BIT_VECTOR 3 downto 0 begin if ADD SUB 1 then AUX A B else AUX A B end if S lt AUX end process end ARCHI Example 6 11 Combinatorial Process entity EXAMPLE is port A B in BIT S out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B variable X Y BIT begin X A and B Y B and A if X Y then B lt TTE 3 end if end process end ARCHI Note In combinatorial processes if a signal is not explicitly assigned in all branches of
165. ains HDL Synthesis Report During this step XST tries to recognize as many macros as possible to create a technology specific implementation This is done on a block by block basis At the end of this step XST gives an HDL Synthesis Report This report contains a summary of recognized macros in the overall design sorted by macro type See Chapter 2 HDL Coding Techniques for more details about the processing of each macro and the corresponding messages issued during the synthesis process Advanced HDL Synthesis During this step XST performs advanced macro recognition and inference In this step XST recognizes dynamic shift registers implements pipelined multipliers codes state machines etc www xilinx com 333 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis Low Level Synthesis During this step XST reports the potential removal of equivalent flip flops register replication etc For more information see Log File Analysis in Chapter 3 Final Report The Final report is different for FPGA and CPLD flows as follows FPGA and CPLD includes the output file name output format target family and cell usage FPGA only In addition to the above the report includes the following information for FPGAs Device Utilization Summary where XST estimates the number of slices gives the number of flip flops IOBs BRAMS etc This report is very close to the one produced by MAP Clock Information gives
166. an give this library mapping file any name you wish but it is best to keep the ini classification The format is library name path to compiled directory Note Use for comments Sample text for my ini workl H NUsersNconfWMny lib Nworkl work2 C mylib work2 www xilinx com XST User Guide 1 800 255 7778 General Constraints XST User Guide XILINX Work Directory The Work Directory XSTHDPDIR parameter defines the location in which VHDL compiled files must be placed if the location is not defined by library mapping files You can access this switch by Selecting the VHDL Working Directory menu in the Synthesis Options tab of the Synthesis process properties in Project Navigator or Using the following command in stand alone mode set xsthdpdir file name Example Suppose three different users are working on the same project They must share one standard pre compiled company shlib This library contains specific macro blocks for their project Each user also maintains a local work library but User 3 places it outside the project directory i e in c temp Users 1 and 2 will share another library lib12 between them but not with User 3 The settings required for the three users are as follows User 1 Mapping file schlib z sharedlibs shlib 1ib12 z userlibs lib12 User 2 Mapping file schlib z sharedlibs shlib lib12 z userlibs lib12 User 3 Mapping file schli
167. and expression is unsigned the left hand expression is padded with 0 s e For unsized x or z constants only the following rule applies If the value of the right hand expression s left most bit is z high impedance or x unknown regardless of whether the right hand expression is signed or unsigned the left hand expression is padded with that value z or x respectively Note The above rules follow the Verilog 2001 standard and are not backward compatible with Verilog 1995 Tasks and Functions The declaration of a function or task is intended for handling blocks used multiple times in a design They must be declared and used in a module The heading part contains the parameters input parameters only for functions and input output inout parameters for tasks The return value of a function can be declared either signed or unsigned The content is similar to the combinatorial always block content Recursive function and task calls are not supported Example 7 9 shows a function declared within a module The ADD function declared is a single bit adder This function is called 4 times with the proper parameters in the architecture to create a 4 bit adder The same example described with a task is shown in Example 7 10 Example 7 9 Function Declaration and Function Call module comb15 A B CIN S COUT input 3 0 A B input CIN output 3 0 S output COUT wire 1 0 SO S1 S2 S3 function signed 1 0 ADD input A B C
168. arallel_case full_case Case current_state Example 4 mult style pipe lut MULT my mult a b c Limitations Verilog 2001 attributes are not supported for the following e signal declarations e statements e port connections e expression operators Language Support Tables The following tables indicate which Verilog constructs are supported in XST Previous sections in this chapter describe these constructs and their use within XST Note XST does not allow underscores as the first character of signal names for example _DATA_1 XST User Guide www xilinx com 317 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support Table 7 3 Constants Integer Constants Supported Real Constants Supported Strings Constants Unsupported Table 7 4 Data Types wire Supported tri Supported supply0 Supported net type supply1 Nets wand wor Supported triand trior tri0 tril Unsupported trireg drive Ignored strength reg Supported integer Supported Registers real Unsupported realtime Unsupported net Supported reg Supported Veetos vectored Supported scalared Supported Multi Supported Dimensional Arrays lt 3 dimensions Parameters Supported Named Events Unsupported 318 www xilinx com XST User Guide 1 800 255 7778 Language Support Tables Table 7 5 Continuous Assignments Drive St
169. ary just before the file name Suppose that hexl2led must be compiled into the library called my 1ib then the project file must be vhdl work statmach vhd vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work vhdl tenths vhd my lib work hex2led vhd Sometimes XST is not able to recognize the order and issues the following message WARNING XST 3204 The sort of the vhdl files failed they will be compiled in the order of the project file In this case you must do the following e Putall VHDL files in the correct order e Add at the end of the list on a separate line the keyword nosort XST then uses your predefined order during the compilation step vhdl work statmach vhd vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work tenths vhd vhdl work hex2led vhd nosort Script Mode It can be very tedious work to enter XST commands directly in the XST shell especially when you have to specify several options and execute the same command several times You can run XST in a script mode as follows 1 Open a new file named xst txt in the current directory Put the previously executed XST shell command into this file and save it run ifn watchvhd prj ifmt mixed ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 2 From the tesh or other shell enter the following command to start syn
170. at s New cr beem ree ar EN ier eir nb qtue ecu ai ded etae a E 21 HDL Language Support o oooooocooorcrr eh 21 VIDE a da e extnE beu e ee eaa a d d ee EAS 21 Menlo ctos A destra A cata ium tested e edis pce E 22 Macro Inference assidu dais E REA REA a brace ENTA PAG ue RAUS 22 Design Constraints iiis iris e o nn RR ERPRETE E E 22 New Features iia he uet eX e haw ee Leo XX RE exea Chee ERE xus 22 Deprecated constraints doen exe d mu etes ei A Cum etr ee S 23 Obsoleted constraints oooo eh hrs 23 EPGA E OW vere a E Evae ad ied EE hai Ei redes 23 nodu cp TET 23 XST in Project NAVIBOLOE finde rath Eee dated ede ed et ele Mi d redii d 23 Chapter 2 HDL Coding Techniques o creer caer qc Eu oe eeu Uere Seti RE eR E e dig pd 29 Signed Unsigned Support sisse 38 E A gu 39 Lop File a Rev Uc aed nia ae DEIN EE 39 Related Constraints sera sedi npiale das cote braga tees HORA GU KU 40 Flip flop with Positive Edge Clock sis psp epee i ae 40 VEIDL Codes 5i coda textes it dad 40 Verilog Coden jj cese veto stes d MUEVE urbe decia ee cde etu a ee sea 41 Flip flop with Negative Edge Clock and Asynchronous Clear 41 VADE Code PCT TELE 42 Verilog Code vs cof tup eT Dar p UP Ves Vite e ped ees ne ves 42 Flip flop with Positive Edge Clock and Synchronous Set ussuue 42 VHDE Code eeieunccbeerkucrcbreeekbbeerebqenpewcieug ebbe respete 43 Verilog Code venias cia cay exer o eee ut a eL ceri 43
171. ate parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 always G8 posedge clk or posedge reset begin if reset state sl else state next_state end always G state or xl begin Case state si if x1 1 b1 next_state s2 else next_state s3 s2 next state s4 S3 next state s4 s4 next state sl endcase end 166 www xilinx com XST User Guide 1 800 255 7778 State Machine Z XILINX always Q8 state begin case state sl outp 1 b1 S2 outp 1 b1 S3 outp 1 b0 S4 outp 1 b0 endcase end endmodule State Registers State registers must be initialized with an asynchronous or synchronous signal XST does not support ESM without initialization signals Please refer to Registers in this chapter for templates on how to write Asynchronous and Synchronous initialization signals In VHDL the type of a state register can be a different type integer bit vector std logic vector for example But it is common and convenient to define an enumerated type containing all possible state values and to declare your state register with that type In Verilog the type of state register can be an integer or a set of defined parameters In the following Verilog examples the state assignments could have been made like this parameter 3 0 sl 4 b0001 S2 4 b0010 s3 4 b0100 s4 4 b1000 reg 3 0 state These parameters can be modified to repr
172. ays posedge C begin tmp tmp lt lt 1 tmp 0 SI end assign SO tmp 7 endmodule XST User Guide www xilinx com 71 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out Note For this example XST infers an SRL16E_1 The following table shows pin definitions for an 8 bit shift left register with a negative edge clock a clock enable a serial in and a serial out IO Pins Description C Negative Edge Clock SI Serial In CE Clock Enable active High SO Serial Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a negative edge clock a clock enable a serial in and a serial out library ieee use ieee std logic 1164 all entity shift is port C SI CE in std logic SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto begin process C begin if C event and C 0 then if CE 1 then for i in 0 to 6 loop tmp 1 1 lt tmp 1 end loop tmp 0 lt SI end if end if end process SO lt tmp 7 end archi 72 www xilinx com 1 800 255 7778 o XST User Guide Shift Registers Z XILINX Verilog Code Following is the Verilog code for an 8 bit shift left register with a negative edge clock a clock enable a serial in and a serial out module shift
173. b c or if inl out 1 b0 else out in2 As the name implies these types of assignments block the current process from continuing to execute additional statements at the same time These should mainly be used in simulation Non blocking assignments on the other hand evaluate the expression when the statement executes but allow other statements in the same process to execute as well at the same time The variable change only occurs after the specified delay XST User Guide www xilinx com 307 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support The syntax for a non blocking procedural assignment is as follows variable lt posedge_or_negedge_bit expression The following shows an example of how to use a non blocking procedural assignment if inl out lt 1 b1 else out lt in2 Constants Macros Include Files and Comments This section discusses constants macros include files and comments Constants By default constants in Verilog are assumed to be decimal integers They can be specified explicitly in binary octal decimal or hexadecimal by prefacing them with the appropriate syntax For example 4 b1010 4012 4410 and 4ha all represent the same value Macros Verilog provides a way to define macros as shown in the following example define TESTEO1 4 b1101 Later in the design code a reference to the defined macro is made as follows if request TESTEOQI1
174. b z sharedlibs shlib User 3 will also set XSTHDPDIR c temp Define this parameter globally with the set xsthdpdir command line option before running the run command Following is the basic syntax set xsthdpdir directory The command can accept a single path only You must specify the directory you want to use There is no default In Project Navigator specify xsthdpdir globally with the VHDL Work Directory option of the Synthesis Options tab in the Process Properties dialog box www xilinx com 225 1 800 255 7778 7 XILINX Chapter 5 Design Constraints HDL Constraints This section describes encoding and extraction constraints Most of the constraints can be set globally in the HDL Options tab of the Process Properties dialog box in Project Navigator The only constraints that cannot be set in this dialog box are Enumerated Encoding and Signal Encoding The constraints described in this section apply to FPGAs CPLDs VHDL and Verilog e Automatic FSM Extraction The Automatic FSM Extraction FSM_EXTRACT constraint enables or disables finite state machine extraction and specific synthesis optimizations This option must be enabled in order to set values for the FSM Encoding Algorithm and FSM Flip Flop Type See F5M EXTRACT in the Constraints Guide for details e Enumerated Encoding VHDL The Enumerated Encoding ENUM_ENCODING constraint can be used to apply a specific encoding to a VHDL enumerated type See ENUM
175. ble lists the expressions supported by XST Table 7 1 Expressions Concatenation Supported Replication Supported uu Supported Arithmetic Supported only if second operand is a power of 2 Modulus Supported only if second operand is a power of 2 Addition Supported Subtraction Supported Multiplication Supported XST User Guide www xilinx com 295 1 800 255 7778 XILINX 296 Table 7 1 Expressions Chapter 7 Verilog Language Support Power dl Supported Both operands must be constants with the second operand being non negative If the first operand is a 2 then the second operand may be a variable XST does not support the real data type Any combination of operands that results in a real type causes an error The values X unknown and Z high impedance are not allowed Division Supported XST generates incorrect logic for the division operator between signed and unsigned constants Example 1235 3 b111 Remainder Supported Relational gt lt gt lt Supported Logical Negation Supported Logical AND amp amp Supported Logical OR LI Supported Logical Equality Supported Logical Inequality I Supported Case Equality Supported Case Inequality l Supported Bitwise Negation Supported Bitwise AND amp Supported Bitwise Inclusive OR Supported Bitwise Excl
176. ce improvement or for satisfying MAX_FANOUT constraints Register replication can be turned off using the REGISTER_DUPLICATION constraint XST User Guide www xilinx com 189 1 800 255 7778 XILINX Chapter 3 FPGA Optimization Following is a portion of the log file Starting low level synthesis Optimizing unit lt down4cnt gt Optimizing unit doc readwrite Optimizing unit doc Building and optimizing final netlist Register doc readwrite state D2 equivalent to doc readwrite cnt ld has been removed Register I cci i2c wr l equivalent to wr 1 has been removed Register doc reset I reset out has been replicated 2 time s Register wr l has been replicated 2 time s Resource Usage In the Final Report the Cell Usage section reports the count of all the primitives used in the design These primitives are classified in the following groups 190 BELS This group contains all the logical cells that are basic elements of the Virtex technology for example LUTs MUXCY MUXF5 MUXF6 MUXF7 MUXF8 Flip flops and Latches This group contains all the flip flops and latches that are primitives of the Virtex technology for example FDR FDRE LD RAMS This group contains all the RAMs SHIFTERS This group contains all the shift registers that use the Virtex primitives They are SRL16 SRL16 1 SRL16E SRL16E 1 and SRLC Tristates This group contains all the tristate primitives
177. chi of counter is signal tmp std logic vector 3 downto 0 begin process C begin if C event and C 1 then if S 1 then tmp 1111 else tmp tmp 1 end if end if end process Q lt tmp end archi 56 www xilinx com XST User Guide 1 800 255 7778 Counters XILINX Verilog Code Following is the Verilog code for a 4 bit unsigned down counter with synchronous set module counter C S Q input C 9 output 3 0 Q reg 3 0 tmp always posedge C begin if S tmp 4 b1111 else tmp tmp 1 b1 end assign Q tmp endmodule 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input The following table shows pin definitions for a 4 bit unsigned up counter with an asynchronous load from the primary input IO Pins Description C Positive Edge Clock ALOAD Asynchronous Load active High D 3 0 Data Input Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned up counter with an asynchronous load from the primary input library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity counter is port C ALOAD in std logic D in std logic vector 3 downto 0 Q out std logic vector 3 downto 0 end counter XST User Guide www xilinx com 57 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of counter is signal tmp std_logic_vector 3 downto 0 begin
178. cing of progressive unit optimizations Optimizing unit unit_name e Information warnings or fatal messages related to unit optimization When equation shaping is applied XC9500 devices only Collapsing Removing equivalent flip flops Register ffl equivalent to ff2 has been removed User constraints fulfilled by XST implementation constraint constraint_name value signal_name e Final results statistics Final Results Top Level Output file name file_name Output format ngc Optimization goal area speed Target Technology 9500 9500x1 9500xv xpla3 xbr cr2s Keep Hierarchy yes soft no Macro Preserve yes no XOR Preserve yes no Design Statistics NGC Instances nb of instances I Os nb of io ports XST User Guide www xilinx com 205 1 800 255 7778 7 XILINX Chapter 4 CPLD Optimization Macro Statistics n bit up FSMs nb_of_FSMs Registers nb_of_registers Tristates nb_of_tristates Comparators nb_of_comparators n bit comparator equal not equal greater less greatequal lessequal nb_of_n_bit_comparators Multiplexers nb_of_multiplexers n bit m to 1 multiplexer nb of n bit m to 1 multiplexers Adders Subtractors nb of adds subs n bit adder nb of n bit adds n bit subtractor nb of n bit subs Multipliers nb of multipliers Logic Shifters nb of logic shifters Counters nb of counters down updown count
179. component instantiation XST links the component to the entity with the same name and same interface and the selected architecture to the most recently compiled architecture If no entity architecture is found a black box is generated during synthesis Generic Parameter Declaration Generic parameters may be declared in the entity declaration part XST supports all types for generics including integer boolean string real std logic vector etc An example of using generic parameters would be setting the width of the design In VHDL describing circuits with generic ports has the advantage that the same component can be repeatedly instantiated with different values of generic ports as shown in Example 6 4 Example 6 4 Generic Instantiation of Components Library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all entity addern is generic width integer 8 port A B in std logic vector width 1 downto 0 Y out std logic vector width 1 downto 0 end addern XST User Guide www xilinx com 265 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support architecture bhv of addern is begin Y lt A B end bhv Library IEEE use IEEE std_logic_1164 all entity top is port X Y Z in std logic vector 12 downto 0 A B in std logic vector 4 downto 0 S out std logic vector 16 downto 0 end top archite
180. ct file my proj prj with the following contents vhdl vhlibl f1 vhd verilog rtfllib fl v vhdl vhlib2 f3 vhd and an LSO file my proj 1so created with the following contents personal_lib rtfllib vhlib2 vhlibl XST User Guide www xilinx com 331 1 800 255 7778 7 XILINX Chapter 8 Mixed Language Support XST uses the following search order rtfllib vhlib2 vhlibl After processing the contents of my proj 1so will be rtfllib vhlib2 vhlibl 332 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis Introduction XST User Guide This chapter contains the following sections Introduction Reducing the Size of the LOG File Timing Report FPGA Log File CPLD Log File The XST log file related to FPGA optimization contains the following sections Copyright Statement Table of Contents Use this section to quickly navigate to different LOG file sections Note These headings are not linked Use the Find function in your text editor to navigate Synthesis Options Summary HDL Compilation See HDL Analysis below HDL Analysis During HDL Compilation and HDL Analysis XST parses and analyzes VHDLY Verilog files and gives the names of the libraries into which they are compiled During this step XST may report potential mismatches between synthesis and simulation results potential multi sources and other issues HDL Synthesis cont
181. cture bhv of top is component addern generic width integer 8 port A B in std logic vector width 1 downto 0 Y out std logic vector width 1 downto 0 i end component for all addern use entity work addern bhv signal Cl std logic vector 12 downto 0 signal C2 C3 std logic vector 16 downto 0 begin Ul addern generic map n gt 13 port map X Y C1 C2 lt Cl amp A C3 lt Z B U2 addern generic map n gt 17 port map C2 C3 S end bhv Combinatorial Circuits The following subsections describe how XST uses various VHDL constructs for combinatorial circuits Concurrent Signal Assignments Combinatorial logic may be described using concurrent signal assignments which can be defined within the body of the architecture VHDL offers three types of concurrent signal assignments simple selected and conditional You can describe as many concurrent statements as needed the order of concurrent signal definition in the architecture is irrelevant A concurrent assignment is made of two parts left hand side and right hand side The assignment changes when any signal in the right part changes In this case the result is assigned to the signal on the left part Simple Signal Assignment The following example shows a simple assignment T lt A and B 266 www xilinx com XST User Guide 1 800 255 7778 Combinatorial Circuits 7 XILINX Selected Signal Assignment The follow
182. d Multiplier For Virtex II II Pro II Pro X in instances where a multiplier would have a registered output XST infers a unique registered multiplier This registered multiplier is 18x18 bits Under the following conditions a registered multiplier is not used and a multiplier register is used instead e Output from the multiplier goes to any component other than the register e The MULT STYLE constraint is set to lut e The multiplier is asynchronous e The multiplier has control signals other than synchronous reset or clock enable e The multiplier does not fit in a single 18x18 bit block multiplier 110 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations 7 XILINX The following pins are optional for a registered multiplier e clock enable port e synchronous and asynchronous reset and load ports Multiplication with Constant When one of the arguments is a constant XST can create an efficient dedicated implementation called a multiplier with constant or KCM Please note that in the current release XST does not infer a KCM automatically for such multipliers A KCM must be implemented via the MULT STYLE constraint Limitations If the either of the arguments is larger than 29 bits XST does not use KCM implementation even if it is specified with the MULT STYLE constraint Log File The XST log file reports the type and size of recognized multipliers during the Macro Recognition step Syn
183. d using parameterized blocks in a design to achieve hierarchy and stimulate modular design techniques The following is an example of the use of parameters Null string parameters are not supported Example 7 13 Using Parameters module lpm_reg out in en reset clk parameter SIZE 1 input in en reset clk output out wire SIZE 1 0 in reg SIZE 1 0 out always posedge clk or negedge reset begin if reset out lt bU else if en out lt in else out lt out redundant assignment end endmodule module top portlist left blank intentionally wire 7 0 sys_in sys_out wire sys_en sys_reset sysclk lpm reg 48 buf 373 sys out sys in sys en sys reset sysclk endmodule Instantiation of the module lpm_reg with a instantiation width of 8 causes the instance buf 373 to be 8 bits wide Verilog Limitations in XST This section describes Verilog limitations in XST support for case sensitivity and blocking and nonblocking assignments Case Sensitivity XST supports case sensitivity as follows e Designs can use case equivalent names for I O ports nets regs and memories e Equivalent names are renamed using a postfix rnm lt Index gt e A rename construct is generated in the NGC file e Designs can use Verilog identifiers that differ only in case XST renames them using a postfix as with equivalent names XST User Guide www xilinx com 313 1 800 255 7778 XILINX Chapte
184. d_logic_vector 3 downto 0 doa out std_logic_vector 3 downto 0 dob out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addra std logic vector 4 downto 0 signal read addrb std logic vector 4 downto 0 begin process clka begin if clka event and clka 1 then if wea 1 then RAM conv integer addra lt dia end if read addra lt addra end if end process XST User Guide www xilinx com 149 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques process clkb begin if clkb event and clkb 1 then read addrb lt addrb end if process doa lt RAM read addra dob lt RAM read addrb end syn Verilog Following is the Verilog code for a dual port RAM with different clocks module raminfr clka clkb wea addra addrb dia doa input clka input clkb input wea input 4 0 addra input 4 0 addrb input 3 0 dia output 3 0 doa output 3 0 dob reg 3 0 RAM 31 0 reg 4 0 read addra reg 4 0 read addrb always posedge clka begin if wea 1 b1 RAM addra lt dia addr rega lt addra end always posedge clkb begin addr regb lt addrb end assign doa RAM addr rega assign dob RAM addr regb endmodule Multiple Port RAM Descriptions dob XST can identify
185. declared reg or wire the left and right bit positions are defined in square brackets separated by a colon In Verilog 2001 both reg and wire data types can be signed or unsigned Example reg 3 0 arb_priority wire 31 0 arb_request wire signed 8 0 arb_signed where arb_request 31 is the MSB and arb request 0 is the LSB Initial Values In Verilog 2001 you can initialize registers when you declare them The value e Must be a constant e Cannot depend on earlier initial values e Cannot be a function or task call e Can be a parameter value propagated to the register When you give a register an initial value in a declaration XST sets this value on the output of the register at global reset or at power up A value assigned this way is carried in the NGC file as an INIT attribute on the register and is independent of any local reset Example reg arb_onebit 1 b0 reg 3 0 arb_priority 4 b1011 You can also assign an set reset initial value to a register via your behavioral Verilog code Do this by assigning a value to a register when the register s reset line goes to the appropriate value as in the following example www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features Z XILINX Example always posedge clk begin if rst arb_onebit lt 1 b0 end end When you set the initial value of a variable in the behavioral code it is implemented in the design as a flip
186. design in the Source window le File Edi View Project Source Process Window iit 0 s u ait jn SourcesinProjeet E readme xcv5 Bbg255 g BE Module View t3 Snapshot View Processes for Source decode o iu a Qo Maps m zi BE Process View E I stopwatch_tb stopwatch tb tbw E stopwatch stopwatch sch E o O ld e CXV Implement Design a QA Translate six ES cnt60 ent60 sch decode decode vhd hex2led hex2led vhd outs3 outs3 sch stmach v stmach v vhd tenths tenths co Library View Add Existing Source Create New Source Design Entry Utilities X39 Create Schematic Symbol BE A View Command Line Loa File E View VHDL Instantiation Template User Constraints 6 Create Timing Constraints ES Assign Package Pins ES Create Area Constraints 4 Edit Constraints Text E View Synthesis Report fq View RTL Schematic GA Check Syntax 2 Tosetthe options right click Synthesize XST in the Process window 24 www xilinx com 1 800 255 7778 XST User Guide XST in Project Navigator XST User Guide 7 XILINX 3 Select Properties to display the Process Properties dialog box lIClockNets Yes 4 Set the desired Synthesis HDL and Xilinx Specific Options For a complete description of these options refer to General Constraints in Chapter 5 www xilinx com 1 8
187. dress di Data Input do Data Output www xilinx com 133 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Following is the VHDL code for a single port RAM with synchronous read read through library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity raminfr is port Clk in std logic we in std logic a in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read a std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if read_a lt a end if end process do lt RAM conv integer read a end syn Verilog Following is the Verilog code for a single port RAM with synchronous read read through module raminfr clk we a di do input clk input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 4 0 read a always posedge clk begin if we ram a lt di read a lt a end assign do ram read a endmodule 134 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs lt XILINX Single Port RAM with Enable The following description implements a single port RAM with a global enable A DO EN WE Bl
188. dt d et 97 gs 98 Related Constraints 2 0 0 000 eer rrr 98 Example duarte ta tdg tales P peau 98 MET Li a RR eR E are GC enin c Ee v Iced Le eir 98 Verllog x vise usa t EEG x ede ia 99 Example 2 a daa a Ea EE EE n s C ME A 99 VADC Zack Re EAE axe EY ended redes 24604 Le CR eave 99 MGTIO e tu vga EAM DEL Cle cct SD LM ii pie et 100 Example 3 45 alt Eos eve Ae whan an vu eg e OS ced 100 MEL eet tere teca ea acere eie rate va raa A A ESA RT AS a 100 Verllog sd br ictu toLku e ORE rr reb tb EE ias be e qug 101 Arithmetic Operations 14 Cete atr dc AAN ER AIR AIR AAA T GEI 101 Adders Subtractors Adders Subtractors 0 0 0 0 102 Log Fleur Er 102 Related Constraints 0 02404 a eru be Vek EET HE eee dd 102 Unsigned 8 bit Addis o e d ERRARE eR 102 Unsigned 8 bit Adder with Carry In 0 ce o 103 Unsigned 8 bit Adder with Carry Out 0 eee tenes 104 Unsigned 8 bit Adder with Carry In and Carry Out 00 0 0 00 c ee eee eee 105 Simple Signed 8 bit Adder 00 cece cee tee teen e eens 106 Unsigned 8 bit S btractor se cziecckru ski e e is teed reek ened 107 Unsigned 8 bit Adder Subtractor 06 cece eee 108 Comparators gt Tossa euer tan ove ria 109 rds c EDU 109 Unsigned 8 bit Greater or Equal Comparator 1 06 eee eens 109 Multiplierss ans voee noue e Ti ei cl cia 110 Large Multipliers Using Block Multipliers 110 Registered Multiplicar A A eine he ee caesus 110 Multiplication with Constant
189. e When you implement a divider with a constant with the power of 2 XST does not issue any message during the Macro Recognition step In case your divider does not correspond to the case supported by XST the following error message displays ERROR Xst 719 filel vhd Line 172 Operator is not supported yet DIVIDE Related Constraints There are no related constraints available Division By Constant 2 This section contains VHDL and Verilog descriptions of a Division By Constant 2 divider The following table shows pin descriptions for a Division By Constant 2 divider IO pins Description DI 7 0 Division Operands DO 7 0 Division Result VHDL Following is the VHDL code for a Division By Constant 2 divider library ieee use ieee std logic 1164 all use ieee numeric std all entity divider is port DI in unsigned 7 downto 0 DO out unsigned 7 downto 0 end divider architecture archi of divider is begin DO lt DI 2 end archi XST User Guide www xilinx com 117 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Following is the Verilog code for a Division By Constant 2 divider module divider DI DO input 7 0 DI output 7 0 DO assign DO DI 2 endmodule Resource Sharing The goal of resource sharing also known as folding is to minimize the number of operators and the subsequent logic in the synthesized design This optimi
190. e 5 2 Synthesis Options CPLD MPG OG VONG DODU O E lol lll XST User Guide www xilinx com 1 800 255 7778 211 XILINX 212 Chapter 5 Design Constraints Following is a list of the Synthesis Options that can be selected from the dialog boxes e Optimization Goal e Optimization Effort e Synthesis Constraint File e Library Search Order e Use Synthesis Constraints File e Keep Hierarchy e Global Optimization Goal e Generate RTL Schematic e Read Cores e Cores Search Directories e Write Timing Constraints e Cross Clock Analysis e Hierarchy Separator e Bus Delimiter e Slice Utilization Ratio e Case e HDL Library Mapping File INI File e Work Directory e Verilog 2001 e Verilog Include Directories Verilog Only e Custom Compile File List e Other Command Line Options To view these options go the Edit drop down menu click Preferences click the Processes tab and set the Property Display Level to Advanced www xilinx com XST User Guide 1 800 255 7778 Setting Global Constraints and Options HDL Options 7 XILINX With the Process Properties dialog box displayed for the Synthesize XST process select the HDL Option tab For FPGA device families the following dialog box displays Sm Dption HDL Option Xilinx Specific Options FSM Encoding Algorithm Case Implementation Style FSM Style RAM
191. e Clock enable function will be implemented through equivalent logic Keeping or not keeping the clock enable signal depends on the design logic Sometimes when the clock enable is the result of a Boolean expression saying no with this option may improve the fitting result because the input data of the flip flop is simplified when it is merged with the clock enable expression Define this constraint globally with the pld ce command line option of the run command Following is the basic syntax pld ce YES NO The default is yes In Project Navigator specify PLD CE globally with the Clock Enable option in the Xilinx Specific Options tab of the Process Properties dialog box within the Project Navigator www xilinx com 231 1 800 255 7778 2 XILINX 232 Chapter 5 Design Constraints Data Gate The CoolRunner II IIS DataGate DATA_GATE feature provides direct means of reducing power consumption in your design Each I O pin input signal passes through a latch that can block the propagation of incident transitions during periods when such transitions are not of interest to your CPLD design Input transitions that do not affect the CPLD design function still consume power if not latched as they are routed among the CPLD s Function Blocks By asserting the DataGate control I O pin on the device selected I O pin inputs become latched thereby eliminating the power dissipation associated with external transitions on those pins
192. e area constraint This means that if the area constraint is not met but the difference between the requested area and obtained area during area optimization is less or equal then 5 then XST runs timing optimization taking into account the achieved area not exceeding it 188 www xilinx com XST User Guide 1 800 255 7778 Log File Analysis Z XILINX In the following example the area was specified as 55 XST achieved only 60 But taking into account that the difference between requested and achieved area is not more than 5 XST considers that area constraint was met Low Level Synthesis Found area constraint ratio of 55 5 on block fpga hm actual ratio is 64 Optimizing block lt fpga_hm gt to meet ratio 55 5 of 1536 slices Area constraint is met for block lt fpga_hm gt final ratio is 60 SLICE_UTILIZATION_RATIO constraint can be attached to a specific block of a design Please refer to the Constraint Guide for more information Log File Analysis The XST log file related to FPGA optimization contains the following sections e Design optimization e Resource usage report e Timing report Design Optimization During design optimization XST reports the following e Potential removal of equivalent flip flops Two flip flops latches are equivalent when they have the same data and control pins e Register replication Register replication is performed either for timing performan
193. e for a 4 bit unsigned up accumulator with an asynchronous clear module accum C CLR D Q input C CLR input 3 0 D output 3 0 Q reg 3 0 tmp always G8 posedge C or posedge CLR begin if CLR tmp 4 b0000 else tmp tmp D end assign Q tmp endmodule Related Constraints There are no related constraints available XST User Guide www xilinx com 67 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Shift Registers In general a shift register is characterized by the following control and data signals which are fully recognized by XST e clock e serial input e asynchronous set reset e synchronous set reset e synchronous asynchronous parallel load e clock enable e serial or parallel output The shift register output mode may be serial only the contents of the last flip flop are accessed by the rest of the circuit parallel the contents of one or several flip flops other than the last one are accessed e shift modes left right etc There are different ways to describe shift registers For example in VHDL you can use e concatenation operator shreg lt shreg 6 downto 0 amp SI e for loop construct for iin 0 to 6 loop shreg i 1 lt shreg i end loop shreg 0 lt SI e predefined shift operators for example sll srl Consult the VHDL Verilog language reference manuals for more information FPGAs Before writing shift register behavior it is impor
194. e macro generation is decided by the Macro Preserve option which can take two values yes macro generation is allowed no macro generation is inhibited The general macro generation flow is the following 1 HDL infers macros and submits them to the low level synthesizer 2 Low level synthesizer accepts or rejects the macros depending on the resources required for the macro implementations An accepted macro is generated by an internal macro generator A rejected macro is replaced by equivalent logic generated by the HDL synthesizer A rejected macro may be decomposed by the HDL synthesizer into component blocks so that one component may be a new macro requiring fewer resources than the initial one and another smaller macro www xilinx com XST User Guide 1 800 255 7778 Log File Analysis 7 XILINX may be accepted by XST For instance a flip flop macro with clock enable CE cannot be accepted when mapping onto the XC9500 In this case the HDL synthesizer submits two new macros e a flip flop macro without clock enable signal a MUX macro implementing the clock enable function A generated macro is optimized separately and then merged with surrounded logic because the optimization process gives better results for larger components Log File Analysis XST messages related to CPLD synthesis are located after the following message Low Level Synthesis The log file produced by XST contains e Tra
195. e new or old style If the extension is not xcf XST will interpret it as the old constraint style Please refer to XST Constraint File XCF and Old XST Constraint Syntax for details on using the new and old constraint styles www xilinx com XST User Guide 1 800 255 7778 General Constraints XST User Guide 7 XILINX Specify a file name with the uc command line option of the run command Following is the basic syntax uc filename In Project Navigator specify a synthesis file with the Use Synthesis Constraints File option in the Synthesis Options tab of the Process Properties dialog box Translate Off Translate On Verilog VHDL The Translate Off TRANSLATE OFF and Translate On TRANSLATE ON directives can be used to instruct XST to ignore portions of your VHDL or Verilog code that are not relevant for synthesis for example simulation code The TRANSLATE OFF directive marks the beginning of the section to be ignored and the TRANSLATE ON directive instructs XST to resume synthesis from that point See TRANSLATE OFF and TRANSLATE ON in the Constraints Guide for details Use Synthesis Constraints File The Use Synthesis Constraints File iuc command line option allows you to ignore the constraint file during synthesis Define this option globally with the iuc command line option of the run command Following is the basic syntax iuc yes no The default is no In Project Navigator specify iuc globally by s
196. e new project format To create a project file containing only VHDL files place a list of VHDL files preceded by keyword VHDL in a separate file The order of the files is not important XST can recognize the hierarchy and compile VHDL files in the correct order For the example perform the following steps 1 Open a new file called watchvhd prj 2 Enter the names of the VHDL files in any order into this file and save the file vhdl work statmach vhd vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work vhdl tenths vhd vhdl work hex2led vhd 3 Tosynthesize the design execute the following command from XST shell or via script file run ifn watchvhd prj ifmt mixed ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 If you want to synthesize just hex2led and check its performance independently of the other blocks you can specify the top level entity to synthesize in the command line using the top option please refer to Table 10 2 page 352 for more details run ifn watchvhd prj ifmt mixed ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 top hex2led XST User Guide www xilinx com 359 1 800 255 7778 360 7 XILINX Chapter 10 Command Line Mode During VHDL compilation XST uses the library work as the default If some VHDL files must be compiled to different libraries then you can add the name of the libr
197. e past XST supported limited private timing constraints Xilinx continues to support the old constraint syntax without any further enhancements for this release of XST but will eventually drop support Please refer to Old Timing Constraint Support in release 5 1i of the XST User Guide for details on using the old constraint style Xilinx strongly suggests that you use the newer XCF syntax constraint style for new devices Constraints Summary 238 Table 5 1 summarizes all available XST specific non timing related options with allowed values for each the type of objects they can be applied to and usage restrictions Default values are indicated in bold www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX Table 5 1 XST Specific Non timing Options Command Command XCF XCF n 5 Ws Constraint Constraint Constraint Line Old XST Old XST Technology Name Syntax Syntax Value Target Constraint Constraint Syntax Syntax Value Target XST Constraints box type primitive model no primitive VHDL Spartan IT IIE 3 black_box inst in model black_box component Virtex TI II Pro user_black_ user_black_ entity II Pro X E XC9500 box box CoolRunner XPLA3 Verilog label module buffer type bufedll net in model no bufgdll signal Spartan I IIE 3 ibufg bufgp ibufg bufgp Virtex M TI II Pro ibuf none ibuf none II Pro X
198. ed within a package The ADD function declared here is a single bit adder This function is called 4 times with the proper parameters in the architecture to create a 4 bit adder The same example described using a procedure is shown in Example 6 24 Example 6 23 Function Declaration and Function Call package PKG is function ADD A B CIN BIT return BIT_VECTOR end PKG package body PKG is function ADD A B CIN BIT return BIT_VECTOR is variable S COUT BIT variable RESULT BIT_VECTOR 1 downto 0 begin S A xor B xor CIN COUT A and B or A and CIN or B and CIN RESULT COUT S return RESULT end ADD end PKG use work PKG all entity EXAMPLE is port A B in BIT_VECTOR 3 downto 0 CIN in BIT S out BIT VECTOR 3 downto 0 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is signal SO S1 S2 S3 BIT VECTOR 1 downto 0 begin SO lt ADD A 0 B 0 CIN S1 lt ADD A 1 B 1 SO 1 S2 lt ADD A 2 B 2 S1 1 S3 lt ADD A 3 B 3 S2 1 S lt S3 0 S2 0 S1 0 amp SO 0 COUT S3 1 end ARCHI XST User Guide www xilinx com 277 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support Example 6 24 Procedure Declaration and Procedure Call package PKG is procedure ADD A B CIN in BIT C out BII VECTOR 1 downto 0 i end P
199. ee use ieee std_logic_1164 all library unisim use unisim vcomponents all entity lut2_attribute is port IO ILl i in std logic O out std logic end lut2 attribute architecture beh of lut2 attribute is attribute INIT string attribute INIT of inst label is 1 begin inst LUT2 port map 10 gt 10 11 gt 11 0 gt 0 end beh Following is the VHDL code for passing an INIT value via the generics mechanism library ieee use ieee std logic 1164 a11 library unisim use unisim vcomponents all entity lut2 generics is port 10 11 in std logic O out std logic i end lut2_generics architecture beh of lut2_generics is begin inst LUT2 generic map INIT gt 1 port map 10 gt 10 11 gt 11 0 gt 0 end beh XST User Guide www xilinx com 195 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization Verilog Following is the Verilog code for passing an INIT value via the INIT constraint module vlut2 attribute 10 11 0 5 input I0 11 output 0 LUT2 inst IO IO 11 11 O 0 synthesis attribute INIT of inst is 2 endmodule Following is the Verilog code for passing an INIT value via the parameters mechanism module vlut2 parameter I0 11 0 input 10 11 output O LUT2 4 h2 inst 10 10 I1 I1 0O 0 endmodule Log File XST does not issue any message concerning instantiation of Virtex primitives during HDL synthesis because the BOX TYPE attribute with its
200. ee std_logic_1164 all use ieee std_logic_signed all entity adder is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 end adder architecture archi of adder is begin SUM lt A B end archi Verilog Following is the Verilog code for a simple signed 8 bit adder module adder A B SUM input signed 7 0 A input signed 7 0 B output signed 7 0 SUM wire signed 7 0 SUM assign SUM A B endmodule Unsigned 8 bit Subtractor The following table shows pin descriptions for an unsigned 8 bit subtractor 10 pins Description A 7 0 B 7 0 Sub Operands RES 7 0 Sub Result VHDL Following is the VHDL code for an unsigned 8 bit subtractor library ieee use leee std_logic_1164 all use ieee std logic unsigned all entity subtr is port A B in std logic vector 7 downto 0 RES out std logic vector 7 downto 0 end subtr architecture archi of subtr is begin RES lt A B end archi XST User Guide www xilinx com 107 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Following is the Verilog code for an unsigned 8 bit subtractor module subtr A B RES input 7 0 A input 7 0 B output 7 0 RES RM assign RES A endmodule B Unsigned 8 bit Adder Subtractor The following table shows pin descriptions for an unsigned 8 bit adder subtractor IO pins Descriptio
201. ee the TIMING REPORT section of the example given in the FPGA Log File section for an example of the timing report sections in the XST log FPGA LogFile Release Copyrig The following is an example of an XST log file for FPGA synthesis 6 1i xst G 23 ht c 1995 2003 Xilinx Inc All rights reserved TABLE O F CONTENTS 1 Synthesis Options Summary HD 4 3 HD 4 HDL Compilation L Analysis L Synthesis 1 HDL Synthesis Report 5 Advanced HDL Synthesis 6 Low Level Synthesis 7 Final Report Ta 7 1 Device utilization summary 2 TIMING REPORT 336 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File m Synthesis Options Summary Source Parameters Input File Name Input Format Ignore Synthesis Constraint File Verilog Search Path Verilog Include Directory Target Parameters Output File Name Output Format Target Device Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm FSM Style RAM Extraction RAM Style ROM Extraction ROM Style Mux Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing Resource Sharing Multiplier Style Automatic Register Balancing Target Options Add IO Buffers Global Maximum Fanout Add Generic Clock Buffer BUFG Register Duplication Equivalent register
202. el Data Input Port optional CIkEn Clock Enable optional LeftRight Direction selection optional SeriallnRight Serial Input Right for Bidirectional Shift Register optional PSO x 0 Serial or Parallel Output The recognition of dynamic shift register happens in the Advanced HDL Synthesis step This is why no message about a dynamic shift register is displayed during HDL synthesis step Instead an n bit register and a multiplexer is inferred Synthesizing Unit dynamic srl Related source file is dynamic srl vhd Found 1 bit 16 to 1 multiplexer for signal lt Q gt Found 16 bit register for signal data Summary inferred 16 D type flip flop s inferred 1 Multiplexer s Unit dynamic srl synthesized www xilinx com 81 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The notification that XST recognized a dynamic shift register is displayed only in the Macro Statistics section of the Final Report Macro Statistics Shift Registers 2 1 16 bit dynamic shift register 1 Related Constraints A related constraint is SHREG EXTRACT VHDL Code Following is the VHDL code for a 16 bit dynamic shift register library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all o entity shiftregluts is port CLK in std logic DATA in std logic CE in std logic A in std logic vector 3 downto 0 Q out s
203. electing the Use Synthesis Constraints File option under the Synthesis Options tab in the Process Properties dialog box Verilog Include Directories Verilog Only Use the Verilog Include Directories option vlgincdir to enter discrete paths to your Verilog Include Directories Define this option globally with the vlgincdir command line option of the run command Allowed values are names of directories vlgincdir directory path directory path There is no default In Project Navigator specify this option with the Verilog Include Directories option of the Synthesis Options tab in the Process Properties dialog box Allowed values are names of directories There is no default Verilog 2001 The Verilog 2001 verilog2001 command line option enables or disables interpreted Verilog source code as the Verilog 2001 standard By default Verilog source code is interpreted as the Verilog 2001 standard Define this option globally with the verilog2001 command line option of the run command Following is the basic syntax verilog2001 yes no The default is yes In Project Navigator set verilog2001 globally with the Verilog 2001 option in the Synthesis Options tab of the Process Properties dialog box www xilinx com 223 1 800 255 7778 lt XILINX 224 Chapter 5 Design Constraints HDL Library Mapping File INI File Use the HDL Library Mapping File command xsthdpini to define the library mapping In the 4 li version o
204. end if end process do lt RAM conv_integer ra The RAM initial contents can be specified in hexadecimal as in the previous example or in binary as shown in the following example type ram_type is array 0 to SIZE 1 of std_logic_vector 15 downto 0 signal RAM ram type 0111100100000101 0000010110111101 1100001101010000 0000100101110011 Verilog XST does not support block RAM initialization in Verilog XST User Guide www xilinx com 155 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Limitations e Initialization is only valid for block RAM resources If you attempt to initialize distributed RAM XST ignores the initialization and issues a warning message e Initialization is only valid for single port RAM If you attempt to initialize multiple port RAM XST ignores the initialization and issues a warning message e Initialization of inferred RAMs from RTL code is not supported via INIT constraints Use of INIT constraints is only supported if RAM primitives are directly instantiated from the UNISIM library ROMs Using Block RAM Resources XST can use block RAM resources to implement ROMs with synchronous outputs or address inputs These ROMs are implement as single port block RAMs The use of block RAM resources to implement ROMs is controlled by the ROM STYLE constraint Please see Chapter 5 Design Constraints for details about the ROM SYTLE attribute Please
205. end if end if end process end archi Verilog Code Following is the equivalent Verilog code for the flip flop with a positive edge clock and synchronous set module flop C D S 0 input C D S output O reg OQ always posedge C begin if S Q 1 b1 else Q D end endmodule XST User Guide www xilinx com 1 800 255 7778 43 7 XILINX Chapter 2 HDL Coding Techniques Flip flop with Positive Edge Clock and Clock Enable The following figure shows a flip flop with positive edge clock and clock enable D FDE X8361 The following table shows pin definitions for a flip flop with positive edge clock and clock enable IO Pins Description D Data Input C Positive Edge Clock CE Clock Enable active High Q Data Output VHDL Code Following is the equivalent VHDL code for the flip flop with a positive edge clock and clock enable library ieee use ieee std logic 1164 a11 entity flop is port C D CE in std logic Q out std logic end flop architecture archi of flop is begin process C begin if C event and C 1 then if CE 1 then Q lt D end if end if end process end archi 44 www xilinx com XST User Guide 1 800 255 7778 Registers 7 XILINX Verilog Code Following is the equivalent Verilog code for the flip flop with a positive edge clock and clock enable module flop C D CE Q input C D CE E output O reg OQ
206. ent XST according to the severity level generates a warning message with the reason for the warming or rejects the design and generates an error message and the reason for the rejection Note XST supports the Assert statement only with static condition The following example contains a block SINGE SRL that describes a shift register The size of the shift register depends on the SRL WIDTH generic value The Assert statement ensures that the implementation of a single shift register does not exceed the size of a single SRL Since the size of the SRL is 16 bit and XST implements the last stage of the shift register using a flip flop in a slice then the maximum size of the shift register cannot exceed 17 bits The SINGE SRL block is instantiated twice in the entity named TOP the first time with SRL WIDTH equal to 13 and the second time with SRL WIDTH equal to 18 library ieee use ieee std logic 1164 a11 entity SINGE SRL is generic SRL WIDTH integer 16 port Clk in std logic inp in std logic outp out std logic end SINGE SRL architecture beh of SINGE SRL is signal shift reg std logic vector SRL WIDTH 1 downto 0 begin assert SRL WIDTH 17 report The size of Shift Register exceeds the size of a single SRL severity FAILURE process clk begin if clk event and clk 1 then shift reg lt shift reg SRL WIDTH 1 downto 1 amp inp end if end process outp shift reg
207. eport ig d 2 File Edit View Project Source Process Window Help l0l x laxi bona verse lems ev me x Cx zd 2 y ZB watch sc E readme E stmach_w dia El Ed xcv50 6bg256 E stopwatch stopwatch sch stopwatch_tb stopwatch tt Ig cnt amp O cntEO sch M ai decode y O AddExisting Source FA Create New Source E pA Design Entry Utilities Create Schematic Symb E eff View Command Line Lo far Check Design Rules E ef View VHDL Functional H View VHDL Instantiatior EM User Constraints Create Timing Constrain Assign Package Pins Es pasi Create Area Constraints Edit Constraints Text Synthesize XST 0 i cu View RTL Schematic EX Implement Design as n 1 2 3 4 5 8 7 8 Release 6 1i xst 6 19 Copyright c 1995 2003 Xilinx Inc Parameter TMPDIR set to projnav CPU 0 00 5 23 s Elapsed 0 00 4 00 s Parameter xsthdpdir set to xst CPU 0 00 5 23 s Elapsed 0 00 4 00 s Reading design stopwatch prj TABLE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilation 3 HDL Analysis 4 HDL Synthesis 4 1 HDL Synthesis Report 5 Advanced HDL Synthesis 6 Low Level Synthesis 7 Final Report 7 1 Device utilization summary 7 2 TIMING REPORT Source Parameters Input File Name Verilog Search Path Verilog Include Direc
208. er nb of n bit counters 11 XORs nb_of_xors Usage BELS nb of bels AND nb of and OR aad no loft Or INV nb of inv XOR2 nb of xor2 GND nb of gnd VCC nb of vcc FlipFlops Latches nb of ff latch ED LB Tri States BUFE BUFT IO Buffers IBUF OBUF IOBUF OBUFE OBUFT Others nb nb of fd nb of ld nb of tristates nb of bufe nb of buft nb of iobuffers nb of ibuf nb of obuf nb of iobuf nb of obufe nb of obuft of others 206 www xilinx com XST User Guide 1 800 255 7778 Constraints 7 XILINX Constraints The constraints attributes specified in the HDL design or in the constraint files are written by XST into the NGC file as signal properties Improving Results XST produces optimized netlists for the CPLD fitter which fits them in specified devices and creates the download programmable files The CPLD low level optimization of XST consists of logic minimization subfunction collapsing logic factorization and logic decomposition The result of the optimization process is an NGC netlist corresponding to Boolean equations which are reassembled by the CPLD fitter to fit the best of the macrocell capacities A special XST optimization process known as equation shaping is applied for XC95001M XL XV devices when the following options are selected e Keep Hierarchy no e Optimization Effort 2 e Macro Preserve no The eq
209. er 6 VHDL Language Support Example 6 7 8 Bit Adder Described with a for generate Statement entity EXAMPLE is port A B in BIT VECTOR 0 to 7 CIN in BIT SUM out BIT VECTOR 0 to 7 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is signal C BIT VECTOR 0 to 8 begin C 0 lt CIN COUT lt C 8 LOOP ADD for I in 0 to 7 generate SUM I lt A I xor B I xor C I C 1 1 lt A I and B I or A I and C I or B I and C I end generate end ARCHI The if condition generate statement is supported for static non dynamic conditions Example 6 8 shows such an example It is a generic N bit adder with a width ranging between 4 and 32 Example 6 8 N Bit Adder Described with an if generate and a for generate Statement entity EXAMPLE is generic N INTEGER 8 port A B in BIT VECTOR N downto 0 CIN in BIT SUM out BIT VECTOR N downto 0 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is signal C BIT VECTOR N 1 downto 0 begin L1 if N gt 4 and N lt 32 generate C 0 lt CIN COUT lt C N 1 LOOP_ADD for I in 0 to N generate SUM I lt A I xor B I xor C I C 1 1 lt A I and B I or A I and C I or B I and C I end generate end generate end ARCHI Combinatorial Process A process assigns value
210. esent different state encoding schemes Next State Equations Next state equations can be described directly in the sequential process or in a distinct combinational process The simplest template is based on a Case statement If using a separate combinational process its sensitivity list should contain the state signal and all FSM inputs Unreachable States XST can detect unreachable states in an FSM It lists them in the log file in the HDL Synthesis step FSM Outputs Non registered outputs are described either in the combinational process or in concurrent assignments Registered outputs must be assigned within the sequential process FSM Inputs Registered inputs are described using internal signals which are assigned in the sequential process XST User Guide www xilinx com 167 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques State Encoding Techniques XST supports the following state encoding techniques e Auto e One Hot e Gray e Compact e Johnson e Sequential e User Auto In this mode XST tries to select the best suited encoding algorithm for each FSM One Hot One hot encoding is the default encoding scheme Its principle is to associate one code bit and also one flip flop to each state At a given clock cycle during operation one and only one state variable is asserted Only two state variables toggle during a transition between two states One hot encoding is very appropriate with most FPGA target
211. esign The basic concepts of hardware structure are the component the port and the 262 www xilinx com XST User Guide 1 800 255 7778 Entity and Architecture Descriptions 7 XILINX signal The component is the building or basic block A port is a component I O connector A signal corresponds to a wire between components In VHDL a component is represented by a design entity This is actually a composite consisting of an entity declaration and an architecture body The entity declaration provides the external view of the component it describes what can be seen from the outside including the component ports The architecture body provides an internal view it describes the behavior or the structure of the component The connections between components are specified within component instantiation statements These statements specify an instance of a component occurring inside an architecture of another component Each component instantiation statement is labeled with an identifier Besides naming a component declared in a local component declaration a component instantiation statement contains an association list the parenthesized list following the reserved word port map that specifies which actual signals or ports are associated with which local ports of the component declaration Note XST supports unconstrained vectors in component declarations Example 6 2 gives the structural description of a half adder composed of four nand2
212. esource Sharing RESOURCE_SHARING constraint enables or disables resource sharing of arithmetic operators See the RESOURCE_SHARING section in the Constraints Guide for details e Signal Encoding The Signal Encoding SIGNAL ENCODIN QG constraint can be used to apply a specific encoding to signals See SIGNAL ENCODINC in the Constraints Guide for details 226 www xilinx com XST User Guide 1 800 255 7778 FPGA Constraints non timing XILINX FPGA Constraints non timing This section describes FPGA HDL options These options apply only to FPGAs not CPLDs XST User Guide Buffer Type Buffer Type BUFFER_TYPE is a new name for the CLOCK_BUFFER constraint Since CLOCK_BUFFER will become obsolete in future releases Xilinx strongly suggest that you use this new name This constraint selects the type of buffer to be inserted See BUFFER_TYPE in the Constraints Guide for details BUFGCE The BUFGCE constraint implements BUFGMUX functionality by inferring a BUFGMUX primitive This operation reduces the wiring clock and clock enable signals are driven to n sequential components by a single wire See BUFGCE in the Constraints Guide for details Clock Buffer Type The Clock Buffer Type CLOCK_BUFFER constraint selects the type of clock buffer to be inserted on the clock port In the current release this constraint has been renamed BUFFER_TYPE Since CLOCK_BUFFER will become obsolete in future releases Xilinx
213. ess 0001 then 1100 if address 0010 then 1011 if address 1111 then 0001 A ROM can also be inferred from an array composed entirely of constants as in the following HDL example type ROM TYPE is array 15 downto 0 of std logic vector 3 downto 0 constant ROM rom type 0010 1100 1011 0001 data lt ROM conv integer address The ROM EXTRACT attribute can be used to disable the inference of ROMs Use the value yes to enable ROM inference and no to disable ROM inference The default is yes Two types of ROM are available in the inference and generation stages Distributed ROM and Block ROM e Distributed ROMs are generated by using the optimal tree structure of LUT MUXF5 MUXF6 MUXF7 and MUXES primitives which allows compact implementation of large inferred ROMs www xilinx com XST User Guide 1 800 255 7778 Mapping Logic onto Block RAM 7 XILINX e Block ROMs are generated by using block RAM resources When a synchronous ROM is identified it can be inferred either as a distributed ROM plus a register or it can be inferred using block RAM resources The ROM STYLE attribute specifies what kind of synchronous ROM that XST infers as follows e If set to block and the ROM fits entirely on a single block of RAM XST infers the ROM using block RAM resources e If set to distributed XST infers a distributed ROM plus register e If set to auto XST determines the most efficient method to u
214. ey are not supported for synthesis in XST Example library ieee use IEEE std logic signed all signal a b c std logic vector 5 downto 0 c lt a b this operator is defined in package std logic signed Operands are converted to signed vectors and function defined in package std logic arith is called with signed operands Synopsys Packages 282 The following Synopsys packages are supported in the IEEE library std logic arith supports types unsigned signed vectors and all overloaded arithmetic operators on these types It also defines conversion and extended functions for these types std logic unsigned defines arithmetic operators on std ulogic vector and considers them as unsigned operators std logic signed defines arithmetic operators on std logic vector and considers them as signed operators std logic misc defines supplemental types subtypes constants and functions for the std logic 1164 package and reduce or reduce www xilinx com XST User Guide 1 800 255 7778 VHDL Language Support VHDL Language Support XST User Guide 7 XILINX The following tables indicate which VHDL constructs are supported in XST For more information about these constructs refer to the sections following the tables Table 6 1 Design Entities and Configurations Generics Supported integer type only Entity Header Ports Su
215. f XST HDL library management was significantly enhanced by the introduction of a library mapping file and two new parameters XSTHDPINI and XSTHDPDIR The library mapping file contains the library name and the directory in which this library is compiled XST maintains two library mapping files The pre installed file which is installed during the Xilinx software installation The user file which users may define for their own projects The pre installed default INI file is named xhdp ini and is located in XILINX vhdl xst These files contain information about the locations of the standard VHDL and UNISIM libraries These should not be modified but the syntax can be used for user library mapping This file appears as follows Default lib mapping for XST std XILINX vhdl xst std ieee SXILINX vhdl xst unisim unisim XILINX vhdl xst unisim aim XILINX vhdl xst aim pls SXILINX vhdl xst pls You may use this file format to define where each of your own libraries must be placed By default all compiled VHDL flies will be stored in the xst sub directory of the ISE project directory You may place your custom INI file anywhere on a disk by Selecting the VHDL INI File menu in the Synthesis Options tab of the Synthesis process properties in Project Navigator or Setting up the sthdpini parameter using the following command in stand alone mode set xsthdpini file name You c
216. f s signal is LOW You may specify the same attribute in the XCF file with the following lines ODEL ENTNAME NET s PWR_MODE LOW NE s KEEP END 250 www xilinx com XST User Guide 1 800 255 7778 Third Party Constraints The following statement is written to the NGC file by XST NET s PWR_MODE LOW NE s KEEP 7 XILINX If the attribute applies to an instance for example IOB DRIVE IOSTANDARD and if the instance is not available not instantiated in the HDL source then the HDL attribute can be applied to the signal on which XST infers the instance Third Party Constraints This section describes constraints of third party synthesis vendors that are supported by XST For each of the constraints Table 5 5 gives the XST equivalent and indicates when automatic conversion is available For information on what these constraints actually do please refer to the corresponding vendor documentation Note that NA stands for Not XST User Guide Available Table 5 5 Third Party Constraints Name Vendor XST Equivalent ELE black box Synplicity box type VHDL Verilog black box pad pin Synplicity NA NA black box tri pins Synplicity NA NA cell list Synopsys NA NA clock list Synopsys NA NA Enum Synopsys NA NA full case Synplicity full case Verilog Synopsys i
217. f the XOR preservation done by HDL synthesis and is guided only by the goal of complexity reduction Define this constraint globally with the pld_mp command line option of the run command Following is the basic syntax pld mp yes no The default is yes In Project Navigator specify pld mp globally with the Macro Preserve option in the Xilinx Specific Options tab of the Process Properties dialog box within the Project Navigator www xilinx com 233 1 800 255 7778 X XILINX Chapter 5 Design Constraints Timing Constraints Timing constraints supported by XST can be applied either via the glob_opt command line switch which is the same as selecting Global Optimization Goal from the Synthesis Options tab of the Process Properties menu in Project Navigator or via the constraints file Using the glob_opt Global Optimization Goal method allows you to apply the five global timing constraints ALLCLOCKNETS OFFSET_IN_BEFORE OFFSET_OUT_AFTER INPAD_TO_OUTPAD and MAX_DELAY These constraints are applied globally to the entire design You cannot specify a value for these constraints as XST optimizes them for the best performance Note that these constraints are overridden by constraints specified in the constraints file Using the constraint file method you can use one of two formats XCF timing constraint syntax which XST supports starting in release 5 1i Using the XCF syntax XST supports constraints such as TNM NET TIM
218. f the specified file in this case modules v has been added to an ISE project and is specified with an include conflicts occur and an error message displays ERROR Xst 1068 fifo v line 2 Duplicate declarations of module RAMBA S8 S8 Comments There are two forms of comments in Verilog similar to the two forms found in a language like C e Allows definition of a one line comment e You can define a multi line comment by enclosing it as illustrated by this sentence Generate Statement XST User Guide Generate is a construct that allows you to dynamically create Verilog code from conditional statements This allows you to create repetitive structures or structures that are only appropriate under certain conditions Structures that are likely to be created via a generate statement are e primitive or module instances e initial or always procedural blocks e continuous assignments e net and variable declarations e parameter redefinitions e task or function definitions XST supports the following types of generate statements e generate for e generate if e generate case Generate For Use a generate for loop to create one or more instances that can be placed inside a module Use the generate for loop the same way you would a normal Verilog for loop with the following limitations e The index for a generate for loop must have a genvar variable e The assignments in the for loop control must refer to
219. fete 295 Blocks eoa ERR uA REM Ee ee ie Se eR od alcala 298 Modules imis e a GER ERR PRAG war REA i 298 Module Declaration o ooooooooo han 298 Verilog ASSP NMEN S eraran Ea o eai etes 299 Continuous Assignments osses srere iade ye een 299 Procedural Assignments 66 6 eee i 299 Combinatorial Always Blocks 2 6 ccc cece nee 299 If Else Statement 300 Case Statement s vet tied A A A Yu eee es 300 Forand Repeat ops sii Sens pete eee eet Chus et d edd 301 While LoOps spec pianista ego sebas eiaei bissduiede sited BiDau be 302 Sequential Always Blocks sta i ERR ERA RE ee et 302 Assign and Deassign Statements oooocoococcoocoocco ee 303 Assignment Extension Past 32 Bits 1 6 ee 306 Tasks and Functions 306 Blocking Versus Non Blocking Procedural Assignments 00 000s eee 307 Constants Macros Include Files and Comments llle 308 Constants divas eh a EES oe ha A auem SN ERE ee Ea eA ae a aad 308 XST User Guide www xilinx com 17 1 800 255 7778 lt XILINX Macros es des a vao fre oet ds Seo dt ds 308 Include Piles zen ye ca Daa aa eae EA Ge ee a Ps 308 Comments isaac trar da Ab aa Meee ETE 309 Generate Statement 309 Generate For si cse di a A Ai 309 Generate IE else a ci a da 310 Generate Cases eve kan dns EREPryehPGdor4 d RYE pex a ais ds 310 Structural Verilog Features iii erra etr eo ade doe oe gel e pg 311 Parameters ortis ebore it dea ie E NL e E
220. flop whose output can be controlled by a local reset as such it is carried in the NGC file as an FDP or FDC flip flop Local Reset z Global Reset Note that local reset is independent of global reset Registers controlled by a local reset may be set to a different value than ones whose value is only reset at global reset power up In the following example the register arb onebit is set to 0 at global reset buta pulse on the local reset rst can change it s value to 1 Example module mult clk rst A IN B OUT input clk rst A IN output B OUT reg arb onebit 1 b0 always posedge clk or posedge rst begin if rst arb onebit lt 1 b1 else arb onebit lt A IN end end B OUT arb onebit endmodule This sets the set reset value on the register s output at initial power up but since this is dependent upon a local reset the value changes whenever the local set reset is activated Arrays Verilog allows arrays of reg and wires to be defined as in the following two examples reg 3 0 mem array 31 0 The above describes an array of 32 elements each 4 bits wide which can be assigned via behavioral Verilog code wire 7 0 mem array 63 0 The above describes an array of 64 elements each 8 bits wide which can only be assigned via structural Verilog code Multi dimensional Arrays XST supports multi dimensional array types of up to three dimensions Multi dimensional arrays can be any net o
221. following is an example of the correct use of parameter override ff init 2 b01 ul sel sel din din dout dout The following is an incorrect use of the of parameter override and is not accepted by XST ff ul sel sel din din dout dout defparam ul init 2 b01 www xilinx com 327 1 800 255 7778 7 XILINX Port Mapping Chapter 8 Mixed Language Support XST uses the following rules and limitations for port mapping in mixed language projects For VHDL entities instantiated in Verilog designs XST supports the following port types in out inout Note XST does not support VHDL buffer and linkage ports For Verilog modules instantiated in VHDL designs XST supports the following port types input output inout Note XST does not support connection to bi directional pass switches in Verilog XST does not support unnamed Verilog ports for mixed language boundaries Use an equivalent component declaration for connecting to a case sensitive port in a Verilog module By default XST assumes Verilog ports are in all lower case XST supports the following VHDL data types for mixed language designs bit bit vector e std logic std ulogic std logic vector e std ulogic vector XST supports the following Verilog data types for mixed language designs wire reg Generics Support in Mixed Language Projects XST supports the following VHDL generic types and their
222. from within the Process Properties dialog box in Project Navigator or from the command line e VHDL attributes can be directly inserted into your VHDL code and attached to individual elements of the design to control both synthesis and placement and routing e Constraints can be added as Verilog meta comments in your Verilog code e Constraints can be specified in a separate constraint file Typically global synthesis settings are defined within the Process Properties dialog box in Project Navigator or with command line arguments while VHDL attributes or Verilog meta comments can be inserted in your source code to specify different choices for individual parts of the design Note that the local specification of a constraint overrides its global setting Similarly if a constraint is set both on a node or an instance and on the enclosing design unit the former takes precedence for the considered node or instance Setting Global Constraints and Options This section explains how to set global constraints and options from the Process Properties dialog box within Project Navigator For a description of each constraint that applies generally that is to FPGAs CPLDs VHDL and Verilog refer to the Constraints Guide Note Except for the Value fields with check boxes there is a pull down arrow or browse button in each Value field However you cannot see the arrow until you click in the Value field Synthesis Options 210 T
223. g construct that can be instantiated in a VHDL design is a Verilog module No other Verilog constructs are visible to VHDL code During elaboration all components subject to default binding are regarded as design units with the same name as the corresponding component name In the binding process XST treats a component name as a VHDL design unit name and searches for it in the logical library work If a VHDL design unit is found then XST binds it If XST cannot find a VHDL design unit it treats the component name as a Verilog module name and searches for it using a case sensitive search XST searches for the Verilog module in the user specified list of unified logical libraries in the user specified search order See Library Search Order File for search order details XST selects the first Verilog module matching the name and binds it Note Please remember that since libraries are unified a Verilog cell by the same name as that of a VHDL design unit cannot co exist in the same logical library A newly compiled cell unit overrides a previously compiled one Instantiating a VHDL Design Unit in a Verilog Design XST User Guide To instantiate a VHDL entity declare a module name with the same as name as the VHDL entity optionally followed by an architecture name that you want to instantiate and perform a normal Verilog instantiation The only VHDL construct that can be instantiated in a Verilog design is a VHDL entity No other VHDL cons
224. g control signals are equivalent to the ones described in Registers in this chapter e Clock e Asynchronous Set Clear e Synchronous Set Clear e Clock Enable Moreover XST supports both unsigned and signed counters Log File The XST log file reports the type and size of recognized counters during the Macro Recognition step Synthesizing Unit lt counter gt Related source file is counters l vhd Found 4 bit up counter for signal tmp Summary inferred 1 Counter s Unit counter synthesized HDL Synthesis Report Macro Statistics Counters 1 4 bit up counter c Note During synthesis XST decomposes Counters on Adders and Registers if they do not contain synchronous load signals This is done to create additional opportunities for timing optimization Because of this counters reported during the Macro Recognition step and in the overall statistics of recognized macros may not appear in the final report Adders registers are reported instead Related Constraints There are no related constraints available 54 www xilinx com XST User Guide 1 800 255 7778 Counters 7 XILINX 4 bit Unsigned Up Counter with Asynchronous Clear The following table shows pin definitions for a 4 bit unsigned up counter with an asynchronous clear IO Pins Description C Positive Edge Clock CLR Asynchronous Clear active High Q 3 0 Data Output VHDL Code Following is VHDL code
225. g data types as found in the declaration section of a Verilog module Example 7 1 Basic Data Types wire netl single bit net reg rl single bit register tri 7 0 busl 8 bit tristate bus reg 15 0 busl 15 bit register reg 7 0 mem 0 127 8x128 memory register parameter statel 3 b001 3 bit constant parameter component TMS380C16 string 294 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features 7 XILINX Legal Statements The following are statements that are legal in behavioral Verilog Variable and signal assignment e Variable expression e if condition statement e if condition statement else statement e case expression expression statement default statement endcase e for variable expression condition variable variable expression statement e while condition statement e forever statement e functions and tasks Note All variables are declared as integer or reg A variable cannot be declared as a wire Expressions An expression involves constants and variables with arithmetic logical amp amp amp 11 lt lt gt gt lt lt lt gt gt gt relational lt lt gt gt and conditional operators The logical operators are further divided as bit wise versus logical depending on whether it is applied to an expression involving several bits or a single bit The following ta
226. g fixes 08 28 00 13 Fine tuning of text frame and paragraph format spacings 04 11 01 2 0 Revised formats to take advantage of FrameMaker 6 0 book features 05 02 01 2 1 Master page changes 07 11 01 2 2 Accumulated miscellaneous updates and bug fixes 04 04 02 2 21 Updated trademarks page in ug000_title fm 06 24 02 3 0 Initial Xilinx release of corporate wide common template set used for User Guides Tutorials Release Notes Manuals and other lengthy multiple chapter documents created by both CMP and ITP See related documents for further information Descriptions for revisions prior to v3 0 have been abbreviated For a full summary of revision changes prior to v3 0 refer to v2 21 template set 06 06 03 4 0 Accumulated miscellaneous updates and bug fixes www xilinx com XST User Guide 1 800 255 7778 XST User Guide www xilinx com 1 800 255 7778 XILINX Preface About This Guide This manual describes Xilinx Synthesis Technology XST support for HDL languages Xilinx devices and constraints for the ISE software The manual also discusses FPGA and CPLD optimization techniques and explains how to run XST from Project Navigator Process window and command line Guide Contents This manual contains the following chapters and appendixes e Chapter 1 Introduction provides a basic description of XST and lists supported architectures e Chapter 2 HDL Coding Technique
227. get better optimization results This filtering depends on the type and size of a macro for example by default 2 to 1 multiplexers are not preserved by the optimization engine You have full control of the processing of inferred macros through synthesis constraints Note Please refer to Chapter 5 Design Constraints for more details on constraints and their utilization There is detailed information about the macro processing in the XST LOG file It contains the following www xilinx com 29 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques e The set of macros and associated signals inferred by XST from the VHDL Verilog source on a block by block basis e The overall statistics of recognized macros Note Some additional macro processing and recognition is done during the Advanced HDL Synthesis step e The number and type of macros preserved by low level optimization The following log sample displays the set of recognized macros on a block by block basis Synthesizing Unit lt timecore gt Related source file is timecore vhd Found finite state machine lt FSM_0 gt for signal lt state gt Found 7 bit subtractor for signal lt fsm_sigl gt Found 7 bit subtractor for signal lt fsm_sig2 gt Found 7 bit register for signal lt min gt Found 4 bit register for signal lt points_tmp gt Summary inferred 1 Finite State Machine s inferred 18 D type flip flop s inferred 10 Adder Subtracter s
228. gic S in std logic vector 1 downto 0 o out std logic end mux architecture archi of mux is begin process a b C d S begin case s is when 00 gt 0 lt a when 01 gt o lt b when 10 gt o lt Cc when others gt o lt d end Case end process end archi Verilog Code Following is the Verilog Code for a 4 to 1 1 bit MUX using a Case statement module mux a b c d S O input a b c d input 1 0 s output o reg o always a or bor c or d or s begin case s 2 b00 o a 2 b01 ob 2 b10 o C default o d endcase end endmodule 88 www xilinx com XST User Guide 1 800 255 7778 Multiplexers lt XILINX 4 to 1 MUX Using Tristate Buffers The following table shows pin definitions for a 4 to 1 1 bit MUX using tristate buffers 10 Pins Description a b c d Data Inputs s 8 0 MUX Selector o Data Output VHDL Code Following is the VHDL code for a 4 to 1 1 bit MUX using tristate buffers library ieee use ieee std_logic_1164 all entity mux is port a S o end mux D O d 2 ab in std_log out std_lo n std_logic ic_vector 3 downto 0 gic architecture archi of mux is begin o lt a o lt o lt c o lt d when s when s when s when s end archi Verilog Code else Z else Z else Z else Z Following is the Verilog Code for a 4 to 1 1
229. gin and end statements and the begin statement must be named with a unique qualifier The following is an example of a generate case statement The generate controls what type of adder is instantiated generate case WIDTH L3 begin casel name adder WIDTH 8 xl a b ci sum case cO case end 23 begin case2 name adder WIDTH 4 x2 a b ci sum case cO case end default begin d case name adder x3 a b ci sum case cO case end endcase endgenerate 310 www xilinx com XST User Guide 1 800 255 7778 Structural Verilog Features 7 XILINX Structural Verilog Features Structural Verilog descriptions assemble several blocks of code and allow the introduction of hierarchy in a design The basic concepts of hardware structure are the module the port and the signal The component is the building or basic block A port is a component I O connector A signal corresponds to a wire between components In Verilog a component is represented by a design module The module declaration provides the external view of the component it describes what can be seen from the outside including the component ports The module body provides an internal view it describes the behavior or the structure of the component The connections between components are specified within component instantiation statements These statements specify an instance of a component occurring within another component or the circuit Each component in
230. gister instances including state bits for the output signal Name clock buffer instances _clockbuffertype like BUFGP or _IBUFG after the output signal Maintain instantiation instance names of black boxes Maintain instantiation instance names of library primitives Name input and output buffers using the form _IBUF or _OBUF after the pad name Name Output instance names of IBUFs using the form instance_name_IBUF Name input instance names to OBUFs using the form instance_name_OBUF www xilinx com 367 1 800 255 7778 7 XILINX Appendix A XST Naming Conventions 368 www xilinx com XST User Guide 1 800 255 7778
231. gned all entity rominfr is port clk in std_logic en in std_logic addr in std_logic_vector 4 downto 0 data out std_logic_vector 3 downto 0 end rominfr architecture syn of rominfr is type rom type is array 31 downto 0 of std logic vector 3 downto 0 constant ROM rom type 0001 9010 0011 0100 01021 0110 0111 1000 1001 TOTO TL011 T T1T00 l1T01 T1110 1117 0001 0010 MOOLI 0100 OLOT OITOT T 0111 I000 TOOT1 10T0 TOTLI T1100 1101 1110 1111 signal rdata std logic vector 3 downto 0 begin rdata lt ROM conv integer addr process clk begin if clk event and clk 1 then if en 1 then data lt rdata end if end if end process end syn XST User Guide www xilinx com 157 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Following is VHDL code for a ROM with registered address library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rominfr is port clk in std logic en in std logic addr in std logic vector 4 downto 0 data out std logic vector 3 downto 0 end rominfr architecture syn of rominfr is type rom type is array 31 downto 0 of std logic vector 3 downto 0 constant ROM rom type 0001 0010 0011 0100 0101 0110 0O111 1000 1001 TOTO UIOII IT100 1101 1110 71111 0001 0010 DOT I 0100 0101 0110 0111 1000 10
232. hat the branches cannot occur in parallel therefore saving latches and priority encoders See Multiplexers in Chapter 2 of this manual and see FULL CASE and PARALLEL CASE in the Constraints Guide for details www xilinx com XST User Guide 1 800 255 7778 General Constraints XST User Guide lt XILINX Define this option globally with the vlgcase command line option of the run command vlgcase full parallel full parallel By default there is no value In Project Navigator specify vlgcase globally with the Case Implementation Style option in the Synthesis Options tab of the Process Properties dialog box Allowed values are Full Parallel and Full Parallel By default the value is blank Full Case Verilog The FULL_CASE directive is used to indicate that all possible selector values have been expressed in a case casex or casez statement The directive prevents XST from creating additional hardware for those conditions not expressed See Multiplexers in Chapter 2 of this manual and FULL_CASE in the Constraints Guide for details Generate RTL Schematic The Generate RTL Schematic rtlview command line option enables XST to generate a netlist file representing an RTL structure of the design This netlist can be viewed by RTL Viewer ECS This option has three possible values yes no and only When the only value is specified XST stops the synthesis process just after the RTL view is generated
233. i bee pad Res os 158 State Machine 160 FSM with 1 Process isis aca ii dit di ide 161 VAD siii A E E EURE RA ERN A A E dale dena A a dis 161 VE A A A ee A 162 FSM withi 2 Processes ui A poe e Re ated 162 O TT 163 Verilog era potete dur med directa an eed hos Riad ieee deus o Ed tod ri ooo PET tosta 164 FSM with 3Processes oooooooooomommrrr hs 165 opp 165 MJ m 166 State Registers io ese coenae s gases dc e a scien v dob ROS os Re a e 167 Next State Equations csse desee rae ree ees reves a Ee eor s 167 Unreachable StateS o ooooooooormrr er n 167 FSM OtltpU lts u bet treten ide delia 167 POM TAPUS evene A E Vade ae etit te Mea dle siis 167 State Encoding Techniques 2 2 0 66 ccc eee ee 168 AO di br REE Desde BOs da Indeed ars dla E E 168 Js T 168 tc Mmmm 168 COMP ACE c M M 168 TOS ci E woe A E pE a AEREE 168 Sequential estyi eaii iiag ie Pater d rede 168 A eda E sah aca ae Geta erik teed ee E lteter dae E EE 168 bo on rere Se ae A ee o e P EUER dete d eee 169 RAM based FSM Synthesis 0 0 0 eens 169 Black Box Support 1 ido AA eH AAA RIA 170 Log File 2k ek RR pardas ehe DR LEES pelada idee piden ies 170 Related Constraints o ooooooorrr ehh 171 sl D PEDE TIT NR 171 Verilog ot oi col yn eas ay ee M LN LI Ue 171 Chapter 3 FPGA Optimization Introduction o boten RP ate d eee petu ed e e ed acid 173 Virtex Specific Synthesis Options
234. icated Carry MUXs based multiplexers For Virtex E MUXFx based multiplexers are generated by using the optimal tree structure of MUXF5 MUXF6 primitives which allows compact implementation of large inferred multiplexers For example XST can implement an 8 1 multiplexer in a single CLB In some cases dedicated carry MUXs are generated these can provide more efficient implementations especially for very large multiplexers For Virtex II Virtex II Pro and Virtex II Pro X XST can implement a 16 1 multiplexer in a single CLB using a MUXF7 primitive and it can implement a 32 1 multiplexer across two CLBs using a MUXF8 To have better control of the implementation of the inferred multiplexer XST offers a way to select the generation of either the MUXF5 MUXF6 or Dedicated Carry MUXs architectures The attribute MUX_STYLE specifies that an inferred multiplexer be implemented on a MUXFx based architecture if the value is MUXE or a Dedicated Carry MUXs based architecture if the value is MUXCY You can apply this attribute to either a signal that defines the multiplexer or the instance name of the multiplexer This attribute can also be global The attribute MUX_EXTRACT with respectively the value no or force can be used to disable or force the inference of the multiplexer Priority Encoder Decoder The if elsif structure described in the Priority Encoders in Chapter 2 is implemented with a 1 of n priority encoder XST u
235. ide 1 800 255 7778 Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode 7 XILINX You can improve the readability of the xst scr file especially if you use many options to run synthesis You can place each option with its value on a separate line respecting the following rules e The first line must contain only the run command without any options e There must be no blank lines in the middle of the command e Each line except the first one must start with a dash For the previous command example the stopwatch xst file should look like the following run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode The goal of this example is to synthesize a hierarchical mixed VHDL Verilog design for a Virtex FPGA using Command Line Mode 1 Create a new directory named vhdl verilog 2 Copy the following files from the ISEexamples watchvhd directory of the ISE installation directory to the newly created vhdl verilog directory stopwatch vhd statmach vhd decode vhd cnt60 vhd smallentr vhd tenths vhd Copy the following file from the ISEexamples watchver directory of the ISE installation directory to the newly created vhdl verilog directory hex2led v To synthesize the design which is now represented by six VHDL files and
236. ierarchy Separator option in the Synthesis Options tab of the Process Properties dialog box in the Project Navigator www xilinx com 221 1 800 255 7778 XILINX 222 Chapter 5 Design Constraints Iostandard Use the IOSTANDARD constraint to assign an I O standard to an I O primitive See TOSTANDARD in the Constraints Guide for details Keep The KEEP constraint is an advanced mapping constraint When a design is mapped some nets may be absorbed into logic blocks When a net is absorbed into a block it can no longer be seen in the physical design database This may happen for example if the components connected to each side of a net are mapped into the same logic block The net may then be absorbed into the block containing the components KEEP prevents this from happening See KEEP in the Constraints Guide for details Library Search Order The Library Search Order 1so command line option is related to the use of mixed language VHDL Verilog projects support It allows you to specify the order in which various library files are used It can be invoked by specifying the file containing the search order in the value field to the right of Library Search option under the Synthesis Options tab in the Process Properties dialog box in Project Navigator or with the lso command line option See the Library Search Order File in Chapter 8 for details LOC The LOC constraint defines where a design element ca
237. ies separated by spaces and enclosed in double quotes vlgincdir Verilog Include Directories Any valid path to directories separated by spaces and enclosed in double quotes Example 1 How to Synthesize VHDL Designs Using Command Line Mode The goal of this example is to synthesize a hierarchical VHDL design for a Virtex FPGA using Command Line Mode The example uses a VHDL design called watchvhd The files for watchvhd can be found in the ISI This design contains 7 entities 358 stopwatch statmach tenths a CORE Generator core decode smallcntr cnt60 hex2led www xilinx com 1 800 255 7778 Eexamples watchvhd directory of the ISE installation directory XST User Guide Example 1 How to Synthesize VHDL Designs Using Command Line Mode 7 XILINX Example 1 1 Create a new directory named vhdl m 2 Copy the following files from the ISEexamples watchvhd directory of the ISE installation directory to the newly created vhd1_m directory stopwatch vhd statmach vhd decode vhd cnt60 vhd smallcntr vhd tenths vhd hex2led vhd To synthesize the design which is now represented by seven VHDL files create a project Please note that starting from the 6 1i release XST supports Mixed VHDL Verilog projects and therefore Xilinx strongly suggests that you use the new project format whether it is a real mixed language project or not In this example we use th
238. if or case statements XST generates a latch to hold the last value To avoid latch creation ensure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the process statements Different statements can be used in a process e Variable and signal assignment e Ifstatement e Case statement e For Loop statement e Function and procedure call The following sections provide examples of each of these statements If Else Statement If else statements use true false conditions to execute statements If the expression evaluates to true the first statement is executed If the expression evaluates to false or x or Z the else statement is executed A block of multiple statements may be executed using begin and end keywords If else statements may be nested Example 6 12 shows the use of an If else statement 270 www xilinx com XST User Guide 1 800 255 7778 lt XILINX Combinatorial Circuits Example 6 12 MUX Description Using If Else Statement library IEEE use IEEE std_logic_1164 all entity mux4 is port a b c d in std logic vector 7 downto 0 sell sel2 in std logic outmux out std logic vector 7 downto 0 end mux4 architecture behavior of mux4 is begin process a b c d sell sel2 begin if sell 1 then if sel2 1 then outmux lt a else outmux b end if else if sel2
239. ilinx Specific Options tab from Synthesis Process Properties dialog box This directive is only available via VHDL attributes or Verilog meta comments or via an XST constraint file Example Figure 3 1 shows how blocks are grouped by use of the INCREMENTAL SYNTHESIS constraint Consider the following LEVA LEVA 1 LEVA 2 my add my sub as one group LEVB my and my or and my sub as another group TOP is considered separately as a single group LEVA incremental synthesis true LEVB incremental synthesis true X9858 Figure 3 1 Grouping through Incremental Synthesis www xilinx com XST User Guide 1 800 255 7778 Incremental Synthesis Flow 7 XILINX RESYNTHESIZE VHDL Flow For VHDL XST is able to automatically recognize what blocks were changed and to resynthesize only changed ones This detection is done at the file level This means that if a VHDL file contains two blocks both blocks are considered modified If these two blocks belong to the same group then there is no impact on the overall synthesis time If the VHDL file contains two blocks that belong to different groups both groups are considered changed and so are resynthesized Xilinx recommends that you only keep different blocks in the a single VHDL file if they belong to the same group Use the RESYNTHESIZE constraint to force resynthesis of the blocks that were not changed Note In the current release XST runs HDL synthesis on the e
240. ilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 5 Design Constraints This chapter describes constraints options and attributes supported for use with XST This chapter contains the following sections Introduction Introduction Setting Global Constraints and Options VHDL Attribute Syntax Verilog Meta Comment Syntax XST Constraint File XCF Old XST Constraint Syntax General Constraints HDL Constraints FPGA Constraints non timing CPLD Constraints non timing Timing Constraints Constraints Summary Implementation Constraints Third Party Constraints Constraints Precedence Constraints are essential to help you meet your design goals or obtain the best implementation of your circuit Constraints are available in XST to control various aspects of the synthesis process itself as well as placement and routing Synthesis algorithms and heuristics have been tuned to automatically provide optimal results in most situations In some cases however synthesis may fail to initially achieve optimal results some of the available constraints allow you to explore different synthesis alternatives to meet your specific needs XST User Guide www xilinx com 209 1 800 255 7778 XILINX Chapter 5 Design Constraints The following mechanisms are available to specify constraints e Options provide global control on most synthesis aspects They can be set either
241. ined using packages Packages contain type and subtype declarations constant definitions function and procedure definitions and component declarations This mechanism provides the ability to change parameters and constants of the design for example constant values function definitions Packages may contain two declarative parts package declaration and body declaration The body declaration includes the description of function bodies declared in the package declaration XST provides full support for packages To use a given package the following lines must be included at the beginning of the VHDL design library lib pack lib pack is the name of the library specified where the package has been compiled work by default use lib pack pack name all pack name is the name of the defined package XST also supports predefined packages these packages are pre compiled and can be included in VHDL designs These packages are intended for use during synthesis but may also used for simulation STANDARD Package The Standard package contains basic types bit bit vector and integer The STANDARD package is included by default IEEE Packages XST User Guide The following IEEE packages are supported e std logic 1164 defines types std logic std ulogic std logic vector std ulogic vector and conversion functions based on these types e numeric bit supports types unsigned signed vectors based on type bit and all
242. infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2003 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes XST User Guide www xilinx com 1 800 255 7778 The following table shows the revision history for this document Version Revision 06 01 00 1 0 Initial Xilinx release 06 15 00 1 1 Accumulated miscellaneous updates and bug fixes 07 26 00 1 2 Accumulated miscellaneous updates and bu
243. ing example shows a selected signal assignment Example 6 5 MUX Description Using Selected Signal Assignment library IEEE use IEEE std_logic_1164 all entity select bhv is generic width integer 8 port a b c d in std logic vector width 1 downto 0 selector in std logic vector 1 downto 0 T out std logic vector width 1 downto 0 end select bhv architecture bhv of select bhv is begin with selector select T lt a when 00 b when 01 c when 10 d when others end bhv Conditional Signal Assignment The following example shows a conditional signal assignment Example 6 6 MUX Description Using Conditional Signal Assignment entity when ent is generic width integer 8 port a b c d in std logic vector width 1 downto 0 selector in std logic vector 1 downto 0 T out std logic vector width 1 downto 0 end when ent architecture bhv of when ent is begin T lt a when selector 00 else b when selector 01 els c when selector 10 els d end bhv Generate Statement Repetitive structures are declared with the generate VHDL statement For this purpose for lin 1 to N generate means that the bit slice description is repeated N times As an example Example 6 7 gives a description of an 8 bit adder by declaring the bit slice structure XST User Guide www xilinx com 267 1 800 255 7778 7 XILINX Chapt
244. input clk input en input we input rst input 4 0 addr input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 3 0 do always posedge clk begin if en optional enable begin if we write enable ram addr lt di if rst optional reset do lt reset_value else do lt ram addr end end end module 154 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Z XILINX Initializing Block RAM VHDL Block RAM initial contents can be specified by initialization of the signal describing the memory array in your VHDL code as in the following example type ram_type is array 0 to 63 of std_logic_vector 19 downto 0 signal RAM ram_type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 X 04002 X 08201 X 00500 X 04001 X 02500 X 00340 X 00241 X 04002 X 08300 X 08201 X 00500 X 08101 X 00602 X 04003 X 0241E X 00301 X 00102 X 02122 X 02021 X 00301 X 00102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X 00303 X 02433 X 00301 X 04004 X 00301 X 00102 X 02137 X 02036 X 00301 X 00102 X 02237 X 04004 X 00304 X 04040 X 02500 X 02500 X 02500 X 0030D X 02341 X 08201 X 0400D i process clk begin if rising_edge clk then if we 1 then RAM conv_integer a lt di end if ra lt a
245. inx com 1 800 255 7778 7 XILINX dob 143 7 XILINX Chapter 2 HDL Coding Techniques The following table shows pin descriptions for a dual port RAM with one enable controlling both ports IO Pins Description clk Positive Edge Clock en Primary Global Enable active High we Primary Synchronous Write Enable active High addra Write Address Primary Read Address addrb Dual Read Address di Primary Data Input doa Primary Output Port dob Dual Output Port VHDL Following is the VHDL code for a dual port RAM with one global enable controlling both ports library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk en we addra addrb di doa dob end raminfr in in in in in in out std logic vector 3 downto 0 0 std logic std logic std logic std logic vector 4 downto 0 std logic vector 4 downto 0 std logic vector 3 downto 0 out std logic vector 3 downto architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addra std logic vector 4 downto 0 signal read addrb std logic vector 4 downto 0 144 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Z XILINX begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM
246. inx com 237 1 800 255 7778 XILINX Chapter 5 Design Constraints See the PERIOD Specifications on CLKDLLs and DCMs subsection of PERIOD in the Constraints Guide A TNM_NET is a property that you normally use in conjunction with an HDL design to tag a specific net All downstream synchronous elements and pads tagged with the TNM NET identifier are considered a group See TNM_NET in the Constraints Guide for details XCF Syntax NET netname TNM_NET predefined_group identifier TIMEGRP TIMEGRP is a basic grouping constraint In addition to naming groups using the TNM identifier you can also define groups in terms of other groups You can create a group that is a combination of existing groups by defining a TIMEGRP constraint You can place TIMEGRP constraints in a constraints file XCF or NCF You can use TIMEGRP attributes to create groups using the following methods Combining multiple groups into one Defining flip flop subgroups by clock sense See TIMEGRP in the Constraints Guide for details XCF Syntax TIMEGRP newgroup existing grpl existing grp2 existing grp3 TIG The TIG constraint causes all paths going through a specific net to be ignored for timing analyses and optimization purposes This constraint can be applied to the name of the signal affected See TIG in the Constraints Guide for details XCF Syntax NET net name TIG Old Timing Constraint Support In th
247. ion globally with the pld_mp command line option of the run command Following is the basic syntax pld mp yes no The default is yes In Project Navigator specify pld mp globally with the Macro Preserve option in the Xilinx Specific Options tab of the Process Properties dialog box No Reduce The No Reduce NOREDUCE constraint prevents minimization of redundant logic terms that are typically included in a design to avoid logic hazards or race conditions This constraint also identifies the output node of a combinatorial feedback loop to ensure correct mapping See NOREDUCE in the Constraints Guide for details www xilinx com XST User Guide 1 800 255 7778 CPLD Constraints non timing Z XILINX XST User Guide WYSIWYG The goal of the WYSIWYG option is to have a netlist as much as possible reflect the user specification That is all the nodes declared in the HDL design are preserved If WYSIWYG mode is enabled yes then XST preserves all the user internal signals nodes creates SOURCE_NODE constraints in the NGC file for all these nodes and skips design optimization collapse factorization only boolean equation minimization is performed Define globally with the wysiwyg command line option of the run command Following is the basic syntax wysiwyg yes no The default is no The constraint can only be defined globally with the WYSIWYG option in the Xilinx Specific Option tab in the Process Properties dialog bo
248. iority processing it is recommended that you use a parallel case Verilog meta comment which ensures parallel evaluation of the sel inputs as in the following Example always ft sel or a or b or c or d synthesis parallel_case For and Repeat Loops When using always blocks repetitive or bit slice structures can also be described using the for statement or the repeat statement The for statement is supported for e Constant bounds e Stop test condition using operators lt lt gt or gt e Next step computation falling in one of the following specifications e var var step var ur step where var is the loop variable and step is a constant value The repeat statement is only supported for constant values The following example shows the use of a For Loop Example 7 4 For Loop Description module countzeros a Count input 7 0 a output 2 0 Count reg 2 0 Count reg 2 0 Count Aux integer i XST User Guide www xilinx com 301 1 800 255 7778 XILINX 302 Chapter 7 Verilog Language Support always a begin Count_Aux 3 b0 for i 0 i lt 8 i i 1 begin if la il Count_Aux Count_Aux 1 end Count Count_Aux end endmodule While Loops When using always blocks use the while statement to execute repetitive procedures A while loop executes other statements until its test expression becomes false It is not executed if the test expression is initiall
249. irtex and Spartan II 3 series See ROM_STYLE in the Constraints Guide for details Shift Register Extraction The Shift Register Extraction SHREG_EXTRACT constraint enables or disables shift register macro inference See SHREG_EXTRACT in the Constraints Guide for details Slice Packing The Slice Packing slice packing option enables the XST internal packer The packer attempts to pack critical LUT to LUT connections within a slice or a CLB This exploits the fast feedback connections among the LUTs in a CLB Define this option globally with the slice packing command line option of the run command Following is the basic syntax slice packing yes no The default is yes In Project Navigator set slice packing globally with the Slice Packing option in the Xilinx Specific Options tab in the Process Properties dialog box Uselowskewlines The USELOWSKEWLINES constraint is a basic routing constraint From a Synthesis point of view it prevents XST from using dedicated clock resources and logic replication based on the value of the MAX FANOUT constraint It specifies the use of low skew routing resources for any net See USELOWSKEWLINES in the Constraints Guide for details XOR Collapsing The XOR Collapsing XOR COLLAPSE constraint controls whether cascaded XORs should be collapsed into a single XOR See XOR COLLAPSE in the Constraints Guide for details Slice Utilization Ratio The Slice Utiliza
250. is port A B in std logic vector 7 downto 0 al bl in std logic SUM out std logic vector 7 downto 0 res out std logic end read cores architecture beh of read cores is component my add port A B in std logic vector 7 downto 0 S out std logic vector 7 downto 0 end component begin res lt al and bl inst my_add port map A gt A B gt B S gt SUM end beh If Read Cores is disabled XST estimates Maximum Combinational Path Delay as 6 639ns critical path goes through a simple AND function and an area of one slice If Read Cores is enabled then XST displays the following messages during Low Level Synthesis Low Level Synthesis Launcher Executing edif2ngd noa my add edn my add ngo INFO NgdBuild Release 6 1i dif2ngd G 21 INFO NgdBuild Copyright c 1995 2003 Xilinx Inc All rights reserved Writing the design to my add ngo Loading core my add for timing and area information for instance inst Estimation of Maximum Combinational Path Delay is 8 281ns with an area of five slices Please note that by default XST reads EDIF NGC cores from the current project directory If the cores are not in the project directory you must use the Cores Search Directories synthesis option to specify which directory the cores are in XST User Guide www xilinx com 197 1 800 255 7778 XILINX Chapter 3 FPGA Optimization
251. istering the read address Summary inferred 1 RAM s Unit raminfr synthesized HDL Synthesis Report Macro Statistics RAMs 1 128 bit single port distributed RAM 1 Related Constraints Related constraints are RAM_EXTRACT RAM_STYLE ROM_EXTRACT and ROM_STYLE 122 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Virtex II Spartan 3 RAM Read Write Modes Block RAM resources available in Virtex II II Pro II Pro X and Spartan 3 offer different read write synchronization modes This section provides coding examples for all three modes that are available write first read first and no change 7 XILINX The following examples describe a simple single port block RAM You can deduce descriptions of dual port block RAMs from these examples Dual port block RAMs can be configured with a different read write mode on each port Inference supports this capability The following table summarizes support for read write modes according to the targeted family and how XST handles it Family Spartan 3TM Virtex IITM Virtex II Pro Virtex II Pro X Inferred i Hode Behavior write first Macro inference and generation read first e Attach adequate no change WRITE_MODE WRITE_MODE_A WRITE MODE B constraints to generated block RAMs in NCF Virtex write first e Macro inference and generation Virtex E e No constraint to attach on Spartan I genera
252. it unsigned up counter with an asynchronous clear and a clock enable module counter C CLR CE Q input C CLR CE output 3 0 Q reg 3 0 tmp always 8 posedge C or posedge CLR begin if CLR tmp 4 b0000 else if CE tmp tmp 1 b1 end assign Q tmp endmodule 4 bit Unsigned Up Down counter with Asynchronous Clear The following table shows pin definitions for a 4 bit unsigned up down counter with an asynchronous clear 10 Pins Description C Positive Edge Clock CLR Asynchronous Clear active High UP DOW up down count mode selector N Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned up down counter with an asynchronous clear library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity counter is port C CLR UP DOWN in std logic Q out std logic vector 3 downto 0 end counter XST User Guide www xilinx com 61 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of counter is signal tmp begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then if UP DOWN 1 then tmp lt tmp 1 else tmp tmp 1 end if end if end process Q lt tmp end archi std logic vector 3 downto 0 Verilog Code Following is the Verilog code for a 4 bit unsigned up down counter with an asynchronous clear module cou
253. ition Unsupported Hierarchical names Unsupported defparam Supported Array of instances Supported Table 7 9 Compiler Directives celldefine endcelldefine Ignored default nettype Supported define Supported undef indef elsif Supported ifdef else endif Supported include Supported resetall Ignored timescale Ignored unconnected_drive Ignored nounconnected drive www xilinx com 1 800 255 7778 XST User Guide Primitives Primitives XST User Guide 7 XILINX Table 7 9 Compiler Directives uselib Unsupported file line Supported XST supports certain gate level primitives The supported syntax is as follows gate_type instance_name output inputs The following example shows Gate Level Primitive Instantiations and Ul out inl in2 bufifl U2 triout data trienable The following table shows which primitives are supported Table 7 10 Primitives and nand nor or xnor xor Supported buf not Supported bufif0 bufif1 notifO notif1 Supported Gate Level Primitives pulldown pullup Unsupported drive strength Ignored delay Ignored array of primitives Supported cmos nmos pmos remos rnmos Unsupported Switch Level TP OS Primitives rtran rtranif0 rtranif1 tran Unsupported tranif0 tranifl User Defined Unsupported Primitives www xilinx com 1 800 255 7778 321 7 XILINX
254. k ibd idum sited idas 250 Example isso is eee Padus na Ere ette pte a 250 Third Party Constraints 0 00 00 251 Constraints Precedence iussus re 254 Chapter 6 VHDL Language Support a C 255 Data Types in VHDL cri Ad 256 Overloaded Data Types sier enets giran tre eerkext he reg en rp ter ee ee a 257 Multi dimensional Array Types sssssessssseeeee 258 Record Types oii e Ete eor EE Hep Y tela ieee reed Vas dr e ard 259 lnital Vales da acid pletri acad e dace pee pic ta 260 Local Reset Y Global Reset serre scra tiesas itda enkan a I 260 Objects mm VHD Lia e E ins 261 Operator Ae a a eiei aed 261 Entity and Architecture Descriptions 0 0 e cece eee eee 262 Entity Declarations ce catia oi ais ni Sark ean te ats is ia 262 Architecture D clarati ti 22s esser se ey Ree A ve ey sek e id Beast 262 Component Instantiation sss eh 262 Recursive Component Instantiation cisci ee 264 Component Configuration siiis lee 265 Generic Parameter Declaration ssss eh 265 Combinatorial Circuits ri cine ere ERR EI ER Ceci Re TR eek era 266 16 www xilinx com XST User Guide 1 800 255 7778 lt XILINX Concurrent Signal Assignments 6 00000 ee 266 Simple Signal Assignment 2 0 066 ekai a i eee eens 266 Selected Signal Assignment 0666s 267 Conditional Signal Assignment 2 0 666 ce rr 267 Generate Statement visos erede edo i
255. kcm II Pro X mux extract yes no force model yes yes no force entity signal Spartan II IIE 3 true false net in model Virtex1M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS mux style auto muxf model yes auto muxf entity signal Spartan IT IIE 3 muxcy net in model muxcy Virtex TI TII Pro II Pro X E noreduce yes no net in model no yes no signal XC9500 true false CoolRunner XPLA3 II IIS optimize yes no model nO yes no VHDL Spartan IT TE 3 _primitives true false instance entity Virtex M TI II Pro in model instance II Pro X E Verilog module instance XST User Guide www xilinx com 241 1 800 255 7778 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options Command Command XCF XCF T E E Constraint Constraint Constraint Line Old XST Old XST Technology Name Syntax Syntax Value Target Constraint Constraint Syntax Syntax Value Target opt level 1 2 model yes L2 entity Spartan IT TE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS opt mode speed area model yes speed area entity Spartan I IIE 3 Virtex II II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS parallel case na na no no value case Spartan I IIE 3 statement Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS priority yes no force model
256. kes an area estimation and if the specified constraint is met XST continues timing optimization trying not to exceed the constraint If the size of the design is more than requested then XST tries to reduce the area first and if the area constraint is met then starts timing optimization In the following example the www xilinx com 187 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization area constraint was specified as 100 and initial estimation shows that in fact it occupies 102 of the selected device XST starts optimization and reaches 95 Low Level Synthesis Found area constraint ratio of 100 5 on block tge actual ratio is 102 Optimizing block lt tge gt to meet ratio 100 5 of 1536 slices Area constraint is met for block lt tge gt final ratio is 95 If the area constraint cannot be met then XST ignores it during timing optimization and runs low level synthesis in order to reach the best frequency In the following example the target area constraint is set to 70 XST was not able to satisfy it and so gives the corresponding warning message Low Level Synthesis Found area constraint ratio of 70 5 on block fpga_hm actual ratio is 64 Optimizing block lt fpga_hm gt to meet ratio 70 5 of 1536 slices WARNING Xst Area constraint could not be met for block lt tge gt final ratio is 94 Note 5 stands for the max margin of th
257. ks Chapter Examples Language Templates RAMs Single Port RAM with Single Port Block RAM Asynchronous Read Single Port RAM with Single Port Distributed RAM False Synchronous Read Single Port RAM with Synchronous Read Read Through Dual Port RAM with Dual Port Block RAM Asynchronous Read Dual Port RAM with False Dual Port Distributed RAM Synchronous Read Dual Port RAM with Synchronous Read Read Through Dual Port Block RAM with Different Clocks Block RAM with Reset Multiple Port RAM Descriptions State Machines FSM with 1 Process Binary State Machine FSM with 2 Processes FSM with 3 Processes One Hot State Machine Black Boxes VHDL None Verilog Signed Unsigned Support When using Verilog or VHDL in XST some macros such as adders or counters can be implemented for signed and unsigned values For Verilog to enable support for signed and unsigned values you must enable Verilog 2001 You can enable it by selecting the Verilog 2001 option under the Synthesis Options tab in the Process Properties dialog box in Project Navigator or by setting the verilog2001 command line option to yes See the VERILOG2001 section in the Constraints Guide for details 38 www xilinx com XST User Guide 1 800 255 7778 Registers lt XILINX For VHDL depending on the operation and type of the operands you must include additional packages in your code For example in order to create an unsigned adder
258. lRunner XPLA3 II IIS iobuf na na yes yes no na Spartan TI TIE 3 Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS 244 www xilinx com 1 800 255 7778 XST User Guide Constraints Summary XILINX Table 5 1 XST Specific Non timing Options Command Command XCF XCF Line Line Constraint Constraint Constraint Ema J Technology Name Suntax Suntax Line Old XST Old XST aac zd et Constraint Constraint 9 Syntax Syntax Value Target iuc na na yes yes no na Spartan I IIE 3 Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS Iso na na yes file_name na Spartan IT TIE 3 Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS pld ce na na yes yes no na XC9500 CoolRunner XPLA3 II IIS pld mp na na yes yes no na XC9500 CoolRunner XPLA3 II IIS pld xp na na yes yes no na XC9500 CoolRunner XPLA3 II IIS read cores na na yes yes no na Spartan I IIE 3 optimize Virtex M TI II Pro II Pro X E sd na na yes directory path na Spartan I IIE 3 Virtex TI II Pro E slice packing na na yes yes no na XC9500 CoolRunner XPLA3 II IIS uc na na yes file name xcf na Spartan TI TIE 3 file name cst Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS verilog2001 na na yes yes no na Spartan
259. lative to other elements Assuming an SRL16 instance of name srl1 to be placed at location R9C0 S0 you may specify the following in your Verilog code synthesis attribute RLOC of srll R9C0 SO0 You may specify the same attribute in the XCF file with the following lines BEGIN MODEL ENTNAME INST srll RLOC R9C0 SO END The binary equivalent of the following line is written to the output NGC file INST srll RLOC R9CO 50 Example 2 The NOREDUCE constraint available with CPLDs prevents the optimization of the boolean equation generating a given signal Assuming a local signal is assigned the arbitrary function below and a NOREDUCE constraint attached to the signal s signal s std logic attribute NOREDUCE boolean attribute NOREDUCE of s signal is true S lt a or a and b You may specify the same attribute in the XCF file with the following lines BEGIN MODEL ENTNAME NET s NOREDUCE NE s KEEP END The following statements are written to the NGC file ET s NOREDUCE s KEEP Example 3 The PWR_MODE constraint available when targeting CPLD families controls the power consumption characteristics of macrocells The following VHDL statement specifies that the function generating signal s should be optimized for low power consumption attribute PWR_MODE string attribute PWR_MODE o
260. le sssssseesese g seat 135 bU 135 VELO P pr 136 Dual Port RAM with Asynchronous Read oooococcccoccccccccrracn eee 136 bac 137 VOTO Sinise eben tpa A A ed eel aged din 138 Dual Port RAM with False Synchronous Read ooooocoocccccccnoorocc 138 bal 139 Verilog Em 139 Dual Port RAM with Synchronous Read Read Through i 140 uppev 140 VOTO Ms 141 Using More than One Clock ied ect ee 141 Dual Port RAM with One Enable Controlling Both PortS o 143 bue ccr 144 Mf c c A Mn 145 Dual Port RAM with Enable on Each Port 0 0 0 0 00 cece cece cence eens 146 bar 147 VELO id r 148 Dual Port Block RAM with Different ClockS 0oooooomomommomomoo 148 buc 149 MGTIO e Ent 150 Multiple Port RAM Descriptions ssssssssssee Ie 150 bu A do dde 151 Jn nnm 152 Block RAM with Reset oo ooooooooorrrrr e c n 152 uper 153 Verilog Template ii iii a Era rr wee dece berti pr redet 154 XST User Guide www xilinx com 1 800 255 7778 13 lt XILINX Initializing Block RAM ios vied needs deen ead oe deed e EI Rag reU was 155 VEDA O A AA cae ae RA anaes a a E 155 Verlo e subbb estu etbsieerid e kae ras daa aaa 155 TIA I N is bebe RR E ERE bee nage nee ERE 156 ROMs Using Block RAM Resources 0 0000 e cr 156 VDE t bes ay Rede heres A A A 156 Verilog invita nr esto d obe ue bg trece read n
261. linx com 1 800 255 7778 XST User Guide Multiplexers XST User Guide 7 XILINX Neither Full nor Parallel module notfull_notparallel sell sel2 il i2 ol input 1 0 sell sel2 input 1 0 i1 i2 output 1 0 o1 reg 1 0 o1 always 8 sell or sel2 begin case 2 b00 sell ol il sel2 ol i2 endcase end endmodule XST automatically determines the characteristics of the Case statements and generates logic using multiplexers priority encoders and latches that best implement the exact behavior of the Case statement This characterization of the Case statements can be guided or modified by using the Case Implementation Style parameter Please refer to the Chapter 5 Design Constraints for more details Accepted values for this parameter are none full parallel and full parallel If none is used the default XST implements the exact behavior of the Case statements e If full is used XST considers that Case statements are complete and avoids latch creation e If parallel is used XST considers that the branches cannot occur in parallel and does not use a priority encoder e If full parallel is used XST considers that Case statements are complete and that the branches cannot occur in parallel therefore saving latches and priority encoders The following table indicates the resources used to synthesize the three examples above using the four Case Implementation Styles The term
262. list of signals the always block is activated for an event in any of the always block s signals as described above Note In combinatorial processes if a signal is not explicitly assigned in all branches of If or Case statements XST generates a latch to hold the last value To avoid latch creation be sure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the process statements XST User Guide www xilinx com 299 1 800 255 7778 lt XILINX 300 Chapter 7 Verilog Language Support Different statements can be used in a process e Variable and signal assignment e Jf else statement e Case statement e For and while loop statement e Function and task call The following sections provide examples of each of these statements If Else Statement If else statements use true false conditions to execute statements If the expression evaluates to true the first statement is executed If the expression evaluates to false or x or z the else statement is executed A block of multiple statements may be executed using begin and end keywords If else statements may be nested The following example shows how a MUX can be described using an If else statement Example 7 2 MUX Description Using If Else Statement module mux4 sel a b c d outmux input 1 0 sel input 1 0 a b c d output 1 0 outmux reg 1 0 outmux always sel or a or b or c or d
263. lkb wea addra addrb dia doa dob input clka input clkb input wea input 4 0 addra input 4 0 addrb input 3 0 dia output 3 0 doa output 3 0 dob reg 3 0 RAM 31 0 reg 4 0 addr_rega reg 4 0 addr regb always posedge clka begin if wea 1 b1 RAM addra lt dia addr rega lt addra end always posedge clkb begin addr regb lt addrb end assign doa RAM addr rega assign dob RAM addr regb endmodule Dual Port Block RAM with Different Clocks The following example shows where the two clocks are used DIA BLOCK RAM WEA ADDRA DOA ADDRB DOB CLKA CLKB X9799 148 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX The following table shows pin descriptions for a dual port RAM with different clocks IO Pins Description clka Positive Edge Clock clkb Positive Edge Clock wea Primary Synchronous Write Enable Active High addra Write Address Primary Read Address addrb Dual Read Address dia Primary Data Input doa Primary Output Port dob Dual Output Port VHDL Following is the VHDL code for a dual port RAM with different clocks library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clka in std_logic clkb in std_logic wea in std_logic addra in std logic vector 4 downto 0 addrb in std logic vector 4 downto 0 dia in st
264. llcntr v e tenths v e hex2led v This design contains seven modules e stopwatch e statmach e tenths a CORE Generator core e decode e cnt60 e smallentr e hex2led XST User Guide www xilinx com 361 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode Example 2 1 Create a new directory named v1g m 2 Copy the watchver design files from the ISEexamples watchver directory of the ISE installation directory to the newly created v1g_m directory To synthesize the design which is now represented by seven Verilog files create a project Please note that starting from the 6 1i release XST supports Mixed VHDL Verilog projects and therefore Xilinx strongly suggest that you use the new project format whether it is a real mixed language project or not In this example we use the new project format To create a project file containing only Verilog files place a list of Verilog files preceded by the keyword verilog in a separate file The order of the files is not important XST can recognize the hierarchy and compile VHDL files in the correct order For our example 1 Openanew file called watchver v 2 Enter the names of the Verilog files into this file in any order and save it verilog work decode v verilog work statmach v verilog work stopwatch v verilog work cnt60 v verilog work smallcntr v verilog work hex2led v 3 To synthesize the design execute the following command from the XST shell or via a
265. lock frequency you may try to disable resource sharing Related Constraint The related constraint is RESOURCE SHARING Example For the following VHDL Verilog example XST gives the following solution B C RES A OPER OPER X8984 XST User Guide www xilinx com 119 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The following table shows pin descriptions for the example 10 pins Description A 7 0 B 7 0 C 7 0 Operands OPER Operation Selector RES 7 0 Data Output VHDL Following is the VHDL example for resource sharing library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity addsub is port A B C in std logic vector 7 downto 0 OPER in std logic RES out std logic vector 7 downto 0 r end addsub architecture archi of addsub is begin RES lt A B when OPER 0 lse A Es end archi Verilog Following is the Verilog code for resource sharing module addsub A B C OPER RES input OPER input 7 0 A input 7 0 B input 7 0 C output 7 0 RES reg 7 0 RES always Q8 A or B or C or OPER begin if OPER 1 b0 RES A B else RES A C end endmodule 120 www xilinx com 1 800 255 7778 XST User Guide RAMS ROMs RAMs ROMs XST User Guide 7 XILINX If you do not want to instantiate RAM primitives to keep your HDL code technol
266. losed in double quotes verilog2001 Verilog 2001 Yes No Table 10 4 HDL Synthesis Options VHDL and Verilog Run Command Options Description Values fsm extract Automatic FSM Extraction Yes No fsm_style FSM Style lut bram fsm encoding Encoding Algorithm Auto One Hot Compact Sequential Gray Johnson User ram extract RAM Extract Yes No ram style RAM Style Auto Distributed Block rom extract ROM Extract Yes No rom style ROM Style Auto Distributed Block mult style Multiplier Style Auto Block Lut Pipe lut mux extract Mux Extraction Yes No Force mux style Mux Style Auto MUXF MUXCY decoder extract Decoder Extraction Yes No priority extract Priority Encoder Extraction Yes No Force shreg extract Shift Register Extraction Yes No shift extract Logical Shift Extraction Yes No xor collapse XOR Collapsing Yes No resource sharing Resource Sharing Yes No www xilinx com 1 800 255 7778 353 XILINX 354 Chapter 10 Command Line Mode Table 10 5 Target Options 9500 9500XL 9500XV XPLA3 CoolRunner II CoolRunner IIS TM Run Command as A Description Values Options iobuf Add I O Buffers Yes No pld mp Macro Preserve Yes No pld xp XOR Preserve Yes No keep hierarchy Keep Hierarchy Yes Soft No pld
267. lt RAM conv integer a end if end process end syn Verilog Following is the Verilog code for a single port RAM with false synchronous read module raminfr clk we a di do input clk input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 3 0 do always posedge clk begin if we ram a lt di do lt ram a end endmodule The following descriptions featuring an additional reset of the RAM output are also only mappable onto Distributed RAM with an additional resetable buffer on the data output as shown in the following figure RST Distributed DO RAM X8978 XST User Guide www xilinx com 131 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The following table shows pin descriptions for a single port RAM with false synchronous read and reset on the output IO Pins Description clk Positive Edge Clock we Synchronous Write Enable active High rst Synchronous Output Reset active High a Read Write Address di Data Input do Data Output VHDL Following is the VHDL code library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std logic rst in std logic a in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array
268. lt mult res pipe 2 lt pipe 1 pipe 3 lt pipe 2 MULT lt pipe 3 end endmodule The following Verilog template shows the multiplication operation placed inside the process block and the pipeline stages are represented as single registers module mult clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a in b in reg 35 0 mult res reg 35 0 pipe 2 pipe 3 always posedge clk begin a_in lt A b_in lt B mult_res lt a_in b_in pipe_2 lt mult_res pipe_3 lt pipe_2 MULT lt pipe_3 end endmodule The following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as shift registers module mult3 clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a_in b_in wire 35 0 mult_res reg 35 0 pipe_regs 3 0 assign mult_res a_in b_in always posedge clk begin a_in lt A b_in lt B pipe regs 3 pipe regs 2 pipe regs 1 pipe regs 0 lt MULT pipe regs 3 pipe regs 2 pipe regs 1 end end module 116 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations 7 XILINX Dividers Dividers are only supported when the divisor is a constant and is a power of 2 In that case the operator is implemented as a shifter otherwise XST issues an error message Log Fil
269. lut4 101 ONESOUT 0 OBUF OBUF 1 gt 0 4 830 ONESOUT 0 OBUF ONESOUT lt O gt Total 6 697ns 5 626ns logic 1 071ns route 84 0 logic 16 0 route Timing constraint Default path analysis Delay 6 214ns Levels of Logic 2 Source xcounter 0 lt 1 gt PAD Destination TENTHSOUT lt 9 gt PAD Data Path xcounter Q 1 to TENTHSOUT lt 9 gt Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name tenths 0 lt 1 gt 10 0 000 0 655 xcounter 0 lt 1 gt LUT4 11 gt 0 1 0 347 0 383 ENTHSOUT lt 0 gt 1 TENTHSOUT 0 OBUF OBUF 1 gt 0 4 830 ENTHSOUT 0 OBUF TENTHSOUT lt O gt Total 6 214ns 5 177ns logic 1 037ns route 83 3 logic 16 7 route CPU 22 28 26 48 s Elapsed 22 00 26 00 s Total memory usage is 73468 kilobytes CPLD Log File The following is an example of an XST log file for CPLD synthesis Release 6 1i xst G 23 Copyright c 1995 2003 Xilinx Inc All rights reserved TABLE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilation 3 HDL Analysis 4 HDL Synthesis 4 1 HDL Synthesis Report 5 Advanced HDL Synthesis 6 Low Level Synthesis 7 Final Report XST User Guide www xilinx com 343 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis m Synthesis Options Summary Source Parameters Input File Name stopwatch prj Input Format mixed Ignore Synthesis Constraint File NO Verilog Search Path Verilog Include Directory
270. lways a or b or c or dor s begin if s 2 b00 o a else if s 2 b01 ob else if s 2 b10 o C end endmodule 90 www xilinx com XST User Guide 1 800 255 7778 lt XILINX Decoders Decoders A decoder is a multiplexer whose inputs are all constant with distinct one hot or one cold coded values Please refer to Multiplexers in this chapter for more details This section shows two examples of 1 of 8 decoders using One Hot and One Cold coded values Log File The XST log file reports the type and size of recognized decoders during the Macro Recognition step Synthesizing Unit lt dec gt Related source file is decoders_1 vhd Found 1 of 8 decoder for signal res Summary inferred 1 Decoder s Unit dec synthesized HDL Synthesis Report Macro Statistics Decoders salt 1 of 8 decoder FH The following table shows pin definitions for a 1 of 8 decoder IO pins Description s 2 0 Selector res Data Output Related Constraints A related constraint is DECODER EXTRACT VHDL One Hot Following is the VHDL code for a 1 of 8 decoder library ieee use ieee std logic 1164 a11 entity dec is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 XST User Guide www xilinx com 91 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of dec is begin res lt 00000001
271. map the logic onto Block RAM and generates a warning message with the reason for the warning If the logic cannot be placed in a single Block RAM primitive XST spreads it over several Block RAMs The following example places two 8 bit adders in a single Block RAM primitive XST User Guide www xilinx com 179 1 800 255 7778 XILINX Chapter 3 FPGA Optimization VHDL library ieee use leee std_logic_1164 all use ieee numeric std all entity logic bram is port Clk rst in std logic A B C D in unsigned 7 downto 0 RES1 RES2 out unsigned 7 downto 0 attribute bram map string attribute bram map of logic bram entity is yes end logic bram architecture beh of logic bram is begin process clk begin if clk event and clk 1 then if rst 1 then RES1 lt 00000000 RES2 lt 00000000 else RES1 lt A B RES2 lt C D end if end if end process end beh VERILOG module vlogic_bram clk rst A B C D RESI ES2 input clk rst input PESO Aj By C D output 7 0 RES1 RES2 reg 12 0 RESI RESZ synthesis attribute bram map of vlogic bram is yes always posedge clk begin if rst RES1 8 b0000000 else RES1 A B end always posedge clk begin if rst RES2 8 b0000000 else RES2 C D end endmodule 180 www xilinx com XST User Guide 1 800 255 7778 Mapping Logic
272. mitations in XST e Verilog Meta Comments e Verilog 2001 Attributes e Language Support Tables e Primitives e Verilog Reserved Keywords e Verilog 2001 Support in XST For detailed information about Verilog design constraints and options refer to Chapter 5 Design Constraints For information about the Verilog attribute syntax see Verilog Meta Comment Syntax in Chapter 5 For information on setting Verilog options in the Process window of Project Navigator refer to General Constraints in Chapter 5 Complex circuits are commonly designed using a top down methodology Various specification levels are required at each stage of the design process As an example at the architectural level a specification may correspond to a block diagram or an Algorithmic State Machine ASM chart A block or ASM stage corresponds to a register transfer block for example register adder counter multiplexer glue logic finite state machine where the connections are N bit wires Use of an HDL language like Verilog allows expressing notations such as ASM charts and circuit diagrams in a computer language Verilog provides both behavioral and structural language structures which allow expressing design objects at high and low levels of abstraction Designing hardware with a language like Verilog allows usage of software concepts such as parallel processing and object oriented programming Verilog has a syntax similar to C and
273. mixed ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 XST User Guide www xilinx com 365 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode 366 www xilinx com XST User Guide 1 800 255 7778 XILINX Appendix A XST Naming Conventions This appendix discusses net naming and instance naming conventions Net Naming Conventions These rules are listed in order of naming priority 1 2 3 Maintain external pin names Keep hierarchy in signal names using underscores as hierarchy designators Maintain output signal names of registers including state bits Use the hierarchical name from the level where the register was inferred Ensure that output signals of clock buffers get _clockbuffertype like BUFGP or _IBUFG follow the clock signal name Maintain input nets to registers and tristates names Maintain names of signals connected to primitives and black boxes Name output net names of IBUFs using the form net name IBUF For example for an IBUF with an output net name of DIN the output IBUF net name is DIN IBUF Name input net names to OBUFs using the form net name OBUEF For example for an OBUF with an input net name of DOUT the input OBUF net name is DOUT_OBUF Instance Naming Conventions These rules are listed in order of naming priority 1 2 e Soy Sho XST User Guide Keep hierarchy in instance names using underscores as hierarchy designators Name re
274. mparators oe sl 8 bit comparator greatequal I Unsigned 8 bit Greater or Equal Comparator The following table shows pin descriptions for a comparator IO pins Description A 7 0 B 7 0 Comparison Operands CMP Comparison Result XST User Guide www xilinx com 109 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Following is the VHDL code for an unsigned 8 bit greater or equal comparator library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity compar is port A B in std logic vector 7 downto 0 CMP out std logic i end compar architecture archi of compar is begin CMP lt 1 when A gt B else 0 end archi Verilog Following is the Verilog code for an unsigned 8 bit greater or equal comparator module compar A B CMP input 7 0 A input 720 By output CMP assign CMP A gt B 1 b1 1 b0 endmodule Multipliers When implementing a multiplier the size of the resulting signal is equal to the sum of 2 operand lengths If you multiply A 8 bit signal by B 4 bit signal then the size of the result must be declared as a 12 bit signal Large Multipliers Using Block Multipliers XST can generate large multipliers using an 18x18 bit block multiplier available in Virtex II II Pro II Pro X For multipliers larger than this XST can generate larger multipliers using multiple 18x18 bit block multipliers Registere
275. n A 7 0 B 7 0 Add Sub Operands OPER Add Sub Select SUM 7 0 Add Sub Result VHDL Following is the VHDL code for an unsigned 8 bit adder subtractor library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity addsub is ES out std logic vector 7 downto 0 port A B in std logic vector 7 downto 0 OPER in std logic e end addsub architecture archi of addsub is begin RES lt A B when OPER 0 else A B end archi Verilog Following is the Verilog code for an unsigned 8 bit adder subtractor module addsub A B OPER RES input OPER input 7 0 A input 7 30 By output 7 0 RES reg 7 0 RES 108 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations 7 XILINX always A or B or OPER begin if OPER 1 b0 RES A B else RES A B end endmodule Comparators lt lt gt gt This section contains a VHDL and Verilog description for an unsigned 8 bit greater or equal comparator Log File The XST log file reports the type and size of recognized comparators during the Macro Recognition step Synthesizing Unit lt compar gt Related source file is comparators l vhd Found 8 bit comparator greatequal for signal n0000 created at line 10 Summary inferred 1 Comparator s Unit compar synthesized HDL Synthesis Report Macro Statistics Co
276. n ifmt ofn e Each option has one value There are no options without a value e The value for a given option can be one of the following Predefined by XST for instance YES or NO Any string for instance a file name or a name of the top level entity There are options like vlgpath and vlgincdir that accept several directories as values The directories must be separated by spaces and enclosed altogether by double quotes as in the following example vlgpath c vlgl c Nvlg2 An integer In the following tables you can find the name of each option and its values e First column the name of the options you can use in command line mode If the option is in bold it must be present in the command line e Second column the option description e Third column the possible values of this option The values in bold are the default values Table 10 1 Global Options Run Command Options Description Values ifn Input Project File Name file name ifmt Input Project Format VHDL Verilog Mixed top Top Level Block Name block name worklib Work Library directory dir_name work where the top level block was compiled lso Library Search Order file_name lso ofn Output File Name file_name ofmt Output File Format NGC XST User Guide www xilinx com 1 800 255 7778 Chapter 10 Command Line Mode Table 10 1 Global Options
277. n Project Navigator Table 5 2 XST Timing Constraints Supported Only by Command Line Process Properties Dialog Box Option glob_opt Process Property ProjNav Global Optimization Goal Values allclocknets Technology Spartan I ITE 3 Virtex TI II Pro inpad to outpad II Pro X E XC9500 offset in before CoolRunner XPLA3 II IIS Offset out after max delay cross clock analysis Cross Clock yes no Spartan TI ITE 3 Virtex M TI II Pro Analysis II Pro X E XC9500 CoolRunner XPLA3 TI IIS write timing constraints Write Timing yes no Spartan I ITE 3 Virtex M II II Pro Constraints II Pro X E XC9500 CoolRunner XPLA3 II IIS The following table shows the timing constraints supported by XST that you can invoke only through the Xilinx Constraint File XCF Table 5 3 XST Timing Constraints Supported Only in XCF Name Value Target Technology period See the See the Spartan TI ITE 3 Constraints Constraints Virtex M TI II Pro Guide for Guide for II Pro X E details details Offset See the See the Spartan TI ITE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E details details timespec See the See the Spartan TI IIE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E details details tsidentifier See the See the Spartan II IIE 3 Constraints Constrain
278. n S assign S assign S deassign posedge DATA IN endmodule A A A S CLOCK ET STATE CLOCK DATA IN block bl 1 0s 1 b0 1 b1 AT E block b2 You cannot assign a bit part select of a signal through an assign deassign statement For example XST rejects the following design module assig input input input input R SE C RST ST EC LOCK Qr DA SE I STATE a ECT CLOCK DATA IN rA IN output reg 0 0 7 S 7 S ATE E always RST ATE block bl if RST begin assign STATI end else begin deassign STATI end E 0 7 8 b0 E O 71 always block b2 begin xf posedge CLOCK SE S else S ECT 0 3 DAT TA IN 0 3 E 4 7 DATA_IN 4 7 B end 305 XST User Guide www Xilinx com 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support Assignment Extension Past 32 Bits If the expression on the left hand side of an assignment is wider than the expression on the right hand side the left hand side is padded to the left according to the following rules e Ifthe right hand expression is signed the left hand expression is padded with the sign bit 0 for positive 1 for negative z for high impedance or x for unknown e Ifthe right h
279. n be placed within an FPGA CPLD See LOC in the Constraints Guide for details Optimization Effort The Optimization Effort OPT LEVEL constraint defines the synthesis optimization effort level See OPT LEVEL in the Constraints Guide for details Optimization Goal The Optimization Goal OPT MODE constraint defines the synthesis optimization strategy Available strategies can be speed or area See OPT_MODE in the Constraints Guide for details Parallel Case Verilog The PARALLEL CASE directive is used to force a case statement to be synthesized as a parallel multiplexer and prevents the case statement from being transformed into a prioritized if elsif cascade See Multiplexers in Chapter 2 of this guide Also see PARALLEL CASE in the Constraints Guide for details RLOC The RLOC constraint is a basic mapping and placement constraint This constraint groups logic elements into discrete sets and allows you to define the location of any element within the set relative to other elements in the set regardless of eventual placement in the overall design See RLOC in the Constraints Guide for details Synthesis Constraint File The Synthesis Constraint File uc command line option creates a synthesis constraints file for XST It replaces the old option called ATTRIBFILE which is obsolete in this release The XCF must have an extension of xcf XST uses this extension to determine if the syntax is related to th
280. nables or disables XST to read EDIF or NGC core files for timing estimation and device utilization control Please refer to Cores Processing in Chapter 3 for more information Define this option globally with the read_cores command line option of the run command Following is the basic syntax read cores yes no optimize The default is yes In Project Navigator set read cores globally with the Read Cores option in the Synthesis Options tab of the Process Properties dialog box Use Carry Chain XST uses carry chain resources to implement certain macros but there are situations where you can get better results by avoiding the use of carry chain The Use Carry Chain USE CARRY CHAIN constraint can deactivate carry chain use for macro generation See USE CARRY CHAIN in the Constraints Guide for details CPLD Constraints non timing This section lists options that only apply to CPLDs not FPGAs XST User Guide Clock Enable The Clock Enable pld ce constraint specifies how sequential logic should be implemented when it contains a clock enable either using the specific device resources available for that or generating equivalent logic This option allows you to specify the way the clock enable function will be implemented if presented in the design Two values are available yes check box is checked the synthesizer implements the use of the Clock Enable signal of the device no check box is not checked th
281. namely the BUFT Clock Buffers This group contains all the clock buffers namely BUFG BUFGP BUFGDLL IO Buffers This group contains all the standard I O buffers except the clock buffer namely IBUF OBUF IOBUF OBUFT IBUF GTL LOGICAL This group contains all the logical cells primitives that are not basic elements namely AND2 OR2 OTHER This group contains all the cells that have not been classified in the previous groups www xilinx com XST User Guide 1 800 255 7778 Log File Analysis 7 XILINX The following section is an example of an XST report for cell usage Cell Usage BELS 70 LUT2 34 LUT3 3 LUT4 34 FlipFlops Latches 9 FDC 8 FDP 1 Clock Buffers 1 BUF GP 1 IO Buffers 24 IBUF 16 OBUF 8 Device Utilization summary Where XST estimates the number of slices gives the number of flip flops IOBs BRAMS etc This report is very close to the one produced by MAP Clock Information A short table gives information about the number of clocks in the design how each clock is buffered and how many loads it has Timing Report At the end of the synthesis XST reports the timing information for the design The report shows the information for all four possible domains of a netlist register to register input Mo to register register to outpad and inpad to outpad The following is an example of a timing report section in the XST log NO
282. nce this is dependent upon a local reset the value changes to 0 whenever the local set reset is activated Objects in VHDL VHDL objects include signals variables and constants Signals can be declared in an architecture declarative part and used anywhere within the architecture Signals can also be declared in a block and used within that block Signals can be assigned by the assignment operator lt Example signal sigl std logic sigl 1 Variables are declared in a process or a subprogram and used within that process or that LZ subprogram Variables can be assigned by the assignment operator Example variable varl std logic vector 7 downto 0 varl 01010011 Constants can be declared in any declarative region and can be used within that region Their value cannot be changed once declared Example signal sigl std_logic_vector 5 downto 0 constant init0 std logic vector 5 downto 0 010111 sigl lt init0 Operators Supported operators are listed in Table 6 7 This section provides an example of how to use each shift operator Example sll Shift Left Logical A 4 downto 0 sll 2 lt A 2 downto 0 amp 00 Example srl Shift Right Logical A 4 downto 0 srl 2 lt 00 amp A 4 downto 2 XST User Guide www xilinx com 261 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support Example sla Shift Left Arithmetic A 4 downto 0 sla 2 lt A 2 do
283. nchronous Read The following descriptions are directly mappable onto distributed RAM only Distributed X8976 The following table shows pin descriptions for a single port RAM with asynchronous read 10 Pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output www xilinx com 1 800 255 7778 XST User Guide RAMS ROMs 7 XILINX VHDL Following is the VHDL code for a single port RAM with asynchronous read library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity raminfr is port Clk in std logic we in std logic a in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if end if end process do lt RAM conv_integer a end syn Verilog Following is the Verilog code for a single port RAM with asynchronous read module raminfr clk we a di do input clk input we input 4 0 a input 350 dis output 3 0 do reg 3 0 ram 31 0 always posedge clk begin if we ram a lt di end assign do ramla endmodule XST User G
284. nd serial out module shift C CLR SI SO input C SI CLR output SO reg 7 0 tmp always G8 posedge C or posedge CLR begin if CLR tmp 8 500000000 else begin tmp tmp 6 0 SI end end assign SO tmp 7 endmodule 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out Note For this example XST does not infer an SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a synchronous set a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In S Synchronous Set active High SO Serial Output 74 www xilinx com XST User Guide 1 800 255 7778 Shift Registers 7 XILINX VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock a synchronous set a serial in and a serial out library ieee use ieee std_logic_1164 all entity shift is port C SI S in std logic SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C S begin if C event and C 1 then if S 1 then tmp lt others gt 1 else tmp lt tmp 6 downto 0 SI end if end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock a synchronous set a se
285. ns XILINX BIT_VECTOR Supported STD ULOGIC VECTOR Supported STD LOGIC VECTOR Supported Composite UNSIGNED Supported SIGNED Supported Record Supported Access Unsupported File Unsupported Table 6 2 Mode In Out Inout Supported Buffer Supported Linkage Unsupported Table 6 3 Declarations Type Supported for enumerated types types with positive range having constant bounds bit vector types and multi dimensional arrays Subtype Supported www xilinx com 1 800 255 7778 285 2 XILINX Table 6 4 Objects Chapter 6 VHDL Language Support Constant Declaration Supported deferred constants are not supported Signal Declaration Supported register or bus type signals are not supported Variable Declaration Supported File Declaration Unsupported Alias Declaration Supported Attribute Declaration Supported for some attributes otherwise skipped see Chapter 5 Design Constraints Component Declaration Supported Table 6 5 Specifications Attribute Only supported for some predefined attributes HIGH LOW LEFT RIGHT RANGE REVERSE RANGE LENGTH POS ASCENDING EVENT LAST VALUE Otherwise ignored Configuration Supported only with the all clause for instances list If no clause is added XST looks for the entity architecture compiled in the defaul
286. ns for use with XST What s New The following is a list of the major changes to XST for release 6 1i HDL Language Support VHDL XST User Guide Support for Assert statements See Assert Statement in Chapter 6 Improved complex data type records array of records etc See Data Types in VHDL in Chapter 6 Improved synthesis time for structural designs See Chapter 6 VHDL Language Support Support of mixed language projects See Chapter 8 Mixed Language Support www xilinx com 21 1 800 255 7778 XILINX 22 Verilog Chapter 1 Introduction Support for generate statements See Generate Statement in Chapter 7 Support for indexed vector part selects See Verilog 2001 Support in XST in Chapter 7 Support for array bit and part selects See Verilog 2001 Support in XST in Chapter 7 Support for module array instantiations See Verilog 2001 Support in XST in Chapter 7 Support of mixed language projects See Chapter 8 Mixed Language Support Macro Inference Counters with modulo See 4 bit Signed Up Counter with Asynchronous Reset and Modulo Maximum in Chapter 2 Multipliers with constant KCM See Multiplication with Constant in Chapter 2 and Multiplier Style in Chapter 5 Block RAMs with Reset See Block RAM with Reset in Chapter 2 RAM initialization via signal declaration mechanism See Initializing Block RAM in Chapter
287. nter C CLR UP DOWN Q input C CLR UP DOWN output 3 0 Q reg 3 0 tmp always 8 posedge C or posedge CLR begin if CLR tmp 4 50000 else if UP DOWN tmp tmp 1 b1 else tmp tmp 1 b1 end assign Q tmp endmodule 4 bit Signed Up Counter with Asynchronous Reset The following table shows pin definitions for a 4 bit signed up counter with an asynchronous reset IO Pins Description C Positive Edge Clock CLR Asynchronous Clear active High Q 3 0 Data Output 62 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Counters VHDL Code Following is the VHDL code for a 4 bit signed up counter with an asynchronous reset library ieee use ieee std logic 1164 a11 use ieee std logic signed all entity counter is port C CLR in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp lt 0000 elsif C event and C 1 then tmp lt tmp 1 end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit signed up counter with an asynchronous reset module counter C CLR Q input C CLR output signed 3 0 Q reg signed 3 0 tmp always posedge C or posedge CLR begin if CLR tmp lt 0000 else tmp lt tmp 1 b1 end assign Q tmp endmodule XST User
288. ntire design However during low level optimization XST re optimizes modified blocks only Verilog Flow For Verilog XST cannot automatically identify when blocks have been modified The RESYNTHESIZE constraint is a workaround for this limitation In this example XST generates three NGC files as shown in the following log file segment Final Report Final Results Top Level Output File Name c users incr_synt new ngc Output File Name c users incr_synt leva ngc Output File Name c users incr_synt levb ngc If you made changes to LEVA_1 block XST automatically resynthesize s the entire group including LEVA LEVA_1 LEVA_2 my_add my_sub as shown in the following log file segment Note f this were a Verilog flow XST would not be able to automatically detect this change and the RESYNTHESIZE constraint would have to be applied to the modified block XST User Guide www xilinx com 185 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization Low Level Synthesis Final Results Incremental synthesis Unit lt my_and gt is up to date Incremental synthesis Unit lt my_and gt is up to date Incremental synthesis Unit lt my_and gt is up to date Incremental synthesis Unit lt my_and gt is up to date Optimizing unit lt my_sub gt Optimizing unit lt my_add gt Optimizing unit lt leva_1 gt Optimizing unit lt leva_2 gt Optimizing unit lt leva gt
289. o HIERARCHY SEPARATOR of the Constraints Guide for details on its usage IMPORTANT If all or part of a specified timing constraint is not supported by XST then XST generates a warning about this and ignores the unsupported timing constraint or unsupported part of it in the Timing Optimization step If the Write Timing Constraints option is set to yes XST propagates the entire constraint to the final netlist even if it was ignored at the Timing Optimization step 236 www xilinx com XST User Guide 1 800 255 7778 Timing Constraints Z XILINX The following timing constraints are supported in the XST Constraints File XCF e Period PERIOD is a basic timing constraint and synthesis constraint A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group The group may contain paths that pass between clock domains if the clocks are defined as a function of one or the other See PERIOD in the Constraints Guide for details XCF Syntax NET netname PERIOD value HIGH LOW value e Offset OFFSFT is a basic timing constraint It specifies the timing relationship between an external clock and its associated data in or data out pin OFFSET is used only for pad related signals and cannot be used to extend the arrival time specification method to the internal signals in a design OFFSET allows you to Calculate whether a setup time i
290. o CPLD synthesis that can only be set from the Process Properties dialog box in Project Navigator XST User Guide Families Five families are supported by XST for CPLD synthesis CoolRunner XPLA3 CoolRunner II IIS XC9500 XC9500XL XC9500XV www xilinx com 203 1 800 255 7778 7 XILINX Chapter 4 CPLD Optimization The synthesis for the CoolRunner XC9500XL and XC9500XV families includes clock enable processing you can allow or invalidate the clock enable signal when invalidating it is replaced by equivalent logic Also the selection of the macros which use the clock enable counters for instance depends on the family type A counter with clock enable is accepted for the CoolRunner XC9500XL and XC9500XV families but rejected replaced by equivalent logic for XC9500 devices List of Options Following is a list of CPLD synthesis options that you can set from the Process Properties dialog box in Project Navigator For details about each option refer to CPLD Constraints non timing in Chapter 5 e Keep Hierarchy e Macro Preserve e XOR Preserve e Equivalent Register Removal e Clock Enable e WYSIWYG e No Reduce Implementation Details for Macro Generation 204 XST processes the following macros e adders e subtractors e add sub e multipliers e comparators e multiplexers e counters e logical shifters e registers flip flops and latches e XORs Th
291. o lt RAM conv integer a dpo lt RAM conv integer dpra end syn XST User Guide www xilinx com 137 1 800 255 7778 7 XILINX 138 Verilog Chapter 2 HDL Coding Techniques Following is the Verilog code for a dual port RAM with asynchronous read module raminfr clk we a input clk input we input 4 0 a input 4 0 dpra input 3 0 di output 3 0 spo output 3 0 dpo reg 3 0 ram 31 0 always posedge clk begin if we ram a lt di end assign spo ram a assign dpo ram dpra endmodule Dual Port RAM with False Synchronous Read The following description is mapped onto Distributed RAM with additional registers on the data outputs Please note that this template does not describe dual port block RAM Distributed V N SPO DPO X8981 The following table shows pin descriptions for a dual port RAM with false synchronous read IO Pins Description clk Positive Edge Clock we Synchronous Write Enable active High a Write Address Primary Read Address dpra Dual Read Address di Data Input spo Primary Output Port dpo Dual Output Port www xilinx com 1 800 255 7778 XST User Guide RAMS ROMs Z XILINX VHDL Following is the VHDL code for a dual port RAM with false synchronous read library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port elk in std logic we
292. o create mixed language projects and what the current limitations are The following are key features of mixed language support Mixing of VHDL and Verilog is restricted to design unit cell instantiation only A VHDL design can instantiate a Verilog module and a Verilog design can instantiate a VHDL entity Any other kind of mixing between VHDL and Verilog is not supported In a VHDL design a restricted subset of VHDL types generics and ports is allowed on the boundary to a Verilog module Similarly in a Verilog design a restricted subset of Verilog types parameters and ports is allowed on the boundary to a VHDL entity or configuration XST binds VHDL design units to a Verilog module during the Elaboration step Component instantiation based on default binding is used for binding Verilog modules to a VHDL design unit Note Configuration specification direct instantiation and component configurations are not supported for a Verilog module instantiation in VHDL In supporting mixed projects VHDL and Verilog project files are unified VHDL and Verilog libraries are logically unified Specification of work directory for compilation xsthdpdir previously available only for VHDL is also available for Verilog The xhdp ini mechanism for mapping a logical library name to a physical directory name on the host file system previously available only for VHDL is also available for Verilog www xilinx com 325 1 800 255 7778 7
293. o specify the HDL synthesis options from Project Navigator 1 Selecta source file from the Source file window 2 Right click on Synthesize XST in the Process window 3 Select Properties 4 When the Process Properties dialog box displays click the Synthesis Options tab www xilinx com XST User Guide 1 800 255 7778 Setting Global Constraints and Options 7 XILINX Depending on the device family you have selected FPGA or CPLD one of two dialog boxes displays Synthesis Options HDL Options Xin Specific Options Property Name Global Optimization Goal Generate RTL Schematic Read Cores Cores Search Directories Write Timing Constraints Cross Clock Analysis Hierarchy Separator Bus Delimiter Slice Utilization Ratio Maintain Pest Verlog 2001 BE Verilog Include Directories see Custom Compile File List Other XST Command Line Options OK Cancel Loses Help Figure 5 1 Synthesis Options FPGA Synthesis Options HDL Options Xilinx Specific Options Property Name Value Optimization Goal Speed Optimization Effort ON RID Dey Normal Use Synthesis Constraints File Vv Library Search Order Keep Hierarchy Yes Generate RTL Schematic Yes Hierarchy Separator Ses x Bus Delimiter o Case Maintain Work Directory Lust HDL INI File Verilog 2001 Vv Verilog Include Directories Cancel Default Help Figur
294. ock RAM DI CLK EVA X9478 The following table shows pin descriptions for a single port RAM with enable IO pins Description clk Positive Edge Clock en Global Enable we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output VHDL Following is the VHDL code for a single port block RAM with enable library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity raminfr is port el a en we a di do end raminfr XST User Guide in in in s dmn in std logic std logic std logic std logic vector 4 downto 0 std logic vector 3 downto 0 out std logic vector 3 downto 0 www xilinx com 135 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_a std_logic_vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer a lt di end if read_a lt a end if end if end process do lt RAM conv_integer read_a end syn Verilog Following is the Verilog code for a single port block RAM with enable module raminfr clk en we a di do input clk input en input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 4 0 read a
295. od D Re 313 Verilog Limitations MAS ici de Ea do oae 313 Case Sensitivity actos i Sage a A aer re ii du p ER E eI ease uas 313 Blocking and Nonblocking Assignments 0 0 000 00000 e rnr 314 Integer Handling soi daa EE 315 Verilog Meta Comments occ ccc 560 ces isdc tio iudsd bud E RYda ib ER en den 315 Merilop 2001 Attributes dd EE deren hl ERR ttt y t ace tid opt 316 OyDt xX id 5 acer e pi GER dae EOD ach ape dd enar det de ae o POR AR Re Pee So es c 317 Example M P 317 Example 2 ep cette ee dese s Vt os d o ta e eee ted eal esa a 317 Example g sese e aer bee dea ob E dor etaed 317 Example Arere edad on deti der decide ee debe edat 317 LAIMA LIONS 4 ned rca oud oe ect nd td Ce tor eod 317 Language Support Tables suas d ERE REICH E ee e eem c q 317 Primilives score RED Poft WI e bpTOD DeL DOeLPE qe eta 321 Verilog Reserved Keywords iiu eda Cer d ei as q rasa 322 Verilog 2001 Support in XST 0 02 eee eee 323 Chapter 8 Mixed Language Support Introduction serein be Sew A dean aed d 325 Mixed Language Project File oe eek eek yen er REV Re d ORC Rd ett 326 VHDL Verilog Boundary Rules sss 326 Instantiating a Verilog Module ina VHDL Design ssseseeeeee 326 Instantiating a VHDL Design Unit in a Verilog DesigN oooooorooommmo 327 Port Mapping eec dora rediere eadera e Endo eu A Mrd ko dde RP dara 328 Generics Support in Mixed Language Projects 0
296. odel yes yes no soft entity Spartan I IIE 3 hierarchy true false VirtexTM T II Pro soft II Pro X XC9500 CoolRunner XPLA3 II IIS 240 www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX Table 5 1 XST Specific Non timing Options Command Command XCF XCF T E p Constraint Constraint Constraint Line Old XST Old XST Technology Name Syntax Syntax Value Target Constraint Constraint Syntax Syntax Value Target loc string net in model no string signal Spartan M TI TIE 3 inst in model primary IO Virtex II II Pro instance II Pro X E XC9500 CoolRunner XPLA3 II IIS lut map yes no model no yes no entity Spartan I IIE 3 true false architecture Virtex M TI II Pro II Pro X E max fanout integer model yes integer entity signal Spartan II TIE 3 net in model Virtex TI TII Pro II Pro X E move_first yes no model yes yes no entity Spartan I IIE 3 _stage true false primary clock primary clock Virtex II II Pro signal signal II Pro X E net in model move_last yes no model yes yes no entity Spartan IT IIE 3 _stage true false primary clock primary clock Virtex TI II Pro signal signal II Pro X E net in model mult_style auto block model yes auto block entity signal Spartan 3 lut pipe_lut net in model lut pipe_lut Virtex M T TI Pro
297. of State2 is yes synthesis attribute fsm encoding of State2 is gray For a full list of constraints refer to Chapter 5 Design Constraints Verilog 2001 Attributes XST supports Verilog 2001 attribute statements Attributes are comments that are used to pass specific information to software tools such as synthesis tools Verilog 2001 attributes can be specified anywhere for operators or signals within module declarations and instantiations and signal declarations Note Other attribute declarations may be supported by the compiler but are ignored by XST Attributes can be used to e Set constraints on individual objects for example module instance net e Set FULL CASE PARALLEL CASE and FULLPARALLEL_CASE synthesis directives 316 www xilinx com XST User Guide 1 800 255 7778 Language Support Tables Z XILINX Syntax Attributes must be bounded by the characters and and are written using the following syntax attribute name attribute value Where e The attribute must precede the signal module or instance declaration it refers to e The attribute value must be a string no integer or scalar values are allowed e Theattribute value must be between quotes e The default value is 1 attribute name is the same as attribute name 1 Example 1 clock_buffer IBUFG input CLK Example 2 INIT 0000 reg 3 0 d_out Example 3 always current state or reset begin p
298. of latch is begin process G D begin if G 1 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a latch with a positive gate module latch G D 0 input G D output 0 reg Q always G or D begin if G Q D end endmodule Latch with Positive Gate and Asynchronous Clear The following figure shows a latch with a positive gate and an asynchronous clear LDC o o O X4070 48 www Xilinx com XST User Guide 1 800 255 7778 Registers Z XILINX The following table shows pin definitions for a latch with a positive gate and an asynchronous clear IO Pins Description D Data Input G Positive Gate CLR Asynchronous Clear active High Q Data Output VHDL Code Following is the equivalent VHDL code for a latch with a positive gate and an asynchronous clear library ieee use ieee std_logic_1164 all entity latch is port G D CLR in std_logic Q out std logic end latch architecture archi of latch is begin process CLR D G begin if CLR 1 then Q lt 0 elsif G 1 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a latch with a positive gate and an asynchronous clear module latch G D CLR Q input G D CLR output Q reg Q always G or D or CLR begin if CLR Q 1 b0 else if G Q D end
299. off Vertical ellipsis Repetitive material that has been omitted IOB IOB n QOUT CLKIN Name Name N Horizontal ellipsis Repetitive material that has allow block block_name Online Document XST User Guide been omitted loci loc2 locn The following conventions are used in this document Convention Meaning or Use Example Cross reference link to a See the section Additional location in the current file or Resources for details Blue text io in another file in the current Refer to Title Formats in document Chapter 1 for details Cross reference link to a See Figure 2 5 in the Virtex II Red text location in another document Platform FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files www xilinx com 1 800 255 7778 7 XILINX Preface About This Guide 8 www xilinx com XST User Guide 1 800 255 7778 Table of Contents Preface About This Guide Guide Contents LT uses eee e e 5 Additional Resources sese RR e eeneens 6 Conventlons vd a e RR eon 6 Typographical setes cree rece A ee Ueber eek aaa prs 6 Online Doc ies tr oet ete Re does Ca n e db Soda oe dg dt 7 Chapter 1 Introduction Architecture SOPA ti eiae ra erc e RR ace M eoe Oa Ro E a cons 21 MST PlOW uti id is it n etuer e 21 Wh
300. ogy independent XST offers an automatic RAM recognition capability XST can infer distributed as well as Block RAM It covers the following characteristics offered by these RAM types Synchronous write Write enable RAM enable Asynchronous or synchronous read Reset of the data output latches Data output reset Single dual or multiple port read Single port write The type of inferred RAM depends on its description RAM descriptions with an asynchronous read generate a distributed RAM macro RAM descriptions with a synchronous read generate a Block RAM macro In some cases a Block RAM macro can actually be implemented with Distributed RAM The decision on the actual RAM implementation is done by the macro generator Following is the list of VHDL Verilog templates that are described below Virtex II RAM Read Write modes Read First Mode Write First Mode No Change Mode Single Port RAM with Asynchronous Read Single Port RAM with False Synchronous Read Single Port RAM with Synchronous Read Read Through Single Port RAM with Enable Dual Port RAM with Asynchronous Read Dual Port RAM with False Synchronous Read Dual Port RAM with Synchronous Read Read Through Dual Port RAM with One Enable Controlling Both Ports Dual Port RAM with Enable Controlling Each Port Dual Port RAM with Different Clocks Multiple Port RAM Descriptions Block RAM with Reset Initializing Block RAM ROMs Using Block RAM Resources If
301. ollowing e Combinatorial process VHDL and always block Verilog e Concurrent assignment Log File The XST log reports the type and size of recognized tristates during the Macro Recognition step Synthesizing Unit lt three_st gt Related source file is tristates l vhd Found 1 bit tristate buffer for signal o Summary inferred 1 Tristate s Unit three st synthesized HDL Synthesis Report Macro Statistics Tristates LT 1 bit tristate buffer 2 L Related Constraints There are no related constraints available XST User Guide www xilinx com 51 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Description Using Combinatorial Process and Always Block The following figure shows a tristate element using a combinatorial process and always block BUFT X9543 The following table shows pin definitions for a tristate element using a combinatorial process and always block IO Pins Description I Data Input T Output Enable active Low Data Output VHDL Code Following is VHDL code for a tristate element using a combinatorial process and always block library ieee use ieee std logic 1164 a11 entity three st is port T in std logic I in std logic O out std logic end three st architecture archi of three st is begin process I T begin if I 0 then O lt I else O lt Z end if end process end archi
302. ons register to register inpad to register register to outpad and inpad to outpad of the design depending on the global optimization goal Please refer to Incremental Synthesis Flow in Chapter 3 for a detailed description of supported timing constraints The Global Optimization Goal glob opt command line option selects the global optimization goal Note You cannot specify a value for Global Optimization Goal glob opt XST optimizes the entire design for the best performance The following constraints can be applied by using the Global Optimization Goal option ALLCLOCKNETS optimizes the period of the entire design OFFSET IN BEFORE optimizes the maximum delay from input pad to clock either for a specific clock or for an entire design OFFSET OUT AFTER optimizes the maximum delay from clock to output pad either for a specific clock or for an entire design INPAD TO OUTPAD optimizes the maximum delay from input pad to output pad throughout an entire design MAX_DELAY incorporates all previously mentioned constraints These constraints affect the entire design and only apply if no timing constraints are specified via the constraint file Define this option globally with the g1ob opt command line option of the run command Following is the basic syntax glob opt allclocknets offset in before offset out after inpad to outpad max delay www xilinx com 235 1 800 255 7778 7 XILINX Chapter 5 Design C
303. onstraints You can specify glob_opt globally with the Global Optimization Goal option in the Synthesis Options tab of the Process Properties dialog box within the Project Navigator Domain Definitions The possible domains are illustrated in the following schematic e ALLCLOCKNETS register to register identifies by default all paths from register to register on the same clock for all clocks in a design To take into account inter clock domain delays the command line switch cross clock analysis must be set to yes e OFFSET IN BEFORE inpad to register identifies all paths from all primary input ports to either all sequential elements or the sequential elements driven by the given clock signal name e OFFSET OUT AFTER register to outpad is similar to the previous constraint but sets the constraint from the sequential elements to all primary output ports e INPAD TO OUTPAD inpad to outpad sets a maximum combinational path constraint e MAX DELAY identifies all paths defined by the following timing constraints ALLCLOCKNETS OFFSET IN BEFORE OFFSET OUT AFTER INPAD TO OUTPAD Offset in Before gt AllClockNets Period gt Offset out After Inpad to Outpad TM X8991 XCF Timing Constraint Support IMPORTANT If you specify timing constraints in the XCF file Xilinx strongly suggests that you use character as a hierarchy separator instead of Please refer t
304. onto Block RAM Z XILINX LOG HDL Synthesis Synthesizing Unit logic bram Related source file is C Users DOC Granite HDL Coding Techniques ise bram map 1l vhd Found 8 bit register for signal lt RES1 gt Found 8 bit register for signal lt RES2 gt Found 8 bit adder for signal n0002 created at line 25 Found 8 bit adder for signal n0003 created at line 26 Summary inferred 16 D type flip flop s inferred 2 Adder Subtracter s Unit logic bram synthesized Advanced HDL Synthesis Entity logic bram mapped on BRAM Device utilization summary Selected Device 2v40cs144 6 Number of bonded IOBs 17 out of 88 19 Number of BRAMs 1 out of 2 50 Number of GCLKs 1 out of 16 6 In the following example an asynchronous reset is used instead of a synchronous one and so the logic is not mapped onto Block RAM VHDL library ieee use ieee std logic 1164 a1l use ieee numeric std all entity no logic bram is port clk rst in std logro A B C D in unsigned 7 downto 0 RES1 RES2 out unsigned 7 downto 0 attribute bram map string attribute bram map of no logic bram entity is yes end no logic bram XST User Guide www xilinx com 181 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization architecture beh of no_logic_bram is begin process clk rst begin if rst 1 then RES1 lt 000000
305. optimization on the complete design The output of this process is an NGC file www xilinx com 173 1 800 255 7778 7 XILINX This chapter describes the following Chapter 3 FPGA Optimization Constraints that can be applied to tune the synthesis and optimization process Macro generation Information in the log file Timing model used during the synthesis and optimization process Constraints available for timing driven synthesis Information on the generated NGC file Information on support for primitives Virtex Specific Synthesis Options XST supports a set of options that allows the tuning of the synthesis process according to the user constraints This section lists the options that relate to the FPGA specific optimization of the synthesis process For details about each option see FPGA Constraints non timing in Chapter 5 174 Following is a list of FPGA options BUFGCE Buffer Type Clock Buffer Type Decoder Extraction FSM Style Global Optimization Goal Incremental Synthesis Keep Hierarchy Logical Shifter Extraction Map Logic on BRAM Max Fanout Move First Stage Move Last Stage Multiplier Style Mux Style Number of Clock Buffers Optimize Instantiated Primitives Pack I O Registers into IOBs Priority Encoder Extraction RAM Style Register Balancing Register Duplication Resynthesize Shift Register Extraction Signal Encoding www xilinx com 1 800 255 7778 XST User Guide
306. ormation XST User Guide www xilinx com 169 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques If it cannot implement a state machine on block RAM XST e generates a warning message with the reason for the warning in the Advanced HDL Synthesis Step of the log file e automatically implements the state machine using LUTs For example if ESM has a asynchronous reset it cannot be implemented using block RAM In this case XST informs the user Advanced HDL Synthesis i WARNING Xst Unable to fit FSM FSM 0 in BRAM reset is asynchronous Selecting encoding for FSM 0 Optimizing FSM FSM 0 on signal current state with one hot encoding Black Box Support 170 Log File Your design may contain EDIF or NGC files generated by synthesis tools schematic editors or any other design entry mechanism These modules must be instantiated in your code to be connected to the rest of your design You can do this in XST by using black box instantiation in the VHDL Verilog code The netlist is propagated to the final top level netlist without being processed by XST Moreover XST allows you to attach specific constraints to these black box instantiations which are passed to the NGC file In addition you may have a design block for which you have an RTL model as well as your own implementation of this block in the form of an EDIF netlist The RTL model is only valid for simulation purposes
307. ot attached to the MUXF5 Then XST processes this block as a user hierarchical block If the name of the user black box is the same as that of a Virtex primitive XST renames it to a unique name and then generates a warning message with the reason for the warning To simplify the instantiation process XST comes with VHDL and Verilog Virtex libraries These libraries contain the complete set of Virtex primitives declarations with a BOX TYPE constraint attached to each component If you use e VHDL You must declare library unisim with its package vcomponents in your source code library unisim use unisim vcomponents all The source code of this package can be found in the vhdlNsrcNunisims vcomp vhd file of the XST installation e Verilog Starting in release 6 1i the unisim library is already precompiled and XST automatically links it with your design www xilinx com XST User Guide 1 800 255 7778 Virtex Primitive Support Z XILINX Some primitives like LUT1 allow you to use an INIT during instantiation There are two ways to pass an INIT to the final netlist e Attach an INIT attribute to the instantiated primitive e Pass the INIT via the generics mechanism in VHDL or the parameters mechanism in Verilog Xilinx recommends this method as it allows you to use the same code for synthesis and simulation VHDL Following is the VHDL code for passing an INIT value via the INIT constraint library ie
308. output path timing See IOB in the Constraints Guide for details Priority Encoder Extraction The Priority Encoder Extraction PRIORITY EXTRACT constraint enables or disables priority encoder macro inference See PRIORITY EXTRACT in the Constraints Guide for details RAM Extraction The RAM Extraction RAM EXTRACT constraint enables or disables RAM macro inference See RAM EXTRACT in the Constraints Guide for details RAM Style The RAM Style RAM STYLE constraint controls whether the macrogenerator implements the inferred RAM macros as block or distributed RAM See RAM STYLE in the Constraints Guide for details Register Balancing The Register Balancing REGISTER BALANCING constraint enables flip flop retiming See REGISTER BALANCINC in the Constraints Guide for details Register Duplication The Register Duplication REGISTER DUPLICATION constraint enables or disables register replication See REGISTER DUPLICATION in the Constraints Guide for details ROM Extraction The ROM Extraction ROM EXTRACT constraint enables or disables ROM macro inference See ROM EXTRACT in the Constraints Guide for details www xilinx com 229 1 800 255 7778 XILINX 230 Chapter 5 Design Constraints ROM Style ROM Style ROM_STYLE controls the way the macrogenerator implements the inferred ROM macros The implementation style can be manually forced to use block ROM or distributed ROM resources available in the V
309. overall frequency of your design The effect of pipelining is similar to flip flop retiming which is described in Flip Flop Retiming in Chapter 3 To insert pipeline stages describe the necessary registers in your HDL code and place them after any multipliers then set the MULT STYLE constraint to pipe lut When XST detects valid registers for pipelining and MULT STYLE is set to pipe lut XST uses the maximum number of available registers to reach the maximum multiplier speed XST automatically calculates the maximum number of registers for each multiplier to get the best frequency If you have not specified sufficient register stages and MULT STYLE is coded directly on a signal XST guides you via the HDL Advisor to specify the optimum number of register stages XST does this during the Advanced HDL Synthesis step If the number of registers placed after the multiplier exceeds the maximum required and shift register extraction is activated then XST implements the unused stages as shift registers Limitations e XST cannot pipeline hardware Multipliers e XST cannot pipeline multipliers if registers contain asynch synch set reset signals www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations 7 XILINX Log File HDL Synthesis Synthesizing Unit my mult Related source file is pipe mult l vhd Found 36 bit register for signal MULT Found 18 bit register for signal a in Found
310. port X A O S1 NANDB Y B A A NANDA Y S3 NANDD Y Os B B A NANDC Y y Q B 1c X8952 Figure 7 1 Synthesized Top Level Netlist The structural features of Verilog HDL also allow you to design circuits by instantiating pre defined primitives such as gates registers and Xilinx specific primitives like CLKDLL and BUFGs These primitives are other than those included in the Verilog language These pre defined primitives are supplied with the XST Verilog libraries unisim comp v Example 7 12 Structural Instantiation of Register and BUFG module foo sysclk in reset out input sysclk in reset output out reg out wire sysclk out FDC register sysclk reset in out position based referencing BUFG clk O sysclk out I sysclk name based referencing endmodule The unisim comp v library file supplied with XST includes the definitions for FDC and BUFG module FDC C CLR D Q input C input CLR input D output 0 endmodule synthesis attribute BOX TYPE of FDC is BLACK BOX module BUFG O I output O0 input I endmodule synthesis attribute BOX TYPE of BUFG is BLACK BOX 312 www xilinx com XST User Guide 1 800 255 7778 Parameters Z XILINX Parameters Verilog modules support defining constants known as parameters which can be passed to module instances to define circuits of arbitrary widths Parameters form the basis of creating an
311. pported no unconstrained ports Entity Declarative Part Supported Entity Statement Part Unsupported Architecture Declarative Part Supported Architecture Bodies Architecture Statement Part Supported Block Configuration Supported Configuration Declarations Component Configuration Supported Functions Supported Subprograms Procedures Supported www xilinx com 1 800 255 7778 283 XILINX 284 Chapter 6 VHDL Language Support Table 6 1 Design Entities and Configurations STANDARD Type TIME is not supported TEXTIO Unsupported STD_LOGIC_1164 Supported STD_LOGIC_ARITH Supported STD_LOGIC_SIGNED Supported STD_LOGIC_UNSIGNED Supported STD_LOGIC_MISC Supported Packages NUMERIC_BIT Supported NUMERIC_EXTRA Supported NUMERIC_SIGNED Supported NUMERIC_UNSIGNED Supported NUMERIC_STD Supported MATH_REAL Supported ASYL ARITH Supported ASYL SL_ARITH Supported ASYL PKG_RTL Supported ASYL ASYL1164 Supported BOOLEAN BIT Supported STD ULOGIC Supported Enumeration Types STD LOGIC XO1 UX01 XO1Z UX01Z Supported Character Supported INTEGER Supported Integer Types POSITIVE Supported NATURAL Supported TIME Ignored REAL Supported only in Physical Types functions for constant calculations www xilinx com 1 800 255 7778 XST User Guide VHDL Language Support XST User Guide Table 6 1 Design Entities and Configuratio
312. process C ALOAD D begin if ALOAD 1 then tmp lt D elsif C event and C 1 then tmp lt tmp 1 end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with an asynchronous load from the primary input module counter C ALOAD D 0 input C ALOAD input 3 0 D output 3 0 Q reg 3 0 tmp always 8 posedge C or posedge ALOAD begin if ALOAD tmp D else tmp tmp 1 b1 end assign Q tmp endmodule 4 bit Unsigned Up Counter with Synchronous Load with a Constant The following table shows pin definitions for a 4 bit unsigned up counter with a synchronous load with a constant IO Pins Description C Positive Edge Clock SLOAD Synchronous Load active High Q 3 0 Data Output 58 www xilinx com XST User Guide 1 800 255 7778 lt XILINX Counters VHDL Code Following is the VHDL code for a 4 bit unsigned up counter with a synchronous load with a constant library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C SLOAD in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C begin if C event and C 1 then if SLOAD 1 then tmp 1010 else tmp lt tmp 1 end if end if end process Q tmp end archi
313. process clk begin if clk event and clk 1 then a in lt A b in lt B pipe 1 lt mult res pipe 2 pipe 1 pipe 3 lt pipe 2 MULT lt pipe 3 end if end process end beh The following VHDL template shows the multiplication operation placed inside the process block and the pipeline stages represented as single registers library ieee use ieee std logic 1164 a1 use ieee numeric std all entity mult is generic A port size integer 18 B port size integer 18 port Clk in std logic A in unsigned A port size 1 downto 0 B in unsigned B port size 1 downto 0 MULT out unsigned A port size B port size 1 downto 0 end mult architecture beh of mult is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 signal pipe 2 pipe 3 unsigned A port size B port size 1 downto 0 begin process clk begin if clk event and clk 1 then a in lt A b in lt B mult res lt a in b in pipe 2 lt mult res pipe 3 lt pipe 2 MULT lt pipe 3 end if end process end beh 114 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations lt XILINX The following VHDL template shows the multiplication operation placed outside the process block and the pipeline stages represented as shift registers library ieee use ieee std logic 1164 all use ieee nume
314. ptimize Instantiated Yes No Primitives read_cores Read Cores Yes No register_balancing Register Balancing Yes No Forward Backward move_first_stage Move First Flip Flop Stage Yes No move last stage Move Last Flip Flop Stage Yes No register duplication Register Duplication Yes No sd Cores Search Directories Any valid path to directories separated by spaces and enclosed in double quotes slice packing Slice Packing Yes No slice utilization ratio Slice Utilization Ratio integer Default 100 slice utilization ratio Slice Utilization Ratio Delta integer Default 5 maxmargin write timing constraints Write Timing Constraints Yes No The following options have become obsolete for the current version of XST Table 10 7 Run Command Options Description Values complex clken Complex Clock Enable Yes No XST User Guide www xilinx com 355 1 800 255 7778 7 XILINX Getting Help 356 Chapter 10 Command Line Mode If you are working from the command line on a Unix system XST provides an online Help function The following information is available by typing help at the command line XST s help function can give you a list of supported families available commands switches and their values for each supported family To get a detailed explanation of an XST command use the following syntax help arch family name command command name where e
315. r 7 Verilog Language Support Following is an example module upperlower4 inputl INPUT1 outputl output2 input inputl input INPUT1I For the above example INPUT1 is renamed to INPUT1_rnm0 The following restrictions apply for Verilog within XST e Designs using equivalent names named blocks tasks and functions are rejected Example always clk begin fir_main5 reg 4 0 fir_main5_wl reg 4 0 fir main5 Wl This code generates the following error message ERROR Xst 863 design v line 6 Name conflict fir main5 fir main5 wl and fir main5 fir main5 W1 e Designs using case equivalent module names are also rejected Example module UPPERLOWER10 module upperlowerl0 This example generates the following error message ERROR Xst 909 Module name conflict UPPERLOWER10 and upperlowerl0 Blocking and Nonblocking Assignments XST rejects Verilog designs if a given signal is assigned through both blocking and nonblocking assignments as in the following example always Q inl begin if in2 outl inl else outl lt in2 end If a variable is assigned in both a blocking and nonblocking assignment the following error message is generated ERROR Xst 880 design v line n Cannot mix blocking and non blocking assignments on signal lt outl gt There are also restrictions when mixing blocking and nonblocking assignments on bits and
316. r SRL16 flip flops are chained to the appropriate width For a parallel shift register each output provides a width of a given shift register For each width a serial shift register is built it drives one output and the input of the next shift register You can enable disable shift register inference using the SHREG EXTRACT constraint Two types of RAM are available in the inference and generation stages Distributed and Block RAMs e Ifthe RAM is asynchronous READ Distributed RAM is inferred and generated e If the RAM is synchronous READ Block RAM is inferred In this case XST can implement Block RAM or Distributed RAM The default is Block RAM In Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II Spartan ITE and Spartan 3 XST uses the following primitives e RAMI6XIS and RAM32XIS for Single Port Synchronous Distributed RAM e RAM16X1D primitives for Dual Port Synchronous Distributed RAM In Virtex II 4 Virtex II Pro Virtex II Pro X and Spartan 3 XST uses the following primitives e For Single Port Synchronous Distributed RAM For Distributed Single Port RAM with positive clock edge RAM16X1S RAM16X25 RAM16X4S RAM16X8S RAM32X1S RAM32X25 RAM32X4S RAM32X8S RAM64X1S RAM64X2S RAM128X1S For Distributed Single Port RAM with negative clock edge RAM16X1S_1 RAM16X25_1 RAM16X45_1 RAM16X85_1 RAM32X15_1 RAM32X25_1 RAM32X45_1 RAM32X85_1 RAM64X15_1 RAM64X25
317. r any variable data type You can code assignments and arithmetic operations with arrays but you cannot select more than one element of an array at one XST User Guide www xilinx com 293 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support time You cannot pass multi dimensional arrays to system tasks or functions or regular tasks or functions Examples The following describes an array of 256 x 16 wire elements each 8 bits wide which can only be assigned via structural Verilog code wire 7 0 array2 0 255 0 15 The following describes an array of 256 x 8 register elements each 64 bits wide which can be assigned via behavioral Verilog code reg 63 0 regarray2 255 0 7 0 The following is a three dimensional array It can be described as an array of 15 arrays of 256 x 16 wire elements each 8 bits wide which can be assigned via structural Verilog code wire 7 0 array3 0 15 0 255 0 15 Data Types The Verilog representation of the bit data type contains the following four values e 0 logic zero e 1 logic one e x unknown logic value e z high impedance XST includes support for the following Verilog data types e Net wire tri triand wand trior wor e Registers reg integer e Supply nets supply0 supply1 e Constants parameter e Multi Dimensional Arrays Memories Net and registers can be either single bit scalar or multiple bit vectors The following example gives some examples of Verilo
318. r used Unit stopwatch synthesized HDL Synthesis Report Macro Statistics FSMs ROMs 16x7 bit ROM 16x10 bit ROM Counters 4 bit up counter NN RPRDN0ayR Advanced HDL Synthesis Es Selecting encoding for FSM 0 Optimizing FSM FSM 0 on signal current state with one hot encoding Low Level Synthesis ze Optimizing unit lt stopwatch gt Optimizing unit lt cnt60 gt Mapping all equations Loading device for application Xst from file 2v40 nph in environment c xilinx Building and optimizing final netlist Found area constraint ratio of 100 5 on block stopwatch actual ratio is 10 Final Report Final Results RTL Top Level Output File Name stopwatch ngr Top Level Output File Name stopwatch Output Format NGC Optimization Goal Speed Keep Hierarchy NO Design Statistics IOs HEN NI Macro Statistics ROMs 3 16x10 bit ROM 1 16x7 bit ROM 2 Registers 2 4 bit register 2 Multiplexers 2 340 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File XILINX 2 to Cell Usage BELS GND LUT1 1 multiplexer FDP Clock Buf IO Buffer IBUF OBUF Others tent Latches fers BUFGP S hs Ss Co o PLENDNRARPROUIRNYRAORPNE SA A Device util ization summary
319. raints Table 5 5 Third Party Constraints Name Vendor XST Equivalent poe xc fast Synplicity fast VHDL Verilog xc slow Synplicity NONE NA You must use the KEEP constraint instead of SIGNAL PRESERVE Verilog example module testkeep inl in2 out1 input inl input in2 output outl wire auxl wire aux2 synthesis attribute keep of auxl is true synthesis attribute keep of aux2 is true assign auxl inl assign aux2 in2 assign outl auxl amp aux2 endmodule The KEEP constraint can also be applied through the separate synthesis constraint file XCF Example Syntax BEGIN MODEL testkeep END NET auxl KE EP true Example of Old Syntax attribute keep of auxl signal is true These are the only two ways of preserving a signal net in an HDL design and preventing optimization on the signal or net during synthesis Constraints Precedence Priority depends on the file in which the constraint appears A constraint in a file accessed later in the design flow overrides a constraint in a file accessed earlier in the design flow Priority is as follows first listed is the highest priority last listed is the lowest 1 Synthesis Constraint File 2 HDL file 3 Command Line Process Properties dialog box in Project Navigator 254 www xilinx com 1 800 255 7778 XST User Guide XILINX Chapter 6 VHDL Language Support
320. rb Dual Read Address dia Primary Data Input doa Primary Output Port dob Dual Output Port 146 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX Following is the VHDL code for a dual port RAM with enable on each port library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity raminfr is port clka in std logic clkb in std logic wea in std logic addra in std logic vector 4 downto 0 addrb in std logic vector 4 downto 0 dia in std logic vector 3 downto 0 doa out std logic vector 3 downto 0 dob out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addra std logic vector 4 downto 0 signal read addrb std logic vector 4 downto 0 begin process clka begin if clka event and clka 1 then if wea 1 then RAM conv integer addra dia end if read addra lt addra end if end process process clkb begin if clkb event and clkb 1 then read addrb lt addrb end if end process doa lt RAM conv integer read addra dob lt RAM conv integer read addrb end syn XST User Guide www xilinx com 147 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Following is the Verilog code for a dual port RAM with enable on each port module raminfr clka c
321. read addr lt addr end if end if end process do lt ram conv integer read addr end syn XST User Guide www xilinx com 125 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog The following template shows the recommended configuration coded in Verilog module raminfr clk we en addr di do input clk input we input en input 4 0 addr input 3 0 di output 3 0 do reg 3 0 RAM 31 0 reg 4 0 read_addr always G8 posedge clk begin if en begin if we RAM addr lt di read_addr lt addr end end assign do RAM read addr endmodule No Change Mode The following templates show a single port RAM in no change mode VHDL The following template shows the recommended configuration coded in VHDL library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity raminfr is port Clk in std logic we in std logic en in std logic addr in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr 126 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addr lt di else do lt RAM conv_in
322. rements set the following options 200 For VHDL designs ensure that the names in the generated netlist are all in uppercase Please note that by default the case for VHDL synthesis flow is lower Specify the case by selecting the Case option under the Synthesis Options tab in the Process Properties dialog box within Project Navigator For Verilog designs ensure that Case is set to maintain which is a default value Specify Case as described above Preserve the hierarchy of the design Specify the Keep Hierarchy setting by selecting the Keep Hierarchy option under the Synthesis Options tab in the Process Properties dialog box within Project Navigator Preserve equivalent flip flops which XST removes by default Specify the Equivalent Register Removal setting by selecting the Equivalent Register Removal option under the Xilinx Specific Options tab in the Process Properties dialog box within Project Navigator www xilinx com XST User Guide 1 800 255 7778 PCI Flow XST User Guide XILINX Prevent logic and flip flop replication caused by high fanout flip flop set reset signals Do this by Setting a high maximum fanout value for the entire design via the Max Fanout menu in the Synthesis Options tab in the Process Properties dialog box within Project Navigator or Setting a high maximum fanout value for the initialization signal connected to the RST port of PCI core by using the MAX_FANOUT attribute for example ma
323. rength Ignored Delay Ignored Table 7 6 Procedural Assignments Blocking Assignments Supported Non Blocking Assignments Supported assign Supported with dence limitations See CASSIEN Assign and Deassign Continuous Procedural Statements Assi t SEEMS force Unsupported release Unsupported if Statement if if else Supported case Statement case casex Supported casez forever Statement Unsupported repeat Statement Supported repeat value must be constant while Statement Supported for Statement Supported bounds must be static fork join Statement Unsupported delay Ignored event O Unsupported pe ecd on Procedural Wal Unsupported named events Unsupported Sequential Blocks Supported Parallel Blocks Unsupported Specify Blocks Ignored XST User Guide www xilinx com 1 800 255 7778 XILINX 319 7 XILINX Chapter 7 Verilog Language Support Table 7 6 Procedural Assignments 320 initial Statement Supported always Statement Supported task Supported Recursion Unsupported functions Supported Recursion Unsupported disable Statement Unsupported Table 7 7 System Tasks and Functions System Tasks Ignored System Functions Unsupported Table 7 8 Design Hierarchy Module definition Supported Macromodule defin
324. riables in assignments Consider the declarations subtype WORD8 is STD LOGIC VECTOR 7 downto 0 type TAB05 is array 4 downto 0 of WORD8 type TAB03 is array 2 downto 0 of TABO5 signal WORD A WORD8 signal TAB A TAB B TABO5 signal TAB C TAB D TABO3 constant CST A TABO3 0000000 0000001 0000010 0000011 0000100 vo010000 0010001 0010010 0100011 0010100 0100000 0100001 70100010 0100011 0100100 A multi dimensional array signal or variable can be completely used TAB A TAB B TAB C TAB D TAB C lt CNST A Just an index of one array can be specified TAB A 5 lt WORD A TAB C 1 lt TAB A Just indexes of the maximum number of dimensions can be specified TAB A 5 0 lt 1 TAB C 2 5 0 lt 101 Just a slice of the first array can be specified TAB A 4 downto 1 lt TAB B 3 downto 0 Just an index of a higher level array and a slice of a lower level array can be specified TAB C 2 5 3 downto 0 lt TAB B 3 4 downto 1 TAB D 0 4 2 downto 0 lt CNST A 5 downto 3 Now add the following declaration subtype MATRIX15 is array 4 downto 0 2 downto 0 of STD LOGIC VECTOR 7 downto 0 258 www xilinx com XST User Guide 1 800 255 7778 Record Types Record Types XST User Guide lt XILINX A multi dimensional array
325. rial in and a serial out module shift C S SI SO input C SI S output SO reg 7 0 tmp always posedge C begin if S tmp 8 b11111111 else begin tmp tmp 6 0 SI end end assign SO tmp 7 endmodule XST User Guide www xilinx com 75 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out Note For this example XST does not infer SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a serial in and a parallel out IO Pins Description C Positive Edge Clock SI Serial In PO 7 0 Parallel Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock a serial in and a parallel out library ieee use ieee std logic 1164 a11 entity shift is port Cp SI an std logic PO out std logic vector 7 downto 0 end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process PO tmp end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock a serial in and a parallel out module shift C SI PO input C SI output 7 0 PO reg 7 0 tmp always posedge C begin tmp tmp
326. ric std all entity mult is generic A port size integer 18 B port size integer 18 i port clk in std_logic A in unsigned A_port_size 1 downto 0 B in unsigned B_port_size 1 downto 0 MULT out unsigned A_port_size B_port_size 1 downto 0 end mult architecture beh of mult is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 type pipe reg type is array 2 downto 0 of unsigned A port size B port size 1 downto 0 signal pipe regs pipe reg type begin mult res lt a in b in process clk begin if clk event and clk 1 then a in lt A b in lt B pipe regs mult res amp pipe regs 2 downto 1 MULT lt pipe regs 0 end if end process end beh Verilog Use the following templates to implement pipelined multipliers in Verilog The following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as single registers module mult clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a in b in wire 35 0 mult res reg 35 0 pipe 1 pipe 2 pipe 3 assign mult res a in b in XST User Guide www xilinx com 115 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques always posedge clk begin a_in lt A b_in lt B pipe 1
327. rrent release Refer to the Constraints Guide for more information Timing constraints that were supported in the old constraint format ALLCLOCKNETS PERIOD OFFSET IN BEFORE OFFSET OUT AFTER INPAD TO OUTPAD MAX DEALY etc are not supported in XCF See Timing Constraints for more information Old XST Constraint Syntax Xilinx continues to support the old constraint syntax without any further enhancements in the current release of XST but will eventually drop support The old constraints syntax is no longer documented in this guide Please refer to Old XST Constraint Syntax in release 5 1i of the XST User Guide available on the Xilinx Support web site for details on using the old constraint style General Constraints This section lists various constraints that you can use with XST These constraints apply to FPGAs CPLDs VHDL and Verilog You can set some of these options under the Synthesis Options tab of the Process Properties dialog box in Project Navigator See Constraints Summary for a complete list of constraints supported by XST XST User Guide Add I O Buffers Add IO Buffers iobuf enables or disables IO buffer insertion Allowed values are yes no By default buffer insertion is enabled XST automatically inserts Input Output Buffers into the design You can manually instantiate I O Buffers for some or all the I Os and XST will insert I O Buffers only for the remaining I Os If you do not want XST
328. s describes a variety of VHDL and Verilog coding techniques that can be used for various digital logic circuits such as registers latches tristates RAMs counters accumulators multiplexers decoders and arithmetic operations The chapter also provides coding techniques for state machines and black boxes e Chapter 3 FPGA Optimization explains how constraints can be used to optimize FPGAs and explains macro generation The chapter also describes the Virtex primitives that are supported e Chapter 4 CPLD Optimization discusses CPLD synthesis options and the implementation details for macro generation e Chapter 5 Design Constraints describes constraints supported for use with XST The chapter explains which attributes and properties can be used with FPGAs CPLDs VHDL and Verilog The chapter also explains how to set options from the Process Properties dialog box in Project Navigator e Chapter 6 VHDL Language Support explains how VHDL is supported for XST The chapter provides details on the VHDL language supported constructs and synthesis options in relationship to XST e Chapter 7 Verilog Language Support describes XST support for Verilog constructs and meta comments e Chapter 8 Mixed Language Support describes how to run an XST project that mixes Verilog and VHDL designs e Chapter 9 Log File Analysis describes the XST log file and explains what it contains e Chapter 10 Command
329. s See Optimize Instantiated Primitives in Chapter 5 e Buffer Type constraint BUFFER TYPE See Buffer Type in Chapter 5 e Hide Messages environmental variable XIL_XST_HIDEMESSAGES See Reducing the Size of the LOG File in Chapter 9 e Library Search Order switch lso See Library Search Order in Chapter 5 Improved Timing constraints support See Timing Constraints in Chapter 5 Deprecated constraints e Quiet Mode quiet switch Obsoleted constraints e Complex Clock Enable Extraction COMPLEX_CLKEN FPGA Flow e Mapping of general logic on Block RAM via Map Logic on BRAM BRAM_MAP constraint See Mapping Logic onto Block RAM in Chapter 3 Log File e Improved HDL Advisor all such messages are referenced as HDL Advisor e Improved HDL reporting See Log File Analysis in Chapter 9 e Verbosity control via Hide Messages XIL_XST_HIDEMESSAGES environment variable See Reducing the Size of the LOG File in Chapter 9 XST in Project Navigator Before you synthesize your design you can set a variety of options for XST The following are the instructions to set the options and run XST from Project Navigator All of these options can also be set from the command line See Chapter 5 Design Constraints and Chapter 10 Command Line Mode for details XST User Guide www xilinx com 23 1 800 255 7778 7 XILINX Chapter 1 Introduction 1 Select your top level
330. s Description A 7 0 B 7 0 Add Operands CI Carry In SUM 7 0 Add Result CO Carry Out XST User Guide www xilinx com 1 800 255 7778 105 7 XILINX Chapter 2 HDL Coding Techniques VHDL Following is the VHDL code for an unsigned 8 bit adder with carry in and carry out library ieee use ieee std logic 1164 a1 use ieee std logic arith all use ieee std logic unsigned all entity adder is port A B in std logic vector 7 downto 0 CI in std logic SUM out std logic vector 7 downto 0 CO out std logic end adder architecture archi of adder is signal tmp std logic vector 8 downto 0 begin tmp lt conv std logic vector conv integer A conv integer B conv integer CI 9 SUM lt tmp 7 downto 0 CO lt tmp 8 end archi Verilog Following is the Verilog code for an unsigned 8 bit adder with carry in and carry out module adder A B CI SUM CO input CI input 7 0 A input 7 0 Be output 7 0 SUM output CO wire 8 0 tmp assign tmp A B CI assign SUM tmp 7 0 assign CO tmp 8 endmodule Simple Signed 8 bit Adder The following table shows pin descriptions for a simple signed 8 bit adder IO pins Description A 7 0 B 7 0 Add Operands SUM 7 0 Add Result 106 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations Z XILINX VHDL Following is the VHDL code for a simple signed 8 bit adder library ieee use ie
331. s a Read First Block RAM with reset ADDR EN WE Block RAM with Reset DI CLK RST X10019 The following table shows pin descriptions for a block RAM with reset IO pins Description clk Positive Edge Clock en Global Enable we Write Enable active High addr Read Write Address rst Reset for data output di Data Input do RAM Output Port VHDL Following is the VHDL code for a read first RAM with reset library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity ramrst is port clk end ramrst im i in s an in in in std logic std logic std logic std logic std logic vector 4 downto 0 std logic vector 3 downto 0 out std logic vector 3 downto 0 www xilinx com 153 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of ramrst is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal ram ram_type begin process clk begin if clk event and clk 1 then if en 1 then optional enable if we 1 then writ nabl ram conv_integer addr lt di end if if rst 1 then optional reset do lt others gt 0 else do lt ram conv integer addr end if end if end if end process end syn Verilog Template Following is the Verilog code for a read first RAM with reset module raminfr clk en we rst addr di do
332. s being violated at a flip flop whose data and clock inputs are derived from external nets Specify the delay of an external output net derived from the Q output of an internal flip flop being clocked from an external device pin See OFFSET in the Constraints Guide for details XCF Syntax OFFSET IN OUT offset time units BEFORE AFTER clk name TIMEGRP group name e From To FROM TO defines a timing constraint between two groups A group can be user defined or predefined FFS PADS RAMS See FROM TO in the Constraints Guide for details Example XCF Syntax TIMESPEC TSname FROM groupl TO group2 value e TNM TNM is a basic grouping constraint Use TNM Timing Name to identify the elements that make up a group which you can then use in a timing specification TNM tags specific FFS RAMs LATCHES PADS BRAMS PORTA BRAMS PORTB CPUS HSIOS and MULTS as members of a group to simplify the application of timing specifications to the group The RISING and FALLING keywords may also be used with TNMs See INM in the Constraints Guide for details XCF Syntax NET PIN net or pin name TNM predefined group identifier e TNM Net TNM NET is essentially equivalent to TNM on a net except for input pad nets Special rules apply when using TNM NET with the PERIOD constraint for Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X or Spartan 3 DLL DCMs XST User Guide www xil
333. s to signals differently than when using concurrent signal assignments The value assignments are made in a sequential mode The latest assignments may cancel previous ones See Example 6 9 First the signal 5 is assigned to 0 but later on for A and B 1 the value for 5 is changed to 1 268 www xilinx com XST User Guide 1 800 255 7778 Combinatorial Circuits XST User Guide 7 XILINX Example 6 9 Assignments in a Process entity EXAMPLE is port A B in BIT S out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B begin S lt 0 if A and B 1 then S lt 1 end if end process end ARCHI A process is called combinatorial when its inferred hardware does not involve any memory elements Said differently when all assigned signals in a process are always explicitly assigned in all paths of the process statements then the process in combinatorial A combinatorial process has a sensitivity list appearing within parentheses after the word process A process is activated if an event value change appears on one of the sensitivity list signals For a combinatorial process this sensitivity list must contain all signals which appear in conditions if case etc and any signal appearing on the right hand side of an assignment If one or more signals are missing from the sensitivity list XST generates a warning for the missing signals and
334. s where a large number of flip flops are available It is also a good alternative when trying to optimize speed or to reduce power dissipation Gray Gray encoding guarantees that only one state variable switches between two consecutive states It is appropriate for controllers exhibiting long paths without branching In addition this coding technique minimizes hazards and glitches Very good results can be obtained when implementing the state register with T flip flops Compact Compact encoding consists of minimizing the number of state variables and flip flops This technique is based on hypercube immersion Compact encoding is appropriate when trying to optimize area Johnson Like Gray Johnson encoding shows benefits with state machines containing long paths with no branching Sequential Sequential encoding consists of identifying long paths and applying successive radix two codes to the states on these paths Next state equations are minimized User In this mode XST uses original encoding specified in the HDL file For example if you use enumerated types for a state register then in addition you can use the ENUM_ENCODING constraint to assign a specific binary value to each state Please refer to Chapter 5 Design Constraints for more details 168 www xilinx com XST User Guide 1 800 255 7778 State Machine Z XILINX Log File The XST log file reports the full information of recognized FSM during the Macro
335. se and infers the ROM accordingly Auto is the default You can apply ROM STYLE as a VHDL attribute or a Verilog meta comment to an individual signal or to the entity module of the ROM This attribute can also be applied globally from the Process Properties dialog box in Project Navigator or from the command line Mapping Logic onto Block RAM If there are unused Block RAM resources and your design does not fit into your target device you can place some of your design logic into Block RAM To do this the you must decide what part of the HDL design is to be placed in Block RAM and put this part of the RTL description in a separate hierarchical block Attach a BRAM_MAP constraint to this separate block either directly in HDL code or via the XCF file Please note that in the current release XST cannot automatically decide what logic could be placed in Block RAM When placing logic into a separate block it must satisfy the following criteria e All outputs must be registered e The block may contain only one level of registers which are output registers e All output registers must have the same control signals e The output registers must have a Synchronous Reset signal e The block cannot contain multisources or tristate busses e The KEEP attribute is not allowed on intermediate signals XST attempts to map the logic onto Block RAM during the Advanced Synthesis step If any of the listed requirements are not satisfied XST does not
336. se ieee std logic 1164 a1 entity priority is port sel in std logic vector 7 downto 0 code out std logic vector 2 downto 0 end priority www xilinx com XST User Guide 1 800 255 7778 Logical Shifters Z XILINX architecture archi of priority is begin code lt 000 when sel 0 1 ls 001 when sel 1 1 els 010 when sel 2 1 els 011 when sel 3 1 els 100 when sel 4 1 els 101 when sel 5 1 els 110 when sel 6 1 els 111 when sel 7 1 els end archi Verilog Following is the Verilog code for a 3 bit 1 of 9 Priority Encoder module priority sel code input 7 0 sel output 2 0 code reg 2 0 code always G8 sel begin if sel 0 code lt 3 b000 else if sel 1 code lt 3 b001 else if sel 2 code lt 3 b010 else if sel 3 code lt 3 b011 else if sel 4 code lt 3 b100 else if sel 5 code lt 3 b101 else if sel 6 code lt 3 b110 else if sel 7 code lt 3 b111 else code lt 3 bxxx end endmodule Logical Shifters Xilinx defines a logical shifter as a combinatorial circuit with 2 inputs and 1 output e The first input is a data input that is shifted e The second input is a selector whose binary value defines the shift distance e The output is the result of the shift operation Note All of these l Os are mandatory otherwise XST does not infer a logical shifter
337. see Chapter 3 FPGA Optimization for details on ROM implementation Here is a list of VHDL Verilog templates described below e ROM with registered output ROM with registered address The following table shows pin descriptions for a registered ROM IO Pins Description clk Positive Edge Clock en Synchronous Enable active High addr Read Address data Data Output VHDL Following is the recommended VHDL code for a ROM with registered output library ieee use ieee std logic 1164 a1 use ieee std logic unsigned all entity rominfr is port clk in std logic en in std logic addr in std logic vector 4 downto 0 data out std logic vector 3 downto 0 end rominfr 156 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX architecture syn of rominfr is type rom_type is array 31 downto 0 of std_logic_vector 3 downto 0 constant ROM rom type 0001 0010 0011 0100 O0T101 0110 O111 1000 1001 T010 ph LOL 1100 1T101 7 17110 1111 0001 0010 0011 0100 OTO0T r O10 0111 1000 1001 1010 1011 1100 1101 1110 1111 begin process clk begin if clk event and clk 1 then if en 1 then data lt ROM conv integer addr end if end if end process end syn Following is alternate VHDL code for a ROM with registered output library ieee use ieee std logic 1164 all use ieee std logic unsi
338. serial in and a serial out module shift C ALOAD SI D SO input C SI ALOAD input 7 0 D output SO reg 7 0 tmp always 8 posedge C or posedge ALOAD begin if ALOAD tmp D else begin tmp tmp 6 0 SI end end assign SO tmp 7 endmodule 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out Note For this example XST does not infer SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a synchronous parallel load a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In SLOAD Synchronous Parallel Load active High D 7 0 Data Input SO Serial Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock synchronous parallel load serial in and serial out library ieee use ieee std_logic_1164 all entity shift is port C SI SLOAD in std_logic D in std_logic_vector 7 downto 0 SO out std_logic end shift 78 www xilinx com XST User Guide 1 800 255 7778 Shift Registers Z XILINX architecture archi of shift is signal tmp std_logic_vector 7 downto 0 begin process C begin if C event and C 1 then if SLOAD 1 then tmp lt D else tmp lt tmp 6 downto 0 amp SI end if end if end process SO lt tmp 7 end archi Verilog Code
339. ses an automatically generated list This user defined file must list all design files and their libraries in the order in which they are to be compiled from top to bottom Type each file library pair on its own line with a semicolon separating the library from the file The format is as follows library name file name library name file name Following is an example work stopwatch vhd work statmach vhd Note This property is not connected to the Custom Compile File List property in the SimulationProperties dialog box which means that a different compile list file is used for synthesis than for simulation VHDL Attribute Syntax You can describe constraints with VHDL attributes in your VHDL code Before it can be used an attribute must be declared with the following syntax attribute AttributeName Type Example attribute RLOC string The attribute type defines the type of the attribute value The only allowed type for XST is string An attribute can be declared in an entity or architecture If declared in the entity it is visible both in the entity and the architecture body If the attribute is declared in the architecture it cannot be used in the entity declaration Once declared a VHDL attribute can be specified as follows attribute AttributeName of ObjectList ObjectType is AttributeValue 216 www xilinx com XST User Guide 1 800 255 7778 Verilog Meta Comment Syntax Z XILINX Examples attribute RL
340. ses the MUXCY primitive to chain the conditions of the priority encoder which results in its high speed implementation You can enable disable priority encoder inference using the PRIORITY_EXTRACT constraint Generally XST does not infer and so does not generate a large number of priority encoders Therefore Xilinx recommends that you use the PRIORITY_EXTRACT constraint with the force option if you would like to use priority encoders A decoder is a demultiplexer whose inputs are all constant with distinct one hot or one cold coded values An n bit or 1 of m decoder is mainly characterized by an m bit data output and an n bit selection input such that n 2 1 lt m lt n 2 www xilinx com XST User Guide 1 800 255 7778 Macro Generation XILINX Once XST has inferred the decoder the implementation uses the MUXF5 or MUXCY primitive depending on the size of the decoder You can enable disable decoder inference using the DECODER EXTRACT property Shift Register RAMs XST User Guide Two types of shift register are built by XST e Serial shift register with single output e Parallel shift register with multiple outputs The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula Width 8 A3 4 A2 2 A1 A0 1 If A3 A2 Al and AO are all zeros 0000 the shift register is one bit long If they are all ones 1111 it is 16 bits long For serial shift registe
341. single process module fsm clk reset x1 outp input clk reset xl output outp reg outp reg 1 0 state parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 always posedge clk or posedge reset begin if reset begin state sl outp 1 b1 end else begin Case state S1 begin if x1 1 b1 state s2 else state s3 outp 1 b1 end s2 begin state s4 outp 1 bl end s3 begin state s4 outp end s4 begin state sl outp end endcase end end endmodule 1 b0 1 b0 FSM with 2 Processes To eliminate a register from the outputs you can remove all assignments outp lt from the Clock synchronization section 162 www xilinx com XST User Guide 1 800 255 7778 State Machine XILINX This can be done by introducing two processes as shown in the following figure State Output Outputs Inputs Function Register Function Only for Mealy Machine PROCESS 1 PROCESS 2 X8986 VHDL Following is VHDL code for an FSM with two processes library IEEE use IEEE std_logic_1164 all entity fsm is port clk reset xl IN std logic outp OUT std logic i end entity architecture behl of fsm is type state type is s1 s2 s3 s4 signal state state type begin processl process clk reset begin if reset 1 then state s1 elsif clk 1 and clk Event then case state is
342. slices 314 www xilinx com XST User Guide 1 800 255 7778 Verilog Meta Comments 7 XILINX The following example is rejected even if there is no real mixing of blocking and non blocking assignments 1f in2 begin out1 0 1 b0 out1 1 lt inl end else begin out1 0 in2 out1 1 lt 1 b1 end Errors are checked at the signal level not at the bit level If there is more than a single blocking non blocking error only the first one is reported In some cases the line number for the error might be incorrect as there might be multiple lines where the signal has been assigned Integer Handling There are several cases where XST handles integers differently from other synthesis tools and so they must be coded in a particular way In Case statements do not use unsized integers in case item expressions as this causes unpredictable results In the following example the case item expression 4 is an unsized integer that causes unpredictable results To avoid problems size the 4 to 3 bits as shown below reg 2 0 conditionl always conditionl begin case conditionl 4 data out 2 lt will generate bad logic 3 d4 data out 2 lt will work endcase end In concatenations do not use unsized integers as this causes unpredictable results If you must use an expression that results in an unsized integer assign the expression to a temporary signal and use the temporary signal in the conca
343. spad Synplicity NA NA map to module Synopsys NA NA net name Synopsys NA NA parallel case Synplicity parallel case Verilog Synopsys return port name Synopsys NA NA resource sharing directives Synopsys resource sharing VHDL directives Verilog set dont touch network Synopsys not required NA set dont touch Synopsys not required NA set dont use cel name Synopsys not required NA set prefer Synopsys NA NA state vector Synopsys NA NA www xilinx com 251 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Table 5 5 Third Party Constraints Name Vendor XST Equivalent id syn allow retiming Synplicity register balancing VHDL Verilog syn black box Synplicity box type VHDL Verilog syn direct enable Synplicity NA NA syn edif bit format Synplicity NA NA syn edif scalar format Synplicity NA NA syn encoding Synplicity fsm encoding VHDL Verilog syn enum encoding Synplicity enum encoding VHDL syn hier Synplicity keep hierarchy VHDL Verilog syn isclock Synplicity NA NA syn keep Synplicity keep VHDL Verilog syn maxfan Synplicity max fanout VHDL Verilog syn netlist hierarchy Synplicity keep hierarchy VHDL Verilog syn noarrayports Synplicity NA NA syn noclockbuf Synplicity clock buffer VHDL Verilog syn noprune Synplicity NA NA syn pipeline Synplicity Register Balancing VHDL Verilog syn probe Synplicity NA NA syn rams
344. stantiation statement is labeled with an identifier Besides naming a component declared in a local component declaration a component instantiation statement contains an association list the parenthesized list that specifies which actual signals or ports are associated with which local ports of the component declaration The Verilog language provides a large set of built in logic gates which can be instantiated to build larger logic circuits The set of logical functions described by the built in gates includes AND OR XOR NAND NOR and NOT Here is an example of building a basic XOR function of two single bit inputs a and b module build xor a b c input a b output c wire c a not b not not a inv a not a not b inv b not b b a and al x a not and a2 y b not or out Cc X y endmodule Each instance of the built in modules has a unique instantiation name such as a inv b inv out The wiring up of the gates describes an XOR gate in structural Verilog Example 7 11 gives the structural description of a half adder composed of four 2 input nand modules Example 7 11 Structural Description of a Half Adder module halfadd X Y C S input X Y output C S wire S1 S2 S3 nand NANDA S3 X Y nand NANDB S1 X S3 nand NANDC S2 S3 Y nand NANDD S S1 S2 assign C S3 endmodule XST User Guide www xilinx com 311 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Sup
345. t synthesized HDL Synthesis Report Macro Statistics Shift Registers sol 8 bit shift register gt I XST User Guide www Xilinx com 69 1 800 255 7778 70 7 XILINX Chapter 2 HDL Coding Techniques Related Constraints A related constraint is SHREG_EXTRACT 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out Note For this example XST infers an SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In SO Serial Output www xilinx com XST User Guide 1 800 255 7778 Shift Registers Z XILINX VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock a serial in and a serial out library ieee use ieee std_logic_1164 all entity shift is port C SI in std logic SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then for i in 0 to 6 loop tmp i1 1 lt tmp i end loop tmp 0 lt SI end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock serial in and serial out module shift C SI SO input C SI output S0 reg 7 0 tmp alw
346. t is attached to is preserved A binary equivalent of the implementation constraints is written to the NGC file but since it is a binary file you cannot edit the implementation constraints there Alternatively you can code implementation constraints in the XCF file according to one of the following syntaxes To apply a constraint to an entire entity use one of the following two XCF syntaxes please refer to the Old XST Constraint Syntax section for more information on the old syntax MODEL EntityName PropertyName MODEL EntityName PropertyName PropertyValue To apply a constraint to specific instances nets or pins within an entity use one of the two following syntaxes BEGIN MODEL EntityName NET INST PIN NetName InstNamelSigName PropertyName END BEGIN MODEL EntityName NET INST PIN NetName l InstName SigName PropertyName Propertyvalue END When written in VHDL code they should be specified as follows attribute PropertyName of NetName InstName PinName signal label is PropertyValue In a Verilog description they should be written as follows synthesis attribute PropertyName of NetName InstNamelPinName is PropertyValue www xilinx com 249 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Examples Following are three examples Example 1 When targeting an FPGA device use the RLOC constraint to indicate the placement of a design element on the FPGA die re
347. t library Disconnection Unsupported Table 6 6 Names Simple Names Supported Selected Names Supported Indexed Names Supported Slice Names Supported including dynamic ranges 286 www xilinx com 1 800 255 7778 XST User Guide VHDL Language Support 7 XILINX Note XST does not allow underscores as the first character of signal names for example _DATA_1 Table 6 7 Expressions Logical Operators Supported and or nand nor xor xnor not Relational Operators Supported ly SA amp concatenation Supported Adding Operators Supported Operators supported rem Supported if the right operand is a constant power of 2 mod Supported Shift Operators Supported sll srl sla sra rol ror abs Supported dd Only supported if the left operand is 2 Sign Supported Abstract Literals Only integer literals are supported Physical Literals Ignored Enumeration Literals Supported String Literals Supported Bit String Literals Supported Operands Record Aggregates Supported Array Aggregates Supported Function Call Supported Qualified Expressions Supported for accepted predefined attributes Types Conversions Supported Allocators Unsupported Static Expressions Supported XST User Guide www xilinx com 1 800 255 7778 287 XILINX 288 Table 6 8 Supported VH
348. tant to recall that Virtex V E II II Pro II Pro X and Spartan II IIE 3 have specific hardware resources to implement shift registers SRL16 for Virtex E II II Pro II Pro X and Spartan II IIE 3 and SRLC16 for Virtex II II Pro II Pro X and Spartan 3 Both are available with or without a clock enable The following figure shows the pin layout of SRL16E SRL16E lo X8423 68 www xilinx com XST User Guide 1 800 255 7778 Shift Registers Z XILINX The following figure shows the pin layout of SRLC16 CLK AO SRLC16 Q15 A1 A2 A3 X9497 Note Synchronous and asynchronous control signals are not available in the SLRC16x primitives SRL16 and SRLC16 support only LEFT shift operation for a limited number of IO signals e clock e clock enable e serial data in e serial data out This means that if your shift register does have for instance a synchronous parallel load no SRL16 is implemented XST uses specific internal processing which allows it to produce the best final results The XST log file reports recognized shift registers when it can be implemented using SRL16 Log File The XST log file reports the type and size of recognized shift registers during the Macro Recognition step Synthesizing Unit lt shift gt Related source file is shift registers l vhd Found 8 bit shift register for signal lt tmp lt 7 gt gt Summary inferred 1 Shift register s Unit shif
349. td logic end shiftregluts architecture rtl of shiftregluts is constant DEPTH WIDTH integer 16 type SRL ARRAY is array 0 to DEPTH WIDTH 1 of std logic The type SRL ARRAY can be array 0 to DEPTH WIDTH 1 of std logic vector BUS WIDTH downto 0 or array DEPTH WIDTH 1 downto 0 of std logic vector BUS WIDTH downto 0 the subtype is forward see below signal SRL SIG SRL ARRAY begin PROC SRL16 process CLK begin if CLK event and CLK 1 then if CE 1 then SRL SIG lt DATA amp SRL SIG 0 to DEPTH WIDTH 2 end if end if end process Q lt SRL SIG conv integer A end rtl 82 www xilinx com XST User Guide 1 800 255 7778 Multiplexers lt XILINX Verilog Code Multiplexers XST User Guide Following is the Verilog code for a 16 bit dynamic shift register module dynamic srl Q CE CLK D A input CLK D CE input 3 0 A output O reg 15 0 data assign Q data A always posedge CLK begin if CE 1 b1 data 15 0 lt data 14 0 D end endmodule XST supports different description styles for multiplexers MUXs such as If Then Else or Case When writing MUXs you must pay particular attention in order to avoid common traps For example if you describe a MUX using a Case statement and you do not specify all values of the selector you may get latches instead of a multiplexer Writing MUXs you
350. tds 210 XST User Guide www xilinx com 15 1 800 255 7778 lt XILINX FIDL ODpEHOnS cri dt ia 213 Xilinx Specific Options 6 n 214 Other Command Line Options 0000s 216 Custom Compile File List 00 ee 216 VHDL Attribute Syntax sis ic eee theless 216 Verilog Meta Comment Syntax conc reo 217 XST Constraint File XCF 0 0 00 0 ccc cece n 217 XCF Syntax and Utilization 0220900 praus trpce Ree bt eek rr RES RES 217 Timing Constraints vs Non timing Constraints lees 218 Di mitatiOBS ob edd A eie ld eg A A ele RS 219 Old XST Constraint Syntax sic toro kh eH de 219 General Constraints issues ree 219 HDL Constraints He e 226 FPGA Constraints non timing sssssssseeee eee 227 CPLD Constraints non timing sess eese 231 Timing Constraints uana ete toten Pe Era deii shed Ke oi Redi dc 234 Global Timing Constraints Support 0 0 0 6 cece eee 235 Domain Definitions o 236 XCF Timing Constraint Support sssssssses e 236 Old Timing Constraint Support sssssseseseeeee ee 238 Constraints Summary sti ap o Rc REA RERO RI RR E REC C RE ERE 238 Implementation Constraints uses eee 249 Handling by XST iiia Re br RR E RE E pay cals ees OE TET ERE 249 Example tiesto Ra eee e eU Y boue ex UD da Ea doe ela edd ta 250 Example 1 32 o tret en A ere eet e civ ette p ed 250 Example lirio do evi e REG debera Lb e
351. ted block RAMs Spartan IIE CPLD none RAM inference completely disabled Read First Mode The following templates show a single port RAM in read first mode VHDL library ieee use ieee std logic 1164 al l use ieee std logic unsigned all entity raminfr is port elk 3 we en addr di do end raminfr XST User Guide in std logic in std logic in std logic in std logic vector 4 downto 0 in std logic vector 3 downto 0 out std logic vector 3 downto 0 www xilinx com 1 800 255 7778 123 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addr lt di end if do lt RAM conv_integer addr end if end if end process end syn Verilog module raminfr clk en we addr di do input clk input we input en input 4 0 addr input 3 0 di output 3 0 do reg 3 0 RAM 31 0 reg 3 0 do always posedge clk begin if en begin if we RAM addr lt di do lt RAM addr end end endmodule Write First Mode The following templates show a single port RAM in write first mode VHDL The following template shows the recommended configuration coded in VHDL library ieee use ieee std logic 1164 a11 use
352. teger addr end if end if end if end process end syn The following templates show an alternate configuration of a single port RAM in no change mode with a registered read address coded in VHDL library ieee use ieee std logic 1164 al use ieee std logic unsigned all entity raminfr is port clk in std logic we in std logic en in std logic addr in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addr std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv integer addr di else read addr lt addr end if end if end if end process do lt RAM read addr end syn XST User Guide www xilinx com 127 1 800 255 7778 7 XILINX 128 Verilog Chapter 2 HDL Coding Techniques The following template shows the recommended configuration coded in Verilog module raminfr clk we en addr di do input input input input input output clk we en 4 0 addr 3 0 di 3 0 do reg 3 0 RAM 31 0 reg 3 0 do always posedge clk begin if en begin if we RAM addr lt di else do lt RAM addr end end endmodule Single Port RAM with Asy
353. tenation as shown below reg 31 0 temp assign temp 4 b1111 2 assign dout 12 3 temp din Verilog Meta Comments XST supports meta comments in Verilog Meta comments are comments that are understood by the Verilog parser XST User Guide www xilinx com 315 1 800 255 7778 XILINX Chapter 7 Verilog Language Support Meta comments can be used as follows e Set constraints on individual objects for example module instance net e Set directives on synthesis parallel case and full case directives translate on translate off directives all tool specific directives for example syn sharing refer to Chapter 5 Design Constraints for details Meta comments can be written using the C style or the Verilog style for comments C style comments can be multiple line Verilog style comments end at the end of the line XST supports the following e Both C style and Verilog style meta comments e translate_on translate off directives synthesis translate_on synthesis translate_off e parallel case full case directives synthesis parallel case full case synthesis parallel case synthesis full case e Constraints on individual objects The general syntax is synthesis attribute AttributeName of ObjectName is AttributeValue Examples synthesis attribute RLOC of u123 is R11C1 S0 synthesis attribute HUSET ul MY SET synthesis attribute fsm extract
354. tension to determine if the syntax is related to the new or old style Please note that if the extension is not xcf XST interprets it as the old constraint style You can specify the constraint file in ISE by going to the Synthesis XST Process Properties clicking the Synthesis Options tab enabling the Use Synthesis Constraints File option by clicking the check box clicking the value field for the Synthesis Constraints File option and typing the constraint file name You can also browse for an existing file to use by clicking the box to the right of the value field Also to quickly enable disable the use of a constraint file by XST you can check or uncheck the Use Synthesis Constraint File option in this same menu By selecting this option you invoke the iuc command line switch To specify the constraint file in command line mode use the uc switch with the run command See Chapter 10 Command Line Mode for details on the run command and running XST from the command line XCF Syntax and Utilization XST User Guide The syntax enables you to specify a specific constraint for the entire device globally or for specific modules in your design The syntax is basically the same as the old UCF syntax for applying constraints to nets or instances but with an extension to the syntax to allow constraints to be applied to specific levels of hierarchy You can use the keyword MODEL www xilinx com 217 1 800 255 7778 XILINX
355. the Reducing the Size of the LOG File in Chapter 9 for more information For example assume that the text below is contained in a file foo scr run ifn ttl prj ifmt MIXED opt mode SPEED opt level 1 ofn ttl ngc p lt parttype gt This script file can be executed under XST using the following command xst ifn foo scr You can also generate a log file with the following command xst ifn foo scr ofn foo log A script file can be run either using xst ifn script name or executed under the XST prompt by using the script script name command Script foo scr If you make a mistake in an XST command command option or its value XST issues an error message and stops execution For example if in the previous script example VHDL is incorrectly spelled VHDLL XST gives the following error message ERROR Xst 1361 Syntax error in command run for option ifmt parameter VHDLL is not allowed www xilinx com XST User Guide 1 800 255 7778 Setting Up an XST Script 7 XILINX Setting Up an XST Script An XST script is a set of commands each command having various options XST recognizes the following commands run e set e elaborate Run Command Following is a description of the run command e The command begins with a keyword run which is followed by a set of options and its values run option 1 value option 2 value e Each option name starts with dash For instance if
356. the circuit are declared Each port has a name and a mode in out and inout as shown in the example below module EXAMPLE A B C D E input A B C output D inout E wire D E assign E oe A 1 bz assign D B amp E endmodule The input and output ports defined in the module declaration called EXAMPLE are the basic input and output I O signals for the design The inout port in Verilog is analogous to a bi directional I O pin on the device with the data flow for output versus input being controlled by the enable signal to the tristate buffer The preceding example describes E as a tristate buffer with a high true output enable signal If oe 1 the value of signal A is output on the pin represented by E If oe 0 then the buffer is in high impedance Z and any input value driven on the pin E from the external logic is brought into the device and fed to the signal represented by D www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features Z XILINX Verilog Assignments There are two forms of assignment statements in the Verilog language e Continuous Assignments e Procedural Assignments Continuous Assignments Continuous assignments are used to model combinatorial logic in a concise way Both explicit and implicit continuous assignments are supported Explicit continuous assignments are introduced by the assign keyword after the net has been separately declared Implicit
357. thesis xst ifn stopwatch xst During this run XST creates the following files watchvhd ngc an NGC file ready for the implementation tools xst srp the xst log file 3 Ifyou want to save XST messages in a different log file for example wat chvhd log execute the following command xst ifn stopwatch xst ofn watchvhd log www xilinx com XST User Guide 1 800 255 7778 Example 2 How to Synthesize Verilog Designs Using Command Line Mode Z XILINX You can improve the readability of the xst txt file especially if you use many options to run synthesis by placing each option with its value on a separate line respecting the following rules e The first line must contain only the run command without any options e There must be no blank lines in the middle of the command e Each line except the first one must start with a dash For the previous command example xst scr should look like the following run ifn watchvhd vhd ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 Example 2 How to Synthesize Verilog Designs Using Command Line Mode The goal of this example is to synthesize a hierarchical Verilog design for a Virtex FPGA using Command Line Mode Example 2 uses a Verilog design called watchver These files can be found in the ISEexamples watchver directory of the ISE installation directory e stopwatch v e statmach v e decode v e cnt60 v e sma
358. thesizing Unit mult Related source file is multipliers_1 vhd Found 8x4 bit multiplier for signal res Summary inferred 1 Multiplier s Unit mult synthesized HDL Synthesis Report Macro Statistics Multipliers LT 8x4 bit multiplier tol Related Constraints A related constraint is MULT STYLE Unsigned 8x4 bit Multiplier The following table shows pin descriptions for an unsigned 8x4 bit multiplier IO pins Description A 7 0 B 3 0 MULT Operands RES 7 0 MULT Result XST User Guide www xilinx com 111 1 800 255 7778 7 XILINX 112 Chapter 2 HDL Coding Techniques VHDL Following is the VHDL code for an unsigned 8x4 bit multiplier library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity mult is port A in std logic vector 7 downto 0 B in std logic vector 3 downto 0 RES out std logic vector 11 downto 0 end mult architecture archi of mult is begin RES lt A B end archi Verilog Following is the Verilog code for an unsigned 8x4 bit multiplier module compar A B RES input 7 0 A input 3 0 B output 11 0 RES assign RES A B endmodule Pipelined Multipliers To increase the speed of designs with large multipliers XST is capable of inferring pipelined multipliers By interspersing registers between the stages of large multipliers pipelining can significantly increase the
359. tion Ratio SLICE UTILIZATION RATIO constraint defines the area size that XST must not exceed during timing optimization If the constraint cannot be met XST makes timing optimization regardless This constraint can be specified by selecting the Slice Utilization Ratio option under the Synthesis Options tab in the Process Properties dialog box within Project Navigator or with the slice utilization ratio command line option See SLICE UTILIZATION RATIO in the Constraints Guide for details Slice Utilization Ratio Delta The Slice Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN constraint is closely related to the SLICE UTILIZATION RATIO constraint It defines the tolerance margin for the SLICE UTILIZATION RATIO constraint If the ratio is within the margin set the constraint is met and timing optimization can continue For details see Speed Optimization Under Area Constraint in Chapter 3 and also see SLICE UTILIZATION RATIO MAXMARGIN in the Constraints Guide www xilinx com XST User Guide 1 800 255 7778 CPLD Constraints non timing Z XILINX Map Entity on a Single LUT The Map Entity on a Single LUT LUT MAD constraint forces XST to map a single block into a single LUT If a described function on an RTL level description does not fit in a single LUT XST issues an error message See the LUT_MAP section in the Constraints Guide for details Read Cores The Read Cores read_cores command line option e
360. tor 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addl1 std logic vector 4 downto 0 signal read add2 std logic vector 4 downto 0 begin process clkl begin if clkl event and clk1 1 then if we 1 then RAM conv_integer add1 lt di end if read_addl lt addl end if end process dol lt RAM conv integer read add1 process clk2 begin if clk2 event and clk2 1 then read add2 lt add2 end if end process do2 lt RAM conv integer read add2 end syn 142 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs Verilog Following is the Verilog code module raminfr clk en we addra addrb di doa input clk input en input we input 4 0 addra input 4 0 addrb input 3 0 di output 3 0 doa output 3 0 dob reg 3 0 ram 31 0 reg 4 0 read addra reg 4 0 read addrb always posedge clk begin if en begin if we ram addra lt di read addra lt addra read addrb lt addrb end end assign doa ram read addra assign dob ram read addrb endmodule Dual Port RAM with One Enable Controlling Both Ports The following descriptions are directly mappable onto Block RAM as shown in the following XST User Guide figure ADDRA ADDRB DOA EN Block WB RAM DOB DI CLK NY X9477 www xil
361. tory Target Parameters A gt All rights reserved stopwatch prj Input Format VHDL Ignore Synthesis Constraint File NO Figure 1 1 View Synthesis Report ln t Col 23 ES 7 XST User Guide www xilinx com 1 800 255 7778 27 7 XILINX Chapter 1 Introduction 28 www xilinx com XST User Guide 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques Introduction XST User Guide This chapter contains the following sections Introduction e Signed Unsigned Support e Registers e Tristates e Counters e Accumulators e Shift Registers e Dynamic Shift Register e Multiplexers e Decoders e Priority Encoders e Logical Shifters e Arithmetic Operations e RAMs ROMs e State Machine e Black Box Support Designs are usually made up of combinatorial logic and macros for example flip flops adders subtractors counters FSMs RAMs The macros greatly improve performance of the synthesized designs Therefore it is important to use some coding techniques to model the macros so that they are optimally processed by XST During its run XST first tries to recognize infer as many macros as possible Then all of these macros are passed to the Low Level Optimization step either preserved as separate blocks or merged with surrounded logic in order to
362. tructs are visible to Verilog code When you do this XST uses the entity architecture pair as the Verilog VHDL boundary XST performs the binding during elaboration In the binding process XST searches for a Verilog module name it ignores any architecture name specified in the module instantiation using the name of the instantiated module in the user specified list of unified logical libraries in the user specified order See Library Search Order File for search order details If found XST binds the name If XST cannot find a Verilog module it treats the name of the instantiated module as a VHDL entity and searches for it using a case sensitive search for a VHDL entity XST searches for the VHDL entity in the user specified list of unified logical libraries in the user specified order assuming that a VHDL design unit was stored with extended identifier See Library Search Order File for search order details If found XST binds the name XST selects the first VHDL entity matching the name and binds it XST has the following limitations when instantiating a VHDL design unit from a Verilog module e Explicit port association must be used That is formal and effective port names must be specified in the port map e All parameters must be passed at instantiation even if they are unchanged e The parameter override shall be named and not ordered The parameter override must be done though instantiation and not through defparams The
363. ts Virtex TI TI Pro Guide for Guide for II Pro X E details details tmn See the See the Spartan II IIE 3 Constraints Constraints Virtex II TI Pro Guide for Guide for II Pro X E details details tnm_net See the See the Spartan II IIE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E details details XST User Guide www xilinx com 1 800 255 7778 247 XILINX Chapter 5 Design Constraints Table 5 3 XST Timing Constraints Supported Only in XCF Name Value Target Technology timegrp See the See the Spartan TI IIE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E details details tig See the See the Spartan II IIE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E details details from to See the See the Spartan IT IIE 3 Constraints Constraints Virtex II TI Pro Guide for Guide for II Pro X E details details The following table shows the timing constraints supported by XST that you can invoke only through the old XST constraint interface Table 5 4 XST Timing Constraints Only Supported by Old XST Syntax Name Value Target Technology allclocknets real ns ps us top entity module Spartan I IIE 3 Virtex TI II Pro II Pro X E period real ns ps us ms primary clock signal Spartan TI TIE
364. tyle Synplicity NA NA syn reference clock Synplicity NA NA syn romstyle Synplicity NA NA syn sharing Synplicity resource sharing VHDL Verilog syn state machine Synplicity fsm extract VHDL Verilog syn tco n Synplicity NA NA syn tpd n Synplicity NA NA 252 www xilinx com XST User Guide 1 800 255 7778 Third Party Constraints Table 5 5 Third Party Constraints 7 XILINX XST User Guide Name Vendor XST Equivalent icd syn tristate Synplicity NA NA syn tristatetomux Synplicity NA NA syn tsu n Synplicity NA NA syn useenables Synplicity NA NA syn useioff Synplicity iob VHDL Verilog translate off translate on Synplicity translate off VHDL Synopsys translate on Verilog xc alias Synplicity NA NA xc clockbuftype Synplicity clock buffer VHDL Verilog xc fast Synplicity fast VHDL Verilog xc fast auto Synplicity fast VHDL Verilog xc global buffers Synplicity bufg VHDL Verilog xc ioff Synplicity iob VHDL Verilog xc isgsr Synplicity NA NA xc loc Synplicity loc VHDL Verilog xc map Synplicity lut map VHDL Verilog xc ncf auto relax Synplicity NA NA xc nodelay Synplicity nodelay VHDL Verilog xc padtype Synplicity iostandard VHDL Verilog xc props Synplicity NA NA xc pullup Synplicity pullup VHDL Verilog xc rloc Synplicity rloc VHDL Verilog www xilinx com 253 1 800 255 7778 7 XILINX Chapter 5 Design Const
365. uation shaping processing also includes a critical path optimization algorithm which tries to reduce the number of levels of critical paths The CPLD fitter multi level optimization is still recommended because of the special optimizations done by the fitter D to T flip flop conversion De Morgan Boolean expression selection How to Obtain Better Frequency The frequency depends on the number of logic levels logic depth In order to reduce the number of levels the following options are recommended e Optimization Effort 2 this value implies the calling of the collapsing algorithm which tries to reduce the number of levels without increasing the complexity beyond certain limits e Optimization Goal speed the priority is the reduction of number of levels The following tries in this order may give successively better results for frequency Try 1 Select only optimization effort 2 and speed optimization The other options have default values e Optimization effort 2 e Optimization Goal speed Try 2 Flatten the user hierarchy In this case the optimization process has a global view of the design and the depth reduction may be better e Optimization effort 1 or 2 e Optimization Goal speed e Keep Hierarchy no XST User Guide www xilinx com 207 1 800 255 7778 XILINX Chapter 4 CPLD Optimization Try 3 Merge the macros with surrounded logic The design flattening is increased e Optimization effort 1
366. uide www xilinx com 129 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Single Port RAM with False Synchronous Read The following descriptions do not implement true synchronous read access as defined by the Virtex block RAM specification where the read address is registered They are only mappable onto Distributed RAM with an additional buffer on the data output as shown below Distributed DO X8977 The following table shows pin descriptions for a single port RAM with false synchronous read IO Pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output VHDL Following is the VHDL code for a single port RAM with false synchronous read library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk we a di do i end raminfr 130 in i un in in std logic std logic std logic vector 4 downto 0 std logic vector 3 downto 0 out std logic vector 3 downto 0 www xilinx com XST User Guide 1 800 255 7778 RAMS ROMs 7 XILINX architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if do
367. usive OR Supported Bitwise Equivalence Supported Reduction AND amp Supported Reduction NAND amp Supported Reduction OR l Supported Reduction NOR Supported www xilinx com 1 800 255 7778 XST User Guide Behavioral Verilog Features XST User Guide Table 7 1 Expressions Reduction XOR N Supported Reduction XNOR IN Ne Supported Left Shift lt lt Supported Right Shift Signed gt gt gt Supported Left Shift Signed lt lt lt Supported Right Shift gt gt Supported Conditional 2 Supported Event OR or Supported 7 XILINX The following table lists the results of evaluating expressions using the more frequently used operators supported by XST Note The and are special comparison operators useful in simulations to check if a variable is assigned a value of x or z They are treated as or in synthesis Table 7 2 Results of Evaluating Expressions ab a b a al b al b agb a amp amp b a b a b a b 00 1 1 0 0 0 0 0 0 0 01 0 0 1 1 0 0 1 1 1 0x x 0 x 1 0 0 x x x 0z x 0 x 1 0 0 x x x 10 0 0 1 1 0 0 1 1 1 11 1 1 0 0 1 1 1 1 0 1x x 0 x 1 x x 1 1 x 1z x 0 x 1 x x 1 1 x x 0 x 0 x 1 0 0 x x x x1 x 0 x 1 x x 1 1 x Xx x 1 x 0 x x x x x XZ x 0 x 1 x x x x x z0 x 0 x 1 0 0 x x x z1 x 0 x 1 x x 1 1 x ZX x 0 x 1 x x x x x ZZ x 1 x 0 x x x x x
368. ut unsigned 7 downto 0 end lshift architecture archi of lshift is begin with SEL select SO DI when 00 DI sll 1 when 01 DI sll 2 when others end archi Verilog Following is the Verilog code module lshift DI SEL SO input 7301 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always Q8 DI or SEL begin case SEL 2 b00 SO lt DI 2 b01 SO lt DI lt lt 1 default SO lt DI lt lt 2 endcase end endmodule Example 3 XST does not infer a logical shifter for this example as the value is not incremented by 1 for each consequent binary value of the selector IO pins Description D 7 0 Data Input SEL shift distance selector SO 7 0 Data Output VHDL Following is the VHDL code library ieee use ieee std_logic_1164 all use ieee numeric_std all 100 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations 7 XILINX Verilog entity lshift is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO out unsigned 7 downto 0 end lshift architecture archi of lshift is begin with SEL select SO DI when 00 DI sll 1 when 01 DI sll 3 when 10 DI sll 2 when others end archi Following is the Verilog code module lshift DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always Q8 DI or SEL begin case SEL 2 b00 SO lt
369. ve several processes 1 2 or 3 in your description depending upon how you consider and decompose the different parts of the preceding model Following is an example of the Moore Machine with Asynchronous Reset RESET e 4 states sl s2 s3 s4 e 5 transitions e linput x1 e loutput outp This model is represented by the following bubble diagram RESET 160 www xilinx com XST User Guide 1 800 255 7778 State Machine Z XILINX FSM with 1 Process Please note in this example output signal outp is a register VHDL Following is the VHDL code for an FSM with a single process library IEEE use IEEE std_logic_1164 all entity fsm is port clk reset xl IN std_logic outp OUT std_logic i end entity architecture behl of fsm is type state type is s1 s2 s3 s4 signal state state type begin process clk reset begin if reset 1 then state lt sl outp lt 1 elsif clk 1 and clk event then Case state is when sl gt if x1 1 then state lt s2 else state lt s3 end if outp lt 1 when s2 gt state lt s4 outp lt 1 when s3 gt state lt s4 outp lt 0 when s4 gt state lt sl outp lt 0 end case end if end process end behl XST User Guide www xilinx com 161 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Following is the Verilog code for an FSM with a
370. when when when res 8 b1111 3 b001 res 8 b1111 3 b010 res 8 b1111 3 b011 res 8 b1111 3 b100 res 8 b111 3 b101 res 8 b1101 3 b110 res 8 b1011 8 b011 Decoders with Unselected Outputs In the current version XST does not infer decoders if one or several of the decoder outputs are not selected except when the unused selector values are consecutive and at the end of the code space Following is an example is sel sel sel sel sel sel sel 1110 1101 10115 0111 01111 ELL I111 000 001 010 011 100 101 110 LETEL else else else else else else else 10 pins Description s 2 0 Selector res Data Output XST User Guide www xilinx com 1 800 255 7778 93 7 XILINX Chapter 2 HDL Coding Techniques VHDL No Decoder Inference For the following VHDL code XST does not infer a decoder library ieee use ieee std logic 1164 a11 entity dec is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end dec architecture archi of dec is begin res lt 00000001 when sel 000 els unused decoder output XXXXXXXX when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 01000000 when sel 110 else 10000000 end archi Verilog No Decoder
371. wnto 0 amp A 0 amp A 0 Example sra Shift Right Arithmetic A 4 downto 0 sra 2 lt A 4 A 4 amp A 4 downto 2 Example rol Rotate Left A 4 downto 0 rol 2 lt A 2 downto 0 amp A 4 downto 3 Example ror Rotate Right A 4 downto 0 ror 2 lt A 1 downto 0 amp A 4 downto 2 Entity and Architecture Descriptions A circuit description consists of two parts the interface defining the I O ports and the body In VHDL the entity corresponds to the interface and the architecture describes the behavior Entity Declaration The I O ports of the circuit are declared in the entity Each port has a name a mode in out inout or buffer and a type ports A B C D E in the Example 6 1 Note that types of ports must be constrained and not more than one dimensional array types are accepted as ports Architecture Declaration Internal signals may be declared in the architecture Each internal signal has a name and a type signal T in Example 6 1 Example 6 1 Entity and Architecture Declaration Library IEEE use IEEE std logic 1164 a11 entity EXAMPLE is port C in std logic out std logic A D end EXAMPLE architecture ARCHI of EXAMPLE is signal T std logic begin end ARCHI Component Instantiation Structural descriptions assemble several blocks and allow the introduction of hierarchy in a d
372. wnto 1 end if end if end process PO tmp end archi Verilog Code Following is the Verilog code for an 8 bit shift left shift right register with a positive edge clock a serial in and a serial out module shift C SI LEFT RIGHT PO input C SI LEFT RIGHT output PO reg 7 0 tmp always posedge C begin if LEFT RIGHT 1 b0 begin tmp tmp 6 0 SI end else begin tmp SI tmp 6 0 end end assign PO tmp endmodule 80 www xilinx com XST User Guide 1 800 255 7778 Dynamic Shift Register Z XILINX Dynamic Shift Register XST can infer Dynamic shift registers Once a dynamic shift register has been identified its characteristics are handed to the XST macro generator for optimal implementation using SRL16x primitives available in Spartan II IIE 3 Virtex II II Pro II Pro X or SRLC16x in Virtex II II Pro II Pro X and Spartan 3 16 bit Dynamic Shift Register with Positive Edge Clock Serial In and Serial Out LOG File XST User Guide The following table shows pin definitions for a dynamic register The register can be either serial or parallel be left or right have a synchronous or asynchronous clear and have a depth up to 16 bits IO Pins Description Clk Positive Edge Clock SI Serial In AClr Asynchronous Clear optional SClr Synchronous Clear optional SLoad Synchronous Parallel Load optional Data Parall
373. x Syntax Constraint Constraint Value Target li Syntax Syntax Value Target fsm_encod auto one hot model yes auto one hot entity signal Spartan II ME 3 ing compact net in model compact Virtex M TI II Pro sequential sequential II Pro X E XC9500 gray johnson gray johnson CoolRunner user user XPLA3 II IIS fsm extract yes no model yes yes no entity signal Spartan I IIE 3 true false net in model Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS fsm style lut bram model yes lut bram entity signal Spartan IT IIE 3 net in model Virtex TI TII Pro II Pro X E full_case na na no no value case Spartan IT IIE 3 statement Virtex TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS incremental yes no model no yes no entity Spartan IT IIE 3 _synthesis true false Virtex II I Pro II Pro X E iob true false net in model no true false signal Spartan I IIE 3 auto inst in model auto instance Virtex TI II Pro II Pro X E iostandard string See net in model no string See signal Spartan I IIE 3 Constraints inst in model Constraints instance Virtex1M TI II Pro Guide for Guide for II Pro X XC9500 details details CoolRunner XPLA3 II IIS keep yes no net in model no yes no signal Spartan IT IIE 3 true false Virtex M TI II Pro II Pro X E XC9500 CoolRunner XPLA3 II IIS keep yes no m
374. x within Project Navigator XOR Preserve The XOR Preserve pld_xp constraint enables or disables hierarchical flattening of XOR macros Allowed values are yes check box is checked and no check box is not checked By default XOR macros are preserved check box is checked The XORs inferred by HDL synthesis are also considered as macro blocks in the CPLD flow but they are processed separately to give more flexibility for the use of device macrocells XOR gates Therefore you can decide to flatten its design Flatten Hierarchy yes Macro Preserve no but you want to preserve the XORs Preserving XORs has a great impact on reducing design complexity Two values are available for this option yes XOR macros are preserved no XOR macros are merged with surrounded logic Preserving the XORs generally gives better results that is the number of PTerms is lower The no value is useful to obtain completely flat netlists Sometimes applying the global optimization on a completely flat design improves the design fitting You obtain a completely flattened design when selecting the following options Flatten Hierarchy yes Macro Preserve no XOR Preserve no The no value for this option does not guarantee the elimination of the XOR operator from the EDIF netlist During the netlist generation the netlist mapper tries to recognize and infer XOR gates in order to decrease the logic complexity This process is independent o
375. x_fanout 2048 Prevent XST from automatically reading PCI cores for timing and area estimation In reading PCI cores XST may perform some logic optimization in the user s part of the design that does not allow the design to meet timing requirements or might even lead to errors during MAP Disable Read Cores by unchecking the Read Cores option under the Synthesis Options tab in the Process Properties dialog box in Project Navigator Note By default XST reads cores for timing and area estimation www xilinx com 201 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization 202 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 4 CPLD Optimization This chapter contains the following sections CPLD Synthesis Options Implementation Details for Macro Generation Log File Analysis Constraints Improving Results CPLD Synthesis Options This section describes the CPLD supported families and their specific options Introduction XST performs device specific synthesis for CoolRunner XPLA3 II IIS and XC9500 XL XV families and generates an NGC file ready for the CPLD fitter The general flow of XST for CPLD synthesis is the following poco ST SES HDL synthesis of VHDL Verilog designs Macro inference Module optimization NGC file generation Global CPLD Synthesis Options This section describes supported CPLD families and lists the XST options related only t
376. xty lsbcount qoutsig 1 LUT3_L 10 gt LO T 0 347 0 100 sixty msbce SW111 SWO N1437 LUT4 13 gt 0 4 0 347 0 553 sixty msbce SW111 sixty_msbce FDCE CE 0 190 sixty msbcount qoutsig 0 Total 2 657ns 1 333ns logic 1 324ns route 50 2 logic 49 8 route Timing constraint Default OFFSET IN BEFORE for Clock CLK Offset 2 055ns Levels of Logic 2 Source xcounter Q THRESHO PAD Destination sixty msbcount qoutsig 3 FF Destination Clock CLK rising Data Path xcounter Q THRESHO to sixty msbcount qoutsig 3 Gate Net Cell in out fanout Delay Delay Logical Name Net Name tenths Q THRESHO 2 0 000 0 519 xcounter xtermcnt UT3_L 12 gt LO ile 0 347 0 100 sixty msbce SW111 SWO N1437 LUT4 13 gt 0 4 0 34 0 553 sixty msbce SW111 sixty_msbce FDCE CE 0 190 sixty msbcount qoutsig 0 Total 2 055ns 0 884ns logic 1 171ns route 43 0 logic 57 0 route Timing constraint Default OFFSET OUT AFTER for Clock CLK Offset 6 697ns Levels of Logic 2 Source sixty lsbcount qoutsig O0 FF Destination ONESOUT 6 PAD Source Clock CLK rising Data Path sixty lsbcount qoutsig 0 to ONESOUT 6 342 www xilinx com XST User Guide 1 800 255 7778 CPLD Log File 7 XILINX Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name FDCE C gt Q 12 0 449 0 688 sixty lsbcount qoutsig 0 sixty lsbcount qoutsig O0 LUT4 10 gt 0 1 0 347 0 383 lsbled Mrom LED inst
377. y false e The test expression is any valid Verilog expression e To prevent endless loops use the iteration_limit switch e The disable statement is not supported The following example shows the use of a While Loop Example 7 5 While Loop Description parameter P 4 always G ID complete begin UNIDENTIFIED integer i reg foung unidentified 0 i 0 found 0 while found amp amp i lt P begin found ID complete i unidentified i ID_complete i i i 1 end end Sequential Always Blocks Sequential circuit description is based on always blocks with a sensitivity list The sensitivity list contains a maximum of three edge triggered events the clock signal event which is mandatory possibly a reset signal event and a set signal event One and only one If else statement is accepted in such an always block An asynchronous part may appear before the synchronous part in the first and the second branch of the If else statement Signals assigned in the asynchronous part must be assigned to the constant values 0 1 X or Z or any vector composed of these values These same signals must also be assigned in the synchronous part that is the last branch of the if else statement The clock signal condition is the condition of the last branch of the if else statement The following example gives the description of an 8 bit register www xilinx com XST User Guide 1
378. ynchronous load Accumulators 4 bit Unsigned Up Accumulator with Asynchronous Clear None www xilinx com 1 800 255 7778 XST User Guide Introduction XST User Guide XILINX Table 2 1 WHDL and Verilog Examples and Templates Macro Blocks Shift Registers Chapter Examples 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out Language Templates 4 bit Loadable Serial In Serial Out Shift Register 4 bit Serial In Parallel out Shift Register 4 bit Serial In Serial Out Shift Register www xilinx com 1 800 255 7778 35 7 XILINX 36 Chapter 2 HDL Coding Techniques Table 2 1 WHDL and Verilog Examples and Templates Macro Blocks Chapter Examples
379. zation is based on the principle that two similar arithmetic resources may be implemented as one single arithmetic operator if they are never used at the same time XST performs both resource sharing and if required reduces the number of multiplexers that are created in the process XST supports resource sharing for adders subtractors adders subtractors and multipliers If the optimization goal is SPEED then the disabling of resource sharing may lead to better results XST advises you to try to deactivate resource sharing at the Advance HDL Synthesis step in order to improve clock frequency 118 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations 7 XILINX Log File The XST log file reports the type and size of recognized arithmetic blocks and multiplexers during the Macro Recognition step Synthesizing Unit lt addsub gt Related source file is resource_sharing_1 vhd Found 8 bit addsub for signal lt res gt Found 8 1 bit 2 to 1 multiplexers Summary inferred 1 Adder Subtracter s inferred 8 Multiplexer s Unit lt addsub gt synthesized HDL Synthesis Report Macro Statistics Multiplexers 1 2 to 1 multiplexer 1 Adders Subtractors 1 8 bit addsub 1 Advanced HDL Synthesis INFO Xst HDL ADVISOR Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization For improved c

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