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F 19 SERVICE MANUAL

1. SOLO PERSINESIDITENSONE 95010 PER MONO 4 SOLO PER SINTESI DI FREQUENZA SOLO PER STEREO SOLO PER MONO O SOLO PER DOPPIA SCART SOLO PER MONO BG 8 5010 CON SINGOLA SCART Ju E g 7 S TT i STEREO NICAM H 38 m H 33 AB 43 di a AA In om ee ux ini s PES a E EE a go I cu oum E ct der pe vs qus sol SE wl cs dimer ur Oso gt as 24 ls mp 2
2. INPUT 8 11 10 9 5 VSSA2 43 VSSA3 56 VSSA4 50 2 IIC ADDRESS 18 11 13 15 16 STEREO A2 MODULE Hin E G 5 11 99 6V 12V STEREO INTERCARRIER ONLY VSSA2 43 VSSA3 56 2 IIC ADDRESS 11 13 15 16 IC1 F19NICAM DRV STEREO MODULE CONNECTOR 3 4 1 2 8 9 FROM PIN 11 TUNER FROM PIN 6 IC 100 1 2 SWITCH FROM PIN8 IC 100 SCART CINC SWITCH SCART 1 IC201 2 3 OF 1 47955 200 2 3 4053 2 F19ASSPH DRW EG 291279 SCART 2 F19 AUDIO STEREO SIGNAL PATH POWER SUPPLY TDA4605 Control IC for Switched Mode Power Supplies using MOS Transistors Features Fold back characteristic provides overload protection for external components e Burst operation under short circuit conditions e Loop error protection e Switch off if line voltage is too low undervoltage switch off Line voltage compensation of overload point e Soft start for quiet start up e Chip over temperature protection thermal shutdown e On chip parasitic transformer oscillation suppression circuitry Functional desciption The IC TDA 4605 1 controls the MOS power transistor and performs all necessary regulation and monitoring functions in free running flyback converters Since good load regulation over a wide load range is
3. R174 TO PIN 201 8128 TO PIN ME PIN 8 IC 2014 R140 IC 200 TR110 R141 FRON PIN 8 SCART 1 FROM PIN 8 SCART 2 111 SWITC INT EX SOUND CVBS FROM ANTENNA TR203 TR211 m CVBS FROM SCART V TUN SWT 16 9 DSC OSC SWT SWT L L MSDA CTI STS MSCL 16 9 STS SDA 1 SWT S1 S2 INTO COPY SWT SCL1 SWT 1 51 AM FM STS VDDM AV2 STS RESET H P STS OSCOUT SYSTEM OSCIN VSS M T OSCGND UHF VDDT TV AV VDDA 0 3 VSYNC 0 4 HSYNC 0 5 BLK OFF R VHF H G L B VSSA RGBREF CVBS0 PIP STS CVBSI COR BLACK INT TEST IREF FRAME TR 208 4 43 MHz TO CTI amp TR 109 16 9 MOULE TR206 3 58MHz TO 205 PIN 35 IC 204 SOUND STDANDARD SWITCH 88 PIN 10 102 TR 108 lt 1 la QZ100 12 MHz ST BY 105 R 106 5V D 102 pom X FLYBACK PULSE FROM EHT VERTICAL BLANKING FROM PIN 8 p ics TR 101 TO PIN 23 24 25 TR 102 gt IC 204 5 R167 FIOMTPER DR EG _ 24099 1 FOR VOLTAGE SISTETIZER ONLY En SAA Sr ee nea eme m VOLT rip EZ EH SOUND LF TUNE TR 208 443 MHz TR p 16 9 TO X13 pix Hz TO PIN 35 3 58M TR219 acus gt HG TR 205 gt IC 204 R174 CVBSPIN 6 TO PIN 10 D IC 102 TO PIN R140 TO PIN 8 IC 201 4 R141 SOUND STDANDARD SWITCH 10 11
4. 9 oe 26 10 uH 1 XIN DD EE mm 1 5 5V 10pF nae 20 48 MHz 16 27 iE CSA20 48 MXZ040 2400 12 15 pF 15 pF ee SSC dani l4 LL4148 BC 807 H Sync for Inset Channel K 1 2 BC 817 330 nF OK uF D 7500 1009 EET L BG Pulse Separator for SSCss 5V e g TDA 9160 UES08584 TDA8310A PAL NTSC colour processor for PIP applications FEATURES Video switch with 2 CVBS inputs One input can beswitched between CVBS and Y C and the circuit can automatically detect whether the incoming signal is CVBS or Y C Integrated chrominance trap and bandpass filters automatically calibrated Integrated luminance delay line Automatic PAL NTSC decoder which can decode all standards available in the world Easy interfacing with the TDA8395 SECAM decoder for multistandard applications Horizontal PLL with an alignment free horizontal oscillator Vertical count down circuit RGB YUV and fast blanking switch with 3 state output and active clamping Low dissipation 560 mW Small amount of peripheral components compared with competition Ics GENERAL DESCRIPTION The TDA8310A is an alignment free PAL NTSC colour processor for Picture in Picture PIP applications The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted in the TDA8310A Therefore the circuit contains an i
5. STS 16 9 STS SWT S1 S2 COPY SWT SWT AVI STS AV2 STS H P STS SYSTEM VSS M T UHF TV AV 0 3 0 4 0 5 ON OFF VHF H VHF L VSSA CVBS0 CVBSI BLACK IREF SWT 16 9 OSC SWT ICRO amp TXT Block Diagram TO CHANGE ASPECT RATIO TO SWITCH S C FROM 4 43 TO 3 58 MHz MAIN BUS pp SOUND STANDARD SWITCH lt lt 5svfrom STBY 4 FROM RESESET CIRCUIT 07100 T 12 MHz VERTICAL lt rrypack lt q HoRIZONTAL FLYBACK PULSE gt To TDAS884X x RGB REFERENCE lt VVOLTAGE 4 PIP DETECTOR NOT CONNECTED NOT CONNECTED e Real time packet 26 engine for processing accented and other characters Comprehensive Teletext language coverage e Video signal quality detector Teletext Display e 525 line and 625 line display e 12 10 character matrix e Double height width and size On Screen Display OSD Definable border colour e Enhanced display features including meshing and shadowing e 260 characters in mask programmed ROM e Automatic FRAME output control with manual override e RGB push pull output to standard decoder ICs e Stable display via slave synchronisation to horizontal sync and vertical sync Additional features of SAA529xA devices e Wide Screen Signalling WSS bit decoding line 23 2 GENERAL DESCRIPTION The SAA529x SAA529xA and SAA549x family of microcontrollers are a derivative of the Philips industry stand
6. E G Data creazione 01 11 99 17 27 30 30 F19MANU doc FORMENTI TO PIN 9IC1 FROM PIN 20 IC TDA9811 6 V TO L L FILTER SWITCH AM AUDIO FROM PIN 22 TDA9811 TDA9875A Ba TDA9875A PINOUT amp PERIPHERALS 9811 Multistandard VIF PLL with QSS IF and AM demodulator FEATURES 5 V supply voltage Two switched VIF inputs gain controlled wide band VIF amplifier AC coupled True synchronous demodulation with active carrier regeneration very linear demodulation good intermodulation figures reduced harmonics excellent pulse response Gated phase detector for L L accent standard VCO frequency switchable between L and L accent alignment external picture carrier frequency Separate video amplifier for sound trap buffering with high video bandwidth VIF AGC detector for gain control operating as peak sync detector for B G optional external AGC and peak white detector for L signal controlled reaction time for L Tuner AGC with adjustable takeover point TOP AFC detector without extra reference circuit SIF input for single reference QSS mode PLL controlled SIF AGC detector for gain controlled SIF amplifier single reference 055 mixer able to operate high performance single reference QSS mode AM demodulator without extra reference circuit AM mute especially for NICAM Stabilizer circuit for ripple rejection and to achieve constant output signals GENERAL DESCRIPTI
7. HOUT VOUT PULSE SANDCASTLE R1 DETECTOR DETECTOR CONTROL SHAPER GENERATOR 2 B1 BLANK1 ix VERTICAL HORIZONTAL SYNC SYNC VERTICAL CLAMP nii SEPARATOR SEPARATOR DIVIDER RGB YUV R SWITCH G B BLANK HI TDA8310A R2 G2 B2 CHROMINANCE CHROMINANCE FILTER BLANC BANDPASS TRAP TUNING IDENT CVBSsw HUE AUTOMATIC INPUT PAL NTSC LUMINANCE DELAY LINE Y DETECTOR SELECTOR GND2 CVBSINT CHROMA CHROMAg li SECAM HI DECODER RW COLOUR2 T COLOUR LOGIC MGD128 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION R2 1 RED input 2 PIP HUE 28 HUE control input G2 2 GREEN input 2 PIP C 29 internally connected test purposes B2 3 BLUE input 2 PIP INTB 30 internal bias IDENT 4 colour standard identification output GND2 31 ground 2 0 V BLANK 5 blanking output CVBSsw 32 CVBS positive negative modulation B 6 BLUE output control switch input G 7 GREEN output 33 connected 8 RED output n c 34 connected SYSTsw 9 CVBS system switch DECeG 35 bandgap decoupling R1 10 RED input 1 VOUT 36 vertical sync output pulse G1 11 GRE
8. FORMENTI 19 SERVICE MANUAL THIS DOCUMENT IS A PROPERTY OF INDUSTRIE FORMENTI ITALIA NO AUTHORIZED MODIFICATIONS ARE PERMITTED CREATED BY There are two different types of 19 chassis that are equipped with two different microcontroller These microcontroller are known as ETT having a code SAA5297A PAINTER with a code number SAA5553 From the point of view of the application on the F19 chassis the two type of microcontroller are substantially having the same performances the same pin out the same firmware but they are not interchangeable as the power supply are different In case of SAA5297A the power supply is 5 V for the SAA5553 is 3 3 V Even if the two devices are non interchangeable the two chassis can be interchanged as the in out interface are exactly the same As the specifications of the two devices are the same and the first version of the chassis was equipped with the SAA5297A in this document the characteristics of it are very much detailed meanwhile there is a very short description as an addendum at the end for the SAA5553 19 CHASSIS DESCRIPTION Summary The F19 is a chassis suitable to drive CRT having both 4 by 3 and 16 to 9 aspect ratio and dimension from 25 up to 34 As we can see from the block diagram the chassis is equipped with the most recent Integrated Circuit like the one chip TV processor TDA884x that does include all the low level signal processing including V
9. 6 lt V6 lt V6 Pin 7 The output of the overload amplifier is connected to pin 7 A load this output causes a reductio in maximal impulse duration This function can be used to implement a soft start when pin 7 is connected to ground by a capacitor Pin 8 The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse double pulsing because an internal circuit inhibits the zero detector for a finite time t UL after the end of each pulse Start Up Behaviour The start up behaviour of the application circuit per sheet 48 is represented on sheet 50 for a line voltage barely above the lower acceptable limit voltage value without soft start After applying the line voltage at the time 10 to the tollowing voltages built up V 6 corresponding to the half wave charge current over R 1 V2 to V2 max typically 6 6 V to the value determined by the divider 10 H 11 The current drawn by the IC in this case is less than 1 6 mA If V6 reaches the threshold V 6E time point t 1 the IC switches on the internal reference voltage The currentdraw max rises to 12 mA The primary current voltage reproducer regulates V 2 down to V 2E and the starting impulse generator generates the starting impulses from time point 5 to
10. SIGNAL CLAMPING analog supply SANDCASTLE DETECTOR GND1 pre amplifiers LINE SAMPLE MEMORY AND HOLD addition output stages buffers gt FREQUENCY PHASE DETECTOR MEMORY AND HOLD 3 MHz shifting clock DIVIDER BY 192 LINE li SAMPLE TDA4665 GND2 R Y colour difference output signals B Y n c n c n c n c MED848 SAA55xx Standard TV microcontrollers with On Screen Display OSD 1 FEATURES Single chip microcontroller with integrated On Screen Display OSD e Versions available with integrated data capture One Time Programmable OTP memory for both program Read Only Memory ROM and character sets Single power supply 3 0 to 3 6 V e 5 V tolerant digital inputs and e 29 lines via individual addressable controls Programmable I O for push pull open drain and quasi bidirectional e Two port lines with 8 mA sink at 0 4 V capability for direct drive of Light Emitting Diode LED e Single crystal oscillator for microcontroller OSD and data capture Power reduction modes Idle and Power down Byte level 2 C bus with dual port I O e Pin compatibility throughout family Operating temperature 20 to 70 2 GENERAL DESCRIPTION The SAA55xx standard family of microcontrollers are a derivative of the Philips industry standard 80C51 microcontroller and are intended for use as the central co
11. end Spanish with which it is possible to control sequentially all video and sound value to adjust several parameter like picture format sound response sleep timer etc and to set others important parameter like standard select country for automatic tuning and sort etc Here below a list of the characteristics of the TV se E G Data creazione 31 10 99 15 38 1 7 f19intro SET CHARACTERISTICS MONO amp STEREO PICTURE TUBE SIZE 4 3 ASPECT RATIO 16 9 ASPECT RATIO 21 25 28 29 34 28 32 STANDARD ANTENNA FOR FREQ SYNTH VIDEO SCART amp CINCH CCIR B G L L D K I B G L L D K I M N TOTAL AVAILABLE CHANNEL NUMBER COLOUR MAX THREE STANDARDS PAL SECAM NTSC SOUND STANDARD B G L L D K I MONO AM amp FM STEREO A2 OR NICAM FACTORY OPTION ww 200 e CHANNELIN ONE RF STANDARD UP TO e NUMBER OF PROGRAM 100 100 e HEADPHONE e LOUDSPEAKERS DIRECT PROGRAM amp CHANNEL CALL WITH PROGRAM amp CHANNEL STEP UP AND DOWN YES VOLTAGE SYNTHESISER CABLE amp HYPERBAND CHANNEL YES e SWITCHABLE AFC YES AUTOMATIC SEARCH TUNING e AST WITH AUTO SORT YES AUDIO SECTION 2 POWER fe MONO 6 W RMS EXTERNAL CONNECTION x O STEREO SET ONLY INTERNAL L S SWITCHED A V INPUT OUTPUT FRONT PANEL CINCH FULL SCART CVBS STEREO RB
12. realised in the YUV domain by detecting the colours near to the skin tone The correction angle can be controlled via the 2 C bus RGB output circuit and black current stabilisation The colour difference signals are matrixed with the luminance signal to obtain the RGB signals The TDA 884X devices have one linear RGB input This RGB signal can be controlled on contrast and brightness like TDA 8374 75 By means of the IE1 bit the insertion blanking can be switched on or off Via the IN1 bit it can be read whether the insertion pin has a high level or not The TDA 885X IC s have an additional RGB input This RGB signal can be controlled on contrast saturation and brightness The insertion blanking of this input can be switched off by means of the IE2 bit Via the IN2 bit it can be read whether the insertion pin has a high level or not E G Data creazione 01 11 99 17 27 20 30 F19MANU doc The output signal has an amplitude of about 2 volts black to white at nominal input signals and nominal settings of the controls To increase the flexibility of the IC it is possible to insert OSD and or teletext signals directly at the RGB outputs This insertion mode is controlled via the insertion input pin 26 in the S DIP 56 and pin 38 in the QFP 64 envelope This blanking action at the RGB outputs has some delay which must be compensated externally To obtain an accurate biasing of the picture tube a Continuous Cathode Calibration circuit
13. viewer by means of the volume control This function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter The AVL function can be activated via the 2 C bus Synchronisation circuit E G Data creazione 01 11 99 17 27 16 30 F19MANU doc The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level These pulses are fed to the slicing stage which is operating at 50 of the amplitude The separated sync pulses are fed to the first phase detector and to the coincidence detector This coincidence detector is used to detect whether the line oscillator is synchronised and can also be used for transmitter identification This circuit can be made less sensitive by means of the STM bit This mode can be used during search tuning to avoid that the tuning system will stop at very weak input signals The first PLL has a very high statical steepness so that the phase of the picture is independent of the line frequency The horizontal output signal is generated by means of an oscillator which is running at twice the line frequency Its frequency is divided by 2 to lock the first control loop to the incoming signal The time constant of the loop can be forced by the 2 C bus fast or slow If required the IC can select the time constant depending on the noise content of the incoming video signal The free running frequency of the oscillator is determined by a digit
14. 55 g oJ E oom 1g III aw 20132 40 Eg i Slo rana E s5 wis mm T i tus Y E n be mom cue wow mom ik 38 nein ma T i am mr g gt ow ee mo T id A 2 Es E i 3 R00 Ls peg ea Ig cap spp y aoa 13 560 cmo n mm REFS uma ee Tmas 7 gm I n 1 E T 5 E ul e owe aeu T m RET n 2 10 zi E meat TT e HEISE LL Pid 10 p ls L m t 5180 hoi Li is c a bs AT gus MET panno 15 fas the E m e 3 m SP a 9 3 Edo E po 1 it I aui E SE ed a ff mem Je T x r3 SAA5553M3 sa d Ja on E sh Pa m s 1 irt te gt a to TEn we 5 me pn w X Y oe MOUNTED x 2 CD m amp RS ao an n 4 Ber im x vis LS w Dd SEE T S M EN e i bes
15. Automatic Volume Level AVL function provides a constant output level of 23 full scale for input levels between 0 and 29 4 full scale There are some fixed decay time constants to choose from i e 2 4 and 8 seconds Pseudo stereo is based on a phase shift in one channel via 2 all pass filter There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150 200 and 300 Hz Volume is controlled individually for each channel ranging from 24 to 83 dB with 1 dB resolution There is also a mute position For the purpose of a simple control software in the microcontroller the decimal number that is sent as an 2 C bus data byte for volume control is identical to the volume setting in dBs e g the 2 C bus data byte 10 sets the new volume value to 10 dB Balance can be realized by independent control of the left and right channel volume settings Contour is adjustable between 0 and 18 dB with 1 dB resolution This function is linked to the volume setting by means of microcontroller software Bass is adjustable between 15 and 12 dB with 1 dB resolution and treble is adjustable between 12 dB with 1 dB resolution For the purpose of a simple control software in the microcontroller the decimal number that is sent as an 2 C bus data byte for contour bass or treble is identical to the new contour bass or treble setting in dBs e g the 2 C bus data byte 8 sets the new value
16. Factory set up LEGENDA FSU FACTORY SET UP REDUCE OF A QUANITY 4 TO GET HOTEL MODE WARNING Do not change value for those parameter that are highlighted please E G Data creazione 31 10 99 15 38 5 7 f19intro Note 1 If during the installation of the TV set the AUTOSTORE method is used it is fundamental before to start the function to select the name of the country as the criteria of listing the broadcasters names is fixed by EBU table that are related to the country itself It is possible to find more channels of the same broadcaster on the Arial In this case the system will place first the signal having TXT with the strongest signal level than the others and finally with the found sequence the weakest one without TXT Note 2 To get HOTEL MODE it is necessary to enter SERVICE MODE and to change the parameter optionb3 Read the original value subtract 4 decimal In HOTEL MODE all tuning systems are not possible the volume is pre fixed and the MENU from the LOCAL KEY BOARD is not accessible Note 3 For fast programming in case of installation of several TV set in Shops or Hotels a Black Box is available on request The procedure for a quick program is as follows 1 Install and tune all channel storing it in the program sequence you want Switch off the Set with the remote control and leave it in Stand by mode Switch on the Black Box and connect it to Scart gt nga N Press the button cor
17. Four 8 bit Analog to Digital converters 2 high current open drain outputs for directly driving LEDs etc 2 C bus interface External ROM and RAM capability on QFP80 package version Teletext acquisition 1 page and 10 page Teletext version Acquisition of 525 line and 625 line World System Teletext with automatic selection Acquisition and decoding of VPS data PDC system A Page clearing in under 64 1 TV line Separate storage of extension packets SAA5296 7 SAA5296 7A and SAA5496 7 Inventory of transmitted Teletext pages stored in the Transmitted Page Table TPT end Subtitle Page Table SPT SAA5296 7 SAA5296 7A and SAA5496 7 Automatic detection of FASTEXT transmission E G Data creazione 01 11 99 17 27 8 30 F19MANU doc FORM ENTI T INTEGRATOR VOLTAGE SINTESYS ONLY TO X13 FRANCE STD SWITCH CTI DETECTOR 16 9 DETECTOR gt SCARTI SCART2 SWITCH SCART 1 TV TO SCART 2 SWITCH FRONT CINCH SCART1 SWITCH SCART LINPUT DETECTOR SCART 2INPUT DETECTOR p HEAD PHONES DETECTOR STANDARD SWITCH UHF SUPPLY VOLTAGE SINTESYS ONLY TV AV SWITCH MENU V V P P LOCAL KEY BOARD OFF SWITCH TUNER SUPPLY V S ONLY TUNER SUPPLY V S ONLY CVBS FROM ANTENNA CVBS FROM SCART SAA5297A DRW PATA SLICER E G 17 10 99 REFPIN SAAS8297A MICRO amp TXT Block Diagram V TUN DSC SWT L L CTI STS 16 9 STS SWT S1 S2 COPY SWT SWT
18. HDRIVE bus TXT lt OPTION gt E W DRIVE COIL amp OSD RBG DRIVER TU PIP LR INPUT BU 150 V OPTION PIP RGB POWER SUPPLY 12 V F19BLDIA DRW TDA 4605 amp STH7N90F1 E G 17 7 99 TDA 9811 nicam TDA 9870A TDA9875A nicam vio E SWITCH LA7955 OPTION IF VIDEO amp PLL DEM H amp V SYNC PROCESSIG nou AGC amp AFC MUTE FULL IIC BUS CONTROLL FOR 522 AUDIO PLL DEM AUTO CUT OFF PAL NTSC SECAM DEC ALL ANALOGUE FUCTIONS LOCAL KEY BOARD B B CHROMA DELAY LINE GEOMETRY CORRECTION FULL SCART INTERFACE RE m Ora Q m gt m z E W LOAD COIL IIC bus FEATURES MODULE TDA4566 SAA4981 16 9 TO 4 3 FI9BDE amp P DRW F19 1 BLOCK DIAGRAM E G 22 04 2000 FORMENTI FI9 TUNING amp TELETEXT SAA529XA FAMILY MAIN CHARACTERISTICS FEATURES General Single chip microcontroller with integrated teletext decoder Single 5 V power supply Single crystal oscillator for teletext decoder display and microcontroller Teletext function can be powered down independent of microcontroller function for reduced power consumption in standby Pin compatibility throughout family Microcontroller 80C51 microcontroller core 16 32 64 kbyte mask programmed ROM 256 768 1280 bytes of microcontroller RAM Eight 6 bit Pulse Width Modulator PWM outputs for control of TV analog signals One 14 bit PWM for Voltage Synthesis Tuner control
19. MUX SC LINE MEMORIES 6 7 MHz LOW PASS FILTER SAA4981 SC LINE MEMORY 5 MHz 6 7 MHz LOW PASS FILTER LOW PASS FILTER SC LINE MEMORY SC LINE MEMORY T 6 7 MHz MEM ORES LOW PASS FILTER SC LINE MEMORY HREF CONTROLLER fe tio fn TEST CTRL2 CTRL1 CTRL3 CLAMP REFERENCE CLMRY CLAOUT BGREF YSIDE BYSIDE RYSIDE YOUT B Y OUT R Y OUT MHA277 Applicable video standards The integrated 16 9 compressor can be used for the following video standards B C D H M and standards D K1 and L will show reducedvideo bandwidth above 5 MHz Clamping circuit The clamping circuits clamp the video input signals Y B Y and P Y to the DC level of the clamp reference signal fed from the clamp reference circuit This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low pass filters and the SC line memories Internal pre filters Before the signals are sampled in the time discrete and amplitude continuous area low pass filtering is necessary to avoid any aliasing Even if the inputs have already been low pass filtered further filtering is advantageous for the electromagnetic compatibility EMC The same transfer function is used for all three low pass filters because of t
20. attained this IC is applicable tor consumer and industrial power supplies The serial circuit of power transistor and primary winding of the flyback transformer is connected to the input voltage During the switch on period of the transistor energy is stored in the transformer and during the switch off period it is fed to the load via the secondary winding By varying switch ontime of the power transistor the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent ot load variations The required control information is taken from the input voltage during the switch on period and from a regulation winding during the switch off period In the different load ranges the switched mode power supply SMPS behaves as follow TDA4605 SMPS CONTRO LC Pagina 1 di 6 e g tda4605R doc No load operation The power supply unit oscillates at its resonant frequency typ 100 kHz to 200 kHz Depending upon the transformator windings the output voltage can be slightly above nominal value Nominal operation The switching frequency declines with increasing load and decreasing AC voltage The duty factor primarly depends on the AC voltage The output voltage is load dependent only Overload point Maximal output power is available at this point ot the output characteristic Overload The energy transferred per operation cycle is limited at the top Therefore the output voltage
21. for attenuation of the carrier harmonics to the video amplifier The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth A low pass filter is integrated to achieve an attenuation of the carrier harmonics for B G and L standard The standard dependent level shift in this stage delivers the same sync level for positive and negative modulation The video output signal is 1 V p for nominal vision IF modulation Video buffer For an easy adaption of the sound traps an operational amplifier with internal feedback is used in the event of B G and L standard This amplifier is featured with a high bandwidth and 7 dB gain The input impedance is adapted output stage delivers a nominal 2 V p p positive video signal Noise clipping is provided 9811 QSS Pagina 3 di 4 e g TDA9811R SIF amplifier and AGC The sound IF amplifier consists of two AC coupled differential amplifier stages Each differential stage comprises a controlled feedback network provided by emitter degeneration The SIF AGC detector is related to the SIF input signals average level of AM or FM carriers and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and single reference QSS mixer The SIF AGC reaction time is set to slow for nominal video conditions But with a decreasing VIF amplitude step the SIF AGC is set to fast mode controlled by the VIF AGC detector In FM mode this reaction t
22. has been developed This function is realised by means of a 2 point black level stabilisation circuit By inserting 2 test levels for each gun and comparing the resulting cathode currents with 2 different reference currents the influence of the picture tube parameters like the spread in cut off voltage can be eliminated This 2 point stabilisation is based on the principle that the ratio between the cathode currents is coupled to the ratio between the drive voltages according to The feedback loop makes the ratio between the cathode currents and 2 equal to the ratio between the reference currents which are internally fixed by changing the black level and the amplitude of the RGB output signals via 2 converging loops The system operates in such a way that the black level of the drive signal is controlled to the cut off point of the gun so that a very good grey scale tracking is obtained The accuracy of the adjustment of the black level is just dependent on the ratio of internal currents and these can be made very accurately in integrated circuits An additional advantage of the 2 point measurement is that the control system makes the absolute value of Ik1 and 2 identical to the internal reference currents Because this adjustment is obtained by means of an adaption of the gain of the RGB control stage this control stabilises the gain of the complete channel RGB output stage and cathode character
23. or displayable characters When the control characters are excluded this gives an addressable set of 212 characters at any given time National option characters The meanings of some character codes between 20H and 7FH depend on the C12 to C14 language control bits from the teletext page header The interpretation of the C12 to C14 language control bits is dependent on the East West bit On Screen Display characters Character codes 80H to 9FH are not addressed by the teletext decoding hardware An editor is available to allow these characters to be redefined by the customer The alternative character shapes in columns 8a and 9 SAA549x only can be displayed when the graphics serial attribute is set This increases the number of customer definable characters to 64 Clock generator The oscillator circuit is a single stage inverting amplifier in a Pierce oscillator configuration The circuitry between XTALIN and XTALOUT is basically an inverter biased to the transfer point A crystal must be used as the feedback element to complete the oscillator circuitry It is operated in parallel resonance XTALIN is the high gain amplifier input and XTALOUT is the output To drive the device externally XTALIN is driven from an external source and XTALOUT is left open circuit E G Data creazione 01 11 99 17 27 12 30 F19MANU doc 12V SOUND LF 4 A 12V D TR218 CVBSPIN 6 FORMENTI 5297 MICRO amp TXT PERIPHERALS
24. source switch FEATURES e Adjustment free wideband synchronous AM demodulator e Audio source mute switch low noise Audio level according EN50049 5 to 8 V power supply or 12 V alternative Low power consumption GENERAL DESCRIPTION The TDA9830 a monolithic integrated circuit is designed for AM sound demodulation used in L and L standard The IC provides an audio source selector and also mute switch FUNCTIONAL DESCRIPTION Sound IF input The sound IF amplifier consists of three AC coupled differential amplifier stages each with approximately 20 dB gain At the output of each stage is a multiplier for gain controlling current distribution gain control The overall control range is approximately 6 to 60 dB and the frequency response 3 dB of the IF amplifier is approximately 6 to 70 MHz The steepness of gain control is approximately 10 mV aB IF AGC The automatic gain control voltage to maintain the AM demodulator output signal at a constant level is generated by a mean level detector This AGC detector charges and discharges the capacitor at pin 3 controlled by the output signal of the AM demodulator compared to an internal reference voltage The maximum charge discharge current is approximately 5 mA This value in combination with the value of the AGC capacitor and the AGC steepness determines the lower cut off audio frequency and the THD figure at low modulation frequency of the whole AM demodulator Therefore
25. to 8 dB Extra bass boost is provided up to 20 dB with 2 dB resolution The implemented coefficient set serves merely as an example on how to use this filter The beeper provides tones in a range from approximately 400 Hz to 30 kHz The frequency can be selected via the 2 C bus The beeper output signal is added to theloudspeaker and headphone channel signals The beeper volume is adjustable with E G Data creazione 01 11 99 17 27 28 30 F19MANU doc respect to full scale between 0 and 93 dB with 3 dB resolution The beeper is effected by mute Soft mute provides a mute ability in addition to volume control with a well defined time 32 ms after which the soft mute is completed A smooth fading is achieved by a cosine masking HEADPHONE AUXILIARY CHANNEL The matrix provides the following functions forced mono stereo channel swap channel and channel 2 or and 5 in Dolby Surround Pro Logic mode Volume is controlled individually for each channel in a range from 24 to 83 dB with 1 dB resolution There is also a mute position For the purpose of a simple control software in the microcontroller the decimal number that is sent as an 2 C bus data byte for volume control is identical to the volume setting in dB e g the 2 C bus data byte 10 sets the new volume value to 10 dB Balance can be realized by independent control of the left and right channel volume settings Bass is adjustable between 15 and 12 dB with 1
26. will only switch to black level AGC in the internal mode The circuits contain a video identification circuit which is independent of the synchronisation circuit Therefore search tuning is possible when the display section of the receiver is used as a monitor However this ident circuit cannot be made as sensitive as the slower sync ident circuit SL and we recommend to use both ident outputs to obtain a reliable search system The ident output is supplied to the tuning system via the 2 C bus The input of the identification circuit is connected to pin 13 S DIP 56 devices the internal CVBS input see Fig 6 This has the advantage that the ident circuit can also be made operative when a scrambled signal is received descrambler connected between pin 6 IF video output and pin 13 A second advantage is that the ident circuit can be used when the IF amplifier is not used e g with built in satellite tuners E G Data creazione 01 11 99 17 27 15 30 F19MANU doc The video ident circuit can also be used to identify the selected CBVS Y C signal The switching between the 2 modes can be realised with the VIM bit Video switches The circuits have two CVBS inputs internal and external CVBS and a Y C input When the Y C input is not required the Y input can be used as third CVBS input The switch configuration is given in Fig 6 The selection of the various sources is made via the 2 C bus For the TDA 884X devices the video sw
27. zoom mode GENERAL DESCRIPTION The TDA8351 is a power circuit for use in 9 and 11 colour deflection systems for field frequencies of 50 to 120 Hz The circuit provides a DC driven vertical deflection output circuit operating as a highly efficient class G system FUNCTIONAL DESCRIPTION The vertical driver circuit is a bridge configuration The deflection coil is connected between the output amplifiers which are driven in phase opposition An external resistor RM connected in series with the deflection coil provides internal feedback information The differential input circuit is voltage driven The input circuit has been adapted to enable it to be used with the TDA9150 TDA9151B TDA9160A TDA9162 TDA8366 and TDA8376 which deliver symmetrical current signals An external resistor RCON connected between the differential input determines the output current through the deflection coil TDA8351 VERTICAL OUTPUT Pagina 1 di 2 e g TDA835IR The relationship between the differential input current and the output current is defined by Idiff RCON Icoil RM The output current is adjustable from 0 5 to A p p by varying RM The maximum input differential voltage is 1 8 V In the application it is recommended that Vdiff 1 5 V typ This is recommended because of the spread of input current and the spread in the value of RCON The flyback voltage is determined by an additional supply voltage VFB The principle of oper
28. 15 m Lr ec he seus xm po 3 eD Lx 1 m EM ns m ST gt tel te 1 IJ LIVE AREA COMPONENTI SOTTO RETE LI E 5v oni IIT ae Industrie Formenti Italia s p a parsed bus LO BASE Fl gt 8 5 12 09 2000 Cod Schema 497 078 Sesser 497008 Dzeondo DIMAIO 1 I 2 T E T 4 5 T 5 7 I T 10 T m I 12 x 1 RN IRE SFI RRA ZTC 474747474747474747 7474747474747474747474747474747474747474747474747474747474747474747474747475 4747474747474747474747474747474747474747474 s E p Y 292 KD b 1 J 3 555 138 1480 n 2 un 133 CND R118 R117 R116 R276 6 9 Kk
29. 9 LER 53 MENU Wred SERVICE 58 SERVICE MODE ENTER E G Data creazione 31 10 99 15 38 3 7 f19intro Table 2 Parameter and value to be adjusted in SERVICE MODE PARAMETER VALUE DESCRIPTION init ctvfor v0 6 on off Default Initialization vg2test on off Cut off adjustment txtbri 0 63 Adjust TXT brightness txtcon 0 63 Adjust TXT Contrast 884c04 Bit FSU Increase blue stretch and the dynamic skin 884c03 Bit FSU acl automatic colour limiter and cathode drive level 88c02 Bit FSU Adgj black stretch blue stretch and the blue back optionb1 Bit FSU Select TV standard and TXT character set optionb2 Bit FSU Scart type selections optionb3 FSU Hotel mode setting nicamuperror 0 63 Nicam sensitivity upper limit nicamlowerror 0 63 Nicam sensitivity Lower limit nicamcon Bit FSU 9875 CONTROL pipcontrast 0 15 PIP Contrast control wblue 0 63 Blue channel gain wgreen 0 63 Green channel gain wred 0 63 Red channel gain ydelaypal 0 63 Luma chroma delay ewtrapeze 0 63 E W Trapezium adjustment ewcorner 0 63 E W Corner Adjustment ewparab 0 63 E W Parabola Adjustment ewwidth 0 63 Horizontal Amplitude h shift 0 63 Horizontal shift S COIT 0 63 Vertical S Correction v shift 0 63 Shift Vertical v ampl 0 63 Vertical Amplitude v slope 0 63 Slope Vertical agc 0 63 AGC adjustment if xx afc 2 3 0 63 FSU
30. A A V INPUT MULTIMEDIA INPUT OUTPUT SCART 5 amp STEREO IN OUT e SCART A TO SCART B LOOP THROUGH VCR SATELLITE ETC FOR PROGRAMS DUBBING e CTI COLOUR TRANSIENT IMPROVEMENT TXT e LEVEL I 8 PAGES LEVEL L5 FASTEXT 7 PAGES FEATURES 4 OPTION e 16 9 TO 4 3 VIDEO COMPRESSION VERTICAL ZOOM OUT MENU DRIVEN SYSTEM ONLY FOR 16 9 TV SET 3 LEVEL e EASY TO USE REMOTE CONTROL REMOTE CONTROL WITH SERVICE USE e PIP E G Data creazione 31 10 99 15 38 247 ACCESSIBLE END USER OPTION f19intro FORMENTI UDI VIDEO EEPROM SCART INTER PCF8582 A V IN OUT TXT amp OSD RBG F16 uppAaTED F19 BLOCK DIAGRAM THIS MODULE IS PRESENT ONLY FOR STEREO SET AUDIO AUDIO VIDEO amp AUDIO 2ND SCART VIDEOSCART FULL SCART SWITCH LA7955 A V CINCH RGB e orron 8584 ST2404CB O gt ARM AAP RGB BUS ONE CHIP VIDEO PROCESSOR gt TDA 8843 4 t UT OFF FILTER IF VIDEO amp PLL DEM H amp V SYNC PROCESSIG l1 T VERTICAL FEEDBACK IIC bus AGC amp AFC MUTE FULL IIC BUS CONTROLL FOR AUDIO PLL DEM AUTO CUT OFF PAL NTSC SECAM DEC ALL ANALOGUE FUCTIONS B B CHROMA DELAY LINE GEOMETRY CORRECTION LOCAL KEY BOARD FULL SCART INTERFACE FEATURES INTERFACE UV ETT FEATURES MODULE TDA4566 CTD SAA5297A SAA4981 16 9 TO 4 3
31. CI S1 voje 1 STS AV2 STS H P STS B SYSTEM U VSS S TXT INT UHF P0 3 0 4 0 5 ON OFF VHF VHF L VSSA 50 CVBS1 BLACK IREF SWT 16 9 OSC SWT MSDA MSCL SDA 1 INTO SCL 1 AM FM VDDM lt RESET OSCOUT OSCIN OSCGND VDDT VDDA VSYNC 4 HSYNC BLK R G B RGBREF PIP STS INT TEST gt FRAME TO CHANGE ASPECT RATIO TO SWITCH S C Jd FROM 4 43 TO 3 58 MHz MAIN IIC BUS IIC BUS FOR pp SOUND STANDARD SWITCH lt 6 5 st By FROM lt keseser incur 1 07100 12 MHz 4 5v VERTICAL lt q FLYBACK 4 HORIZONTAL FLYBACK PULSE TDA884x gt 4 RGB REFERENCE 2 5 VVOLTAGE lt PIP DETECTOR NOT CONNECTED NOT CONNECTED FORMENTI SAA5553M3 TO CURRENT INTEGRATOR VOLTAGE SINTESYS ONLY TO X13 FRANCE STD SWITCH CTI DETECTOR 16 9 DETECTOR SCARTI SCART2 SWITCH 4 SCART 1 TV TO SCART 2 SWITCH FRONT CINCH SCARTI SWITCH SCART 1 INPUT DETECTOR SCART 2 INPUT DETECTOR STANDARD SWITCH UHF SUPPLY VOLTAGE SINTESYS ONLY gt gt HEAD PHONES DETECTOR lt TV AV SWITCH MENU V V P P LOCAL KEY BOARD TV ON OFF SWITCH TUNER SUPPLY V S ONLY TUNER SUPPLY V S ONLY I CVBS FROM ANTENNA CVBS FROM SCART DATA SAA5553 DRW SLICER E G 22 04 2000 REF PIN V TUN DSC SWT L L
32. EN input 1 PH1LF 37 phase 1 loop filter B1 12 BLUE input 1 GND3 38 ground 3 0 V BLANK1 13 blanking input 1 HOUT 39 horizontal sync output pulse CLAMP 14 clamping pulse input SAND 40 sandcastle pulse output 15 decoupling filter tuning 2 41 voltage 2 8 V CHROMA 16 chrominance input XTAL1 42 4 4336 MHz crystal CVBSext 17 external CVBS Y input XTAL2 43 3 5820 MHz crystal for PAL N GND1 18 ground 1 0 V XTAL3 44 3 5756 MHz crystal for PAL M 19 supply voltage 1 8 V XTAL4 45 3 5795 MHz crystal for NTSC CVBSint 20 internal CVBS input PLL 46 PLL colour filter DECpia 21 decoupling digital supply 47 chrominance output for TDA8395 i c 22 internally connected test purposes SECAM 48 SECAM reference output LOGIC2 23 crystal logic 2 input output Y 49 Y output LOGIC1 24 crystal logic 1 input output B Y 50 B Y output COLOUR 25 colour system logic 2 input output R Y 51 R Y output COLOUR1 26 colour system logic 1 input output BLANK2 52 blanking insertion input 2 PIP RAW 27 read write selection input TDA8395 SECAM DECODER FEATURES e Fully integrated filters Alignment free For use with baseband delay GENERAL DESCRIPTION The TDA8395 is self calibrating fully integrated SECAM decoder The IC should preferably be used in conjunction with the PAL NTSC decoder TDA8362 or TDA8366 and with the switched capa
33. IC 200 TR110 i 33V FRON PIN 8 SCART 1 108 di rg 1810 5V FROM PIN 8 SCART 2 D 105 s R40 5V P R146 QZ100 5 lt 12 MHz JE 111 LL sy 0542 5 TO SWITC INT EX SOUND FLYBACK FROM EHT re 4 VERTICAL BLANKING FROM PIN 8 TO PIN 4 IC 10 TV ON OFF CVBS FROM ANTENNA TR203 gt FI9PAPER DRW EG 22 04 2000 CVBS FROM SCART TR211 SISTETIZER ONLY PAINTER SIGNAL PROCESSING FOR VOLTAGE SINTHESIS ONLY FORMENTI Li F19 27 gt L TR202 TO PIN 33 FROM IC 100 1 100 PIN 14 20 21 CVBS BAND SWITCHING FOR TXT TO PIN 24 TR203 100 4 CVBS FOR TXT TO PIN 9 IC 100 TR204 AVI A STATUS FROM PIN 6 1 100 AV1 AV2 SWITCH TR212 CVBSI CVBS OUT FROM PIN 52 IC 100 4 3 TO 16 9 1 3 0F IC201 LA7955 A AVIATS ERE CVBS IN SWITCH IC 100 VIDEO SIGNAL PATH Reset signal The externally applied RESET signal active HIGH is used to initialize the microcontroller core in addition to the teletext decoder However the teletext decoder incorporates a separate internal reset function which is activated on the rising edge of the analog supply The purpose of this internal res
34. L simultaneously with NICAM Programmable identification B G D K and M standard and different identification times DSP section Digital crossbar switch for all digital signal sources and destinations Control of volume balance contour bass treble pseudo stereo spatial bass boost and soft mute Plop free volume control Automatic Volume Level AVL control Adaptive de emphasis for satellite Programmable beeper Monitor selection for FM AM DC values and signals with peak detection option I 2 S bus interface for a feature extension e g Dolby surround with matrix level adjust and mute Analog audio section Analog crossbar switch with inputs for mono and stereo E G Data creazione 01 11 99 17 27 23 30 F19MANU doc e also applicable as SCART 3 input SCART 1 e input output SCART 2 input output and line output User defined full level dB scaling for SCART outputs Output selection of mono stereo dual A B dual A or Dual e 20 kHz bandwidth for SCART to SCART copies e Standby mode with functionality for SCART copies e Dual audio digital to analog converter from DSP to analog crossbar switch bandwidth 15 kHz Dual audio ADC from analog inputs to DSP Two dual audio Digital to Analog Converters DACs for loudspeaker Main and headphone Auxiliary outputs also applicable for L R C and S in the Dolby Pro Logic mode with feature extension GENERAL DESCRIPTION TDA9875A is a single chip Digit
35. ON The TDA9811 is an integrated circuit for multistandard vision IF signal processing and sound AM demodulation with single reference QSS IF in TV and VCR sets TDA9811 QSS Pagina 1 di 4 e g TDA9811R 23186 pit loop VIF input switch T filter IH AFC 23 video 1 V VIF AMPLIFIER AND INPUT SWITCH VIDEO CNES BUFFER 2 V V i vid SINGLE REFERENCE MIXER AND AM DEMODULATOR AF AMPLIFIER AF AM AND SWITCH INTERNAL VOLTAGE STABILIZER n c 1 2Vp A MHA046 CAGC VIL 5V 7 standard gt switch Switch 2nd SIF mute switch Vo QSS FUNCTIONAL DESCRIPTION Vision IF amplifier and input switch The vision IF amplifier consists of three AC coupled differential amplifier stages Each differential stage comprises a feedback network controlled by emitterdegeneration T The first differential stage is extended by two pairs of emitter followers to provide two IF input channels The VIF input can be selected by pin 30 Tuner and VIF AGC The AGC capacitor voltage is transferred to an internal IF control signal and is fed to the tuner AGC to generate the tuner AGC output current open collector output The tuner AGC takeover point can be adjusted This allows the tuner and the SWIF filter to be matched to achieve the optimum IF input level The AGC detector charges
36. Sc2 outR 51 VSSA4 50 VSSD2 19 5 1 5 1 outR VREF2 LC LC VSSA2 LC 42 41 VREF N 40 VREF P 2 2 Sc2InL 37 5 2 InR VSSD3 Scl InL Scl TDA 9875 RO RAZ 47K AK 1K 22 16V 4X C64 C 5 R65 2N2 2N2 10K KIA7812 R43 1K R66 10K Industrie Formenti Italia s p a Stabilimento di Sessa Aurunca CE Stereo Nicam per Telaio F19 Descr Cod Schema 511 055 05 07 2000 Data Sost schema Approvato 1 511 055 TOP eS 77 ose e C39 641 C45 15 prt 2 ES IO S s QZ Je e C68 C32 _t om de C62 1 1 2 1 E 1 4 1 5 1 5 1 7 1 8 1 3 1 10 1 1 12
37. TAL OSCILLATOR The digital controlled crystal oscillator is illustrated in Fig 8 see Chapter 12 The circuitry of the DCXO is fully integrated only the external 24 576 MHz crystal is needed E G Data creazione 01 11 99 17 27 26 30 F19MANU doc TEST PINS Both test pins are active HIGH in normal operation of the device they are wired to VSSD1 Test functions are for manufacturing tests only and are not available to customers Without external circuitry these pads are pulled down to LOW level with internal resistors POWER FAIL DETECTOR The power fail detector monitors the internal power supply for the digital part of the device If the supply has temporary been lower than the specified lower limit the power on reset bit POR transmitter register subaddress 0 will be set to HIGH The CLRPOR bit slave register subaddress 1 resets the power on reset flip flop to LOW If this is detected an initialization of the TDA9875A has to be carried out to ensure reliable operation LEVEL SCALING All input channels to the digital crossbar switch except for the loudspeaker feedback path are equipped with a level adjust facility to change the signal level in a range of 15 GB It is recommended to scale all input channels to 15 dB below full scale 15 dB full scale under nominal conditions NICAM PATH The NICAM path has a switchable J17 de emphasis FM AM PATH A high pass filter suppresses DC offsets from the FM demodulator due t
38. VREF P 39 VDEC2 38 Sc2InL 37 Sc2InR VSSD3 35 Scl Inl Scl 339 TDA 9870 1004H 820 8 n Ta sy s 12 ia ed RI2 4 615 AK K OK cis 470 10V C30 R3 R32 2N2 10K 10K KIA7812 CUFFIA Industrie Formenti Italia s p a Stabilimento di Sessa Aurunca CE Stereo Nicam i c per Telaio F19 Descr 531 015 Cod Schema 06 07 1999 Data 531 005 Sost schema Approvato lll 9 1 511 055 Vi AFC VCO1 VCO2 Cref GND CvAgc INSW 11 SIF2 TDA 9811 1004 16 NC 15 NC 14 NC 13 12 9 LSW CVBS 0 SID 99 CsAgcs 7 TAdj MFA Yoon 12K Cbl 3 VIF2 FOS2 K3953M IC2 178 08 5 C19 23 47K C22 C24 100 100N NICAM data 2 SCL SDA VSSAI1 VDEC1 IREF Port 1 10 SIF2 VREFI 12 SIFT 13 2C addr 2 14 VSSD1 15 VDDDI 16 RESET CAP 17 VSSD4 918 IN 19 XTAL OUT 20 PORT2 21 SYSCLK 222 SCK 223 WS 24 SDO2 25 SDOI 26 SOI2 27 28 TESTI 29 MONO IN TEST2 Ex InR 032 Ex InL VDDD2 4 9 Line outR 63 Line outl 62 o Main outl Main outR 60 9 VDDA359 e AUX outl 58 AUX oul 57 o VSSA3 56 9 55 e PCAPR54 9 VREF3 53 Sc2 outl 52
39. a large time constant has to be chosen which leads to slow AGC reaction at IF level change To speed up the AGC in case of IF signal jump from low to high level there is an additional comparator built in which can provide additional discharge current from the AGC capacitor up to 5 mA in a case of overloading the AM demodulator by the internal IF signal AM demodulator The IF amplifier output signal is fed to a limiting amplifier two stages and to a multiplier circuit However the limiter output signal which is not any more AM modulated is also fed to the multiplier which provides AM demodulation in phase demodulation After lowpass filtering fg 400 kHz for carrier rejection and buffering the demodulator output signal is present at pin 6 The AM demodulator operates over a wide frequency range so that in E ae ES open n pin 9 osed pin 7 AGC AGC CONTROL DETECTOR AF output 1 AM output AM input external input combination with frequency response of the IF amplifier applications in a frequency range from approximately 6 MHz up to 70 MHz are possible Audio switch This circuit is an operational amplifier with three input stages and internal feedback network determining gain 0 dB and frequency response fg 700 kHz Two of the input stages are connected to pin 7 and pin 9 the third input stage to an internal reference voltage Controlled by the switching pins 10 and 12 one of the three input stage
40. able errors are detected in any other Hamming checked data the byte is not written into the memory E G Data creazione 01 11 99 17 27 10 30 F19MANU doc Packet 26 processing One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set The family automatically decodes packet 26 data and if a character corresponding to that being transmitted is available in the character set automatically writes the appropriate character code into the correct location in the teletext memory This is not a full implementation of the packet 26 specification allowed for in level 2 teletext and so is often referred to as level 1 5 By convention the packets 26 for a page are transmitted before the normal packets To prevent the default character data overwriting the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten Fastext detection When a packet 27 designation code 0 is detected whether or not it is acquired the TXTI3 FASTEXT is set If the device is receiving 525 line teletext a packet X 0 27 0 15 required to set the flag The flag can be reset by writing a logic 0 into the SFR bit When a packet 8 30 is detected or a packet 4 30 when the device is receiving a 525 line transmission the TXT13 Pkt 8 30 is set The flag can be reset by writing a logic O into the SFR bit THE DISPLAY Introduction The capabilities of the display are based on the req
41. al Sound Processor DTVSP for analog and digital multi channel sound systems in TV sets and satellite receivers Supported standards The multistandard multi stereo capability of the TDA9875A is mainly of interest in Europe but also in Hong Kong Peoples Republic of China and South East Asia This includes B G D K 1 standard In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted M standard is transmitted in Europe by the American Forces Network AFN with European channel spacing 7 MHz VHF 8 MHz and monaural sound The AM sound of L L standard is normally demodulated in sound IF The resulting AF signal has to be entered into the mono audio input of the TDA9875A A second possibility is to use the internal AM demodulator stage however this gives limited performance Korea has a stereo sound system similar to Europe and is supported by the TDA9875A Differences include deviation modulation contents and identification It is based on M standard FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section SIF INPUT E G Data creazione 01 11 99 17 27 24 30 F19MANU doc Two input pins are provided SIF1 e g for terrestrial TV and SIF2 e g for a satellite tuner For higher SIF signal levels the SIF input can be attenuated with an internal switchable 10 dB resistor divider As no specific filters are integrated
42. al control circuit which is locked to the reference signal of the colour decoder When the IC is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all sub address bytes have been sent When the frequency of the oscillator is correct the horizontal drive signal is switched on To obtain a smooth switching on and switching off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch on and switch off slow start stop During that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage To protect the horizontal output transistor the horizontal drive is immediately switched off when a power on reset is detected The drive signal is switched on again when the normal switch on procedure is followed i e all sub address bytes must be sent and after calibration the horizontal drive signal will be released again via the slow start procedure When the coincidence detector indicates an out of lock situation the calibration procedure is repeated The circuit has a second control loop to generate the drive pulses for the horizontal driver stage The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time Via the 2 C bus adjustments can be made of the horizontal and vertical geometry The vertical sawtooth generator drives the vertical outpu
43. ard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver They provide control functions for the television system and include an integrated teletext function The teletext hardware has the capability of decoding and displaying both 525 line and 625 line World System Teletext The same display hardware is used both for Teletext and On Screen Display which means that the display features give greater flexibility to differentiate the TV set The family offers both 1 page and 10 page Teletext capability in a range of ROM sizes Increasing display capability is offered from the SAA5290 to the SAA5497 TELETEXT DECODER Data slicer E G Data creazione 01 11 99 17 27 9 30 F19MANU doc The data slicer extracts the digital teletext data from the incoming analog waveform This is performed by sampling the CVBS waveform and processing the samples to extract the teletext data and clock Acquisition timing The acquisition timing is generated from a logic level positive going composite sync signal VCS This signal is generated by a sync separator circuit which adaptively slices the sync pulses The acquisition clocking and timing are locked to the VCS signal using a digital phase locked loop The phase error in the acquisition phase locked loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected Teletext acquisition This family is capable of acquirin
44. ating with two supply voltages class G makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage Using this method very high efficiency is achieved The supply voltage VFB is almost totally available as flyback voltage across the coil this being possible due to the absence of a decoupling capacitor not necessary due to the bridge configuration The output circuit is fully protected against the following thermal protection e short circuit protection of the output pins pins 4 and 7 e short circuit of the output pins to A guard circuit VO guard is provided The guard circuit is activated at the following conditions e during flyback e during short circuit of the coil and during short circuit of the output pins pins 4 and 7 to VP or ground e during open loop e when the thermal protection is activated This signal can be used for blanking the picture tubescreen TDA8351 VERTICAL OUTPUT Pagina 2 di 2 e g TDA835IR drive pos drive neg PP VEB TDA8351 GND MBC988 1 PINNING SYMBOL PIN DESCRIPTION ldrive pos 1 input power stage positive includes liso signal bias ldrive neg 2 input power stage negative includes liso signal bias Vp 3 operating supply voltage 4 outpu
45. both inputs have the same specification giving flexibility in application The selected signal is passed through an AGC circuit and then digitized by an 8 bit ADC operating at 24 576 MHz AGC The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations For AM demodulation the AGC must be switched off When switched off the control loop is reset and fixed gain settings can be chosen from Table 15 subaddress 0 MIXER The digitized input signal is fed to the mixers which mix one or both input sound carriers down to zero IF A 24 bit control word for each carrier sets the required frequency Access to the mixer control word registers is via the 2 C bus When receiving NICAM programs a feedback signal is added to the control word of the second carrier mixer to establish a carrier frequency loop FM AND AM DEMODULATION An FM or AM input signal is fed via a band limiting filter to a demodulator that can be used for either FM or AM demodulation Apart from the standard fixed de emphasis characteristic an adaptive de emphasis is available for encoded satellite programs A stereo decoder recovers the left and right signal channels from the demodulated sound carriers Both the European and Korean stereo systems are supported FM IDENTIFICATION The identification
46. bypass not via the SC line memories is available When the signals do not pass the line memories the frequencyresponse is not affected by the si function SAA4981 16 9 TO 4 3 PROCESSOR Pagina 3 di 3 e g SAA4981R doc sampled video l l 1 49 us used for compression 1 3 us lt lt 52 7 Ei 1 lt 36 75 ps m 1 1 compressed video centre position zo EE 08 compressed video right position 7 compressed video left position bypassed video bypass via the Line Memories bypassed video full bypass not through the Line Memories 278 TDA4566 Colour transient improvement circuit GENERAL DESCRIPTION The TDA4566 is a monolithic integrated circuit for colour transient improvement and luminance delay line in gyrator technique in colour television receivers Features Colour transient improvement for colour difference signals R Y and B Y with transient detecting storage and switching stages resulting in high transients of colour difference output signals luminance signal path Y which substitutes the conventional Y delay coil with an integrated Y delay line Switchable delay time from 550 ns to 820 ns in steps of 90 ns and additional fine adjustment of 37 ns Two Y output signals one of 180 ns less delay TDA4566 CTI Pagina 1 di 1 e g TDA4566R
47. citor baseband delay circuit TDA4660 The IC incorporates HF and LF filters a demodulator and an identification circuit luminance is not processed in this IC The IC needs no adjustments and very few external components are required A highly stable reference frequency is required for calibration and a two level sandcastle pulse for blanking and burst gating FUNCTIONAL DESCRIPTION The TDA8395 is a self calibrating SECAM decoder designed for use with a baseband delay circuit During frame retrace a 4 433619 MHz reference frequencyis used to calibrate the filters and the demodulator Thereference frequency should be very stable during this period The Cloche filter is a gyrator capacitor type filter theresonance frequency of which is controlled during the calibration period and offset during scan this ensures thecorrect frequency during calibration The demodulator is a Phase Locked Loop PLL type demodulator which uses the frequency reference and the bandgap reference to force the PLL to the required demodulation characteristic The low frequency de emphasis is matched to the PLL and is controlled by the tuning voltage of the PLL Secam secoder TDA8395 Pagina di 2 e g TDA8395R CLOCHE I PLL 100 nF 220 BANDGAP INTERF ACE fret DENT SAND Fig 1 Block diagram CLOCHE ef 8 Y B Y 10 PINNING SYMBOL PIN DESCRIPTION fret IDENT 1 reference frequency input
48. dB resolution and treble is adjustable between 12 dB with 1 dB resolution For the purpose of a simple control software in the microcontroller the decimal number that is sent as an 2 C bus data byte for bass or treble is identical to the new bass or treble setting in dB e g the 2 C bus data byte 8 sets the new value to 8 dB The beeper provides tones in a range from approximately 400 Hz to 30 kHz The frequency can be selected via the 2 C bus The beeper output signal is added to the loudspeaker and headphone channel signals The beeper volume is adjustable with respect to full scale between 0 and 93 dB with 3 dB resolution The beeper is not effected by mute Soft mute provides a mute ability in addition to volume control with a well defined time 32 ms after which the soft mute is completed A smooth fading is achieved by a cosine masking SCART INPUTS The SCART specification allows for a signal level of up to 2 V rms Because of signal handling limitations due to the 5 V supply voltage of the TDA9875A it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input This results in a 3 dB SCART to SCART copy gain If 0 dB copy gain is preferred with maximum 1 4V input there are 3 dB O dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line E G Data creazione 01 11 99 17 27 29 30 F19MANU doc output The input attenuator is realized by an external series resistor in combinat
49. declines by secondary overloading Semiconductor Group 35 TDA 4605 Pin Definitions and Functions Pin No Function 1 Regulating Voltage Information input concerning secondary voltage By comparing the regulating voltage obtained from the regulating winding ot the transformer with the internal reference voltage the output impulse width on pin 5is adapted to the load ot the secondary side normal overload short circuit no load 2 Primary Current Simulation Information input regarding the primary current The primary current rise in the primary winding is simulated at pin 2 as a voltagerise by means ot external RC element When a value is reached that is derivedfrom the regulating voltage at pin 1 the output impulse at pin 5 is terminated TheRC element serves to set the maximum power at the overload point set 3 Input for Primary Voltage Monitoring In the normal operation V 3 is moving between the thresholds V V V3H gt gt V3L lt V 3L SMPS is switched OFF line voltage too low V 3 gt Compensation of the overload point regulation controlled by pin 2 starts at V 3H V3L 1 7 TDA4605 SMPS CONTRO LC Pagina 2 di 6 e g tda4605R doc 4 Ground 5 Output Push pull output provides 1 A for rapid charge and discharge of the gate capacitance ot the power MOS transistor 5 Supply Voltage Input A stable internal reference voltage V REF is derived from the supply voltage also the switching t
50. discharges the AGC capacitorto the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level Therefore for negative video modulation the sync level and for positive video modulation the peak white level of the video signal is detected In order to reduce the reaction time for positive modulation where a very large time constant is needed an additional level detector increases the discharging current of the AGC capacitor fast mode in the event of a decreasing VIF amplitude step The additional level information is given by the black level detector voltage Frequency Phase Locked Loop detector FPLL The VIF amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal After frequency lock in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter which controls the VCO frequency In the event of positive modulated signals the phase detector is gated by composite sync in order to avoid signal distortion for overmodulated VIF signals TDA9811 QSS Pagina 2 di 4 e g TDA9811R VCO Travelling Wave Divider TWD and AFC The VCO operates wi
51. doc a fine adjustment 0 37 switching voltage Ar 0 90 180 270 ns Vp 12V TDA4566 luminance input signal r CLAMPING GYRATOR DELAY CELLS 7 180 ns Y CIRCUIT 7 90 330nF Y output R Y 4 180 ns output DIFFERENTIATING SWITCHING 8 AND STORAGE STAGE F gt INTEGRATOR colour difference input signals STAGE PULSEFORMER SWITCHING DIFFERENTIATING 5 gt SPASE RE STAGE Y output 8 output 7222778 F19 amp 16 9 4 3 COMPRESSOR GYRATOR DELAY CELLS 7 x 90 ns INTEGRATOR amp PULSE FORMER 16 9 TO 4 3 SWITCH SIGNAL DUAL MONOSTABLE MULTIVIBRATOR IC 4 HEF 4538 us iH Pup idee c e FI9FEAT DRW E G 12 12 99 FORMENTI SCANNING SECTION TDA8351 DC coupled vertical deflection Circuit FEATURES Few external components Highly efficient fully DC coupled vertical output bridge circuit Vertical flyback switch Guard circuit Protection against e short circuit of the output pins 7 and 4 e short circuit of the output pins to VP e Temperature thermal protection e High EMC immunity because of common mode inputs A guard signal in
52. er as a reference The frequency setting for the various standards 33 4 33 9 38 38 9 45 75 and 58 75 MHz is realised via the 2 C bus To get a good performance for phase modulated carrier signals the control speed of the PLL can be increased by means of the FFI bit The AFC output is generated by the digital control circuit of the IF PLL demodulator and can be read via the 2 C bus For fast search tuning systems the window of the AFC can be increased with a factor 3 The setting is realised with the AFW bit The AFC data is valid only when the horizontal PLL is in lock SL 1 Depending on the type the AGC detector operates on top sync level single standard versions or on top sync and top white level multi standard versions The demodulation polarity is switched via the 2 C bus The AGC detector time constant capacitor is connected externally This mainly because of the flexibility of the application The time constant of the AGC system during positive modulation is rather long to avoid visible variations of the signal amplitude To improve the speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period When during 3 field periods no action detected the speed of the system is increased For signals without peak white information the system switches automatically to a gated black level AGC Because a black level clamp pulse is required for this way of operation the circuit
53. erential input signal voltage 1 Vi vIF2 2 differential input signal voltage 2 3 black level detector Vi viF3 4 VIF differential input signal voltage 3 Vi viFA 5 differential input signal voltage 4 TADJ 6 AGC takeover adjust TOP 7 PLL loop filter CsAGC 8 AGC capacitor STD 9 standard switch Vo cvBs 10 CVBS output signal voltage LSWI 11 L L accent switch Vo AF 12 AM audio voltage frequency output n c 13 not connected n c 14 not connected n c 15 not connected n c 16 not connected MUTE 17 mute n c 18 not connected TAGC 19 tuner AGC output Voass 20 single reference QSS output voltage 21 composite video output voltage 22 video buffer input voltage AFC 23 AFC output VCO1 24 VCO1 reference circuit for 2fpc VCO2 25 VCO2 reference circuit for 2fpc Cref 26 YoVp reference capacitor GND 27 ground 28 AGC capacitor Vp 29 supply voltage INSWI 30 VIF input switch Vi siF1 31 SIF differential input signal voltage 1 Vi SIF2 32 SIF differential input signal voltage 2 Vi SIF2 Vi VIF2 Vi SIF1 CBL INSWI Vi VIF3 Vp Vi VIF4 CvAGC TADJ 6 GND TPLL Cret 8 VCO2 TDA96811 STD 9 VCO1 Vo CVBS AFC LSWI Vi vid Vo AF Vo vid Vo 055 MUTE MHA047 Fig 2 Pin configuration TDA9830 TV sound AM demodulator and audio
54. et circuit is to initialize the teletext decoder when returning from the text standby mode TDA884X FAMILY SPECIFICATION FEATURES The following features are available in all IC s Multi standard vision IF circuit with an alignment freePLL demodulator without external components Alignment free multi standard FM sound demodulator 4 5 MHz to 6 5 MHz Audio switch e Flexible source selection with CVBS switch andY CVBS C input so that a comb filter can be applied Integrated chrominance trap circuit Integrated luminance delay line e Asymmetrical peaking in the luminance channel with a defeatable noise coring function e Black stretching of non standard CVBS or luminancesignals Integrated chroma band pass filter with switchablecentre frequency e Dynamic skin tone control circuit e Blue stretch circuit which offsets colours near whitetowards blue RGB control circuit with Continuous CathodeCalibration and white point adjustment e Possibility to insert a blue back option when no videosignal is available Horizontal synchronization with two control loops andalignment free horizontal oscillatoroptimised N2 application Functionally the IC series is split up is 3 categories viz E G Data creazione 01 11 99 17 27 13 30 F19MANU doc CVBS OUT Secam I xta Loop FO CVBS int IN CVBS Y IN comb filter Decoupling Atal filter R M NTI CVBS OUTPUT CVBS ext IN CHROMA IN SCL SDA P
55. f period of is rectified by D3 smoothed by 6 and stepped down adjustable ratio by R 5 R 6 and R7 The R 6 C 7 network suppresses parasitic overshoots transformer oscillation The peak voltage at pin 2 and thus the primary peak current is adjusted by the IC so that the voltage applied across the control winding and hence the output voltages are at the desired level When the transformer has supplied its energy to the load the control voltage passes through zero The IC detects the zero crossing via series resistors R 9 connected to pin 8 But zero crossings are also produced by transformer oscillation after T1 has turned off if output is short circuited Thereforethe IC ignores zero crossings occurring within a specitied period of time after T1 turn off The capacitor C 8 connected to pin 7 causes the power supply to be started with shorter pulses to keep the operating ftrequency outside the audible range during start up On the secondary side tive output voltages are produced across winding n 3 to n 7 rectified by D4 to 08 and smoothed by C 9 to C 13 Resistors 12 14 R 19 to R 21 are used as bleeder resistors Fusable resistors R 15 to A 18 protect the rectifiers against short circuits in the output circuits which are designed to supply only small loads TDA 4605 Block Diagram Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal reference voltage V R in the regulati
56. g 625 line and 525 line World System Teletext see World System Teletext and Data Broadcasting System Teletext pages are identified by seven numbers magazine page hundreds page tens page units hours tens hours units minutes tens and minutes units The last four digits hours and minutes are known as the subcode and were originally intended to be time related hence their names For the ten page device each packet can only be written into one place in the teletext RAM so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request At power up each page request defaults to any page hold on and error check Mode 0 Rolling headers and time When a new page has been requested it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page has been found Error checking Before teletext packets are written into the page memory they are error checked The error checking carried out depends on the packet number the byte number the error check mode bits in the page request data and the 1 8 BIT bit If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8 30 bit 4 of the byte written into the memory is set to act as an error flag to the software If uncorrect
57. ge The potential at pin 1 typically is 400 mV If the output is loaded the regulation amplifier allows broader impulses V 5 H The peak voltage value at pin 2 increases up to V 2S If the secondary load is further increased the overload amplifier begins to regulate the pulse width downward This point is referred to as the overload point of the power supply As the IC supply voltage V 6 is directly proportional to the secondary voltage it goes down in accordance with the overload regulation behaviour If V 6 falls below the value V 6 min the IC goes into burst operation As the time constant of the half wave charge up is relatively large the short circuit power remains small The overload amplifier cuts back to the pulse width pk This pulse width must remain possible in order to permit the IC to start up without problems from the virtual short circuit which every switching on with V 1 0 represents If the secondary side is unloaded the loading impulses V 5 H become shorter The frequency increases up to the resonance frequency of the system If the load is further reduced the secondary voltages and V 6 increase When V 6 V 6 the logic is blocked The IC converts to burst operation This renders the circuit absolutely safe under no load conditions TDA4605 SMPS CONTRO LC Pagina 6 di 6 e g tda4605R doc Regulation of the switched mode power supply is pin 1 The control voltage of winding n 1 during the of
58. hase O 6 Pu 6 Detector 17 1 10 35 TUNER AGC gating calibration LF value Y B Y R Y Y 32 N R Y P U 23 R T 24 G 25 B F B CON Black 0 Deenphasis Currente U gt 19 R T EXTERNAL AUDIO IN G 4 AVL 5 Decoupling Vertical Drive Output INTER mee 37 14 56 43 42 512 52 i i 1 i BandGap T 8V Sound T uU E i srt i i ilter DRIVE shes Decoupling Supply Supply Groun Decoupling Castle Vertical dixe s TDA8844BLDIA DRW filter 1 Out Sawtooth Reference E G 17 10 99 e Versions intended to be used in economy TV receiverswith all basic functions envelope S DIP 56 and QFP 64 e Versions with additional features like E W geometrycontrol H V zoom function and YUV interface which are intended for TV receivers with 110 picture tubes envelope S DIP 56 e Versions which have in addition a second RGB inputwith saturation control and a second CVBS output envelope QFP 64 Vertical count down circuit e Vertical driver optimised for DC coupled vertical outputstages GENERAL DESCRIPTION The various versions of the TDA 884X 5X series arel 2 C bus controlled single chip TV processors which are intended to be applied in PAL NTSC PAL NTSC and multi standard television receivers The N2 version is pin and application c
59. he same bandwidth for the luminance and chrominance signals up to 5 MHz SC line memories After the low pass filters the input signals are fed to the SC line memories The signals are sampled at a clock frequency of 13 5 MHz One video line later the signals are read with a clock frequency of 18 MHz in the compression mode The result of the different clock frequencies is a horizontal compression by a factor of 4 3 The clocks and the horizontal starting pulses for the SC line memories are fed from the controller Two line memories are required for each signal path because in the compression mode in one video line the signals are sampled to the SC line memories with 13 5 MHz and one video line later the signals are read with 18 MHz In the bypass mode via the SC line memories in one video line the signals are sampled with 13 5 MHz and one video line later the signals are read with 13 5 MHz The SC line memories are suitable for signals with a bandwidth up to 5 MHz With a multiplexer MUX behind the SC line memories the sampled video signal is connected to the internal post filters Output multiplexer MUX Y MUX B Y and MUX P Y SAA4981 16 9 TO 4 3 PROCESSOR Pagina 2 di 3 e g SAA4981R doc The output multiplexers are controlled and C2 fed from controller The multiplexers are used to connect one of the four input signals to the output and also enable fast switching The input signals of the multiplexers for one comp
60. hresholds V6A V6E V6 max and V6 min for the supply voltage detector If V6 gt V 6E then V REF is switched on and swiched off when V 6 lt V6A In addition the logic is only enable for V6 min V6 V6 max 7 Soft Start Input for soft start Start up will begin with short pulses by connecting a capacitor from pin 7 to ground 8 Zero Detector Input tor the oscillation feedback After starting oscillation every zero transit of the feedback voltage falling edge triggers an output impulse at pin 5 The trigger threshold is at 50 mV typical Semiconductor Group 36 TDA 4605 Application Circuit Application circuit shows a flyback converter for video recorders with a power rating of 50 W The circuit is designed as a wide range power supply tor AC line voltages ot 90 to 270 V The AC input voltage is rectified by bridge rectifier GR1 and smoothed by C 1 The NTC limits the rush in current In the period before the switch on threshold is reached the IC is supplied via resistor R 1 during the start up phase it uses the energy stored in C 2 under steady state conditions the IC receives its supply voltage from transformer winding n 1 via diode D1 The switching transistor T1 is a BUZ 90 The parallel connected capacitor C 3 and the inductance ot primary winding 112 determine the system resonance frequency The R 2 C 4 D2 circuitry limits overshoot peaks and R 3 protects the gate of against static charges While T1 conducts the curre
61. identification input TEST fet IDENT 3 16 5 V P TESTLZ SANO not connected 14 not connected 4 13 GND ground 0 8395 CLOCHE rer Cloche reference filter PLL reference GND CF n c output output PLtref R Y n c 11 not connected 13 not connected SAND 15 sandcastle pulse input Fig 2 Pin configuration CVBS 16 video chrominance input digital identification circuit scans the incoming signal for SECAM only line identification is implemented The identification circuit needs to communicate with theTDA8362 to guarantee that the output signal from the decoder is only available when no PAL signal has been identified If a SECAM signal is decoded a request for colour on is transmitted to pin 1 current is sunk If the signal request is granted e pin 1 is HIGH therefore no PAL the colour difference outputs B Y and P Y from the TDA8362 are high impedance and the output signals from the TDA8395 are switched ON If no SECAM signal is decoded during a two frame period the demodulator will be initialized before another attempt is made also during a two frame period The CD outputs will be blanked or high impedance depending on the logic level at pin 1 A two level sandcastle pulse generates the required blanking periods and also clocks the digital identificati
62. ideo Audio synchronisation process and chroma decoder see more detail at the TDA884x FAMILY SPECIFICATION paragraph and the Sound Processor TDA9875A that perform all sound function including digital decoding of NICAM signals see more detail at the TDA9870A amp tda9875A MAIN CHARACTERISTICS paragraph The above mentioned devices are driven by an Integrated Circuit that does include the microcontroller function with 64 K ROM and the TELETEXT acquisition and 8 pages RAM SAA5297A In the F19 chassis there are besides the stereo one two possible module that are performing FEATURES like picture in picture and or CTI colour transients improvement and 4 by 3 to 16 by 9 signal processing One further module is dedicated to the so called Zero Power Stand By A 26 Key Remote Control is performing the full control for the end used but can also be used in SERVICE MODE to control and adjust without open the back cover of the TV set all the necessary functions With the 5 LOCAL KEY BOARD button all the end user function can also be performed When the TV set is equipped with a PLL tuner the microcontroller recognise it and the tuning method became a frequency synthesis system if not it work as a voltage tuning system provided all necessary components are mounted The TV make use of a multilevel MENU activated both by the Remote Control and Local Keyboard using five selectable languages Italian German English France
63. ime is also set to fast controlled by the standard switch Single reference QSS mixer The single reference QSS mixer is realized by a multiplier The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier VCO The mixer output signal is fed via a high pass for attenuation of the video signal components to the output pin 20 With this system a high performance hi fi stereo sound processing can be achieved AM demodulator The AM demodulator is realized by a multiplier The modulated SIF amplifier output signal is multiplied in phase with the limited AM is removed SIF amplifier output signal The demodulator output signal is fed via an integrated low pass filter for attenuation of the carrier harmonics to the AF amplifier Internal voltage stabilizer and 1 22 VP reference The bandgap circuit internally generates a voltage of approximately 1 25 V independent of supply voltage and temperature A voltage regulator circuit connected to this voltage produces aconstant voltage of 3 6 V which is used as an internal reference voltage For all audio output signals the constant reference voltage cannot be used because large output signals are required TDA9811 QSS Pagina 4 di 4 e g TDA9811R PINNING SYMBOL PIN DESCRIPTION Vi vIF1 1 VIF diff
64. ion with the input impedance both of which form a voltage divider With this voltage divider the maximum SCART signal level of 2 V rms is scaled down to 1 4 V rms at the input pin EXTERNAL AND MONO INPUTS The 3 dB input attenuators are not required for the external and mono inputs because those signal levels are under control of the TV designer The maximum allowed input level is 1 4 V rms By adding external series resistors the external inputs can be used as an additional SCART input SCART OUTPUTS The SCART outputs employ amplifiers with two gain settings The gain can be set to 3 or to 0 dB the 2 C bus The 3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART to SCART copies with 0 dB gain be preferred under the condition of 1 4 V rms maximum input level 0 dB position is needed for example for an external to SCART copy with 0 dB gain LINE OUTPUT The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels This can be either an external signal that comes from the dual audio ADC or a signal from an internal digital audio source that comes from the dual audio DAC The line output employs amplifiers with two gain settings The 3 dB position is needed to compensate for the attenuation at the SCART inputs while the 0 dB position is needed for example for non attenuated external or internal digital signals see Section 6 3 4
65. istic As a result variations in the gain figures during life will be compensated by this 2 point loop An important property of the 2 point stabilisation is that the off set as well as the gain of the RGB path is adjusted by the feedback loop Hence the maximum drive voltage for the cathode is fixed by the relation between the test pulses the reference current and the relative gain setting of the 3 channels This has the consequence that the drive level of the CRT cannot be adjusted by adapting the gain of the RGB output stage Because different picture tubes may require different drive levels the typical cathode drive level amplitude can be adjusted by means of an 2 C bus setting Dependent on the chosen cathode drive E G Data creazione 01 11 99 17 27 21 30 F19MANU doc level the typical gain of the RGB output stages can be fixed taking into account the drive capability of the RGB outputs pins 19 to 21 More details about the design will be given in the application report The measurement of the high and the low current of the 2 point stabilisation circuit is carried out in 2 consecutive fields The leakage current is measured in each field The maximum allowable leakage current is 100 uA When the TV receiver is switched on the RGB output signals are blanked and the black current loop will try to set the right picture tube bias levels Via the AST bit a choice can be made between automatic start up or a start up the u p
66. itch configuration is identical to the switch of the TDA 8374 75 series So the circuit has one CVBS output amplitude of 2 VP P for the TDA884X series and the 2 C bus control is similar to that of the TDA 8374 75 For the TDA 885X IC s the video switch circuit has a second output amplitude of 1 VP P which can be set independently of the position of the first output The input signal for the decoder is also available on the CVBS1 output Therefore this signal can be used to drive the Teletext decoder If S VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again Sound circuit The sound bandpass and trap filters have to be connected externally The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator This PLL circuit tunes itself automatically to the incoming carrier signal so that no adjustment is required The volume is controlled via the 2 C bus The deemphasis capacitor has to be connected externally The non controlled audio signal can be obtained from this pin via a buffer stage The FM demodulator can be muted via the 2 C bus This function can be used to switch off the sound during a channel change so that high output peaks are prevented The TDA 8840 41 42 46 contain an Automatic Volume Levelling AVL circuit which automatically stabilises the audio output signal to a certain level which can be set by the
67. l It is optimized for the use of the horizontal decimation factor 3 1 A window signal derived from the sync pulses and the detected line standard defines the part of the active video area used for decimation For HSIDEL 0 the decimation window is opened about 104 clock periods 13 5 MHz after the horizontal synchronization pulse For the 625 lines standard the 36th video line is the first decimated line for the 525 lines standard decimation starts in the 26th video line The realized chrominance filtering allows omitting the color decoder delay line for PAL and SECAM demodulation if the color decoder supplies the same output voltages independent of the kind of operation In case of SECAM signals an amplification of the chrominance signals by a factor of 2 is necessary because just every second line a signal is present This chrominance amplification is programmable via pin SYS or I 2 C Bus AMSEC The horizontal and vertical decimation factors are free programmable DECHOR DECVER Using different decimations horizontal and vertical 16 9 applications become realizable DECHOR 4 DECVER 70 picture size 1 9 for 4 3 inset signals on 16 9 displays DECHOR 0 DECVER 1 picture size 1 16 for 16 9 inset signals on 4 3 displays PIP Field Memory The on chip memory stores one decimated field of the inset picture Its capacity is 169 812 bits The picture size depends on the horizontal and vertical decimation factors In fie
68. ld mode display just every second inset field is written into the memory in frame mode display the memory is continuously written Data are written with the lower inset clock frequency depending on the horizontal decimation factor 4 5 MHz or 3 375 MHz Normally the read frequency is 13 5 MHz and 27 MHz for scan conversion systems For progressive scan conversion systems and HDTV displays a line doubling mode is available LINEDBL Every line of the inset picture is read twice Memory writing can be stopped by program FREEZE a freeze picture display results one field Having no scan conversion and the same line numbers in inset and parent channel 625 lines or 525 lines both frame mode display is possible The result is a higher vertical and time resolution because of displaying every incoming field For this purpose the standards are internally analysed and activating of frame mode display is blocked automatically when the described restrictions are not fulfilled As in the inset channel a field number detection is carried out for the parent channel SDA 9288X P I P Pagina 3 di 4 e g sda9288xR doc Depending the phase between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter The display position of the inset picture is free programmable POSHOR POSVER The first possible picture position with
69. n 3 matrices are integrated Matrix selection is done by pin SYS or I 2 C Bus The matrices are designed for the following input voltages 100 white 75 color saturation SDA 9288X P I P Pagina 4 di 4 e g sda9288xR doc OUT OUT2 0115 SEL SELD VbDA1 Vss Von VSsa2 VREFH YIN Clamping Circuit Input Output UIN Signal Signal Triple Processing Processing VIN ADC VREFL Input Read Output Clock Write Clock Generator Controller Generator 27 MHz ADR Numerical PLL SW1 Sync Signal Processing SDA SCL SYS HVI VPD VI VP HP SCP Veg T XQ XIN UEB06157 Yop sm 2 Es 10 uH 33 uF I gt 0 75V without Syne 100 nF 10 nF 4 i 100 nF 10 nF t ME iN 100 nF 10 nF mae 3 gt oB 6800 6800 6800 SDA 9288 0 10 nF 12 50 60 Hz Blanking 5 for Parent Channel 13 100 120 Hz Fast Blanking FBL2 y Syne for Inset Channel 25 Switch Output 1 wo SWI INI 3 Level Signal for Inset Channel 24 Switch Output 2 gt o SW 21 SDA oy 22 gt o SCL 2 x Jumper 1 5 1 0 1 uF SSCss 10V H Sync for Parent Channel ones HP SCP ph 5 1V x 47 2 HPD SCI ion L
70. n the centre frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier frequencies All IC s have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level back porch The timeconstant for the black stretcher is realised internally The resolution of the peaking control DAC has been increased to 6 bits All IC s have a defeatable coringfunction in the peaking circuit Some of these IC s have a YUV interface see table on page 2 so that picture improvement IC s like the TDA 9170 Contrast improvement TDA 9177 Sharpness improvement and TDA 4556 66 CTI can be applied When the CTI IC s are applied it is possible to increase the gain of the luminance channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals are not affected Colour decoder Depending on the IC type the colour decoder can decode PAL PAL NTSC or PAL NTSC SECAM signals The PAL NTSC decoder contains an alignment free X tal oscillator a killer circuit and two colour difference demodulators The 90 phase shift for the reference signal is made internally The IC s contain an Automatic Colour Limiting ACL circuit which is switchable via the 2 C bus and which prevents that oversaturation occurs when signals with a high chroma to burst ratio are received The ACL circuit is designed such that it only reduces the chr
71. nance of side panels e Standard video inputs and outputs Y B Y and P Y Horizontal and vertical sync signals are not processed Pre filters and post filters on chip GENERAL DESCRIPTION The integrated 16 9 compressor is an IC which compresses the active part of a video line by a factor of 4 3 from for example 52 ms to 39ms This is necessary to display 4 3 video software on a 16 9 tube in the correctproportion The capacitively coupled video inputs are Y B Y and P Y The synchronisation input HREF is a line frequencyreference signal The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories Switched Capacitors Line Memories The output of the 16 9 compressor also has the format Y B Y and P Y and provides the following two possibilities 1 Bypass function the input signal is not compressed 2 Compressed video by a factor of 4 3 with three different fixed screen positions left centre and right The luminance and chrominance of the side panels are determined by the external signals YSIDE BYSIDE and RYSIDE The horizontal compression is a time discrete and amplitude continuous signal processing This provides pre and post filters which are realized on chip FUNCTIONAL DESCRIPTION SAA4981 16 9 TO 4 3 PROCESSOR Pagina 1 di 3 e g SAA4981R doc VEEA VEED SUB Vi 23 5 MHz LOW PASS FILTER SC LINE MEMORY SC LINE MEMORY
72. ng and overload amplifier The output of this stage is ted to the stop comparator Pin 2 A voltage proportional to the drain current ot the switching transistor is generated there by theexternal RC combination in conjunction with the primary current transducer The output of this transducer is controlled by the logic and referenced to the internal stable voltage V 2B If the voltage V 2 exceeds the output voltage of the regulating amplifier the logic is reset by the stop comparator and consequently the output ot pin 5 is switched to low potential Further inputs tor the logic stage are the output for the start impulse generator with the stable reference potential V ST and the supply voltage monitor TDA4605 SMPS CONTRO LC Pagina 4 di 6 e g tda4605R doc Reference Voltage typ 5 V Supply Voltage Monitor min Yen Vet Regulating amp Overload Amplitier Overload Point Correction Primary Current Reproducer Starting Impulse Generator Stop Comparator Voltage Protection Output Stage and Current Limit Zero Transit Detector 8 UEB00490 S M P S CONFIGURATION WITHOUT MAINS ISOLATED SECTOR ZERO POWER STAND BY MODULE line output stage gt 148 V 110 TR4 26V START UP sound power SOFTSTART x line driver 26 V ZERO CROSSING DETECTOR 12V signal gt processing s
73. ng the insertion of RGB signals the maximum vertical frequency is increased to 72 Hz so that the circuit can also synchronise on signals with a higher vertical frequency like VGA To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window by means of the NCIN bit The vertical deflection can be set in the de interlace mode via the 2 C bus To avoid damage of the picture tube when the vertical deflection fails the guard output current of the TDA 8350 51 can be supplied to the beam current limiting input When a failure is detected the RGB outputs are blanked and a bit is set NDF in the status byte of the 2 C bus When no vertical deflection output stage is connected thisguard circuit will also blank the output signals This can be overruled by means of the EVG bit Chroma and luminance processing The circuits contain a chroma bandpass and trap circuit The filters are realised by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the X tal frequency of the decoder The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits The centre frequency of the chroma bandpass filter is switchable via the 2 C bus so that the performance can be optimised for E G Data creazione 01 11 99 17 27 18 30 F19MANU doc front end signals and external CVBS signals During SECAM receptio
74. nput signal selector a PAL NTSC colour decoder horizontal and vertical synchronization and an RGB YUV switch The input signal selector has 2 CVBS inputs One of the inputs can be switched between CVBS and Y C and the circuit can automatically detect whether the incoming signal is CVBS or Y C The output signals for the PIP processor are e Luminance signal e Colour difference signals and V e Horizontal and vertical synchronization pulses e The RGB YUV switch can select between two RGB or YUV sources e g between the PIP processor and the SCART input signal e The supply voltage for the IC is 8 V Itis available a 52 SDIP package FUNCTIONAL DESCRIPTION CVBS switch The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y C The circuit contains an identification circuit which can automatically switch between the CVBS and Y C signals It is also possible to force the switch to CVBS or Y C TDA8310A CHROMA DECODER FOR Pagina 1412 e g TDA8310A doc Synchronization circuit The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level The sync pulses are fed to the slicing stage separator which operates at 50 of the amplitude The separated sync pulses are fed to the first phase detector and to the coincidence detector The coincidence detector is used to detect whether the line oscillator is synchronized and for t
75. nt rise in the primary winding depends on the winding s inductance and the V C1 voltage A voltage reproduction ot the current rise is tabbed using the R 4 C 5 network and forwarded into pin 2 ot the IC The RC time constant ot R4 R5 must be dimensioned correctly in order to prevent driving the transformer core into saturation The R 10 H 11 divider ratio provides the line voltage threshold controlling the undervoltage control circuit in the IC The voltage present at pin 3 also determines the overload Detection of overload together with the current characteristic at pin 2 controls the on period ot T1 This keeps the cut off point stable even with higher AC line voltages TDA4605 SMPS CONTRO LC Pagina 3 di 6 e g tda4605R doc Pin 3 The down divide primary voltage applied there stabilizes the overload point In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage V V in the primary voltage monitor block Pin 4 Ground Pin 5 In the output stage the output signals produced by the logic are shifted to a leved suitable for MOS power transistors Pin 6 From the supply voltage V 6 are derived a stable internal reference V REF and the switching threshold V 6A V6E V6 max and V 6 min for the supply voltage monitor All reference values V2B VST are derived from V REF If V6 gt VVE the V REF is switched and switched off when V 6 lt V6A In addition the logic is released only for V
76. ntrol mechanism in a television receiver They provide control functions for the television system OSD and some versions include an integrated data capture and display function The data capture hardware has the capability of decoding and displaying both 525 and 625 line World System Teletext WST Video Programming System VPS and Wide Screen Signalling WSS information The same display hardware is used both for Teletext and OSD which means that the display features available give greater flexibility to differentiate the TV set The SAA55xx standard family offers a range of functionality from non text 16 kbyte program ROM and 256 byte Random Access Memory RAM to a 10 page text version 64 kbyte program ROM and 1 2 kbyte RAM S 1 531 015 100 6V R4 47 u 100uH R5 P ace 390 E 470N 1 NICAM data 2 SCL SDA IREF Port 1 SIF2 VREF1 12C addr 2 VSSD1 VDDD1 RESET CAP VSSDA XTAL IN OUT PORT2 SYSCLK SCK Ws 5002 001 5012 SDI1 TESTI MONO IN TEST2 Ex InR Ex InL VDDD2 Line outR e Line 2 Main outl Main out 60 e VDDA3 59 AUX outL 58 AUX 57 VSSA3 56 PCAPL 55 PCAPR54 VREF3 53 5 2 outl 52 Sc2 outR VSSA4 VSSD2 5 outl 48 5 outR 47 VREF2 46 LC 45 LC VSSA2 LC 41 VREF N 40
77. o carrier frequency offsets and supplies the monitor peak function with DC values and an unfiltered signal e g for the purpose of carrier detection The de emphasis function offers fixed settings for the supported standards 50 us 60 us 75 us and J17 An adaptive de emphasis is available for Wegener Panda 1 encoded programs matrix performs the dematrixing of the A2 stereo dual and mono signals NICAM AUTO MUTE If NICAM B G 1 D K is received the auto mute is enabled and the signal quality becomes poor the digital crossbar switch switches automatically to FM and switches the matrix to channel 1 The automatic switching depends on the NICAM bit error rate The auto mute function can be disabled via the 2 C bus For NICAM L applications it is recommended to demodulate AM sound in the first sound IF and connect the audio signal to the mono input of the TDA9875A By setting the AMSEL bit subaddress 14 see Section 10 3 11 the auto mute function will switch to the audio ADC instead of switching to the E G Data creazione 01 11 99 17 27 27130 F19MANU doc first sound carrier The ADC source selector subaddress 23 see Section 10 3 20 should be set to mono input where the AM sound signal should be connected LOUDSPEAKER MAIN CHANNEL The matrix provides the following functions forced mono stereo channel swap channel 1 channel 2 and spatial effects There are fixed coefficient sets for spatial settings of 30 40 and 52 The
78. o choose this 4 X 0 value C1 for the 1 in service 5 X 0 mode 6 E E TXT W E TXT 1 64 7 CATV 1 128 If we want to change from West Europe character set to East Europe bit 6 became 0 that is the new value is 129 128 plus 1 that in hexadecimal format is 41 REMEMBER TO INSERT COUNTRY TABLE E G Data creazione 31 10 99 15 38 7 7 f19intro THE SECOND METHOD to enter service mode is to use the LOCAL KEY BOARD as describe here below 1 Starting from TV off press VOLUME on the LOCAL KEYBOARD in the mean time switch on the TV with the mains switch 2 Within three second switch on the TV using the SWITCH OFF button on the Remote Control 3 A small windows with black background and yellow characters will appear in the 4 Using the Remote control program top bottom will change the PARAMETER and the VOLUME left right will change the value 5 Each parameter can stored leaving the service mode by using the middle of the screen yellow button on the remote control 6 To leave SERVICE MODE without to store the new value use the TV button 7 lt is not necessary to store each value one by one this means that you can change all value you need and finally leave the SERVICE MODE pressing the YELLOW button MEM In the Table 3 we can find all parameter and related value to be seated Some parameter have to adjusted with a simple on off value others are just factory option and more
79. of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow band detection of the identification frequencies The result is available via the 2 C bus interface A selection can be made via the 2 C bus for B G D K and M standard and for three different modes that represent different trade offs between speed and reliability of identification NICAM DEMODULATION The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit s The NICAM demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock signal onto the NICAM decoder and for evaluation purposes to PCLK pin 1 and NICAM E G Data creazione 01 11 99 17 27 25 30 F19MANU doc pin 2 A timing loop controls the frequency of the crystal oscillator to lock the sampling rate to the symbol timing of the NICAM data NICAM DECODER The device performs all decoding functions in accordance with the EBU NICAM 728 specification After locking to the frame alignment word the data is descrambled by applying the defined pseudo random binary sequence the device will then synchronize to the periodic frame flag bit CO The status of the NICAM decoder can be read out from the NICAM status register by the user The OSB bit indicates that the decoder has locked to the NICAM data The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sound data The C4 bit indicates that the sound conve
80. oma signal and not the burst signal This has the advantage that the colour sensitivity is not affected by this function The SECAM decoder contains an auto calibrating PLL demodulator which has two references viz the 4 4 MHz sub carrier frequency which is obtained from the X tal oscillator which is used to tune the PLL to the desired free running frequency and the bandgap reference to obtain the correct absolute value of the output signal The VCO of the PLL is calibrated during each vertical blanking period when the IC is in search or SECAM mode The frequency of the active X tal is fed to the Fsc output pin 33 and can be used to tune an external comb filter e g the SAA 4961 base band delay line TDA 4665 function is integrated in the PAL SECAM IC s and in the NTSC IC TDA 8846A In the latter IC it improves the cross colour performance chroma comb filter The demodulated colour difference signals are internally supplied to the delay line The colour difference matrix switches automatically between PAL SECAM and NTSC however it is also possible to fix the matrix in the PAL standard E G Data creazione 01 11 99 17 27 19 30 F19MANU doc The blue stretch circuit is intended to shift colour near white with sufficient contrast values towards more blue to obtain a brighter impression of the picture Which colour standard the IC s can decode depends on the external X tals The X tal to be connected to pin 34 must have a fre
81. ompatible with the N1 version however a new feature has been added which makes the N2 more attractive The IF PLL demodulator has been replaced byan alignment free IF PLL demodulator with internal VCO no tuned circuit required The setting of the variousfrequencies 33 4 33 9 38 38 9 45 75 and 58 75 MHz can be made via the 2 C bus Because of this difference the N2 version is compatiblewith the N1 however N1 devices cannot be used in an optimized N2 application Functionally the IC series is split up is 3 categories viz e Versions intended to be used in economy TV receivers with all basic functions envelope S DIP 56 and QFP 64 e Versions with additional features like E W geometry control H V zoom function and YUV interface which areintended for TV receivers with 110 picture tubes envelope S DIP 56 e Versions which have in addition a second RGB input with saturation control and a second CVBS output envelope QFP 64 FUNCTIONAL DESCRIPTION Vision IF amplifier The IF amplifier contains 3 ac coupled control stages with a total gain control range which is higher then 66 dB The sensitivity of the circuit is comparable with that of modern E G Data creazione 01 11 99 17 27 14 30 F19MANU doc IF IC s The video signal is demodulated by means of an alignment free PLL carrier regenerator with an internalVCO This VCO is calibrated by means of a digital control circuit which uses the X tal frequency of the colour decod
82. on pulse on the falling edge of the burst gate pulse To enable The calibration period to be defined the vertical retrace is discriminated from the horizontal retrace this is achieved by measuring the width of the blanking period Secam secoder TDA8395 Pagina 2 di 2 e g TDA8395R TEA6415C BUS CONTROLLED VIDEO MATRIX SWITCH DESCRIPTION 20MHz BANDWIDTH CASCADABLE WITH ANOTHER TEA6415C INTERNAL ADDRESS BE CHANGED BY PIN 7VOLTAGE e INPUTS CVBS RGB CHROMA e POSSIBILITY OF MAC OR CHROMA SIGNAL e FOR EACH INPUT BY SWITCHING OFF THE e CLAMP WITH AN EXTERNAL RESISTOR BRIDGE e BUS CONTROLLED 6598 GAIN BETWEEN ANY INPUT AND OUT PUT e 55dB CROSSTALK AT 5MHz e FULLY ESD PROTECTED GENERALDESCRIPTION The mainfunctionof the IC is to switch 8 video input sources on 6 outputs Each output can be switched on only one of each input On each input an alignment of the lowest level of the signal is made bottom of synch top for CVBS or black level for RGB signals Each nominal gain between any input and output is 6 5dB For D2MAC or Chroma signal the align ment is switched off by forcing with an external resistor bridge 5 VDC on the input Each input can be used as a normal input or as a MAC or Chroma input with external resistor bridge All the switch ing possibilities are changed through the BUS Driving 75Q load needs an external transistor It is possible to have the same input connected to several
83. onent e The output signal of the post filter The uncompressed signal after the clamping e The clamping reference signal The signal for the side panel determined by YSIDE BYSIDE and RYSIDE The horizontal separation circuit The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal which is generated in the positive edge of the burst key of a sandcastle signal 54 MHz horizontal PLL The 13 5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL The 13 5 MHzclock and the 18 MHz clock are line locked Clamp reference Reference voltages are generated In the clamp reference block These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories Four external capacitors at the pins CLMY CLMBY CLMRY and BGREF respectively are necessary to provide smoothing for the reference voltages A black level reference signal is available at CLAOUT Controller The controller generates the clocks and the horizontal start signals for the SC line memories and also the control signals for the output multiplexers The timing for the start reading signal for three different screen positions centre and right and the control signals for the multiplexers C1 and C2 is fixed For the uncompressed signals a bypass via the SC line memories and a
84. others must be adjusted with value that are expressed in hexadecimal form ranging from 0 to FF that is from 0 to 63 in decimal form Table 3 represent the value to be assigned to three parameter to properly set options Table 3 Option bye 1 2 and 3 value and related meaning BIT 1 OPTIONB2 OPTIONB3 WEIGHT 0 1 0 1 0 1 0 2 SCART 1 MUST 1 BACKGROUND SVHS NTSC M UV1316 X V GUARD E E TXT W E TXT CATV E G Data creazione 31 10 99 15 38 f19intro A N PICTURE IN PICTURE MODULE SDA 9288X PICTURE IN PICTURE 1 General Description The Picture in Picture Processor SDA 9288X A141 generates a picture of reduced size of a video signal inset channel for the purpose of combining it with another video signal parent channel The easy implementation of the IC in an existing system needs only a few additional external components There is a great variety of application facilities professional and consumer products TV sets supervising monitors multi media Data Sheet e 212 luminance and 53 chrominance pixels per inset line for picture size 1 9 e 6 bit amplitude resolution for each incoming signal component e Field and frame mode display e Horizontal and vertical filtering e Special antialias filtering for the luminance signal 16 9 compatibility e Operation in 4 3 and 16 9 sets e 4 3 inset signals on 16 9 displays or v v with picture size 1 9 and 1 16 respec
85. out frame is 54 clock periods 13 5 MHz or 27 MHz after the horizontal and 4 lines after the vertical synchronization pulses Starting at this position the picture can be moved over the whole display area Even POP positions Picture Outside Picture at 16 9 applications are possible Horizontal Decimation PIP PIXELS per Line Having different line standards in inset and parent channels we have a so called mixed mode display It causes deformations in the aspect ratio of the inset picture A special mixed mode display is available for the picture size 1 9 MIXDIS Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals in the same way as described for the inset channel The synchronization signals are fed to the IC at pin HP SCP for horizontal synchronization and pin VP for vertical synchronization In the same way as described for the inset channel the burst gate of the sandcastle signal can be used for horizontal synchronization In scan conversion systems also the inputs HPD SCI and VPD VI are available if the input HVI is activated for inset synchronization 2 4 Output Signal Processing At the memory output the chrominance components are demultiplexed and linearly interpolated to the luminance sample rate Different output formats are available luminance signal Y with inverted or non inverted chrominance signals B Y R Y or RGB For the RGB conversio
86. outputs The starting configuration upon power on power supply 0 to 10V is undetermined In this case 6 words of 16 bits are necessary to determine one configuration In other case 1 word of 16 bits is necessary to determine one configura tion TEA6415C video matrix switch Pagina 1 di 1 e g TEA6415C doc TDA4665 Baseband delay line FEATURES Two comb filters using the switched capacitor technique for one line delay time 64 ms e Adjustment free application No crosstalk between SECAM colour carriers diaphoty e Handles negative or positive colour difference input signals Clamping of AC coupled input signals P Y and B Y VCO without external components 3 MHz internal clock signal derived from a 6 MHz line locked by the sandcastle pulse 64 ms line Sample and hold circuits and low pass filters to suppress the 3 MHz clock signal e Addition of delayed and non delayed output signals Output buffer amplifiers Comb filtering functions for NTSC colour difference signals to suppress cross colour GENERAL DESCRIPTION The TDA4665 is an integrated baseband delay line circuit with one line delay It is suitable for decoders with colour difference signal outputs P Y and B Y PINNING COLI 5 supply voltage for digital part TDA4665 Crhroma Delay line Pagina 1 di 3 e g TDA4665 doc R Y 4 colour difference input signals sandcastle pulse input SIGNAL CLAMPING
87. quency of 3 5 MHz NTSC M PAL M or PAL N and pin 35 can handle X tals with a frequency of 4 4 and 3 5 MHz Because the X tal frequency is used to tune the line oscillator the value of the X tal frequency must be given to the IC via the 2 C bus It is also possible to use the IC in the so called Tri norma mode for South America In that case one X tal must be connected to pin 34 and the other 2 to pin 35 The switching between the 2 latter X tals must be done externally This has the consequence that the search loop of the decoder must be controlled by the To prevent calibration problems of the horizontal oscillator the external switching between the 2 X tals should be carried out when the oscillator is forced to pin 34 For a reliable calibration of the horizontal oscillator it is very important that the X tal indication bits XA and XB are not corrupted For this reason the X tal bits can be read in the output bytes so that the software can check the 2 C bus transmission Under bad signal conditions e g VCR playback in feature mode it may occur that the colour killer is activated although the colour PLL is still in lock When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO bit Forced Colour On in the control 5 subaddress The IC s contain a so called Dynamic skin tone flesh control feature This function is
88. ransmitter identification The first PLL has a very high static steepness this ensures that the phase of the picture is independent of the line frequency The line oscillator operates at twice the line frequency The oscillator network is internal Because of the spread of internal components an automatic adjustment circuit has been added to the IC The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder This results in a free running frequency which deviates less than 2 from the typical value The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper The pulse width of the output pulse is 5 4 ms the front edge of this pulse coincides with the front edge of the sync pulse at the input The vertical output pulse is generated by acount down circuit The pulse width is approximately 380 ms Both the horizontal and vertical output pulses will always be available at the outputs even when no input signal is available In addition to the horizontal and vertical sync pulse outputs the IC has a sandcastle pulse output which contains burst key and blanking pulses Integrated video filters The circuit contains a chrominance bandpass and trap circuit The filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder When a Y C signal is supplied to the input the chrominance trap is automatically s
89. responding to the chassis to be programmed and at the same time press the button Read for a while corresponding LED will be on When the LED Write became off after few seconds disconnect the Black Box Insert the Black Box in the new TV set in stand by condition Press F19 and Write buttons at same time Corresponding Write LED will light After few seconds when the Write LED will switch off the procedure is finished o Ngo Repeat points from 6 to 8 to program others TV set WARNING The above procedure can be applied only to TV set specially prepared for this functions E G Data creazione 31 10 99 15 38 6 7 f19intro Table 4 List of languages that can be reproduced a function of the TXT characters set setting with the optionb1 bit number 6 WEST EUROPE CHARACTER SET EAST EUROPE CHARACTER SET LANGUAGES LANGUAGES ENGLISH POLISH GERMAN GERMAN SWEDISH ESTONIA ITALIAN SERB CROAT FRENCH CZECH SPANISH RUMEN TURKISH Just to give an example how to set the option byte 1 2 and 3 we can start from a TV set for BG standard with hyperband tuner to be sold in a country using West European character set Locking at the table 3 Optionb1 we have the following condition BIT OPTIONB1 NUMBER 0 1 VALUE WEIGHT 0 1 1 Adding value of the last column we get 193 1 0 in decimal form and C 2 0 in hexadecimal This means that we 3 0 have t
90. rocessor In the automatic mode the RGB drive signals are switched on as soon as the black current loop has been stabilised In the other mode the BCF bit is set to 0 when the loop is stabilised The RGB drive can than be switched on by setting the AST bit to 0 In the latter mod some delay can be introduced between the setting of the BCF bit and the switching of the AST bit so that switch on effects can be suppressed It is also possible to start up the devices with a fixed internal delay as with the TDA 837X and the TDA884X 5X N1 This mode is activated with the BCO bit The vertical blanking is adapted to the incoming CVBS signal 50 Hz or 60 Hz When the flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking can be increased to the same value as that of the 50 Hz blanking This can be set by means of the LBM bit For an easy manual adjustment of the Vg2 control voltage the VSD bit is available When this bit is activated the black current loop is switched off a fixed black level is inserted at the RGB outputs and the vertical scan is switched off so that a horizontal line is displayed on the screen This line can be used as indicator for the Vg2 adjustment Because of the different requirements for the optimum cut off voltage of the picture tube the RGB output level is adjustable when the VSD bit is activated The control range is 2 5 0 7 V and be controlled via the brightness control DAC It is po
91. s can be activated and a choice made between two different AF signals or mute state The selected signal is present at pin 8 The decoupling capacitors at the input pins are needed because the internally generated bias voltage for the input stages must not be influenced by the application in order to avoid DC plop in case of switching The AM demodulator output is designed to provide almost the same DC voltage as the input bias voltage of the audio switch But there may be spread between both voltages Therefore it is possible to connect pin 6 directly to pin 7 without a decoupling capacitor but in this event the DC plop for switching can increase up to 100 mV Reference circuit This circuit is a band gap stabilizer in combination with a voltage regulation amplifier which provides an internal reference voltage of about 3 6 V nearly independent from supply voltage and temperature This reference voltage is filtered by the capacitor at pin 4 in order to reduce noise It is used as a reference to generate all important voltages and currents of the circuit For application in 12 V power supply concepts there is an internal voltage divider in combination with a Darlington transistor in order to reduce the supply voltage for all IC function blocks to approximately 6 V This is necessary because of use of modern high frequency IC technology where most of the used integrated components are only allowed to operate at maximum 9 V supply voltage
92. signal of the inset channel If the burst gate pulse of the sandcastle is used it must be adapted to TTL compatible levels by a simple external circuit Centering of the displayed picture area is possible by a programmable delay for the horizontal synchronization signal HSIDEL The inset horizontal synchronization signals are sampled with 27 MHz This 27 MHz clock and the AD converter clocks are derived from the parent horizontal synchronization pulse or from the quartz frequency converted by a factor of 4 3 Delay differences between luminance and chrominance signals at the input of the IC caused by chroma decoding are compensated by a programmable luminance delay line YDEL of about 290 ns 740 ns at decimation input By analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed For applications with fixed line standard only 625 lines or 525 lines the automatic detection can be switched off The phase of the vertical sync pulse is programmable VSIDEL VSPDEL By this way a correct detection of the field number is possible an important condition for frame mode display Input Signal Processing SDA 9288X Pagina 2 di 4 e g sda9288xR doc This stage performs the decimation of the inset signal by horizontal and vertical filtering and sub sampling A special antialias filter improves the frequency response of the luminance channe
93. ssible to insert a so called blue back back ground level when no video is available This feature can be activated via the BB bit the control2 subaddress E G Data creazione 01 11 99 17 27 22 30 F19MANU doc FOR VOLTAGE SINTHESIS ONLY FORMENTI Li F19 27 gt L TR202 TO PIN 33 FROM IC 100 1 100 PIN 14 20 21 CVBS BAND SWITCHING FOR TXT TO PIN 24 TR203 100 4 CVBS FOR TXT TO PIN 9 IC 100 TR204 AVI A STATUS FROM PIN 6 1 100 AV1 AV2 SWITCH TR212 CVBSI CVBS OUT FROM PIN 52 IC 100 4 3 TO 16 9 1 3 0F IC201 LA7955 A AVIATS ERE CVBS IN SWITCH IC 100 VIDEO SIGNAL PATH RGB AMPLIFIER 12V 200 V A 3 1 N R17 R18 R19 RGB IN FROM SCART R600 2 6 11 14 Da D800 D801 D802 TO G1 TRC 9 12 15 4 5112 19 RGBCO DRW E G 14 11 99 FORMENTI 19 FEATURE MODULE Colour Transient Improvment amp 4 3 to 16 9 Signal Processing SAA4981 Monolithic integrated 16 9 Compressor FEATURES e Fixed horizontal compression by a factor of 4 93 for most video standards e Three fixed screen positions left centre and right e 5 MHz bandwidth Bypass function e Inputs for luminance and chromi
94. t drive circuit which has a differential output current For the E W drive a single ended current output is available A special E G Data creazione 01 11 99 17 27 17 30 F19MANU doc feature is the zoom function for both the horizontal and vertical deflection and the vertical scroll function which are available in some versions When the horizontal scan is reduced to display 4 3 pictures on a 16 9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen Overvoltage conditions X ray protection can be detected via the EHT tracking pin When an overvoltage condition is detected the horizontal output drive signal will be switched off via the slow stop procedure but it is also possible that the drive is not switched off and that just a protection indication is given in the 2 C bus output byte The choice is made via the input bit PRD The IC s have a second protection input on the 2 filter capacitor pin When this input is activated the drive signal is switched off immediately and switched on again via the slow start procedure For this reason this protection input can be used as flash protection The drive pulses for the vertical sawtooth generator are obtained from vertical countdown circuit This countdown circuit has various windows depending on the incoming signal 50 Hz or 60 Hz and standard or non standard The countdown circuit can be forced in various modes by means of the 2 C bus Duri
95. t voltage B GND 5 ground VFB 6 input flyback supply voltage Vo A 7 output voltage Vo guard 8 guard output voltage 9 input feedback voltage drive pos drive neg GND TDA8351 MBC989 FORMENTI HEATER VOLTAGE L __ VIDEO SUPPLAY LINE 18 BUS08D e PIN22 PIN 50TDA8844 EHT P SERVICE FLYBACK PULSE TO PIP TUNING mum OSD SYNC 16 V C51 BUK474 6 PIN3 I TDA835 www F19 VERTICAL amp LINE OUTPUT YOKE PLUS E W CORRECTION FORMENTI CVBS amp INTERCARRIER OUT TR202 TR201 TR210 FROM PIN8 IC 100 SCART CINCH SWITCH AUDIO CINCH IN 200 2 3 HEF 4053 FROM PIN 12 28 V IC100 AUDIO OUT SAAS297A TR575 TR209 F19 AUDIO MONO SIGNAL PATH ad 29 12799 TDA 9870 8 TDA9875A MAIN CHARACTERISTICS FEATURES Demodulator and decoder section Sound IF SIF input switch e g to select between terrestrial TV SIF and SAT SIF sources SIF AGC with 24 dB control range SIF 8 bit Analog to Digital Converter ADC DQPSK demodulation for different standards simultaneously with 1 channel FM demodulation NICAM decoding B G and L standard Two carrier multistandard FM demodulation B G D K and M standard Decoding for three analog multi channel systems A2 A2 and 2 and satellite sound Optional AM demodulation for system
96. t6 The feedback to pin 8 starts the next impulse and so impulses including the starting impulse are TDA4605 SMPS CONTRO LC Pagina 5 di 6 e g tda4605R doc controlled in width by regulating voltage of pin 1 When switching on this corresponds to short circuit event i e V 1 0 Hence the IC starts up with short circuit impulses to assume a width depending on the regulating voltage feedback the IC operates in the overload range The maximum pulse width is reached at time point 2 V 2 V2 max The IC operates at the overload point Thereafter the peak values ot V 2 decrease rapidly as the IC is operating within the regulation range The regulating loop has built up If voltage V 6 falls below the switch off threshold V 6 min before the reversal point is reached the starting attempt is aborted pin 5 is switched to low As the IC remains switched on V 6 further decreases to V6 The IC switches off V 6 can rise again time point 14 and a new start up attempt begins at time point 1 If the rectified alternating line voltage primary voltage collapses during load V can fall below V is happening at time point t3 switch on attempt when voltage is too low The primary voltage monitor then clamps V to V 3S until the IC switches off V 6 lt V6A Then a new start up attempt begins at time point t Regulation Overload and No Load Behaviour When the IC has started up it is operating in the regulation ran
97. tand by SMPS CONTR 1 TDA 4605 gt 8 5v 5V 1 ww FROM PIN 190FF IC Mom gt TRG SAAS29f N SUPPLY VOLTAGE 5 PRIMARY ADJUSTMENT SENSING PROTECTION 7 11 99 F19SMPS DRW gt line output stage F 1 9 148 V 110 TR4 26 V LOW POWER ats STAND BY line CONFIGURATION 12 V signal 5V processing stand by FROM PIN 19 gt 110 85 ini MAINS TO MAIN BOARD FI9LPSBC DRW EG 14 11 99 FORMENTI F19 SERVICE MODE REMOTE CONTRO DIGICOMPUTER 25 REMOTE 26 For the description of use of the TV make use of the Instruction Manual Service mode As already mentioned in the summary the remote control can be used to set all parameter and to adjust the TV set without to open the back cover There are two ways to enter the SERVICE MODE that are to use the LOCAL KEYBOARD or to have a precial prepared REMOTE CONTROL FIRST METHOD If the special remote control is available use the button following the indication of the Table 1 Table 1 List of command of the SERVICE REMOTE CONTROL BUTTON 5 Sub Decimal Coce Function System 0 0 0 Vertical Slope 1 0 1 Vertical Amplitude Vertical Shift Vertical S Correctio Horizontal Shift HorizontalAmplitude E W parabola E W Corner E W Trapezium AGC 5 6 7 8
98. th a resonance circuit with L and C in parallel at double the PC frequency The VCO is controlled by two integrated variable capacitors The control voltage required to tune the VCO from its free running frequency to actually double the PC frequency is generated by the frequency phase detector and fed via the loop filter to the first variable capacitor FPLL This control voltage is amplified and additionally converted into a current which represents the AFC output signal The VCO centre frequency can be decreased required for L accent standard by activating an additional internal capacitor This is achieved by using the L accent switch In this event the second variable capacitor can be controlled by a variable resistor at the L accent switch for setting the VCO centre frequency to the required L accent value At centre frequency the AFC output current is equal to zero The oscillator signal is divided by two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency Video demodulator and amplifier The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth The vision IF input signal is multiplied with the in phase signal of the travelling wave divider output In the demodulator stage the video signal polarity can be switched in accordancewith the TV standard The demodulator output signal is fed via an integrated low pass filter
99. tively Analog inputs e Y B Y R Y or Y R Y Analog outputs e Y B Y R Y or Y B Y R Y or RGB 3 RGB matrices EBU NTSC Japan NTSC USA Free programmable position of inset picture e Steps of 1 pixel and 1 line All PIP and POP positions are possible 2 picture sizes e 1 9 or 1 16 of normal size High resolution display 13 5 MHz 27 MHz display clock frequency Freeze picture I 2 C Bus control SDA 9288X P I P Pagina 1 di 4 e g sda9288xR doc Threefold PIP POP facility e Three different I 2 C addresses pin programmable System Description AD Conversion Inset Synchronization The inset video signal is fed to the SDA 9288X A141 as analog luminance and chrominance components 1 The polarity of the chrominance signals is programmable After clamping the video components are AD converted with an amplitude resolution of 6 bit The conversion is done using a 13 5 MHz clock for the luminance signal and a 3 375 MHz clock for the chrominance signals For the adaption to different application the clamp timing for the analog inputs can be chosen CLPS CLPFIX Setting this bits to 1 can be useful for non standard input signals For inset synchronization it is possible to feed either a special 3 level signal via pin detection of horizontal and vertical pulses or separate signals via pins SCI for horizontal and VI for vertical synchronization SCI is the horizontal synchron
100. uirements of level 1 teletext with some enhancements for use with locally generated on screen displays The display consists of 25 rows each of 40 characters with the characters displayed being those from rows 0 to 24 of the basic page memory If the TXT7 STATUS ROW TOP bit is set row 24 is displayed at the top of the screen followed by row 0 but normally memory rows are displayed in numerical order The teletext memory stores 8 bit character codes which correspond to a number of displayable characters and control characters which are normally displayed as spaces The character set of the device is described in more detail below E G Data creazione 01 11 99 17 27 11 30 F19MANU doc SEIECO es 82 OPTION BYTE 1 BIT 3 SETTED TO 0 EAST EUROPE CHARACTER SET NATIONAL OPTION FOR POLISH GERMAN ESTONIAN SERBO CROAT CZECH SLOVAKIA RUMANIAN WEST EUROPE CHARACTER SET NATIONAL OPTION FOR WEST EAST ENGLISH GERMAN e SWEDISH ITALIAN FREANCH SPANISH TURKISH OPTION BYTE 1 BIT 6 SETTED TO 1 7 11 99 Character matrix Each character is defined by a matrix 12 pixels wide and 10 pixels high When displayed each pixel is 1 12 s wide and 1 TV line in each field high East West selection In common with their predecessors these devices store teletext pages as a series of 8 bit character codes which are interpreted as either control codes to change colour invoke flashing etc
101. witched off by the Y C detection circuit however it is also possible to force the filters in the CVBS or Y C position The luminance delay line is also realised by gyrator circuits Colour decoder The colour decoder contains an alignment free crystal oscillator a colour killer circuit and colour difference demodulators The 90 phase shift for the reference signal is achieved internally The colour decoder is very flexible Together with the SECAM decoder TDA8395 an automatic multistandard decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the IC The decoder can be forced to one of the standards via the forced mode pins The crystal pins which are not used must be connected to the positive supply line a 8 2 Q resistor Itis also possible to connect the non used pins with one resistor to the positive supply line In this event the resistor must have a value of 8 2 divided by the number of pins The chrominance output signal of the video switch is externally available and must be used as an input signal for the SECAM decoder RGB YUV switch The RGB YUV switch is for switching between two RGB or YUV video sources The outputs of the switch can be set to high impedance state so that other switches can be used in parallel The switch is controlled via pins 13 and 52 TDA8310A CHROMA DECODER FOR PIP Pagina 2 di 2 e g TDA8310A doc
102. yed by the FM mono channel is identical to the sound conveyed by the NICAM channel The error byte contains the number of sound sample errors resulting from parity checking that occurred in the past 128 ms period NICAM AUTO MUTE This function is enabled by setting bit AMUTE LOW subaddress 14 Upper and lower error limits may be defined by writing appropriate values to two registers in the 2 C bus section subaddresses 16 and 17 When the number of errors in a 128 ms period exceeds the upper error limit the auto mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier FM or AM When the error count is smaller than the lower error limit the NICAM sound is restored The auto mute function can be disabled by setting bit AMUTE HIGH In this condition clicks become audible when the error count increases the user will hear a signal of degrading quality A decision to enable disable the auto muting is taken by the microcontroller based on an interpretation of the application control bits C1 C2 C3 and C4 and possibly any additional strategy implemented by the set maker in the microcontroller software For NICAM L applications it is recommended to demodulate AM sound in the first sound IF and connect the audio signal to the mono input of the TDA9875A By setting the AMSEL bit subaddress 14 the auto mute function will switch to the audio ADC instead of switching to the first sound carrier CRYS

F 19 SERVICE MANUAL

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