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User Manual TPMC670

1. 9 4 1 PCI9030 Local Space Configuration U U u u u nnns u 9 4 2 Local Register Space Address Map U U U U U u u u uu u 9 4 2 1 Data Output netten renes nn nnne ns 10 4 2 2 Data Input Register ener ener entren renes nn 11 4 2 3 Control Status Register sse enne nnne nnns nnne ns 12 4 2 4 Rising Edge Interrupt Enable 13 4 2 5 Falling Edge Interrupt Enable Register 14 426 Rising Edge Interrupt Status 15 427 Falling Edge Interrupt Status Register 1000 16 4 2 8 Debounce Time 444 17 5 8030 TARGET CHIP dandas rrr 19 5 1 PCI Configuration Registers PCR u u u u uu u u J 19 5 1 wauu 19 5 1 2 PCI Base Address InitialiZation 20 5 2 Local Configuration Register _ 21 5 3 Config r tion IU sassa err 22 5 4 Local Softwa
2. 9030 LOCAL SPACE 9 FIGURE 42 FPGA REGISTER SPACES uuu u gun etti n ra ree ret 9 FIGURE 43 DATA OUTPUT REGISTER u ttr the treten rtu unte vu ne eda Ru ev Peu vd 10 FIGURE 4 4 DATA INPUT REGISTER eiae indi qq ue ea 11 FIGURE 4 5 CONTROL STATUS 77 12 FIGURE 4 6 RISING EDGE INTERRUPT ENABLE 2 13 FIGURE 4 7 FALLING EDGE INTERRUPT ENABLE 14 FIGURE 4 8 RISING EDGE INTERRUPT STATUS 15 FIGURE 4 9 FALLING EDGE INTERRUPT STATUS REGISTER seen 16 FIGURE 4 10 DEBOUNCE TIME 5 17 FIGURE 4 11 FORMULAS TO DETERMINE PRELOAD nemen 17 FIGURE 4 12 DEBOUNCE TIME 18 FIGURE 5 1 PGCI9030 HEADER ttr CO 19 FIGURE 5 2 9030 PLD BASE ADDRESS 05 20 FIGURE 5 3 9030 LOCAL CONFIGURATION REGISTER esent 21 FIGURE 5 4 CONFIGURATION EEPROM 6 777 22 FIGURE 6 1 LOCAL BUS LITTLE BIG 24 FIGURE 7 1 INPUT WIRING uu ae 26 FIGURE 7 2 OUTPUT WIRING HIGH SIDE 26 FIGURE 7 3 OUTPUT WIRING LOW SIDE 26 FIG
3. to the corresponding bit 10 OUTPUT11 9 OUTPUT10 0 inactive 8 OUTPUT9 1 active R W 0 0000 7 OUTPUT8 6 OUTPUT7 5 OUTPUT6 Bit 0 represents output line 1 and bit 15 represents 4 OUTPUTS Output line 16 After power on or reset the Data Output Register is 3 OUTPUTA cleared to 0 all outputs are inactive 2 OUTPUTS 1 OUTPUT2 0 OUTPUT1 Figure 4 3 Data Output Register TPMC671 User Manual Issue 1 1 Page 10 of 28 TEWS S TECHNOLOGIES 4 2 2 Data Input Register The Data Input Register is a word wide read only register that reflects the actual status of the inputs Bit Symbol Description Access Reset Value 15 INPUT16 14 INPUT15 13 INPUT14 12 INPUT13 11 INPUT12 10 INPUT11 0 Input line is logic low 9 DTE 1 Input line is logic high 8 INPUT9 R _ 7 INPUT8 6 INPUT7 Bit 0 represents Input Line 1 and bit 15 represents the 5 INPUT6 Input Line 16 4 5 3 INPUT4 2 INPUT3 1 INPUT2 0 Figure 4 4 Data Input Register 671 User Manual Issue 1 1 Page 11 of 28 TEWS TECHNOLOGIES 4 2 3 Control Status Register The Control Status Register is a read write register Bit Symbol Description Access Reset Value 15 4 Not used and undefined during reads 3 WD STA Watchdog Status Flag R W 0 1 indicates that the watchdog had recognized a failure and had disabled a
4. 9030 Local Space 0 Used 0x1G PC19030 Local Space 1 Not used 0x30 Expansion ROM Not used Figure 5 2 PCI9030 PLD Base Address Usage 671 User Manual Issue 1 1 Page 20 of 28 TEWS TECHNOLOGIES 5 2 Local Configuration Register LCR After reset the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI 1 Space Offset 0x14 in the PCI9030 PCI Configuration Register Space Do not change hardware dependent bit settings in the PCI9030 Local Configuration Registers Offset from Register Value PCI Base Address 0x00 Local Address Space 0 Range OxOFFF FFF1 0x04 Local Address Space 1 Range 0x0000 0000 0x08 Local Address Space 2 Range 0x0000 0000 0x0G Local Address Space 3 Range 0x0000_0000 0x10 Local Exp ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000_0001 0x18 Local Re map Register Space 1 0x0000_0000 0x1G Local Re map Register Space 2 0x0000_0000 0x20 Local Re map Register Space 3 0x0000_0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0x0171_78A0 0x2G Local Address Space 1 Descriptor 0x0000_0000 0x30 Local Address Spac
5. The output circuits are protected against overload short circuit and over temperature In case of such a failure the corresponding output is switched off until the error condition is removed Then the output returns automatically to normal operation and the state programmed in the Data Output Register For details about the protection of the TDE1707 please refer to the data sheet which is part of the TPMC671 ED Engineering Documentation 671 User Manual Issue 1 1 Page 7 of 28 TEWS S TECHNOLOGIES 3 1 4 Output Watchdog Writing 1 into bit 1 of the Global Control Register enables the hardware watchdog function The status of the watchdog is indicated at the bit 3 of Global Control Register Any software access read or write to the Data Output Register of the TPMC671 will retrigger the watchdog The maximum time between two accesses is set to 120ms if the time expires without a software access all outputs go into the OFF state At the same time the watchdog status will change from 0 to 1 and lock the Data Output Register This prevents a write access to the Data Output Register Writing 1 to the watchdog status Bit 3 Control Register clears this bit and also unlocks the Output Register After unlocking the Data Output Register the outputs stays in the OFF state till the next write access to this Register The watchdog is disabled after power on or reset 3 2 Digital Inputs 3 2 1 Optical Isolat
6. PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the software must enable the PCI9030 for PCI I O and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9030 set bit 0 to 1 To enable PCI Memory Space access to the PCI9030 set bit 1 to 1 Offset in Config Description Usage 0x10 PCI9030 LCR s MEM Used 0x14 9030 LCR s I O Used 0x18
7. 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x0171 0x78A0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0009 0x0000 0x0000 0x0000 0x0000 0x70 0x0000 0x0000 0x0030 0x0041 0x0078 0x0000 0x0249 0x2492 0x80 0x0000 0x0000 0x0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF 0x90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxBO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0 0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Figure 5 4 Configuration EEPROM TPMC671 xx Subsystem ID Value Offset 0 0 TPMC671 10 0x000A 671 11 0 000 671 20 0 0014 671 21 0x0015 671 User Manual Issue 1 1 Page 22 of 28 TEWS S TECHNOLOGIES 5 4 Local Software Reset The PCI9030 Local Reset Output LRESETo is used to reset the on board local logic The PCI9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted PCI9030 remains in this reset condition until the PCI Host clears this
8. 4 I O 64 pin Mezzanine connector Physical Data Power Requirements 85 mA typical 3 3V DC with all inputs and outputs inactive 200 mA typical 3 3V DC with all inputs and outputs active Temperature Range Operating 25 C to 85 Storage 55 C to 125 G MTBF 252000 h Humidity 5 95 non condensing Weight 72g TPMC671 User Manual Issue 1 1 Figure 2 1 Technical Specification Page 6 of 28 TEWS 22 TECHNOLOGIES 3 Functional Description 3 1 Digital Outputs 3 1 1 Optical Isolation The TPMC671 has 16 high side switch TPMC671 10 20 or 16 low side switch 671 11 21 digital outputs The standard signal level for these outputs is 24V DC All outputs are isolated by optocouplers from the computer system and are also isolated against each other in groups of four outputs GROUP VS standard 24V DC GROUND OUTPUT O1 VS O1 GND O1 OUT 1 OUT2 OUT 3 OUT 4 O2 VS O GND C2 OUT 5 OUT 6 OUT 7 OUT 8 O3 VS O3 OUT9 OUT 10 OUT 11 OUT 12 O4 VS O4 GND O4 OUT 13 OUT 14 OUT 15 OUT 16 Figure 3 1 Isolated Digital Outputs 3 1 2 Output Polarity Each output can be individually switched to the according power supply VS Ox high side switch or GND low side switch 3 1 3 Overload Protection The output drivers used on the 671 are smart drivers TDE1707 The maximum continuous output current is 0 5A
9. ECHNOLOGIES Bit Symbol Description Access Reset Value 15 INT STA H16 14 INT STA 5 Read access 13 INT STA H14 0 no interrupt request pending 12 INT STA H13 11 INT STA H12 1 interrupt request pending IB Write access 9 INT STA H10 8 INT STA H9 0 no effect R W 0x0000 7 INT_STA_H8 2116 1 clear pending interrupt request 6 INT STA H7 5 INT STA Bit 0 of this register reflects the interrupt request state 4 INT STA H5 of input line 1 for the rising edge bit 15 reflects the 3 INT STA H4 request state of input line 16 for the rising 2 INT_STA_HS An interrupt request for a specific input line is cleared 1 INT_STA_H2 by writing 1 to the according bit of the Rising Edge 0 INT STA H1 Interrupt Status Register TPMC671 User Manual Issue 1 1 Figure 4 8 Rising Edge Interrupt Status Register Page 15 of 28 4 2 7 Falling Edge Interrupt Status Register The Falling Edge Interrupt Status Register is a word wide read write register TEWS S TECHNOLOGIES Bit Symbol Description Access Reset Value 15 INT STA L16 14 INT STA L15 Read access 13 INT STA L14 0 no interrupt request pending 12 INT STA 113 11 INT STA L12 1 interrupt request pending 10 INT STA L11 9 INT STA L10 Write access 8 INT STA L9 0 no effect R W 0x0000 7
10. INT_STA_L8 6 INT_STA_L7 1 clear pending interrupt request 5 INT_STA_L6 Bit 0 of this register reflects the interrupt request state INTL STA L5 of input line 1 for the falling edge bit 15 reflects the 3 INT STA 14 interrupt request state of input line 16 for the falling 2 INT STA L3 edge 1 INT STA 12 An interrupt request for a specific input line is cleared 0 INT STA L1 by writing 1 to the according bit of the Falling Edge Interrupt Status Register TPMC671 User Manual Issue 1 1 Figure 4 9 Falling Edge Interrupt Status Register Page 16 of 28 TEWS S TECHNOLOGIES 4 2 8 Debounce Time Register The Debounce Time Register is a word wide read write register Bit Symbol Description Access Reset Value 15 14 The debounce time could be programmed by writing a 13 hexadecimal value in the register 12 One hexadecimal step corresponds to a debounce time of about 7us 10 DB TIME min debounce time 7us 9 max debounce time 440ms 8 debounce step 7us RW 0 0000 6 5 4 value 0 this register sets the debounce time a minimum of 7us This is the default state after 3 power on or reset Any debounce time in the range of 2 7us to 440ms can be programmed in steps of 7ps 1 The debounce time is common for all 16 inputs 0 Figure 4 10 Debounce Time Register To use the programmable debounce time the Debounce Enab
11. Mezzanine Card Connector P14 Description 5 7 Output Line 11 Description Output Line 2 Output Line 4 5 0076 Output Line 6 0078 Output Line 8 Output Line 10 Output Line 12 Output Line 14 Output Line 16 Input Line 2 Ground IN 15 Input Line 4 Input Line 6 Input Line 8 Input Line 10 Input Line 12 Input Line 14 Input Line 16 External Supply OUT1 OUT4 External Supply OUT5 OUT8 External Supply OUT9 OUT12 External Supply OUT13 OUT16 Ground OUT 1 OUT 4 Ground OUT 5 OUT 8 Ground OUT 9 OUT 12 Ground OUT 13 OUT 16 Ground IN 2 Ground IN 4 54 6 Ground IN 6 56 8 Ground IN 8 Ground IN 10 60 12 Ground IN 12 Ground 14 64 16 Ground 16 Figure 8 2 Card 14 Please verify that the tracks from the 14 connector to the Px connector of the PMC carrier board are designed for a current of typical 0 5 A min per output 671 User Manual Issue 1 1 Page 28 of 28
12. TEWS The Embedded I O Company TECHNOLOGIES 671 16 Digital Inputs 24 16 Digital Outputs 24 0 5 Version 1 0 User Manual Issue 1 1 October 2004 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany 1 E Liberty Street Sixth Floor Reno Nevada 89504 USA Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 Phone 1 775 686 6077 Fax 1 775 686 6024 e mail info Qtews com www tews com e mail usasales tews com www tews com 671 10 16 digital inputs 16 digital high side switch outputs front panel I O 671 11 16 digital inputs 16 digital low side switch outputs front panel I O TPMC671 20 16 digital inputs 16 digital high outputs P14 I O side switch TPMC671 21 16 digital inputs 16 digital low side switch outputs P14 I O TEWS S TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox 0x029E that means hex
13. URE 8 1 PIN ASSIGNMENT I O HD68 SCSI 3 TYPE CONNECTOR 27 FIGURE 8 2 MEZZANINE CARD CONNECTOR sss 28 TPMC671 User Manual Issue 1 1 Page 4 of 28 TEWS S TECHNOLOGIES 1 Product Description The TPMC671 is a standard single width 32 bit PMC with 16 digital inputs 24V galvanically isolated from the computer system by optocouplers The inputs are also potential free to each other A high performance input circuit ensures a defined switching point and polarization protection against confusing the pole All inputs have a common electronic debounce circuit with a freely programmable debounce time All inputs can generate an interrupt The signal edge handling is programmable to interrupt on rising falling or both edges of the input signal The 671 has 16 digital high side or low side switches build option with galvanic isolation from the computer system by optocouplers The outputs are isolated against each other in groups of four outputs All outputs are protected against short circuit and thermal overload The output drivers are capable of driving 0 5A continuous per channel A hardware watchdog clears all outputs in case of trigger fail The TPMC671 1x provides front panel I O the 671 2 provides P14 I O 8 Figure 1 1 Block Diagram 671 User Manual Issue 1 1 Page 5 of 28 TEWS TECHNOLOGIES 2 Technical Spec
14. adecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e RESET4 Access terms are described as W Write Only R Read Only RW Read Write Read Clear 5 Read Set 2004 by TEWS TECHNOLOGIES GmbH Issue Description Date 1 0 First Issue September 2004 1 1 Correction of PCI Header October 2004 TPMC671 User Manual Issue 1 1 Page 2 of 28 TEWS S TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION uuu 5 2 TECHNICAL SPECIFICATION l J 6 3 FUNCTIONAL DESCRIPTION 7 21 Sua Qha 7 3 1 1 Optical 150 E 7 Np 7 3 1 9 PrOtectioD ho c a tot ern e bt 7 3 1 4 Output WatchdO0g iieri reete t rupe tex kun ee eae oe 8 3 2 Digital INPUts qq 8 3 2 50 2 tette tte 8 3 2 2 Deboutnce FUnDcllOrni i crier ttc 8 3 2 9 ias 8 4
15. apped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFFF1 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI Cardbus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N s b 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 0x3C Lat Min Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM Nxt Cap PM Cap ID N 4801 00 01 0x44 PM Data PM CSR EXT PM CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID Y 23 16 00 00 00 06 0x4C VPD Address VPD Nxt Cap VPD ID Y 31 16 0000 00 03 0x50 VPD Data Y 00000000 Subsystem ID 671 10 Figure 5 1 9030 Header 0x000A TPMC671 11 0x000B TPMC671 20 0x0014 671 21 0 0015 671 User Manual Issue 1 1 Page 19 of 28 TEWS TECHNOLOGIES 5 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the 9030 PCI Base Address Register 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires
16. bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI Interface is not reset 671 User Manual Issue 1 1 Page 23 of 28 TEWS TECHNOLOGIES 6 Configuration Hints 6 1 Software Reset Controller and LRESET A host on the PCI bus can set the software reset bit in the Miscellaneous Control Register CNTRL 0x50 of the PCI Controller PCI9030 to reset the Controller and assert LRESET output The PCI9030 remains in this reset condition until the PCI host clears the software reset bit 6 2 Big Little Endian PCI Bus Little Endian Byte 0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 81 24 e Every Local Address Space 0 3 and the Expansion ROM Space can programmed to operate in Big or Little Endian Mode Big Endian Little Endian 32 Bit 32 Bit Byte 0 07 0 Bye 1 015 8 Byte 2 0123 16 Byte 3 0131 24 16 16 Byte0 07 0 015 8 16 Bit lower lane Ps 8 Bit upper lane 8 Bit 0 D 31 24 D 7 0 8 Bit lower lane Byte 0 D 7 0 Figure 6 1 Local Bus Little Big Endian 671 User Manual Issue 1 1 Page 24 of 28 Standard use of the TPMC671 Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space TEWS S TECHNOLOGIES 16 bit bus in Big Endian Mode not used not used not used not used To change t
17. e 2 Descriptor 0x0000_0000 0x34 Local Address Space 3 Descriptor 0x0000_0000 0x38 Local Exp ROM Descriptor 0x0000_0000 Ox3C Chip Select 0 Base Address 0x0000 0009 0x40 Chip Select 1 Base Address 0x0000 0000 0x44 Chip Select 2 Base Address 0x0000 0000 0x48 Chip Select 3 Base Address 0x0000 0000 0x4C Interrupt Control Status 0x0041 Ox4E EEPROM Write Protect Boundary 0x0030 0x50 Miscellaneous Control Register 0x0078 0000 0x54 General Purpose Control 0x0249 2492 0x70 Hidden1 Power Management data select 0x0000 0000 0x74 Hidden 2 Power Management data scale 0x0000_0000 Figure 5 3 PCI9030 Local Configuration Register 671 User Manual Issue 1 1 Page 21 of 28 TEWS S TECHNOLOGIES 5 3 Configuration EEPROM After power on or PCI reset the PCI9030 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 to OxFF Reserved See the PCI9030 Manual for more information Address Offset 0x00 0x02 0x04 0x06 0x08 Ox0A 0x0C Ox0E 0x00 0x029F 0x1498 0x0280 0x0000 0x1180 0x0000 s b 0x1498 0x10 0x0000 0x0040 0x0000 0x0100 0x4801 0x0001 0x0000 0x0000 0x20 0x0000 0x0006 0x0000 0x0003 OxOFFF OxFFF1 0x0000 0x0000 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40
18. e local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces PCI9030 PCI9030 PCI Size Port Endian Description Local PCI Base Address Space Byte Width Mode Space Offset in PCI Mapping Bit Configuration Space 0 2 0x18 IO 16 16 BIG Local Register Space 1 3 0x1C Not Used 2 4 0x20 Not Used 3 5 0x24 Not Used Figure 4 1 PCI9030 Local Space Configuration 4 2 Local Register Space Address Map Offset to PCI Register Name Size Base Address 2 Bit 0x00 Data Output Register 16 0x02 Data Input Register 16 0x04 Control Status Register 16 0x06 Rising Edge Interrupt Enable Register 16 0x08 Falling Edge Interrupt Enable Register 16 Ox0A Rising Edge Interrupt Status Register 16 0x0C Falling Edge Interrupt Status Register 16 OxOE Debounce Time Register 16 Figure 4 2 FPGA Register Space TPMC671 User Manual Issue 1 1 Page 9 of 28 4 2 1 Data Output Register TEWS S TECHNOLOGIES The Data Output Register is a word wide read write register that is used to set or clear the different outputs of the TPMC671 Bit Symbol Description Access Reset Value 15 OUTPUT16 14 OUTPUT15 13 OUTPUT14 12 OUTPUT13 TO Set an output line active write 1 to the corresponding bit 11 OUTPUT12 For the inactive state write 0
19. gnal Description Pin Signal Description 1 OUT 1 Output Line 1 35 VS O2 External Supply OUT5 OUT8 3 External Supply OUT9 OUT12 4 External Supply OUT9 OUT12 5 External Supply OUT13 OUT16 6 7 8 OUT6 Output Line 6 VS 04 External Supply OUT13 OUT16 OUT 7 Output Line 7 GND O1 Ground OUT 1 OUT 4 OUT8 Output Line 8 GND_O1 Ground OUT 1 OUT 4 9 0079 Output Line 9 GND O2 Ground OUT 5 OUT 8 10 Output Line 10 44 GND 02 Ground OUT 5 OUT 8 11 00711 Output Line 11 45 GND Ground OUT 9 OUT 12 12 OUT12 Output Line 12 46 GND round OUT 9 OUT 12 13 OUT13 Output Line 13 GND O4 Ground OUT 13 OUT 16 14 OUT14 Output Line 14 GND O4 Ground OUT 13 OUT 16 15 OUT15 Line 15 Ground IN 1 16 OUT16 Output Line 16 Ground IN 2 24 Input Line 8 Em IN 10 Ground IN 10 25 Input Line 9 IN 11 Ground 11 26 IN 10 Input Line 10 E IN 12 Ground IN 12 27 IN11 Input Line 11 IN 13 Ground IN 13 28 IN 12 Input Line 12 IN 14 Ground IN 14 29 IN 13 Input Line 13 IN 15 Ground IN 15 30 IN 14 Input Line 14 IN 16 Ground IN 16 34 VS O1 External Supply OUT1 OUTA Not Used Figure 8 1 Pin Assignment HD68 SCSI 3 type Connector Please check the maximum current of the used connection cable Some standard cables AWG28 68pin are limited to 0 75 A per lead 671 User Manual Issue 1 1 Page 27 of 28 TEWS S TECHNOLOGIES 8 2
20. he Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the Mode A value of 1 indicates Big Endian and a value of 0 indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TPMC671 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset LASOBRD LAS1BRD LAS2BRD LAS3BRD EROMBRD Name 0x28 0 2 0 30 0 34 0x38 Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TPMC671 User Manual Issue 1 1 Page 25 of 28 TEWS 22 7 Installation 7 1 Input Wiring 24V GND Figure 7 1 Input Wiring 7 2 Output Wiring High Side Switch 10 20 External Supply 6 to 48V x K TDE 1707 Load GND OUT Figure 7 2 Output Wiring High Side Switch 7 3 Output Wiring Low Side Switch 11 21 Exterr Supply 6 to 48V TDE 1707 GND OUT Figure 7 3 Output Wiring Low Side Switch 671 User Manual Issue 1 1 Page 26 of 28 TEWS S TECHNOLOGIES 8 Pin Assignment l O Connector 8 1 Front Panel Connector Pin Si
21. ification Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 1 compliant 33 MHz 32 bit PCI 3 3V and 5V PCI Signaling Voltage On Board Devices PCI Target Chip PCI9030 PLX Technology Interface Number of Inputs 16 digital Inputs Input Isolation Optocouplers for galvanic isolation also isolated to each other Input Voltage 24V DC typical Input Current 4 2mA typical at 24V input voltage Input Switching Level 12V typical 7 5V minimum 14V maximum Input Signal Debouncing Electronic debouncing 7us to 440 ms in steps of 7us common for all input channels can be disabled Input Interrupts 16 input interrupts Trigger on rising falling or both edges Outputs TPMC671 10 20 16 digital high side switch Outputs TPMC671 11 21 16 digital low side switch Outputs Output Isolation Optocouplers for galvanic isolation also isolated to each other in groups of four outputs External Output Voltage 24N DC typical 6V DC minimum 48V DC maximum Output Current 0 5A typical 0 3A for voltages over 32V Short Circuit Current 0 8A typical Output Voltage Drop 1 1V typical at 0 5A Output Protection Overload short circuit GND and Vs open wire protection thermal shutdown Connector 671 10 11 HD68 connector SCSI 3 type connector 671 20 21 PMC P1
22. ion 671 has 16 digital inputs The standard signal level for these inputs is 24V DC The switching level of the inputs is between 7 5V and 14V All inputs are isolated by optocouplers from the computer system and are also isolated against each other 3 2 2 Debounce Function A programmable debounce function common for all inputs is implemented on the TPMC671 There is only one debounce time adjustable for all 16 digital inputs If the debounce function is enabled the input pin must be static for the programmed debounce time before the rising or falling edge is recognized as valid So only after a correct identification the Data Input Register is updated and an interrupt is generated The debounce function is disabled after power on and reset The debounce time is set to value 0 after power on and reset 3 2 3 Interrupt Logic Interrupt generation can be individually programmed for each channel and input transition To enable the interrupt after a reset the Global Interrupt Enable bit in the Control Register must be set to the value 1 Also the respective bit for rising or falling edge in the Rising Edge Falling Edge Interrupt Enable Registers must be set The Global Interrupt Enable and also all individually interrupt enable bits are disabled after power on and reset 671 User Manual Issue 1 1 Page 8 of 28 TEWS S TECHNOLOGIES 4 Local Space Addressing 4 1 PCI9030 Local Space Configuration Th
23. ising Edge Interrupt Enable Register 6 INT ENA H7 enables the interrupt of input line 1 for the rising edge 5 INT ENA He Bit 15 enables interrupt of input line 16 for rising edge 4 INT ENA H5 All other bits are equivalent 3 INT ENA H4 2 INT ENA H3 1 INT ENA H2 0 INT ENA H1 Figure 4 6 Rising Edge Interrupt Enable Register 671 User Manual Issue 1 1 Page 13 of 28 TEWS S TECHNOLOGIES 4 2 5 Falling Edge Interrupt Enable Register The Falling Edge Interrupt Enable Register is a word wide read write register Bit Symbol Description Access Reset Value 15 INT ENA L16 14 INT ENA 115 13 INT ENA L14 12 INT 113 11 INT 112 10 INT ENA 111 0 Interrupt for input line disabled E eNO 1 Interrupt for input line enabled 8 INT_ENA_L9 R W 0x0000 7 INT ENA 18 Bit 0 of the Falling Edge Interrupt Enable Register 6 INT ENA L7 enables the interrupt of input line 1 for the falling edge 5 INT ENA Le Bit 15 enables interrupt of input line 16 for falling edge 4 INT ENA 15 other bits equivalent 3 14 2 1 12 0 11 Figure 4 7 Falling Edge Interrupt Enable Register 671 User Manual Issue 1 1 Page 14 of 28 4 2 6 Rising Edge Interrupt Status Register The Rising Edge Interrupt Status Register is a word wide read write register TEWS S T
24. le Bit of the Control Status Register must be set to 1 If the Debounce Enable Bit of the Control Status Register is set to 0 no debounce function is active for all inputs The following formulas can be used to determine the preload value pes Z 1 3 5 tab typical debounce time s t Z b PCICLK 1 2 preload value 64 3 5 PCICLK 33 33 MHz 64 tmax max debounce time s A tmin min debounce time 5 Fs Z 1 oer Figure 4 11 Formulas to determine preload value TPMC671 User Manual Issue 1 1 Page 17 of 28 TEWS S TECHNOLOGIES Debounce Time Examples 5007 s001 0 0x00 0 041 0x0005 10 0 090 0 012 0x000C 0x0252 Figure 4 12 Debounce Time Examples TPMC671 User Manual Issue 1 1 Page 18 of 28 5 9030 5 1 PCI Configuration Registers PCR 5 1 1 PCI9030 Header TEWS S TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits PCI Initial Values Register writeable Hex Values padres 24 23 16 15 2717 0 0 00 Device ID Vendor ID N 029F 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 118000 00 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for M
25. ll output channels Also the Output Register is locked 0 clears this bit and unlocks Output Register 2 DB ENA Debounce Enable R W 0 1 enables the debounce function for all 16 inputs 0 disables debounce function 1 WD Watchdog Enable R W 0 1 enables watchdog for all 16 outputs 0 disables watchdog function 0 Global Interrupt Enable R W 0 globally enables interrupt for all 16 inputs 0 globally disables interrupts The input channels generate interrupts at pin INTA of the PCI bus Figure 4 5 Control Status Register Additional to this Global Interrupt Enable the Interrupt INTA must be enabled in the PCI Interrupt Line Register PCIILR 0x3C of the PCI Controller PCI9030 Default after power on and reset is INTA is enabled The watchdog status is only active if the watchdog is enabled TPMC671 User Manual Issue 1 1 Page 12 of 28 TEWS S TECHNOLOGIES 4 2 4 Rising Edge Interrupt Enable Register The Rising Edge Interrupt Enable Register is a word wide read write register Bit Symbol Description Access Reset Value 15 INT H16 14 INT 15 13 INT ENA H14 12 INT H13 11 INT H12 10 INT H11 0 Interrupt for input line disabled 1 T ENA MID 1 Interrupt for input line enabled 8 INT ENA H9 R W 0x0000 Y INT ENA H8 Bit 0 of the R
26. re Reset LI I u aaa aeaa Aaa 23 6 CONFIGURATION HINTS 24 6 1 Software Reset Controller and LRESET 8 J 24 6 2 Big Little 24 f INSTALLATION ois ERE RD ERR RI EIN RD ARMEN A RR RN ADEM AMNEM MM ENS 26 3 1 mput WANING E 26 7 2 Output Wiring High Side Switch 10 20 U U U U u J 26 7 3 Output Wiring Low Side Switch 11 21 U u u u J 26 8 PIN ASSIGNMENT CONNECTOR J 27 8 1 Front Panel Connector I 27 8 2 Mezzanine Card Connector P14 28 671 User Manual Issue 1 1 Page 3 of 28 Table of Figures TEWS S TECHNOLOGIES FIGURE 1 1 BLOCK DIAGBAM iet salah P Rr RR OUR 5 FIGURE 2 1 TECHNICAL SPECIFICATION eese nnne eret nnne 6 FIGURE 3 1 ISOLATED DIGITAL OUTPUTS sssssseeeeeneennrennennnnn nnne enne rennen nre 7 FIGURE 4 1

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