User manual MSC TDC-MACH 330, Rev. 1.2
Contents
1. HS RoN in imema pull up Read strobe low activey OV Out 8mA 0 TDC Core and Precounter ok 1 Overflow of TDC Core or Precounter 1 2 3 4 6 7 8 9 14 NC Do not connect 15 16 17 18 19 20 21 22 23 26 27 31 33 34 37 39 43 44 45 46 47 49 50 51 52 53 54 55 56 57 59 70 72 76 78 83 87 91 94 96 98 100 Notes All Inputs Outputs are LVCMOS 3 3V When operating via the parallel interface SCK and MOSI have to be tied to GND and SSN has to be tied to Vcc When operating via the SPI DATA 7 0 and ADR 2 0 have to be tied to GND Table 4 3 Pin Function List TQFP100 TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 10 of 37 10 21 26 38 52 53 63 82 93 Vcc Power supply 3 0V 3 6V 98 117 128 129 135 11 16 27 37 42 59 64 83 88 ND Ground 99 118 123 127 136 HON NN 4 VALID Out 8mA 0 No valid data for readout 1 End of measurement Raw value registers contain valid data for readout 9 O START n j Statinputtriggersonrisingedges Power on reset low active 55 SSN In SPI Slave select When SSN 1 then SPI in reset CALCLK In Input for crystal clock 3MHz lt CALCLK lt 32MHz SLEEPN In internal pull up 0 Sleep mode PN a 0000 80 DATAO Bid 8mA BiOdaabus y O 9 DATA Bid 8mA BiOdaabus i y O 922. 9 x JL ae c wp O ns tawr 10 ms twrape 3 ms o tom 0 J ms twas 0 ms tow 25 ms Voc 3 0V 3 6V T4 0 to 70 C Load 30pF Table 6 1 Read and Write Cycle Timing Characteristics 6 5 2 Serial Peripheral Interface SPI 6 5 2 1 Data and Control Lines The SPI of the TDC Mach330 acts as slave providing the following data and control lines e MOSI Serial data line master out slave in e MISO Serial data line master in slave out e SCK Serial SPI clock provided by the master e SSN Slave select SSN 0 resp SPI reset SSN 1 Master and TDC exchange their data bit by bit via 8 bit data packets on the serial data lines MOSI and MISO sending the MSB at first and the LSB at last Each bit of an 8 bit SPI cycle is transmit ted using the rising edge of the SPI clock SCK and received using the falling edge of SCK The idle state of SCK is 0 When SSN is 1 then the SPI is in reset and the line MISO is in tristate When SSN is 0 then the SPI is active and any number of SPI cycles can be made running with or with out a rest period of SCK 6 5 2 2 Timing Diagram tsu Voc 3 0V 3 6V T4 0 to 70 C Load 30pF Table 6 2 SPI Cycle Timing Characteristics TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 22 o
3. MOS mn jSPEMastrouslavein 58 7 4 0 parallel interface 1 SPI DATA4 Bidi 8mA Bit4 data bus MISO Tristate Out 8mA SPI Master in slave out uem eue When pin SSN 1 then MISO tristate 143 Out 8mA 0 TDC Core and Precounter ok 1 Overflow of TDC Core or Precounter 1 2 3 5 6 7 8 13 14 15 17 NC Do not connect 18 19 20 22 23 24 25 28 29 30 31 32 33 34 35 36 39 40 41 43 44 45 46 47 48 50 51 54 56 57 60 61 62 65 66 67 68 69 71 72 73 74 75 76 77 79 84 85 86 87 90 91 100 101 102 104 105 107 108 109 110 112 113 115 116 119 121 122 125 126 130 131 132 134 137 138 140 142 144 Notes All Inputs Outputs are LVCMOS 3 3V When operating via the parallel interface SCK and MOSI have to be tied to GND and SSN has to be tied to Vcc When operating via the SPI DATA 7 0 and ADR 2 0 have to be tied to GND 2 9 0 8 1 2 5 7 Table 4 4 Pin Function List TQFP144 TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 11 of 37 P4 P7 B12 B7 B6 B5 Vcc Power supply 3 0V 3 6V A14 H14 P10 G1 P1 H1 N2 N4 N3 N10 GND Ground G14 B13 A10 B8 A4 N9 B9 C2 VALID Out 8mA 0 No valid data for readout 1 End of measurement Raw value registers contain valid data for readout Input for crystal clock 3MHz lt fcarcik lt
4. User Manual Version 1 2 Date 2011 12 22 MSC Vertriebs GmbH Industriestra e 16 76297 Stutensee Germany Author AP Phone 49 7249 910 288 Fax 49 7249 910 4388 Email AP msc ge com MSC All rights reserved Although great care has been taken in preparing this document MSC can not be held responsible for any errors or omissions All information in here is subject to change without notice All hardware and software names used are trade names and or trademarks of the respective owners tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 2 of 37 Contents 1 IN FRODUCTION wisssssssscsccssccscicssccccsessccdsscesscosesdsesssiceseseseosseutseceseceseossesesdecsdceseoesesesises sesensseseses 4 2 MBCA TURES 07 iot en o0 2t ov E UE ed 0 02 0000 Ps EOS VE SP Ue UE US PR UUUC 00 00 00 00 00 9s UU US 0 00 0 VE 20 PN OU NE UO UE UOCE 5 3 BLOCK DIAGRAM sissies 6627 6 2 29596450007 002505 F 6b 9r tore as edo eid ros dr 53s oa i001 Ps OUO L aS S OSEE Pea osudi 6 4 PACKAGES PIN AND BALL CONFIGURATIONSS eee ee ee eese eee oeste ense ette en au 7 4 1 THIN QUAD FLAT PACKAGE TQFP ccccscsscccececsesssssececececsesssssaeceseceesenesseseeeceeseeesensaaeees 7 4 2 CHIP SCALE BALL GRID ARRAY CSBGA sis ecastanszcasincazeGicsatstanastensceienuncnieniezaien 8 4 3 PIN AND BALL CONFIGURATIONS cccscsseccsccccsccsssssceccccsscesseusscecceesseeuseasseecsesseseuseusseesseseeeea 9 5 M
5. 25ps is used for reference measurements The offset of the diagram is approx 700ps This systematic error results from a different length of cables for start and stop and is irrelevant here TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 35 of 37 14 1 2 0 6 0 4 0 2 TDC Mach330 Singleshot from 9 to 10ps Increment 1ns auto Cal Clock 4MHz 3 3V Measurement Error ns 0 8 4 Ie n E i SS d MERC nnd I EL Lu m 1 zer tdc msc ge com www msc ge com 0 9 de GY LOM DH LV ut uo OD uo atu uu nO av P so cq ae AV udo a 9 AO drum uu up utr a o9 uo ua d af PH GS a SF GOOD XD LP qo qo di di q E q di di do do di do do di dV dV dU do di d d d dU dU dU Time ns Figure 9 3 Measurement Errors of Singleshot Measurements at 3 3 V 9 10 2 Auto Noise Unit Effect on Measurement Errors If there is the possibility to measure the same time difference several times a higher accuracy can be achieved by calculating the average measurement result With an increasing number of measure ments the average measurement result will converge the real time difference So in theory the measurement error of the average measureme
6. 32MBz M12 SLEEPN In internal pull up 0 Sleep mode F14 i 8mA E14 EN SPI In 0 parallel interface 1 SPI Al OV Out 8mA 0 TDC Core and Precounter ok 1 Overflow of TDC Core or Precounter B1 Cl D2 D1 El E2 NC Do not connect F1 F2 J1 J2 K1 K2 L1 L2 M1 M2 N1 M3 P2 P3 P5 P6 N6 P8 P9 P11 N11 P12 N12 P13 P14 N13 N14 M14 L13 L14 M13 K14 K13 J13 C14 B14 A13 B11 A9 A7 A5 B4 B3 C3 B2 Notes All Inputs Outputs are LVCMOS 3 3V When operating via the parallel interface SCK and MOSI have to be tied to GND and SSN has to be tied to Voc When operating via the SPI DATA 7 0 and ADR 2 0 have to be tied to GND Table 4 5 Ball Function List csBGA100 TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 12 of 37 5 Measuring Procedure The TDC Mach330 provides a measurement channel with TDC Core with a typical resolution of 115ps LSB In addition the TDC has a Precounter for counting the calibration clocks between start and stop of a time measurement 5 1 Time Measurement As shown in Figure 3 1 and Figure 5 1 one start and one stop input are available for measuring the time differences tggs Both inputs trigger on rising edges Each measurement is divided into three stages 1St stage 2nd stage 3rd stage VALO CLK Precounter 0 0 1 PRE 1 PRE START S
7. after readout of VALO VAL 1 0 gt 1 Clock Auto Noise Unit and PRE Bit has to be cleared to 0 before setting to 1 again 0 21 Stand alone calibration measurement start Bit has to be cleared to 0 after readout of CAL1 and CAL2 Warning Reading out bit 3 will always show a 0 no matter if bit 3 is set to 1 or cleared to 0 Setting bit 3 to 1 can be done along with clearing bit 0 1 or 2 to 0 Clearing bit 3 to 0 can be done along with setting bit 0 1 or 2 to 1 Figure 7 1 Control Register CTRL REG Format TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 25 of 37 7 2 2 Status Register STATUS REG 7 3 2 1 0 Bit 00000 0 0 O Default after power on reset reserved OV PRE flag VALID flag 0 Precounter ok 0 No valid data for readout 1 Overflow Precounter 1 End of measurement Raw value registers contain valid data for readout OV CORE lag 0 TDC Core ok 1 Overflow TDC Core Figure 7 2 Status Register STATUS REG Format 7 2 3 Raw Value Registers 15 8 7 0 Bit Default after power on reset high byte low byte Figure 7 3 Raw Value Register Format All raw values are 16 bit UNSIGNED INTEGER numbers Thus the maximum number for the measurement and calibration values VALO VALI CALI and CAL2 is Oxffff 65535 Because the MSB of PRE is fixed to 0 a
8. are specified in Table 8 2 After leaving Sleep Mode and reaching Normal Mode first of all a low active reset pulse has to be performed at the RSTN pin The pulse has to be 100ns at least After this reset the TDC has its default settings Sleep Mode I O lewRDOWN SLEEPN twsteepn OF twawake Figure 8 1 Sleep Mode Timing Symbol Parameter Min Max Unit ewepows SLEEPN low to power down 400 ms SLEEPN high to power up 60 ps SLEEPN pulse width 400 ms SLEEPN pulse rejection 100 n Notes Do not enter Sleep Mode during power on device configuration cp Chapter 9 8 SLEEPN has a glitch filter to prevent false triggering Table 8 2 Sleep Mode Timing Characteristics TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 27 of 37 9 Appendix 9 1 Electrical Specification Ticow Junction Temperature Commercial Operation 0 85 C Table 9 1 Recommended Operating Conditions l PLD Configuration Current Vcc 33V TA 25C 38 mA lc Standby Current Vcc233V TA 25C 24 mA ls SleepModeCuren Vcc233V TA 25C 21 pA cw Current during Measurement Ts 25 C 15 m ELT Crystal Clock is is active fcarc k 4MHz 0s Vas V02 fips ot igs rs v
9. 9 6 5 PROCESSOR INTERFACE wiv sssescdccacsedenosebesdcedsdacencesnacecssssudesugeneeadsdegace desshedscatiucenesshaeteeteiadgedaas 19 6 5 1 Parallel Interface eee Here EE eer te eee E caved Ee DR Peel e be pe pesa Deed e Ee ER 19 6 5 1 1 Data and Control Lines wi cccccccsssesescccccccecessesescsccccesssseessuceeesceseseuensuseeses 19 2122 imine Di gtaMs codecs bib ERU PREMIT DD ene ae ae 20 6 5 2 Serial Peripheral Interface SPD oeste eret r era vereda E Tan nio Uo pa Ys UR ek Yep E ved Eee sEaes 21 6 5 2 1 Data and Control Lines oui eececcccccccccesesescscccccesessesssceccccsssssseusesececcsssseeeusnsssesss 21 65 22 Inline Dl fra Meare vtae uxo M pd rd Een eee 21 ACE Me a PP 22 7 PROGRAMMING OF THE TDC MACH330 000000000000000s0s0sssosssssssosssssssssssssssssssssssssso 23 7 1 ADDRESSING erecta ere E e A E A E N e A ERa 23 7 1 1 Parallel Interface taenn a a E E TE REN aE 23 7 1 2 Serial Peripheral Interface SPD eese tus rii tatem daas re bist tren lt Cena 23 7 2 REGISTER FORMAT verirsin T 24 72 4 Control Register CTRL REG sescireiiiia aoea tai an ata aes 24 7 2 2 Status Register STATUS_REG So quies eta idus eds m textu mdi qun n prd NE EIE 25 T23 RaW Vale C ui cu ERR UT m Em 25 TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 3 of 37 S SLEEP MODE 6o n ni en repo POPE VO VETERI IE Ga PO VOV UV E
10. C 50 C 70 C Table 9 4 Resolution Voltage and Temperature Dependance TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 29 of 37 9 3 Differential Non Linearity The quality of a measurement not only depends on the TDC s resolution but also on its so called differential non linearity DNL The DNL is a criterion for the variation of the quantisation stage s width LSB width Figure 9 1 shows a typical histogram of the TDC s LSB widths at Vcc 3 3V where the average LSB width is identical with the resolution RES sp Furthermore the figure illustrates the definition of the DNL TDC Mach330 LSB widths 350 300 LSB width ps 250 200 150 RES iss 100 4 Maximum differential non linearity max DNL max 1 RES sg i Medium differential non linearity m DNL m A RES se Figure 9 1 Resolution LSB Width and Differential Non Linearity Table 9 5 shows the maximum and medium differential non linearity based upon measurements of several TDCs at different supply voltages m DNL max DNL 150 Table 9 5 Differential Non Linearity Ta 25 C TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 30 of 37 9 4 Minimum and Maximum Measureme
11. DC s raw value registers needs three SPI cycles Within the first cycle the lowest 6 bits of a MOSI data packet are taken as register address Within the second cycle the low byte of the addressed register is transferred via line MISO In order to read out the register s high byte TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 24 of 37 within the third cycle the register s address has to be transmitted once more within the second cy cle Please make sure that SSN is set to 0 all the time between the three SPI cycles MOSI data packet bin Register write w MSB LSB read r 0000 0000 gt low byte first 0000 0001 CAL2 gt low byte first 0000 0010 VALO gt low byte first 0000 0011 VALI low byte first 0000 0100 PRE low byte first 0000 0101 0000 0110 STATUS REG 0000 0111 CTRL REG Olxx xxxx CTRL REG Table 7 2 MOSI data packet format 7 2 Register Format 7 2 1 Control Register CTRL REG 7 6 5 4 Bit 8 2 141 0 00 00 o o 0 O Default after power on reset L 0 gt 1 Time measurement with automatic calibration reserved measurement activation Bit has to be cleared to 0 after readout of VALO VAL1 PRE CAL1 and CAL2 Calibration Clock Divider 00 1 1 10 1 4 0121 2 11 1 8 0 21 Stand alone time measurement activation Bit has to be cleared to 0
12. EASURING PROCEDURE esesososososssssosssosssosssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssse 12 5 1 TIME MEASUREMENT 0000000ssesesesesesesesesesesssessseseseseseseseseseseeeseseseseseseseseseseseseseseseeseeeeeees 12 5 2 GENERATING CALIBRATION VALUES cccccsccccccccecsssssececcccceceessusseeccecseeeensucseesceseeauensnsneses 13 5 3 RESULT CALCULATION sseni vedetesshcdueassdedecsetectdedavveredeabeckucdacuseerssdecad dussuavedsuaeed consueeaees 14 5 4 GENERAL MEASUREMENT CYCLE eee nen nennen nnn nnne n n n nn nnn n n nn panneau 15 6 FUNCTIONAL DESCRIPTION eee ee eese ettet ettet ttt ttes sese ee eese se sess esee cue 16 6 1 CALIBRATION CLOCK DIVIDER eceeeeeeeeeeene eee eene nn nennen etes esse e iier eese s esse siente ees 16 6 2 MEASUREMENT CHANNEL cccccccccccccscessscececcsccesseusecccecescsessuueussesecesssseuuuuseceeecssessuueuensssesss 16 62 1 Do Unit RR 17 6 2 2 Preco ntek 52 erre re rente i ce e Yee canes eee vlde eu va ede a db eve Ys eee vue a Eee EE NH TER E 17 6 2 3 Auto Noise Units iie iE eere teet eere bebe eiTe debe Lese Pee aepo e Eee Dee eR ERE 17 6024 TDC CO 18 6 3 CONTROL AND STATUS REGISTER 000000ssssssssessesssssesesssesesesessseseseseseseseseseseseseseseseseeesees 19 6 4 RAW VALUE REGISTERS 0 00000essessesessessesesssessseseseseseseseseseseseseseseseseseseseseeeseseseseseseseeecees 1
13. PUM IE 26 D APPEND co Mn 27 9 1 BEEBCTRICAL SPECIFICATION 5 nee rte EDI DO Daten s 27 9 2 RESOLUTION LS B Jaenen onana tester sa Miete Ree re inea abi Ceo neues aou eo Pea ue ei ee end OO 28 9 2 1 How to calculate the Resolution esses eene eene nnne enne enint 28 9 2 2 Voltage and Temperature Dependance eere eene netta anon atn ener nane th dna eaae n 28 9 3 DIFFERENTIAL NON LINEARITY cccccscssssssecececcceceesenseseceeececeeeensaeeeeeeceeeeesessaaeeeseceeseeeeas 29 9 4 MINIMUM AND MAXIMUM MEASUREMENT PERIOD sssscsscccececsesessnseceeecececsesensaececeeeens 30 9 4 1 Minimum Measurement Period sess eene nennen entente 30 9 4 2 Maximum Measurement Period sss eene eene nemen meme m emen ee nennen 30 9 5 MINIMUM PULSE WIDTH OF START AND STOP SIGNALS eese enne 30 9 6 TIMING WHEN ACTIVATING A TIME MEASUREMENT eere eene eene nnne sene na 31 9 7 DEAD TIME S iii a A E E T TEE 31 9 7 1 Dead Time of a stand alone Time Measurement eese 32 9 7 2 Dead Time of a stand alone Calibration Measurement see 32 9 7 3 Dead Time of a Time Measurement with autom Calibration Measurement 32 9 8 POWER ON CHARACTERISTICS 1soeoserp eo PSU pL PIU doppie end es 1nd te ndseed uu hd Up RP atu pun d Len iinan sia 33 9 9 BOARD LAYOUT RECOMMENDATIONS ssssscsssecec
14. TOP thes gt tvan H tore tres tvato leng tvari Figure 5 1 Time Measurement In the first stage of the measurement the TDC Core measures the time difference tyAro between the start signal and the following rising edge of the divided calibration clock CLK The result is stored as measurement value VALO in a raw value register In the second stage the Precounter counts the clock periods of CLK between the start and the stop signal to get the time difference tprr The re sult PRE is also stored in a raw value register Finally in the third stage of the measurement the time difference tyar between the stop signal and the following rising edge of CLK is measured using the TDC Core once again The result is stored as measurement value VALI in a raw value register TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 13 of 37 The measurement values VALO and VALI are dependant on the temperature and the supply vol tage Therefore they have to be weighted according to the TDC characteristic see Figure 5 2 Off set and gradient of the characteristic have to be determined by a so called calibration measure ment Raw value 1 calibration value 2 measurement value 2 calibration value A 1 measurement value CAL2 NN x VALI P d VALO mo ae CAL1 ato a esis ES M sar qe ps OFFSET s gt T teat tv
15. ations 9 9 1 General Power and Ground Recommendations To guarantee a high degree of signal integrity a power and a ground plane are a must for layout The power plane must have low resistance to ensure minimum voltage drop to the devices Furthermore it is strongly recommended to isolate the TDC s power supply plane from the supply plane of all other components This can be done either by using a separate voltage regulator for the TDC s sup ply or by placing a Ferrite Bead with good current carrying characteristics and low resistance in series with the voltage source to choke off the high frequency noise that may be caused by the other shared power supply 9 9 2 Decoupling Recommendations Decoupling or bypass capacitors play a big role in the TDC s performance The main role of bypass capacitors is to act as a local DC power supply to meet the demands of fluctuating power espe cially when the measurement starts and block unwanted noise coming from or going into the power plane The following guideline is a good rule of thumb for proper decoupling e Bypass capacitor usage must take into account both a low ESR and a low ESL e Use four 100nF X7R ceramic capacitors 0805 or 0603 one each side of the TDC and one 2 2nF X7R ceramic capacitor 0805 or 0603 per power pin e Locate decoupling capacitors as close as possible to the device power pins and run short wide traces to vias when they are required e Use two 10uF tantalum electr
16. ato taut toate Figure 5 2 Characteristic of the TDC Core 5 2 Generating Calibration Values To generate the calibration values CAL1 and CAL2 shown in Figure 5 3 a clock signal has to be provided at the TDC s pin CALCLK This clock is the absolute time reference and therefore it must have the precision of a crystal This crystal clock is divided by the internal calibration clock divider The resulting calibration clock CLK is measured during a calibration measurement using the TDC Core CAL1 CAL2 CLK TT teat toate l Figure 5 3 Calibration Measurement TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 14 of 37 During the calibration measurement the length of one and two periods of the divided calibration clock CLK are measured and the resulting calibration values CALI and CAL2 are stored just like the measurement value VAL in the raw value registers The time periods tcar and tcAr2 2 tear are well known A calibration measurement is performed either automatically after a time measurement or has to be started stand alone from time to time depending on the required accuracy 5 3 Result Calculation The time differences tvAro tvar1 and tpre of each measurement stage and the resulting time differ ence tres are calculated using the divided calibration clock period tcar and the raw values VALO VAL1 PRE CALI and CAL2 in accordan
17. be supplied by an externally generated crystal clock The crystal clock is divided by the internal calibration clock divider circuit Sleep Mode allows up to 1000x static current reduction TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 7 of 37 4 Packages Pin and Ball Configurations 4 1 Thin Quad Flat Package TQFP Figure 4 1 shows the TDC s Thin Quad Flat Package with either 100 pins TQFP100 14 x 14mm or 144 pins TQFP144 20 x 20mm The package dimensions are specified in Table 4 1 and Table 4 2 tz a MARKING WHO 123 Figure 4 1 Thin Quad Flat Package Tad en it oe IRE ma o5 15 oU 95 o typ 1400 140 050 022 060 16 00 ma 160 OIS 145 027 O75 7 Table 4 1 TQFP100 Package Dimensions mm pi A At A e 5 1 5 5 e 95 15 017 945 9 min typ 2000 140 050 022 060 22 00 max 160 015 L45 027 075 7 Table 4 2 TQFP144 Package Dimensions mm TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 8 of 37 4 2 Chip Scale Ball Grid Array csBGA Figure 4 2 shows the TDC s space saving Chip Scale Ball Grid Array with 100 balls csBGA100 8 x 8mm The package dimen
18. ce with the TDC s quantisation characteristic shown in Figure 5 2 as follows VALO OFFSET D t7 CAD2 CALI teat VALI OFFSET 2 Wau CADZ CALI toa 3 OFFSET 2 CALI CAL2 4 tre PRE t VALO VALI PRE 5 tres CAL2 CALI tear TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 15 of 37 5 4 General Measurement Cycle Figure 5 4 shows the flowchart of a general measurement cycle At the very beginning of a meas urement cycle the Calibration Clock Divider s division factor has to be specified within the TDC s Control Register The actual measurement cycle is initiated by setting one of three action bits to 1 within the Con trol Register Either a time measurement with or without a following automatic calibration meas urement will be activated or a stand alone calibration measurement will start Activating a time measurement the TDC is ready now for measurement and waits for a start signal on the start input START After start the time measurement stops when the stop signal hits the stop input STOP Now an automatic calibration measurement follows or not A stand alone calibration measurement will start immediately after setting the action bit to 1 If the time measurement and or calibration measurement are completed error free the VALID flag is set to 1 within the Status Register and at the TDC pi
19. ecsesessnsececececeesessnseceeececeeeesessaaeeeeeeeeeeseeas 33 9 9 1 General Power and Ground Recommendations eene 33 9 9 2 Decoupling Recommendations ies ese traer baa et t ndr anda qub den E adu REO RR TE YF dedu EN Tea ERR 33 9 10 MEASUREMENT RESUIDES 2 cci tr axes auda od eeu de end tds ocius EN pho EKR 34 9 10 1 X Singleshot Measurements and RMS Resolution see 34 9 10 2 Auto Noise Unit Effect on Measurement Errors esee 35 TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 4 of 37 1 Introduction MSC Vertriebs GmbH has many years of experience in the development of high precision Time to Digital Converters TDCs Our first TDC was developed in 1990 and implemented in a cost effec tive CMOS Gate Array technology This manual describes the TDC Mach330 an innovative PLD based Time to Digital Converter Designed specially for a programmable logic device of the Lattice MachXO family the TDC is born in our company s state of the art programming center tested and delivered to you in a 14x14mm TQFP100 a 20x20mm TQFP144 or an 8x8mm csBGA100 package each with 0 5mm pitch Supplied with 3 3V the TDC Mach330 achieves a typical resolution of up to 115ps LSB This resolution cannot be achieved using conventional FPGA or PLD based time measuring compo nents The integrated measurement principle allows hig
20. ee Yas i8 Ta p a 03 5 1 98 V cin ME e ee AEE Vo JOuputLowVolage 04 V Vou Output High Voltage Veaj V lo Output Low Current 0 0 0 8 m4 lo Output High Current 0 8 m4 Ie UO Active Pull up Curent 0 Va 97 Va 39 5 nA Ho W O Active Pull down Current Vi Max Va s Vg May 30 150 uA Max T4 25 C f 1 0MHz Max T4 25 C f 1 0MHz NOTES Over recommended Operation Conditions All I Os are LVCMOS 3 3V Icp amp 160uA MHz fcaycik Vcc 3 3V Table 9 2 Electrical Characteristics Ts Junction Temperature 125 C NOTE Stresses above these values may cause permanent damage to the device Table 9 3 Absolute Maximum Ratings TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 28 of 37 9 2 Resolution LSB 9 2 1 How to calculate the Resolution The TDC s resolution RES sp is calculated using the divided calibration clock period tcAr and the calibration values CAL1 and CAL2 A1 RESiss teat CAL2 CAL1 9 2 2 Voltage and Temperature Dependance Table 9 4 shows the supply voltage and ambient temperature dependance of the TDC s resolution arised from averaging the measured resolution of numerous TDCs Supply Voltage Resolution RES ss ps at T4 Vcc V 0 C 25
21. egister and the OV flag at the TDC pin OV are set to 1 Furthermore the ongoing time or calibration measurement is aborted immediately TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 19 of 37 6 3 Control and Status Register The width of both registers is 8 bit They are accessible via the processor interface see Chapter 6 5 For addressing the registers refer to Chapter 7 1 The Control Register is read and writeable The Status Register is read only For detailed informa tion on the individual register bits refer to Chapter 7 2 6 4 Raw Value Registers The TDC provides 5 read only raw value registers in which the measurement values VALO VAL1 and PRE and the calibration values CAL1 and CAL2 are stored for readout The width of all raw value registers is 16 bit The registers can be read out via the processor interface For addressing the raw value registers refer to Chapter 7 1 Please note that the raw values are valid only and can be read out only as long as the VALID flag is set to 1 6 5 Processor Interface The access to the Control and Status Register as well as the access to the raw value registers is controlled by the processor interface either via the Parallel Interface or the Serial Peripheral Interface SPI depending on pin EN_ SPI 0 Parallel Interface 1 SPI In addition to data and control lines the processor
22. er The external crystal clock CALCLK is divided by the Calibration Clock Divider The division fac tor is programmable and can be set to 1 2 4 and 8 CALCLK has to meet the following requirements 3MHz lt fcarc k lt 32MHz The divided calibration clock CLK is limited to 3MHz lt fcar lt 4MHz 6 2 Measurement Channel Figure 6 2 shows the block diagram of the measurement channel Enable Start Enable Stop START Start T TDC Core STOP Auto Noise CLK Unit Clock AN gt Enable Precounter P OV PRE PRE VALO VAL1 CAL1 CAL2 OV CORE Figure 6 2 Measurement Channel Block Diagram TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 17 of 37 6 2 1 Input Unit The Input Unit handles the incoming start stop and calibration clock signals The Input Unit de cides which signal START STOP or CLK has to be passed on as a start or stop signal to the TDC Core depending on the Control Register s action bits and on the partial step of the measure ment cycle If there is for example no action bit set to 1 within the Control Register then no incoming signal will be passed on to the TDC Core 6 2 2 Precounter The Precounter is enabled by the start signal and disabled by the stop signal of a time measurement It counts the clock periods tcar of the divided calibration clock CLK between the start signal and the stop
23. eriods are also treated as dead times TDCMach330RefManEng doc Version 1 2 Author AP MSC User Manual MSC TDC MACH 330 Page 32 of 37 9 7 1 Dead Time of a stand alone Time Measurement The dead time tror m of a time measurement without automatic calibration measurement is defined as the time period between the stop signal at the TDC pin STOP and the rising edge of the VALID flag at pin VALID The dead time tror m depends on the divided calibration clock period tear cp Chapter 5 2 Its maximum value is calculated as follows A5 tror M 1 5 tc 115ns 9 7 2 Dead Time of a stand alone Calibration Measurement When using the parallel interface the dead time tror c of a stand alone calibration measurement is defined as the time period between the rising edge of the write strobe at TDC pin WRN when acti vating the corresponding action bit within the Control Register and the rising edge of the VALID flag at pin VALID When using the SPI the dead time tror c is defined as the time period between the last falling SCK edge of the SPI cycle when writing the Control Register and the rising edge of the VALID flag at pin VALID The dead time tror c depends on the period tcr of the divided calibration clock cp Chapter 5 2 Its maximum value is calculated as follows A6 tror c 5 5 tcaL 130ns 9 7 3 Dead Time of a Time Measurement with autom Calibration Measurement The dead time tror mc of a time measure
24. f 37 Figure 6 6 shows the SPI cycle timing The associated timing characteristics are specified in Table 6 2 tL SSN lsck SCK lsckn tsu t tao SCK t vos 7777777 VITIS VITIS Y E YIII uso e m T lr Figure 6 6 SPI Cycle Timing 6 5 3 Flags Four flags VALID OV CORE OV PRE and OV are provided described in Table 6 3 AII flags are cleared to 0 on power on reset or by clearing the Control Register s action bits to 0 Flag Description No valid data for readout Status Register End of measurement Raw value registers contain and valid data for readout Pin VALID OV CORE 0 TDC Core is ok Status Register Overflow of TDC Core OV PRE Precounter is ok Status Register Overflow of Precounter OV TDC Core and Precounter are ok Pin OV Overflow of TDC Core or Precounter Table 6 3 Flags TDCMach330RefManEng doc Version 1 2 Author AP MSC User Manual MSC TDC MACH 330 Page 23 of 37 7 Programming of the TDC Mach330 7 1 Addressing 7 1 1 Parallel Interface Accessing the TDC s Control and Status Register and reading out the TDC s raw values is done via the Parallel Interface when pin EN SPI is 0 The relevant data is read and written via the bi directional data bus DATA 7 0 Addressing of all the registers shown in Table 7 1 is done via the address bus ADR 2 0 Each 16 bit raw value has to be read out by two consecutive read cycles on
25. h precision time difference measurement at very low prices The TDC Mach330 is perfectly suited for applications like distance measurement using laser phase measurement ultrasonic positioning temperature measurement etc which have been implemented successfully with our Gate Array based TDCs many times before Please contact us We are keen on satisfying your wishes TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 5 of 37 2 Features Channels one channel for Start Stop measurements consisting of one Start and one Stop input Both inputs trigger on rising edges Resolution LSB 115ps Vec 3 3V Ta 25 C Resolution RMS 250ps Vec 3 3V Ta 25 C Measurement range 1 5 tcar 100ns pn tCAL Calibration Clock external crystal clock required 3MHz lt cAL lt 4MHz Calibration measurement automatically after time measurement or stand alone Processor interface parallel interface 8 bit data 3 bit address serial interface 4 wire SPI flags for end of measurement and overflow Internal memory result of time measurement three 16 bit values result of calibration measurement two 16 bit values Configuration programmable via processor interface Measurement improvement Auto Noise Unit Technology Lattice MachXO PLD Voltage range Vcc 3 0V 3 6V Temperature range Ta 0 C 70 C Package TQFP100 14 x 14mm TQFP144 20 x 20mm or c
26. interface provides flags to indicate the end of a measurement and to indicate an overflow of the TDC Core or the Precounter 6 5 1 Parallel Interface 6 5 1 1 Data and Control Lines The Parallel Interface of the TDC Mach330 provides the following data and control lines e DATA 7 0 Bi directional data bus e CSN Chip select low active e RDN Read strobe low active e WRN Write strobe low active e ADR 2 0 Address bus In principle all controllers addressing a SRAM directly are connectable to the TDC s processor interface e g RENESAS H8 Controller TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 20 of 37 6 5 1 2 Timing Diagrams Figure 6 4 and Figure 6 5 show the read and write cycle timings The associated read and write cy cle timing characteristics are specified in Table 6 1 towr DATA T 0 1I IIK S WII LLL LLLLL D twrD RDN trowr twan twr WRN lcswn lwRcs CSN lapRwR ADP 2 0 g g MAL B BL BgLLLLUN NL LLL LLL LLL LEE lwRADR Figure 6 4 Write Cycle Timing tapos DATA 7 0 tappe WRN twarp tron tro RDN lcsnp i lacs tarp CSN ADR EO f I M LLLLLLUN XLII LLY LLL LLL LLL lapApR Figure 6 5 Read Cycle Timing TDCMach330RefManEng doc Version 1 2 tdc 2 msc ge com www msc ge com Author AP MSC User Manual MSC TDC MACH 330 Page 21 of 37
27. ment with automatic calibration measurement is defined as the time period between the stop signal at the TDC pin STOP and the rising edge of the VALID flag at pin VALID The dead time tror mc depends on the period tcr of the divided calibration clock cp Chapter 5 2 Its maximum value is calculated as follows A7 tror mc 7 tea 215ns Load 30pF TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 33 of 37 9 8 Power On Characteristics A MachXO PLD is SRAM based After switching on the power supply Vcc the device is config ured automatically as TDC by loading a program from its internal flash memory During this PLD configuration time all I Os are tri stated with an internal pull up resistor enabled After configura tion all TDC relevant I Os are activated and operate as shown in Table 4 3 The PLD configuration time is defined as the time period between reaching the minimum power supply Vcc 3 0V and the activation of the device I Os The maximum PLD configuration time is 600us After device configuration a low active power on reset pulse has to be performed at the TDC pin RSTN The pulse has to be 100ns at least After power on reset the TDC has its default settings Now a measurement cycle can be initiated by setting one of three action bits to 1 within the TDC s Control Register see Chapter 5 4 9 9 Board Layout Recommend
28. n VALID as well All the raw values of the cycle s measurements are ready for readout If a time or calibration measurement is not completed error free because of Start an overflow of the TDC Core or the Control Register Configuration of the clock divider s division factor Precounter then the OV CORE or OV PRE flag is set to 1 within the Control Register Setting of one of three action bits to 1 Status Register In addition the OV Time measurement Start Stop flag at the TDC pin OV is set to 1 In this case the raw value registers Calibration measurement VALID 1 Readout of raw values contain no valid data for readout Control Register Clearing of the action bit to 0 Figure 5 4 General Measurement Cycle Flow A general measurement cycle is fin ished by clearing the corresponding action bit to 0 In so doing all the flags are cleared to 0 and the raw values are not valid any more A following measurement cycle has to be initiated by setting one of three action bits to 1 once again TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 16 of 37 6 Functional Description 6 1 Calibration Clock Divider Figure 6 1 shows the principle function of the Calibration Clock Divider JUUUUUUUT 1 i DP E We CALCLK fi j CLK TLS Lh 1 4 1 8 Figure 6 1 Calibration Clock Divid
29. nate their TDCMach330RefManEng doc Version 1 2 Author AP MSC User Manual MSC TDC MACH 330 Page 36 of 37 quantisation errors Using the Auto Noise Unit results in an improved standard deviation because not only the quantization errors of the measurement values but also those of the calibration values are eliminated TDC Mach330 16x per Time Difference 9 to 10ps Increment 1ns auto Cal Clock 4MHz 3 3V no AN 14 Measurement Error ns 12 ln nei 04 02 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 Time ns Figure 9 4 Measurement Errors of average Measurement Results 16x without Auto Noise TDC Mach330 16x per Time Difference 9 to 10ps Increment 1ns auto Cal Clock 4MHz 3 3V AN 144 Measurement Error ns 12 SIA lg y 0 4 0 2 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 Time ns Figure 9 5 Measurement Errors of average Measurement Results 16x with Auto Noise TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 37 of 37 Figure 9 6 and Figure 9 7 show the TDC s measurement errors with 64 and 128 measurements per time difference using the Auto Noise Unit The standard deviation of the average measurement results is 054 3lps resp 012g 22ps TDC Mach330 64x per Time Difference 9 to 10p
30. nt Period The minimum and maximum measurement periods depend on the divided calibration clock period tcAL cp Chapter 5 2 and Chapter 6 1 9 4 1 Minimum Measurement Period As shown in Chapter 5 1 each time measurement is divided into three stages At the end of the first measurement stage the TDC Core has to be reactivated automatically for the third measurement stage Only after this time the TDC will detect a stop signal Therefore the minimum measurement period tmm of the TDC is A2 tyon 1 5 i tcaL 100ns Stop signals which don t meet the minimum measurement period are detected sometimes but not always As mentioned in Chapter 6 1 the maximum frequency of the divided calibration clock is limited to 4MHz Therefore an ultimate minimum measurement period of 475ns can be achieved 9 4 2 Maximum Measurement Period The maximum measurement period tmax is defined by the 15 bit wide Precounter A3 tuax tcAL As mentioned in Chapter 6 1 the minimum frequency of the divided calibration clock is limited to 3MHz Therefore an ultimate maximum measurement period of about 10 9ms can be achieved 9 5 Minimum Pulse Width of Start and Stop Signals The minimum pulse width t of signals on the start and stop inputs START and STOP is A4 ts 6ns The time t is relevant for both high and low level of the signals TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com tdc 2 msc ge com www m
31. nt result is getting smaller and smaller In practice however a satisfying accuracy will not be achieved if systematic errors are not eliminated or mini mized by averaging Figure 9 4 and Figure 9 5 show the TDC s measurement errors of the average measurement results from 16 measurements per time difference for a measurement period from 9 to 10us with an incre ment of Ins The measurements of Figure 9 4 are made without using the Auto Noise Unit the measurements of Figure 9 5 are made using the Auto Noise Unit In Figure 9 4 the standard deviation of the average measurement results is improved by almost 1 V16 from o 240ps singleshot standard deviation of Figure 9 3 down to o amp 61ps However using the Auto Noise Unit Figure 9 5 results in an even better standard deviation of o16 56ps The reason for this difference is the quantisation of the TDC Core s characteristic cp Chapter 6 2 3 If assuming that the start signal and the calibration clock are totally asynchronous to each other and that the stop signal and the calibration clock are asynchronous to each other as well then measuring exactly the same time difference many times will lead to different measurement values VALO and VALI each time If the Auto Noise Unit is not used then all associated calibration measurements will sample always the same quantisation stages So in contrast to VALO and VALI the calibration values CALI and CAL2 are always the same and averaging will not elimi
32. olytic capacitors to help eliminate low frequency coupling and maintain a low impedance power system e Use a large 220uF tantalum electrolytic capacitor at power source TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 34 of 37 9 10 Measurement Results 9 10 1 Singleshot Measurements and RMS Resolution Table 9 7 shows the singleshot standard deviation o also referred to as rms resolution depend ing on the power supply voltage Vcc In a normal distribution the so called one sigma area to contains about 68 of the singleshot measurement results About 95 596 will fall within the two sigma area 20 Power Supply Vcc V o ps Table 9 7 RMS Resolution o T4 25 C All singleshot standard deviations of Table 9 7 are averaged values derived from singleshot measurements of several TDCs at the following conditions Measurement period 9 10us Increment 1ns Sampling rate One measurement per measuring point Calibration clock fcar 4 MHz Automatic calibration measurement after time measurement Supply voltage 3 0V 3 3V and 3 6V Temperature approx 25 C Reference Universal Time Interval Counter SR620 Stanford Research Systems Figure 9 3 shows exemplarily the TDC s measurement errors of singleshot measurements for a measurement period from 9 to 10us at 3 3V The Universal Time Interval Counter SR620 RMS resolution
33. s Increment 1ns auto Cal Clock 4MHz 3 3V AN 14 Measurement Error ns 12 0 8 ohne IH gt Aut Annie 0 6 0 4 0 2 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 Time ns Figure 9 6 Measurement Errors of average Measurement Results 64x with Auto Noise TDC Mach330 128x per Time Difference 9 to 10ps Increment 1ns auto Cal Clock 4MHz 3 3V AN 14 Measurement Error ns 1 2 08 arctan lip ul Ae Mey Hy 0 6 0 4 0 2 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 Time ns Figure 9 7 Measurement Errors of average Measurement Results 128x with Auto Noise TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com
34. sBGA100 8 x 8mm each with 0 5mm pitch I Os LVCMOS 3 3V Outputs 8mA Sleep Mode Allows up to 1000x static current reduction fear I tca 4MHz TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 6 of 37 3 Block Diagram Figure 3 1 shows the block diagram of the TDC Mach330 Raw value Registers Processor IF VALID START OV Measurement STOP channel with MOSI TDC Core MISO and SCK Precounter SSN Calibration CALCLK clock divider ADR 2 0 DATA 7 0 RDN WRN RSTN Status Register CSN 4 SLEEPN EN SPI Figure 3 1 TDC Mach330 Block Diagram The TDC offers one Measurement channel with TDC Core and Precounter for time measure ments between one start and one stop signal The uncalibrated measurement values are stored in the Raw value registers Two flags indicate either the end of a measurement or an overflow of the TDC Core or Precounter After the end of a measurement the raw values have to be read out either parallel or serial via the Processor interface The calibration and calculation of the measurement s result has to be done outside the TDC e g by using a microcontroller The configuration of the TDC is done by writing the Control Register via the processor interface Status information can be accessed by reading the Status Register The calibration clock necessary for the calibration of the uncalibrated measurement values has to
35. sc ge com MSC User Manual MSC TDC MACH 330 Page 31 of 37 9 6 Timing when Activating a Time Measurement Figure 9 2 shows the timing of the TDC s pins SCK WRN and START when activating a time measurement via the parallel interface resp via the SPI by setting bit 0 or bit 1 to 1 within the Control Register In Table 9 6 the associated characteristics are specified SCK Writing the Control Register with the last falling SCK edge of the SPI cycle tscxs gt WRN Writing the Control Register lt twans START Figure 9 2 Timing when activating a Time Measurement waws Parallel IF Setup time for start detection 3 5 13 ms ltscxs___ SPI Setup time for start detection 55 20 ms Table 9 6 Timing Characteristics when activating a Time Measurement 9 7 Dead Times Due to the measurement principle the TDC Mach330 has got a dead time after the execution of a time measurement During this time period the start and stop detection of the TDC Core and the Precounter is disabled because of post processing and storing the measurement and precounter values into the raw value registers So reading out the TDC and initiating a new measurement cycle for another time and or calibration measurement before the end of dead time is unwise Due to the fact that the TDC s core and precounter are not available for time measurements during automatic or stand alone calibration measurements this time p
36. signal The width of the resulting precounter value PRE is 15 bit Therefore the maximum measurement period of the TDC is tmax 2 tcr cp Appendix 9 4 2 If the time difference the Precounter has to measure exceeds the maximum measurement period an overflow OV PRE will occur The OV PRE flag within the Status Register and the OV flag at the TDC pin OV are set to 1 Furthermore the ongoing time measurement is aborted including any automatic calibration measurement 6 2 3 Auto Noise Unit The characteristic of the TDC is a straight line with offset and upward gradient which due to the digital measurement procedure possesses quantisation stages so called LSBs Least Significant Bits with the width of the resolution For a single measurement one therefore gets a quantisation error of up to one quantisation stage at ideal quantisation This precision is sufficient for most ap plications A higher precision can be achieved when the measurement of the same time difference is repeated several times and statistical methods are used Changing the offset of the characteristic for each single measurement by delaying the stop signal according to Figure 6 3 causes sampling at different positions of the characteristic If the same off set is used for the time measurement and the associated calibration measurement the total offset is eliminated during the result calculation cp Chapter 5 3 When averaging all the single measure ment results
37. sions are also specified in Figure 4 2 Al EALL I D SI sss IDENTIFIER o 5 s E 14 13 12 11 10 9 9 5 4 3 2 1 N OOOOOOO OOOOOOO b PAS s eas SERI 0 0 amp D c NOTES UNLESS OTHERWISE SPECIFIED SYMBOL PER ANSI Y14 5M EET EN REESE RNC LET ON 8 00 BSC ALL DIMENSIONS ARE IN MILLIMETERS DIMENSION b IS MEASURED AT THE M N 6 50 BSC MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM PLANE ARE DEFINED BY THE SPHERICAL 0 50 BSC CROWNS OF THE SOLDER BALLS D L ow BILATERAL TOLERANCE ZONE IS APPLIED Dae ec EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL PPPP Figure 4 2 csBGA100 Package and Dimensions mm TDCMach330RefManEng doc Version 1 2 Author AP tdc msc ge com Wwww msc ge com MSC User Manual MSC TDC MACH 330 Page 9 of 37 4 3 Pin and Ball Configurations Table 4 3 Table 4 4 and Table 4 5 show the TDC s pin and ball configurations Pin resp ball names of low active signals end with N 80 88 90 92 EEPEERMIEEEEENN LEN 75 81 84 86 93 5 VALID Out 8mA 0 No valid data for readout 1 End of measurement Raw value registers contain valid data for readout 48 SLEEPN In internal pull up 0 Sleep mode 1 Normal mode i 8mA E In 0 parallel interface 1 SPI s MISO Tristate Out SA SPT Master in slave out When pin SSN z T misae 9 DATAS Bii SMA BIS dads
38. t all times it s maximum number is Ox 7fff 32767 To read out a complete raw value via the 8 bit processor interface two read cycles are necessary see Chapter 7 1 The raw value registers are not resettable so there default state is undefined after power on reset TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 26 of 37 8 Sleep Mode The TDC Mach300 provides a Sleep Mode that allows standby current to be reduced dramatically during periods of system inactivity Sleep Mode is controlled by the SLEEPN pin During Sleep Mode the TDC is not operational the contents of the registers is not maintained and the I Os are tristated In Sleep mode power supply is in its normal operating range eliminating the need for external switching of the power supply Table 8 1 compares the characteristics of Normal Mode Off Mode and Sleep Mode Characteristic Normal Mode Off Mode Sleep Mode SLEEPNpin high low Static Current Icc Ics 24mA typical 0 2IuA typical Supply Voltage Vcc normal range 0 mormalrange maintained not maintained see Table 9 2 Table 8 1 Characteristics of Normal Off and Sleep Modes Typically the TDC enters Sleep Mode several hundred nanoseconds after SLEEPN is held at a valid low and restarts normal operation as specified in Figure 8 1 The associated timing characteristics
39. the same address The first cycle reads out the low byte the second cycle reads out the high byte Address ADR 2 0 Register writable w hex bin readable r 0x00 000 CALI gt low byte first 0x01 001 CAL2 low byte first 0x02 010 VALO low byte first 0x03 011 VALI gt low byte first 0x04 100 PRE _ gt low byte first 0x05 101 0x06 110 STATUS_REG 0x07 111 CTRL REG Table 7 1 Register Addresses 7 1 2 Serial Peripheral Interface SPI Accessing the TDC s Control and Status Register and reading out the TDC s raw values is done via the SPI when pin EN SPI is 1 Master and TDC exchange their data via 8 bit data packets on the serial data lines MOSI and MISO sending the MSB at first and the LSB at last As shown is Table 7 2 the information for writing into or reading out the TDC is coded within the two upper most bits of a MOSI data packet Writing into the Control Register needs only one SPI cycle The lowest 6 bits of a MOSI data packet are clocked into the Control Register using the eighth last falling SCK edge of the cycle Reading out the TDC s Control and Status Register needs two SPI cycles Within the first cycle the lowest 6 bits of a MOSI data packet are used as register address Within the second cycle the data of the addressed register is transferred via line MISO Please make sure that SSN is set to 0 all the time between the two SPI cycles Reading out the T
40. then all their quantisation errors are averaged as well The different delays are generated by the pseudo random number generator of the Auto Noise Unit The delays are added to the already existing offset of the channel and can be changed every time you set the action bit clock auto noise to 1 within the Control Register The pseudo random number generator provides 64 different states each generating another delay The pseudo random number generator is cleared on power on reset only TDCMach330RefManEng doc Version 1 2 Author AP tdc 2 msc ge com www msc ge com MSC User Manual MSC TDC MACH 330 Page 18 of 37 Raw value Quantisation stage LSB width resolution VALO with ee ee ere C delay E i S p VALO Different offsets of mr Auto Noise Unit calibration CAL1 with clock period rd delay mu i CAL1 ae OFFSET with delay 4 Offset enlargement by delaying the stop signal OFFSET tcAL Figure 6 3 Influence of the Auto Noise Unit on the Characteristics of the TDC Core 6 2 4 TDC Core The TDC core determines the time difference between a start and a stop signal with a typical resolution of 115ps LSB The TDC Core stores the resulting measurement and calibration values in the raw value registers for readout If the time difference exceeds the TDC Core s typical maximum measurement period of about 4 2us an overflow will occur The OV CORE flag within the Status R
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