CATCH1 User Manual Update for VME Block Transfer 1 Changes
Contents
1. D01 1 Reset command D00 1 Trigger command PROG_FIFO 80 D31 D16 set FIFO flags PROG_FPGA 88 D07 D00 data transferred 01 enable programming pins 02 disable programming pins 04 set PROG pin to 0 08 set PROG pin to 1 10 set DIN pin to 1 20 set DIN pin to 0 40 set CCLK pin to 1 80 set CCLK pin to 0 REFRAME 98 D07 D00 no longer available BISTEN 90 D07 D00 no longer available RESET_FIFO CO reset FIFO buffer RESET_FPGA C8 reset Test Pulse Controller 2 Erratum Internal Scalers of the Test Pulse Controller In the actual design of the Test Pulse Control Unit the readout of the internal scalers for the four User Commands and Pattern Strobe does not work Thus each attempt to read out one of the scalers results in obtaining a value of zero A new revision of this design will be provided soon2. Compass Note 1999 9 CATCH1 A Test facility for COMPASS Front End Electronics User Manual Update for VME Block Transfer G Braun H Fischer J Franz A Grunemaier F H Heinsius K Konigsmann M Schierloh T Schmidt H Schmitt J Urban Fakultat fiir Physik Universitat Freiburg 79104 Freiburg Germany June 30 1999 1 Changes for addressing the CATCH1 The latest version of the CATCH1 s VME interface can handle block transfer requests to read front end data from the FIFO buffer As shown in the table below the READ_FIFO command s offset address changed to 8000 was 08 At this address the CATCHI1 responds to both single quad byte transfers and block transfers For the block transfer block sizes of up to 32 kByte are allowed Other changes concern the two commands REFRAME and BISTEN which are no longer available and the modules base address The two four bit rotary switches now are compared to the adress lines A23 A16 was A15 A08 which results in a range for possible base addresses from E000 0000 to EOFF 0000 Table 1 Offset addresses of the CATCH1 commands COMMAND OFFSET DATA WORD READ_ID 00 D31 D00 CATCHI1 identifier READ_FIFO 8000 D31 D00 three data words from the front end READ_STATUS 10 D15 D07 status bits READ_FPGA 18 D31 D16 scaler values WRITE_SERIAL 40 D23 D00 setup data to front end WRITE_FPGA 48 D31 D16 pattern pulse height WRITE TRIG 50 D03 1 User command D02 1 Clear command
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