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Z80 Family CPU User Manual - Thomas Scherrer Z80

1. 1 0 1 0 0 1 1 o A6 a d gt r identifies registers B C D E H L or A specified as follows in the assembled object code field above UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 153 Register r B 000 C 001 D 010 E 011 H 100 L 101 A 1711 Description A logical AND operation is performed between the byte specified by the s operand and the byte contained in the Accumulator the result is stored in the Accumulator Instruction M Cycles T States 4 MHz E T AND r 1 4 1 00 AND n 2 7 4 3 1 75 AND HL 2 7 4 3 1 75 AND IX d 5 19 4 4 3 5 3 4 75 AND IX d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set P V is reset if overflow reset otherwise N is reset C is reset Example If the B register contains 7BH 0111 1011 and the Accumulator contains C3H 1100 0011 at execution of AND B the Accumulator contains 43H 0100 0011 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 154 zitoc ORs Operation A lt Avs Op Code OR Operands s The s operand is any of r n HL X d or 1Y d as defined for the analogous ADD instructions These possible Op Code operand combinations are assembled as follows in the object code OR r 1 0 1 1 O a i gt ORn 1 1 1 1 0 1 1 0 F6
2. Oo 1 0j 0jj 04j 1 41 1 1 UM008004 1204 Z80 Instruction Set 220 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description RLD 1 1 1 oj1il1lo 1 ED oj 1f1 o 41 4 4 4 F The contents of the low order four bits bits 3 2 1 and 0 of the memory location HL are copied to the high order four bits 7 6 5 and 4 of that same memory location the previous contents of those high order four bits are copied to the low order four bits of the Accumulator register A and the previous contents of the low order four bits of the Accumulator are copied to the low order four bits of memory location HL The contents of the high order bits of the Accumulator are unaffected Note HL means the memory location specified by the contents of the HL register pair M Cycles T States 4 MHz E T 5 18 4 4 3 4 3 4 50 Condition Bits Affected S is set if Accumulator is negative after operation reset otherwise Z is set if Accumulator is zero after operation reset otherwise H is reset P V is set if parity of Accumulator is even after operation reset otherwise N is reset C is not affected UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 221 Example If the contents of the HL register pair are 5000H and the contents of the Accumulator and memory location 5000H
3. Logical Exclusive OR e Compare Leftor Right Shifts or Rotates Arithmetic and Logical e Increment e Decrement e Set Bit Reset Bit Test bit Instruction Register and CPU Control As each instruction is fetched from memory it is placed in the INSTRUCTION register and decoded The control sections performs this function and then generates and supplies the control signals necessary to read or write data from or to the registers control the ALU and provide required external control signals PIN DESCRIPTION Overview The Z80 CPU I O pins are illustrated in Figure 3 and the function of each is described in the following paragraphs UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG Mi aq A0 A1 MREQ lt gt A2 System Z ORQA lt A3 Control RD lt A4 we 22 AS AG 28 RFSH A7 Address A8 Bus HALT q A9 A10 wT y A11 CPU A12 Control INT 6 y Z80 CPU A13 mMm 7 y A14 A15 RESET 2 ye CPU BUSRA y us EASA 23 Control BUSACK lt DO D1 cK y D2 11 45V Fr D3 Data GND y D4 Bus D5 D6 D7 Figure 3 Z80 I O Pin Configuration Pin Functions A15 A0 Address Bus output active High tristate A15 AO form a 16 bit address bus The Address Bus provides the address for memory data bus exchanges up to 64 Kbytes and for I O device exchanges UM008004 1 204 Overview 8 Z80 CPU User s Manual ZiLOG BUSACK Bus Acknowledge output a
4. UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 186 ZiLOG INC IY Operation IY lt IY 1 Op Code INC Operands IY A a el eh a te 0 0 4 0 0 0 1 1 23 Description The contents of the Index Register IY are incremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If the contents of the Index Register are 2977H at execution of INC IY the contents of Index Register IY are 2978H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 187 DEC ss Operation ss lt ss 1 Op Code DEC Operands ss 0 0 s s 141 04 14 4 1 Description The contents of register pair ss any of the register pairs BC DE HL or SP are decremented Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE Ol HL 10 SP 11 M Cycles T States 4 MHz E T 1 6 1 50 Condition Bits Affected None Example If register pair HL contains 1001H at execution of DEC HL the contents of HL are 1000H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 188 ZiLoOG DEC IX Operation IX lt Ix 1 Op Code DEC Operands IX 1 1 0 1414 1 0 41 DD 0 0 1 0 1 0 1 1 2B Description The contents of Index Register IX are decremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bi
5. a d gt The contents of the Index Register IY register pair IY are added to a two s complement displacement integer d to point to an address in memory The contents of this address are then incremented M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if Y d was 7FH before operation reset otherwise N is reset C is not affected If the contents of the Index Register pair TY are 2020H and the memory location 2030H contain byte 34H at execution of INC IY 10H the contents of memory location 203 0H are 35H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 164 ZiLOG Operation m lt m 1 Op Code DEC Operands m DEC m The m operand is any of r HL X d or 1Y d as defined for the analogous INC instructions These possible Op Code operand combinations are assembled as follows in the object code DEC r DEC HL DEC IX d DEC IY d 0 o er i o 1 O 0 9 P O poe 4 35 1 4 0 1 1 14 0 417 0D o o 1 1 of 1fo 35 e 1 4 a 4 4 4 0 44 FD o oj 1 1 of1fo 3 a Lai r identifies registers B C D E H L or A assembled as follows in the obje
6. Description Integer n is loaded to the memory address specified by the contents of the HL register pair M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the HL register pair contains 4444H the instruction LD HL 28H results in the memory location 4444H containing byte 28H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 90 ZiLOG LD IX d n Operation IX d lt n Op Code LD Operands IX d n 111 0 1 1 1 0f1 DD 0101 1 0 1 1 0 36 a d gt a n gt Description The n operand is loaded to the memory address specified by the sum of the Index Register IX and the two s complement displacement operand d M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None Example If the Index Register IX contains the number 219AH the instruction LD 1X 5H 5AH results in byte 5AH in the memory address 219FH UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 91 LD IY d n Operation IY d lt n Op Code LD Operands lY d n 1 4 14 14 14 1440 4 14 FD 0 0 1 1 0 1 1 0 36 a d gt a n Description Integer n is loaded to the memory location specified by the contents of the Index Register summed with the two s complement displacement integer d M Cycles T States 4 MHz
7. Inc HL Dec BC ED Bl CPRI Inc HL Dec BC Repeat until BC 0 or find match ED A9 WD Dec HL and BC ED B9 CPDR Dec HL and BC Repeat until BC 0 or find match Note HL points to location in memory to be compared with accumulator contents BC Is byte counter Arithmetic and Logical Table 7 lists all the 8 bit arithmetic operations that can be performed with the accumulator also listed are the increment INC and decrement DEC UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z ZiLOG 59 instructions In all these instructions except INC and DEC the specified 8 bit operation is performed between the data in the accumulator and the source data The result of the operation is placed in the accumulator with the exception of compare CP that leaves the accumulator unchanged All these operations effect the flag register as a result of the specified operation INC and DEC instructions specify a register or a memory location as both source and destination of the result When the source operand is addressed using the index registers the displacement must follow directly With immediate addressing the actual operand follows directly For example the instruction AND 07H is Address A E6 Op Code A 1 07 Operand Assuming that the accumulator contained the value F3H the result of 03H is placed in the accumulator Accumulator before operatio
8. When BC is set to zero prior to instruction execution the instruction loops through 64 Kbytes For BC 0 M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is reset N is reset UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z ZiLOG 133 Example If the HL register pair contains 1114H the DE register pair contains 2225H the BC register pair contains 0003H and memory locations have these contents 1114H contains 1113H contains 1112H contains Then at execution of LDDR locations are HL contains DE contains DC contains 1114H contains 1113H contains 1112H contains UM008004 1204 A5H 2225H contains C5H 36H 2224H contains 59H 88H 2223H contains 66H the contents of register pairs and memory 1111H 2222H 0000H A5H 2225H contains A5H 36H 2224H contains 36H 88H 2223H contains 88H Z80 Instruction Set 134 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description CPI A HL HL lt HL 1 BC lt BC 1 CPI 1 1 1 0 1 1 0 1 ED 1 10 1 0 0 0 0 0 Al The contents of the memory location addressed by the HL register is compared with the contents of the Accumulator In case of a true compare a condition bit is set Then HL is incr
9. X d or 1Y d as defined for the analogous ADD instructions These possible Op Code operand combinations are assembled as follows in the object code CP r 1 0 1 1 1 a r gt CPn 0 a a a fa ae tae FE CP HL 1 0 1 14 414 1 444 0 BE CP IX d 1 4 o0 14 14 4 0 14 DD CP IY d 1 4 4 4 44 4707 4 FD d gt r identifies registers B C D E H L or A specified as follows in the assembled object code field above UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 159 Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The contents of the s operand are compared with the contents of the Accumulator If there is a true compare the Z flag is set The execution of this instruction does not affect the contents of the Accumulator Instruction M Cycles T States 4 MHz E T CPr 1 4 1 00 CP n 2 7 A 3 1 75 CP HL 2 7 4 3 1 75 CP X d 5 19 4 4 3 5 3 4 75 CP 1Y d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if borrow from bit 4 reset otherwise P V is set if overflow reset otherwise N is set C is set if borrow reset otherwise Example If the Accumulator contains 63H the HL register pair contains 6000H and memory location 6000H contains
10. 0 000000 02 eee 73 Table 20 Miscellaneous CPU Control 0 0 000005 73 UM008004 1 204 List of Tables Z80 CPU User s Manual xviii ziLoa List of Tables UM008004 1204 Z80 CPU User s Manual Z ZiLOG xix Manual Objectives This user manual describes the architecture and instruction set of the Z80 CPU About This Manual ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product However we recognize that users have different styles of learning some will want to set up and use their new evaluation kit while they read about it others will open these pages only to check on a particular specification Therefore we have designed this manual to be used either as a how to procedural manual or a reference guide to important data Intended Audience This document is written for ZiLOG customers who are experienced at working with microprocessors or in writing assembly code or compilers Manual Organization The Z80 CPU User s Manual is divided into four chapters Overview Presents an overview of the User s Manual Architecture Pin descriptions timing and Interrupt Response Hardware and Software Implementation Presents examples of the User s Manual hardware and software UM008004 1204 Manual Objectives XX User s Manual Z80 CPU ziLtoGc Z80 CPU Instruction Description Presents the User s Manual instruction types
11. C is not affected If the contents of the Accumulator are 1011 0100 at execution of CPL the Accumulator contents are 0100 1011 UM008004 1204 Z80 Instruction Set Operation Op Code Description Z80 CPU User s Manual ZiLOG 169 NEG 1 0 4 0 4 a fe EB 0 1 0 0 0 1 0 0 44 The contents of the Accumulator are negated two s complement This is the same as subtracting the contents of the Accumulator from zero Note that 80H is left unchanged M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is 0 reset otherwise H is set if borrow from bit 4 reset otherwise P V is set if Accumulator was 80H before operation reset otherwise N is set C is set if Accumulator was not 00H before operation reset otherwise If the contents of the Accumulator are 1 0 0 1 1 0 0 0 at execution of NEG the Accumulator contents are 0 1 14 0 1 0 00 UM008004 1204 Z80 Instruction Set 170 Z80 CPU User s Manual ZiLoG CCF Operation CY lt CY Op Code CCF 0 0 1 1 1 1 3F Description The Carry flag in the F register is inverted M Cycles 1 Condition Bits Affected S is not affected Z is not affected H previous carry is copied P V is not affected N is reset T Sta
12. INDR Operation HL lt C B 131 HL lt HL1 Op Code INDR 1111 1 0 ae ae ae 1 0 1 1 1 0 1 0 BA Description The contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B is used as a byte counter and its contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory Then HL and the byte counter are decremented If decrementing causes B to go to zero the instruction is terminated If B is not zero the PC is decremented by two and the instruction repeated Interrupts are recognized and two refresh cycles are executed after each data transfer When B is set to zero prior to instruction execution 256 bytes of data are input IfBz 0 M Cycles T States 4 MHZ E T 5 21 4 5 3 4 5 5 25 If B 0 M Cycles T States 4 MHZ E T 4 16 4 5 3 4 4 00 Condition Bits Affected S is unknown Z is set H is unknown P V is unknown N is set UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z 278 ZiLOG C is not affected Example If the contents of register C are 07H the contents of register B are 03H the contents of
13. Z80 Family CPU User Manual User Manual UM008004 1204 ZiLOG Worldwide Headquarters 532 Race Street e San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com Z80 CPU User s Manual Z ZiLOG This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2004 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized No licenses are conv
14. d Mi Port A Port B O D Output Data Input Data Figure 1 Minimum Z80 Computer System Because the Z80 CPU requires only a single 5V power supply most small systems can be implemented using only this single supply The external memory can be any mixture of standard RAM ROM or PROM In Figure 1 a single 8K bit ROM 1 Kbytes comprises the entire memory system The Z80 internal register configuration contains sufficient Read Write storage requiring no external RAM memory TO circuits allow computer systems to interface with the external devices In Figure 1 the output is an 8 bit control vector and the input is an 8 bit status word The input data can be gated to the data bus using any standard three state driver while the output data can be latched with any type of stan dard TTL latch A Z80 PIO serves as the I O circuit This single circuit attaches to the data bus as indicated and provides the required 16 bits of TTL compatible I O Refer to the Z80 CPU Peripherals User s Manual for details on the operation of this circuit This powerful computer is built with only three LSI circuits a simple oscillator and a single 5V power supply UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual Z ZiLOG 29 Adding RAM Most computer systems require some external Read Write memory for data storage and stack implementation Figure 2 illustrates how 256 bytes of static memory are added to the prev
15. multiplicand in hl 4 5 on exit result in hl 6 7 register uses 8 a 9 10 h high order partial result 11 l low order partial result 12 d high order multiplicand 13 e low order multiplicand 14 b counter for number of shifts 15 c high order bits of multiplier UM008004 1204 Hardware and Software Implementation Examples 39 Z80 CPU User s Manual 40 ZiLOG Table 2 Multiply Listing Continued Obj Loc Code Stmt Source Statement 16 a low order bits of multiplier 17 5 0000 0610 18 ld b 16 number of bits initialize 0002 4a 19 ld c d move multiplier 0003 7b 20 ld a 0004 leb 21 ex de hl move multiplicand 0005 210000 22 ld hl 0 clear partial result 0008 cb39 23 mloop srl c shift multiplier right 000a lif 24 rra least significant bit is 25 in carry 000b 3001 26 je nc noadd if no carry skip the add good 19 27 add hl de else add multiplicand to 28 a partial result 000e leb 29 noadd ex de h l shift multiplicand left goof 29 30 add hl hl by multiplying it by two 0010 eb 31 ex de hl 0011 10f5 32 djnz mloop repeat until no more bits 0013 c9 33 ret 34 end UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual ZiLOG 41 Z80 CPU Instruction Description Overview The Z80 CPU can execute 158 different instruction types including all 78 of the 8080A CPU The inst
16. 1 4 4 14 4 41 0 7 14 4 FD 1 1 0 0 1 0 1 1 CB a d gt 1 1 a b gt 11 0 Description Bit b in the memory location addressed by the sum of the contents of the TY register pair and the two s complement displacement d is set Operand b is specified as follows in the assembled object code Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 iri M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected None Example If the contents of Index Register IY are 2000H at execution of SET 0 IY 3H bit0 in memory location 2003H is 1 Bit 0 in memory location 2003H is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 236 ZiLOG RES b m Operation sb lt 0 Op Code RES Operands b m Operand b is any bit 7 through 0 of the contents of the m operand any of r HL IX d or Y d as defined for the analogous SET instructions These possible Op Code operand combinations are assembled as follows in the object code RES b rn 1 1 0 0 1 0 1 1 CB RES b HL f 4 0 O Y 0 a a CB RES b IX d 1 1 0 1 1 1 0 14 DD RES b IY d 1 4 1441 1 1 01141 FD UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 237 B
17. 3 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise R is set if carry out of bit 11 reset otherwise P V is set if overflow reset otherwise N is reset C is set if carry from bit 15 reset otherwise If the register pair BC contains 2222H register pair HL contains 5437H and the Carry Flag is set at execution of ADC HL BC the contents of HL are 765AH UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 181 SBC HL ss Operation HL lt HI ss CY Op Code SBC Operands HL ss Description The contents of the register pair ss any of register pairs BC DE HL or SP and the Carry Flag C flag in the F register are subtracted from the contents of register pair HL and the result is stored in HL Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if a borrow from bit 12 reset otherwise P V is set if overflow reset otherwise N is set C is set if borrow reset otherwise Example If the contents of the HL register pair are 9999H the contents of register pair DE are 1111H and the Carry flag is set At execution of SBC HL DE the content
18. B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None Example If the C register contains byte 1CH and the Index Register IX contains 3100H then the instruction LID IX 6H C performs the sum 3100H 6H and loads 1CH to memory location 3106H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 88 ZiLoG LD IY d r Operation lY d lt r Op Code LD Operands lY d r 1 at a a deh ge ah 0 1 1 1 0 q r p A d p Description The contents of resister r are loaded to the memory address specified by the sum of the contents of the Index Register IY and d a two s complement displacement integer The symbol r is specified according to the following table Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None Example If the C register contains byte 48H and the Index Register IY contains 2A11H then the instruction LD IY 4H C performs the sum 2A11H 4H and loads 48H to memory location 2A15 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 89 LD HL n Operation HL lt n Op Code LD Operands HL n 0 o 1 14 0 1 41 0 36 et n Pe
19. HL 1 1 0 0 141 0 1 1 CB 1 1 a b a r gt Description Bit b in the memory location addressed by the contents of register pair HL is set Operand b is specified as follows in the assembled object code Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 iri M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected None Example If the contents of the HL register pair are 3000H at execution of SET 4 HL bit 4 in memory location 3000H is 1 Bit 0 in memory location 3000H is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 234 ZiLOG SET b IX d Operation IX d b 1 Op Code SET Operands b IX d Description Bit b in the memory location addressed by the sum of the contents of the IX register pair and the two s complement integer d is set Operand b is specified as follows in the assembled object code Bit Tested b 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 y 6 M Cycles T States 4 MHz E T 23 4 4 3 5 4 3 5 75 Condition Bits Affected None Example If the contents of Index Register are 2000H at execution of SET 0 IX 3H bit 0 in memory location 2003H is 1 Bit 0 in memory location 2003H is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 235 SET b IY d Operation IY d b lt 1 Op Code SET Operands b Y d
20. Indexed Rest DD FD ae 0 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 87 80 81 82 83 84 85 86 d d 86 86 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 8F 88 89 8A 88 8C 8D 8E d d 8E 8E DD FD 2 C8 C8 CS C8 C8 C8 C8 C8 C8 C8 97 90 91 92 93 94 95 96 d d 96 96 DD FD 3 C8 C8 C8 C8 CS C8 C8 C8 C8 C8 OF 98 99 9A 98 90 90 9E d d 9E 9E DD FD 4 C8 C8 C8 C8 C6 C8 C8 C8 C8 C8 A7 AO AI A2 A3 A4 A5 A6 d d A6 A6 DD FD 5 C8 C8 C8 C8 08 C8 C8 C8 C8 C8 AF A8 A9 AA AB AC AD AE d d AE AE DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 B7 BO B1 82 B3 B4 B5 B6 d d B6 B6 DD DD 7 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 BF B8 89 8A B8 8C BD 9E d d BE BE UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual 68 ErEOG Table 11 Bit Manipulation Group Continued Register Addressing Reg Indir Indexed Set DD FD a 0 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 C7 CO C1 C2 C3 C4 C5 C6 d d C6 C6 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 CF C8 c9 CA C8 CC CD CE d d CE CE DD FD 2 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 D7 DO D1 D2 D3 D4 DS D6 d d D6 D6 DD FD 3 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 DF D8 09 DA DS DC DD DE d d DE DE DD FD 4 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 E7 EO El E2 E3 E4 E5 E6 d d E6 E6 DD FD 5 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 EF E8 E9 EA EB EC ED EE d d EE EE DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 F7 FO Fl F2 F3 F4 FS F6 d d F6 F6 DD FD 7 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 FF
21. M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is reset N is reset C is not affected UM008004 1204 Z80 Instruction Set 130 Z80 CPU User s Manual ZiLOG Example If the HL register pair contains 11111H the DE register pair contains 2222H the BC register pair contains 0003H and memory locations have these contents 1111H contains 1112H contains 1113H contains 88H 2222H contains 66H 36H 2223H contains 59H A5H 2224H contains C5H then at execution of LDIR the contents of register pairs and memory locations are HL DE BC 11118 1112H 1113H contains contains contains contains contains contains UM008004 1204 1114H 2225H 0000H 88H 2222H contains 88H 36H 2223H contains 36H A5H 2224H contains A5H Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 131 LDD DE amp HL DE DE 1 HL 4 HL 1 BC lt BC 1 LDD 1 1 1 0 1 1 0 1 ED 1 0 1 0 1 0 0 0 A8 This 2 byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both of these register pairs including the BC Byte C
22. The B register is decremented and if a non zero value remains the value of the displacement e is added to the Program Counter PC The next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction Op Code and has a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the result of decrementing leaves B with a zero value the next instruction executed is taken from the location following this instruction if B 0 M Cycles T States 4 MHz E T 3 13 5 3 5 3 25 If B 0 M Cycles T States 4 MHz E T 2 8 5 3 2 00 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z 254 ZiLOG Example A typical software routine is used to demonstrate the use of the DJNZ instruction This routine moves a line from an input buffer INBUF to an output buffer OUTBUF It moves the bytes until it finds a CR or until it has moved 80 bytes whichever occurs first LD 8 80 Set up counter LD HL Inbuf Set up pointers LD DE Outbuf LOOP LID A HL Get next byte from jinput buffer LD DE A Store in output buffer CP ODH jIs it a CR JR Z DONE Yes finished INC HL Increment pointers INC DE DJNZ LOOP Loop back if 80 bytes have not been moved DONE UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 255 Call And Return Group CALL nn
23. Z80 CPU User s Manual 266 ZiLOG 1000H The program flow continues where it left off with an Op Code fetch to address 1A45H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 267 RST p Operation SP 1 lt PCH SP 2 lt PCL PCH lt 0 PCL lt P Op Code RST Operands p 1 1 t gt 1 1 1 Description The current Program Counter PC contents are pushed onto the external memory stack and the page zero memory location given by operand p is loaded to the PC Program execution then begins with the Op Code in the address now pointed to by PC The push is performed by first decrementing the contents of the Stack Pointer SP loading the high order byte of PC to the memory address now pointed to by SP decrementing SP again and loading the low order byte of PC to the address now pointed to by SP The Restart instruction allows for a jump to one of eight addresses indicated in the table below The operand p is assembled to the object code using the corresponding T state Because all addresses are in page zero of memory the high order byte of PC is loaded with 00H The number selected from the p column of the table is loaded to the low order byte of PC p t 00H 000 08H 001 10H 010 18H 011 20H 100 28H 101 30H 110 38H ii M Cycles T States 4 MHz E T 3 11 5 3 3 2 75 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 268 ZiLOG Example If t
24. Z80 CPU User s Manual Z zitoa 287 Condition Bits Affected Example S is unknown Z is set H is unknown P V is unknown N is set C is not affected If the contents of register C are 07H the contents of register B are 03H the contents of the HL register pair are 1000H and memory locations have the following contents OFFEH contains 51H OFFFH contains A9H 1000H contains 03H then at execution of OTDR the HL register pair contain OF FDH register B contains zero and a group of bytes is written to the peripheral device mapped to I O port address 07H in the following sequence 03H A9H 51H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 288 ZiLOG UM008004 1204 Z80 Instruction Set
25. accumulator with itself Table 9 lists all the 16 bit arithmetic operations between 16 bit registers There are five groups of instructions including add with carry and subtract with carry ADC and SBC affect all the flags These two groups simplify address calculation operations or other 16 bit arithmetic operations Table 7 8 Bit Arithmetic and Logic Source Register Addressing Reg Indir Indexed Immed A B C D JE F L_ AL IX d 1Y d ADD so s1 82 FD 86 d ADD W CARRY FD ADC 8E d SUBTRACT FD SUB 96 d SUB w CARR FD SBC 9E d AND FD A6 d XOR FD AE d UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z ZiLOG Table 7 8 Bit Arithmetic and Logic Source Register Addressing Indexed COMPARE CP INCREMENT INC DECREMENT FD DEC Table 8 General Purpose AF Operation Decimal Adjust Acc DAA Complement Acc CPL Negate Acc NEG 2 s complement Complement Carry Flag CCF Set Carry Flag SCF Table 9 16 Bit Arithmetic UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual 62 ZiLOG Table 9 16 Bit Arithmetic Destination Source HL ADD IX DD DD DD DD 09 19 39 29 IY FD FD FD FD 09 19 39 29 ADD with carry and set flags ADC HL ED ED ED ED 4A 5A 6A 7A SUB
26. addressing modes and instruction Op Codes Z80 Instruction Set Presents an overview of the User s Manual assenbly language status indicator flags and the Z80 instructions Related Documents Part Number Title DC number Part Number Title DC number Part Number Title DC number Manual Conventions The following assumptions and conventions are adopted to provide clarity and ease of use Use of the Words Set and Clear The words set and clear imply that a register bit or a condition contains the values logical 1 and logical 0 respectively When either of these terms is followed by a number the word logical may not be included but it is implied Notation for Bits and Similar Registers A field of bits within a register is designated as Register n n For example PWM_CR 31 20 A field of bits within a bus is designated as Busp n For example PCntl7_4 A range of similar whole registers is designated as Registern Registern For example OPBCS5 OPBCSO UM008004 1204 Manual Objectives Z80 CPU User s Manual ZiLoG Xxi Use of the Terms LSB and MSB In this document the terms LSB and MSB when appearing in upper case mean least significant byte and most significant byte respectively The lowercase forms msb and lsb mean least significant bit and most significant bit respectively Courier Font Commands code lines and fragments register and other mnemonics values equations and various executab
27. register pair PC is loaded with the contents of the IX Register Pair The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Example If the contents of the Program Counter are 1000H and the contents of the IX Register Pair are 4800H at execution of JP IX the contents of the Program Counter are 4800H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 252 ZiLOG JP IY Operation PC lt IY Op Code JP Operands IY 1 4 4 4 4 44 1440 4147 FD 1 1 1 0 1 0 0 1 E9 Description The Program Counter register pair PC is loaded with the contents of the TY Register Pair The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Example If the contents of the Program Counter are 1000H and the contents of the TY Register Pair are 4800H at execution of JP IY the contents of the Program Counter are 4800H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 253 DJNZ e Operation Op Code DJNZ Operands e 0 0 0 1 0 0 0 o 10 lt a e 2 a Description This instruction is similar to the conditional jump instructions except that a register value is used to determine branching
28. request is not accepted until after the instruction following EI is executed This single instruction delay is necessary when the next instruction is a return instruction Interrupts are not allowed until a return is completed The EI instruction sets both IFF1 and IFF2 to the enable state When the CPU accepts a maskable interrupt both IFF1 and IFF2 are automatically reset inhibiting further interrupts until the programmer issues a new El instruction Note that for all of the previous cases IFF1 and IFF2 are always equal The purpose of IFF2 is to save the status of IFF1 when a non maskable interrupt occurs When a non maskable interrupt is accepted IFF1 resets to prevent further interrupts until reenabled by the programmer Thus after a non maskable interrupt is accepted maskable interrupts are disabled but the previous state of IFF1 has been saved so that the complete state of the CPU just prior to the non maskable interrupt can be restored at any time When a Load Register A with Register I LDA I instruction or a Load Register Awith Register R LDA R instruction is executed the state of IFF2 is copied to the parity flag where it can be tested or stored A second method of restoring the status of IFF1 is through the execution of a Return From Non Maskable Interrupt RETN instruction This instruction indicates that the non maskable interrupt service routine is complete and the contents of IFF2 are now copied back into IFF1 so that the
29. status of IFF1 just prior to the acceptance of the non maskable interrupt is restored automatically Table 1 is a summary of the effect of different instructions on the two enable flip flops Table 1 Interrupt Enable Disable Flip Flops 23 Action IFF1 IFF2 Comments CPU Reset UM008004 1204 0 0 Maskable Interrupt INT Disabled Overview Z80 CPU User s Manual 24 ZiLOG Table 1 Interrupt Enable Disable Flip Flops Action IFF1 IFF2 Comments DI Instruction Execution 0 0 Maskable INT Disabled EI Instruction Execution 1 1 Maskable INT Enabled LD A I Instruction Execution IFF2 gt U Parity Flag LD A R instruction Execution IFF2 gt U Parity Flag Accept NMI 0 Maskable Interrupt RETN Instruction Execution IFF2 IFF2 indicates completion of non maskable interrupt service routine CPU Response Non Maskable The CPU always accepts a non maskable interrupt When this occurs the CPU ignores the next instruction that it fetches and instead performs a restart to location 0066H The CPU functions as if it had recycled a restart instruction but to a location other than one of the eight software restart locations A restart is merely a call to a specific address in page 0 of memory The CPU can be programmed to respond to the maskable interrupt in any one of three possible modes Mode 0
30. 1 DD RRC IY d 1 1 1 1 1 1 0 1 FB UM008004 1204 Z80 Instruction Set 206 Z80 CPU User s Manual ZiLOG r identifies registers B C D E H L or A assembled as follows in the object code field above Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The contents of the m operand are rotated right 1 bit position The content of bit 0 is copied to the Carry flag and also to bit 7 Bit 0 is the least significant bit Instruction M cycles T States RRCr 2 8 4 4 RRC HL 4 15 4 4 4 3 RRC IX d 6 23 4 4 3 5 4 3 RRC 1Y d 6 23 4 4 3 5 4 3 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is data from bit 0 of source register Example If the contents of register A are 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 4 Miz E T 2 00 3 75 5 75 5 75 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 207 at execution of RRC A the contents of register A and the Carry flag are UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 208 ZiLOG RR m Operation Op Code RR Operands
31. 215 r identifies registers B C D E H L or A assembled as follows in the object code field above Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description An arithmetic shift right 1 bit position is performed on the contents of operand m The content of bit 0 is copied to the Carry flag and the previous content of bit 7 is unchanged Bit 0 is the least significant bit Instruction M Cycles T States 4 MHz E T SRA r 2 8 4 4 2 00 SRA HL 4 15 4 4 4 3 3 75 SRA IX d 6 23 4 4 3 5 4 3 5 75 SRA lY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity is even reset otherwise N is reset C is data from bit 0 of source register Example If the contents of the Index Register IX are 1000H and the contents of memory location 1003H are 7 6 5 4 3 2 1 0 1 0j 1 1 1 0 0 0 UM008004 1204 Z80 Instruction Set 216 Z80 CPU User s Manual ZiLOG at execution of SRA IX 3H the contents of memory location 1003H and the Carry flag are 7 6 5 4 3 2 1 1 1 0 1 1 1 0 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 217 SRL m Operation 0o 7 o cy Op Code SRL Operands m The operand m is any of r HL X d or 1Y d as defi
32. CPU User s Manual ZiLOG 275 IND Operation HL lt C B B 1 HL lt HL 1 Op Code IND 1 1 11 0 1 1 O0OJ 1 ED 1 0J 1 0 1 0 1 0 AA Description The contents of register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports Register B may be used as a byte counter and its contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory Finally the byte counter and register pair HL are decremented UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 276 ZiLOG M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected S is unknown Z is set if B 1 0 reset otherwise H is unknown P V is unknown N is set C is not affected Example If the contents of register C are 07H the contents of register B are 10H the contents of the HL register pair are 1000H and byte 7BH is available at the peripheral device mapped to I O port address 07H At execution of IND memory location 1000H contains 7BH the HL register pair contains OFFFH and register B contains OFH UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 277
33. Condition Bits Affected None Example If the Index Register IX contains 5A3 0H at instruction LD 4392H IX memory location 4392H contains number 30H and location 4393H contains 5AH UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 112 ZiLOG LD nn IY Operation nn 1 lt IYh nn lt IYI Op Code LD Operands nn IY 1 4 14 14 4 41 0 14 FD 0 0 1 0 01 01 0 22 lt a n a at n gt Description The low order byte in Index Register IY is loaded to memory address nn the upper order byte is loaded to memory location nn 1 The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If the Index Register IY contains 4174H at instruction LD 8838H IY memory location 8838H contains number 74H and memory location 8839H contains 41H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 113 LD SP HL Operation SP lt HL Op Code LD Operands SP HL A ge ee eee Description The contents of the register pair HL are loaded to the Stack Pointer SP M Cycles T States 4 MHz E T 1 6 1 5 Condition Bits Affected None Example If the register pair HL contains 442EH at instruction LD SP HL the Stack Pointer also contains 442EH UM008004 1204 Z80 Instruction Set Z
34. E 160 NG SS ae tone oad cust eh sath tree hd bet hus dist ts a a r 184 IND prenie seteirs debts EAEN EEA A E Aa eae E EER ware ake 275 INDR teh cots eneeia u eE aad EEE Beaded dan hed aS aa 277 Nee os eto ete eee tees peace acetates eat 272 INIR irre yt tesa Pte atone ache deve causa ave tetas ana datasheet tua 273 JP HL coed iste died Be A ast te dSude N Bue a E da ah Dats ake A Bese 250 SPT oso io sty tacos tee ey a oes tes ctor E tone woe aera A EET decay dren eh 251 PLY o o aa E dosent oh bras EEEE E Bone dea ides TEREA wate ease 252 JP Ce Dii segs A misa raa hae eked ed EN E R eae dad d 239 JENN ects ioe a eh ace dona a dt ed co a decays staan 238 PREC SG ethic eel ts dota a a a a aed Sates cae ean 242 DRS seeped arae po arene aise tec Wtonewn alae Rim anaes EEO ia NRS 241 IRE ING ery ti teense bts coarse EE A E S Bios Gone wane ees 244 IR NZ O a ast e sessed IER a E e oases acetate ak eae dan ate danas 248 IRZ e 2 ink a8 savas erat sack Gana ted a date av wets eens alone ets 246 List of Instructions UM008004 1204 LD BC A LD DE A LD HL n LD HL r LD I X d n LD I X d r LD IY d n LD IY d r LD nn A LD nn dd LD nn HL LD nn IX LD nn IY LD A BC LD A DE LD LA LD IY nn LD IY nn LD r HL LD r X d LD r Y d LDR A UM008004 1204 Z80 CPU User s Manual ZitoG List of Instructions xi xii Z80 CPU User s Manual ZiL LOG LD SP IY eeccrinicri
35. F8 F9 FA FB FC FD FE d d FE FE UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z ZiLOG Table 12 Jump Call and Return Group Condition Un Carry Non Zero Non Parity Parity Sign Sign Reg Cond Carry Zero Even Odd Neg Pos Bz0 JUMP JP IMMED nn EXT JUMP JR RELATIVE PC e 18 38 30 28 20 e 2 e 2 e 2 e 2 e 2 JUMP JP Register HL INDIR ax IDD E9 dY FD E9 CALL IMMED nn EXT Decrement B Jump RELATIVE PC e 10 If Non Zero DINZ e 2 Return RE REGISTER SP Return From INDIR SP 1 ED INT RETI 4D Return From ED Non Maskable 45 INT RETN The instruction DJNZ is used to facilitate program loop control This two byte relative jump instruction decrements the B register and the jump occurs if the B register has not been decremented to zero The relative displacement is expressed as a signed two s complement number A simple example of its use is Address Instruction Comments N N 1 LD B 7 set B register to count of 7 N 2 to N 9 Perform a sequence of instructions loop to be performed 7 times N 10 N 11 DJNZ 8 to jump from N 12 to N 2 N 12 Next Instruction UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual 70 ZiLOG Table 13 lists the eight Op Codes for the restart instruction This instruction is a single byte
36. FD 1 1 1 0 0 0 1 1 E3 Description The low order byte in Index Register IY is exchanged with the contents of the memory address specified by the contents of register pair SP Stack Pointer and the high order byte of IY is exchanged with the next highest memory address SP 1 M Cycles T States 4 MHz E T 6 23 4 4 3 4 3 5 5 75 Condition Bits Affected None Example If the Index Register IY contains 3988H the SP register pair contains 0100H memory location 0100H contains byte 90H and memory location 0101H contains byte 48H then the instruction EX SP IY results in the TY register pair containing number 4890H memory location 0100H containing 88H memory location 0101H containing 39H and the Stack Pointer containing 0100H UM008004 1204 Z80 Instruction Set 128 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description LDI DE lt HL DE lt DE 1 HL HL 1 BC BC 1 LDI SP HL 1 1 1lo0oj1 1 o 1 ED 1 01 0 0 0 0 0 AD A byte of data is transferred from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both these register pairs are incremented and the BC Byte Counter register pair is decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected
37. HL register pair are 4343H and the contents of memory location 4343H and the Carry flag are 7 6 5 4 3 2 1 0 C 1 1 0 1 1 1 0 1 0 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 210 ZiLOG at execution of RR HL the contents of location 4343H and the Carry flag are 7 6 5 4 8 2 1 0 C 0 1 1 0 1 1 1 0 1 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 211 SLA m Operation CY a 7 4 0 0 Op Code SLA Operands m The m operand is any of r HL X d or 1Y d as defined for the analogous RLC instructions These possible Op Code operand combinations are specified as follows in the assembled object code SLAr 1 14 0 04 1 041 14 4 CB SLA HL 1 1 0 0 1 0 1 41 CB SLA IX d 1 1 0 1 1 1 0 1 DD SLA IY d 111 1 4 44 4 0 7 4 FD UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 212 ZiLOG r identifies registers B C D E H L or A assembled as follows in the object code field above Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description An arithmetic shift left 1 bit position is performed on the contents of operand m The content of bit 7 is copied to the Carry flag Bit 0 is the lea
38. O operations the time from when the IORQ signal goes active until the CPU must sample the WAIT line is very short Without this extra state sufficient time does not exist for an I O port to decode its address and activate the WAIT line if a wait is required Also without this wait state it is difficult to design MOS I O devices that can operate at full CPU speed During this wait state time the WAIT request signal is sampled During a read I O operation the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read For I O write operations the WR line is used as a clock to the I O port UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG Automatically inserted WAIT state Figure 7 Input or Output Cycles Bus Request Acknowledge Cycle Figure 8 illustrates the timing for a Bus Request Acknowledge cycle The BUSREQ signal is sampled by the CPU with the rising edge of the last clock period of any machine cycle If the BUSREQ signal is active the CPU sets its address data and tristate control signals to the high impedance state with the rising edge of the next clock pulse At that time any external device can control the buses to transfer data between memory and I O devices This operation is generally known as Direct Memory Access DMA using cycle stealing The maximum time for the CPU to respond to a bus request is the length of a machine cycle and the external cont
39. One Wait State to an M1 Cycle UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual ZiLOG 31 Figure 4 Adding One Wait State to Any Memory Cycle Interfacing Dynamic Memories Each individual dynamic RAM has it s own specifications that require minor modifications to the examples given here ZiLOG Application Notes are available describing how the Z80 CPU is interfaced with most popular dynamic RAM Figure 5 illustrates the logic necessary to interface 8 Kbytes of dynamic RAM using 18 pin 4K dynamic memories This logic assumes that the RAMs are the only memory in the system so that A12 is used to select between the two pages of memory During refresh time all memories in the system must be read The CPU provides the correct refresh address on lines AO through A6 When adding more memory to the system it is necessary to replace only the two gates that operate on A12 with a decoder that oper ates on all required address bits Address buffers and data bus buffers are generally required for larger systems UM008004 1 204 Hardware and Software Implementation Examples Z80 CPU User s Manual 32 ZiLOG 4K x 8 RAM Array Page 1 1000 to 1FFFF 4K x 8 RAM Array Page 0 0000 to OFFFF Figure 5 Interfacing Dynamic RAMs UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual ZiLOG 33 SOFTWA
40. Register B may be used as a byte counter and its contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are then placed on the address bus and the input byte is written to the corresponding location of memory Finally the byte counter is decremented and register pair HL is incremented M Cycles T States 4 MHZ E T 4 16 4 5 3 4 4 00 Condition Bits Affected Example S is unknown Z is set if B 1 0 reset otherwise H is unknown P V is unknown N is set C is not affected If the contents of register C are 07H the contents of register B are 10H the contents of the HL register pair are 1000H and byte 7BH is available at the peripheral device mapped to I O port address 07H At execution of INI memory location 1000H contains 7BH the HL register pair contains 1001H and register B contains OFH UM008004 1204 Z80 Instruction Set Operation Op Code Description Z80 CPU User s Manual ZiLOG INIR HL C B B 1 HL lt HL 1 INIR 111l ol1 1 oj 1 ED 11 101 1 0 01 0 B2 The contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B is used as a byte counter and its contents are placed on the top half A8 through A1
41. This mode is similar to the 8080A interrupt response mode With this mode the interrupting device can place any instruction on the data bus and the CPU executes it Thus the interrupting device provides the next instruction to be executed Often this is a restart instruction because the interrupting device only need supply a single byte instruction Alternatively any other UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG 25 instruction such as a 3 byte call to any location in memory could be executed The number of clock cycles necessary to execute this instruction is two more than the normal number for the instruction This occurs because the CPU automatically adds two wait states to an Interrupt response cycle to allow sufficient time to implement an external daisy chain for priority control Figure 9 and Figure 10 illustrate the detailed timing for an interrupt response After the application of RESET the CPU automatically enters interrupt Mode 0 Mode 1 When this mode is selected by the programmer the CPU responds to an interrupt by executing a restart to location 0038H Thus the response is identical to that for a non maskable interrupt except that the call location is 0038H instead of 0066H The number of cycles required to complete the restart instruction is two more than normal due to the two added wait states Mode 2 This mode is the most powerful interrupt response mode With a single 8 bit byte from the use
42. V FLAG IS USED TO INDICATE THAT REGISTER BC WAS DECREMENTED TO ZERO Nineteen bytes are required for this operation Example Three A 16 digit decimal number is shifted as depicted in the Figure 6 This shift is performed to mechanize BCD multiplication or division The 16 digit decimal number is represented in packed BCD format two BCD digits byte The operation is programmed as follows LD HL DATA ADDRESS OF FIRST BYTE LD B COUNT SHIFT COUNT XOR A CLEAR ACCUMULATOR ROTAT RLD ROTATE LEFT LOW ORDER DIGIT IN ACC WITH DIGITS IN HL INC HL ADVANCE MEMORY POINTER DJNZ ROTAT DECREMENT B AND GO TO ROTAT IF UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual 36 ZiLOG B IS NOT ZERO OTHERWISE FALL THROUGH Eleven bytes are required for this operation NN SANAAN Figure 6 Shifting of BCD Digits Bytes Example Four One number is to be subtracted from another number both of which are in packed BCD format and are of equal but varying length The result is stored in the location of the minuend The operation is programmed as follows LD HL ARG1 ADDRESS OF MINUEND LD DE ARG2 ADDRESS OF SUBTRAHEND LD B LENGTH LENGTH OF TWO ARGUMENTS AND A CLEAR CARRY FLAG SUBDEC LD A DE SUBTRAHEND TO ACC SBC A HL SUBTRACT HL FROM ACC UM008004 1 204 Hardware and Software Implementation Examples DAA VALUE LD INC INC Z80 CPU User
43. accepted The programmer can change this table by storing it in Read Write Memory which also allows individual peripherals to be serviced by different service routines When the interrupting device supplies the lower portion of the pointer the CPU automatically pushes the program counter onto the stack obtains the starting address from the table and performs a jump to this address This mode of response requires 19 clock periods to complete seven to fetch the lower eight bits from the interrupting device six to save the program counter and six to obtain the jump address The Z80 peripheral devices include a daisy chain priority interrupt structure that automatically supplies the programmed vector to the CPU during interrupt acknowledge Refer to the Z80 CPU Peripherals User Manual for more complete information UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG 27 Hardware and Software Implementation Examples HARDWARE Minimum System This chapter is an introduction to implementing systems that use the Z80 CPU Figure 1 illustrates a simple Z80 system Any Z80 system must include the following elements UM008004 1204 5V Power Supply Oscillator Memory Devices T O Circuits CPU Hardware and Software Implementation Examples Z80 CPU User s Manual 28 ZiLOG OSC 5V Power Supply CLK Ag Ao 5V GND MREQ CET m ode 5V Z80 CPU Data Bus Ue Data B A IORQ Z80 PIO
44. are 0 1 1 1 1 0 1 0 Accumulator 0 0 1 1 O OJO 1 5000H at execution of RLD the contents of the Accumulator and memory location 5000H are 0 1 1 1 0 0 1 1 Accumulator 0 0 0 4 1 01 0 5000H UM008004 1204 Z80 Instruction Set 222 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description 1 1 1 0 14 14 0 4 ED 0 1 1 0 0 1 1 1 67 The contents of the low order four bits bits 3 2 1 and 0 of memory location HL are copied to the low order four bits of the Accumulator register A The previous contents of the low order four bits of the Accumulator are copied to the high order four bits 7 6 5 and 4 of location HL and the previous contents of the high order four bits of HL are copied to the low order four bits of HL The contents of the high order bits of the Accumulator are unaffected HL means the memory location specified by the contents of the HL register pair M Cycles T States 4 MHz E T 5 18 4 4 3 4 3 4 50 Condition Bits Affected S is set if Accumulator is negative after operation reset otherwise Z is set if Accumulator is zero after operation reset otherwise H is reset P V is set if parity of Accumulator is even after operation reset otherwi
45. call to any of the eight addresses listed The simple mnemonic for these eight calls is also listed This instruction is useful for frequently used routines because memory consumption is minimized Table 13 Restart Group Op Code CALL Address 0000H RST 0 0008H RST 8 0010H RST 16 0018H RST 24 0020H RST 32 0028H RST 40 0030H RST 48 0038H RST 56 Input Output The Z80 has an extensive set of input and output instructions as shown in Table 14 and Table 15 The addressing of the input or output device can be either absolute or register indirect using the C register In the register indirect addressing mode data can be transferred between the I O devices and any of the internal registers In addition eight block transfer instructions have been implemented These instructions are similar to the memory block transfers except that they use register pair HL for a pointer to the memory source output commands or destination input commands while register B is used as a byte counter Register C holds the address of the port for which the input or output command is required Because register B is eight bits in length the I O block transfer command handles up to 256 bytes In the instructions IN A and OUT n A the I O device address n appears in the lower half of the address bus A7 A0 while the accumulator content UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 71 is transferred in the
46. in the 8080A CPU UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z ZiLOG Also depicted is the assembly language mnemonic that is used for each instruction All instruction Op Codes are listed in hexadecimal notation Single byte Op Codes require two hex characters while double byte Op Codes require four hex characters For convenience the conversion from hex to binary is repeated in Table 1 Table 1 Hex Binary Decimal Conversion Table Hex Binary Decimal 0 0000 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 7 Olll 7 8 1000 8 9 1001 9 A 1010 10 B 1011 ll C 1100 12 D 1101 13 E 1110 14 F ill 15 The Z80 instruction mnemonics consist of an Op Code and zero one or two operands Instructions where the operand is implied contains no operand Instructions that contain only one logical operand where one operand is invariant such as the Logical OR instruction are represented by a one operand mnemonic Instructions that contain two varying operands are represented by two operand mnemonics Load and Exchange UM008004 1204 Z80 CPU Instruction Description 49 50 Z80 CPU User s Manual ZiLOG Table 2 defines the Op Code for all the 8 bit load instructions implemented in the Z80 CPU Also described in this table is the type of addressing used for each instruction The source of the data is found on the top horiz
47. indirect call using register I and B bits from INTER device as a pointer Z80 CPU Instruction Description 73 Z80 CPU User s Manual 74 ZiLOG UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 75 Z80 Instruction Set Z80 Assembly Language The assembly language allows the user to write a program without concern for memory addresses or machine instruction formats It uses symbolic addresses to identify memory locations and mnemonic codes Op Codes and operands to represent the instructions Labels symbols are assigned to a particular instruction step in a source program to identify that step as an entry point for use in subsequent instructions Operands following each instruction represent storage locations registers or constant values The assembly language also includes assembler directives that supplement the machine instruction A pseudo op for example is a statement that is not translated to a machine instruction but rather is interpreted as a directive that controls the assembly process A program written in assembly language is called a source program which consists of symbolic commands called statements Each statement is written on a single line and may consist of from one to four entries A label field an operation field an operand field and a comment field The source program is processed by the assembler to obtain a machine language program object program that can be executed di
48. instruction The stack push is accomplished by first decrementing the current contents of the Stack Pointer SP loading the high order byte of the PC contents to the memory address now pointed to by SP then decrementing SP again and loading the low order byte of the PC contents to the top of the stack Because this is a 3 byte instruction the Program Counter was incremented by three before the push is executed Condition cc is programmed as one of eight status that corresponds to condition bits in the Flag Register register F These eight status are UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 258 ZiLOG defined in the table below which also specifies the corresponding cc bit fields in the assembled object code Relevant cc Condition Flag 000 NZ non zero Z 001 Z zero Z 010 NC non carry C 011 C carry Z 100 PO parity odd P V 101 PE parity even P V 110 P sign positive S 111 M sign negative S If cc is true M Cycles T States 4 MHz E T 5 17 4 3 4 3 3 4 25 If cc is false M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the C Flag in the F register is reset the contents of the Program Counter are 1A47H the contents of the Stack Pointer are 3002H and memory locations have the contents Location Contents 1A47H D4H 1448H 35H 1A49H 21H then if an instruction fetch sequence begins the 3 byte instruction D43521H is fetched to the CPU for execution
49. instructions For example the instruction to load the accumulator with the operand in memory location 6F32H is written LID A 6F 32H and its instruction sequence is Address A 3A Op Code A 1 32 Low Order Address A 2 6F High Order Address Notice that the low order portion of the address is always the first operand The load immediate instructions for the general purpose 8 bit registers are two byte instructions The instruction load register H with the value 36H is written LD H 36H and its sequence is Address A 26 Op Code A 1 36 Operand UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z ZiLOG 53 Loading a memory location using indexed addressing for the destination and immediate addressing for the source requires four bytes For example LD IX 15 21H appears as Address A DD Op Code A 1 36 A 2 F1 One or Two Bytes Displacement 15 in Signed A 3 21 Two s Complement Operand to Load Notice that with any indexed addressing the displacement always follows directly after the Op Code Table 3 specifies the 16 bit load operations The extended addressing feature covers all register pairs Register indirect operations specifying the stack pointer are the PUSH and POP instructions The mnemonic for these instructions is PUSH and POP These differ from other 16 bit loads in that the stack pointer is automatically decremented and in
50. is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 0 of Accumulator If the contents of the Accumulator are 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 at execution of RRCA the contents of the Accumulator and the Carry flag are 7 6 5 4 3 2 1 0 C 1 0101 1 0 0 01 UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 193 RRA o o o i1 41 14 4 4 4 4F The contents of the Accumulator register A are rotated right 1 bit position through the Carry flag The previous content of the Carry flag is copied to bit 7 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected Example S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 0 of Accumulator If the contents of the Accumulator and the Carry Flag are 7 6 5 4 3 2 1 0 C 1 11 0 0 0 0 1 at execution of RRA the contents of the Accumulator and the Carry flag are 7 6 5 4 3 2 1 0 C 0 1 1 1 0 0 00 1 UM008004 1204 Z80 Instruction Set 194 Z80 CPU User s Manual ZiLOG RLC r Operation CY a 7 a 0 a Op Code RLC Opera
51. m The m operand is any of r HL X d or 1Y d as defined for the analogous RLC instructions These possible Op Code operand combinations are specified as follows in the assembled object code RRe 1 1 0 0 1 4 0 1 41 CB 0 0 0 0 1 s rt RR HL 1 1 0 0 1 0 414 4 14 CB RR IX d 1 1 0 1 1 1 0 1 DD RR IY d 1 4 4 14 14 4 0 4 14 4 FD UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 209 r identifies registers B C D E H L or A assembled as follows in the object code field above Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The contents of operand m are rotated right 1 bit position through the Carry flag The content of bit 0 is copied to the Carry flag and the previous content of the Carry flag is copied to bit 7 Bit 0 is the least significant bit Instruction M Cycles T States 4 MHz E T RRr 2 8 4 4 2 00 RR HL 4 15 4 4 4 3 3 75 RR IX d 6 23 4 4 3 5 4 3 5 75 RR 1Y d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is data from bit 0 of source register Example If the contents of the
52. of the Accumulator are 23H at executionof ADD A 33H the contents of the Accumulator are 56H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 143 ADD A HL A amp A HL ADD A HL 1 0101 10 0 111 0 86 The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator and the result is stored in the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if overflow reset otherwise N is reset C is set if carry from bit 7 reset otherwise If the contents of the Accumulator are AOH and the content of the register pair HL is 2323H and memory location 2323H contains byte 08H at execution of ADD A HL the Accumulator contains A8H UM008004 1204 Z80 Instruction Set 144 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description ADD A IX d A amp A IX d ADD A IX d 1 1 0 a a fo 4 BD 1 0 0 0 1 0 1 1 0 86 d gt The contents of the Index Register register pair IX is added to a two s complement displacement d to point to an address in memory T
53. s Manual ZiLOG ADJUST RESULT TO DECIMAL CODED HL A STORE RESULT HL ADVANCE MEMORY POINTERS DE DJNZ SUBDEC DECREMENT B AND GO TO SUBDEC IF B NOT ZERO OTHERWISE FALL THROUGH Seventeen bytes are required for this operation Examples of Programming Tasks As depicted in Table 1 this example program sorts an array of numbers to ascending order using a standard exchange sorting algorithm These numbers range from 0 to 255 Table 1 Bubble Listing UM008004 1204 Loc Obj Code Stmt Source Statement 1 E standard exchange bubble sort routine 2 3 at entry hl contains address of data 4 c contains number of elements to be sorted 5 1 lt c lt 256 6 7 at exit data sorted in ascending order 8 9 use of registers 10 j 11 register contents 12 13 temporary storage for calculations 14 b counter for data array Hardware and Software Implementation Examples 37 Z80 CPU User s Manual 38 ZiLOG Table 1 Bubble Listing Continued Loc Obj Code Stmt Source Statement 15 c length of data array 16 d first element in comparison 17 e second element in comparison 18 h flag to indicate exchange 19 l unused 20 ix pointer into data array 21 iy unused 22 0000 222600 23 sort ld data hl save data address 0003 cb84 24 jloop res flag h Initialize exchange flag 0005 41 25 ld b c initialize length count
54. set if overflow reset otherwise N is reset C is set if carry from bit 7 reset otherwise If the Accumulator contents are 11H the Index Register Pair IY contains 1000H and if the content of memory location 1005H is 22H at execution of ADD A IY 5H thecontents of the Accumulator are 33H UM008004 1204 Z80 Instruction Set 146 Z80 CPU User s Manual ZiLOG ADC A s Operation A lt A s CY Op Code ADC Operands A s This s operand is any of r n HL X d or Y d as defined for the analogous ADD instruction These possible Op Code operand combinations are assembled as follows in the object code ADC A r 1 0 0 0 1 a r p ADC A n 1 1 0 0 1 1 1 o CE a n lt ADC A HL 1 0 0 4 4 4 0 8E ADC A IX d 1 1 0 1 1 1 1 o DD 1 0107 0 1 11 0 8E a d ADC A IY d 1 1 1 1 1 1 0 1 FD 1 0101 0 1 11 0 8E a d gt r identifies registers B C D E H L or A assembled as follows in the object code field above UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 147 Register r B 000 C 001 D 010 E 011 H 100 L 101 A iii Description The s operand along with the Carry Flag C in the F register is added to the contents of the Accumulator and the result is stored in the Accumulator Instruction M Cycle T States 4 MHz E T ADC A r 1 4 1 00 ADC A n 2 7 4 3
55. single exchange instruction so that it is possible to work with either pair General Purpose Registers Two matched sets of general purpose registers each set containing six 8 bit registers may be used individually as 8 bit registers or as 16 bit register pairs One set is called BC DE and HL while the complementary set is called BC DE and HL At any one time the programmer can select either set of registers to work through a single exchange command for the entire set In systems that require fast interrupt response one set of general purpose registers and an ACCUMULATOR FLAG register may be reserved for handling this fast routine One exchange command is executed to switch routines This greatly reduces interrupt service time by eliminating the requirement for saving and retrieving register contents in the external stack during interrupt or subroutine processing These general purpose registers are used for a wide range of applications They also simplify programing specifically in ROM based systems where little external read write memory is available Arithmetic Logic Unit ALU The 8 bit arithmetic and logical instructions of the CPU are executed in the ALU Internally the ALU communicates with the registers and the external data bus by using the internal data bus Functions performed by the ALU include UM008004 1 204 Overview 6 Z80 CPU User s Manual ZiLOG Add Subtract e Logical AND Logical OR
56. the HL register pair are 1000H and the following sequence of bytes are available at the peripheral device mapped to I O port address 07H 51H A9H 03H then at execution of INDR the HL register pair contains OF FDH register B contains zero and memory locations contain the following OFFEH contains 03H OFFFH contains A9H 1000H contains 51H UM008004 1204 Z80 Instruction Set Operation n lt A Op Code OUT Operands n A OUT n A 1 0 0 1 1 a z Z80 CPU User s Manual ZiLOG 279 D3 Description The operand n is placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports The contents of the Accumulator register A also appear on the top half A8 through A15 of the address bus at this time Then the byte contained in the Accumulator is placed on the data bus and written to the selected peripheral device T States 4 MHz E T 11 4 3 4 2 75 Condition Bits Affected None Example If the contents of the Accumulator are 23H at execution of OUT 01H byte 23H is written to the peripheral device mapped to I O port address 01H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 280 ZiLOG OUT C r Operation C lt r Op Code OUT Operands C r Description The contents of register C are placed on the bottom half AO through A7 of the addre
57. the actual operand Op Code Lone or Two Bytes Op Code D7 DO Examples of this type of instruction is loading the accumulator with a constant where the constant is the byte immediately following the Op Code Immediate Extended This mode is an extension of immediate addressing in that the two bytes following the Op Codes are the operand Op Cod One or Two Bytes Op Code Low Order Op Code High Order Examples of this type of instruction is loading the HL register pair 16 bit register with 16 bits two bytes of data UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 45 Modified Page Zero Addressing The Z80 has a special single byte CALL instruction to any of eight locations in page zero of memory This instruction which is referred to as a restart sets the PC to an effective address in page zero The value of this instruction is that it allows a single byte to specify a complete 16 bit address where commonly called subroutines are located thus saving memory space Op Code One Byte B7 BO Effective Address is B5 B4 B3 000 2 Relative Addressing Relative addressing uses one byte of data following the Op Code to specify a displacement from the existing program to which a program jump can occur This displacement is a signed two s complement number that is added to the address of the Op Code of the following instruction Op Code Jump Relati
58. the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent memory location are loaded to the high order portion of IX The SP is incremented again M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example If the Stack Pointer contains 1000H memory location 1000H contains 55H and location 1001H contains 33H the instruction POP IX results in Index Register IX containing 3355H and the Stack Pointer containing 1002H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 121 POP IY Operation IYH lt SP X1 IYL lt SP Op Code POP Operands 1Y 1 1 0 1 14 14 0 41 DD ari ae ae ae a ae Wat Description The top two bytes of the external memory LIFO last in first out Stack are popped to Index Register IY The Stack Pointer SP register pair holds the 16 bit address of the current top of the Stack This instruction first loads to the low order portion of TY the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent memory location are loaded to the high order portion of IY The SP is incremented again M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example If the Stack Pointer Contains 1000H memory location 1000H contains 55H and loc
59. upper half of the address bus In all register indirect input output instructions including block I O transfers the content of register C is transferred to the lower half of the address bus device address while the content of register B is transferred to the upper half of the address bus CPU Control Group Table 16 illustrates the six general purpose CPU control instructions The NOP is a do nothing instruction The HALT instruction suspends CPU operation until a subsequent interrupt is received while the DI and E1 are used to lock out and enable interrupts The three interrupt mode commands set the CPU to any of the three available interrupt response modes as follows If Mode 0 is set the interrupting device can insert any instruction on the data bus and allow the CPU to execute it Mode 1 is a simplified mode where the CPU automatically executes a restart RST to location 0038H so that no external hardware is required the old PC content is pushed onto the stack Mode 2 is the most powerful because it allows for an indirect call to any location in memory With this mode the CPU forms a 16 bit memory address where the upper eight bits are the content of register I and the lower eight bits are supplied by the interrupting device This address points to the first of two sequential bytes in a table where the address of the service routine is located The CPU automatically obtains the starting address and performs a CALL instruction to this ad
60. user s program This group uses several different techniques for obtaining the new program counter address from specific external memory locations A unique type of call is the RESTART instruction This instruction actually contains the new address as a part of UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 43 the 8 bit Op Code This is possible because only eight separate addresses located in page zero of the external memory may be specified Program jumps may also be achieved by loading register HL IX or IY directly into the PC thus allowing the jump address to be a complex function of the routine being executed The input output group of instructions in the Z80 allow for a wide range of transfers between external memory locations or the general purpose CPU registers and the external I O devices In each case the port number is provided on the lower eight bits of the address bus during any I O transaction One instruction allows this port number to be specified by the second byte of the instruction while other Z80 instructions allow it to be specified as the content of the C register One major advantage of using the C register as a pointer to the I O device is that it allows multiple I O ports to share common software driver routines This advantage is not possible when the address is part of the Op Code if the routines are stored in ROM Another feature of these input instructions is the automatic sett
61. 0 L 101 A iii Description The contents of the m operand are rotated left 1 bit position The content of bit 7 is copied to the Carry flag and the previous content of the Carry flag is copied to bit 0 Instruction M Cycles T States 4 MHz E T RLr 2 8 4 4 2 00 RL HL 4 15 4 4 4 3 3 75 RL IX d 6 23 4 4 3 5 4 3 5 75 RL IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is data from bit 7 of source register Example If the contents of register D and the Carry flag are Cc 7 6 5 4 3 2 1 0 0 1 000 1 1 1 1 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 204 ZiLOG at execution of RL D the contents of register D and the Carry flag are C 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 1 0 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 205 RRC m Operation Ge sea Op Code RRC Operands m The m operand is any of r HL X d or 1Y d as defined for the analogous RLC instructions These possible Op Code operand combinations are specified as follows in the assembled object code RRC r 1 1 0 0 1 0 1 1 CB RRC HL 1 1 0 0 1 0 14 1 CB RRC IX d 1 1 0 1 1 1 0
62. 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 SUB 0 0 9 0 0 9 00 0 SBC 0 0 8 1 6 F FA 0 DEC 1 7 F 0 0 9 AO 1 NEG 1 6 7 1 6 F 9A 1 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 167 M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected Example S is set if most significant bit of Accumulator is 1 after operation reset otherwise Z is set if Accumulator is zero after operation reset otherwise H see instruction P V is set if Accumulator is even parity after operation reset otherwise N is not affected C see instruction If an addition operation is performed between 15 BCD and 27 BCD simple decimal arithmetic gives this result 15 27 42 But when the binary representations are added in the Accumulator according to standard binary arithmetic 0001 0101 0010 0111 0011 1100 3C the sum is ambiguous The DAA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 UM008004 1204 Z80 Instruction Set 168 Z80 CPU User s Manual ZiLOG Operation Op Code Description CPL AA CPL oloi olija 2 The contents of the Accumulator register A are inverted one s complement M Cycles T States 4 MHZ E T 1 4 1 00 Condition Bits Affected Example S is not affected Z is not affected H is set P V is not affected N is set
63. 0 is the least significant bit M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is data from bit 7 of source register Example If the contents of the HL register pair are 2828H and the contents of memory location 2828H are 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 197 at execution of RLC HL the contents of memory location 2828H and the Carry flag are C 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 1 UM008004 1204 Z80 Instruction Set 198 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description RLC IX d CY lt a 7 4 0 IX d RLC IX d 1 1 0 1 14 14 0 14 DD 11 0 01 0 11 CB a d gt 00 0 0J0 111 0 06 The contents of the memory address specified by the sum of the contents of the Index Register IX and a two s complement displacement integer d are rotated left 1 bit position The content of bit 7 is copied to the Carry flag and also to bit 0 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Af
64. 1 75 ADC A HL 2 7 4 3 1 75 ADC A IX d 5 19 4 4 3 5 3 4 75 ADC A 1Y d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if overflow reset otherwise N is reset C is set if carry from bit 7 reset otherwise Example If the Accumulator contents are 16H the Carry Flag is set the HL register pair contains 6666H and address 6666H contains 10H at execution of ADCA HL the Accumulator contains 27H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 148 ZiLOG SUB s Operation A lt A s Op Code SUB Operands s This s operand is any of r n HL X d or 1Y d as defined for the analogous ADD instruction These possible Op Code operand combinations are assembled as follows in the object code SUB r 1 0 0 1 0 a r gt SUB n 1 1 0 1 0 1 1 o D6 SUB HL 1 0 0 1 0 41441 0 96 SUB IX d 1 14 0 14 14 4 0 4 DD SUB IY d 41 Ae a se ae a ae FD 110 01 11 0 1 1096 a d gt r identifies registers B C D E H L or A assembled as follows in the object code field above UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 149 Register r B 000 C 001 D 010 E 011 H 100 L 101 A ii Descr
65. 16 bit address of the current top of a stack located anywhere in external system RAM memory The external stack memory is organized as a last in first out LIFO file Data can be pushed onto the stack from specific CPU registers or popped off of the stack to specific CPU registers through the execution of PUSH and POP instructions The data popped from the stack is always the last data pushed onto it The stack allows simple implementation of multiple level interrupts UM008004 1204 Overview 4 Z80 CPU User s Manual ZiLOG unlimited subroutine nesting and simplification of many types of data manipulation Two Index Registers IX and IY The two independent index registers hold a 16 bit base address that is used in indexed addressing modes In this mode an index register is used as a base to point to a region in memory from which data is to be stored or retrieved An additional byte is included in indexed instructions to specify a displacement from this base This displacement is specified as a two s complement signed integer This mode of addressing greatly simplifies many types of programs especially where tables of data are used Interrupt Page Address Register I The Z80 CPU can be operated in a mode where an indirect call to any memory location can be achieved in response to an interrupt The I register is used for this purpose and stores the high order eight bits of the indirect address while the interrupting device provi
66. 4000se00ssecedeseobeguwesens 14 Bus Request Acknowledge Cycle 0 00 e ee eee 15 Interrupt Request Acknowledge Cycle 0 16 Non Maskable Interrupt Response 0000000 17 HALT FRG arse cenio pai ei buen ease ade bebe base nasa 18 Power Down Acknowledge Cycle 005 19 Power Down Release Cycle 0 0 0 eee eee eee 20 Interrupt Response cc22c54 lt 0de Khas sea ea dad acewadacwensids 22 OYVCIVIOW lt i uu cader ase eade ee sen tee ester KOREA K ESA 22 Interrupt Enable Disable y14 2s00ces es S00 asec sere aden ede 22 CPU Response conc Sa cxede ries eet ee een oe e See seers 24 Hardware and Software Implementation Examples 27 HardWare ih hakc peee ad Babee haa havad nea bheeeheee Reads 27 Minimum System 22454 x xteee sen sedest Ce cSenrverederes 27 UM008004 1204 Table of Contents Z80 CPU User s Manual vi ZiLoG Adding RAM 43552955405 4245 4S5 83 Ss os Sy i Deua e Ree 29 Memory Speed Control 2442 d eseneeceees bee Foden yen ees 30 Interfacing Dynamic Memories 00 000 eee 31 Software Implementation Examples 00 000 5 33 Overview of Software Features 0 0 0 0 e eee 33 Examples of Specific Z80 Instructions 4 34 Examples of Programming Tasks 005 37 Z80 CPU Instruction Description 000 cece 41 OVCIVICW 2 jscty ce os erga tends a a a a E 41 Instruction Types lt 215 6 ch
67. 5 Condition Bits Affected None Example If the contents of register pair DE are 1128H and the Accumulator contains byte AOH the instruction LD DE A results in AOH in memory location 1128H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 97 LD nn A Operation nn lt A Op Code LD Operands nn A 0o11 0 0 1 0 32 lt a n al lt a n Description The contents of the Accumulator are loaded to the memory address specified by the operand nn The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 4 13 4 3 3 3 3 25 Condition Bits Affected None Example If the contents of the Accumulator are byte D7H at execution of LD 3141 H AD7H results in memory location 3141H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 98 ZiLOG LD A Operation A lt 1 Op Code LD Operands A I 1 1 14 0 1 14 0 1 4 ED Oo tel A ici aca Ak ae Description The contents of the Interrupt Vector Register I are loaded to the Accumulator M Cycles T States MHz E T 2 9 4 5 2 25 Condition Bits Affected S is set if Register is negative reset otherwise Z is set if I Register is zero reset otherwise H is reset P V contains contents of IFF2 N is reset C is not affected If an interrupt occurs during execution of this instruction the Par
68. 5 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory Then register pair HL is incremented the byte counter is decremented If decrementing causes B to go to zero the instruction is terminated If B is not zero the PC is decremented by two and the instruction repeated Interrupts are recognized and two refresh cycles execute after each data transfer Note if B is set to zero prior to instruction execution 256 bytes of data are input If B 0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 If B 0 M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected S is unknown Z is set H is unknown P V is unknown UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z 274 ZiLOG N is set C is not affected Example If the contents of register C are 07H the contents of register B are 03H the contents of the HL register pair are 1000H and the following sequence of bytes are available at the peripheral device mapped to I O port of address 07H 51H A9H 03H then at execution of INIR the HL register pair contains 1003H register B contains zero and memory locations contain the following 1000H contains 51H 1001H contains A9H 1002H contains 03H UM008004 1204 Z80 Instruction Set Z80
69. 56H contains byte 11H and memory location 8857H contains byte 22H then the instruction EX SP HL results in the HL register pair containing number 2211H memory location 8856H containing byte 12H memory location 8857H containing byte 70H and Stack Pointer containing 8856H UM008004 1204 Z80 Instruction Set 126 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description EX SP IX IXH SP 1 IXL SP EX SP IX 1 1 0 oa 4 a ila BD 1 1 1 0 0 0 1 1 E3 The low order byte in Index Register IX is exchanged with the contents of the memory address specified by the contents of register pair SP Stack Pointer and the high order byte of IX is exchanged with the next highest memory address SP 1 M cycles T States 4 MHZ E T 6 23 4 4 3 4 3 5 5 75 Condition Bits Affected None Example If the Index Register IX contains 3988H the SP register pair Contains 0100H memory location 0100H contains byte 90H and memory location 0101H contains byte 48H then the instruction EX SP IX results in the IX register pair containing number 4890H memory location 0100H containing 88H memory location 0101H containing 39H and the Stack Pointer containing 0100H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 127 EX SP IY Operation IYH lt SP 1 IYL lt SP Op Code EX Operands SP IY 1 4 4 1 4 441 50 1 4
70. 60H the instruction CP HL results in the PN flag in the F register resetting UM008004 1204 Z80 Instruction Set 160 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description INC r rer l1 INC r Register r is incremented and register r identifies any of the registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 Cc 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if r was 7FH before operation reset otherwise N is reset C is not affected If the contents of register D are 28H at execution of INC D the contents of register D are 29H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 161 INC HL HL HL 1 INC HL O04 4 ae a o o e The byte contained in the address specified by the contents of the HL register pair is incremented M Cycles T States 4 MHz E T 3 11 4 4 3 2 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if HL was 7FH before operation reset
71. 80 CPU User s Manual 114 zitoc LD SP IX Operation SP lt IX Op Code LD Operands SP 1X 11 01 17 ate 1 1 1 1 1 0 0 1 F9 Description The 2 byte contents of Index Register IX are loaded to the Stack Pointer SP M Cycles T States 4 MHZ E T 2 10 4 6 2 50 Condition Bits Affected None Example If the contents of the Index Register IX are 98DAH at instruction LD SP IX the contents of the Stack Pointer are also 98DAH UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 115 LD SP IY Operation SP lt IY Op Code LD Operands SP 1Y 1 14 4 1 14 1440 414 4 FD 1 1 4 1 14 0 0 41 4 F9 Description The 2 byte contents of Index Register IY are loaded to the Stack Pointer SP M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If Index Register IY contains the integer A227H at instruction LD SP IY the Stack Pointer also contains A227H UM008004 1204 Z80 Instruction Set 116 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description PUSH qq SP 2 qqL SP 1 4 qqH PUSH qq 1 1 q q 0 1 0 1 The contents of the register pair qq are pushed to the external memory LIFO last in first out Stack The Stack Pointer SP register pair holds the 16 bit address of the current top of the Stack This
72. A47H contains CDH IA48H contains 35H 1A49H contains 21H If an instruction fetch sequence begins the 3 byte instruction CD3521H is fetched to the CPU for execution The mnemonic equivalent of this is CALL 2135H At execution of this instruction the contents of memory address 3001H is 1AH the contents of address 3000H is 4AH the contents of the Stack Pointer is 3000H and the contents of the Program Counter is 2135H pointing to the address of the first Op Code of the subroutine now to be executed UM008004 1204 Z80 Instruction Set sp 2 PCL pe lt nn Op Code CALL Operands cc nn CALL cc nn Operation IF cc true sp 1 lt PCH 1 lt a cc 0 a n gt a n gt Z80 CPU User s Manual ZiLOG 257 Note The first of the two n operands in the assembled object code above is the least significant byte of the 2 byte memory address Description If condition cc is true this instruction pushes the current contents of the Program Counter PC onto the top of the external memory stack then loads the operands nn to PC to point to the address in memory where the first Op Code of a subroutine is to be fetched At the end of the subroutine a RETurn instruction can be used to return to the original program flow by popping the top of the stack back to PC If condition cc is false the Program Counter is incremented as usual and the program continues with the next sequential
73. CB CB DD_ FD RLA gt Right 17 10 11 12 13 14 15 16 ICB CB d d 16 16 Shift CYa lt RR cB cB cB cB cB cB cB CcB DD FD RRA Left Arithmetic 1F 18 19 1A 1B 1C 1D 1E ICB CB d d 1E HE _ Shift gt _ Right Arithmetic SLA CB CB CB CB CB CB CB CB DD FD A 27 20 21 22 23 24 25 26 ICB CB d d 25 126 Shift gt Right Logical SRA CB CB CB CB CB CB CB CB DD_ FD g 2F 28 29 2A 2B 2C 2D 2E ICB CB 0 d d Rotate sa E Bsbo br bg bso HL Digit SRL CB CB CB CB CB CB CB CB DD_ FD eft 3F 38 39 3A 3B 3C 3D 3E CB CB acch L d d 3E 3E ED l HL Rotate 6F Digit ACC Right ED 67 Bit Manipulation The ability to set reset and test individual bits in a register or memory location is needed in almost every program These bits may be flags in a general purpose software routine indications of external control UM008004 1204 Z80 CPU Instruction Description 64 Z80 CPU User s Manual ZiLOG conditions or data packed into memory locations making memory utilization more efficient The Z80 can set reset or test any bit in the accumulator any general purpose register or any memory location with a single instruction Table 11 lists the 240 instructions that are available for this purpose Register addressing can specify the accumulator or any general purpose register on which the operation is to be performed Regist
74. E T 5 19 4 4 3 5 3 2 50 Condition Bits Affected None Example If the Index Register IY contains the number A94 0H the instruction LD IY 10H 97H results in byte 97H in memory location A950H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 92 ZiLOG LD A BC Operation A lt BC Op Code LD Operands A BC 0 0 0 0 1 0 1 0 0A Description The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the BC register pair contains the number 4747H and memory address 4747H contains byte 12H then the instruction LD A BC results in byte 12H in register A UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 93 LD A DE Operation A lt DE Op Code LD Operands A DE e lolojililojijoj Description The contents of the memory location specified by the register pair DE are loaded to the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the DE register pair contains the number 30A2H and memory address 30A2H contains byte 22H then the instruction LD A DE results in byte 22H in register A UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 94 ZiLOG LD A nn Operation A lt nn Op Code LD Oper
75. Example S is not affected Z is not affected H is reset P V is set if BC 1 0 reset otherwise N is reset C is not affected If the HL register pair contains 1111H memory location 1111H contains byte 88H the DE register pair contains 2222H the memory location 2222H contains byte 66H and the BC register pair contains 7H then the instruction LDI results in the following contents in register pairs and memory addresses HL contains 1112H 1111H contains 88H DE contains 2223H 2222H contains 88H BC contains 6H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 129 LDIR DE HL DE DE 1 HL lt HL 1 BC Fe BC 1 LDIR B8 1 1 1 oj1il1lo 1 ED 1 0 1 1 0 0 0fo0o BO This 2 byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the DE register pair Both these register pairs are incremented and the BC Byte Counter register pair is decremented If decrementing causes the BC to go to zero the instruction is terminated If BC is not zero the program counter is decremented by two and the instruction is repeated Interrupts are recognized and two refresh cycles are executed after each data transfer When BC is set to zero prior to instruction execution the instruction loops through 64 Kbytes For BC 0
76. G EXX Operation BC BC DE DE HL HL Op Code EXX Operands 1 1 0 14 1 0 0 0 D9 Description Each 2 byte value in register pairs BC DE and HL is exchanged with the 2 byte value in BC DE and HL respectively M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If the contents of register pairs BC DE and HL are the numbers 445AH 3DA2H and 8859H respectively and the contents of register pairs BC DE and HL are 0988H 9300H and 00E7H respectively at instruction EXX the contents of the register pairs are as follows BC contains 0988H DE contains 9300H HL contains 00E7H BC contains 445AH DE contains 3DA2H and HL contains 885 9H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 125 EX SP HL Operation H lt gt SP 1 L lt gt SP Op Code EX Operands SP HL 11111 0 o0l0 1 1 E3 Description The low order byte contained in register pair HL is exchanged with the contents of the memory address specified by the contents of register pair SP Stack Pointer and the high order byte of HL is exchanged with the next highest memory address SP 1 M Cycles T States 4 MHz E T 5 19 4 3 4 3 5 4 75 Condition Bits Affected None Example If the HL register pair contains 7012H the SP register pair contains 8856H the memory location 88
77. H 03H UM008004 1204 Z80 Instruction Set Operation Op Code Description Z80 CPU User s Manual ZiLOG 285 OUTD C HL B B 1 HL lt HL 1 OUTD 1 14 1 0 14 1 0 1 ED 1 0 1 0 1 0 1 1 AB The contents of the HL register pair are placed on the address bus to select a location in memory The byte contained in this memory location is temporarily stored in the CPU Then after the byte counter B is decremented the contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B may be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written to the selected peripheral device Finally the register pair HL is decremented M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected Example S is unknown Z is set if B 1 0 reset otherwise H is unknown P V is unknown N is set C is not affected If the contents of register C are 07H the contents of register B are 10H the contents of the HL register pair are 1000H and the contents of memory location 1000H are 59H at execution of OUTD register B contains OFH the HL register pair contains OF FFH and byte 59H is written to the peripheral device mapped to I O port addres
78. If the condition is met M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If the condition is not met M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example The Zero Flag is set and it is required to jump forward five locations from address 300 The following assembly language statement is used JRZ 5 The resulting object code and final PC value is UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 247 Location Instruction 300 28 301 03 302 303 304 305 lt PC after jump UM008004 1204 Z80 Instruction Set 248 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description JR NZ e If Z 1 continue IfZ 0 PC lt pete JR NZ e 0 0 1 0 0 0 0 0 20 En e 2 p This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag If the flag is equal to a 0 the value of the displacement e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction Op Code and has a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the Zero Flag is equal to a 1 the next instruction executed is taken from the location following this instruction If the condi
79. OR HL 1 0 1 41 0 1 1 oJ B6 OR IX d 1 1 0 1 1 1 0 1 DD OR IY d 1 4 44 4 44 4707 14 FD r identifies registers B C D E H L or A specified as follows in the assembled object code field above UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 155 Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description A logical OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator the result is stored in the Accumulator Instruction M cycles T States 4 MHz E T ORr 1 4 1 00 OR n 2 7 4 3 1 75 OR HL 2 7 4 3 1 75 OR X d 5 19 4 4 3 5 3 4 75 OR 1Y d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if overflow reset otherwise N is reset C is reset Example If the H register contains 48H 0100 0100 and the Accumulator contains 12H 0001 0010 at execution of OR H the Accumulator contains 5AH 0101 1010 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 156 ZiLOG XOR s Operation A lt A s Op Code XOR Operands s The s operand is any of r n HL X d or LY d as defined for the analogous ADD instructions These possible Op Code operand combinations are assembled as follows in the obj
80. Operation SP 1 lt PCH SP 2 lt PCL PC lt nn Op Code CALL Operands nn 1 1 0 0 1 14 0 41 CD wet n a lt a n The first of the two n operands in the assembled object code above is the least significant byte of a 2 byte memory address Description The current contents of the Program Counter PC are pushed onto the top of the external memory stack The operands nn are then loaded to the PC to point to the address in memory where the first Op Code of a subroutine is to be fetched At the end of the subroutine a RETurn instruction can be used to return to the original program flow by popping the top of the stack back to the PC The push is accomplished by first decrementing the current contents of the Stack Pointer register pair SP loading the high order byte of the PC contents to the memory address now pointed to by the SP then decrementing SP again and loading the low order byte of the PC contents to the top of stack Because this is a 3 byte instruction the Program Counter was incremented by three before the push is executed M Cycles T States 4 MHz E T 5 17 4 3 4 3 3 4 25 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z 256 ZiLOG Example If the contents of the Program Counter are 1A47H the contents of the Stack Pointer are 3002H and memory locations have the contents 1
81. RE IMPLEMENTATION EXAMPLES Overview of Software Features The Z80 instruction set provides the user with a large number of operations to control the Z80 CPU The main alternate and index registers can hold arithmetic and logical operations form memory addresses or act as fast access storage for frequently used data Information can be moved directly from register to register from memory to memory from memory to registers or from registers to memory In addi tion register contents and register memory contents can be exchanged without using temporary storage In particular the contents of main and alternate registers can be completely exchanged by executing only two instructions EX and EXX This register exchange procedure can be used to separate the set of working registers from different logical procedures or to expand the set of available registers in a single procedure Storage and retrieval of data between pairs of registers and memory can be controlled on a last in first out basis through PUSH and POP instructions that utilize a special STACK POINTER register SP This stack register is available both to manipulate data and to automatically store and retrieve addresses for subroutine linkage When a subroutine is called for example the address following the CALL instruction is placed on the top of the push down stack pointed to by SP When a subroutine returns to the calling routine the address on the top of the stack is used to
82. The mnemonic equivalent of this is CALL NC 2135H At execution of this instruction the contents of memory address 3001H is 1AH the contents of address 3000H is 4AH the UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual zitog 259 contents of the Stack Pointer is 3000H and the contents of the Program Counter is 2135H pointing to the address of the first Op Code of the subroutine now to be executed UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 260 ZiLOG Operation Op Code Description RET pCL lt sp pCH lt sp 1 RET 1 1 0 0 1 0 0 1 C9 The byte at the memory location specified by the contents of the Stack Pointer SP register pair is moved to the low order eight bits of the Program Counter PC The SP is now incremented and the byte at the memory location specified by the new contents of this instruction is fetched from the memory location specified by the PC This instruction is normally used to return to the main line program at the completion of a routine entered by a CALL instruction M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the contents of the Program Counter are 3535H the contents of the Stack Pointer are 2000H the contents of memory location 2000H are B5H and the contents of memory location of memory location 2001H are 18H At execution of RET the contents of the Stack Point
83. User s Manual ZiLOG Overview ARCHITECTURE The ZiLOG Z80 CPU family of components are fourth generation enhanced microprocessors with exceptional computational power They offer higher system throughput and more efficient memory utilization than comparable second and third generation microprocessors The speed offerings from 6 20 MHz suit a wide range of applications which migrate software The internal registers contain 208 bits of read write memory that are accessible to the programmer These registers include two sets of six general purpose registers which may be used individually as either 8 bit registers or as 16 bit register pairs In addition there are two sets of accumulator and flag registers The Z80 CPU also contains a Stack Pointer Program Counter two index registers a REFRESH register and an INTERRUPT register The CPU is easy to incorporate into a system since it requires only a single 5V power source All output signals are fully decoded and timed to control standard memory or peripheral circuits the Z80 CPU is supported by an extensive family of peripheral controllers Figure 1 illustrates the internal architecture and major elements of the Z80 CPU UM008004 1 204 Overview Z80 CPU User s Manual 2 ErEOG Data Bus Control Inst i lt Register Internal Data Bus Pa ALU H y an System CPU CPU Control Control Re
84. Y d BED By tg ek cc Bas eee ed CALL CG N sigs ccs sorrow and ae 8 8 CAL GI 6 54 ceekek ek eae ki UM008004 1204 Z80 CPU User s Manual ZitoG List of Instructions x Z80 CPU User s Manual ZiL LOG Elea ean geek secs A a aa pce eee eee ee 175 EX SP HLE reiia eel oe hen het Ge et ee 125 EX SP DX oo sccsenense iid te noonea eae EE ane andy E E EAE 126 EX SP IY alesen beawonesva dragged aden jun ie aided Bre adda belo heed 127 EEA AE 024 5 aa cast hk ag Grea ach wale Gea loth tb sats Cat e e aa 123 EX DE Doe ao 8 suse fore haan eh asain has ele acetal oes eke 122 PAX oo e esses aspen tse agree ean een BAe Sete eee 124 HALE ices chick a etree asp ean se begs wade ak ge Se ac ate ee 173 IMO rers sets Sak eked Be ae od Rand aah Shee Ha Sh a ea 176 Me Bo se aaa paces ot apctnde essa rs E E atest carson tah 2 fect es tat at Selva crates 177 IM 2 ss Sind deh og ad hansa oe dS a tay dbo eal dette halberd dies atc on esoets 178 TIN AS DY Senden EEE E Brie ante canis EE E ol dha aeeed ne 269 TIN CY E E E E ears arson A EE ATE E E E E AT 270 INC HC isa dae hig miaa nea aa anha a che dead daa a A aad 161 ING CIX4 0 edo ds Gee ao eet he eet y ia 162 ING IY FO 2 5 28d eae Sha ee i ee i 163 TIN CX eredi Secs stare hose see ia se dhe e tetera ENEE E a nes Arse ARS hon dashes 185 INC DY 2d sbtes seoeea es aterm nels steers ean weenie es EEEE ENTE 4 186 INCE eas ck aoe E a wg arash tse wig sian aid E A
85. ands A nn olo 1 1 1 0 1l 04 3A lt a n gt lt a n p Description The contents of the memory location specified by the operands nn are loaded to the Accumulator The first n operand after the Op Code is the low order byte of a 2 byte memory address M Cycles T States 4 MHZ E T 4 13 4 3 3 3 3 25 Condition Bits Affected None Example If the contents of nn is number 8832H and the content of memory address 8832H is byte 04H at instruction LD A nn byte 04H is in the Accumulator UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 95 LD BC A Operation BC lt A Op Code LD Operands BC A 0 0 0 0 0 0 1 o 0 Description The contents of the Accumulator are loaded to the memory location specified by the contents of the register pair BC M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the Accumulator contains 7AH and the BC register pair contains 1212H the instruction LD BC A results in 7AH in memory location 1212H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 96 ZiLOG LD DE A Operation DE lt A Op Code LD Operands DE A folofo ojol1 o Description The contents of the Accumulator are loaded to the memory location specified by the contents of the DE register pair M cycles T States 4 MHz E T 2 7 4 3 1 7
86. are Cc 7 6 5 4 8 2 1 0 1 010 0 1 0 0 01 UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 191 RLA 0 0 0 1 0 111 1117 The contents of the Accumulator register A are rotated left 1 bit position through the Carry flag The previous content of the Carry flag is copied to bit 0 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected Condition Bits Affected Example S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 7 of Accumulator If the contents of the Accumulator and the Carry flag are Cc 7 6 5 4 3 2 1 0 1 0 1 1 1 0 1 1 0 at execution of RLA the contents of the Accumulator and the Carry flag are C 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 0 1 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 192 zitoc Operation Op Code Operands Description RRCA ol ofo oj 4 4 1 oF The contents of the Accumulator register A are rotated right 1 bit position Bit 0 is copied to the Carry flag and also to bit 7 Bit O is the least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected Example S
87. ates 4 MHZ E T 4 15 4 4 4 3 3 75 Condition Bits Affected Example S is not affected Z is not affected H is set if carry out of bit 11 reset otherwise P V is not affected N is reset C is set if carry from bit 15 reset otherwise If the contents of Index Register IY are 33 3H and the contents of register pair BC are 555H at execution of ADD IY BC the contents of IY are 8888H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 184 ZiLOG INC ss Operation ss lt ss 1 Op Code INC Operands ss 0 0 s s 0 Of 1 1 Description The contents of register pair ss any of register pairs BC DE HL or SP are incremented Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 1 6 1 50 Condition Bits Affected None Example If the register pair contains 1000H after the execution of INC HL HL contains 1001H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual zitog 185 INC IX Operation IX lt Ix 1 Op Code INC Operands IX 1 1 0 1 0 DD 0 0 1 0 1 23 Description The contents of the Index Register IX are incremented M Cycles T States 4 MHz E T 10 4 6 2 50 Condition Bits Affected None Example If the Index Register IX contains the integer 3300H at execution of INC IX the contents of Index Register IX are 3301H
88. ation 1001H contains 33H the instruction POP IY results in Index Register IY containing 3355H and the Stack Pointer containing 1002H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 122 zitoc Exchange Block Transfer and Search Group EX DE HL Operation DE lt gt HL Op Code EX Operands DE HL 1 1 1 0 1 0 1 1 EB Description The 2 byte contents of register pairs DE and HL are exchanged M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If the content of register pair DE is the number 2822H and the content of the register pair HL is number 499AH at instruction EX DE HL the content of register pair DE is 499AH and the content of register pair HL is 2822H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 123 EX AF AF Operation AF lt AF Op Code EX Operands AF AF 0 0 0 0 14 0 4 0 0 08 Description The 2 byte contents of the register pairs AF and AF are exchanged Register pair AF consists of registers A and F M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If the content of register pair AF is number 9900H and the content of register pair AF is number 5944H at instruction EX AF AF the contents of AF is 5944H and the contents of AF is 9900H UM008004 1204 Z80 Instruction Set 124 Z80 CPU User s Manual ZiLO
89. ca tint ee Sed ee a eee ee 115 EDD irec cee he Ske HR ee eee ed beat pk ea 131 EDDR oh dei termi Peas i Suen same a E ee tuleeee 132 EDI i000 heueeesLecwasgh ewes laewadeiaten da E E 128 LDIR versioi bed oe Che eae E ea dae 129 NEG car jain Ghee ea dle Pk EA ee ec da eke eek ed one ee 169 NOP 2s Aetane laine tae oasdasieakian sea nian Hoke daS 172 ORS ccccietod atten dark atau aes ede E nada ein a ES 154 OTDR a c054 nete cra che eda EON eds Sod a i a 286 OTIR scnccicineosneTadbuietade tediate ladtea Lede ada 283 OUT OC T senie ctw ie ek i ls die 280 OUT MJA seed iia eee ead E Gee kale E ened E ean dae athena 279 QUID 5 0832 chee ae es eee Rea ea Eee 285 OUEL acd S035 anette ated ad gonda wt dbs bide a Bodden hg ance e ees 282 POP IX fee tiie te bee tiia ies deed de Sed hee hoe 120 POP TY picisiatitea shin eee kka SOA kA cede ea 121 POP Gis sdectas edad dodge E EE Lo eee iu ane etna neat 119 PUSH IX 6 vas coedeus ertem aaa E ead dale oa dae dadalw aware 117 PUSHUTY evict tet hacdeie baci de aes Aa ta thes eae Ae oe 118 PUSH daescaire ech tad detent diane aoe eae 116 RES D Mi aeos eioan coarse a suianaiestagleaventa A E EE EG 236 RED E E ad E 260 RET GC os pias noen t eia eke ie be al he edie eae 261 RETE serenodre tt nis aea E E T EEN E EE E as edo 263 RETIN scccninn ete nahi dei al bea hes eel 265 REA cu cite eee sae lathe dean la tee eeeee 202 RL Ag oi athe tiie ein eee E Oba aie ean satin 191 REC AL 4 4 stowid sa mienne siautedd s
90. cacetd oneedads caddy 196 RLC X ie certius esd net eek ea bee ek eee betas 198 RLC YFA cs seg ee edd Ae ee ead ee ee eee bs 200 RECT peta nhs sd eae ear ene ieee dae nde A 194 RLCA ceras Lead nt eee est Loqwus abana eoene te een de 190 RED aeei e igne Sia ae cha ea eda eli eee 220 RRM eso cen tha etek heels la ean elke bee ade aa ee 208 List of Instructions UM008004 1204 Z80 CPU User s Manual ZiLOG T XIII RRAY a a eh bh eh is ee de ied ot beet 193 RRG A hei sessocr ew dos toeacnerarenauenareelars eaa She w wtbyhes Gio ed don aie 205 RRCA canine nEn beats od a aad bn ewe go bears davon bia Raa Bae 192 el ana eS grt a Wr OT SPS OR E E A 222 RST D s2 nto hei a eiga rat ira add niaw etd ceeded weed ees 267 SBCA Suessi gg EEE OEE GS sow and gwen op anda he eee 150 SBC HIS SS eraun sudan esta gia alani ae ae oa ete eas eae es 181 SCE g ode EE EE Seon aided amp Suh andl deh hbtia Sheed 171 SET Ds CHDS oien eea a E i Mo Olva nd edo Oded eae whee tale ws 233 SET OIX AG ciie edi bbe hia ia eee ees dhe wey eh oe 234 SETDA EI aco tek ck oe dose aes ted lncaciog aed ded a aioe E aad ere 8 a an 235 SED Byres eea E aaa a atau bn lathes be ee te Seeds 232 SLA E e aE E Een gO a ET 211 SRAI dm indo dod hiina e aiaa pa e a a a A wen S 214 SRE Tis ge ceoe ates decane 8 a AE ga E E daw E deg ete we E E 217 SUBS cnain Bea wan taeda WG aie dia eo EA were a waa andes CaS 148 XOR Srne a EEEE wiv E E NA A E N 156 UM008004 1204 List of Instr
91. can be used to make very fast interrupt response times UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z ZiLOG Table 3 16 Bit Load Group LD PUSH and POP Source Register Imm Ext Ext Addr Reg Indir Register AF BC DE HL SP X IY nn nn SP AF BC DE HL SP DD FD F9 F9 IX n n n n TY FD FD FD 21 2A El n n n n EXT nn ED ED ED DD FD ADDR 43 53 73 22 22 n n n n n n n n n n PUSH REG SP DD FD Instructions gt IND E6 E6 NOTE The Push amp Pop instruction adjust the SP after every execution i POP UM008004 1204 Z80 CPU Instruction Description Instructions 55 56 Z80 CPU User s Manual ZiLOG Table 4 Exchanges EX and EXX Implied Addressing AF BC DE and HL HL IX_ IY IMPLIED AF 08 BC DE D9 HL DE REG SP DD FD IND E3 E3 Block Transfer and Search Table 5 lists the extremely powerful block transfer instructions These instructions operate with three registers HL points to the source location DE points to the destination location BC isa byte counter After the programmer initializes these three registers any of these four instructions can be used The LDI Load and Increment instruction moves one byte from the location pointed to by HL to the location pointed to by DE R
92. clock periods to complete or they can be lengthened to synchronize the CPU to the speed of external devices The clock periods are referred to as T time cycles and the operations are referred to as M machine cycles Figure 4 illustrates how a typical instruction is series of specific M and T cycles Notice that this instruction consists of three machine cycles M1 M2 and M3 The first machine cycle of any instruction is a fetch cycle which is four five or six T cycles long unless lengthened by the WAIT signal which is described in the next section The fetch cycle M1 is used to fetch the opcode of the next instruction to be executed Subsequent machine cycles move data between the CPU and memory or I O devices and they may have anywhere from three to five T cycles again they may be lengthened by wait states to synchronize the external devices to the CPU The following paragraphs describe the timing which occurs within any of the basic machine cycles During T2 and every subsequent Tw the CPU samples the WAIT line with the falling edge of Clock If the WAIT line is active at this time another WAIT state is entered during the following cycle Using this technique the read can be lengthened to match the access time of any type of memory device UM008004 1204 Overview Z80 CPU User s Manual 12 ZiLOG Machine Cycle M1 M2 M3 Opcode Fetch Memory Read Memory Write Instruction Cycle e E Figure 4 Basic CPU Timi
93. counter is decremented by two and the instruction is repeated Interrupts are recognized and two refresh cycles execute after each data transfer When BC is set to zero prior to instruction execution the instruction loops through 64 Kbytes if no match is found For BC OandA HL M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 and A HL M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is set if result is negative reset otherwise Z is set if A HL reset otherwise H is set if borrow form bit 4 reset otherwise P V is set if BC 1 0 reset otherwise N is set C is not affected UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z ZiLOG 139 Example If the HL register pair contains 1118H the Accumulator contains F3H the Byte Counter contains 0007H and memory locations have these contents 1118H contains 52H 1117H contains 00H 1116H contains F3H Then at execution of CPDR the contents of register pair HL are 1115H the contents of the Byte Counter are 0004H the P V flag in the F register sets and the Z flag in the F register sets UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 140 ZiLOoG 8 Bit Arithmetic Group Operation Op Code Operands Description ADD A r A lt Atr ADD A r 1 0 0 0 0 lt r The contents of register r are added to the contents of th
94. cremented as each byte is pushed onto or popped from the stack respectively For example the instruction PUSH AF is a single byte instruction with the Op Code of F5H During execution this sequence is generated Decrement SP LD SP A Decrement SP LD SP F The external stack now appears as UM008004 1204 Z80 CPU Instruction Description 54 Z80 CPU User s Manual Z ZiLOG SP F e Top of stack SP 1 A The POP instruction is the exact reverse of a PUSH All PUSH and POP instructions utilize a 16 bit operand and the high order byte is always pushed first and popped last PUSH BC is PUSH 8 then C PUSH DE is PUSH D then E PUSH HL is PUSH H then L POP HL is POP L then H The instruction using extended immediate addressing for the source requires two bytes of data following the Op Code For example LD DE 0659H appears as Address A E6 Op Code A 1 07 Operand In all extended immediate or extended addressing modes the low order byte always appears first after the Op Code Table 4 lists the 16 bit exchange instructions implemented in the Z80 Op Code 08H allows the programmer to switch between the two pairs of accumulator flag registers while D9H allows the programmer to switch between the duplicate set of six general purpose registers These Op Codes are only one byte in length to minimize the time necessary to perform the exchange so that the duplicate banks
95. ct code field above Register rroemoaw UM008004 1204 000 O01 010 011 100 101 111 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 165 Description The byte specified by the m operand is decremented Instruction M Cycles T States 4 MHz E T DEC r 1 4 1 00 DEC HL 3 11 4 4 3 2 75 DEC IX d 6 23 4 4 3 5 4 3 5 75 DEC 1Y d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if borrow from bit 4 reset otherwise P V is set if m was 80H before operation reset otherwise N is set C is not affected Example If the D register contains byte 2AH at execution of DEC D register D contains 29H UM008004 1204 Z80 Instruction Set 166 Z80 CPU User s Manual ZiLOG General Purpose Arithmetic and CPU Control Groups DAA Operation Op Code DAA 0 0 0 0 1 1 1 27 Description This instruction conditionally adjusts the Accumulator for BCD addition and subtraction operations For addition ADD ADC INC or subtraction SUB SBC DEC NEG the following table indicates the operation performed Hex Value Hex Value In In Lower Number C Before Upper Digit H Before Digit Added To C After Operation DAA bit 7 4 DAA bit 3 0 Byte DAA 0 9 0 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 INC 0 A F 1 0 3 66 1 1 0 2
96. ct the I O device at one of 256 possible ports Register B may be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus The byte to be output is placed on the data bus and written to a selected peripheral device Finally the register pair HL is incremented M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected Example S is unknown Z is set if B 1 0 reset otherwise H is unknown P V is unknown N is set C is not affected If the contents of register C are 07H the contents of register B are 10H the contents of the HL register pair are 100014 and the contents of memory address 1000H are 5914 then after thee execution of OUTI register B contains OFH the HL register pair contains 1001H and byte 59H is written to the peripheral device mapped to I O port address 07H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 283 OTIR Operation C lt HL B B 1 HL HL 1 Op Code OTIR 1111 1 0 1 1 0 1 ED 1 0J 1 1 0 0 1 1 B3 Description The contents of the HL register pair are placed on the address bus to select a location in memory The byte contained in this memory location is tempo rarily stored in the CPU Then after the byte counter B is decremented the contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device a
97. ctive Low Bus Acknowledge indicates to the requesting device that the CPU address bus data bus and control signals MREQ IORQ RD and WR have entered their high impedance states The external circuitry can now control these lines BUSREQ Bus Request input active Low Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle BUSREQ forces the CPU address bus data bus and control signals MREQ IORQ RD and WR to go to a high impedance state so that other devices can control these lines BUSREQ is normally wired OR and requires an external pull up for these applications Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS D7 D0 Data Bus input output active High tristate D7 D0 constitute an 8 bit bidirectional data bus used for data exchanges with memory and I O HALT HALT State output active Low HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non maskable or a maskable interrupt with the mask enabled before operation can resume During HALT the CPU executes NOPs to maintain memory refresh INT Interrupt Request input active Low Interrupt Request is generated by T O devices The CPU honors a request at the end of the current instruction if the internal software controlled interrupt enable flip flop IFF is enabled INT is normally wired OR and require
98. d the instruction automatically terminates Both the block transfer and the block search instructions can be interrupted during their execution so they do not occupy the CPU for long periods of time The arithmetic and logical instructions operate on data stored in the accumulator and other general purpose CPU registers or external memory locations The results of the operations are placed in the accumulator and the appropriate flags are set according to the result of the operation An example of an arithmetic operation is adding the accumulator to the contents of an external memory location The results of the addition are placed in the accumulator This group also includes 16 bit addition and subtraction between 16 bit CPU registers The rotate and shift group allows any register or any memory location to be rotated right or left with or without carry either arithmetic or logical Also a digit in the accumulator can be rotated right or left with two digits in any memory location The bit manipulation instructions allow any bit in the accumulator any general purpose register or any external memory location to be set reset or tested with a single instruction For example the most significant bit of register H can be reset This group is especially useful in control applications and for controlling software flags in general purpose programming The JUMP CALL and RETURN instructions are used to transfer between various locations in the
99. d by the execution of certain instructions is 0 For 8 bit arithmetic and logical operations the Z flag is set to a 1 if the resulting byte in the Accumulator is 0 If the byte is not 0 the Z flag is reset to 0 For compare Search instructions the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the Register pair HL When testing a bit in a register or memory location the Z flag contains the complemented state of the indicated bit see Bit b s UM008004 1204 Z80 Instruction Set 80 Z80 CPU User s Manual ZiLOG When inputting or outputting a byte between a memory location and an I O device INI IND OUTI and OUTD if the result of decrementing the B Register is 0 the Z flag is 1 otherwise the Z flag is 0 Also for byte inputs from I O devices using IN r C the Z flag is set to indicate a 0 byte input Sign Flag The Sign Flag S stores the state of the most significant bit of the Accumulator bit 7 When the Z80 performs arithmetic operations on signed numbers the binary twos complement notation is used to represent and process numeric information A positive number is identified by a 0 in Bit 7 A negative number is identified by a 1 The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127 A negative number is represented by the twos complement of the equivalent positi
100. d object code UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 231 Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 LEL M Cycles T States 4 MHz E T 5 20 4 4 3 5 4 5 00 Condition Bits Affected S is unknown Z is set if specified Bit is 0 reset otherwise H is set P V is unknown H is reset C is not affected Example If the contents of Index Register are 2000H and bit 6 in memory location 2004H contains 1 at execution of BIT 6 IY 4H the Z flag and the F register still contain 0 and bit 6 in memory location 2004H still contains 1 Bit 0 in memory location 2004H is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 232 zitoe Operation rb lt 1 Op Code SET Operands b r SET b r 0 0 1 0 1 1 CB a b a r Description Bit b in register r any of registers B C D E H L or A is set Operands b and r are specified as follows in the assembled object code Bit b Register r 0 000 B 000 1 001 C 001 2 010 D 010 3 011 E 011 4 100 H 100 5 101 L 101 6 110 A 111 7 igi M Cycles T States4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Example At execution of SET 4 A bit 4 in register A sets Bit 0 is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 233 SET b HL Operation HL b lt 1 Op Code SET Operands b
101. d rotate instructions to indicate the resulting parity is Even The number of 1 bits in a byte are counted If the total is Odd ODD parity is flagged P 0 If the total is Even EVEN parity is flagged P 1 During search instructions CPI CPIR CPD CPDR and block transfer instructions LDI LDIR LDD LDDR the P V Flag monitors the state of the UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 79 Byte Count Register BC When decrementing if the byte counter decrements to 0 the flag is cleared to 0 otherwise the flag is set to1 During LDA I and LDA R instructions the P V Flag is set with the value of the interrupt enable flip flop IFF2 for storage or testing When inputting a byte from an I O device with an IN r C instruction the P V Flag is adjusted to indicate the data parity Half Carry Flag The Half Carry Flag H is set 1 or cleared 0 depending on the Carry and Borrow status between Bits 3 and 4 of an 8 bit arithmetic operation This flag is used by the Decimal Adjust Accumulator instruction DAA to correct the result of a packed BCD add or subtract operation The H Flag is set 1 or cleared 0 according to the following table H Flag Add Subtract 1 A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs 0 No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs Zero Flag The Zero Flag Z is set 1 or cleared 0 if the result generate
102. d with the HALT instruction is shown in Figure 12 T Te ia T4 T T Ts T CLK g s MI HALT Figure 12 Power Down Acknowledge UM008004 1204 Overview Z80 CPU User s Manual 20 ZiLOG Power Down Release Cycle The system clock must be supplied to the CMOS Z80 CPU to release the power down state When the system clock is supplied to the CLK input the CMOS Z80 CPU restarts operations from the point at which the power down state was implemented The timing diagrams for the release from power down mode are featured in Figure 13 14 and 15 When the HALT instruction is executed to enter the power down state the CMOS Z80 CPU also enters the HALT state An interrupt signal either NMI or ANT or a RESET signal must be applied to the CPU after the system clock is supplied in order to release the power down state HALT Figure 13 Power Down Release Cycle No 1 T T2 T Ts CLK me y MI HALT z i Figure 14 Power Down Release Cycle No 2 UM008004 1204 Overview Z80 CPU User s Manual Figure 15 Power Down Release Cycle No 3 UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG INTERRUPT RESPONSE Overview An interrupt allows peripheral devices to suspend CPU operation and force the CPU to start a peripheral service routine This service routine usually involves the exchange of data status or control informati
103. dded to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC This jump is measured from the address of the instruction Op Code and has a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 Condition Bits Affected None Example To jump forward five locations from address 480 the following assembly language statement is used JR 5 The resulting object code and final PC value is shown below UM008004 1204 Location 480 481 482 483 484 485 Instruction 18 03 lt PC after jump Z80 Instruction Set 242 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description JRC e If C 0 continue IfC 1 PC lt PC e JR C e 0 0 1 1 1 0 0 0 38 lt a e 2 This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag If the flag is equal to a 1 the value of the displacement e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction Op Code and has a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the flag is equal to a O the next instr
104. des the lower eight bits of the address This feature allows interrupt routines to be dynamically located anywhere in memory with minimal access time to the routine Memory Refresh Register R The Z80 CPU contains a memory refresh counter enabling dynamic memories to be used with the same ease as static memories Seven bits of this 8 bit register are automatically incremented after each instruction fetch The eighth bit remains as programmed resulting from an LD R A instruction The data in the refresh counter is sent out on the lower portion of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction This mode of refresh is transparent to the programmer and does not slow the CPU operation The programmer can load the R register for testing purposes but this register is normally not used by the programmer During refresh the contents of the I register are placed on the upper eight bits of the address bus UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG Accumulator and Flag Registers The CPU includes two independent 8 bit accumulators and associated 8 bit flag registers The accumulator holds the results of 8 bit arithmetic or logical operations while the FLAG register indicates specific conditions for 8 bit or 1 16 bit operations such as indicating whether or not the result of an operation is equal to zero The programmer selects the accumulator and flag pair with a
105. dress A Pointer to Interrupt Table Register is Upper Address Peripheral Supplies Lower Address Address of Interrupt Service Routine 4 UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z 72 ZiLOG Table 14 Input Group Register Immed Indir n c Input Input IN Register A ED Destination Address 7B INI input amp Register HL ED Block inc HL Dec B Indir A2 Input INIR INP Inc HL ED Commands Dec B repeat IF B40 B2 IND input amp Inc ED Dec HL Dec B AA INDR input Dec HL ED Dec B repeat IF B40 BA UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG Table 15 8 Bit Arithmetic and Logic Source Register Register Indir A B C D JE JH L D 110UT Immed n Reg c ED ED ED JED ED ED ED Ind 79 41 49 51 59 61 69 110UT output ED Block inc HL dec B A3 Output HOUT output ED Command dec B repeat if B40 B3 11OUT output ED dec HL and B AB 11OUTDR output dec HL and B ED repeat IF B40 BB Port Destination Address Table 16 Miscellaneous CPU Control NOP HALT Disable INT ED Enable INT D Set INT mode 0 IMO 46 Set INT mode 1 ED IMI 56 Set INT mode 2 ED IM2 SE UM008004 1204 8080A mode Call to location 0038H
106. during each T4 state as depicted in Figure 11 If a non maskable interrupt has been received or a maskable interrupt has been received and the interrupt enable flip flop is set then the HALT state is exited on the next rising clock edge The following cycle is an interrupt acknowledge cycle corresponding to the type of interrupt that was received If both are received at this time then the non maskable one is acknowledged since it has highest priority The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh signals active Each cycle in the HALT state is a normal M1 fetch cycle except that the data received from the memory is ignored and a NOP instruction is forced internally to the CPU The HALT acknowledge signal is active during this time indicating that the processor is in the HALT state UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG 19 CLK HALT RD or NMI HALT Instruction is repeated during this Memory Cycle Figure 11 HALT Exit Power Down Acknowledge Cycle When the clock input to the CMOS Z80 CPU is stopped at either a High or Low level the CMOS Z80 CPU stops its operation and maintains all registers and control signals However ICC2 standby supply current is guaranteed only when the system clock is stopped at a Low level during T4 of the machine cycle following the execution of the HALT instruction The timing diagram for the power down function when implemente
107. e LD Operands TY nn 1 1 1117 1 1 0 f14 FD 0101 0 1 01 O 2A a n B T n a Description The contents of address nn are loaded to the low order portion of Index Register IY and the contents of the next highest memory address nn 1 are loaded to the high order portion of TY The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If address 6666H contains 92H and address 6667H contains DAH at instruction LD TY 6666H the Index Register IY contains DA92H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 109 LD nn HL Operation nn 1 lt H nn L Op Code LD Operands nn HL 0 0 4 O 0 O o 2 a n a n Description The contents of the low order portion of register pair HL register L are loaded to memory address nn and the contents of the high order portion of HL register H are loaded to the next highest memory address nn 1 The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 5 16 4 3 3 3 3 4 00 Condition Bits Affected None Example If the content of register pair HL is 483AH at instruction LD B2291 1 HL address B229H contains 3AH and address B22AH contains 48H UM008004 1204 Z80 Ins
108. e OUT n A routine is complete Enable Interrupt Return This seven byte sequence can be replaced with the one byte EI instruction and the two byte RETI instruction in the Z80 This is important because interrupt service time often must be minimized Table 11 Bit Manipulation Group Register Addressing Reg Indir Indexed A 8 C D E H L HL IX d TY d Bit DD FD UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual 66 ErEOG Table 11 Bit Manipulation Group Continued Register Addressing Reg Indir Indexed Test 0 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 Bit 47 40 41 42 43 44 45 46 d d 46 46 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 4F 48 49 4A 48 4C 4D 4E d d 4E 4E DD FD 2 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 57 50 51 52 53 54 55 56 d d 56 56 DD FD 3 C8 c8 C8 C8 C8 C8 C8 C8 C8 C8 SF 58 59 5A 5B 5C 5D 5E d d 46 46 DD FD 4 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 67 60 61 62 63 64 65 66 d d 66 66 DD FD 5 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 6F 68 69 6A 68 6C 6D 6E d d 6E 6E DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 77 70 71 72 73 74 75 76 d d 76 76 DD DD 7 C8 C8 C8 C8 C8 C8 CS C8 C8 C8 TF 78 79 7A 78 7C 7D TE d d 46 46 UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG Table 11 Bit Manipulation Group Continued Register Addressing Reg Indir
109. e The parentheses indicate that this value is used as a pointer to external memory Register Addressing Many of the Z80 Op Codes contain bits of information that specify which CPU register is to be used for an operation An example of register addressing is to load the data in register 6 into register C Implied Addressing Implied addressing refers to operations where the Op Code automatically implies one or more CPU registers as containing the operands An example is the set of arithmetic operations where the accumulator is always implied to be the destination of the results Register Indirect Addressing This type of addressing specifies a 16 bit CPU register pair such as HL to be used as a pointer to any location in memory This type of instruction is very powerful and it is used in a wide range of applications Op Code L One or Two Bytes An example of this type of instruction is to load the accumulator with the data in the memory location pointed to by the HL register contents Indexed addressing is actually a form of register indirect addressing UM008004 1204 Z80 CPU Instruction Description 48 Z80 CPU User s Manual ZiLOG except that a displacement is added with indexed addressing Register indirect addressing allows for very powerful but simple to implement memory accesses The block move and search commands in the Z80 are extensions of this type of addressing where automatic register incrementing decrementi
110. e Accumulator and the result is stored in the Accumulator The symbol r identifies the registers A B C D E H or L assembled as follows in the object code Register r 111 000 001 010 O11 100 101 cles T States 4 MHz E T 4 1 00 rFomoaaeep MC lt Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if overflow reset otherwise N is reset C is set if carry from bit 7 reset otherwise UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual zitog 141 Example If the contents of the Accumulator are 44H and the contents of register C are 11H at execution of ADD A C the contents of the Accumulator are 55H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 142 ZiLOG Operation Op Code Operands Description ADD A n AA n ADD A n 1 1 0 0 0 1 1 0 C6 lt a n The integer n is added to the contents of the Accumulator and the results are stored in the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if overflow reset otherwise N is reset C is set if carry from bit 7 reset otherwise If the contents
111. ect code OR r 1 Oj 1 1 O ma rm gt ORn 1 1 1 1 0 41 4 04 F6 OR HL 1 0 1 1 0 4141 1 0 B6 OR IX d 1 1 0 1 1 1 0 1 DD OR IY d 1 4 4 14 14 4 4 0 4 14 4 FD 1 0 1 1 0 144 0 Be a d gt r identifies registers B C D E H L or A specified as follows in the assembled object code field above UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 157 Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The logical exclusive OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator the result is stored in the Accumulator Instruction M Cycles T States 4 MHz E T XOR r 1 4 1 00 XOR n 2 7 4 3 1 75 XOR HL 2 7 4 3 1 75 XOR IX d 5 19 4 4 3 5 3 4 75 XOR l1Y d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is reset Example If the Accumulator contains 96H 1001 0110 at execution of XOR 5DH 5DH 0101 1101 the Accumulator contains CBH 1100 1011 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 158 ZiLOG CPs Operation A s Op Code CP Operands s The s operand is any of r n HL
112. efresh read of all memory elements The refresh signal can not be used by itself because the refresh address is only guaranteed to be stable during MREQ time M1 Cycle Figure 5 Instruction Op Code Fetch Memory Read Or Write Figure 6 illustrates the timing of memory read or write cycles other than an Op Code fetch cycle These cycles are generally three clock periods long unless wait states are requested by the memory through the WAIT signal The MREQ signal and the RD signal are used the same as in the fetch cycle In a memory write cycle the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories The WR line is active when data on the data bus is stable so that UM008004 1 204 Overview 13 14 Z80 CPU User s Manual ZiLOG it can be used directly as a R W pulse to virtually any type of semiconductor memory Furthermore the WR signal goes inactive one half T state before the address and data bus contents are changed so that the overlap requirements for almost any type of semiconductor memory type is met Memory Read Cycle Memory Write Cycle CLK Ais Ao y m MREQ zoe a F a o D7 Do Data Out WAIT Figure 6 Memory Read or Write Cycle Input or Output Cycles Figure 7 illustrates an I O read or I O write operation During I O operations a single wait state is automatically inserted The reason is that during I
113. egister pairs HL and DE are then automatically incremented and are ready to point to the following locations The byte counter register pair BC is also decremented at this time This instruction is valuable when blocks of data must be moved but other types of processing are required between each move The LDIR Load Increment and Repeat instruction is an extension of the LDI instruction The same load and increment operation is repeated until the byte counter reaches the count of zero Thus this single instruction can move any block of data from one location to any other UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 57 Because 16 bit registers are used the size of the block can be up to 64 Kbytes 1K 1024 long and can be moved from any location in memory to any other location Furthermore the blocks can be overlapping because there are no constraints on the data used in the three register pairs The LDD and LDDR instructions are very similar to the LDI and LDIR The only difference is that register pairs HL and DE are decremented after every move so that a block transfer starts from the highest address of the designated block rather than the lowest Table 6 specifies the Op Codes for the four block search instructions The first CPI Compare and Increment compares the data in the accumulator with the contents of the memory location pointed to by register HL The result of the compare is stored in o
114. emented and the Byte Counter register pair BC is decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if A is HL reset otherwise His set if borrow from bit 4 reset otherwise P V is set if BC 1 is not 0 reset otherwise N is set C is not affected If the HL register pair contains 1111H memory location 1111H contains 3BH the Accumulator contains 3BH and the Byte Counter contains 0001H At execution of CPI the Byte Counter contains 0000H the HL register pair contains 1112H the Z flag in the F register sets and the P V flag in the F register resets There is no effect on the contents of the Accumulator or address 1111H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 135 CPIR A HL HL 4 HL 1 BC lt BC 1 CPIR 1 1 1 0 14 14 0 14 ED 1 0 1 1 0 0 0 1 BI The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator In case of a true compare a condition bit is set HL is incremented and the Byte Counter register pair BC is decremented If decrementing causes BC to go to zero or if A HL the instruction is terminated If BC is not zero and A HL the program counter is decremented by two and the instruction is repeated Interru
115. er 0006 05 26 dec b adjust for testing 0007 dd2a2600 27 Id ix data initialize array pointer 000b dd7e00 28 next Id a ix first element in comparison 000e 57 29 ld d a temporary storage for element goof dd5e01 30 ld e ix 1 second element in comparison 0012 93 31 sub e comparison first to second 0013 3008 32 jr pc noex _ if first gt second no jump 0015 dd7300 33 Id ix e exchange array elements 0018 dd7201 34 Id ix i d 00lb cbc4 35 set flag h record exchange occurred 0010 dd23 36 noex linc 1X point to next data element OOI1f 10ea 37 djnz next count number of comparisons 38 repeat if more data pairs 0021 cb44 39 bit flag h determine if exchange occurred 0023 20de 40 jr nz loop continue if data unsorted 0025 c9 41 ret otherwise exit 42 d UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual ZiLOG Table 1 Bubble Listing Continued Loc 0026 0026 Obj Code Stmt Source Statement 43 flag _jequ designation of flag bit 44 data defs 2 storage for data address 45 end The following program see Table 2 multiplies two unsigned 16 bit integers leaving the result in the HL register pair Table 2 Multiply Listing Obj Loc Code Stmt Source Statement 0000 1 mult unsigned sixteen bit integer multiply 2 on entrance multiplier in de 3
116. er indirect and indexed addressing are available to operate on external memory locations Bit test operations set the Zero flag Z if the tested bit is a zero Jump Call and Return Table 12 lists all the jump call and return instructions implemented in the Z80 CPU A jump is a branch in a program where the program counter is loaded with the 16 bit value as specified by one of the three available addressing modes Immediate Extended Relative or Register Indirect Notice that the jump group has several conditions that can be specified before the jump is made If these conditions are not met the program merely continues with the next sequential instruction The conditions are all dependent on the data in the flag register The immediate extended addressing is used to jump to any location in the memory This instruction requires three bytes two to specify the 16 bit address with the low order address byte first followed by the high order address byte For example an unconditional jump to memory location 3E3 2H is Address A C3 Op Code A 1 32 Low Order Address A 2 3E High Order Address The relative jump instruction uses only two bytes the second byte is a signed two s complement displacement from the existing PC This displacement can be in the range of 129 to 126 and is measured from the address of the instruction Op Code UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual Z Z
117. er is 2002H and the contents of the Program Counter is 18B5H pointing to the address of the next program Op Code to be fetched UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 261 RET cc If cc true PCL lt sp pCH lt sp 1 RET cc 1 1 cc 0 0 0 If condition cc is true the byte at the memory location specified by the contents of the Stack Pointer SP register pair is moved to the low order eight bits of the Program Counter PC The SP is incremented and the byte at the memory location specified by the new contents of the SP are moved to the high order eight bits of the PC The SP is incremented again The next Op Code following this instruction is fetched from the memory location specified by the PC This instruction is normally used to return to the main line program at the completion of a routine entered by a CALL instruction If condition cc is false the PC is simply incremented as usual and the program continues with the next sequential instruction Condition cc is programmed as one of eight status that correspond to condition bits in the Flag Register register F These eight status are defined in the table below which also specifies the corresponding cc bit fields in the assembled object code UM008004 1204 Z80 Instruction Set 262 Example Z80 CPU User s Manual ZiLOG cc Condition 000 NZ
118. eresdi adeesseriseneseeanen nnd 4 Addressing Modes 2 24 4 eiseabe oe bavi bees baudineenas 44 Instruction Op Codes c2 t229 42 ounce eunegheadaaeusaae dt 48 Z80 Instruction Set 6 568i 066i esa wid da eews esis 75 Z80 Assembly Language 0 00 cee eee ee eee 75 Z80 Status Indicator Flags 0 0 eee eee 76 Add Subtract Flag 24 ou 655 wandah on 55 uke Saath ened ees 71 Z80 Instruction Description 0 0 eee eee eee 80 8 Bit Load Groupe 49 05 254 55 ee oO eae ES ES Se PEE REO 81 16 Bit Load Group 2 222405 o2 asaeebess ade adeteeaea ns 102 Exchange Block Transfer and Search Group 122 o Bit Arithmetic Group 254 45u4e0sieoncees ce dueenseues 140 General Purpose Arithmetic and CPU Control Groups 166 16 Bit Arithmetic Group 20002 e cece eee eee 179 Rotate and Shift Group 0 0 0c eee eee eee 190 Bit Set Reset and Test Group 2 226 205 008seeec asada es 224 JUMP OUP foe she sae G ee ode boe eka E ends Sees 238 Call And Return Group 2 0 4 42c00802 seers ber eoeeavens ee 255 Input and Output Group 0 eee ee eee 269 Table of Contents UM008004 1204 List of Instructions ADCA S sd0c sae iden ste cdaw ak ADC HL ISS opinia a econ de ADD A HL ADD A IX d ADD A IY d ADD A fh eice cited awn ca cae es ADDA Liro 250 5 rinane eae ADD HL 8S5 rers ded die reski BIT HE eor gs eror a ces BIT b IX d BIT b I
119. escription The top two bytes of the external memory LIFO last in first out Stack are popped to register pair qq The Stack Pointer SP register pair holds the 16 bit address of the current top of the Stack This instruction first loads to the low order portion of qq the byte at memory location corresponding to the contents of SP then SP is incriminated and the contents of the corresponding adjacent memory location are loaded to the high order portion of qq and the SP is now incriminated again The operand qq identifies register pair BC DE HL or AF assembled as follows in the object code Pair r BC 00 DE o1 HL 10 AF 11 M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the Stack Pointer contains 1000H memory location 1000H contains 55H and location 1001H contains 33H the instruction POP HL results in register pair HL containing 3355H and the Stack Pointer containing 1002H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 120 ZiLOG POP IX Operation IXH lt SP 1 IXL lt SP Op Code POP Operands IX 1 1 0 1 14 14 0 41 DD 1 4 41 0f f0 o o 14 Et Description The top two bytes of the external memory LIFO last in first out Stack are popped to Index Register IX The Stack Pointer SP register pair holds the 16 bit address of the current top of the Stack This instruction first loads to the low order portion of IX
120. etic or logical operations are only eight bits which results in better memory utilization than is achieved with fixed instruction sizes such as 16 bits UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG Table 2 8 Bit Load Group LD Source Implied Register Reg Indirect 11indexed Ext Addr Imme Destination I R DE IX d 1Y d Inn n Register A ED ED 1A FD DD 57 5F TE TE d d B DD FD 46 46 d d C DD FD 4E 4E d d D DD FD 56 56 d d E DD FD SE SE d d H DD FD 66 66 d d L DD FD 6E 6E d d Reg HL Indirect BC DE INDEXED IX d DD 36 d n ITY d FD 77 70 71 72 733 74 75 36 d d jd jd d d jd d n EXT nn ADDR IMPLIED JI ED 47 R ED 4F UM008004 1204 Z80 CPU Instruction Description 51 52 Z80 CPU User s Manual Z ZiLOG All load instructions using indexed addressing for either the source or destination location actually use three bytes of memory with the third byte being the displacement d For example a load register E with the operand pointed to by IX with an offset of 8 is written LID E IX 8 The instruction sequence for this in memory is Address A DD Op Code A 1 5E ag Displacement A 2 oe Operand The two extended addressing instructions are also three byte
121. eyed implicitly or otherwise by this document under any intellectual property rights UM008004 1204 Z80 CPU User s Manual ziLoG iii Revision History Each instance in Table 1 reflects a change to this document from its previous revision To see more detail click the appropriate link in the table Table 1 Revision History of this Document Revision Date Level Section Description Page December 04 Z80 Instruction Corrected discrepancies in the bit 176 177 2004 Set patterns for IM 0 IM 1 and IM 2 178 instructions Chapter Title UM008004 1204 Z80 CPU User s Manual IV ZiLoG UM008004 1204 PRELIMINARY DRAFT v1 0 Chapter Title Z80 CPU User s Manual Table of Contents Revision History 666s 86629 e 86S AERA REAR E RIE OS iii Overview srcssicscnics esos Rete aE E eee 1 ATCMMSCIUES 2x bod oveeds aa e sow ender e E e e E A 1 CPU Registers 26 22 hesesieeatasessd eas besadeie rebk seuss 2 Arithmetic Logic Unit ALU 0 0 02 e eee 5 Instruction Register and CPU Control 04 6 Pin Description sssuseuanaan enearo 6 OVErvVieW cerent erroe smia AEREE E A E E 6 Pin FUNCION Se serenon eeracp oreren pie unaa E E Eana 7 TIMME 2e450 eneesdecb Serene enata np a a En enia ea a 11 OVETVIEW apsu cin aE E REN E Ge od eo DS E E E Se oS 11 Instr ction Fetch oes srs anssen tu saas aiaa E dob TA ES 12 Memory Read Or Write 2 429422 5245s dedeadevete Se ays 13 Input or Output Cycles 2 s4
122. fected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is data from bit 7 of source register If the contents of the Index Register IX are 1000H and the contents of memory location 1022H are UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 199 7 6 5 4 3 2 1 0 1 0100 1 0 00 at execution of RLC IX 2H the contents of memory location 1002H and the Carry flag are UM008004 1204 Z80 Instruction Set 200 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description RLC IY d CY lt a 7 4 0 m IY d RLC 1Y d 4 Pa ae fs ae ED 1 1 o of1 0of 1 1 0B a d gt 010 0 0J0 111 0 06 The contents of the memory address specified by the sum of the contents of the Index Register IY and a two s complement displacement integer d are rotated left 1 bit position The content of bit 7 is copied to the Carry flag and also to bit 0 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if pari
123. gister contains 1 and bit 2 in register B remains 0 Bit 0 in register B is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 226 ZiLOG BIT b HL Operation Z lt HL b Op Code BIT Operands b HL 1 1 0 0 1 0 414 1 CB 0 1 b 1 1 0 Description This instruction tests bit b in the memory location specified by the contents of the HL register pair and sets the Z flag accordingly Operand b is specified as follows in the assembled object code Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 1 111 M Cycles T States 4 MHZ E T 3 12 4 4 4 4 3 00 Condition Bits Affected S is unknown Z is set if specified Bit is 0 reset otherwise H is set P V is unknown H is reset C is not affected UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual zitoa 227 Example If the HL register pair contains 4444H and bit 4 in the memory location 4444 contains 1 at execution of BIT 4 HL the Z flag in the F register contains 0 and bit 4 in memory location 4444H still contains 1 Bit O in memory location 4444H is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 228 ZiLOG Operation Z lt IX d b Op Code BIT Operands b IX d BIT b IX d 1 110 1 1 0 1 1 0 1 0 1 a 0 1 a gt 1 1 DD CB Descrip
124. gisters Signals Address Control i 16 Bit 5V GND CLK Address Bus Figure 1 Z80 CPU Block Diagram CPU Registers The Z80 CPU contains 208 bits of R W memory that are available to the programmer Figure 2 illustrates how this memory is configured to eighteen 8 bit registers and four 16 bit registers All Z80 registers are implemented using static RAM The registers include two sets of six general purpose registers that may be used individually as 8 bit registers or in pairs as 16 bit registers There are also two sets of accumulator and flag registers and six special purpose registers UM008004 1204 Overview Z80 CPU User s Manual ZiLOG 3 Main Register Set Alternate Register Set Accumulator Flags Accumulator Flags A F A F B c B B General D E D E gt Purpose H L H L Registers Interrupt Vector Memory Refresh l R Index Register IX Special Purpose Index Register IY Registers Stack Pointer SP Program Counter PC Figure 2 Z80 CPU Register Configuration Special Purpose Registers Program Counter PC The program counter holds the 16 bit address of the current instruction being fetched from memory The PC is automatically incremented after its contents have been transferred to the address lines When a program jump occurs the new value is automatically placed in the PC overriding the incrementer Stack Pointer SP The stack pointer holds the
125. he contents of this address is then added to the contents of the Accumulator and the result is stored in the Accumulator M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if overflow reset otherwise N is reset C is set if carry from bit 7 reset otherwise If the Accumulator contents are 11H the Index Register IX contains 1000H and if the contents of memory location 1005H is 22H at execution of ADD A IX 5H the contents of the Accumulator are 33H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 145 ADD A IY d A amp A ID d ADD A IY d 1 a 4 4 4 4 o0 4 FD 1 0 0 0 4 0 1 1 0 86 a d gt The contents of the Index Register register pair IY is added to a two s complement displacement d to point to an address in memory The contents of this address is then added to the contents of the Accumulator and the result is stored in the Accumulator M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is
126. he contents of the Program Counter are 15B3H at execution of RST 18H Object code 1101111 the PC contains 0018H as the address of the next Op Code fetched UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 269 Input and Output Group IN A n Operation A lt n Op Code IN Operands A n 111 0 1 1 0 1 1 DB a n gt Description The operand n is placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports The contents of the Accumulator also appear on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the Accumulator register A in the CPU M Cycles T States 4 MHz LT 3 11 4 3 4 2 75 Condition Bits Affected None Example If the contents of the Accumulator are 23H and byte 7BH is available at the peripheral device mapped to I O port address 01H At execution of INA 01H the Accumulator contains 7BH UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 270 ZiLOG IN r C Operation r lt C Op Code IN Operands r C 1 41 14 0 14 1 0 1 EB O 1 me r 0 0 0 Description The contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports The contents of Regi
127. he interrupt routine was entered Before doing the RETI instruction the enable interrupt instruction EI should be executed to allow recognition of interrupts after completion of the current service routine M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example Given Two interrupting devices with A and B connected in a daisy chain configuration and A having a higher priority than B A B io IEI IEO ____ IE IEO m UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 264 ZiLOG B generates an interrupt and is acknowledged The interrupt enable out IEO of B goes Low blocking any lower priority devices from interrupting while B is being serviced Then A gen erates an interrupt suspending service of B The IEO of A goes Low indicating that a higher priority device is being serviced The A routine is completed and a RETI is issued resetting the IEO of A allowing the B routine to continue A second RETI is issued on completion of the B routine and the IEO of B is reset high allowing lower priority devices interrupt access UM008004 1204 Z80 Instruction Set Operation Op Code Description Z80 CPU User s Manual ZiLOG 265 RETN Return from non maskable interrupt RETN 1 1 1 0 14 14 0 14 ED 0 1 0 0 0 1 01 45 This instruction is used at the end of a non maskable interrupts serv
128. iLOG 65 Three types of register indirect jumps are also included These instructions are implemented by loading the register pair HL or one of the index registers 1X or IY directly into the PC This feature allows for program jumps to be a function of previous calculations A call is a special form of a jump where the address of the byte following the call instruction is pushed onto the stack before the jump is made A return instruction is the reverse of a call because the data on the top of the stack is popped directly into the PC to form a jump address The call and return instructions allow for simple subroutine and interrupt handling Two special return instruction are included in the Z80 family of components The return from interrupt instruction RETI and the return from nonmaskable interrupt RETN are treated in the CPU as an unconditional return identical to the Op Code c9H The difference is that RETI can be used at the end of an interrupt routine and all Z80 peripheral chips recognize the execution of this instruction for proper control of nested priority interrupt handling This instruction coupled with the Z80 peripheral devices implementation simplifies the normal return from nested interrupt Without this feature the following software sequence is necessary to inform the interrupting device that the interrupt routine is completed Disable Interrupt Prevent interrupt before routine is exited LDA n Notify peripheral that servic
129. ic state depending on the operation performed For arithmetic operations this flag indicates an Overflow condition when the result in the Accumulator is greater than the maximum possible number UM008004 1204 Z80 Instruction Set 78 Z80 CPU User s Manual Z ZiLOG 127 or is less than the minimum possible number 128 This Overflow condition is determined by examining the sign bits of the operands For addition operands with different signs never cause Overflow When adding operands with like signs and the result has a different sign the Overflow Flag is set for example 120 0111 1000 ADDEND 105 0110 1001 AUGEND 225 1110 0001 95 SUM The two numbers added together resulted in a number that exceeds 127 and the two positive operands have resulted in a negative number 95 which is incorrect The Overflow Flag is therefore set For subtraction Overflow can occur for operands of unlike signs Operands of like signs never cause Overflow For example 127 0111 1111 MINUEND 64 1100 0000 SUBTRAHEND 191 1011 1111 DIFFERENCE The minuend sign has changed from a Positive to a negative giving an incorrect difference Overflow is set Another method for identifying an Overflow is to observe the Carry to and out of the sign bit If there is a Carry in and no Carry out or if there is no Carry in and a Carry out then Overflow has occurred This flag is also used with logical operations an
130. ice routine to restore the contents of the Program Counter PC analogous to the RET instruction The state of IFF2 is copied back to IFF1 so that maskable interrupts are enabled immediately following the RETN if they were enabled before the nonmaskable interrupt M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example If the contents of the Stack Pointer are 1000H and the contents of the Program Counter are 1A45H when a non maskable interrupt NMJ signal is received the CPU ignores the next instruction and instead restarts to memory address 0066H The current Program Counter contents of 1445H is pushed onto the external stack address of OF FFH and OFFEH high order byte first and 0066H is loaded onto the Program Counter That address begins an interrupt service routine that ends with a RETN instruction Upon the execution of RETN the former Program Counter contents are popped off the external memory stack low order first resulting in a Stack Pointer contents again of 1000H The program flow continues where it left off with an Op Code fetch to address 1445H order byte first and 0066H is loaded onto the Program Counter That address begins an interrupt service routine that ends with a RETN instruction At execution of RETN the former Program Counter contents are popped off the external memory stack low order first resulting in a Stack Pointer contents again of UM008004 1204 Z80 Instruction Set
131. ing of the flag register making additional operations unnecessary to determine the state of the input data The parity state is one example The Z80 CPU includes single instructions that can move blocks of data up to 256 bytes automatically to or from any I O port directly to any memory location In conjunction with the dual set of general purpose registers these instructions provide fast I O block transfer rates The power of this I O instruction set is demonstrated by the Z80 CPU providing all required floppy disk formatting on double density floppy disk drives on an interrupt driven basis For example the CPU provides the preamble address data and enables the CRC codes Finally the basic CPU control instructions allow various options and modes This group includes instructions such as setting or resetting the interrupt enable flip flop or setting the mode of interrupt response UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual 44 ZiLOG Addressing Modes Most of the Z80 instructions operate on data stored in internal CPU registers external memory or in the I O ports Addressing refers to how the address of this data is generated in each instruction This section is a brief summary of the types of addressing used in the Z80 while subsequent sections detail the type of addressing available for each instruction group Immediate In this mode of addressing the byte following the Op Code in memory contains
132. instruction The two bytes of address nn are used as a pointer to a memory location The use of the parentheses always means that the value enclosed within them is used as a pointer to a memory location For example 3200 refers to the contents of memory at location 1200 Indexed Addressing In this type of addressing the byte of data following the Op Code contains a displacement that is added to one of the two index registers the Op Code specifies which index register is used to form a pointer to memory The contents of the index register are not altered by this operation Op Code m gt Two Byte Op Code Op Code Displacement Operand added to index register to form a pointer to memory An example of an indexed instruction is to load the contents of the memory location Index Register Displacement into the accumulator UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 47 The displacement is a signed two s complement number Indexed addressing greatly simplifies programs using tables of data because the index register can point to the start of any table Two index registers are provided because very often operations require two or more tables Indexed addressing also allows for relocatable code The two index registers in the Z80 are referred to as IX and IY To indicate indexed addressing the notation use IX d or IY d Here d is the displacement specified after the Op Cod
133. instruction first decrements SP and loads the high order byte of register pair qq to the memory address specified by the SP The SP is decremented again and loads the low order byte of qq to the memory location corresponding to this new address in the SP The operand qq identifies register pair BC DE HL or AF assembled as follows in the object code Pair qq BC 00 DE 01 HL 10 AF 11 M Cycles T States 4 MHz E T 3 11 5 3 3 2 75 Condition Bits Affected None Example If the AF register pair contains 2233H and the Stack Pointer contains 1007H at instruction PUSH AF memory address 1006H contains 22H memory address 1005H contains 33H and the Stack Pointer contains 1005H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 117 PUSH IX SP 2 IXL SP 1 lt IXH PUSH IX 1 1 0 1 1 1 0 1 DD 1 14 4 0 0 1 0 1 65 The contents of the Index Register IX are pushed to the external memory LIFO last in first out Stack The Stack Pointer SP register pair holds the 16 bit address of the current top of the Stack This instruction first decrements SP and loads the high order byte of IX to the memory address specified by SP then decrements SP again and loads the low order byte to the memory location corresponding to this new address in SP M Cycles T States 4 MHz E T 4 15 4 5 3 3 3 75 Condition Bits Affec
134. ion Set Z80 CPU User s Manual ZiLOG 179 16 Bit Arithmetic Group ADD HL ss Operation HL lt HL ss Op Code ADD Operands HL ss 0 0 s s 1 0 0 1 Description The contents of register pair ss any of register pairs BC DE HL or SP are added to the contents of register pair HL and the result is stored in HL Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 3 11 4 4 3 2 75 Condition Bits Affected S is not affected Z is not affected H is set if carry out of bit 11 reset otherwise P V is not affected N is reset C is set if carry from bit 15 reset otherwise Example If register pair HL contains the integer 4242H and register pair DE contains 1111H at execution of ADD HL DE the HL register pair contains 5353H UM008004 1204 Z80 Instruction Set 180 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description ADC HL ss HL HL ss CY ADC HL ss The contents of register pair ss any of register pairs BC DE HL or SP are added with the Carry flag C flag in the F register to the contents of register pair HL and the result is stored in HL Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 4 15 4 4 4 3
135. ious example in Figure 1 The memory space is assumed to be organized as follows Address 0000H 03FFH 0400H 04FFFH In this diagram the address space is described in hexadecimal notation Address bit A10 separates the ROM space from the RAM space allowing this address to be used for the chip select function For larger amounts of external ROM or RAM a simple TTL decoder is required to form the chip selects Address Bus Data Bus Figure 2 ROM and RAM Implementation UM008004 1204 Hardware and Software Implementation Examples Z80 CPU User s Manual 30 ZiLOG Memory Speed Control Slow memories can reduce costs for many applications The WAIT line on the CPU allows the Z80 to operate with any speed memory Memory access time requirements which are covered in Chapter A3 are most severe during the M1 cycle instruction fetch All other memory access cycles complete in an additional one half clock cycle Hence it is sometimes appropriate to add one wait state to the M1 cycle so slower memories can be used Figure 3 is an example of a simple circuit that accomplishes this objective This circuit can be changed to add a single wait state to any memory access as indicated in Figure 4 WAIT 5V Mn gt Te Tw Ts Ta C S ani a en ne en ee en O S AEA fhe df or CK ff ip U PLP uy D Q D Qr 7474 mt C Q R Eo j WAIT 5V Figure 3 Adding
136. iption The s operand is subtracted from the contents of the Accumulator and the result is stored in the Accumulator Instruction M Cycle T States 4 MHz E T SUB r 1 4 1 00 SUB n 2 7 4 3 1 75 SUB HL 2 7 4 3 1 75 SUB IX d 5 19 4 4 3 5 3 4 75 SUB 1Y d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise His set if borrow from bit 4 reset otherwise P V is set if overflow reset otherwise N is set C is set if borrow reset otherwise Example If the Accumulator contents are 29H and register D contains 11H at execution of SUB D the Accumulator contains 18H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 150 ZiLOG SBC A s Operation A lt A s CY Op Code SBC Operands A s The s operand is any of r n HL X d or 1Y d as defined for the analogous ADD instructions These possible Op Code operand combinations are assembled as follows in the object code SBC A r 1 0 0 1 1 a r gt SBC A n 1 1 0 1 1 1 1 0 DE SBC A HL 1 0 0 1 41444144 04 9E SBC A IX d 1 Ge a Ae oe 4 BB SBC A IY d 1 4 4 4 144 47 0 4 14 4 FD UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 151 r identifies registers B C D E H L or A assembled as follows in the objec
137. it b Register r 0 000 B 000 1 001 C 001 2 010 D 010 3 011 E 011 4 100 H 100 5 101 L 101 6 110 A 111 7 iri Description Bit b in operand m is reset Instruction M Cycles T States 4 MHz E T RES r 4 8 4 4 2 00 RES HL 4 15 4 4 4 3 3 75 RES IX d 6 23 4 4 3 5 4 3 5 75 RES lY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected None Example At execution of RES 6 D bit 6 in register 0 resets Bit 0 in register D is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 238 ZiLOG Jump Group JP nn Operation PC lt nn Op Code JP Operands nn a n aa mat n Note The first operand in this assembled object code is the low order byte of a two byte address Description Operand nn is loaded to register pair PC Program Counter The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHZ E T 3 10 4 3 3 2 50 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Operation IF cc true PC lt nn JP cc nn Op Code JP Operands cc nn 1 00 0 1 0 Ts n el a n aa Z80 CPU User s Manual ZiLOG 239 The first n operand in this assembled object code is the low order byte of a 2 byte memory address Description If condition cc is true the instruc
138. ity flag contains a 0 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 99 LD A R Operation A lt R Op Code LD Operands A R 111 110 1 11 0 1 ED o 1fo 4a a 4 fa oF Description The contents of Memory Refresh Register R are loaded to the Accumulator M Cycles T States MHz E T 2 9 4 5 2 25 Condition Bits Affected S is set if R Register is negative reset otherwise Z is set if R Register is zero reset otherwise H is reset P V contains contents of IFF2 N is reset C is not affected If an interrupt occurs during execution of this instruction the parity flag contains a 0 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 100 ZiLoOG Operation I lt A Op Code LD Operands I A LD I A 1 1 1 0 1 0 0 1 0 0 1 1 1 ED 47 Description The contents of the Accumulator are loaded to the Interrupt Control Vector Register I Condition Bits Affected None UM008004 1204 M Cycles T States 9 4 5 MHZz E T 2 25 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 101 LD R A Operation R lt A Op Code LD Operands R A 1 41 1 1 1 0 1 0 1 0 0 1 1 1 1 4F Description The contents of the Accumulator are loaded to the Memory Refresh register R M Cycles T States MHz E T 2 9 4 5 2 25 C
139. le items are distinguished from general text by the use of the Courier font This convention is not used within tables For example The STP bit in the CNTR register must be 1 Where the use of the font is not possible as in the Index the name of the entity is presented in upper case Hexadecimal Values Designated by H Hexadecimal values are designated by a uppercase H and appear in the Courier typeface For example STAT is set to F8H Use of All Uppercase Letters The use of all uppercase letters designates the names of states and commands For example The receiver can force the SCL line to Low to force the transmitter into a WAIT state The bus is considered BUSY after the Start condition A START command triggers the processing of the initialization sequence Use of Initial Uppercase Letters Initial uppercase letters designate settings modes and conditions in general text For example The Slave receiver leaves the data line High In Transmit mode the byte is sent most significant bit first The Master can generate a Stop condition to abort the transfer Manual Objectives UM008004 1204 User s Manual Z80 CPU xxii ZiLOG Register Access Abbreviations Register access is designated by the following abbreviations Designation Description R Read Only R W Read Write W Write Only Unspecified or indeterminate Trademarks Z80 Z180 Z380 and Z80382 are trademarks of ZiLOG Inc UM008004 1204 Manual Objectives Z80 CPU
140. n1111 0011 F3H Operand 0000 0111 07H Result to Accumulatoro000 0011 03H The Add instruction ADD performs a binary add between the data in the source location and the data in the accumulator The Subtract SUB performs a binary subtraction When the Add with Carry is specified ADC or the Subtract with Carry SBC then the Carry flag is also added or subtracted respectively The flags and decimal adjust instruction DAA in the Z80 allow arithmetic operations for e Miultiprecision packed BCD numbers e Miultiprecision signed or unsigned binary numbers e Miultiprecision two s complement signed numbers Other instructions in this group are logical and AND logical or OR exclusive or XOR and compare CP UM008004 1204 Z80 CPU Instruction Description 60 Z80 CPU User s Manual ZiLOG Five general purpose arithmetic instructions operate on the accumulator or carry flag These five are listed in Table 8 The decimal adjust instruction can adjust for subtraction as well as addition making BCD arithmetic operations simple Note that to allow for this operation the flag N is used This flag is set if the last arithmetic operation was a subtract The negate accumulator NEG instruction forms the two s complement of the number in the accumulator Finally notice that a reset carry instruction is not included in the Z80 because this operation can be easily achieved through other instructions such as a logical AND of the
141. nds r 111 0 0 1 0 1 1 B 0 0 0 0J O pe a Description The contents of register r are rotated left 1 bit position The content of bit 7 is copied to the Carry flag and also to bit 0 Operand r is specified as follows in the assembled object code Register r B 000 C 001 D 010 E oii H 100 L 101 A 111 M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity even reset otherwise N is reset C is data from bit 7 of source register UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 195 Example If the contents of register r are 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 at execution of RLC r the contents of register r and the Carry flag are C 7 6 5 4 3 2 1 0 1 0 0 0 4 0 0 0 4 1 UM008004 1204 Z80 Instruction Set 196 Z80 CPU User s Manual ZiLOG RLC HL Operation CY a 7 a 0 a HL Op Code RLC Operands HL 1111 10 0 1 0 1 1 CB 00 0 0J0 111 o 06 Description The contents of the memory address specified by the contents of register pair HL are rotated left 1 bit position The content of bit 7 is copied to the Carry flag and also to bit 0 Bit
142. ne Example If the Index Register IY contains the number 25AFH the instruction LD B IY 19H causes the calculation of the sum 25AFH 19H which points to memory location 25C8H If this address contains byte 39H the instruction results in register B also containing 39H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 86 ZiLOG LD HL r Operation HL lt r Op Code LD Operands HL r fo s i oh r x Description The contents of register r are loaded to the memory location specified by the contents of the HL register pair The symbol r identifies register A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the contents of register pair HL specifies memory location 2146H and the B register contains byte 29H at execution of LD HL B memory address 2146H also contains 29H UM008004 1204 Z80 Instruction Set Operation IX d lt r Op Code LD Operands IX d r LD IX d r 1 1 0 p a p Z80 CPU User s Manual ZiLOG 87 DD Description The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d a two s complement displacement integer The symbol r identifies register A
143. ne of the flag bits and the HL register pair is then incremented and the byte counter register pair BC is decremented The instruction CPIR is merely an extension of the CP1 instruction in which the compare is repeated until either a match is found or the byte counter register pair BC becomes zero Thus this single instruction can search the entire memory for any 8 bit character The CPD Compare and Decrement and CPDR Compare Decrement and Repeat are similar instructions their only difference is that they decrement HL after every compare so that they search the memory in the opposite direction The search is started at the highest location in the memory block These block transfer and compare instructions are extremely powerful in string manipulation applications UM008004 1204 Z80 CPU Instruction Description 58 Z80 CPU User s Manual Z ZiLOG Table 5 Block Transfer Group Destination Source Reg Indir DE Reg Indir AL ED LDI Load DE gt HL AO Inc HL and DE Dec BC ED LDIR Load DE gt HL BO Inc HL and DE Dec BC Repeat until BC 0 ED LDD Load DE gt HL A8 Inc HL and DE Dec BC ED LDDR Load DE gt HL B8 Dec HL and DE Dec BC Repeat until BC 0 Table 6 Block Search Group Search Location Reg Indir HL Note Reg HL points to source Reg DE points to destination Reg BC is byte counter ED Al CPI
144. ned for the analogous RLC instructions These possible Op Code operand combinations are specified as follows in the assembled object code UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 218 ZiLOG SRL r 1 1 0 0 1 0 1 1 CB SRL HL 1 1 0 0 1 0 1 1 CB SRL IX d 111lo 1 1 1 0 1 DD SRL IY d 1 1 1 1 il 1 0 1 FD 0 01 1 1 111 0 3E r identifies registers B C D E H L or A assembled as follows in the object code field above Description The contents of operand m are shifted right 1 bit position The content of bit 0 is copied to the Carry flag and bit 7 is reset Bit 0 is the least significant bit Instruction M Cycles T States 4 MHz E T SRLr 2 8 4 4 2 00 SRL HL 4 15 4 4 4 3 3 75 SRL 1X d 6 23 4 4 3 5 4 3 5 75 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 219 SRL 1Y d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected Example S is reset Z is set if result is zero reset otherwise H is reset P V is set if parity is even reset otherwise N is reset C is data from bit 0 of source register If the contents of register B are 7 6 5 4 3 2 1 0 1 0100 1 111 1 at execution of SRL B the contents of register B and the Carry flag are 7 6 5 4 3 2 1 0 C
145. ng and comparing has been added The notation for indicating register indirect addressing is to put parentheses around the name of the register that is to be used as the pointer For example the symbol HL specifies that the contents of the HL register are to be used as a pointer to a memory location Often register indirect addressing is used to specify 16 bit operands In this case the register contents point to the lower order portion of the operand while the register contents are automatically incremented to obtain the upper portion of the operand Bit Addressing The Z80 contains a large number of bit set reset and test instructions These instructions allow any memory location or CPU register to be specified for a bit operation through one of three previous addressing modes register register indirect and indexed while three bits in the Op Code specify which of the eight bits is to be manipulated Addressing Mode Combinations Many instructions include more than one operand such as arithmetic instructions or loads In these cases two types of addressing may be employed For example load can use immediate addressing to specify the source and register indirect or indexed addressing to specify the destination Instruction Op Codes This section describes each of the Z80 instructions and provides tables listing the Op Codes for every instruction In each of these tables the Op Codes in shaded areas are identical to those offered
146. ng Example Instruction Fetch Figure 5 depicts the timing during an M1 opcode fetch cycle The PC is placed on the address bus at the beginning of the M1 cycle One half clock cycle later the MREQ signal goes active At this time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories The RD line also goes active to indicate that the memory read data should be enabled onto the CPU data bus The CPU samples the data from the memory on the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off the RD and MREQ signals Thus the data has already been sampled by the CPU before the RD signal becomes inactive Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories The CPU uses this time to decode and execute the fetched instruction so that no other operation could be performed at this time During T3 and T4 the lower seven bits of the address bus contain a memory refresh address and the RFSH signal becomes active tindicating that a refresh read of all dynamic memories must be accomplished An RD signal is not generated during refresh time to prevent data from different memory UM008004 1204 Overview CLK A15 Ao MREQ Z80 CPU User s Manual ZiLOG segments from being gated onto the data bus The MREQ signal during refresh time should be used to perform a r
147. non zero 001 Z zero 010 NC non carry 011 C carry 100 PO parity odd 101 PE parity even 110 P sign positive 111 M sign negative If cc is true M Cycles T States 3 11 5 3 3 If cc is false M Cycles T States 1 5 Condition Bits Affected None Relevant Flag Z Z C C P V P V S S 4 MHz E T 2 75 4 MHz E T 1 25 If the S flag in the F register is set the contents of the Program Counter are 3535H the contents of the Stack Pointer are 2000H the contents of memory location 2000H are B5H and the contents of memory location 2001H are 18H At execution of RET M the contents of the Stack Pointer is 2002H and the contents of the Program Counter is 18B5H pointing to the address of the next program Op Code to be fetched UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 263 RETI Operation Return from Interrupt Op Code RETI 1111 1 0 1 1 0f1 ED 01 0 0 1 1 0 1 4D Description This instruction is used at the end of a maskable interrupt service routine to Restore the contents of the Program Counter PC analogous to the RET instruction e Signal an I O device that the interrupt routine is completed The RETI instruction also facilitates the nesting of interrupts allowing higher priority devices to temporarily suspend service of lower priority service routines However this instruction does not enable interrupts that were disabled when t
148. ntents of the Accumulator In case of a true compare a condition bit is set The HL and Byte Counter register pair BC are decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if A equals HL reset otherwise H is set if borrow from bit 4 reset otherwise P V is set if BC 1 x 0 reset otherwise N is set C is not affected If the HL register pair contains 1111H memory location 1111H contains 3BH the Accumulator contains 3BH and the Byte Counter contains 0001H At execution of CPD the Byte Counter contains 0000H the HL register pair contains 1110H the flag in the F register sets and the P V flag in the F register resets There is no effect on the contents of the Accumulator or address 1111H UM008004 1204 Z80 Instruction Set 138 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description CPDR A HL HL lt HL 1 BC lt BC 1 CPDR 1 1 1 loj1il1lo 1 ED 1 0j 1 1 1 0 0 1 B9 The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator In case of a true compare a condition bit is set The HL and BC Byte Counter register pairs are decremented If decrementing causes the BC to go to zero or if A HL the instruction is terminated If BC is not zero and A HL the program
149. of the next highest memory address nn 1 are loaded to the high order portion of dd Register pair dd defines BC DE HL or SP register pairs assembled as follows in the object code Pair dd BC 00 DE 01 HL 10 SP 11 The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHZ E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If Address 2130H contains 65H and address 2131M contains 78H at instruction LD BC 2130H the BC register pair contains 7865H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 107 LD IX nn Operation IXh lt nn 1 IXI lt nn Op Code LD Operands TX nn 1 1 0 1 4441 0 14 DD 0 0 1 0 1 0 1 0 2A a n aai e n ai Description The contents of the address nn are loaded to the low order portion of Index Register IX and the contents of the next highest memory address nn 1 are loaded to the high order portion of IX The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If address 6666H contains 92H and address 6667H contains DAH at instruction LD IX 6666H the Index Register IX contains DA92H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 108 ZiLOG LD IY nn Operation IYh lt nn 1 TYI lt nn Op Cod
150. on between the CPU and the peripheral When the service routine is completed the CPU returns to the operation from which it was interrupted Interrupt Enable Disable The Z80 CPU has two interrupt inputs a software maskable interrupt INT and a non maskable interrupt NMI The non maskable interrupt cannot be disabled by the programmer and is accepted whenever a peripheral device requests it This interrupt is generally reserved for very important functions that can be enabled or disabled selectively by the programmer This routine allows the programmer to disable the interrupt during periods when his program has timing constraints that do not allow interrupt In the Z80 CPU there is an interrupt enable flip flop IFF that is set or reset by the programmer using the Enable Interrupt EI and Disable Interrupt DI instructions When the IFF is reset an interrupt cannot be accepted by the CPU The two enable flip flops are IFF1 and IFF2 IFF1 IFF2 Disables interrupts Temporary storage from being accepted location for IFF1 The state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage location for IFF1 UM008004 1204 Overview Z80 CPU User s Manual ZiLOG A CPU reset forces both the IFF1 and IFF2 to the reset state which disables interrupts Interrupts can be enabled at any time by an EI instruction from the programmer When an EI instruction is executed any pending interrupt
151. ondition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 102 ZiLOG 16 Bit Load Group LD dd nn Operation dd lt nn Op Code LD Operands dd nn o0ololdldajololo i Tn n lt a n gt Description The 2 byte integer nn is loaded to the dd register pair where dd defines the BC DE HL or SP register pairs assembled as follows in the object code Pair dd BC 00 DE 01 HL 10 SP 11 The first n operand after the Op Code is the low order byte M Cycles T States 4 MHz E T 2 10 4 3 3 2 50 Condition Bits Affected None Example At execution of LD HL 5000H the contents of the HL register pair is 5000H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 103 LD IX nn Operation Ix lt nn Op Code LD Operands IX nn a n a n ai Description Integer nn is loaded to the Index Register IX The first n operand after the Op Code is the low order byte M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example At instruction LD IX 45A2H the Index Register contains integer 45A2H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 104 ZiLOG LD IY nn Operation IY lt nn Op Code LD Operands IY nn Description Integer nn i
152. ontal row and the destination is specified in the left column For example load register C from register B uses the Op Code 48H In all the figures the Op Code is specified in hexadecimal notation and the 48H 0100 1000 binary code is fetched by the CPU from the external memory during M1 time decoded and then the register transfer is automatically performed by the CPU The assembly language mnemonic for this entire group is LD followed by the destination followed by the source LD DEST SOURCE Note that several combinations of addressing modes are possible For example the source may use register addressing and the destination may be register indirect such as load the memory location pointed to by register HL with the contents of register D The Op Code for this operation is 72 The mnemonic for this load instruction is LD HL D The parentheses around the HL indicates that the contents of HL are used as a pointer to a memory location In all Z80 load instruction mnemonics the destination is always listed first with the source following The Z80 assembly language is defined for ease of programming Every instruction is self documenting and programs written in Z80 language are easy to maintain In Table 2 some Op Codes that are available in the Z80 use two bytes This feature is an efficient method of memory utilization because 8 18 24 or 32 bit instructions are implemented in the Z80 Often utilized instructions such as arithm
153. otherwise N is reset C is not affected If the contents of the HL register pair are 3434H and the contents of address 3434H are 82H at execution of INC HL memory location 3434H contains 83H UM008004 1204 Z80 Instruction Set 162 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description INC IX d IX d lt IX d 1 INC IX d 1 1 0 1 4 14 0 1 DD 0 0 1 1 0 1 0 0 34 a d gt The contents of the Index Register IX register pair IX are added to a two s complement displacement integer d to point to an address in memory The contents of this address are then incremented M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected Example S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if carry from bit 3 reset otherwise P V is set if X d was 7FH before operation reset otherwise N is reset C is not affected If the contents of the Index Register pair IX are 2020H and the memory location 203 0H contains byte 34H at execution of INC IX 10H the contents of memory location 203 0H is 35H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 163 INC IY d Y d 1Y d 1 INC 1Y d 1 9 fe ae a g ae AD 0 0 1 1 0 1 0 0 34
154. ounter register pair are decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected Example S is not affected Z is not affected H is reset P V is set if BC 1 0 reset otherwise N is reset C is not affected If the HL register pair contains 1111H memory location 1111H contains byte 88H the DE register pair contains 2222H memory location 2222H contains byte 66H and the BC register pair contains 7H then instruction LDD results in the following contents in register pairs and memory addresses HL contains 1110H 1111H contains 88H DE contains 2221H 2222H contains 88H BC contains 6H UM008004 1204 Z80 Instruction Set 132 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description LDDR DE lt HL DE D lt 1 HL lt HL 1 BC lt BC 1 LDDR 1 1 1 0 1 1 0 1 ED 1 10 1 1 1 0 0 o B8 This 2 byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both of these registers as well as the BC Byte Counter are decremented If decrementing causes BC to go to zero the instruction is terminated If BC is not zero the program counter is decremented by two and the instruction is repeated Interrupts are recognized and two refresh cycles execute after each data transfer
155. peration r lt IX d Op Code LD Operands r X d LD r IX d 1 1 0 0 1 a a DD Description The operand IX d the contents of the Index Register IX summed with a two s complement displacement integer d is loaded to register r where r identifies register A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHZ E T 5 19 4 4 3 5 3 2 50 Condition Bits Affected None Example If the Index Register IX contains the number 25AFH the instruction LD B IX 19H causes the calculation of the sum 25AFH 19H which points to memory location 25C8H If this address contains byte 39H the instruction results in register B also containing 39H UM008004 1204 Z80 Instruction Set Operation r lt IY D Op Code LD Operands r lY d LD r IY d 1 1 0 1 a 0 a g Z80 CPU User s Manual ZiLOG 85 FD Description The operand 1Y d the contents of the Index Register IY summed with a two s complement displacement integer d is loaded to register r where r identifies register A B C D E H or L assembled as follows in the object code Register r A iti B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 15 Condition Bits Affected No
156. ple If the H register contains the number 8AH and the E register contains 10H the instruction LD H E results in both registers containing 10H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 82 ZiLOG LD r n Operation r lt n Op Code LD Operands r n 0o 0 e r 1 1 0 p Description The 8 bit integer n is loaded to any register r where r identifies register A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example At execution of LD E A5H the contents of register E are A5H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 83 LD r HL Operation r lt HL Op Code LD Operands r HL 0 1 r gt 1 1 0 Description The 8 bit contents of memory location HL are loaded to register r where r identifies register A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If register pair HL contains the number 75A1H and memory address 75A1H contains byte 58H the execution of LD C HL results in 58H in register C UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 84 ZiLOG O
157. pts are recognized and two refresh cycles are executed after each data transfer If BC is set to zero before instruction execution the instruction loops through 64 Kbytes if no match is found For BC 0 and A HL M cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 and A HL M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is set if result is negative reset otherwise Z is set if A equals HL reset otherwise H is set if borrow from bit 4 reset otherwise P V is set if BC 1 does not equal 0 reset otherwise N is set C is not affected UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual Z 136 ZiLOG Example If the HL register pair contains 1111H the Accumulator contains F3H the Byte Counter contains 0007H and memory locations have these contents 1111H contains 52H 1112H contains 00H 1113H contains F3H Then at execution of CPIR the contents of register pair HL is 1114H the contents of the Byte Counter is 0004H the P V flag in the F register sets and the Z flag in the F register sets UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 137 CPD A HL HL lt HL 1 BC lt BC 1 CPD 1 1 1 0 1 1 0 1 ED 1 0J 1 0 1 0 0 1 AY The contents of the memory location addressed by the HL register pair is compared with the co
158. r an indirect call can be made to any memory location In this mode the programmer maintains a table of 16 bit starting addresses for every interrupt service routine This table may be located anywhere in memory When an interrupt is accepted a 16 bit pointer must be formed to obtain the desired interrupt service routine starting address from the table The upper eight bits of this pointer is formed from the contents of the I register The I register must be loaded with the applicable value by the programmer such as LD I A A CPU reset clears the I register so that it is initialized to zero The lower eight bits of the pointer must be supplied by the interrupting device Only seven bits are required from the interrupting device because the least significant bit must be a zero This is required UM008004 1 204 Overview 26 Z80 CPU User s Manual Z ZiLOG because the pointer is used to get two adjacent bytes to form a complete 16 bit service routine starting address and the addresses must always start in even locations Starting Address Pointed to by Interrupt Service Routine Low Order I Register Seven Bits From 0 Starting High Order Contents Peripheral Address J Table Figure 16 Mode 2 Interrupt Response Mode The first byte in the table is the least significant low order portion of the address The programmer must complete this table with the correct addresses before any interrupts are
159. rectly by the Z80 CPU ZiLOG provides several assemblers that differ in the features offered Both absolute and relocatable assemblers are available with the Development and Micro computer Systems The absolute assembler is contained in base level software operating in a 16K memory space while the relocating assembler is part of the RIO environment operating in a 32K memory space UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 76 ZiLOG Z80 Status Indicator Flags The flag registers F and F supply information to the user about the status of the Z80 at any given time The bit positions for each flag is listed below X N X P V N C Symbol Field Name C Carry Flag N Add Subtract P V Parity Overflow Flag H Half Carry Flag Z Zero Flag S Sign Flag X Not Used Each of the two flag registers contains 6 bits of status information that are set or cleared by CPU operations Bits 3 and 5 are not used Four of these bits C P V Z and S may be tested for use with conditional JUMP CALL or RETURN instructions Two flags may not be tested H N and are used for BCD arithmetic Carry Flag The Carry Flag C is set or cleared depending on the operation performed For ADD instructions that generate a Carry and SUB instructions that generate a Borrow the Carry Flag sets The Carry Flag is reset by an ADD instruction that does not generate a Carry and by a SUB in
160. roller can maintain control of the bus for as many clock cycles as is required If very long DMA cycles are used and dynamic memories are used the external controller also performs the refresh function This situation only occurs if very large blocks of data UM008004 1 204 Overview Z80 CPU User s Manual 16 ZiLOG are transferred under DMA control During a bus request cycle the CPU cannot be interrupted by either an NMI or an INT signal Any M Cycle Bus Available Status A a CLK BUSREQ BUSACK A15 Ao D7 Do MREQ RD WR IORQ RFSH Figure 8 Bus Request Acknowledge Cycle Interrupt Request Acknowledge Cycle Figure 9 illustrates the timing associated with an interrupt cycle The CPU samples the interrupt signal INT with the rising edge of the last clock at the end of any instruction The signal is not accepted if the internal CPU software controlled interrupt enable flip flop is not set or if the BUSREQ signal is active When the signal is accepted a special M1 cycle is generated During this special M1 cycle the IORQ signal becomes active instead of the normal MREQ to indicate that the interrupting device can place an 8 bit vector on the data bus Two wait states are automatically added to this cycle These states are added so that a ripple priority interrupt scheme can be easily implemented The two wait states allow sufficient time for the ripple signals to stabilize and identify which T O device must inser
161. rovide both the testing of shift results and to link register register or register memory shift operations Examples of Specific Z80 Instructions Example One When a 737 byte data string in memory location DATA must be moved to location BUFFER the operation is programmed as follows LD HL DATA START ADDRESS OF DATA STRING LD DE BUFFER START ADDRESS OF TARGET BUFFER LD BC 737 LENGTH OF DATA STRING LDIR MOVE STRING TRANSFER MEMORY POINTED TO BY HL INTO MEMORY LOCATION POINTED TO BY DE INCREMENT HL AND DE DECREMENT BC PROCESS UNTIL BC 0 Eleven bytes are required for this operation and each byte of data is moved in 21 clock cycles UM008004 1 204 Hardware and Software Implementation Examples Z80 CPU User s Manual Z ZiLOG 35 Example Two A string in memory limited to a maximum length of 132 characters starting at location DATA is to be moved to another memory location starting at location BUFFER until an ASCH used as a string delimitor is found This operation is performed as follows LD HL DATA STARTING ADDRESS OF DATA STRING LD DE BUFFER STARTING ADDRESS OF TARGET BUFFER LD BC 132 MAXIMUM STRING LENGTH LD A US STRING DELIMITER CODE LOOP CP HL COMPARE MEMORY CONTENTS WITH DELIMITER JR Z END GO TO END IF CHARACTERS EQUAL LDI MOVE CHARACTER HL to DE INCREMENT HL AND DE DECREMENT BC JP PE LOOP GO TO LOOP IF MORE CHARACTERS END OTHERWISE FALL THROUGH NOTE P
162. rs the PC and registers I and R and sets the UM008004 1 204 Overview 10 Z80 CPU User s Manual ZiLOG interrupt status to Mode 0 During reset time the address and data bus go to a high impedance state and all control output signals go to the inactive state Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete RFSH Refresh output active Low RFSH together with MREQ indicates that the lower seven bits of the system s address bus can be used as a refresh address to the system s dynamic memories WAIT WAIT input active Low WAIT communicates to the CPU that the addressed memory or I O devices are not ready for a data transfer The CPU continues to enter a WAIT state as long as this signal is active Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory WR Write output active Low tristate WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I O location CLK Clock input Single phase MOS level clock UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG 11 TIMING Overview The Z80 CPU executes instructions by stepping through a precise set of basic operations These include e Memory Read or Write e I O Device Read or Write e Interrupt Acknowledge All instructions are series of basic operations Each of these operations can take from three to six
163. ructions fall into these major groups Load and Exchange Block Transfer and Search e Arithmetic and Logical Rotate and Shift e Bit Manipulation Set Reset Test Jump Call and Return Input Output e Basic CPU Control Instruction Types The load instructions move data internally among CPU registers or between CPU registers and external memory All these instructions specify a source location from which the data is to be moved and a destination location The source location is not altered by a load instruction Examples of load group instructions include moves between any of the general purpose registers such as move the data to register B from register C This group also includes load immediate to any CPU register or to any external memory location Other types of load instructions allow transfer between CPU registers and memory locations The exchange instructions can trade the contents of two registers UM008004 1204 Z80 CPU Instruction Description 42 Z80 CPU User s Manual Z ZiLOG A unique set of block transfer instructions is provided in the Z80 With a single instruction a block of memory of any size can be moved to any other location in memory This set of block moves is extremely valuable when processing large strings of data With a single instruction a block of external memory of any desired length can be searched for any 8 bit character When the character is found or the end of the block is reache
164. s 07H UM008004 1204 Z80 Instruction Set 286 Z80 CPU User s Manual ZiLOG Operation Op Code Description OTDR C HL B B 1 HL amp HL 1 OTDR 1 1 1 0 1 1 0 1 ED 1 o 14 4 4 0 f4 1 BB The contents of the HL register pair are placed on the address bus to select a location in memory The byte contained in this memory location is tempo rarily stored in the CPU Then after the byte counter B is decremented the contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Regis ter B may be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written to the selected peripheral device Then register pair HL is decremented and if the decremented B register is not zero the Program Counter PC is decremented by two and the instruction is repeated If B has gone to zero the instruction is termi nated Interrupts are recognized and two refresh cycles are executed after each data transfer Note When B is set to zero prior to instruction execution the instruc tion outputs 256 bytes of data IfB 0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 If B 0 M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 UM008004 1204 Z80 Instruction Set
165. s an external pull up for these applications UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG IORQ Input Output Request output active Low tristate IORQ indicates that the lower half of the address bus holds a valid I O address for an I O read or write operation IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus M1 Machine Cycle One output active Low MI together with MREQ indicates that the current machine cycle is the opcode fetch cycle of an instruction execution M1 together with IORQ indicates an interrupt acknowledge cycle MREQ Memory Request output active Low tristate MREQ indicates that the address bus holds a valid address for a memory read of memory write operation NMI Non Maskable Interrupt input negative edge triggered NMI has a higher priority than INT NMI is always recognized at the end of the current instruction independent of the status of the interrupt enable flip flop and automatically forces the CPU to restart at location 006 6H RD Read output active Low tristate RD indicates that the CPU wants to read data from memory or an I O device The addressed I O device or memory should use this signal to gate data onto the CPU data bus RESET Reset input active Low RESET initializes the CPU as follows it resets the interrupt enable flip flop clea
166. s loaded to the Index Register IY The first n operand after the Op Code is the low order byte M Cycles T States 4 MHZ E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example At instruction LD IY 7733H the Index Register IY contains the integer 7733H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 105 LD HL nn Operation H lt nn 1 L 4 nn Op Code LD Operands HL nn 0 o0 1 0 1 0 1 0 2A a n ai a n ai Description The contents of memory address nn are loaded to the low order portion of register pair HL register L and the contents of the next highest memory address nn 1 are loaded to the high order portion of HL register H The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 5 16 4 3 3 3 3 4 00 Condition Bits Affected None Example If address 4545H contains 37H and address 4546H contains A1H at instruction LD HL 4545H the HL register pair contains A137H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 106 ZiLOG LD dd nn Operation ddh lt nn 1 ddl lt nn Op Code LD Operands dd nn 1 4 14 0 14 440 1 ED 0 1 dji d 1 0 1 1 a n aa a n aa Description The contents of address nn are loaded to the low order portion of register pair dd and the contents
167. s of HL are 8887H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 182 ZiLOG Operation Op Code Operands Description ADD IX pp IX amp IX pp ADD IX pp 1 110 1 1 1 0 1J DD 0 O0Olplp 1il0 0 Ji The contents of register pair pp any of register pairs BC DE IX or SP are added to the contents of the Index Register IX and the results are stored in IX Operand pp is specified as follows in the assembled object code Register Pair pp BC 00 DE 01 IX 10 SP 11 M Cycles T States 4 MHZ E T 4 15 4 4 4 3 3 75 Condition Bits Affected Example S is not affected Z is not affected H is set if carry out of bit 11 reset otherwise P V is not affected N is reset C is set if carry from bit 15 reset otherwise If the contents of Index Register IX are 33 3H and the contents of register pair BC are 5555H at execution of ADD IX BC the contents of X are 8888H UM008004 1204 Z80 Instruction Set Operation Op Code Operands Description Z80 CPU User s Manual ZiLOG 183 ADD IY rr IY amp IY rr ADD IY rr The contents of register pair rr any of register pairs BC DE IY or SP are added to the contents of Index Register IY and the result is stored in IY Operand rr is specified as follows in the assembled object code Register Pair rr BC 00 DE 01 IY 10 SP 11 M Cycles T St
168. se N is reset C is not affected UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 223 Example If the contents of the HL register pair are 5000H and the contents of the Accumulator and memory location 5000H are 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 0 Accumulator 0 o0 1 0 0 0 0 0 Gooon at execution of RRD the contents of the Accumulator and memory location 5000H are 1 0 0 0 0 0 0 0 Accumulator o 1 0 0 0 0 1 o 5000 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 224 ZiLOG Bit Set Reset and Test Group BIT b r Operation Z lt rb Op Code BIT Operands b r Description This instruction tests bit b in register r and sets the Z flag accordingly Operands b and r are specified as follows in the assembled object code Bit Tested b Register r 0 000 B 000 1 001 C 001 2 010 D 010 3 011 E 011 4 100 H 100 5 101 L 101 6 110 A 111 7 111 M Cycles T States 4 MHz E T 2 8 4 4 4 50 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 225 Condition Bits Affected S is unknown Z is set if specified bit is 0 reset otherwise H is set P V is unknown N is reset C is not affected Example If bit 2 in register B contains 0 at execution of BIT 2 B the Z flag in the F re
169. set the program counter for the address of the next instruction The stack pointer is adjusted automatically to reflect the current top stack position during PUSH POP CALL and RET instructions This stack mechanism allows pushdown data stacks and subroutine calls to be nested to any practical depth because the stack area can potentially be as large as memory space The sequence of instruction execution can be controlled by six different flags carry zero sign parity overflow add subtract half carry which reflect the results of arithmetic logical shift and compare instructions UM008004 1204 Hardware and Software Implementation Examples 34 Z80 CPU User s Manual Z ZiLOG After the execution of an instruction that sets a flag that flag can be used to control a conditional jump or return instruction These instructions provide logical control following the manipulation of single bit 8 bit byte or 18 bit data quantities A full set of logical operations including AND OR XOR exclusive OR CPL NOR and NEG two s complement are available for Boolean opera tions between the accumulator and all other 8 bit registers memory loca tions or immediate operands In addition a full set of arithmetic and logical shifts in both directions are available which operate on the contents of all 8 bit primary registers or directly on any memory location The carry flag can be included or set by these shift instructions to p
170. ss bus to select the I O device at one of 256 possible ports The contents of Register B are placed on the top half A8 through A15 of the address bus at this time Then the byte contained in register r is placed on the data bus and written to the selected peripheral device Register r identifies any of the CPU registers shown in the following table which also shows the corresponding three bit r field for each that appears in the assembled object code Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 M Cycles T States 4 MHz E T 3 12 4 4 4 3 00 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 281 Example If the contents of register C are 01H and the contents of register D are 5AH at execution of OUT C D byte 5AH is written to the peripheral device mapped to I O port address 01H UM008004 1204 Z80 Instruction Set 282 Z80 CPU User s Manual ZiLOG Operation Op Code Description OUTI C HL B lt B 1 HL HL 1 OUTI ffl ste fia aN Na ae I af EB 1 Oj 1 0 0 0 1 1 A3 The contents of the HL register pair are placed on the address bus to select a location in memory The byte contained in this memory location is temporarily stored in the CPU Then after the byte counter B is decremented the contents of register C are placed on the bottom half AO through A7 of the address bus to sele
171. st significant bit Instruction M Cycles T States 4 MHz E T SLA r 2 8 4 4 2 00 SLA HL 4 15 4 4 4 3 3 75 SLA IX d 6 23 4 4 3 5 4 3 5 75 SLA IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is reset P V is set if parity is even reset otherwise N is reset C is data from bit 7 Example If the contents of register L are UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 213 at execution of SLA L the contents of register L and the Carry flag are UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 214 ZiLOG SRA m Operation 7 0 gt CY ie Op Code SRA Operands m The m operand is any of r HL X d or 1Y d as defined for the analogous PLC instructions These possible Op Code operand combinations are specified as follows in the assembled object code SRAr 1 1 0 0 14 0 14 1 CB 0 0J 1 0 0 ma rm gt SRA HL 1 1 0 0 1 0 414 1 CB SRA IX d 1 414 o0 14 14 4 0 14 0D SRA IY d 1 1 1 1 1 1 0 1 FD UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG
172. ster B are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to register r in the CPU Register r identifies any of the CPU registers shown in the following table which also indicates the corresponding 3 bit r field for each The flags are affected checking the input data Register r Flag 110 Undefined Op Code set the flag B 000 C 001 D 010 E 011 H 100 L 101 A 111 M Cycles T States 4 MHz E T 3 12 4 4 4 3 00 UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 271 Condition Bits Affected Example UM008004 1204 S is set if input data is negative reset otherwise Z is set if input data is zero reset otherwise H is reset P V is set if parity is even reset otherwise N is reset C is not affected If the contents of register C are 07H the contents of register B are 10H and byte 7BH is available at the peripheral device mapped to I O port address 07H After execution of IN D C register D contains 7BH Z80 Instruction Set 272 Z80 CPU User s Manual ZiLOG Operation Op Code Description INI HL amp C B B 1 HL e HL 1 INI 1 1 1 0 1 1 0 1 ED 1 10 1 0 0 0 1 0 A2 The contents of register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports
173. struction that does not generate a Borrow This saved Carry facilitates software routines UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 77 for extended precision arithmetic Also the DAA instruction sets the Carry Flag if the conditions for making the decimal adjustment are met For instructions RLA RRA RLS and RRS the Carry bit is used as a link between the least significant byte LSB and most significant byte MSB for any register or memory location During instructions RLCA RLC and SLA the Carry contains the last value shifted out of Bit 7 of any register or memory location During instructions RRCA RRC SRA and SRL the Carry contains the last value shifted out of Bit 0 of any register or memory location For the logical instructions AND OR and XOR the Carry is reset The Carry Flag can also be set by the Set Carry Flag SCF and complemented by the Compliment Carry Flag CCF instructions Add Subtract Flag The Add Subtract Flag N is used by the Decimal Adjust Accumulator instruction DAA to distinguish between ADD and SUB instructions For ADD instructions N is cleared to 0 For SUB instructions N is set to 1 Add Subtract Flag The Decimal Adjust Accumulator instruction DAA uses this flag to distinguish between ADD and SUBTRACT instructions For all ADD instructions N sets to 0 For all SUBTRACT instructions N sets to 1 Parity Overflow Flag P V This flag is set to a specif
174. t code field above Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The s operand along with the Carry flag C in the F register is subtracted from the contents of the Accumulator and the result is stored in the Accumulator Instruction M Cycles T States 4 MHz E T SBC A r 1 4 1 00 SBC A n 2 7 A 3 1 75 SBC A HL 2 7 A 3 1 75 SBC A IX d 5 19 4 4 3 5 3 4 75 SBC A 1Y d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative reset otherwise Z is set if result is zero reset otherwise H is set if borrow from bit 4 reset otherwise P V is reset if overflow reset otherwise N is set C is set if borrow reset otherwise Example If the Accumulator contains 16H the carry flag is set the HL register pair contains 3433H and address 3433H contains 05H at execution of SBC A HL the Accumulator contains 10H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 152 ZiLOG AND s Operation A lt Aas Op Code AND Operands s The s operand is any of r n HL X d or 1Y d as defined for the analogous ADD instructions These possible Op Code operand combinations are assembled as follows in the object code AND r 1 0J 1 0 O a r gt ANDn 1 14 14 0 0 41 4 0 E6 AND HL 1 0 1 50 0 1441 0 A6 AND IX d 1 1 0 1 1 1 0 1 DD AND IY d 1 4 44 4 44 4 0 4 14 4 FD
175. t one of 256 possible ports Register B may be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written to the selected peripheral device Then register pair HL is incremented If the decremented B register is not zero the Program Counter PC is decremented by two and the instruction is repeated If B has gone to zero the instruction is terminated Interrupts are recognized and two refresh cycles are executed after each data transfer Note When B is set to zero prior to instruction execution the instruc tion outputs 256 bytes of data If B 0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 If B 0 M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected UM008004 1204 Z80 Instruction Set 284 Z80 CPU User s Manual Z ZiLOG Example S is unknown Z is set H is unknown P V is unknown N is set C is not affected If the contents of register C are 07H the contents of register B are 03H the contents of the HL register pair are 1000H and memory locations have the following contents 1000H contains 51H 1001H contains A9H 1002H contains 03H then at execution of OTIR the HL register pair contains 1003H register B contains zero and a group of bytes is written to the peripheral device mapped to I O port address 07H in the following sequence 51H A9
176. t the response vector Refer to Chapter 6 for details on how the interrupt response vector is utilized by the CPU UM008004 1 204 Overview Z80 CPU User s Manual ZiLOG 17 Last M Cycle of Instruction M1 CLK NT 7 Ais Ao Figure 9 Interrupt Request Acknowledge Cycle Non Maskable Interrupt Response Figure 10 illustrates the request acknowledge cycle for the non maskable interrupt This signal is sampled at the same time as the interrupt line but this line takes priority over the normal interrupt and it can not be disabled under software control Its usual function is to provide immediate response to important signals such as an impending power failure The CPU response to a non maskable interrupt is similar to a normal memory read operation The only difference is that the content of the data bus is ignored while the processor automatically stores the PC in the external stack and jumps to location 0066H The service routine for the non maskable interrupt must begin at this location if this interrupt is used UM008004 1 204 Overview Z80 CPU User s Manual 18 ZiLOG Last M Cycle Figure 10 Non Maskable Interrupt Request Operation HALT Exit Whenever a software HALT instruction is executed the CPU executes NOPs until an interrupt is received either a non maskable or a maskable interrupt while the interrupt flip flop is enabled The two interrupt lines are sampled with the rising clock edge
177. te of a multi byte instruction is read during the interrupt acknowledge cycle Subsequent bytes are read in by a normal memory read sequence M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 177 IM 1 Operation Op Code IM Operands 1 1 14 4 o0 14 1 0 1 ED 0 1 041 0 11 0 56 Description The IM 1 instruction sets interrupt mode 1 In this mode the processor responds to an interrupt by executing a restart to location 0038H M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None UM008004 1204 Z80 Instruction Set 178 Z80 CPU User s Manual ZiLoG IM 2 Operation Op Code IM Operands 2 FE ae Qe a ad ae 0 TO pa te a o ED 5E Description The IM 2 instruction sets the vectored interrupt mode 2 This mode allows an indirect call to any memory location by an 8 bit vector supplied from the peripheral device This vector then becomes the least significant eight bits of the indirect pointer while the I register in the CPU provides the most significant eight bits This address points to an address in a vector table that is the starting address for the interrupt service routine Condition Bits Affected None UM008004 1204 M Cycles 2 T States 8 4 4 4 MHz E T 2 00 Z80 Instruct
178. ted None Example If the Index Register IX contains 2233H and the Stack Pointer contains 1007H at instruction PUSH IX memory address 1006H contains 22H memory address 1005H contains 33H and the Stack Pointer contains 1005H UM008004 1204 Z80 Instruction Set 118 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description PUSH IY SP 2 lt IYL SP 1 lt IYH PUSH IY 1 T4 4 ha a eel PF 1 4 1 0 0 1 0 1 ES The contents of the Index Register IY are pushed to the external memory LIFO last in first out Stack The Stack Pointer SP register pair holds the 16 bit address of the current top of the Stack This instruction first decrements the SP and loads the high order byte of IY to the memory address specified by SP then decrements SP again and loads the low order byte to the memory location corresponding to this new address in SP M Cycles T States 4 MHz E T 4 15 4 5 3 3 3 75 Condition Bits Affected None Example If the Index Register IY contains 2233H and the Stack Pointer Contains 1007H at instruction PUSH IY memory address 1006H contains 22H memory address 1005H contains 33H and the Stack Pointer contains 1005H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 119 POP qq Operation qqH lt SP 1 qqL lt SP Op Code POP Operands qq 1 1 q q 0 0 0 1 D
179. ted is taken from the location following this instruction If the condition is met M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If the condition is not met M Cycles T States 4 MHz E T 7 7 4 3 1 75 Condition Bits Affected None Example The Carry Flag is reset and it is required to repeat the jump instruction The assembly language statement is JR NC The resulting object code and PC after the jump are UM008004 1204 Z80 Instruction Set UM008004 1204 Location 480 481 Z80 CPU User s Manual ZiLOG 245 Instruction 30 lt PC after jump 00 Z80 Instruction Set 246 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description JRZ e If Z 0 continue If Z 1 PC lt PC e JR Z e 0 0 1 0 1 0 0 0 28 E e 2 p This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag If the flag is equal to a 1 the value of the displacement e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction Op Code and has a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the Zero Flag is equal to a 0 the next instruction executed is taken from the location following this instruction
180. tes 4 MHz E T 1 00 C is set if CY was 0 before operation reset otherwise UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 171 SCF Operation CY lt 1 Op Code SCF 0o o 1 1 0 414 1 1 37 Description The Carry flag in the F register is set M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is set UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 172 ZiLOG NOP Operation Op Code NOP olololojlolo ojo o00 Description The CPU performs no operation during this machine cycle M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 173 HALT Operation Op Code HALT ea ee ae te i S Description The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received While in the HALT state the processor executes NOPs to maintain memory refresh logic M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 174 zitoc DI Operation IFF lt 0 Op Code DI fe lie Pa AB OP AOE pale to Fs Description DI disables the maskable interrupt by rese
181. tion This instruction tests bit b in the memory location specified by the contents of register pair IX combined with the two s complement displacement d and sets the Z flag accordingly Operand b is specified as follows in the assembled object code UM008004 1204 Bit Tested 0 1 2 3 4 5 6 7 M cycles 5 b 000 0o01 010 011 100 101 110 ITI T States 4 MHz E T 20 4 4 3 5 4 5 00 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 229 Condition Bits Affected S is unknown Z is set if specified Bit is 0 reset otherwise H is set P V is unknown N is reset C is not affected Example If the contents of Index Register IX are 2000H and bit 6 in memory location 2004H contains 1 at execution of BIT 6 IX 4H the Z flag in the F register contains 0 and bit 6 in memory location 2004H still contains 1 Bit 0 in memory location 2004H is the least significant bit UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 230 ZiLOG BIT b IY d Operation Z lt IY d b Op Code BIT Operands b 1Y d 1 1 1 1711 1 01 FD 1 1 o0 o 14 o 14 1 cB A d gt 0 1 a b gt 1 1 0 Description This instruction tests bit b in the memory location specified by the content of register pair IY combined with the two s complement displacement d and sets the Z flag accordingly Operand b is specified as follows in the assemble
182. tion is met M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If the condition is not met M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example The Zero Flag is reset and it is required to jump back four locations from 480 The assembly language statement is JR NZ 4 The resulting object code and final PC value is UM008004 1204 Z80 Instruction Set UM008004 1204 Location 47C 47D 47E 47F 480 481 Instruction lt PC after jump 20 Z80 CPU User s Manual ZiLOG 249 FA two s complement 6 Z80 Instruction Set Z80 CPU User s Manual 250 ZiLOG JP HL Operation pc lt hL Op Code JP Operands HL 1 41 1 0 1 0 0 41 1 E9 Description The Program Counter register pair PC is loaded with the contents of the HL register pair The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If the contents of the Program Counter are 1000H and the contents of the HL register pair are 4800H at execution of JP HL the contents of the Program Counter are 4800H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 251 JP IX Operation pc lt IX Op Code JP Operands IX 11110 1 1 1 0 141 DD 1 1 14 0 1 0 0 1 9 Description The Program Counter
183. tion loads operand nn to register pair PC Program Counter and the program continues with the instruction beginning at address nn If condition cc is false the Program Counter is incremented as usual and the program continues with the next sequential instruction Condition cc is programmed as one of eight status that corresponds to condition bits in the Flag Register register F These eight status are defined in the table below that also specifies the corresponding cc bit fields in the assembled object code UM008004 1204 cc 000 001 010 011 100 101 110 111 Condition NZ non zero Z zero NC no carry C carry PO parity odd PE parity even P sign positive M sign negative Relevant Flag Z80 Instruction Set Z80 CPU User s Manual 240 ZiLOG M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the Carry flag C flag in the F register is set and the contents of address 1520 are 03H at execution of JP C 1520H the Program Counter contains 1520H and on the next machine cycle the CPD fetches byte 03H from address 1520H UM008004 1204 Z80 Instruction Set Operation PC lt PC e Z80 CPU User s Manual ZiLOG 241 JRe 1 0 0 7018 Op Code JR Operands e 0 lt a e 2 Description This instruction provides for unconditional branching to other segments of a program The value of the displacement e is a
184. truction Set Z80 CPU User s Manual 110 ZiLOG LD nn dd Operation nn 1 lt ddh nn lt ddl Op Code LD Operands nn dd 1 1 141 0 1 1 0417 ED 0 1idjd 0 01 1 jt n a lt a n a Description The low order byte of register pair dd is loaded to memory address nn the upper byte is loaded to memory address nn 1 Register pair dd defines either BC DE HL or SP assembled as follows in the object code Pair dd BC 00 DE 01 HL 10 SP 11 The first n operand after the Op Code is the low order byte of a two byte memory address M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If register pair BC contains the number 4644H the instruction LD 1000H BC results in 44H in memory location 1000H and 46H in memory location 1001H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 111 LD nn IX Operation nn 1 lt IXh nn lt IXI Op Code LD Operands nn IX 1 14 0 1 1 414 40 417 0D 0 0 4 0 0j 0 1 0 22 lt a n a n Description The low order byte in Index Register IX is loaded to memory address nn the upper order byte is loaded to the next highest address nn 1 The first n operand after the Op Code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00
185. ts Affected None Example If the contents of Index Register IX are 2006H at execution of DEC IX the contents of Index Register IX are 2005H UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual zitog 189 DEC IY Operation IY lt IY 1 Op Code DEC Operands IY 1 4 4 4 4 4 0 4 FD 0 0 1 0 1 0 1 1 2B Description The contents of the Index Register IY are decremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If the contents of the index Register IY are 7649H at execution of DEC IY the contents of index Register IY are 7648H UM008004 1204 Z80 Instruction Set 190 Z80 CPU User s Manual Rotate and Shift Group RLCA Operation ley lt 7 o a Op Code RLCA Operands 0 0 0 0 0 1 1 1 07 Description The contents of the Accumulator register A are rotated left 1 bit position The sign bit bit 7 is copied to the Carry flag and also to bit 0 Bit 0 is the least significant bit M cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 7 of Accumulator Example If the contents of the Accumulator are 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 at execution of RLCA the contents of the Accumulator and Carry flag
186. tting the interrupt enable flip flops IFF1 and IFF2 Note that this instruction disables the maskable interrupt during its execution M cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example When the CPU executes the instruction DI the maskable interrupt is disabled until it is subsequently re enabled by an EI instruction The CPU does not respond to an Interrupt Request INT signal UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 175 El Operation IFF lt 1 Op Code EI 1 14 4 1 41 0 1 1 FB Description The enable interrupt instruction sets both interrupt enable flip flops IFFI and IFF2 to a logic 1 allowing recognition of any maskable interrupt Note that during the execution of this instruction and the following instruction maskable interrupts are disabled M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example When the CPU executes instruction El RETI the maskable interrupt is enabled at execution of the RETI instruction UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual 176 ZiLOG IM 0 Operation Op Code IM Operands 0 1 14 1 0 14 1 0 1 ED 0 1 0 0 0 1 1 0 46 Description The IM 0 instruction sets interrupt mode 0 In this mode the interrupting device can insert any instruction on the data bus for execution by the CPU The first by
187. ty even reset otherwise N is reset C is data from bit 7 of source register If the contents of the Index Register IY are 1000H and the contents of memory location 1002H are UM008004 1204 Z80 Instruction Set UM008004 1204 Z80 CPU User s Manual ZiLOG at execution of RLC IY 2H the contents of memory location 1002H 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 and the Carry flag are C 7 6 5 4 3 2 4 0 1 0 0 0 1 0 0 0 1 Z80 Instruction Set 201 Z80 CPU User s Manual 202 zitoc RL m Operation CY a 7 a 0M Op Code PL Operands m The m operand is any of r HL X d or 1Y d as defined for the analogous PLC instructions These possible Op Code operand combinations are specified as follows in the assembled object code RLe 1 4 0 0 1 0 1 5 4 CB 0 0 0 1 O ma r gt RL HL 1 1 0 0 14 0 1 1 CB RL IX d 1 1 0 1 1 1 0 1 DD RL IY d 1 4 4 14 414 4 4 0 14 FB UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 203 r identifies registers B C D E H L or A assembled as follows in the object code field above Register r B 000 C 001 D 010 E 011 H 10
188. uction executed is taken from the location following this instruction If condition is met M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If condition is not met M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example The Carry flag is set and it is required to jump back four locations from 480 The assembly language statement is JR C 4 The resulting object code and final PC value is shown below UM008004 1204 Z80 Instruction Set UM008004 1204 Location 47C 47D 47E 47F 480 481 Instruction lt PC after jump 38 Z80 CPU User s Manual ZiLOG 243 FA two s complement 6 Z80 Instruction Set 244 Z80 CPU User s Manual ZiLOG Operation Op Code Operands Description JR NC e If C 1 continue If C 0 PC lt PC e JR NC e 0 0 1 1 0 0 0 0 30 q e 2 m This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag If the flag is equal to 0 the value of the displacement e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction Op Code and has a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the flag is equal to a 1 the next instruction execu
189. uctions Z80 CPU User s Manual xiv ziLoa List of Instructions UM008004 1204 Z80 CPU User s Manual List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 UM008004 1204 Z80 CPU Block Diagram 0 0 00 2 Z80 CPU Register Configuration 000 3 Z80 I O Pin Configuration 0 0 0 0 eee eee ee 7 Basic CPU Timing Example 00 000 12 Instruction Op Code Fetch 0 0 0 0 00 e eee 13 Memory Read or Write Cycle 0 0 0 0 20000 14 Input or Output Cycles 0 eee eee ee 15 Bus Request Acknowledge Cycle 0000 16 Interrupt Request Acknowledge Cycle 17 Non Maskable Interrupt Request Operation 18 HALT EXil srsntsdaavevhatn ad aciiow setae E E saa 19 Power Down Acknowledge 000 e005 19 Power Down Release Cycle No 1 2 0 5 20 Power Down Release Cycle No 2 0005 20 Power Down Release Cycle No 3 2 2 0 5 21 Mode 2 Interrupt Response Mode 26 Minimum Z80 Computer System 28 ROM and RAM Implementation 29 Adding One Wait State to an M1 Cycle 30 Adding One Wait State to An
190. ve One Byte Op Code 8 Bit Two s Complement Op Code Displacement Added to Address A 2 The value of relative addressing is that it allows jumps to nearby locations while only requiring two bytes of memory space For most programs relative jumps are by far the most prevalent type of jump due to the proximity of related program segments Thus these instructions can Significantly reduce memory space requirements The signed displacement can range between 127 and 128 from A 2 This allows for a total displacement of 129 to 126 from the jump relative Op Code address Another major advantage is that it allows for relocatable code UM008004 1204 Z80 CPU Instruction Description 46 Z80 CPU User s Manual Z ZiLOG Extended Addressing Extended Addressing provides for two bytes 16 bits of address to be included in the instruction This data can be an address to which a program can jump or it can be an address where an operand is located One or Op Code Two Bytes Low Order Address to Low Order Operand High Order Address to Low Order Operand Extended addressing is required for a program to jump from any location in memory to any other location or load and store data in any memory location During extended addressing use specify the source or destination address of an operand This notation nn is used to indicate the content of memory at nn where nn is the 16 bit address specified in the
191. ve number The total range for negative numbers is from 1 to 128 When inputting a byte from an I O device to a register using an IN r C instruction the S Flag indicates either positive S 0 or negative S 1 data Z80 Instruction Description Execution time E T for each instruction is given in microseconds for an assumed 4 MHz clock Total machine cycles M are indicated with total clock periods T States Also indicated are the number of T States for each M cycle For example M Cycles 2T States 7 4 3 4 MHZE T 1 75 indicates that the instruction consists of 2 machine cycles The first cycle contains 4 clock periods T States The second cycle contains 3 clock periods for a total of 7 clock periods or T States The instruction executes in 1 75 microseconds Register format is indicated for each instruction with the most significant bit to the left and the least significant bit to the right UM008004 1204 Z80 Instruction Set Z80 CPU User s Manual ZiLOG 81 8 Bit Load Group LDr r Operation r lt r Op Code LD Operands r r 0 1 r gt a r gt Description The contents of any register r are loaded to any other register r r r identifies any of the registers A B C D E H or L assembled as follows in the object code Register r C A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States MHz E T 1 4 1 0 Condition Bits Affected None Exam
192. with carry and set flags SBC HL ED ED ED ED 42 52 62 72 Increment INC DD FD 23 23 Decrement DEC DD FD Rotate and Shift 2B 2B A major feature of the Z80 is to rotate or shift data in the accumulator any general purpose register or any memory location All the rotate and shift Op Codes are depicted in Figure 10 Also included in the Z80 are arithmetic and logical shift operations These operations are useful in a wide range of applications including integer multiplication and division Two BCD digit rotate instructions RRD and RLD allow a digit in the accumulator to be rotated with the two digits in a memory location pointed to by register pair HL See Figure 10 These instructions allow for efficient BCD arithmetic UM008004 1204 Z80 CPU Instruction Description Z80 CPU User s Manual ZilLoG 63 Table 10 Rotates and Shifts Source T A B C D E F L_ HL aX 4 Y d Rotate aa pears e cy by bo Left Circular Rotate Shift Rotate RCL CB CB CB CB CB CB CB CB DD_ FD RLCA Right Circular 07 00 01 02 03 04 06 JOE CB CB d d 06 06 Rotate RRC CB CB CB CB CB CB CB CB DD_ FD RRCA a Left oF 08 o9 oa 06 oc oD 0E CB CB N d d o oE Rotate RL CB CB CB CB CB CB
193. y Memory Cycle 31 Interfacing Dynamic RAMS 0 0 0 ee eee 32 Shifting of BCD Digits Bytes 0 0 36 List of Figures XV Z80 CPU User s Manual xvi ziLoa List of Figures UM008004 1204 Z80 CPU User s Manual ZiLOG xvii List of Tables Table 1 Revision History of this Document iii Table 2 Interrupt Enable Disable Flip Flops 23 Table 3 Bubble Listing 0 0 0 eee eee eee eee 37 Table 4 Multiply Listing 0 0 0 0 eee eee ee eee 39 Table 5 Hex Binary Decimal Conversion Table 49 Table 6 8 Bit Load Group LD 0 0 00 eee eee eee 51 Table 7 16 Bit Load Group LD PUSH and POP 55 Table 8 Exchanges EX and EXX 1 0 ce eee ee eee 56 Table 9 Block Transfer Group 20 0 cece eee eee 58 Table 10 Block Search Group 0 0 cece eee eee eee 58 Table 11 8 Bit Arithmetic and Logic 0 000000 0008 60 Table 12 General Purpose AF Operation 0004 61 Table 13 16 Bit Arithmetic 0 0 0 eee eee eee 61 Table 14 Rotates and Shifts 0 0 eee eee eee eee 63 Table 15 Bit Manipulation Group 00 0 0 eee eee eee 65 Table 16 Jump Call and Return Group 04 69 Table 17 Restart Group cacica eee ee eee 70 Table 18 Input Group ss oioi ers cee eee 72 Table 19 8 Bit Arithmetic and Logic

Z80 Family CPU User Manual - Thomas Scherrer Z80

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