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Service Manual - System 2000 Winchester Disk Controller

1. 1 6 Related 1 1 6 INSTALLATION 4 26 5 55 5 ae s ea verra eV n d Single Board 555 5 5 5 5 894 68 2 Unpacking Packing Instructions 2 1 Installation Requirements 2 1 Two Board WDC 2 4 Unpacking Packing Instructions 2 4 Installation Requirements 2 4 FUNCTIONAL DESCRIPTION 444 55 6665 5 45 5 54 8 4 hdi Adaptor Section Functions 3 1 Controller Section 10 8 32 3 System I O Interface OU AAA VOTO WDC I O Addresses 594 E ROSA RU Ve 60S s CL 3 WDC TransacLtlODn 44 ses9 999 9 eva AV Te Completion Status 2 7 Error SENSING a WS NON OS 6 O 00 5 l Sense Byte 2 Error Codes wav 9 ers 2 exe 6 RARE sux 55950 Class 00 Error Codes e 3 8 Class 01 Error Codes 3 84 Class 02 Error Codes 3 8 Power 5 64 5 5 8 6 5 4 64279 Power Down Power Fail 3 10 Disk Drive
2. 3 10 BOSS IX System to WDC 4 3 10 Output Buffer Empty Status 3 10 Direct Fetching of Data 3 11 Unpacking Data Registers 3 11 Generating Internal Bus Requests 3 11 WDC to BOSS IX System 3 11 Input Buffer Empty Status 3 12 Operation Complete Status 3 12 Direct Loading of Data 3 12 v M8158A TABLE OF CONTENTS cont d Page SECTION 3 FUNCTIONAL DESCRIPTION cont d Generating Internal Bus Requests 3 12 Diagnostic Features 45 299 945 6 3 13 Register and Buffer Tests 3 13 DMA and Interrupt Logic Tests 3 13 Detailed Description of Command Description Block CDB 3 14 Class 00 Command Descriptions 23 14 Class 00 Command Code Summary 3 15 Test Unit Ready Op Code 00h 3 15 Rezero Unit Op Code Oih 3 15 Request Sense Op Code 03h 3 16 Format Unit Op Code 04h 23 16 Read Op Code 08h 23 17 Write Op Code Ah 3 17 Seek Op Code OBh 3 18 Translate Op Code OFh 3
3. LS nin ary Bg NE fe 5 43 aie amp Sa INIST IS ISIS S IS NSIS Us 91 91 91919 Di o o QQ Io o DA Quo amp 13 lt i q q lt lt lt lt lt lt S Jala f N N S SIS lt lt lt lt q X X S X X X X X X X Y q X amp wo 0 48 s s ESSE gt 5 gt S S SISI S S Is 445 SA a rs I ORR SR ESSERI SN 8 Yen t Ql aia Sele tig N SISI SISI Ui VIO Ered QIS azl AAR d 55532 5 25455245 a ui laini n 5 SRSERISSISSISISISNISSISRIS SIS siivicizielsizisigisisisigigisls Figure B 12 Part No 907649 001 Logic Diagram Sheet 13 of 15 B 45 M8158A n ew Ira 2 SD 19 2 s 252 EE 4 01 ig 29 252 6 7 5052 18 SGS TESI GAO 5 1 505 EG GND 2 112 GNO 24 ACK I 1 8060 38 GND 14 GNO ip 29 AST 807 42 GND rC GNO 16 EIB MSG CA 22 1 29 45 250 NO 2 20 i ie GNO REQ jg 724 CEA euo Guo a 1 01 25 5 1 Figure B 12 Part No 907649 001 Logic Diagram Sheet 14 of 15 8158 B 46 Figure B 12 8158 PAL i MASTER PAL
4. BRQOUT DRBUS OPCOMP MSG BUSY Load into lower byte of input data register Buffer empty LLDR 1 ACKOUTsO PIOUTF 0 Load into upper byte of input data register Buffer empty ACKOUT 0 LUDR 1 PIOUTF 0 Initiate bus request Reset LLDR BRQOUT 1 LLDRsO Reset LUDR Upper data register full LUDR 0 UDRF 1 DRBUS 1 Reset BRQOUT BRQOUT 0 REQ DRBUS Figure B 8 WDC to BOSS IX System Programmed DMA PAL State Diagram B 10 Table B 2 SIGNAL AB00 23 AS BGACK BGNT BERR BR BPRO to BPR3 CCLK DB00 15 M8158A BOSS IX System I O Bus EBUS Interface Signal Descriptions IN OUT IN OUT IN OUT IN OUT IN IN OUT OUT IN IN OUT DESCRIPTIONS 23 BIT ADDRESS BUS ADDRESS STROBE TO INDICATE ADDRESS ON THE ADDRESS BUS IS STABLE BUS GRANT ACKNOWLEDGE TO INDICATE BUS CONTROL IS BEING TRANSFERRED BUS GRANT TO INDICATE GRANT THE BUS FROM 68000 UP BUS ERROR TO INDICATE ABNORMAL CONDITION ON THE HOST BUS BUS REQUEST TO INDICATE ADAPTER IS RE QUESTING USAGE OF BUS BUS PRIORITIES ENCODED PRIORITY ADDRESS USED TO RESOLVE PRIORITIES BY BUS MASTER CPU CLOCK 16 BIT DATA BUS USED TO TRANSFER COMMANDS AND DATA B 11 SIGNAL I O C D BUSY REQ ACK RST SEL 7 to DBO 8158 Table B 3 IN OUT IN IN IN IN OUT OUT OUT IN OUT SCSI Interface Signal D
5. EERE 38 74537 122222 74802 4 ol 74574 5 5 7 77 rac asne 5 5 ae 741574 9 6 77 757 lt aw rasna e 22222 74 582402 e eee sx s02 7 pnt rac z 7 Ew sene 1 BAL EE ENG asa itt N Figure B 10 MB158A COMPONENT MAP an 745274 7 LL AA 74374 9 Eug Wu pee pecu sure 4 _L L 40 7415649 0 ae P ar PAL 46 7415374 Id 2122 7415374 10 7 27 7415273 9 T 4K 7415374 9 Dorm u l am 2415374 9 ew 7445374 7 7419244 9 9 9 9 s Es ps su ON 5C RES NTWK Id ur 50 7464 TAREAS E N rsa 74504 7 19 E pe 71500 5 on 57 741500 amp s usos 5 E IN N we NNN NN li 18 Ge e T Part No 903439 001 Logic Diagram Sheet 2 of 13 Jil J OF SY THRU 32 5 V t n HAS amp Figure B 10 Part No 903439 001 Logic Diagram Sheet 3 of 13 B 19 M8158A 8158 O 5V qua 8 5 7 S 48 3
6. NEM zoo Se ee ete ee eg ee Pe LXVI ass eee d ar BEEN A 6 17 ET sino igw 9 i Scb 2 51 4 07 HI 27 sl 4 SUNL GRIS CER ae Se LE ee T m 9 5 9 xv ep CA FE E LI 251212 Es MEE LIE 7905 S NN LUN E 7051 02 232 279 N32N3n039 10 1 02 100735 300 3 FivOW2IV T U v vIVO 45 di el o VIVO JN WIW 1 er oe 91 Oi 3 z i e Y207 SAS X3GA1 be vdi Gdi Qi X2072d39 IM 2 SR 2 S l i 222139009396 v4va grass MO M a mm WEST 406 36 3NO 2M3 H a ee SS ae Ba ey es prn ira ari 2 42 3 gram Sheet 8 of 12 ic Dia Schemat Part No 903496 Figure A 10 A 32 MB158A 113590 Qm Fea t FA zi E ee 2 LT Ff j 1 lt by bivay 9 avin ei Fz lt Lew Ei as 2357 4 V 1vOM gt Xt St p 2 S1PL 2 11vQu ef 4 t KU 63 Ades lt Age 6 5 DA Fd Wier mom 4 EN 31 SE 6 9 I 2 i n 63 s3N9 e E d di 2 3 octy 21 m in vi DIVO er bes tvr
7. ONnONO 21901 s i 42070 435 g ngd 402 31 LINd tawy e Ou 1972392 1226 2 Ch i p 651 0049 d3 gvi SNgi g 3N AV730 Viva MYY tli NED S ny ANNOY DOWNY 10 Figure lt lt lt 6 H 1 gs IA 4 121511 S oi 1412196 lt d Q 2 a di a O g c z ic z a me YF 4149349444544 2149 Zen z daz ez lt Zz z Glee SHO AAY Glowing SS ES ax 20 i ay o 0 O 2 lt ja ajajaja lt lt lt lt lt a 9 e O DI Cr ELS mman RNN 8141220 44 444 4444 AI oa eo zii mio SS ses aq cono Saada jaa aia s ez o le 44444 lt lt lt lt lt 55150 5 AL 402 422 445 406 487 ra aio rm a2 Asa Ais LIS A2 22 23 yi d amp 11a Ba daoo gd 22 222 53 ds 4 buf 0 T oo d 8 3 NISI esM S giu e 1 S 3 po 3 C NI SSESSSSSSisiadalstssilss
8. 254444624 2009020v 2 facts ss 9595 1 Pi H H MP ZZ 2 o ogre T b ELEELE S 2 LE e 8 gt woeeer O 5 s LE she v 5 outa E e gt ele A oj be E y gt ne el 2 ejej ee ovje 4e ele ae 1 gt e ejo o ipei e b NE 93 e ov a we vs gt ME D eee 090614 999920990 J 9909090099799 5 722 EA n ni a ee i dii OTT T 225241 WE Part No 907649 001 Parts Location Diagram Figure B 11 B 30 M8158A NO 0001 0003 0005 0007 0008 0009 0010 0011 0014 0021 0022 0024 0026 0027 0029 0030 0033 0034 0035 0036 0037 0038 0039 0041 0043 0044 0045 0046 0047 0048 0050 0051 0055 0056 0061 0062 0075 0076 0080 0081 0082 0084 0085 0086 0087 0090 Table B 6 Part No 907649 001 List of Parts Sheet 1 of 2 PART NO 905150 001 762022 003 101514 101709 101710 101711 101656 161015 101740 101633 161068 001 161064 001 161023 161065 001 161111 001 161151 001 101315 101655 101623 101625 101627 101615 101628 101629 101630 16
9. Part No 903496 Schematic Diagram Sheet 5 of 12 Figure A 10 8158 29 ts diWOJg0 8 003 4073 009 sond S WNIONM SUYIININDIS Wd N3035 lt SEZ 73809 071 7775 2 zaya 2 100014 nite TONIOIS KIKE iviivds ya7 201 g YNI PET a g t I 10026794 PRSE 2 uc MN V AG 201915 _ 49 ori 2327 CS 155 Sneed 400049 4 2101019 Gee OED 6 0 _ x g ASH YIYO Ted 2 003 asa 9 b 1703 0 1 722 034 fid fe t e 33g 460 16 609 y 2 6 0 Vi IGN 2 49 Figure A 10 Part No 903496 Schematic Diagram Sheet 6 of 12 30 8158 4 CKENVECT SNBDSEL 4 4 CCLK Un S SKCOMP NT I 5 9 DORSEL f 9 DASELO 5 INTEND OF NTOt PU9 HINTR MYBERR 5 6 INTENY 4 CLRBER ORB2 OPCOMP 4 PIOIN 86 4 E NAUOR PLOINOL 4 INTERRUPT PAL 1 PU2 Jt cra BERRI BERR Figure A 10 Part No 903496 Schematic Diagram Sheet 7 of 12 A 31 M8158A Speen ee ee 2506 HUM DOKN ee O eee ee 9
10. 2 eva I 2gav ava 1 6 Sav engyua i 21611208 5 1N01S9S ecisavL 1534N395 VN s 213638 m EEE TE 1 507 2f ELE 1 1353u if 4122 1 122 ef 100122 vil 5 l r 231999 uqnvN3 HO VN3 EUT 6 019125 2152 83 5 dd ld HON 2 FIT LEA BI HEH iray poses 1 MISHA 2 zi 7123 H 1 I WS be Love sve MOR 2 vg 6 0759 c 2 ie 8v 9 1 253 9v Wuovwa we ruv 6 r 255509 vQ192 1v I QY S CL 1 61 1 9122 vd D ery 28v Part No 903496 Schematic Diagram Sheet 4 of 12 Figure A 10 A 28 M8158A 2 999 608 109 mo m 200 609 909 109 Gt431lNI O QH3 NI 3035 N31N Qo ESTE 1595 mS gg WS 6795100 Bk WNIS YILGIOIN 6n1v15 acy 2 9 325 1511 29 9 O g P 1noold vL lap mp _ _ g gt CIS ES 7 e 7110019 7 Was si 2 54 TEE AG4 M3191034 70102 315193 YOLIIN k H Old TaS NI er 9 S usa lt 6426171 961 N
11. OH OY 9 2 19 9 19 92 19 9 10 9 19 9 19 9 0 0242 7 804 Je 7 82021 Sr Taz 7 ADG ATTE 4802 1 72 2 05 AB 2 5 48042 7 C3 1 ABQ2 I ABOS 1 ABGO L 4807 1 4 7 8028 7 8009 7 50107 7 BDIIY 7 80 24 y ED 2 4 7 BD 5 DMADRM e DMADRH t 2 8004 3 BDOS 7 BOOT s JBACK PB22 T 2 5 1 6 Figure B 12 Part No 907649 001 Logic Diagram Sheet 8 of 15 8158 40 2 a R3 O SY ORN X 2320 INTEN SEQEN ERST 7125544 SRST RESET 2g 6 Dit 02 03 04 25 07 08 5 DREUS OBOO 0821 1 422 0804 7 15 0605 1 0826 2807 I 18 BD G e P OOUT BOQI DBDIR 5 184666 73 be 525 FIZE 241520 82 5 8020 IE 8047 4 0471 47 LL 1 LLL LUC Dvd E mI 18 028 1 21 Ll 4 l 17 BDS DY2 amp DI 6 0 3 Gs IP EM FET 011 16 04 eee 2012 0 5 ee as 17 55 2 BDI3 032 5 BD14 ip 22 ES saa EE RENNES EL TI 8015 Figure B 12 Part No 907649 001 Logic Diagram Sheet 9 of 15 M8158A B 41 S YN SN NON NNNNNN NON 9 7 DO 7 Qi 7 22 7 03 7 7 06 D t 7 07 ae FLOR Le ALOR LLLI ee ee G C
12. 74LS 00 44 4 gt 7445 7428 SRESE REQ 4 92 4 804 y Ll MEG s rca a 9 VA _ Lag 7 0 1 pe gt F e Figure B 10 Part No 903439 001 Logic Diagram Sheet 10 of 13 8158 26 5 D BZ 2 5 741508 3 15 HINTR 5 CLRBER RESET 4 A V 2 9 _SEQEN 10 5 7415098 PAL IGRO ij BUSY N BROIN hi p 1207 57 ERE FUDR 7 1g pila 2 _ l ADR 9 1g DABUS 2 DATLAT ACKIN yg f PION ECLK 5 OPCOMP REQ 4 TNR LLOR ig ACKOUT 1 2 PIOOUT PUO 45244 24 18 BOGE 7 Q 5 4 WE MES BDO2 d ea Z 22 SRESET 9 peu F MS G 3 4 7 8245 7 E 17 3 8027 Dar p Figure B 10 Part No 903439 001 Logic Diagram Sheet 11 of 13 B 27 M8158A an 9 RRA AR 24722 I 2 9 For ev SGA Se 2 204 6 2 IND TAS 2046 SOAS 622 2 6 20 622 1 507 1 500 ONS ONS 822 lgzv 822 OND ONI 20452 204 CF M 222 5 E 222 Y M 204 204 G4 522 6 Gey 622 d I 71999 22 6 3 598 2v T Ono 22 OND 22 7 60680 FEE 6 17 5090 z2r 222 75090 122 6 12040 72 722 Teddi 222 4 18900 za 201 022 204 G7 612 L Fg EG 612 1 82 17 0797 OND 452 8 2 ane g v 8 2 2 451 LL Hz p
13. FLDR ENABLE BUSY ACKIN PIOIN BUSY ENABLE LDRE LDRE FLDR ENABLE OUT DAT REQ LDRE ENABLE DRBUS BUSY DRBUS BUSY ENABLE LDRE FLDR BUSY ACKIN REQ DATLAT REQ ACKIN DATLAT BUSY BRQIN REQ PREFET ENABLE OUT DAT REQ UDRE LDRE OUT DAT ACKIN ENABLE BRQIN DRBUS ENABLE PIOIN ENABLE BUSY PREFET PIOIN REQ OUT ACKIN MB158A B 6 E f z Jum EE ACKOUT fr PIOUTF Sma ii P EP _ i REQ Pp Figure B 5 WDC to BOSS IX System Programmed I O PAL Timing Diagram B 7 8158 Idle State Request transfer of a byte from SASI controller PIOUTF 1 Reset LLDR amp ACKOUT LLDR 0 ACKOUT 0 Load into lower input data register Return ACK Buffer empty LLDR 1 ACKOUT 1 PIOUTF 0 Figure B 6 WDC to BOSS IX System Programmed I O PAL State Diagram M8158A B 8 CCLK OPCOHP BRQOUT M E mM s i H pn ait ARE PIOUTF zii ETUR i q ef F ACKDLY Y MM ACKOUT Figure B 7 WDC to BOSS IX System Programmed DMA PAT Timing Diagram B 9 M8158A 8158 Send ACK Load data into SASI input buffer ACKOUTs1 PIOUTF 1 REQ PIOUTF UDRF ENABLE BROOUT BUSY
14. HINTR 0 OPCOMP MYBERR LENVECT SINTEN RESET INTEN BERR INTO INTL CKENVEC CLRBER NC DRB2 ENB OPCOMP PIOIN PIOINDL LENVECT MYBERR HINTR RESET VCC INTO RESET RESET MYBERR INTEN LENVECT RESET OPCOMP INTEN LENVECT RESET BERR DRB2 RESET MYBERR CLRBER RESET CKENVEC LENVECT OPCOMP INTEN LENVECT MYBERR INTEN Il PIOIN ENAUDR Figure 8 Interrupt PAL State Diagram and Signal Listing A 12 I O PORT ADDRESS 00H TO 7FH 80H 81H 82H 83H 84H 85H 86H to FFH Table A 4 Microprocessor Memory and I O Addressing Map MEMORY ADDRESS 0000H TO 3 FFH 4000H TO 7FFFH 8000H TO BFFFH 000 TO FFFFH Not Used DESCRIPTION 8085 FIRMWARE EPROM 8K AIC 010 and AIC 300 8156 RAM 256 bytes Not used Not mapped DESCRIPTION 8156 Command Status Status Register 8156 I O Port A 8156 I O Port B 8156 I O Port C 8156 Lower Byte of Timer Count 8156 High Byte of Timer Count Mode Not Used 13 Out DATA BITS D0 D7 D0 D7 D0 D7 DATA BITS D0 D7 D0 D7 D0 D7 0 5 D0 D7 D0 D7 8158 SIGNAL AB00 23 AS BGACK BGNT BERR BR BPRO to BPR3 CCLK DB00 15 DTACK IACK RESET R W FC2 LDS 8158 IN OUT IN OUT IN OUT IN OUT IN IN OUT OUT IN IN OUT IN OUT IN IN IN OUT IN IN OU
15. 2 Hrs a Jii 2 6 J a BPR2 I p BPRI c 74538 i 9 8 BPR 72538 E ie M N 1 ho fs 5 HMATCH MYTURN 5 SF 745 2 ENVE CT e L08 12 az 2 7 Figure B 10 Part No 903439 001 Logic Diagram Sheet 4 of 13 B 20 so S amp s e M8158A BAB q s 2F p 482 13 c 72538 BAB 2 l 5 Tack E 2 2 74558 7 Coats uz Wie fe ee UD x 2 1 E BGNT I D 18 I CCLK4 Putt DTACK BERR CCLK MYTURN lla TACK 4 ASt 9 a 2E RESET Figure B 10 745260 Part No 903439 001 Logic Diagram Sheet 5 of B 21 Ji HMATCH g PREZI IBACK o Ji BACK I 4 2 I8ACK 7 8 13 W R 7 2 8 2821 1 q DMADRM 4820 1 42 54532 a s AED DMADRL g 8 A8 7 I l4 74532 48 YR b WRCTR PIO N H s RACK WRSEL 7 CLRBER 7415220 37 823 2 18 4822 1 4 gt a BAB3t_ ES ae 4818 1 8 Jl 2 indes RDCTLST 4803 1 o PIOQUT 7 8 AB 2 I s 2 0 7 7 BA D NE 4 ENVECT YECOUT 745244 MYDTACK IH J2 cog LOS I 2 P 429 2 72 DTACK Bead QU
16. 4 g 19 521 7 9 Diagram Sheet 1 of 12 Schemati 903496 A 10 Part No Figure 8158 25 NOILVYILIGYY YWO LdYH31NI S09 3 1 o2 i LO E DE Sm v Lv el va 1 0 25 tsi 343 tv P 4 I 3bf d M2vid 2 v vnd 1 w2v8 wv 3122 vena reuse 4 44122 S naug 4 21795 219595 0 Odd 649 75y 155 21595 5 77909 2979 tovg ING WINIW amp 059 x3vi8 4 ri TT v8 702 Wd o eDVIO O h ges 5 1 Er u lt j 1721 ET 5 gram Sheet 2 of 12 Schematic D A 26 Part No 903496 Figure A 10 8158 6M31N002 ONY 6639449 vwa 1 lt 28 1 224 1 1 8 3 lt uc o U lt qm o 66 S1bL 66961 66961 e Ir WHOvWQO 11 ni 6696104 6695164 662s1vL 5 1 ALS O a d al a c i Sheet 3 of 12 Diagram 903496 Schematic A 10 Part No Figure M8158A 27 6 6 t 2 2 2 s o a 00 m SYINFIIIA ong 3 30070 653000 pe j 1 gva 1 1
17. BD0 8 BDSEL BERR CCLK CLRBER DB00 15 DBDIR DMADRL DMADRM DMADRH DRBUS DTACK Table A 8 List of WDC Mnemonics DESCRIPTION BOSS IX SYSTEM ADDRESS BUS BITS 01 THROUGH 23 ACKNOWLEDGE DATA IN TO CONTROLLER SECTION ACKNOWLEDGE DATA OUT FROM CONTROLLER SECTION BOST ACKNOWLEDGE BUS REQUEST BUFFERED DATA BITS 0 THROUGH 8 HOST ACCESS SELECT WDC BOARD BOSS IX SYSTEM BUS ERROR BOSS IX SYSTEM BUS GRANT HOST CPU CLOCK CLEAR BUS ERROR LATCH BOSS IX SYSTEM DATA BUS BIT 00 THROUGH 15 DATA BUS DIRECTION LOAD LOWER DMA ADDRESS REGISTER LOAD MIDDLE DMA ADDRESS REGISTER LOAD HIGHER DMA ADDRESS REGISTER DRIVE BOSS IX SYSTEM BUS BOSS IX SYSTEM DATA TRANSFER ACKNOWLEDGE ENABLE LOWER DATA TRANSCEIVER A 17 8158 SS SS C2 fl mm FE ene GE 1538 CS at mil 5 E fl ki pie 28 TSN lt I DOR rv ES 249 691 Part No 903496 Parts Location Diagram Figure A 9 18 8158 NO 0001 0003 0005 0010 0011 0012 0014 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0050 0051 0052 0053 0054 0060 0061 0062 0063 0064 0065 0066 0067 Table A 9 Part No 903496 001 List of Parts Sheet 1 of 3 PART NO 905019 001 762022 003 101514 168014 001 168000 006 168000 008 101710 101781
18. R31 R2 38 R34 R13 R10 11 30 R42 R15 R16 R19 R32 CR2 3 4 5 6 7 9 10 1 C64 C65 66 C67 68 69 C61 C58 C63 C71 C3 48 52 56 57 59 60 62 C53 54 55 72 8158 NO 0133 0134 0140 0141 0142 0145 0150 0151 0160 0161 0162 0163 0164 0165 0170 0171 0174 0175 0176 0177 0178 0179 0180 0181 0182 PART NO 102000 001 108016 004 140005 001 140028 001 141022 001 135041 001 132016 001 132015 001 300092 001 310019 001 907388 001 907769 001 907985 001 214027 001 300032 016 300032 009 325005 011 325005 012 325005 007 325005 010 325005 001 700023 300032 002 325026 003 325033 001 M8158A DESCRIPTION CAP SOLID TANTALUM AXIAL 15UF 10 20V CAP ALUM ELECT 100 UF 75 20 TRANS NPN GEN PURP 2N3904 CASE TO 92 TRANSISTOR NPN LOW VOLT SILICON SW TRANS PNP 2N5771 INDUCTOR 2 2UH SHIELDED 10 1 78105 3TERM FIX 5 0V POS VOLT REG Ic 79L05 3TERM FIX 5 0V NEG VOLT REG CONN DIN FML 3X32 PRESS FIT 64 POS A amp C CONN HOUSING GUIDE DIN 3X32 100CTS ML EJECTOR EURO DIN CONN STACK LATCH EURO DIN CONNECTOR STACK CATCH PCBA STACK CONTROLLERS FASTENER PUSH ON 312 DIA STUD CONN HDR DBL ROW 100CTS 025SQ 34POS CONN HDR DBL ROW 100CTS 025SQ 20POS SOCKET IC DIP 4 LEAF CONT GOLD 20POS SOCKET IC DIP 4 LEAF GOLD 24POS 300 SOCKET IC DIP 4 LEAF CONT GOLD 28POS SOCKET IC DIP 4 LEAF CONT GOLD 40POS SOCKET DIP 4 LEAF CONT GOLD 24POS TAPE DOUBLE SIDED 50 W
19. 100 CARBON FILM 25W 5 220 CARBON 25W 5 330 CARBON 25W 5 390 CARBON FILM 25W 5 680 CARBON 25W 5 1K CARBON FIIM 25W 5 4 7KOHM CARBON FIIM 25W 5 10K CARBON FIIM 25W 5 75K OHM CARBON 25W 5 100K OHM CARBON FIIM 25W 5 1 0K OHM CARBON 25W 5 620 OHM METAL 125W 1 511 OHM METAL FILM 125W 1 1 10K OHM METAL FIIM 125W 1 1 02K OHM METAL FILM 125W 1 1 65K OHM METAL 125W 1 1 96K OHM METAL FILM 125W 1 2 67K OHM METAL FILM 125W 1 3 09K OHM CARBON FILM 25W 5 150 OHM CARBON 25W 5 430 OHM CARBON FIIM 25W 5 470 OHM SQ CERMET 5W MULTI SQ CERMET 5W MULTI NTWK 8 PIN SIP 220 OHM NTWK SIP LP 10PIN 9 RES 1 0K OHM NTWK 8 PIN SIP 330 OHM TURN 2 0K OHM TURN 50K OHM NTWK SIP C C 10 PIN 9 RES 2 2K OHM CRYSTAL PARALLEL RESONANCE 6 0MHZ 30PF CRYSTAL FUND 10 000MHZ 005 IC DELAY LINE 10 TAPS 100 OHMS 100NS DIODE LIGHT EMITTING GREEN DIFF LENS DIODE SWITCHING 1N914B DIODE VAPACTOR HIGH CAP 400 500PF MICA DIPPED RADIAL 51PF 5 500V MICA DIPPED RADIAL 10PF 5 500V MICA DIPPED RADIAL 18PF 5 300V MICA DIPPED RADIAL 150PF 5 500V MICA DIPPED RADIAL 330PF 5 100V MICA DIPPED RADIAL 270PF 1 500V CERAMIC COG AXIAL 6800PF 5 50V CERAMIC 250 AXL 10 80 20 50V SOLID TANTALUM RDAL 4 7UF 20 35V A 23 REFERENCE SU R1 R14 20 26 33 36 37 R22 24 27 R4 5 23 25 35 R21 R3 R39
20. BUSY LUDA e LLDR DAT ACKOUT PIOOUT REQ DAT e QUT ENABLE PIODUT e REQ DAT e OUT ACKOUT PIOUTF LLDR LUDR 9 BUSY LUDA PIOUTF UDRF ENABLE BROOUT e DRBUS OPCOMP e BUSY e DAT LUDR PIOUTF e ENABLE BUSY LUDR ACKOUT BUSY 9 ENABLE 9 DAT UDRF LUDR ENABLE e BUSY DAT UORF ENABLE e BUSY DRBUS LLOR e PIOUTF UDRF ENABLE e BROOUT BUSY LUDR e DAT LLOR PIOUTE ENABLE BUSY PIOUTF e PIOQUT PIODUT BUSY ENABLE LLDR ACKOUT 6 BUSY ENABLE DAT ACKOUT REO PIOUTF e OUT ENABLE DAT LUDR e LLDR REQ PIOGUT OUT e PIOUTF ACKOUT REG 8USY PIOOUT BROOUT UDRF LLDR ENABLE 9 BUSY DAT 9 DABUS BROOUT DRBUS ENABLE BUSY UDRP OUT DAT N8Q e REO DRSUS OPCOMP REO OUT DAT BROOUT UDRF DOBYTE UDRF OUT DAT e MgO 9 REQ e BUSY DOBYTE M8Q BUSY Part No 907649 001 Logic Diagram Sheet 15 of 15 B 47 8158
21. BYTE BIT 7 bo 3 O 00 100 0 1 0 1 1 1 0 01 Logical Unit No Reserved 02 MSB Logical Block Address 03 Logical Block Address i 04 Logical Block Address 05 i Logical Block Address LSB 06 i Reserved 07 Number of Blocks 08 j Number of Blocks 09 i Control Byte Reserved 3 3 2 7 Verify Op Code 2Eh The VERIFY command is similar to the WRITE AND VERIFY command Op Code 2Eh except that VERIFY checks the ECC of an already existing set of data blocks It is up to the host to provide data for rewriting and correcting if an error is detected The bit pattern for VERIFY is as follows BYTE BIT 5 4 5 3 2 00 0 0 1 0 1 1 1 J 3 01 Logical Unit No Reserved 02 MSB Logical Block Address 03 Logical Block Address t 04 Logical Block Address 05 Logical Block Address LSB 06 i Reserved i 07 i Number of Blocks 08 Number of Blocks 09 4 Control Byte Reserved 3 3 2 8 Search Data Equal Op Code 31h The SEARCH DATA EQUAL command provides for a search and compare on equal of any data on the disk using indexed access methods for rapidly searching for record key fields When a SEARCH is satisfied it will terminate with a Condition Met Status M8158A 3 26 A REQUEST SENSE command can then be issued to determine the block address of the matching record and reported as follows EQUAL setting o
22. PAD ISOLATION CHART 1 j 529 JUMPER WIRE CHART 1 ses ane cove soe x Z soe 5 5 7 S0 6 side LOCATION 1 RGR TERS 9 FRO e 26 RI CE CGE CR fJ Part No 903439 001 Parts Location Diagram B 14 REF NO 0001 0003 0005 0007 0008 0009 0010 0011 0014 0015 0018 0021 0022 0024 0026 0027 0029 0030 0033 0034 0035 0036 0037 0038 0039 0041 0043 0044 0045 0046 0047 0048 0055 0056 0061 0062 0075 0076 0080 0081 0082 0084 0085 0086 0087 0090 0095 Table 5 Part No 903439 001 List of Parts Sheet 1 of 2 PART NO 904854 001 762022 003 101514 101709 101710 101711 101656 161015 101740 101741 101719 101633 161068 001 161064 001 161023 161065 001 161111 001 161145 001 101315 101655 101623 101625 101627 101615 101628 101629 101630 161076 001 101631 161009 101637 161074 001 911006 008 911009 004 119016 003 119009 004 104010 001 108016 004 300092 001 310019 001 300032 012 907388 001 907769 001 907985 001 214027 001 325005 011 331014 005 8158 DESCRIPTION PCB WDC BUS ADAPTER LABEL TAB 375X1 250 YEL IC 7438 BUFFER QUAD 2 INPUT NAND IC 74LS00 QUAD 2 IN NAND 1 741502 QUAD 2 IN NOR IC 74LS08 QUAD 2INP AND IC 74LS04 HEX INVERTER IC 74LS14 HEX SCHMITT TRIGGER INVERTER IC 74LS51 DUAL 2 WIDE 2 IN amp OR INVERT IC 741574
23. i Starting Address of Dump LSB Dumped Data xx00 Dumped Data xxFF Send Diagnostic Op Code 1Dh The SEND DIAGNOSTIC command sends data to the WDC to specify diagnostic tests SEND DIAGNOSTIC command are as follows 4 6 4 5 4 3 2 1 01 i 0 0 0 1 1 1 0 l i Logical Unit No Reserved i Reserved MSB Data Length Data Length LSB Control Byte Reserved The bit pattern and significance of the Data Length Field Byte 03 Specifies the length of the data to be sent Length must be a minimum of four bytes long and equal to the length of the data block to be passed to the WDC if the speci fied length is longer than needed the excess is ignored pattern and significance of the data field are as follows BYTE BIT i 7 34 6 5 3 4 3 i 2 t 1 i 00 Diagnostic Specifier 01 Diagnostic Option or Coded Release Level I 02 iLow Byte of Patch Starting Address or Qualifier 03 Patch Data Length 00 100h or Reserved 04 i Optional Patch Data N 3 Optional Patch Data The bit Diagnostic Specifier Byte 00 The specific function being reques Patch options 63h and 64h require a data block greater than 4 bytes 60h Re initialize Drive 61h Dump Hardware Area 4000 40FF Dump RAM 8000 80FF ted 62h 63h 64h 65h Patch Hardware Area Patch RAM Set Read Error Handling Options 3 23 8158 Diagnostic Option or Coded Release Level Byte 01 Th
24. 1 0 0 1 1 Logical Unit No Reserved Reserved i Reserved i Reserved i Control Byte Reserved 3 3 1 11 Read Buffer RAM Code 14h The READ BUFFER RAM command is used by the host to fill the Output Buffer with lk bytes of data for diagnostic purposes The bit pattern for WRITE DATA BUFFER Although data remains in the buffer after normal operations begin it is undefined until overwritten with sig nificant data BYTE BIT 00 01 02 03 04 05 The bit pattern for the READ BUFFER RAM is as follows E P y 5 O A 0v oe 0 i 0 0 0 1 0 1 0 0 iLogical Unit No Reserved Reserved i Reserved i Reserved Control Byte Reserved 3 3 1 12 Mode Select Op Code 15h The MODE SELECT command always precedes the FORMAT UNIT command it specifies the formatting parameters When the SENSE byte returns a blown format Error Code 1Ch MODE SELECT can be used to inform the WDC about the Drive infor mation The Drive should be backed up and reformatted bit significance for MODE SELECT are as follows 3 19 The bit pattern and 8158 00 01 02 03 04 05 4 71 52 2 5 q 1 2 1 3 0 0 011 0 1 0 1 Logical Unit No Reserved 1 Reserved Reserved Number of Bytes Control Byte Reserved Byte 04 of the MODE SELECT command specifies the number of information bytes to be passed with the comma
25. 100UF 75 20 6V CONN DIN FML 3X32 PRESS FIT 64 POS A amp C CONN HOUSING GUIDE DIN 3X32 100CTS ML CONN HDR 025SQ PCB 50POS RA W LG LTCH EJECTOR EURO DIN CONN STACK LATCH EURO DIN CONNECTOR STACK CATCH PCBA STACK CONTROLLER FASTENER PUSH ON 312 DIA STUD SOCKET IC DIP 4 LEAF CONT GOLD 20 POS B 31 REFERENCE x 5B 5H SJ 3K JL 5K 5G 4C 1D 3B 4L 4P 1 3 47 3N 3P 4H 4K 4M 4N 1K 1L 4D 1J 1M 1N 1P 2 3M 5L 2D 3C 3G 2K 1A 2F 2L 1B 2C 2H 3D 5D 3F 6E 3E 5F 2G 2J 3H 1F 1G 6D 2E 1H 4G 5E 4E AF R1 2 5C C3 32 C1 2 J1 2 J1 2 J3 J1 2 21 2 71 2 71 2 4 4E NO 0095 0096 0097 0100 0101 8158 Table B 6 Part 907649 001 List of Parts Sheet 2 of 2 PART NO 331014 005 152001 001 111000 029 907821 001 208000 001 DESCRIPTION SWITCH DIP SLIDE SPST AUTO INSERT 8SEC DIODE LIGHT EMITTING GREEN DIFF LENS RES CARBON 25W 5 330 COVER PLATE 1 2 STREAMER CONTROLLER RIVET BLIND 116DX 188L ALUM B 32 REFERENCE SW1 4B DS1 R3 J3 REFERENCE DESIGNATIONS LAST USED NOT USED e a x zz 2 ve Car m o Figure B 12 Part No 907649 001 Logic Diagram Sheet 1 of 15 B 33 M8158A ta 74528 lt a UE MI pj ren 1S LL eel Fe e EF mana
26. 1024 bytes long o Define Format bits lt 2 0 gt in the following combinations only Data bit lt 4 gt 1 0 0 0 Default 0 1 0 Format with data fill byte 6Ch 1 1 0 Use Cyl Head Byte Count format in data list 1 1 1 Use data pattern defined by FORMAT UNIT Byte 02 b Data Pattern Field Byte 02 lt 7 0 gt contains the defect list whose format is established by Byte 01 lt 2 0 gt above The list which is limited to 1024 bytes so it can fit into the available buffer space includes the physical coordinates of known media flaws in ascending order of cylinder head and bytes from Index 8158 3 16 If defects are not presented to the WDC in ascending order Bad Argument Error 24h is reported The following is the defect list format BYTE BIT 7 6 i 5 4 i 3 2 1 O 00 Reserved i 01 Reserved 02 1 MSB Length of Defect List in Bytes 8N 03 LSB i 04 MSB Cylinder Number of Defect 1 I 05 06 d Cylinder Number of Defect 1 LSB 07 Head Number of Defect 1 08 i MSB Bytes from Index 09 10 d 11 Bytes from Index 85 4 to i 8N 3 Nth Defect i Interleave Field Bytes 03 04 WDC does not require inter leaving because of its high speed buffer control 3 3 1 6 Read Op Code 08h The READ Command transfers to the DTC the specified number of blocks starting at the specified Logical Block Address The WDC veri
27. 1909 PETRAEA 6 5 1 4 Inch Winchester Disk Drive Controller Figure 1 1 M8158A SECTION 1 1 1 GENERAL The Winchester Disk Drive Controller WDC Figure 1 1 provides the means by which an BOSS IX system communicates with one or two 5 1 4 Winchester disk drives The controller is comprised of two functionally independent sections an Adapter section and a Controller section The adapter section provides an interface between the host s I O bus and the SCSI Small Computer Svstem Interface bus in the WDC In the current version of the WDC Part No 903496 the Adapter section and the Controller section are physically combined on a single PCBA printed cir cuit board assembly In the older version of the WDC Part No 903439 the SCSI Bus Adapter Part No 907649 is mounted piggy back style on top of the controller portion Either configuration allows the WDC to support one or two Winchester disk drives with disk capacities ranging from 10 to 190 megabytes Table 1 1 lists the 5 1 4 Winchester fixed disk drives that are supported by the WDC 1 2 DESCRIPTION 1 2 1 Single Board WDC The single board WDC consists of a PCBA which is designed for I O stack mount ing in the system housing 11 components are mounted on one side of the board and soldered except for the microprocessor and sequencer all PAL program array logic chips PROM and static RAM chips encoder decoder chips and buffer controller chip
28. 2 DMA and Interrupt Logic Tests The DMA and Interrupt arbitration logic is tested by first initiating a bus request by doing a dummy programmed I O WRITE to location CC0008 when DMA is enabled during the Bus Free Phase The CC00008 data is loaded into the Upper BOSS IX system Transceiver followed by the loading of the Lower BOSS IX system Transceiver The data is then transferred sequentially through the Upper and Lower SCSI Bus Transceivers to the SCSI Bus At the same time the Lower SCSI Bus Transceiver is being loaded the BOSS IX system is performing a programmed I O READ on the Upper SCSI Bus Transceiver Next another program med I O WRITE to location CC0008 is performed which causes the above cycle to be repeated The operation is repeated as many times as desired with the ad dress counters being incremented at the end of each DMA cycle 8158 4 2 4 2 3 WDC Adjustments Following a WDC repair procedure the WDC Data Separator must be adjusted as described in the paragraphs that follow 4 2 3 1 Test Equipment Required The recommended test equipment is as follows b 4 2 3 2 100 MHz dual channel oscilloscope Tektronix 465 or equivalent 50 MHz frequency counter 50 MHz function generator 0 5 DUM BOSS IX System to power up and reset the WDC board Data Separator Adjustment Verify that the jumper and switch setitngs are as specified in Sec tion 2 of this manual Apply power to the WDC bo
29. 3 3 2 Class 01 Commands Class 01 Commands are 10 byte commands that express additional Read Write in structions and Verify and Search instructions 3 3 2 1 CDB Class 01 Command Code Summary Table 3 3 lists the codes that are currently used for Class 01 commands M8158A Table 3 3 Class 01 Command Code Summary OP CODE COMMAND OP CODE COMMAND 25 READ CAPACITY 2E WRITE AND VERIFY 28 READ 2F VERIFY 2A WRITE 31 SEARCH DATA EQUAL 3 24 3 3 2 2 Class 01 Command Block Format Table 3 4 shows a typical Class 01 command descriptor format Table 3 4 Class 01 Command Block Format BYTE BIT 00 01 02 03 04 05 06 07 08 09 7 6 5 41 3 2 Class Code OpCode Logical Unit No Command Specific Bits 1 MSB Logical Block Address Logical Block Address J E O Logical Block Address i Loqical Block Address LSB Reserved Number of Blocks Number of Blocks Control Byte Reserved 3 3 2 3 Read Capacity Op Code 25h If CDB Class 01 Byte 08 is 00h the READ CAPACITY command will return the ad dress of the last block on the unit a starting address block is not If Byte 08 is 01 the READ CAPACITY command will return the ad dress of the block after the specified starting address at which a sub stantial delay in data transfer will be encountered such as a cylinder bound ary The block address and size of the data to be read are specified in the eight bytes 4
30. 7 BDI3 7 2014 7 BD 5 AB 3 T ABI4 I c9 Ald _OMAORM E AB 6 6 7 1 e AB 8 I o 19 1 b 20 J2 7 1 All 8 DMADRH 4812 I 42 J2 3 PUL t 21 1 an Zia 415 21 6 4B22 I 5 IBACK AB23 T 5 Figure B 10 Part 903439 001 Logic Diagram Sheet 8 of 13 MB158A B 24 at WC aaga OSY IWTEN T 5 SRST SRST jy 17 p RESET Lr rss 6 WRCTR Dit 7 E pi RM ati 07 7 6 ROCTR 7 5 DRBUS J2 us c irc C25 an DB O3 I 0807 EDODt _ o 0007 800 DBD R BD 2 T 2 IBACK 13 te D 30445 7 741509 20959 2 Bogor 8 7 _ EET T PDT BD008 7 78009 Dy2t BD 1p 22 5 ig 2T4 BDI2 5 EEL BDI3 g DY6 BD 4 5 E Na 8015 _ 7 jj 00 Figure B 10 Part No 903439 001 Logic Diagram Sheet 9 of 13 B 25 8158 S 1 DO 01 02 D3 05 Der 07 FUDR FLOR LLOR CCLK PUS WRSEL RESET ACKIN ACKOU7 SA27 J3 48 RtQ I 1 36 BUZY 1 MSG I 46 C DI sg OL PVOE 7 9 T ts DY D OY i 072 9 Oy 5 r 9 DY4 9 DY5 DYG _ 0 7 9 I Q 38
31. 8 I ABQ2 I AB 2 I e 8 8 e Ji ca 8 8 e ABDI I 3 PUS DOBYTE 2 RT J2 lt lt Im gt 0 14 1 i UR DNE 2 s 5 7 745 32 DMADRL 8 Kasse WRSEL CLRBER BAB3 5 BABI 5 RDCTR RDCILST PIOQUT RDAUXST 2 VECOUT 7 7 g RESET q5 9 DTACK E 5 A 45 At 5 DTACK 45 2 Figure B 12 8158 B 38 Part No 907649 001 Logic Diagram Sheet 6 of 15 72 iy 252 5 1 4 EUR E 12 772812 1 212 08 2 4 Iu L3 79 5B I Les Eo pod 4 7 19 6 c 26 9 1 17 29 8 1 8 Bl e W R 12 e _ 2L 2 0 E 74832 Q s DRBUS 74 504 744628 FUDR Figure B 12 Part No 907649 001 Logic Diagram Sheet 7 of 15 B 39 MB158A Jex gt 4 4 5 74832 744522 1 4 1 3 1732 WRVECT I el 2 6 WECOUT BD 5 80 4 8013 BDI2 EDI1 80124 8009 8048 PB DIR 80 7 802604 BOOS BOG4 80043 8002 800 8002 07 D 5 D4 03 22 ott 002 t 0 Q 9 99 0 MOM 919 9919999 N gt M IN CT hei 42 sS lt oM NNNSN x M N amp 090900 t 9
32. A 4 WDC to BOSS IX System Programmed DMA PAL State Diagram A 5 M8158A Table A 1 BOSS IX to Controller PAL Signal Listing CCLK DMAENA DRBUS LUDR PIOOUT OUT PIOINDL LLDR REQ BUSY DAT ACKIN BRQIN ACKOUT BRQIN FUDR FLDR PIOINM LDRF E VDRF E SBUSENA M8158A GND ENB SDATLAT SBUSENA UDRF FLDR LDRF FUDR PIOINM HOSTPIO VCC RQU OUT SATLAT PIOINM ACKOUT REQ DMAENA DAT SDATLAT REQ OUT DMAENA DAT REQ OUT UDRF LDRF BUSY DRBUS FLDR DRBUS BUSY BROIN DRBUS DMAENA DMAENA BUSY PIONDL UDRF SDATLAT DMAENA DAT BUSY OUT DRBUS HOSTPIO UDRF LDRF BUSY DRBUS SDATLAT UDRF LDRF SDATLAT DMAENA DAT BUSY OUT DRBUS HOSTPIO UDRF LDRF DRBUS BUSY SDATLAT REQ OUT ACKIN DMAENA DAT OUT DRBUS BUSY LDRF FLDR DAT BUSY DRBUS BUSY LDRF FLDR BUSY DMAENA DAT OUT DRBUS BUSY UDRF FUDR DAT BUSY DRBUS BUSY UDRF FUDR BUSY REQ OUT BUSY SDATLAT DMAENA DAT OUT BUSY SDATLAT FLDR BUSY PIOINDL BUSY LLDR LUDR 6 CCLK I BACK I ABXX I DRBUS AS DS R W DBXX I 31 MAX ADDRESS VALID 22 MAX DATA 15 EE Figure A 5 DMA WRITE Operation Timing Diagram A 7 8158 Figure A 6 WDC to BOSS IX System Programmed I O PAL Stat
33. DRBUS to signal completion although the actual trans fer of upper and lower byte data is not complete the HTC PAL continues transferring data until data transfer is complete o When the upper byte data transfer is completed UDRE goes TRUE to enable lower byte data transfer At the same time BRQIN goes FALSE to enable another DMA cycle This interaction results in the possible overlap of bus request BRQIN with the fetching of lower byte data 3 2 11 WDC to BOSS IX System Sequencing WDC to BOSS IX system sequencing is similar to BOSS IX system to WDC sequenc ing in that the activities are controlled primarily by PAL Sequencers Refer to the appropriate Appendix for detailed examination of sequencer operation Overall the following functions are involved with WDC to BOSS IX system se quencing operations o Set and reset SCSI Input Buffer empty status PIOUTF Set and reset Operation Complete status bit OPCOMP Direct fetch of data from the SASI Input Buffer into the upper or lower byte of the Data Registers Pack and load upper or lower byte of Data Register for transfer to host memory o Internal bus request to BOSS IX system interface o Provide diagnostic features O O 3 11 8158 WDC BOSS IX system sequencing is significantly different when data transfer from the controller to host is via DMA than when transfer is via I O bus The following paragraphs summarize the sequencing functions 3 2 11 1 Input Bu
34. G8 6TT 67921 68778 TL Carts n oede qao S Z WAA dAItKI dWeb MIN t 5 Ivnd S tb TWAA c9 SC 0c c9 SC 0c tS OV 07 0 0t S tv 99 9c 0c 99 97 0c OT S8 GL S9 v9 09 8 0T 98 6 TS Z T6T 06 T 6 OCT T SOT 06 ce S8 58 oven TW uuoJun OM ay3 Aq syioddng YSTA 3938909uIM T G T T TEL SALON 900715 500415 4700 02 0 TOZ coz SCET Vcet OCT Vott 06 2 0 OpIT SOTT 5801 1 2 MB158A JUMP 123 SINGLE BOARD WINCHESTER DISK CONTROLLER WDC DRIVE BUS ADAPTER E BUS 2 sIRIT Pu oru Jl pRIVE 1 20 7 ADAPTER j o BOARD 20 ADAPTER BOARD Loquo Figure 1 2 WDC PCBA Location of Major Components 1 3 8158 1 2 2 Two Board WDC The two board WDC consists of a PCBA containing the Controller section of the WDC which is mounted piggy back style onto the PCBA containing the Adapter section WDC consisting of both boards is mounted on the I O stack in the system housing All components of the boards are mounted on one side of the board and soldered except for the microprocessor and sequencer PAL program array logic chips PROM and static RAM chips and selected encoder decoder chips These ICs are socketed for ready exchange or replace ment additi
35. Lv 213 EEL T sig 22 4 THIS 2 2 6 2 8 I c2gVv sev 972 Izay 9 7 729 brv GND 2 2 ONS 2 HE T 2 OND ON 7 59 1212 8 H 12 2 S IOV 1 6 8V EFEK 112 8 b p T48V 7546 0529 0 2 g piy gt v 0 lt gt z Ft 62 ONT TFPI 8 elev a ON El 1 27 9 I i 8V 92 1 139398 OND 42 5 2 aN IED 22 3 7 lt 2 EE 1 829 652 8 1 708 E11 52 2 353 9 29 22 g 1 SQgv 5 2 ane 12989 cv lt gt I 298V 22 9 108 20 SGA 64 20 70195 INS dA wr INS EE 282 3 lt bib lt 3 lt gram Sheet 12 of 13 NIN SESSI lt lt lt lt N lt BS 28 Part No 903439 001 Logic D halls im Figure B 10 8158 J3 3 GND SD GND GND 19 3 a aS Id 5 30 mE 1p GND 32 503 L8 TN 2 34 SD4 1g GND BYSY I ano 1 58 500 2 15 40 E 207 16 END ano SELL ig 1 9 44 GND GN lt L ip ec GND REQ I 23 E ao GUD I OI EA 9 Figure B 10 Part 903439 001 Logic Diagram Sheet 13 of 13 B 29 8158 fU m 523 TEGO Ie CII wry
36. SPEC SER DESERIALIZER AIC 010 PROC SPEC ENCODE DECODE AIC 250 IC QUAD DIFFRNTL LINE RECIEVER 3486 IC QUAD DIFFRNTL LINE DRIVER 3487 IC 8 BIT NMOS MICROPROCESOR 8085A IC PROM 8K X 8 2764 300NS WDC FRMWRE A 22 REFERENCE 5K 1N 1P 5M 1R 1T 10 3R 3T 3U 3B 3H 2H SF 4T 4H 3F 1F 1H 1E 2E 4B 4C 5B 6A 6B 2F 3E 1 11 5 70 1 4R 3K 17 3 4K 4L 3J 6L 6K 6H 6F 7M 7N 5R SP REF NO 0068 0070 0071 0073 0074 0075 0076 0077 0078 0079 0080 0081 0082 0083 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 0100 0101 0105 0106 0107 0108 0109 0110 0111 0115 0116 0117 0123 0124 0125 0126 0127 0128 0130 0131 0132 Table A 10 Part No 903496 002 List of Parts Sheet 2 of 3 PART NO 162058 001 111000 095 111000 043 111000 048 111000 029 111000 051 111000 055 111000 031 111000 060 111000 063 111000 004 111000 071 111000 072 111000 054 116000 003 116000 175 116000 241 116000 156 116000 158 116000 183 116000 161 111000 045 111000 124 111000 052 118004 005 118004 009 101054 119004 004 101055 119017 004 151004 001 101336 155003 001 152001 001 130006 001 130028 001 103000 010 103000 009 103000 007 103000 008 103000 018 103000 012 104012 012 104010 001 102004 014 DESCRIPTION IC 2048 BIT STATIC RAM W I O PRT TMR RES RES RES RES CARBON 25W 5 51 CARBON 25W 5
37. Status Bit 7 are all asserted The host reads the Message byte which is always zero and has no significance and causes the WDC to return to the Bus Free Phase all control lines deasserted To initiate another command the WDC must be again selected and the six phased transaction is repeated M8158A 3 6 3 2 3 Completion Status Byte The Completion Status Byte indicates the results of the current transaction it is read by the host during the Status Phase The structure and the sig nificance of the Completion Status Byte are as follows BYTE BIT beet du Doo 5 che Ro p 00 I Reserved i BUSY EQUAL CHECK Resvd Bits lt 7 4 gt Reserved Always zero Bit lt 3 gt BUSY WDC is not ready and is unable to accept a command from BOSS IX system BUSY is always sent when a CHECK status Bit 1 set is returned Bit lt 2 gt EQUAL When set indicates Search Complete Bit lt 1 gt CHECK When set indicates a WDC error and that SENSE data is available To determine the type of error that occurred the host issues a REQUEST SENSE command which causes the appropriate Command Error Code to be issued refer to paragraph 3 2 4 Bit lt 0 gt Reserved Always zero 3 2 4 Error Sensing Setting the CHECK bit in the Completion Status Byte causes SENSE data to be made available for return to the BOSS IX system in response to a REQUEST SENSE Command BUSY is returned to the host The SENSE data is saved by the WDC un
38. failed from the start of the test to the point at which an error was detected The following logic is tested at power up 1 Microprocessor ALU Registers and Status Lines 2 Adapter Section Control Logic Arbitration Logic and Status Regis ters 3 SCSI Transceivers and Latches 4 Winchester and Bus Controllers and Buffers The WDC self test sequence is performed during the reset phase approximately one second long of a cold start or emergency power up sequence If the connected drive s is are not ready after the 20 second initialization timeout the drive parameter information is not read Failure of the self tests causes the Self Test Failed bit in a Class 01 Error Code to be set 4 2 2 System Diagnostics The WDC can be tested by the BOSS IX system by performing appropriate READ WRITE operations on the various I O data registers data buffers and data paths in the WDC Verify that the jumper and switch connections are as specified in Section 2 of this manual 4 2 2 1 Register and Buffer Tests These tests are executed by performing a programmed WRITE to location CC0008 in the Bus Free Phase with DMA disabled Data is routed through the Upper Output Data Register and the Output Buffer into the Input Buffer Next programmed READ operation to location CC0008 is performed Data is trans ferred from the Input Buffer through the Lower Input Data Register to the EBUS BOSS IX system monitors the results 4 2 2
39. handle all the BOSS IX system program I O to and from the WDC at odd byte addresses Bus Transceivers handle all program I O to and from the SCSI bus The input buffers are also used during DMA Read from Memory to allow overlapped operations the output latches buffer data during DMA Write operations to memory 3 1 2 Controller Section Functions The Controller section provides an intelligent interface between the internal SCSI bus and the ST 506 disk drive interface The primary control unit in the Controller section is the 8085 Microprocessor Microprocessor communi cates with the other logical elements in the Controller section over its own Microprocessor data bus The RAM element is a 1K FIFO first in first out RAM buffer which transfers DMA data and control signals between the Microproc essor bus and the SCSI bus RAM is protected from overflow or underflow of data by the Buffer Control circuit Through the RAM the Buffer Control recognizes arbitration logic on the SCSI bus and controls direct memory access of data out of the FIFO RAM Buffer Control also controls the flow of synchronous data to from the hard disk and the asynchronous SCSI interface through the dual port Winchester Controller circuit The Encoder Decoder includes the data separator functions needed to convert the MFM read data from the disk into a synchronized clock and NRZ data stream required by the SCSI bus Encoder Decoder also per f
40. of the SEEK Command is as follows BYTE BIT 5 TY 00 0 0 0 1 0 1 0 1 l i 01 Logical Unit No MSB Logical Block Address 02 dis Logical Block Address i 03 Loqical Block Address LSB 04 Reserved 05 i Control Byte Reserved 3 3 1 9 Translate Op Code OFh The TRANSLATE command translates a Logical Block Address LBA into a physical location and returns the physical address to the DTC in a cylinder head bytes from Index format If LBA is used to build a defect list for the FORMAT UNIT command eight bytes are required If there is a data error in the LBA field a CHECK status is returned in Completion Status It is then necessary to TRANSLATE the blocks before and after the targeted block to determine the location of the target block The bit pattern of TRANSLATE is as follows M8158A 3 18 BYTE BIT 00 01 02 03 04 05 goa dc do 39 ub bec 00 0 0 0 1 1 1 1 Logical Unit No MSB Logical Block Address elo i 1 I i 1 1 1 Logical Block Address i Logical Block Address LSB 1 1 1 Reserved i Control Byte Reserved 3 3 1 10 Write Data Buffer Op Code 13h The WRITE DATA BUFFER command is used by the host during diagnostics to fill the Input Buffer with 1K bytes of data is as follows BYTE BIT 00 01 02 03 04 05 5 1 58 i 0 0 0
41. seeks to alternate tracks Programmable logical addressing to access variable length 256 512 or 1024 byte blocks Self configuring on power up including reading and storing drive parameter data on Track 0 and copying and saving the largest block ad dress and defect counts o Multiple block data transfers and implied Seek by imbedding logical block addresses within the basic Read and Write requests o Host programmable disk parameters such as number of cylinders heads and sectors Sector interleaving and sector size as well as step type and rate are also programmable by the host o On the single board WDC Interrupt driven overlapped Seek operations which allows one drive to be available for use while the other is seek ing The Seek Complete interrupt can be enabled and disabled by host command 1 5 8158 1 5 SPECIFICATIONS Table 1 2 provides the specifications for the WDC Table 1 2 Winchester Disk Drive Controller Specifications PHYSICAL Width Single Board 8 8 Two Board Adapter 8 8 Two Board Controller 8 8 Depth Single Board 8 6 Two Board Adapter 8 6 Two Board Controller 8 6 1 6 RELATED PUBLICATIONS The following servicing documentation publication for the 5 1 4 Winchester O O ENVIRONMENTAL Operating Temperature 32 F to 122 F 0 C to 50 C gt Operating Humidity 20 to 80 non condensing ELECTRICAL Power 5VDC 5 12VDC 5 may be used in co
42. the 5 1 4 Inch Disk Drives This information is presented as an aid for field service personnel and supports the installation operation and maintenance of the Controller The major topics covered in this manual are Section 1 Introduction Section 2 Installation Section 3 Functional Description Section 4 Maintenance Section 5 Removal Replacement Appendix A Single Board WDC Maintenance Aids Appendix B Two Board WDC Maintenance Aids WARNING This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the in structions manual may cause interference to radio communications It has been tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules which are designed to provide reasonable protection against such interference when operated in a commercial environment Operation of this equipment in a residential area is likely to cause inter ference in which case the user at his own expense will be required to take whatever measures that may be required to correct the in terference The use of shielded I O cables is required when connecting unit to any and all optional peripheral or host devices Failure to do so may violate FCC rules ix 8158 r 9 lt 2 29 EE cose p gt t ns pt E xU eu Lee ar as ETE AD I C67 C68 Olu 1910 Exe irs ioe 3
43. 001 400569 003 400569 001 400569 002 161157 001 161158 001 162059 001 165053 005 M8158A DESCRIPTION PCBA 5 1 4 WDC CONTROLLER LABEL TAB 375X1 250 YEL IC 7438 BUFFER QUAD 2 INPUT NAND Ic 745132 QUAD 2 INPUT NAND SCHMITT TRIG IC 74 64 4 2 3 2 AND OR INV GATE IC 74F74 DUAL D TYPE FLIP FLOP IC 74LS02 QUAD 2 IN NOR IC 74LS27 TRIPLE 3 IN NOR GATE IC 74LS32 QUAD 2 IN OR IC 741574 DUAL D TYPE POS EDG TRIG F F IC 74LS123 DUAL ONE SHOT IC 74LS138 3 8 LINE DECODER DEMPLEX IC 74LS240 BUFF LINE DR 3 ST OCTAL IC 74LS244 OCTAL BUFFER LINE DRIVER IC 74LS273 OCTAL D TYPE FLIP FIOP IC 74LS373 OCTAL D TYPE LATCH 3 STATE IC 7415374 OCTAL REGISTER D TYPE F F IC 74F533 OCTL TRNSPRNT LATCH 3STATE IC 74LS648 OCTAL BUS TRNSRCVR REGISTER IC 74LS699 SYNC U D COUNT REG IC 74500 QUAD 2 INPUT POS NAND GATE IC 74802 POS NOR GATE TOTEM POLE IC 74508 QUAD 2 INPUT POS AND GATE 74511 3 INPUT AND IC 74832 QUAD 2 INPUT POSITIVE OR GATE IC 5 74538 QUAD 2 INPUT POS NAND BUFF IC SN74S74 DUAL D TYPE FLIP FLOP 745112 DUAL J K EDGE TRIG FLIP FIOP IC 748240 OCTAL BUFFER 3STATE TTL IC 745244 OCTAL BUFFER 5 745260 DUAL 5 INPUT POS NOR GATE IC 748138 DECODER DEMULTIPLEXER IC PAL FAST 20L8A 2ND WDC BUS ARBTRTN IC PAL FAST 20L8A WDC ADDRESS DECODER IC PAL FAST 20R6A WDC HOST CONT SEQ IC PAL FAST 20R6A WDC CONT HOST SEQ IC PAL HIGH SPEED 16RA INTERRUPT CTL IC STATIC RAM 2KX8 S LINE 150NS PROC SPEC IC DUAL PORT BFR CNT AIC 300 PROC
44. 07644 001 TWO DRIVE CABLE TO DRIVE 207633 001 TO J2 ONE DRIVE CABLE 907632 002 TO DRIVE 1 TO J1 TO DRIVE 0 307632 001 TO JO TO J2 J4 907635 001 OF ADAPTER DRIVE BUS ADAPTER 2 SIRIT PU orU 2 OF Jl DRIVE 1 2 ADAPTER 9 orive o SORRI 20 SW1 BUS ARBITRATION ADAPTER BOARD 1 CLOSED ON JUMPER CONNECTIONS PROG REDUCE WRITE CONNECT CURRENT CYLINDER FROM TO DRIVE 0 DRIVE 1 DRIVE 0 DRIVE 1 R T RODIME NONE 132 R T RODIME RODIME 132 132 R S RODIME MICROPOLIS 1300A 132 400 R U RODIME MAXTOR MICROP 1300B 1320 132 919 400 R S MICROPOLIS 1300A NONE 400 R S MICROPOLIS 1300A MICROPOLIS 1300A 400 400 R U MICROPOLIS 1300A MAXTOR 400 919 R U MAXTOR MICROP NONE 919 400 _ 1300B 1320 R U MAXTOR MICROP MAXTOR MICROP 1300B 1320 1300B 1320 919 400 919 400 NOTES 1 Drives 0 and 1 are for reference only That is if positions are switched so are the parameters in the appropriate columns 2 Jump position R U is equivalent to no jumper installed 3 1 drive models 1304A amp B and 1320 are used 4 Rodime drive models 204 203E and 240E are used 5 Maxtor drive models XT1140 and XT1105 are used Figure 2 2 Two Board Cable Jumper and Switch Connections M8158A 2 6 SECTION 3 FUNCTIONAL DESCRIPTION 3 1 GENERAL This section contains a functional description of the 5 1 4 Winchester Disk Controller WDC on three levels a general block diagram
45. 1 1 903496 002 JMP B amp C 1 1A 2A 1B 2B 1c 2c NOTES PCA SINGLE BOARD WINCHESTER DISK CONTROLLER WDC TO J4 TO J5 TO 93 907604 907604 001 002 TO TO TO DRIVE 0 DRIVE 1 DRIVE TO DRIVES JUMP A WDC BOARD ADDRESS CABLE 907605 001 907606 001 JMP A BOARD ADDRESS PAL LOCATION 1J 1 2 Hex 911017 001 2 3 CDXXXX Hex 911017 007 If one WDC is on the system bus it must be PCBA 903496 001 If two WDC s are on the system bus one must be PCBA 903496 001 and the other must be 903496 002 Combinations other than those shown are not allowed 1 2 3 4 JUMP B amp C WDC WRITE PRECOMDENSATION DRIVE TYPE Maxtor Micropolis 1300B 1320 Note 2 Rodine Note 3 Micropolis 1300A Note 4 JMP B controls drive 0 on the 001 assembly drive 2 on the 002 assembly JMP C controls drive 1 on the 001 assembly drive 3 on the 002 assembly Write precompensation always off Write precompensation always on Write precompensation on at and above the reduced write current cylinder Figure 2 1 Single Board Cable Jumper and Switch Connections 2 3 8158 2 3 TWO BOARD WDC 2 3 1 Unpacking Packing Instructions Each board of the two board WDC is shipped in an anti static bag inserted be tween two layers of styrofoam and sealed a cardboard shipping carton Un pack the WDC as follows 1 Prior to accepting the package from the carrie
46. 101714 101741 161062 001 101719 161064 001 161068 001 161023 161013 161065 001 168002 007 168012 001 161151 001 101315 101655 101615 101623 101625 101627 101629 101630 161009 161074 001 101637 101631 911017 001 911017 004 911018 001 911018 002 911003 008 162062 001 400569 003 400569 001 400569 002 161157 001 161158 001 162059 001 165053 002 DESCRIPTION PCBA 5 1 4 WDC CONTROLLER LABEL TAB 375X1 250 YEL IC 7438 BUFFER QUAD 2 INPUT NAND IC 748132 QUAD 2 INPUT NAND SCHMITT TRIG IC 74F64 4 2 3 2 AND OR INV GATE IC 74F74 DUAL D TYPE FLIP FIOP IC 74LS02 QUAD 2 IN NOR IC 74LS27 TRIPLE 3 IN NOR GATE IC 74LS32 QUAD 2 IN OR IC 74LS74 DUAL D TYPE POS EDG TRIG F F IC 74LS123 DUAL ONE SHOT IC 74LS138 3 8 LINE DECODER DEMPLEX IC 74LS240 BUFF LINE DR 3 ST OCTAL IC 74LS244 OCTAL BUFFER LINE DRIVER IC 74LS273 OCTAL D TYPE FLIP FLOP IC 74LS373 OCTAL D TYPE LATCH 3 STATE IC 74LS374 OCTAL REGISTER D TYPE F F IC 74F533 OCTL TRNSPRNT LATCH 3STATE IC 74LS648 OCTAL BUS TRNSRCVR REGISTER IC 74LS699 SYNC U D COUNT REG IC 74500 QUAD 2 INPUT POS NAND GATE IC 74502 POS NOR TOTEM POLE 74508 QUAD 2 INPUT POS AND GATE Ic 74S11 3 INPUT AND Ic 74532 QUAD 2 INPUT POSITIVE OR GATE IC SN74S38 QUAD 2 INPUT POS NAND BUFF IC SN74S74 DUAL D TYPE FLIP FLOP 745112 DUAL J K EDGE TRIG FLIP FLOP IC 74S240 OCTAL BUFFER 3STATE TTL 745244 OCTAL BUFFER 5 745260 DUAL 5 INPUT POS NOR
47. 1076 001 101631 161009 101637 161074 001 161006 101671 911006 009 911009 004 119001 002 119009 004 104010 001 108016 004 300092 001 310019 001 325003 061 907388 001 907769 001 907985 001 214027 001 325005 011 M8158A DESCRIPTION PCB BUS ADAPT 1 2 STREAMER CONTROLLER LABEL TAB 375X1 250 YEL Ic 7438 BUFFER QUAD 2 INPUT NAND 74LS00 QUAD 2 IN NAND 741502 QUAD 2 IN NOR 741 508 QUAD 2INP AND 741 504 HEX INVERTER 741514 HEX SCHMITT TRIGGER INVERTER 74LS51 DUAL 2 WIDE 2 IN amp OR INVERT SN748157 QUAD 2 1 LINEDATA SLCT MUX 74LS244 OCTAL BUFFER LINE DRIVER 741 5240 BUFF LINE DR 3 ST OCTAL 74LS273 OCTAL D TYPE FLIP FLOP 74LS374 OCTAL REGISTER D TYPE F F 74LS640 OCTAL BUS TRANS INV 3 STATE 74LS699 SYNC U D COUNT REG 74500 QUAD 2 INPUT POS NAND 74802 POS NOR GATE TOTEM POLE 74S11 3 INPUT AND 74532 QUAD 2 INPUT POSITIVE OR GATE 5 74538 QUAD 2 INPUT POS NAND BFFR 74508 QUAD 2 INPUT POS AND 74564 4 2 3 2 INPUT AND OR INV GATE SN74S74 DUAL D TYPE FLIP FIOP 748112 DUAL J K EDGE TRIG FLIP FLOP 745133 13 INP NAND 748138 DECODER DEMULTIPLEXER 745240 OCTAL BUFFER 3 STATE TTL SN74S260 DUAL 5 INPUT POS NOR GATE 74S244 OCTAL BUFFER 745374 OCTAL D TYPE FLIP FLOP 745280 9 BIT ODD EVEN PARITY GEN PAL SCSI TAPE ADAPT CONT HOST SEQR PAL WDC HOST CONTROLLER SEQUENCER RES NIWK SIP 8 PIN 7 RES 1 0K OHM RES NTWK DIP 16 PIN 28 RES 220 330 OHM CAP CERAMIC 250 AXL 10 80 20 50V CAP ALUM ELECT
48. 18 Write Data Buffer Op Code 13h 3 19 Read Buffer RAM Op Code 14h 3 19 Mode Select Op Code 15h 3 19 Mode Sense Op Code 1Ah 3 21 Start Stop Op Code 1Bh 3 22 Receive Diagnostic Result Op Code 1Ch 3 22 Send Diagnostic Op Code 1Dh 3 23 Class 01 Commands 3 24 CDB Class 01 Command Code Summary 3 24 CBD Class 01 Command Block Format 3 25 Read Capacity Op Code 25h 3 25 Read Op Code 28h vise s xia iere REC 28265 Write Op Code 2A 555545 455 lt 545 5 453 26 Write and Verify Op Code 2Eh 3 26 Verify Code 2Fh 3 1 26 Search Data Equal Op Code 31h 3 26 4 gt CO CO CO CO CO CO CO CO CO CO CO CO CO GO CO CO CO CO CO CO CO CO CO CO CO GO CO CO CO CO CO CO CO GO GO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO WW CO CO CO CO N FO e 4 FP t 2 S F gt e e NF NNN FO N IO FO FO FO jp IB P RP RPE ES ES IE ES ES E M O Qn No gt gt e e e F gt O OND t F gt Om WHF 4 MAINTENANCE Preventive 4 1 Corrective 4 4 Power U
49. 5 1 4 Winchester Disk Drive Controller Service Manual June 1987 008158 001 MA BasicFour M8158A Status Table of Contents Preface Section 1 Section 2 Section 3 Section 4 Section 5 Appendix A Appendix B PAGE STATUS iii iv V through viii ix x through 1 8 2 1 through 2 8 3 1 through 3 28 4 1 through 4 4 5 1 through 5 2 A 1 through A 38 B 1 through B 48 111 iv June June June June June June June June June June 1987 1987 1987 1987 1987 1987 1987 1987 1987 1987 M8158A e e N OY gt O 2 FO NN e e N N FO S IS 2 N N 2 FO FO FO FO FO N N FO N FO N P FF e a s e e e e PREP RPO 1 O O G O 0 iO tH o C2 N F gt e gt CON W CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO TABLE OF CONTENTS Page INTRODUCTION Generals tics veuve Hele SHS y eee PCBA DESCFIDELON 6 3 etic neues x Wax Tek ue Single Board uu ruo lo Two Board WDC sees ee ee 2 eee Kee eek Adapter Section 1 4 Controller Section d E PE 5 Speci r icat ONS
50. 6 Class 00 Command Block 3 13 Class 00 Command Code 23 14 CDB Class 01 Command Code Summary 3 23 Class 01 Command Block 2 24 BOSS IX System to WDC PAL Signal 1 BOSS IX System to WDC PAL State 10 Address PAL and Arbitration PAL Signal Listing A 11 Microprocessor Memory and I O Addressing Map A 13 BOSS IX System I O Bus EBUS Interface Signal Descriptions 44529409 4 edison vro id SCSI Interface Signal 15 Drive Interface Signal 16 List of WDC Mnemonics 117 Part No 903496 001 List of Parts 3 Sheets A 19 f Part No 903496 002 List of Parts 3 Sheets ecsocoosoo 22 BOSS IX System to WDC PAL Signal 6 BOSS IX System I O Bus EBUS Interface Signal Descriptions 452 55 5522655 55 44 55 4 e BLL SCSI Interface Signal 12 List of WDC Mnemonics B 1 Part No 903439 001 List of 15 Part No 907649 001 List of Parts B 31 This manual provides service information for the Winchester Controller for
51. 8 001 103000 010 103000 009 103000 007 103000 008 103000 018 103000 012 104012 012 104010 001 102004 014 MB158A DESCRIPTION IC 2048 BIT STATIC RAM W I O PRT TMR RES CARBON 25W 5 51 RES CARBON 25W 5 100 OHM RES CARBON FIIM 25W 5 220 OHM RES CARBON FIIM 25W 5 330 OHM RES CARBON FILM 25W 5 390 OHM RES CARBON FILM 25W 5 680 OHM RES CARBON FIIM 25W 5 1K OHM RES CARBON FILM 25W 5 4 7KOHM RES CARBON FILM 25W 5 10K OHM RES CARBON FILM 25W 5 75K OHM RES CARBON FILM 25W 5 100K OHM RES CARBON FILM 25W 5 1 0K OHM RES CARBON FILM 25W 5 620 OHM RES METAL FIIM 125W 1 511 OHM RES METAL FIIM 125W 1 1 10K OHM RES METAL FIIM 125W 1 1 02K OHM RES METAL FIIM 125W 1 1 65K OHM RES METAL FIIM 125W 1 1 96 OHM RES METAL FILM 125W 1 2 67K OHM RES METAL FIIM 125W 1 3 09K OHM RES CARBON FIIM 25W 5 150 OHM RES CARBON FIIM 25W 5 430 OHM RES CARBON 25W 5 470 OHM I POT SQ CERMET 5W MULT POT SQ CERMET 5W MULTI RES NTWK 8 PIN SIP 220 RES NTWK SIP LP 10PIN 9 RES 1 0K OHM RES NIWK 8 SIP 330 OHM TURN 2 0K OHM TURN 50K OHM RES NIWK SIP C C 10 PIN 9 RES 2 2K OHM CRYSTAL PARALLEL RESONANCE 6 0MHZ 30PF CRYSTAL FUND 10 000MHZ 005 IC DELAY LINE 10 TAPS 100 OHMS 100NS DIODE LIGHT EMITTING GREEN DIFF LENS DIODE SWITCHING 1N914B DIODE VAPACTOR HIGH CAP 400 500PF CAP MICA DIPPED RADIAL 51PF 5 500V CAP MICA DIPPED RADIAL 10PF 5 500V CAP MICA DIPPE
52. CLK 3 PUS OYI 6 WASEL YO 093 9 DY4 DYS 9 DY a 7451 2 DY 7 9 0 MI Pas e 77 5 o SRESET 19 12 u AC K IN 7 3 7 ACK OUT SEL 44 ues 705 5 20 EDITT RENE ml 48 REO 3 Z MAS 36 BuSY I BUSY 42 454 e Tere T m C DI 9 8 0 daa LETT 5 745280 0 1 5 SDP 18 SDP INPARERR 745240 919 SDPAR 15 3L 3 4 508 Figure B 12 Part No 907649 001 Logic Diagram Sheet 10 of 15 MB158A B 42 4 2 52401 7 l BERR gt 12 BERRY I 5 Puce 242592 3 Auer LLRBER e RESET 4 Mec 92 QEN t 792598 PAL 76 AUSY FUDR c D 1 FLOR ORBUS 2 DATLAT ACK IN b PIOIN e K JIBRQ 3 2 741500 PAL REQ T 6 LLOR DOBYTE ACK OUT 0007 3 PUO Bb4d 804 8002 RO GAY RE 8004 MS G Pr UG ROCTLST m Figure B 12 Part No 907649 001 Logic Diagram Sheet 11 of 15 8158 B 43 5 5 2 9 2 amp RDAUAST Figure B 12 Part No 907649 001 Logic Diagram Sheet 12 of 15 8158 B 44 00909 AR NAAA an 3 3 oly mima oleo xS x gt Six xxx lt lt lt lt lt ix 4424 885 5 WOON Ouan 00 9 9
53. D RADIAL 18PF 5 300V CAP MICA DIPPED RADIAL 150PF 5 500V CAP MICA DIPPED RADIAL 330PF 5 100V CAP MICA DIPPED RADIAL 270PF 1 500V CAP CERAMIC COG AXIAL 6800PF 5 50V CAP CERAMIC 250 AXL 1UF 80 20 50V CAP SOLID TANTALUM RDAL 4 7UF 20 35V A 20 REFERENCE 5U R1 R14 20 26 33 36 37 R22 24 27 R4 5 23 25 35 R21 R3 R39 R31 R2 38 R34 R10 11 30 R42 R15 R16 R19 R32 RP6 C65 66 C67 68 69 C61 C58 C63 C71 C3 48 52 56 57 59 60 62 C53 54 55 72 NO 0133 0134 0140 0141 0142 0145 0150 0151 0160 0161 0162 0163 0164 0165 0170 0171 0174 0175 0176 0177 0178 0179 0180 0181 0182 Table A 9 Part No 903496 001 List of Parts Sheet 3 of 3 PART NO 102000 001 108016 004 140005 001 140028 001 141022 001 135041 001 132016 001 132015 001 300092 001 310019 001 907388 001 907769 001 907985 001 214027 001 300032 016 300032 009 325005 011 325005 012 325005 007 325005 010 325005 001 700023 300032 002 325026 003 325033 001 DESCRIPTION CAP SOLID TANTALUM AXIAL 15UF 10 20V CAP ALUM ELECT 100 UF 75 20 TRANS NPN GEN PURP 2N3904 CASE TO 92 TRANSISTOR NPN LOW VOLT SILICON SW TRANS PNP 2N5771 INDUCTOR 2 2UH SHIELDED 10 78L05 3TERM FIX 5 0 POS VOLT REG IC 79L05 3TERM FIX 5 0V NEG VOLT REG CONN DIN FML 3X32 PRESS FIT 64 POS A amp C CONN HOUSING GUIDE DIN 3X32 100CTS ML EJECTOR EURO DIN CONN STACK LATCH EURO DIN CONNECTOR STACK CATC
54. DUAL D TYPE POS EDG TRIG F F IC 74LS138 3 8 LINE DECODER DMLTPLXR IC SN74S157 QUAD 2 1 LINEDATA SLCT MUX IC 74LS244 OCTAL BUFFER LINE DRIVER IC 74LS240 BUFF LINE DR 3 ST OCTAL IC 74LS273 OCTAL D TYPE FLIP FLOP IC 74LS374 OCTAL REGISTER D TYPE F F IC 74LS640 OCTAL BUS TRANS INV 3 STATE IC 74LS697 SYNC U D BINARY COUNTER IC 74500 QUAD 2 INPUT POS NAND GATE 74502 POS NOR GATE TOTEM POLE IC 74S11 3 INPUT AND 74532 QUAD 2 INPUT POSITIVE OR GATE IC SN74S38 QUAD 2 INPUT POS NAND BFFR IC 74508 QUAD 2 INPUT POS AND GATE IC 74S64 4 2 3 2 INPUT AND OR INV GATE 5574574 DUAL D TYPE FLIP FLOP IC 745112 DUAL J K EDGE TRIG FLIP FIOP IC 748133 13 INP NAND IC 748138 DECODER DEMULTIPLEXER IC 748240 OCTAL BUFFER 3 STATE TTL 5 745260 DUAL 5 INPUT POS NOR GATE IC 745244 OCTAL BUFFER IC PAL WDC CONTROLLER HOST SEQUENCER IC PAL WDC HOST CONTROLLER SEQUENCER RES NTWK SIP C C 8 PIN 7 RES 1 0K OHM RES NTWK 16 PIN 28 RES 220 330 CAP CERAM 250 AXIAL 1UF 80 20 50V CAP ALUM ELECT 100UF 75 20 6V CONN DIN FML 3X32 PRESS FIT 64 POS A amp C CONN HOUSING GUIDE DIN 3X32 100CTS ML CONN HDR DBL ROW 100CTS 025SQ 50 POS EJECTOR EURO DIN CONN STACK LATCH EURO DIN CONNECTOR STACK CATCH PCBA STACK CONTROLLERS FASTENER PUSH ON 312 DIA STUD SOCKET DIP 4 LEAF CONT GOLD 20 POS SWITCH SLIDE SPST AUTO INSERT 85 B 15 REFERENCE 5 SH SJ 3K 3L 5K 5 4C 1 3H 3B 4L 4
55. E x gt 2 T MANN mE RESET RESET 48 ESET I 45231011 gt ASF 5 e 27521 ma r ar 1G Rs 12 DTACK T gt gt 5 Q K E 2 PU 5 03 gt gt K 45 RE MES 1p 2 gt DTACK 4 5 5 QRBUS IE Figure B 10 Part No 903439 001 Logic Diagram Sheet 6 of 13 MB158A B 22 9 0814 1 uf 2 2 24 A 6 n D813 1 13 La aJl EC ey EA 2 1 208 2 1 4 EJ GG Bl L3 1111 19 28 1 5 2 2 jg DB 0 r W R e MYDTACK 5 1 WRVECT 2 00 28805 7 FUDR AH 17 12 7 2L D 2 74832 3 13K 742692 18 4 1 3 i 1 8 1 1 q 3 4 o ED dar oo 74832 Q 741504 74L 08 H Ld 30 5 BD 4 8013 BDI2 8017 8012 8009 80284 DBDIR 8007 8000 8005 8004 8003 8002 BOO 8000 07 D G 05 04 23 02 Dit DOr Figure B 10 Part No 903439 001 Logic Diagram Sheet 7 of 13 8158 23 OOH amp Ho 9 19 vO 9 00 M 90 tt OOOO 9 99 XO 49 Sls SSS M BDOQ 7 809 J2 8002 ABOI 5 003 7 B004 8 2 1 75 7 8095 7 BODO 48 3 1 15 ET AB I AB I I 5 22 6 DMADRL 7 8008 7 8009 2 BDId 7 BDII 7 80 2
56. GATE IC 748138 DECODER DEMULTIPLEXER IC PAL FAST 20L8A WDC BUS ARBITRATION IC PAL FAST 20L8A WDC ADDRESS DECODER IC PAL FAST 20R6A WDC HOST CONT SEQ IC PAL FAST 20R6A WDC CONT HOST SEQ PAL HIGH SPEED 16RA INTERRUPT CTL IC STATIC RAM 2KX8 S LINE 150NS PROC SPEC IC DUAL PORT BFR CNT AIC 300 PROC SPEC SER DESERIALIZER AIC 010 PROC SPEC IC ENCODE DECODE AIC 250 IC QUAD DIFFRNTL LINE RECIEVER 3486 IC QUAD DIFFRNTL LINE DRIVER 3487 IC 8 BIT NMOS MICROPROCESOR 8085A IC PROM 8K X 8 2764 300NS WDC FRMWRE A 19 REFERENCE 5K 1N 1P 5M 1R 1T 1U 3R 3T 3U 3B 3H 2H SF 4T 4H 3F 1F 1H 1 2 4 4 5B 6A 6B 2F 3E 1 11 5 70 M8158A REF NO 0068 0070 0071 0073 0074 0075 0076 0077 0078 0079 0080 0081 0082 0083 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 0100 0101 0105 0106 0107 0108 0109 0110 0111 0115 0116 0117 0123 0124 0125 0126 0127 0128 0130 0131 0132 Table A 9 Part No 903496 001 List of Parts Sheet 2 of 3 PART NO 162058 001 111000 095 111000 043 111000 048 111000 029 111000 051 111000 055 111000 031 111000 060 111000 063 111000 004 111000 071 111000 072 111000 054 116000 003 116000 175 116000 241 116000 156 116000 158 116000 183 116000 161 111000 045 111000 124 111000 052 118004 005 118004 009 101054 119004 004 101055 119017 004 151004 001 101336 155003 001 152001 001 130006 001 13002
57. H PCBA STACK CONTROLLERS FASTENER PUSH ON 312 DIA STUD CONN HDR DBL ROW 100CTS 025SQ 34POS CONN HDR DBL ROW 100CTS 025SQ 20POS SOCKET DIP 4 LEAF CONT GOLD 20POS SOCKET DIP 4 LEAF GOLD 24POS 300 SOCKET IC DIP 4 LEAF CONT GOLD 28POS SOCKET DIP 4 LEAF CONT GOLD 40POS SOCKET IC DIP 4 LEAF CONT GOLD 24POS TAPE DOUBLE SIDED 50 WIDE CONN HDR DBL ROW 100CTS 025SQ 6POS CONN HDR SGL ROW 100CTS 025SQ 3POS JUMPER 0 025 SQ 0 100 CENTERS GOLD PL A 21 REFERENCE C49 50 70 C1 2 Q1 Q2 3 Q4 L3 VR2 VR1 J1 J2 71 22 J3 J4 J5 3J 1J 3M 4K 4L 5 SR SU 6H 6K 6F X1 Y2 JUMP B C JUMP A JUMP A B amp C MB158A REF NO 0001 0003 0005 0010 0011 0012 0014 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0050 0051 0052 0053 0054 0060 0061 0062 0063 0064 0065 0066 0067 Table A 10 Part No 903496 002 List of Parts Sheet 1 of 3 PART NO 905019 001 762022 003 101514 168014 001 168000 006 168000 008 101710 101781 101714 101741 161062 001 101719 161064 001 161068 001 161023 161013 161065 001 168002 007 168012 001 161151 001 101315 101655 101615 101623 101625 101627 101629 101630 161009 161074 001 101637 101631 911017 007 911017 004 911018 001 911018 002 911003 008 162062
58. Hal 3isgs 5 mc 4NIBN3WIA Pi sig 0 13834 FINO 158 e e 37 31v SN VIVI YA WIW 6 aag 94 6i m 27 ecu 01 WI 9 ea 7 eas iene a m 20v 12 689 ov z L9 31v5A 9 zS 0 944 9 6 L sa 6 D Gib gt 59 0 I ug E 29794 9 7393 Cae VS 92 i136ud 2 125 OH 70 135 GH 081 ns L r 21 oc 2918 H H M er 9 MIT 40oumu yan in Lens j VERI RIT ERA PSE g yT OT 8 IX NI 3W 2417 gram Sheet 9 of 12 tic Dia Part No 903496 Schema Figure A 10 M8158A 33 1 2119 ce IUM 22 ca 7100155 69 112 45 ale 4 e 8 4794 9 24 e s 9 6 e e Za 9 iG 29 44 gt 9 1 A WO c 4 2 595 ZEST ELE SID 20 gt w T as T 9 e Te q gi amp 82 6109 INL 735 1535 sei w Part No 903496 Schematic Diagram Sheet 10 of 12 Figure A 10 34 8158 WO4Vovgd3e viva 6 Diagram Sheet 11 of 12 Schematic Part No 903496 MB158A A 35 t Qend pul ONnOW
59. IDE CONN HDR DBL ROW 100CTS 02550 6POS CONN HDR SGL ROW 100CTS 025SQ 3POS JUMPER 0 025 SQ 0 100 CENTERS GOLD PL A 24 Part No 903496 002 List of Parts Sheet 3 of 3 REFERENCE C49 50 70 C1 2 01 02 3 04 L3 VR2 VR1 J1 J2 J1 J2 13 74 25 37 1J 3M 4K AL 5P SR SU 6H 6K 6F Y1 Y2 JUMP B C JUMP A JUMP A B amp C Top pp SE EEE po pos TT WEINE ES Savas Renan Coveney Rear EE Le 1 5 ee Tee ZT Tor gt BESS ee pee rt or PASI RET SONS p GAS ASH 25 438 po er DESEE hae p 994 a po m 242 GO Q3sn LON 035 1541 SNOILVNDIS3Q 32N3uH34338 1N334502 UIAM 0220035 Sv d3Q0N 12 3wrS dWO23Nd 31 54 J 2 aJownr 6 B NOILVSN3HW723Xd FLIM Y3H XXYXO2 X JH XXXX22 200 26 7100 96 EQF SIFY V SND 567 00 Qavog win eie JI o U Qtuinoxyo SI05YH7 27991 I WHO M32 pein 16183 EHS wim 9 4 lt lt lt 1 lt lt m rn npo Sia SA 0919 ro L amp 9i I 2 inim DS ws RARER qu Si N RSESESESE 2 2 6
60. IT OBh SEEK 1Ch RECEIVE DIAGNOSTIC 1Dh SEND DIAGNOSTIC 3 3 1 2 Test Unit Ready Op Code 00h The TEST UNIT READY Command returns zero status if the requested unit is turned on and ready If not ready a Check condition will be set in the Com pletion Status Byte and the appropriate Error Code is set in the Sense Byte described later The possible Sense Errors are Drive Not Ready 04h and Write Fault 03h normal bit pattern for the TEST UNIT READY Command is as follows BYTE BIT E Oh A MS MM 2 1 0 00 mE 0 0 0 0 0 i 01 0 0 0 Reserved 02 NAT Reserved 03 Reserved 04 Reserved 05 Reserved 3 3 1 3 Rezero Unit Op Code 01h The REZERO UNIT Command sets the selected drive to Track 0 then sends Comple tion Status Possible Sense Errors are No Seek Complete 02 Drive Not Ready 04h No Track Zero 06h normal bit pattern for the REZERO UNIT Command is as follows BYTE BIT Zo B 700 094 4 3 SD 1 Oe 1 00 0 0 0 0 0 0 0 _ 1 01 i 0 0 0 1 Reserved i 02 LL Reserved 03 Reserved m 04 Reserved 05 Reserved 3 15 M8158A 3 3 1 4 Request Sense Op Code 03h The REQUEST SENSE Command is issued by the host when the CHECK bit is set in the Completion Status Byte which is sent to the host at the end of each Com mand cycle Refer to paragraphs 3 2 4 through 3 2 6 for a discussion of the Error Sensing information exchange betw
61. MA PAL State Diagram A 5 DMA WRITE Operation Timing 7 WDC to BOSS IX System Programmed I O PAL State Diagram A 8 WDC to BOSS IX System Programmed DMA PAL State Diagram 9 Interrupt PAL State Diagram and Signal Listing A 12 Part No 903496 001 Parts Location Diagram A 18 Part No 903496 001 Schematic Diagram 12 Sheets A 25 BOSS IX System to WDC Programmed I O PAL Timing Diagram B 2 BOSS IX System to WDC Programmed I O PAL State Diagram B 3 BOSS IX System to WDC Programmed DMA PAL Timing Diagram B 4 WDC to BOSS IX System Programmed DMA PAI State Diagram B 5 WDC to BOSS IX System Programmed I O PAL Timing Diagram B 7 WDC to BOSS IX System Programmed I O PAL State Diagram B 8 WDC to BOSS IX System Programmed DMA PAL Timing Diagram B 9 WDC to BOSS IX System Programmed DMA PAL State Diagram B 10 Part No 903439 001 Parts Location Diagram B 14 Part No 903439 001 Logic Diagram ee eee e e s B 17 Part No 907649 001 Parts Location Diagram B 30 Part No 907649 001 Logic 33 vii 8158 Table eoo i Q2 h gt gt CO 2 I gt poo o 7 8 A 9 A 10 B 1 B 2 B 3 B 4 B 5 B 6 M8158A LIST OF TABLES Page 5 1 4 Winchester Disk Drives Supported by the WDC 1 2 Winchester Disk Drive 1 1
62. N N NEN sc ses LLL 20 74574 n se 5289 0 ee LUE a sa 24804 9 n oz su 791800 sr 74522 e ol fac soo 5 E B N LIL B 34 A EE 7 AN NN x Part No 907649 001 Logic Diagram Sheet 2 of 15 5V Figure B 12 Part No 907649 001 Logic Diagram Sheet 3 of 15 B 35 M8158A 3 J BPR2 Cit BPR e 6 CCLK 5 HMATCHY n CCLK 3 PU 2 w MY RN 5 D7ACK TACK e e D8 12 NYECT g 7 6 Figure B 12 No 907649 001 Logic Diagram Sheet 4 of 15 M8158A B 36 4 J 42 P 2F p 2e 2 BAB 74538 BAB t 1 5 e d2E e TACK 3 124 7245220 i 7 A17 74538 LEES 2 07 12 HINTR E Li 8 18407 rm C L e o gt 0 HMATCH 4 I I RID BG6eNT I 6 CCLK 3 PUII 5 D7ACK 2eg827 HU MYTURN e IACK 6 5 BACKE JI BACK ITA 2 I8AcK 7 BACK e Figure B 12 Part No 907649 001 Logic Diagram Sheet 5 of 15 B 37 8158 PU 482 1 482 ABI7 I AB e ZI 5 BACK AB25 I 822 1 48 9 1 AB
63. P 1E 3J 4J 3N 3P 4G 4H 4K 4M AN 1K 1L 4D 1J 1M 1N 1P 2C 2H 3D 5D 3E 5F Table B 5 Part No 903439 001 List of Parts Sheet 2 of 2 REF NO PART NO DESCRIPTION REFERENCE 0096 152001 001 DIODE LIGHT EMITTING GREEN DIFF LENS CR1 0097 111000 029 RES CARBON FILM 25W 5 3300HM R3 0098 216021 004 STANDOFF INS 62L SNAP IN 0099 907634 001 ASSY DC PWR WDC BUS ADAPTOR WDC 8158 16 BECCONSNE E e UHR ENS SE 252 ssvr sve 6 ano z vFizv sv 2 jot e te _ i ee E usc dd EGRE BES ses qam pocas p p qan Figure B 10 Part No 903439 001 Logic Diagram Sheet 1 of 13 8158 B 17 Jajaja 78564 Le pst III mE o aes 5 L7 7415240151515 5 LEM lee e e ee pu ea ze seep s 5 7 22 74538 5 5 5 lt 26 24535 22 7as7e 27 7415138 22 arl asse e e 7 7 z 74504 7 e a Exe B FUN MEC 22 7415097 s IE M
64. ROR I D ADDRESS MARK NOT FOUND DATA ADDRESS MARK NOT FOUND RECORD NOT FOUND SEEK ERROR NOT ASSIGNED NOT ASSIGNED Class 02 Error Codes INVALID COMMAND ILLEGAL BLOCK ADDRESS NOT ASSIGNED 26 2F NOT ASSIGNED 3 8 The codes are as follows 03 WRITE FAULT 04 DRIVE NOT READY 06 NO TRACK ZERO 18 19 1 1B 1 1 1 1 Error Codes are system related errors 23 24 25 Error Codes are target data related errors The codes are as DATA CHECK IN NO RETRY MODE ECC ERROR DURING VERIFY INTERLEAVE ERROR NOT ASSIGNED UNFORMATTED OR BAD FORMAT ON DRIVE SELF TEST FAILED DEFECTIVE TRACK MEDIA ERRORS NOT ASSIGNED The codes are as follows VOLUME OVERFLOW BAD ARGUMENT INVALID LOGICAL UNIT NUMBER 3 2 7 Power UP Reset When power is applied the WDC enters a 10 to 20 second 10 seconds per drive power up sequence Once the drive s come s ready the WDC reads driver parameter information for Track 0 including block size and drive type data If a Software Reset is received the power up sequence is the same ex cept the 20 second timeout is reduced to 200 milliseconds sirice the drives are assumed to be at speed The drive parameter information is not read if a drive is not ready after timeout instead a WDC command must be issued to that unit excluding the TEST UNIT READY command to initiate reading other drive parameters In a cold start the WDC recalibrates the head to Track 0 by introd
65. S IS IN THE MESSAGE PHASE REQUEST TO REQUEST BYTE FROM ADAPTOR OR TO INDICATE THAT DATA ON BUS IS STABLE ACK OUT ACKNOWLEDGE TO INDICATE TO CONTROLLER THAT ADAPTOR HAS ALREADY TAKEN A BYTE OR THAT DATA ON THE BUS IS STABLE RST OUT RESET TO FORCE THE CONTROLLER INTO AN IDLE STATE SEL OUT SELECT TO INITIATE A COMMAND TRANSACTION SD7 to IN OUT 8 BIT DATA BUS USED TO TRANSFER COMMANDS SD0 AND DATA A 15 M81 Table 7 Drive Interface Signal Descriptions SIGNAL IN OUT DESCRIPTIONS RWC OUT REDUCED WRITE CURRENT SIGNAL TO WRITE ON DISK WITH A LOWER WRITE CURRENT WGATE OUT WRITE GATE SIGNAL ENABLES WRITE DATA TO BE WRITTEN ON THE DISK SKCOMP IN SEEK COMPLETE SIGNAL TRUE WHEN R W HEADS HAVE SETTLED ON FINAL TRACK 0 TRACK ZERO SIGNAL TRUE R W HEADS HAVE SETTLED ON TRACK ZERO WELT IN WRITE FAULT INDICATES CONDITION EXISTS WHICH CAUSES IMPROPER WRITING INDEX IN INDEX SIGNAL INDICATES THE BEGINNING OF A TRACK DRDY DRIVE READY INDICATES THAT DRIVE READY TO READ WRITE SEEK AND VALID I O SIGNALS STEP OUT STEP CONTROL LINE WHICH CAUSES R W HEADS TO MOVE DRSELX OUT DRIVE SELECT SIGNALS CONNECT DRIVES TO INTERFACE LOGIC HDSELX OUT HEAD SELECT SIGNALS TO SELECT HEADS IN A BINARY CODED SEQUENCE DIRIN OUT DIRECTION IN DEFINES DIRECTION OF HEAD MOVEMENT WDATXX OUT MFM DIFFERENTIAL WRITE DATA 8158 16 SIGNAL NAMES AB01 23 ACKIN ACKOUT BACK
66. T IN OUT BOSS IX System I O Bus EBUS Interface Signal Descriptions DESCRIPTIONS 23 BIT ADDRESS BUS ADDRESS STROBE TO INDICATE ADDRESS ON THE ADDRESS BUS IS STABLE BUS GRANT ACKNOWLEDGE TO INDICATE BUS CONTROL IS BEING TRANSFERRED BUS GRANT TO INDICATE GRANT THE BUS FROM 68000 UP BUS ERROR TO INDICATE ABNORMAL CONDITION ON THE HOST BUS BUS REQUEST TO INDICATE ADAPTOR IS RE QUESTING USAGE OF BUS BUS PRIORITIES ENCODED PRIORITY ADDRESS USED TO RESOLVE PRIORITIES BY BUS MASTER CPU CLOCK 16 BIT DATA BUS USED TO TRANSFER COMMANDS AND DATA DATA TRANSFER ACKNOWLEDGE ACKNOWLEDGING TRANSFER OF DATA FROM SLAVE INTERRUPT ACKNOWLEDGE ACKNOWLEDGING AN INTERRUPT REQUEST BY 68000 UP SYSTEM RESET USED TO RESET ADAPTOR CON TROLLER LOGICS DURING POWER UP OR RESET FROM 68000 UP READ WRITE TO INDICATE DIRECTION OF DATA FLOW BY THE MASTER ON THE BUS FUNCTION CODE TO INDICATE STATUS OF 68000 UP LOWER DATA STROBE TO INDICATE TRANSFER OF THE LOWER 8 BIT DATA BUS UPPER DATA STROBE TO INDICATE TRANSFER OF THE UPPER 8 BIT DATA BUS 14 Table A 6 SCSI Interface Signal Descriptions SIGNAL IN OUT DESCRIPTIONS I O IN IN OUT TO INDICATE FLOW DIRECTION OF IN FORMATION ON THE SCSI BUS C D IN COMMAND DATA TO INDICATE WHETHER INFORMA TION ON THE BUS IS COMMAND OR DATA BUSY IN BUSY TO INFORM ADAPTOR THAT CONTROLLER IS READY TO CONDUCT TRANSACTIONS MSG IN MESSAGE TO INDICATE THAT SCSI BU
67. WDC MOST CONT BF18D PART NUMBER 632036 RAM PART NUMBER 911008 004 LOCATION 4F CCLK susY REO 7 DAT ENABLE DRBUS DATLAT PIOIN OND 1 1 ACKIM FLDR UDRE FUDR SROIN PREPET VCC PREFET ENABLE PREFET BROIN 9U8Y REOS UORE LDREe PREFETe DRBUBe ACKINe BRGINSENABLE OUT e DAT REQ PIOIN FUOR ACKIM ENABLE PIOIN BUSY ENABLE LDRE FLDR LDRE BUSY ENABLE DRBUS UDRE 7 6 FUDR e ENABLE DAT PIOIN e REO UDRE ENABLE e DRBUB BUSY FUDR ENABLE BUBY LDRE UDRE ENABLE BUSY FLDR REQ ENABLE DAT UDRE LDRE ACKIN FLOR ENABLE BUSY ACKIN PIOIN BUGY ENABLE LORE FLDR ENABLE QUT DAT REO LORE ENABLE DRBUS BUSY DRDUS BUSY ENABLE LORE FLOR e BUSY 9 8 4948 44 8 ACKIN REG 9 DATLAT REQ DATLAT BUSY e REQ PREFET ENABLE OUT e DAT REQ UDRE LDRE s OUT DAT ACKIN ENABLE BROIN DRBUS ENABLE PIOIN ENABLE 8USY PREFET 6 BROIN PIOINN REQ OUT ACKIN PAL16R6 MASTER PAL SCSI TAPE CONT HOST BFISD PART NUMBER 532094 RAW PART NUMBER 91 1004 009 LOCATION 4E CHECKSUM 6ADC CCLK ausy REQ OUT IDAT ENABLE DRBUS MSO PIOOUT ONO PIOUTF ACKOUT DOBYTE LLDR UORF LUDR ZBRQOUT OPCOMP vece PIOUTF ACMOUT ENABLE PIOOUT
68. agram A 5 WDC to BOSS IX System Programmed I O PAL State Diagram A 6 WDC to BOSS IX System Programmed DMA PAL State Diagram A 7 WDC to BOSS IX System PAL Signal Listing A 2 Address PAL and Arbitration PAL Signal Listing A 3 Interrupt PAL State Diagram and Signal Listing A 8 Microprocessor Memory and I O Addressing Map A 4 BOSS IX System I O Bus EBUS Interface Signal Descriptions A 5 SCSI Interface Signal Descriptions A 6 Drive Interface Signal Descriptions A 7 List of WDC Mnemonics A 8 Part No 903496 Parts Location Didra A 9 Part No 903496 001 List of Parts 3 Sheets A 9 Part No 903496 002 List of Parts 3 Sheets A 10 Part No 903496 Schematic Diagram 12 Sheets A 10 NOTE The PAL state diagrams and equations in this appendix are provided for reference purposes only and will not be maintained A 1 8158 DTACK I BDX SYNBDSEL MYDTACK WRXXX SDATLAT SELPIO 8158 Figure 1 BOSS System WRITE Timing Diagram A 2 CCLK I AS DS R W DBXX I BDSEL MYDTACK RDXX SYNBDSEL SELPIO 50 51 52 53 54 SW SW S5 S6 57 50 51 N li MAX EC MAX VALID DATA J pnt a JSE Figure A 2 BOSS IX System READ Timing Diagram A 3 MB158A Figure A 3 BOSS IX System to WDC Programmed I O PAL State Diagram M8158A 4 word BRQIN 1 BUSY DMAENA DAT OUT UDRF LDRF DRBUS BUSY IDLE STATE Figure
69. ard Reset the WDC board through a manual hard reset or soft reset Th soft reset can be executed by loading WDAFS and using command CC Provide a TTL signal at pin 7C 10 with a period fo 400 ns The duty cycle can be approximately 50 Adjust pot R32 for a positive pulse width of 250 ns 5 at pin 7C 5 11 Ground pin 6C 2 Adjust R19 for a VCO frequency of 10 MHz 1 at TP3 Use counte for this measurement Remove ground from 6C 2 4 3 MB158A 8158 4 4 SECTION 5 REMOVAL REPLACEMENT There are no specific removal replacement procedures for the WDC The PCBA is removed the same as any other PCBA When installing the WDC observe the cor rect jumper and DIP switch settings and the correct card placement in accord ance with instructions in Section 2 of this manual 5 1 8158 MB158A 5 2 APPENDIX SINGLE BOARD WDC MAINTENANCE AIDS The following Programmed Logic Array PAL information interface data parts list data and logic diagrams for the single board WDC part number 903496 are provided to aid in clarifying the operation of the WDC and assist in the maintenance of the PCBA INFORMATION FIGURE TABLE BOSS IX System WRITE Operation Timing Diagram 1 BOSS IX System READ Operation Timing Diagram A 2 BOSS IX System to WDC Programmed I O PAL State Diagram A 3 WDC to BOSS IX System Programmed DMA PAL State Diagram A 4 BOSS IX System to WDC PAL Signal Listing A 1 DMA WRITE Operation Timing Di
70. bytes for Block Address 4 bytes for Block Size in bytes of necessary the Data Field returned as a result will return a CHECK status with an Error Code of 24h Invalid Argument bit pattern for the READ CAPACITY command is as follows BYTE BIT 00 01 02 03 04 05 06 07 08 09 4 1 Loqical Block Address LSB Reserved Reserved 7 0 Logical Unit No Reserved Rel Add MSB Logical Block Address Iogical Block Address i Logical Block Address Control Byte Reserved 61 5 404 3 2 1 0 0 1 0 1 0 0 1 1 1 1 Full or Partial Media Indicator 3 3 2 4 Read Op Code 28h The READ command for Class 01 operations is the same as for Class 00 opera tions described in paragraph 3 3 1 6 3 25 byte value other than 00h or 01h The MB158A 3 3 2 5 Write Op Code 2A The WRITE command for Class 01 operations is the same as for Class 00 opera tions described in paragraph 3 3 1 7 3 3 2 6 Write and Verify Op Code 2Eh The WRITE AND VERIFY command for Class 01 operations is similar to the WRITE function for Class 00 in that data is written in the specified number of blocks 64K for Class 01 256 for Class 00 In this command the written data is then verified block by block data is transferred to the host hence correctable data checks are treated the same as uncorrectable data checks The bit pattern for the WRITE AND VERIFY command is as follows
71. bytes have been loaded into the Input Data Register controller to host PAL monitors the DMA cycle and causes DRBUS to go FALSE to signal completion although the actual transfer of data is not complete the PAL continues transferring data until loading is com plete 8158 3 12 3 2 12 Diagnostic Features The BOSS IX system can test the WDC by appropriate READ WRITE operations to the various I O data registers data buffers and data paths through the PAL Sequencers on the board The testable areas are Interrupt Vector Register Control Register Status Register EBUS I O Data Register SCSI Interface I O Data Buffers DMA and Interrupt Logic 3 2 12 1 Register and Buffer Tests The registers and buffers are tested by performing a programmed WRITE to loca tion CC0008 in the Bus Free Phase with DMA disabled Data is routed through the Upper Output Data Register and the Output Buffer into the Input Buffer Next a programmed READ operation to location 0008 is performed Data is transferred from the Input Buffer through the Lower Input Data Register to the EBUS The BOSS IX system monitors the results 3 2 12 2 DMA and Interru ic Tests The DMA and Interrupt arbitration logic is tested by first initiating a bus request by doing a dummy programmed I O WRITE to location CC0008 when DMA is enabled during the Bus Free Phase CC0008 data is loaded into the Upper BOSS IX system Transceiver followe
72. cord is removed before opening the Base Unit cover 2 1 M8158A 8158 Shut down the system turn the Base Unit off and remove the power cord To prepare the MAI 2000 system insert a screwdriver or similar device into the slot at the bottom right hand side of the Base Unit cover and push in to disengage the plastic latch Repeat for the left hand latch and remove the cover To prepare the MAI 3000 system perform the following a Remove the CCA front panel by using a screwdriver to disengage two captive screws at the bottom and then pulling from the bot tom If device controller boards memory boards or drives are to be installed remove the side panels also b The side panels slide forward for easy removal It may be helpful to insert the tip of a flat blade screwdriver between the front flange of the panel and the frame about midway down the panel carefully twist the blade to disengage the panel from the frame Remove the drive cables connected to board connectors J3 J4 and J5 see Figure 2 1 for connector locations Prepare the replacement WDC board for installation by installing the appropriate jumpers and setting the dip switches as indicated in Figure 2 1 Replace the Base Unit cover by lowering the cover onto the Base Unit and allowing it to snap into place Reconnect the power cord Follow the instructions in the propriate BOSS IX System User Guide for operating the host system 2 2 0 903496 00
73. d Offset 05 First Record Offset 06 First Record Offset 07 i First Record Offset LSB 08 MSB Number of Records 09 Number of Records 10 i Number of Records 11 i Number of Records LSB i 12 MSB Search Argument Length 13 i Search Argument Length LSB 14 MSB Search Field Displacement 15 Search Field Displacement 16 i Search Field Displacement 17 i Search Field Displacement LSB i 18 MSB Pattern Length 19 Pattern Length LSB 20 MSB Data Pattern 19 5 Data Pattern LSB Record Size Field Bytes 00 03 Bytes specified must equal _blocksize or zero the format block size o First Record Offset Field Bytes 04 07 Field must be zero o Number of Records Field Bytes 08 11 Number of blocks must be more than zero and equal to or less than the number of blocks specified in the SEARCH command SEARCH terminates upon a match or when the specified block size is reached o Search Argument Length Field Bytes 12 13 Number of bytes in the SEARCH argument must pattern length 6 o Search Field Displacement Field Bytes 14 17 Must be zero o Pattern Length Field Bytes 18 19 Number of bytes specified in the following Data Pattern to be compared with an equal size field in each record o Data Pattern Field Bytes 20 M 19 Variable length field of M bytes where M block size MB158A 3 28 SECTION 4 4 1 PREVENTIVE MAINTENANCE Maintena
74. d by the loading of the Lower BOSS IX system Transceiver The data is then transferred sequentially through the Upper and Lower SCSI Bus Transceivers to the SCSI Bus At the same time the Lower SCSI Bus Transceiver is being loaded the BOSS IX system is performing a programmed I O READ on the Upper SCSI Bus Transceiver Next another program med I O WRITE to location CC0008 is performed which causes the above cycle to be repeated The operation is repeated as many times as desired with the ad dress counters being incremented at the end of each DMA cycle 3 13 M8158A 3 3 DETAILED DESCRIPTION OF COMMAND DESCRIPTION BLOCK The Command Description Block CDB is a series of 8 bit command words which define the character of the I O request made by the DTC to the WDC The words are transmitted to the WDC one byte at a time all bytes must be transmitted to complete a command At the end of the command the WDC returns a Comple tion Status Byte which is read by the host during the Status Phase Class 00 CDBs are 6 byte commands Class 01 CDBs are 10 byte commands In each class the first byte 00 contains the Class Code and the Operation Code Depending upon the value of this byte the remaining 5 or 9 bytes contain the Logical Unit Number Logical Block Address and the Number of Blocks that may be trans ferred under a single command Class 01 CDBs also contain a field of Command Specific Bits The following definitions apply to the f
75. description a dis cussion of the system interface characteristics and a detailed functional description of the WDC circuits Figure 3 1 is a functional block diagram of the WDC showing the relationship of the Adapter section and the Controller section to the circuit elements with which they are involved As indicated the basic internal interface is the SCSI Small Computer System Interface bus The 8 bit parallel SCSI bus hand les all communication between the Adapter and the Controller sections NOTE The MAI 3000 system does not support the two board WDC 3 1 1 Adapter Section Functions The Adapter section provides an intelligent interface between the BOSS IX system I O bus and the SCSI bus internal to the WDC Primary bus control and interrupt priority are determined by the DMA and Interrupt Arbitration logic which performs parallel arbitration with up to 16 other device controllers that may be connected to the I O bus Through this logic and the Control Logic circuit the WDC responds to a Level 2 interrupt with 0 being the highest with a priority level which is lower than that of Memory Refresh LAN controller or 4 Way controller in the system PAL Program Array Logic devices are used in the Arbitration and Control circuits as well as in other circuits such as sequencing interrupt acknowledge addressing status and overall control circuits to establish logical patterns The Address and Bus Control unit determines if the WDC
76. e Diagram MB158A A 8 LLDR 0 LODR 0 SBUSENA 0 SBUSENA 0 0 1 lag LDRIN i H to LLDR Wait for data to SBUAENA 1 be latched into Piour SEUSENA 1 Load into PIOUTE SREGIN LDRE Load into UDRIN LDRE OUT HOSTPIO IDLE STATE Figure 7 WDC to BOSS IX System Programmed DMA PAL State Diagram A 9 MB158A Table 2 WDC to BOSS IX System PAL Signal Listing CCLK DMAENA DRBUS FUDR PIOOUT OUT PIOINDL FLDR MSG BUSY DAT GND ENB REQ OPCOMP SDATLAT LLDR ACKOUT LDRE LUDR BRQOUT PIOUTF HOSTPIO VCC ACKOUT SDATLAT PIOOUT REQ OUT ACKOUT REQ DMAENA DAT REQ OUT SDATLAT PIOUTF DMAENA DAT REQ OUT SDATLAT BRQOUT LLDR DMAENA DAT DRBUS BUSY BROOUT DRBUS DMAENA BUSY LUDR DMAENA DAT OUT BRQOUT DRBUS PIOUTF BUSY OPCOMP LDRE HOSTPIO LLDR LDRE PIOUTF DRBUS OUT BUSY BRQOUT DMAENA DAT OPCOMP HOSTPIO PIOUTF REQ OUT SDATLAT ACKOUT PIOUTF LUDR LLDR DMAENA DAT OPCOMP REQ OUT DAT MSG BRQOUT LDRE LUDR LLDR BUSY DMAENA LDRE LLDR BUSY DMAENA SDATLAT REQ OUT PIOUTF SDATLAT REQ FUDR DAT OUT DMAENA BUSY FLDR DAT OUT DMAENA BUSY SDATLAT ACKOUT DMAENA DAT OUT BUSY FUDR BUSY FLDR BUSY PIOINDL M8158A A 10 Table 3 Address PAL and Arbitration PAL Signal List
77. e WDC a series of Command words byte by byte The Com mand words are defined by the Command Description Block CDB format to be described later Bit 1 PIOINM goes TRUE high when the Adapter Output Register is empty and FALSE when full Command bytes cannot be sent via DMA o Information Transfer Phase Depending upon the CDB values data may be transferred between the BOSS IX system and the WDC either via DMA or via programmed I O as discussed in the paragraphs that follow 1 SEQEN Control Register Bit 3 TRUE data transferred via DMA Data transfer takes place at a Microprocessor controlled rate 2 SEQEN FALSE CMD Status Bit 7 held TRUE asserted data is transferred via programmed I O as follows o When PIOINM Status Bit 1 is asserted Input Buffer full host writes data to Output Register Address cc0008 o When PIOUTF Status Bit 3 is asserted Output Buffer full host reads data from Input Register Address 000 o Status Phase Status Phase is entered when CMD Status Bit 7 and PIOUTF Status Bit 3 and OPCOMP Status Bit 2 are asserted If host interrupts are enabled INTEN Control Register Bit 2 is TRUE the host is interrupted if not OPCOMP is monitored by the host to determine command completion status See paragraph 3 2 3 for a discussion of the Completion Status Bytes Message Phase The Message Phase occurs after the Status Phase is read PIOUTF Status Bit 2 MSG Status Bit 5 and CMD
78. e cass cot as a am ala Jaa aasia ala ala a z Z wl Z i aS 1412 Sizi S gt Z gt gt Z gt gt hi 5 nha Jin c 2 d d amp ole x 3 I rers m 7 TT 5 AIS aS hg Z 215 Q ALAS EE ER ERE EE EE BEBE 4161414141 Figure A 10 Part No 903496 Schematic Diagram Sheet 12 of 12 8158 36 NOTES 8 57 8158 NOTES 8158 58 APPENDIX TNHO BOARD WDC MAINTENANCE AIDS The following Programmed Logic Array PAL information interface data parts list data and logic diagrams for the WDC Controller Part No 903439 001 and SCSI Bus Adapter Part No 907649 001 are provided to aid in clarifying the operation of the WDC and assist in the maintenance of the PCBAs INFORMATION BOSS IX System to WDC Programmed I O PAL Timing Diagram BOSS IX System to WDC Programmed I O PAL State Diagram BOSS IX System to WDC Programmed DMA PAL Timing Diagram WDC to BOSS IX System Programmed DMA PAL State Diagram BOSS IX System to WDC PAL Signal Listing WDC to BOSS IX System Programmed I O PAL Timing Diagram WDC to BOSS IX System Programmed I O PAL State Diagram WDC to BOSS IX System Programmed DMA PAL Timing Diagram WDC to BOSS IX System Programmed DMA PAL State Diagram BOSS IX System I O Bus EBUS Interface Signal Descriptions SCSI Interface Signal Description
79. e subtest or qualifiers specific to the test selected by Byte 00 not checked if the 65h option code is specified Low Byte of Patch Starting Address Byte 02 Starting address in RAM or the memory mapped registers to be patched high byte is im plicit in the specified diagnostic Note A Patch RAM operation with a third byte of Alh will overwrite an area of RAM starting with 80A1h Patch Data Length Byte 03 Number of bytes to be overwritten from 1 to 256 bytes 0 256 ECC Options Field Byte 02 Specifies the actions to take place upon encountering a ECC check of Option 65h is selected for the Logical Unit Number addressed by the command Default state is es tablished by WDC Reset and remain in effect until next Reset Set Read Error Handling Options Data Block Option Byte 65h Value 00 Selects default options where a correctable error is corrected without comment and all data transferred without CHECK status If the error is not correctable the WDC transfers the uncorrected data and set CHECK status with an Error Code of 91h The Valid Address is that of the bad block Value 01 Report all corrections and stop correctable error will be corrected and the data transferred but the operations will stop with a CHECK status and Error Code of 98h An uncorrectable error is handled as in 00 above Value 02 Do not correct All ECC errors will be treated as uncorrectable except that the Error Code is set to 98h
80. een the DTC and WDC which results 3 3 1 5 Format Unit Op Code 04h The FORMAT UNIT Command formats all sectors with ID and data fields in accord ance with the selected interleave factor The WDC writes from index to index the ID and data fields with block size as specified by an immediately preceding MODE SELECT Command If no MODE SELECT Command has been executed the block size from the previous block data is used On unformatted or bad format disks SENSE 1Ch following a READ Command a MODE SELECT Command is required prior to the FORMAT UNIT Command Unless otherwise specified in the FORMAT UNIT Command data fields are completely written with 6Ch The command structure and significance of the fields are as follows BYTE BIT 2 75 a 3 00 i 0 0 0 0 0 1 0 0 01 iLogical Unit No Data iCmplt List Format Bits 02 Data Pattern 03 MSB Interleave 04 I Interleave MSB 05 Control Byte Reserved Block Field Byte 01 lt 4 0 gt Specifies the format of the bad block list for defect skipping o Data bit lt 4 gt is set to alert the WDC that a list of bad areas is forthcoming and that defect skipping is to take place if bit is not set formatting is accomplished with no user sup plied data o Complete List bit lt 3 gt is set to specify that all of the known defects on the drive are contained in the bad block list which must be less than
81. er empty See Adapter Data Phase and Command Phase Bit 2 OPCOMP Operation Complete See Adapter Status Phase Bit 3 PIOUTF Input Data Register Full See Adapter Status Phase and Message Phase Bit 4 SRESET SCSI bus in Reset state Bit 5 MSG SCSI bus in Message Phase Bit 6 BUSY SCSI bus BUSY Bit 7 CMD SCSI bus in Command Status or Message Phase Address 000 Host Selects WDC The host selects the Controller by writing to this address the presence of data is indicated by a logical 1 Refer to the paragraphs that follow concerning bus transaction phases Address 000 Host Read Input Register During the Information Transfer Phase the host reads the Input Register to determine if the register is full or if data is expected Refer to the paragraphs that follow concerning bus transaction phases o Address 000 Host Clears Bus Error Latch The Bus Error signal is latched if it occurs during WOC bus mastership All DMA transfers are halted and control of the SCSI bus is released The latch remains set TRUE until cleared by the host If interrupts are enabled a host interrupt is generated 3 2 2 WOC Transaction Communication between the BOSS IX system and the WDC is controlled by a six phase transaction which is initiated by the host The transaction is in itiated when the host selects the WDC Upon being selected the WDC contends for bus mastership with the other DMAs connected to the host Up
82. escriptions DESCRIPTIONS IN OUT TO INDICATE FLOW DIRECTION OF IN FORMATION ON THE SASI BUS COMMAND DATE TO INDICATE WHETHER INFORMA TION ON THE BUS IS COMMAND OR DATA BUSY TO INFORM ADAPTER THAT CONTROLLER IS READY TO CONDUCT TRANSACTIONS MESSAGE TO INDICATE THAT SASI BUS IS IN THE MESSAGE PHASE REQUEST TO REQUEST A BYTE FROM ADAPTER OR TO INDICATE THAT DATA ON BUS IS STABLE ACKNOWLEDGE TO INDICATE TO CONTROLLER THAT ADAPTER HAS ALREADY TAKEN A BYTE OR THAT DATA ON THE BUS IS STABLE RESET TO FORCE THE CONTROLLER INTO AN IDLE STATE SELECT TO INITIATE A COMMAND TRANSACTION 8 BIT DATA BUS USED TO TRANSFER COMMANDS AND DATA B 12 SIGNAL NAMES AB01 23 ACKIN ACKOUT BD0 15 BERR BG BACK CCLK CLRBER DATLAT DB00 15 DBDIR DMADRL DMADRM DMADRH DRBUS DTACK ENVECT FC2 FLDR M8158A Table B 4 List of WOC Mnemonics DESCRIPTION EBUS ADDRESS BUS BITS 01 THROUGH 23 ACKNOWLEDGE DATA IN TO CONTROLLER ACKNOWLEDGE DATA OUT FROM CONTROLLER BUFFERED DATA BITS 0 THROUGH 15 EBUS BUS ERROR EBUS BUS GRANT EBUS BUS GRANT ACKNOWLEDGE HOST CPU CLOCK CLEAR BUS ERROR LATCH DATA LATCH EBUS DATA BUS BIT 00 THROUGH 15 DATA BUS DIRECTION LOAD LOWER DMA ADDRESS REGISTER LOAD MIDDLE DMA ADDRESS REGISTER LOAD HIGHER DMA ADDRESS REGISTER DRIVE EBUS EBUS DATA TRANSFER ACKNOWLEDGE ENABLE VECTOR ONTO EBUS EBUS FUNCTION CODE BIT 2 FETCH FROM LOWER BYTE OF DATA REGISTER B 13 Figure B 9
83. f the SENSE byte will be reported The Address Valid bit in the SENSE byte will be set 1 address of the block containing the first matching record will be reported in the Information Bytes in the SENSE byte Following an unsuccessful SEARCH terminating in an inequality the following is reported o A Error Code of 00 NO SENSE is sent provided there are no other er rors The Address Valid bit in the SENSE byte is not set 0 The bit pattern and significance of the SEARCH DATA EQUAL command are as follows BYTE BIT 00 01 02 03 04 05 06 07 08 09 7 28 4 5 1 4 b 2 1 1 0 0 1 I 0 0 0 Logical Unit No iInvrti Reserved MSB Logical Block Address ical Block Address Logical Block Address Logical Block Address LSB Reserved Number of Blocks Number of Blocks Control Byte Reserved qe oam a Invert Byte 01 lt 4 gt Inverts the sense of the search comparison op eration With Invert ON the first block not equal will return a matching response also SEARCH DATA HIGH and SEARCH DATA LOW returns would be reversed 8158 b The argument following a SEARCH command is as follows BYTE BIT 7 6 5 4 3 i 2 1 i O0 00 MSB Record Size i 01 Record Size i 02 Record Size 03 Record Size LSB i 04 MSB First Recor
84. ffer Empty Status The Input Buffer Empty status bit PIOUTF is set if the WDC requests a byte of data and ACKOUT has not been returned to acknowledge host acceptance PIOUTF is set for DMA mode and when ACKOUT goes TRUE the host clocks data into the Input Buffer upper bytes first PIOUTF is reset when ACKOUT is set and is polled by the host to determine DMA transfer activity 3 2 11 2 Operation Complete Status The OPCOMP bit in the Control Register Word is set when the WDC enters the Status Phase and issues the Status Completion Byte The BOSS IX system may accept the completion byte through the Status Register or wait for an inter rupt if interrupts are enabled 3 2 11 3 Direct Loading of Data Direct loading of data into the Input Data Register is accomplished in one of two ways o If SEQEN is FALSE data transfer is via programmed I O message or data bytes are loaded from the SASI bus into the Lower Input Data Register Command and status bytes are always transferred by programmed I O o If SEQUEN is TRUE low a DMA cycle with full handshake between the WDC to BOSS IX system is initiated Data is transferred from the Input Buffer upper byte first Loading of the lower data byte enables the next bus request there is no overlap of bus request and loading of data 3 2 11 4 Generating Internal Bus Requests In a DMA cycle an internal bus request BRQOUT with full handshaking is gen erated after both upper and lower
85. fies that the Seek Ad dress is valid and causes a Seek to the specified address When Seek Complete occurs the WDC reads the starting address data field into the buffer checks ECC and begins DMA data transfer Data transfer continues until the block count is decremented to zero ON a data ECC error the block is re read up to five times before correction is attempted Correction is done directly into the data buffer transparent to the host The bit pattern of the READ Command is as follows BYTE BIT 06 f 5 2 1 1 41 00 0 0 0 0 1 0 0 0 1 01 Logical Unit No MSB Logical Block Address 02 Logical Block Address i 03 Logical Block Address 04 Reserved i 05 Control Byte Reserved 3 3 1 7 Write Op Code 0Ah The WRITE Command transfers to the target drive the specified number of blocks starting at the specified Logical Block Address The WDC verifies that the Seek Address is valid and Causes a Seek to the specified starting block When Seek Complete occurs the WDC transfers the first block into its buffer and writes its buffered data and its associated ECC into the first logical sector Subsequent data blocks are transferred as available from the FIFO buffer until the block count is decremented to zero 3 17 M8158A The WDC also supports extended READ and WRITE Commands using the Class 01 format described later The bit pattern of the WRITE Command is as f
86. he BOSS IX system main memory as follows 32 megabytes on the single board WDC 2 megabytes on the two board WDC o Control logic which provides the appropriate interface between the BOSS IX system I O bus and the controller s SCSI bus logic starts DMA or Interrupt cycles when necessary and handles packing and unpacking of the data transferred between the 16 bit I O bus and the internal 8 bit bus M8158A 1 4 1 4 CONTROLLER SECTION FEATURES The Controller section consists of a daisy chained control bus and a radial data bus The control bus handles all the control functions of the disk drive controller interface primarily in the form of 5 volt DC control signals The radial data bus handles read and write MFM data in the form of differential signals Write precompensation can be set for either Drive 0 or Drive 1 by means of jumpers on the PCBA In a two board controller write precompensation is NOT individually selectable for each drive Also precompensation may be set to be always on always off or enabled at and beyond the reduced write current cylinder using the jumpers Overall operations performed by the Controller section include Support for standard SCSI commands including a high speed data search command dual ported lk byte data buffer for rapid data transfers with no sec tor interleaving required O Transparent to the host disk defect handling No spare tracks are re quired eliminating long
87. ields specified in Tables 3 1 and 3 2 o Class Code Can be 0 to 7 only 0 and 1 used at this time Operation Code 32 commands allowed for each class 00h thru 1Fh o Logical Unit Number Up to eight devices per Controller WDC allows only two 00 for Drive 0 and 01 for Drive 1 Logical Block Address Class 00 commands contain 21 bit starting block addresses o Number of Blocks Variable number of blocks may be transferred under a single command Class 00 256 blocks 00 value defaults to maximum value o Control Byte Last byte reserved must be zero 3 3 1 Class 00 Command Descriptions Class 00 Commands are 6 byte commands which typically express Read Write in structions Table 3 1 shows a typical Class 00 command descriptor format Table 3 1 Class 00 Command Block Format BYTE BIT 6 5 4 3 1 2 1 0 00 Class Code OpCode 01 Logical Unit No MSB Logical Block Address 02 Logical Block Address 03 Logical Block Address I Number of Blocks 05 i Control Byte Reserved 8158 3 14 3 3 1 1 Class 00 Command Code Summary Table 3 2 lists the codes that are currently used for Class 00 Commands Table 3 2 Class 00 Command Code Summary OP CODE COMMAND OP CODE COMMAND 00h TEST UNIT READY TRANSLATE 01h REZERO UNIT 13h WRITE BUFFER 03h REQUEST SENSE 14h READ BUFFER 04h FORMAT UNIT 15h MODE SELECT 08h READ 1Ah MODE SENSE 0Ah WRITE 1Bh START STOP UN
88. ing PAD1 PAD2 17 16 LDS SBUSENA AS WRITE IBACK UDS GND FLDR FUDR DBDIR CKENVECT ENVECT SCSIOUT BDSEL ENAUDR ENALDR SELPIO SNBDSEL VCC BDSEL PAD1 PAD2 AS AB17I 16 KO SBUSENA FUDR FLDR PADI PAD2 AS AB17I AB16I KO SBUSENA SCSIOUT FUDR FLDR PAD1 PAD2 AS 17 16 KO SBUSENA FUDR FLDR PAD2 AS 17 16 SBUSENA SCSIOUT FUDR FLDR ENAUDR SNBDSEL UDS IBACK SCSIOUT FUDR BDSEL ti ENALDR SNBDSEL UDS IBACK SCSIOUT FUDR BDSEL ENVECT Il DBDIR SNBDSEL BDSEL WRITE IBACK SCSIOUT ENVECT Il SLEPIO SNBDSEL ENVECT CKENVEC ENVECT FUDR FLDR SBUSENA BAB3 IACK 1 BPR2 BPR1 BAB2 IBRQ HINTR BGNTI HMATCH SRST GND PFD DTACK REQ1 CCLK BPRO RST IBPR2 IBPRO PG1 RESET VCC REQL BABl BAB2 BAB3 IACK DTACK HINTR IBRQ BGNTI IACK PGl BPR2 IBPR1 HMATCH IBPR2 HMATCH BPR1 IBRPO HMATCH BPRO HMATCH IBPR2 CCLK IBPRl CCLK IBPRO CCLK RST SRST RESET PFD A 11 M8158A CCLK ENAUDR HINTR MYBERR PTOINDL MB158A CKENVECT HINTR 1 LENVECT 0 INTO INTI INTO INT MYBERR INTEN OPCOMP INTEN HINTR 1 LENVECT 1 7INTO INTI HINTR O LENVECT 0 OPCOMP INTEN MYBERR INTEN
89. is being addressed by the host and which port is being used for communication When the interrupt is acknowledged an 8 bit value is placed on the BOSS IX system data bus which is used to create an interrupt vector The vector is programmed into latches in the Data Transceiver and Latch circuit before a DMA is initiated During the DMA cycle a latch counter drives the BOSS IX system bus address lines and automatically increments the address on an even word boundary at the end of the cycle The Control Vector and Status Registers are used for a variety of purposes by the host which include switching DMA on or off enabling interrupts on the SCSI bus disk drive Seek Complete Command Complete resetting the WDC turning the LED control line on or off polling the Status Register for WDC status information and making decisions based on the results 3 1 8158 011235 3110 1 02 011235 314 sna d M 300230 lt 30023 93 YAYLI SALVLS HINO 3 180 HONIM la 8 0103 1041402 u1NO2 21901 HINO sng 3308 1031802 sng SNG YLNOD sng 0 1 sng 0 1 am 1525 VIVO INI 210 210 WDC Functional Block Diagram Figure 3 1 3 2 M8158A The Data and SCSI Bus Transceivers 8 bit bidirectional registers consist ing of upper byte and lower byte segments Associated with each segment is a pair of buffers latches one for input data and one for output data The Data Transceivers
90. nce of the WDC consists of general cleaning which should be ac complished along with scheduled maintenance on the host system Cleaning of the WDC is done in the following manner CAUTION Do not use abrasive cleaners and chemical cleaning agents that contain acetone toluene xylene or benzene These cleaners may cause equipment damage that requires major repair ESD sensitivity requires proper handling of boards 1 Use a soft bristle brush to clean dust from the surface of the printed circuit board 2 Use a lint free cloth dampened with a solution of 90 percent isopropyl alcohol to clean non electrical surfaces 4 2 CORRECTIVE MAINTENANCE The following paragraphs describe power up initialization and self test and the system diagnostics for the WDC Failure of the self tests or system diag nostics requires that the WDC be repaired using the maintenance data furnished in Appendix A single board WDC and Appendix B two board WDC Refer to Section 2 for descriptions and pinouts of the one and two board WDC interfaces 4 2 1 Power Up Initialization and Self Test Upon power up or any reset WDC firmware performs a basic test of hardware which is crucial to correct operation of the controller Memory bus accesses to on board buffer RAM will be disabled from the time the reset occurs until successful completion of all of the self tests 4 1 M8158A In each test the firmware does a loop on the section of the test that
91. nd a minimum of 12 bytes OCh If Drive para meters are being specified the count is 22 bytes 16h The Extent Descrip tor List and the Drive Parameter List are a single data block of 8 bytes and 10 bytes respectively Byte 04 consists of the following 8158 Mode Select Parameter List 4 Bytes The first three bytes are re served the fourth byte specifies the length in bytes of the Extent Descriptor List always 8 bytes in this application The bit pat tern for the Mode Select Parameter List is as follows BYTE BIT 6 Dep 4 13 1 2 d b x8 4 00 i Reserved 01 Reserved 02 Reserved 03 i Length of Extent Descriptor List 08h i Extent Descriptor List 8 Bytes Byte 00 specifies the data density of the Drive must be zero FM density Bytes 01 thru 04 are zero reserved Bytes 5 thru 7 specify Data Block Size 256 512 or 1024 bytes any other value will return a SENSE byte CHECK status with a Bad Argument Error Code 24h The Extent Descrip tor List bit pattern is as follows BYTE BIT DS 53 227 OL O 00 Density Code 01 E Reserved 02 Reserved 03 i Reserved 04 i Reserved 05 MSB Block Size 06 Block Size 07 Block Size LSB i Driver Parameter List 10 Bytes optional feature if present must include all the data necessary to specify a Drive within the limits stated If data is not supplied or is inc
92. ng Diagram 8158 4 REO QUT DA DRE LDRE ACKIN Idle State REO PREFET ENABLE OUT DAT REQ UDRE LDRE ACKIN I PREFET DRBUS BRQIN DRBUS 0 ENABLE Request DMA Read Initiate bus request Fetch lower byte first word BRQIN 1 PREFET 0 FLDR 1 BRQIN 1 DATLAT 1 PIOINM 1 PIOINM 1 DRBUS 1 ACKIN 1 DRBUS 1 Reset DMA request BRQIN 0 Lower data reg empty Output buffer empty LDREs1 PIOINM 0 DRBUS 0 Fetch from UDR and Load into SASI output buffer FUDR 1 DATLAT BRQINsO UDRE 0 FLDR 0 DATLAT 0 LDRE 0 REQ DATLAT Return ACK ACKIN 1 UDRE 0 PIOINM 0 REQ 1 FUDR 0 DATLAT 1 Figure B 4 WDC to BOSS IX System Programmed DMA PAL State Diagram B 5 M8158A Table B 1 BOSS IX System to WDC PAL Signal Listing CCLK BUSY REQ OUT DAT ENABLE DRBUS DATLAT PIOIN GND ENB PIOINM ACKIN LDRE FLDR UDRE FUDR BRQIN PREFET VCC PREFET ENABLE PREFET BRQIN BUSY FUDR REQ UDRE LDRE PREFET DRBUS ACKIN BRQIN ENABLE OUT DAT REQ PIOIN FUDR ACKIN ENABLE PIOIN BUSY ENABLE LDRE FLDR LDRE BUSY ENABLE DRBUS UDRE UDRE FUDR ENABLE OUT DAT PIOIN REQ UDRE ENABLE DRBUS BUSY FUDR ENABLE BUSY LDRE UDRE ENABLE BUSY FLDR FLDR REQ ENABLE OUT DAT UDRE LDRE ACKIN
93. ng Zone Position Used with START STOP command to indi cate the direction and number of cylinders from the last or first data cylinder to the shipping position MSB 0 Landing Zone outside highest track MSB 1 Landing Zone outside Track 0 Bits lt 6 0 gt give the number of cylinders Default 0 land highest innermost track Step Pulse Output Rate Code Timing of Seek steps 00 Non Buf fered Seek 3 0 msec rate per ST 506 01 Buffered Seek 28 usec rate per ST 412 02 Buffered Seek 12 usec rate 3 3 1 13 Mode Sense Op Code 1Ah The MODE SENSE command is used to interrogate the Device Parameter table paragraph 3 3 1 12 to determine the specific characteristics of the attached Disk Drive s Error 1Ch will be returned The bit pattern and significance of MODE SENSE are as follows If the Drive was not formatted by the WDC a Blown Format 3 21 MB158A BYTE BIT Rh 4 4 1 00 1 0 0 0 1 1 0 1 0 01 iLogical Unit No Reserved 02 Reserved 03 Reserved 04 i Number of Bytes Returned i 05 i Control Byte Reserved Byte 04 of the MODE SENSE command specifies the number of data bytes to be returned from the command a minimum of 12 bytes 0 If Drive parameters are being specified the count is 22 bytes 16h Parameter List Extent Descriptor List and the Drive Parameter List if requested are used here in the same as they are used fo
94. njunction with this Disk Controller M8079 MAI 2000 System Service Manual M8083 5 1 4 Fixed Media Disk Drive Service Manual o M8108 MAI 3000 System Service Manual M8158A 1 6 SECTION 2 2 1 GENERAL This section contains unpacking packing instructions and installation require ments for the single board and two board WDC 2 2 SINGLE BOARD WDC 2 2 1 Unpacking Packing Instructions The single board WDC is shipped in an anti static bag inserted between two layers of styrofoam and sealed in a cardboard shipping carton Unpack the WDC as follows 1 Prior to accepting the package from the carrier inspect the ship ping carton for signs of external damage Any indication of ex ternal damage must be noted on the carrier s shipping form and reported immediately to the MBF Sales Office NOTE When unpacking the PCBA set aside the packing materials and shipping carton for use if it should become necessary to reship PCBA is ESD sensitive Proper handling procedures should be used With the PCBA shipping carton in its upright position open the carton and carefully remove the PCBA Unwrap the PCBA and inspect it for signs of shipping damage Im mediately report any damage to the MBF Sales Office 2 2 2 Installation Requirements Install the single board WDC as follows WARNING Dangerous voltages exist within the Base Unit of the BOSS IX system Be sure that the power is turned off and the power
95. ny of the above operations will return an error status and an error code of 1C The 1C code indicates that the format on this drive is bad drive must be formatted by the WDC to prevent this blown format lockout If the drive has been formatted by a WDC and an error comes up at reset the probable cause is the controller being unable to read the disk The controller will make another attempt to recover the drive format informa tion every time a read write command is issued 1C4 error is returned only when the recovery attempt is failed 3 9 8158 3 2 8 Power Down Power Fail Detect When the WDC experiences a power failure the Power Fail Detect PFD line on the BOSS IX system I O bus is driven TRUE and the entire WDC is Reset because PFD is logically OR d with Reset addition PFD causes Write Gate Inhibit to be asserted to prevent a Write glitch on the disk Since the drive does not receive PFD it must be independently capable of detecting a power fail ure So that it can position the heads over the landing zone area and or pre vent erroneous writing 3 2 9 Disk Drive Formatting Every disk drive must be formatted by the WDC or comparable controller be fore data can be written to or read from the drive Formatting is initiated by the Test Unit Ready command from the BOSS IX system the WDC responds with a Status byte value of 00 or the command is repeated until the Check and Busy bytes are clear When the 00 S
96. ollows BYTE BIT 7 6 i 41 3 1 2 4 1 O 3 00 1 0 0 0 1 0 1 0 01 1 Unit No MSB Logical Block Address 02 Logical Block Address 03 i Logical Block Address LSB 04 Reserved i 05 Control Byte Reserved 3 3 1 8 Seek Op Code OBh The SEEK Command causes the selected drive to seek to the specified starting address Immediately after the Seek pulses are issued and head motion starts the WDC returns Completion Status If the WDC receives another command while seek is in progress it returns a Completion Status of BUSY this allows the host to use the SCSI bus to do other processing while waiting for Seek Com plete WDC uses an implied Seek on READ WRITE and SEARCH commands making it unnecessary to issue a SEEK command with each operation Whenever overlapped operations are desired the SEEK command must be used and INTENDO bit 4 gt or INTEND1 lt bit 5 gt in Control Register I O Address CC0007 must be set Setting this bit causes the DTC to check CC0007 bit 6 INTD 0 or 7 INTD 1 for Seek Complete Interrupt Status before executing an RTE instruc tion The appropriate interrupt status bit is reset before the overlapping interrupt is in service the host is thus prevented from being re interrupted by the Seek routine when it is completed The overlapped operations feature may be used only with buffered seek type drives checked with the Mode Sense Command The bit pattern
97. omplete viously supplied values will be used if available if not the fol lowing default values will be used 3 20 00 01 O 02 03 04 05 06 07 08 09 AL O rO PE 3 EE List Format Code 01 i MSB Cylinder Count Cylinder Count LSB i Data Head Count 1 MSB Reduced Write Current Cylinder i Reduced Write Current Cylinder LSB MSB _ Write Precompensation Cylinder Write Precompensation Cylinder LSB DN Landing Zone Position i Step Pulse Output Rate Code List Format Code Always 01 a lao Cylinder Count Number of data cylinders on the Drive Minimum 1 Maximum 2048 Default 306 Data Head Count Number of usable data heads numbered 0 15 Default 2 must use Reduced Write Current line to select heads numbered 8 15 Reduced Write Current Cylinder Cylinder number beyond which the WDC asserts the Reduced Write Current line Minimum 0 Maximum 2047 Default 150 See also Data Head Count descrip tion Write Precomposition Cylinder Cylinder beyond which the WDC compensates for inner track bit shift field ignored by controller value set by jumpers JMP B and JMP as follows Pos 1C 2C Wrt Precomp Cyl Red Wrt Curr Cyl Cannot be used for Drives with more than 8 heads Pos 1A 2A Wrt Precomp always off Pos 1B 2B Wrt Precomp always on i
98. on to the electronic and electrical components the Adapter also contains an 8 position DIP switch a green LED indicator and three electrical connectors DC power is applied to the Adaptec Controller through a four pin cable assembly which is hard wired to the Adapter board The Adapter board is similarly equipped except that no DC power connection is re quired See Figure 1 2 1 3 ADAPTER SECTION FEATURES The Adapter section operates as a Type 1 bus master and will DMA 16 bits at a time that is only on DMA word boundaries Overall operations performed by the Adapter section include o Programmable vectored interrupt to the host when a disk command or disk seek is completed single board WDC only The interrupt is hard wired a level 2 interrupt 7 is highest Interrupts can be enabled or disabled by host command o DMA and interrupt arbitration with up to 15 other controllers for con trol of the BOSS IX system I O bus when requesting a DMA transfer or during an interrupt acknowledge cycle o Provisions for allowing one or two WDCs single board WDC only to oper ate independently on an BOSS IX system I O bus using jumper blocks on the PCBA o Bi directional data driver registers or transceivers which combine two 8 bit data latches for input and two 8 bit data latches for output to form two 16 bit registers O Address registers and drivers consisting of six 4 bit register counter driver devices capable of addressing t
99. on winning the arbitration the WDC takes control of the SCSI bus and issues appropriate interrupt requests to the host The host responds accordingly and the six phase transaction begins The host may cancel a transaction that has started by sending SRST to the WDC this will initialize the WDC and put the SCSI bus into its Bus Free status The entire six phase transaction within the WDC is controlled by a group of Programmed Logic Array PAL devices 3 5 M8158A The detailed operation of the PALs for the single board WDC is slightly dif ferent from that for the two board WDC consequently the PAL state diagrams operation timing diagrams and logic diagrams as well as parts lists for each WDC are continued in separate portions of this manual Appendix A for the single board WDC and Appendix B for the two board WDC The following is a summary of the six phase transaction o Bus Free Phase This Phase occurs when the WDC is initialized or reset indicating a NOT BUSY condition Status Bit 6 BUSY 0 FALSE 11 control lines are deasserted o Selection Phase Before a command is initiated the BOSS IX system monitors Status Bit 6 BUSY for FALSE high condition if high BOSS IX system issues SEL signal and begins writing DBO bits to Address CC000A data present 1 o Command Phase With the WDC selected Status Bit 7 CMD is asserted the I O line is asserted high with Status Bit 1 PIOINM BOSS IX system sends th
100. orms the reverse conversion process and it incorporates address mark gener ation and detection logic as well as the write precompensation functions re quired for appropriate disk drive interface 3 2 SYSTEM I O INTERFACE 3 2 1 WDC I O Addresses The BOSS IX system assigns address block space in its memory by means of a combination of jumpers and board addresses The jumpers allow the system to determine whether one or two WDCs are to operate independently on the system I O bus The board address defines the exact function the WDC is to perform The jumper board address assignments for single board WDCs are specified in Figure 2 1 The jumper board address assignments for the two board WDC are as follows No WDCs JMP A Board Address 1 1 2 2 2 3 CDXXXX The address is loaded into the WDC address registers one byte at a time Each byte must be acknowledged before the next byte can be loaded The sig nificance of each address is as follows 3 3 M8158A o Address 0001 Load DMA Address Register HI byte Address CC0002 Load DMA Address Register MID byte Address CC0003 Load DMA Address Register LO byte These registers are loaded one byte at a time with the 1 s complement 7 of the BOSS IX system address right shifted once Address CC0004 Read Interrupt Vector Register The BOSS IX system initializes this register before using interrupt The operation is required only once per DMA it is not clea
101. p Initialization and Self Test 4 1 System 1 8 55 5 456 54 44 4 4 2 Register and Buffer Tests 4 2 DMA and Interrupt Logic Tests 4 2 WDC Adjustments 4 Test Equipment Required 4 3 Data Separator Adjustment 4 3 bh D P amp P P gt ho 2 to N FO N NH ES LJ C2 CO C2 Fo Fo fto 5 1 APPENDIX SINGLE BOARD WDC MAINTENANCE 6 1 APPENDIX B TWO BOARD WDC MAINTENANCE 6 1 M8158A vi Figure 1 1 1 2 2 1 2 2 3 1 1 2 3 4 5 6 7 8 9 10 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 11 B 12 LIST OF ILLUSTRATIONS Page 5 1 4 Inch Winchester Disk Drive Controller X WDC PCBA Location of Major Components eee eee eO 1 73 Single Board Cable Jumper and Switch Connections 2 3 Two Board Cable Jumper and Switch Connections 2 6 WDC Functional Block 2 2 BOSS IX System WRITE Timing 2 BOSS IX System READ Timing 3 BOSS IX System to WDC Programmed I O PAL State Diagram A 4 WDC to BOSS IX Programmed D
102. r inspect the ship ping carton for signs of external damage Any indication of ex ternal damage must be noted on the carrier s shipping form and reported immediately to the MBF Sales Office NOTE When unpacking each PCBA set aside the packing materials and shipping carton for use if it should become necessary to reship The PCBA is ESD sensitive Proper handling procedures should be used With the PCBA shipping carton in its upright position open the carton and carefully remove the PCBA Unwrap the PCBA and inspect it for signs of shipping damage Im mediately report any damage to the MBF Sales Office 2 3 2 Installation Requirements Install the two board WDC as follows M8158A WARNING Dangerous voltages exist within the Base Unit of the BOSS IX system Be sure that the power is turned off and the power cord is removed before opening the Base Unit cover Shut down the system turn the Base Unit off and remove the power cord To prepare the MAI 2000 system insert a screwdriver or similar device into the slot at the bottom right hand side of the Base Unit cover and push in to disengage the plastic latch Repeat for the left hand latch and remove the cover 2 4 10 To prepare the 3000 system perform the following a Remove the CCA front panel by using a screwdriver to disengage two captive screws at the bottom and then pulling from the bot tom If device controller boards memory boards or d
103. r MODE SELECT paragraph 3 3 1 12 3 3 1 14 Start Stop Op Code 1Bh The START STOP command is used on drives with a designated shipping or landing zone STOP command positions the head to the Landing Zone Position desig nated by the Mode Parameter List in the MODE SELECT command If the command is START bit Byte 04415 must be set otherwise it is a STOP command bit pattern for the START STOP command is as follows BYTE BIT 4 y 3 00 i 0 0 ao 1 1 0 1 1 01 iLogical Unit No Reserved 02 i Reserved i 03 Reserved 04 Reserveq iSt Stp 05 Control Byte Reserved i 3 3 1 15 Receive Diagnostic Result Op Code 1Ch The RECEIVE DIAGNOSTIC RESULT command sends analysis data to the host immedi ately after completion of a SEND DIAGNOSTIC command which initiated the dump The bit pattern and significance of the RECEIVE DIAGNOSTIC RESULT command are as follows BYTE BIT CH bou 3 3 Q vhs ie D ee 00 i 0 0 0 1 1 1 0 0 01 iLogical Unit No Reserved i 02 Reserved 03 MSB Data Length i 04 i Data Length LSB 05 Control Byte Reserved t 8158 3 22 Dump data sent to the Input Data Buffer is formatted as follows BYTE BIT 00 01 02 03 04 103 3 3 1 16 for the WDC and peripheral units T 0 B 5 4 du 3 2 1 beu MSB Data Block Length 0104h Data Block Length LSB MSB Starting Address of Dump
104. red with R t Y di y 2 Bs Address CC000 Read Write Control Register The Control Register contains control bits 0 5 and status bits 6 7 During a Write operation only bits 0 5 are significant during a Read operation all eight bits are significant Individual bits may be turned on or off using a single BSET or BCLR 68000 instruction The register is cleared with Power On Reset The significance of the bits is as follows Bit Name Read Write Function Bit 0 SRST R W Reset the WDC Bit must be maintained gt for a minimum of 25 microseconds logi cally OR d with POR and PFD Bit 1 LED R W LED control signal Bit 2 INTEN R W ENA Oper Compl amp Bus Error Interrupts Bit 3 SEQEN R W Enable DMA Bit 4 INTENDO R W ENA Drive 0 Seek Compl Interrupts Bit 5 INTENDI R W ENA Drive 1 Seek Compl Interrupts Bits 4 and 5 used for buffered seek type drives only set before issuing Seek command reset before leaving interrupt service routine Bit 6 INTDO R Only Drive 0 Seek Compl Interrupt Status Bit 7 INTD1 R Only Drive 1 Seek Compl Interrupt Status Address 0008 Host Write to Output Register This address byte is written to by the host during I O data transfer Information Transfer Phase Host to Controller operations M8158A 3 4 o Address CC0009 Read Adapter s Status Register Bit Name Function Bit 0 MYBERR Bus Error occurring during WDC s bus mastership Bit 1 PIOINM Output Data Regist
105. rives are to be installed remove the side panels also b The side panels slide forward for easy removal It may be helpful to insert the tip of a flat blade screwdriver between the front flange of the panel and the frame about midway down the panel carefully twist the blade to disengage the panel from the frame Remove the drive cables connected to connectors J0 Jl and J2 on the WDC Adapter PCBA see Figure 2 2 for connector locations Prepare the replacement WDC for installation by installing the ap propriate jumpers and setting the dip switches for the WDC Adapter PCBA and Controller PCBA as indicated in Figure 2 2 Locate the Adapter PCBA on the Controller PCBA in the position shown in Figure 2 2 four plastic standoffs one in each corner of the Adapter PCBA should line up with the holes in the Controller PCBA Press down on the corners of the Adapter PCBA until the retainers on the standoffs engage the Controller PCBA Install the power connector into connector J3 of the Adapter PCBA Install Adapter Drive and Bus cable and the CMB and Drive Bus cables as specified in Figure 2 2 Replace the Base Unit cover by lowering the cover onto the Base Unit and allowing it to snap into place Reconnect the power cord Follow the instructions in the BOSS IX System User Guide for operating the host system 2 5 M8158A CONNECTIONS TO ADAPTER BOARD 907634 001 THIS IS PART OF ADAPTER BOARD ASSEMBLY 9
106. s List of WDC Mnemonics Part No Part No Part No Part No Part No Part No 903439 001 903439 001 903439 001 907649 001 907649 001 907649 001 Parts Location Diagram List of Parts 2 Sheets Schematic Diagram 13 Sheets Parts Location Diagram List of Parts Schematic Diagram NOTE 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 10 B 11 B 12 The PAL state diagrams and equations in this appendix are provided for reference purposes only and will not be maintained B 1 FIGURE TABLE 8158 CCLK ul d PIA H HT FUDR ACKIN i TIRE NM DATLAT ww hl OUT REQ Figure B 1 BOSS IX System to Programmed I O PAL Timing Diagram M8158A B 2 REQ 0 Idle State REQ OUT ACKIN PIOIN 0 Sasi output buffer empty PIOINM 1 PIOIN REQ Fetch from UDR and load into Sasi output buffer FUDR 1 DATLAT 1 Complete handshake ACKIN 0 REQ DATLAT Return an ACK ACKIN 1 PIOINM 0 EQ DATLAT Reset FUDR amp DATLAT PIOIN 0 FUDR 0 DATLAT 0 REQ 1 Figure B 2 BOSS IX System to WDC Programmed I O PAL State Di 3 8158 CCLK FUDR FLDR PIOINM DRBUS T SA IIO TN IN mim ai fs SSE T ULL RC dE HAUT HOD ce OA Figure B 3 55 IX System to Programmed DMA PAL Timi
107. s These ICs are socketed for ready exchange or re placement In addition to the electronic and electrical components the PCBA also contains three jumper blocks a green LED indicator and five electrical connectors whose locations are shown in Figure 1 2 NOTE The single board WDC is not supported in the MAI 3000 system 1 1 M8158A 006 00S1 0002 00ST 0002 0091 t 0002 009 OTS OTS 0002 000 0002 009 0002 0091 000 000 000 0061 0061 000 lt 0002 000t 0007 uo OdSW Of G9 SS ASW GG JdSW GS ASW 06 JASN 06 ASW 06 06 JASN 8 SASW 82 OASW OE SASW Ot JSW Ot JdJSW LC LC JdSW LC OASW 8C Suit 6519 619 079 079 079 OTE OTE OTE 079 COT TOT 0 8 0t8 Vect 816 816 816 COT 20 LT T LT LI LT LT LT ct ct LT LT LT LT LT LT 6 Li LT Jod CTS CTs cts CIS CIS CIS CIS 9GcC 9G CIS CIS TIS cts cts cls COT CIS CIS CoNo ST SI ST Tt 8 Jo3098 Jod 8109095 20 09 09tc 0214 0786 0r8 0 16 098 09GC 08cT 618 rtrI9 0966 0867 09 8T OLLET OLLET 8600T 618 SXoe1 jo Joqumw ST 0c ST 0c 96777 9p TE CEE 9G pt 8c cc 46702 6 0 T S F 69 98 Gc tr T8 6ST
108. tatus byte is received the BOSS IX system is sues Mode Select containing the necessary drive parameters followed by a Format command to initiate the actual format The WDC formats the disk and stores the drive parameters on the disk so there is no need to repeat this information to the WDC with every Reset or Power Up 3 2 10 BOSS IX system to WOC Sequencing The BOSS IX system host to WDC controller sequencing logic is primarily implemented in PAL Programmed Logic Array Sequencers using combinational and sequential machine logic State diagrams timing diagrams PAL signal listings and the logic diagrams associated with the single board WDC are contained in Appendix A those asso ciated with the two board WDC are contained in Appendix B of this manual These sources may be used when considering the detailed operation of the se quencers Overall the following functiong are involved in BOSS IX system to WDC sequencing o Set and reset SCSI Output Buffer Empty status PIOINM o Direct fetching of data from lower or upper byte of Data Registers for SCSI controller o Unpack upper and lower Status Byte of Data Register o Internal Bus Request to BOSS IX system interface Provide diagnostic features BOSS IX system to WDC sequencing is significantly different when data transfer from host to controller is via DMA than when transfer is via I O bus following paragraphs summarize the sequencing functions 3 2 10 1 Ou
109. tee tee e De IG OO Aer DAAR LE e 1597 s 74540 7 1 rian 7418 97 8 21227 ra 741597 5 raises 8 E eT z 21 2e 2459 5 5 L7 22 7558 s 5 5 2e 745133 Lb 2 r z 27 745 28 7 ea asse e 7 7 Far see 7 amp 5 a Ecce NE EMI L2P 74 5097 8 A EE Sree scs RET 28 745 57 4 72 3 745022 Jaj _ 30 45744 5 5 7 7452 5 5 3F 4574 0 0 21 3G 796 twin 34 7419138 2 2 2 74 52401 e e jejejeje 2 74502 710 3L 4508 e 7 9 101 zese99 8 Lore L I P s N NNN N N Figure B 12 8158 8 524 4 L7 L NM NE COMPONENT MAP 20 7425374 7 74 6374 9 _ cu 48 4 40 74 5640 16 jar oL Iu P 46 748374 id 48 746374 ID 37 2415273 9 7415374 9 jn 4 7418376 9 an 74534 7 N N N
110. til requested and is cleared when the host acknowledges receipt of the CHECK data In the REQUEST SENSE Command structure the Number of Blocks field Byte 04 specifies the number of bytes allocated by the host for returned SENSE Byte values of 00 to 03 default to 04 BYTE BIT EM DE 024 ee UE 00 1 0 0 0 0 0 0 1 1 1 01 iLogical Unit No Reserved t 02 Reserved 03 Reserved 04 Number of Bytes 05 Control Byte Reserved 3 2 5 Sense Byte Structure The structure and significance of the bits in the SENSE byte which is returned to the BOSS IX system in response to the REQUEST SENSE Command is shown below In the SENSE byte the Address Valid bit Byte 0047 indicates that the Logi cal Address bytes contain valid information The Error Class field value defines whether the error is drive related 00 data related 01 or system related 02 3 7 8158 BYTE BIT t 4 123 2 r 1 1 0 1 00 iAdVal Error Class i Error Code 01 1 Reserved MSB Logical Block Address 02 Logical Block Address 03 i Logical Block Address 3 2 6 Error Codes 3 2 6 1 Class 00 Error Codes Class 00 Error Codes are drive related errors 00 01 02 3 2 6 2 Class 01 follows 10 11 12 13 14 15 16 17 3 2 6 3 1 02 20 21 22 8158 NO SENSE NO INDEX SIGNAL NO SEEK COMPLETE Class 01 Error Codes I D CRC ERROR UNCORRECTABLE DATA ER
111. tput Buffer Empty Status The Output Buffer Empty status bit PIOINM is set if the WDC requests a byte of data and ACKIN has not been sent to acknowledge transfer of data PIOINM is reset when ACKIN is set to acknowledge transfer M8158A 3 10 3 2 10 2 Direct Fetching of Data During a data transfer sequence SEQEN Control Register bit 3 is used to distinguish between a DMA cycle and a programmed I O cycle If SEQEN is FALSE high data transfer is via programmed I O if SEQEN is TRUE low a DMA cycle with full handshake between BOSS IX system and WDC is initiated Com mand and status bytes are always transferred by programmed I O 3 2 10 3 Unpacking Data Registers During each cycle of a DMA WRITE operation a word is transferred into the upper and lower bytes of the WDC Input Data Register The Data Register Empty flags UDRE Upper LDRE Lower provide status and data flow steering func tions into the SASI Output Buffer The upper byte is fetched before the lower byte 3 2 10 4 Generating Internal Bus Requests Generation of an internal bus request with full handshaking with tlie host through the EBUS interface logic is controlled primarily by the BRQIN signal in conjunction with PREFE as follows When a DMA cycle has been initiated and there has been no new DMA re quest PREFET and BRQIN are both TRUE DMA is enabled and a bus re quest is initiated The HTC host to controller PAL monitors the DMA cycle and causes
112. ucing a 3 Head Offset and verifying a Head Seek back to Track 0 The drive parameter information for that unit is then saved in the WDC If the drive is unformatted or the format data is not recognized by the WDC the WDC causes a blown format bit in BOSS IX on board system memory to be set the Power Up sequence is halted for that unit If the drive format is correct the WDC causes the drive to read the largest block address present up through the last cylinder The drive is returned to Track 0 stopping in selected zones in each track to read the defect count in the zone These counts are saved in the WDC and used to establish the location of target blocks on the disk during reads writes and seeks During the Reset sequence the WDC performs a series of self diagnostics which render the WDC unavailable for use for about one second after a hardware Reset is sent Therefore the Reset line should be used only for initial or emergency power up not if the disk system is lost or between commands Also if the drive is not formatted or the format is unreadable the first command after reset except Request Sense Test Unit Ready Start Stop Send Diagnostic or Mode Select will show an error If a SENSE command is issued the returned error code will be an error code without the address valid bit bit 7 set The controller will NOT allow any operation that READs WRITEs or moves the heads on a drive with a blown format Instead a

Service Manual - System 2000 Winchester Disk Controller

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