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EPPCBug™ Diagnostic Firmware User's Guide - ps

1. MBX821 XXX MPC821 based embedded controllers MBX860 XXX MPC860 based embedded controllers They are collectively referred to in this manual as the MBX board or board When necessary to refer to them individually they are called the MBX821 and MBX860 respectively This introductory chapter includes information about the operation and use of the diagnostics Chapter 2 contains descriptions of the diagnostic utilities Chapter 3 contains descriptions of the diagnostic test routines Before using the EPPCBug diagnostics you should ensure that your MBX board and other hardware have been properly configured and connected according to the installation guide for your MBX board You also need the User s manual for EPPCBug It contains a complete description of EPPCBug the start up procedure descriptions of all general software debugging commands and other information you need to know about the debugger 1 1 General Information Overview of EPPCBug Firmware The EPPCBug diagnostic firmware package resides in flash memory which has been programmed on the MBX These flash memory devices which also contain EPPCBug contain a complete diagnostic monitor along with a battery of utilities and tests for exercise test and debug of hardware in the MBX environment The diagnostics are menu driven for ease of use The Help HE command displays a menu of the diagnostic functions i e the tests and utilities Several tests have a sub tes
2. Error Message Lookup of AUI connector product configuration option in VPD data failed Symptom or Cause A problem was encountered accessing the AUI header Product Configuration Option in the Vital Product Data Serial ROM The nature of the problem is displayed just before this message Error writing XX to CR1 SR1 Expected XX Actual XX This is caused by an onboard problem accessing the board Control Status register 1 Frame transmit time failure Expected dus to S dus Actual dus The time required to transmit a frame is out of range The expected range and the actual time taken are displayed The clock source to the MPC8xx transceiver may have diverged from 10MHz Lookup of TP connector product configuration option in VPD data failed A problem was encountered accessing the TP connector Product Configuration Option in the Vital Product Data Serial ROM The nature of the problem is displayed just before this message 3 47 SCCI1ETH SCC1 Ethernet Tests 3 48 Glossary Abbreviations Acronyms and Terms to Know This glossary defines some of the abbreviations acronyms and key terms used in this document 10Base 5 10Base 2 10Base T 100Base TX ACIA AIX architecture ASCII An Fthernet implementation in which the physical medium is a doubly shielded 50 ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters al
3. Row Address Strobe A clock signal used in dynamic RAMs to control the input of the row addresses GL 10 Glossary Raven The PowerPC to PCI local bus bridge chip developed by Motorola for the MVME2600 and MVME3600 series of boards It provides the necessary interface between the PowerPC 60x bus and the PCI bus and acts as interrupt controller Reduced Insiruction Set Computer RISC RFI RGB RISC ROM RTC SBC SCSI SCSI 2 Fast Wide serial port SIM SIMM A computer in which the processor s instruction set is limited to constant length instructions that can usually be executed in a single clock cycle Radio Frequency Interference The three separate color signals Red Green and Blue Used with color displays an interface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal Both digital and analog RGB interfaces exist See Reduced Instruction Set Computer RISC Read Only Memory Real Time Clock Single Board Computer Small Computer Systems Interface An industry standard high speed interface primarily used for secondary storage SCSI 1 provides up to 5 Mbps data transfer An improvement over plain SCSI and includes command queuing Fast SCSI provides 10 Mbps data transfer on an 8 bit bus Wide SCSI provides up to 40 Mbps data transfer on a 16 or 32 bit bus A connector that can exchange data with an I O device on
4. Running gt FAILED Data Miscompare Error Expected Actual RAM Local RAM Tests REF Memory Refresh Testing Command Input EPPC Diag gt RAM REF Description The memory range and address increment is specified by the RAM test directory configuration parameters Refer to CF Test Group Configuration Parameters Editor First the real time clock is checked to see if it is functioning properly Second each memory location to be tested has the data portion verified by writing verifying all zeros and all ones Next a data pattern is written to the test location After all the data patterns are filled for all test locations a refresh wait cycle is executed After the wait cycle the data is read and if the previously entered data pattern does not match the data pattern read in a failure occurs If the data patterns match then the test is passed Response Messages After the command has been issued the following line is printed RAI REF mory Refresh Test Running gt If all parts of the test are completed correctly then the test passes RAl REF mory Refresh Test Running gt PASSED If any part of the test fails then the display appears as follows RAI REF mory Refresh Test Running gt FAILED error message Here error message is one of the following If the real time clock
5. and then press the RETURN or ENTER key The command may be the name of a diagnostic utility routine and may include one or more arguments or it may be the name of one or more test groups listed in a main root directory and may include one or more subcommands individual test names listed in the subdirectory for a particular test group The utility routines are described in Chapter 2 The test groups are described in Chapter 3 Examples of command entry for both are given below Root Level Command Utility The utility or root level commands affect the operation of the tests that are subsequently run A test group name may be entered on the same command line For example EPPC Diag gt CF RAM causes an interactive dialog to begin in which you may enter parameters for the RAM tests Command entry may also include a subcommand individual test name For example EPPC Diag gt HE RAM CODE causes a help screen to appear that gives information about the CODE test in the RAM test group 1 3 General Information Root Level Command Test Group Entering just the name of a test group causes all individual tests that are part of that group to execute in sequence with some exceptions For example EPPC Diag gt RAM causes all Random Access Memory RAM tests to execute except for two that only execute if specified Subdirectory Level Command Individual Test Entering the name of a test group
6. gt PASSED If the test fails then the display appears as follows RAI BIOG Bit Toggles eeraa e was n E a Running gt FAILED Data Miscompare Error Address Expected Actual 3 25 RAM Local RAM Tests CODE Code Execution Copy Command Input EPPC Diag gt RAM CODE Description Copy test code to memory and execute The code in the memory under test copies itself to the next higher memory address and executes the new copy This process is repeated until there is not enough memory as specified by the configuration parameters to perform another code copy and execution Response Messages After the command has been issued the following line is printed RAM CODE Code Execution Copy Running gt If all parts of the test are completed correctly then the test passes RAM CODE Code Execution Copy Running gt PASSED The test failure mode is typified by the nonjudicial of the passEp message above after more than about 1 minute which indicates that the MPU has irrecoverably crashed Hardware reset is required to recover from this error Test Descriptions PATS Data Patterns Command Input EPPC Diag gt RAM PATS Description If the test address range test range is less than 8 bytes the test immediately returns pass status The effective test range end address is reduced to the next lower 8
7. Battery Backed Up RAM Tests BBRAM Addressing ADR Command Input EPPC Diag gt D1350 ADR Description This test is designed to assure proper addressability of the D13xxY BBRAM The algorithm used is to fill the BBRAM with data pattern a a single address line of the D13xxY is set to one and pattern b is written to the resultant test address All other locations in the BBRAM are checked to ensure that they were not affected by this write The a pattern is then restored to the test All address lines connected to the D13xxY are tested in this manner Since this test overwrites all memory locations in the BBRAM the BBRAM contents are saved in debugger system memory prior to writing the BBRAM The D1350 test group features a configuration parameter which overrides automatic restoration of the BBRAM contents The default for this parameter is to restore BBRAM contents upon test completion Response Messages After the command has been issued the following line is printed D1350 ADR D1350Y RAM Addressing 520 Running gt If all parts of the test are completed correctly then the test passes D1350 ADR D1350Y RAM Addressing 620 Running gt PASSED If any part of the test fails then the display appears as follows D1350 ADR D1350Y RAM Addressing 5 Running gt FAILED error message Here error message is one of the following If de
8. 39 40 47 48 55 56 63 ADR4 ADR5 ADR6 ADR7 The terms control bit and status bit are used extensively in this document The term control bit is used to describe a bit in a register that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions The following conventions are used in this document bold is used for user input that you type just as it appears Bold is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples courier is used for system output e g screen displays reports examples and system prompts lt RETURN gt represents the carriage return key CTRL represents the Control key Execute control characters by holding down the control key while pressing the letter key e g CTRL d Related Documentation T
9. Port Interrupt Running gt If all parts of the test are completed correctly then the test passes LPT IRQ Parallel Port Interrupt Running gt PASSED If any part of the test fails then the display appears as follows LPT IRQ Parallel Port Interrupt Running gt FAILED LPT Super I O Parallel Port Tests LPT IRQ Test Failure Data error message Refer to the section LPT Error Messages for a list of the error messages and their meaning Test Descriptions LPT Error Messages The LPT test group error messages generally take the following form LPT IRQ Parallel Port Interrupt Running gt FAILED LPT IRQ Test Failure Data IRQ 7 Failed to Occur Interrupt Controller IRR2 22 IRR1 00 The first line of the failure identifies what type of failure occurred The following line provides additional information about the failure LPT Super I O Parallel Port Tests Table 3 6 LPT Error Messages Error Message Lookup of PC I O product configuration option in VPD data failed Symptom or Cause The I2C bus access to the serial ROM device containing vital product data failed The product configuration option tells whether PC I O devices are installed on this board Unsolicited IRQ Sd occurred while device sourc of IRQ d is still disabled This indicates a failure to part 1 of the test The
10. being toggled RAM PED Test Failure Data Unexpected Exception Er Address Under Test ror Vector If no exception occurred when data with bad parity was read RAM PED Test Failure Da Parity Error Detection Exception Vector Address Under Test tca Exception Did Not Occur If the exception address was different from that of the test location RAM PED Test Failure Data Fault Address Miscompare Expected Actual 3 29 RAM Local RAM Tests PERM Permutations Command Input EPPC Diag gt RAM PERM Description This command performs a test which verifies that the memory in the test range can accommodate 8 bit 16 bit and 32 bit writes and reads in any combination The test range is the memory range specified by the RAM test group configuration parameters for starting and ending address If the test address range test range is less than 16 bytes the test immediately returns pass status The effective test range end address is reduced to the next lower 16 byte boundary if necessary This test performs three data size test phases in the following order 8 16 and 32 bits Each test phase writes a 16 byte data pattern using its data size to the first 16 bytes of every 256 byte block of memory in the test range The 256 byte blocks of memory are aligned to the starting address configuration parameter for the RAM test group The test phase then reads and ver
11. command The individual tests are described in alphabetical order on the following pages Table 3 5 LPT Test Group Name Description IRQ Parallel Port Interrupt The IRQ test does not require any connection to Parallel Port header J13 Test Descriptions IRQ Parallel Port Interrupt Command Input EPPC Diag gt LPT IRQ Description This test verifies the capability of the Peripheral I O Controller parallel port function to generate interrupts to the system The test consists of two parts Part 1 checks that no interrupt occurs when the parallel port interrupt output is disabled and the parallel port interrupt is unmasked at the cascaded 8259 interrupt controller and external interrupts are unmasked at the MPC 8xx interrupt controller Part 2 checks that an interrupt and the correct 8259 IRQ does occur when the parallel port interrupt output is asserted and the parallel port interrupt is unmasked at the cascaded 8259 interrupt controller and external interrupts are unmasked at the MPC 8xx interrupt controller The parallel port interrupt output is asserted by configuring the parallel port function into ECP Mode ECP Test Mode and enabling the service interrupt This asserts an interrupt since the direction is output and the Test FIFO is empty This test does not require any offboard connections Response Messages After the command has been issued the following line is printed LPT IRQ Parallel
12. either color or B W systems but not the color GL 14 A abbreviations acronyms and terms to know GL 1 ACCESS test SCC 3 39 addressing memory 3 21 addressing test for BBRAM 3 4 ADR 3 21 AEM append error messages command 2 2 All Errors Mode Command AE 2 2 ALTS 3 23 AM79C970 79C974 Ethernet Controller tests 3 12 3 35 Append Error Messages Mode Com mand AEM 2 2 arguments specifying 2 3 B battery low test 3 6 Battery Backed Up SRAM RAM 3 7 BBRAM addressing test results 3 4 battery backed up RAM tests 3 2 BBRAM Addressing ADR 3 4 Bit Toggle BTOG 3 24 bridge tests 3 9 BTOG 3 24 Index C CEM clear error messages command 2 2 CE test group config parameter editor command 2 3 Clear Zero Error Counters Command ZE 2 8 Clear Error Messages Command CEM 2 2 CODE 3 26 command entry and directories 2 1 commands entering 2 1 configuration parameters 2 3 CERTC 33 connectors AUI and 10base t 3 37 D D1350 BBRAM test command 3 2 Data Patterns PATS 3 27 DE display error counters 2 3 DEM display error messages 2 3 design requirements diagnostic 1 3 diagnostic firmware 1 2 diagnostic monitor 2 1 commands to 2 1 error message accumulation 2 2 Diagnostic Test Groups 3 1 directories 2 1 2 7 IN 15 Index Display Error Counters Command DE 20 Display Error Messages Command DEM 2 3 Display Pass Count Command DP 2 4 Display Revise Self Test Mask Com mand MASK 2
13. first IRQ number is the IRQ number that caused the external interrupt at the cascaded 8259 interrupt controller The second IRQ number is the IRQ line at the cascaded 8259 interrupt controller that is connected to the parallel port IRQ Sd Failed to Occur Interrupt Controller IRR2 XX IRR1 YY This indicates a failure to part 2 of the test The IRQ number is the IRQ line at the cascaded 8259 interrupt controller that is connected to the parallel port XX is the hex value of IRR register of the slave 8259 at the time the failure is reported YY is the hex value of IRR register of the master 8259 at the time the failure is reported Wrong IRQ occurred expected d actual d An interrupt from a different IRQ than expected occurred 3 16 Test Descriptions PCIB PCI ISA Bridge Tests This section describes the individual PCI Bridge tests Entering PCIB without parameters causes all PCIB tests to execute in the order shown in the following table To run an individual test add that test name to the PCIB command The individual tests are described in alphabetical order on the following pages Table 3 7 PCIB Test Group Name Description REG Register IRQ Interrupt PCIB PCI ISA Bridge Tests IRQ Interrupt Command Input PPC1 Diag gt PCIB IRQ Description This test verifies that the PCI Bridge can generate interrupts It uses the software interrupt of the PC
14. prefix 2 8 ST command 2 8 ZE command 2 8 ZP command 2 8 WwW write read 3 31 Z ZE clear error counters 2 8 IN 18 Zero Pass Count Command ZP 2 8 ZP zero pass count 2 8 IN 19
15. 1 to pin3 and connect pin 2 to pin 6 A cable at least 6 feet long should be used for the loopback Response Messages After the command has been issued the following line is printed SCC1ETH TPLOOP 10BaseT Connector External Loopback Running gt If all parts of the test are completed correctly then the test passes SCC1ETH TPLOOP 10BaseT Connector External Loopback Running gt PASSED If any part of the test fails then the display appears as follows SCC1ETH TPLOOP 10BaseT Connector External Loopback Running gt FAILED SCC1ETH TPLOOP Test Failure Data error message Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning 3 42 Test Descriptions SCC1ETH Error Messages The SCC1ETH test group error messages generally take the following form SCCIE SCCIE H I OOP Interface Transceiver Loopback Running gt FAIL H I OOP Test Failure Data Time out error while receiving packet on SCC1 ED The first line of the failure identifies what type of failure occurred The following line provides additional information about the failure 3 43 SCC1ETH SCC1 Ethernet Tests Table 3 10 SCC1ETH Error Messages Error Message Software error couldn t find network driver node control memory Symptom or Cause No node control memory was found for the
16. 7 DP display pass count command 2 4 E ELPBCK test SCC 3 39 EPPCBug 1 1 compatibility 1 1 directories described 1 2 Help command 1 2 location 1 2 menus 1 2 EPPC Diag command nomenclature 1 3 root level commands 1 3 running individual tests 1 4 running multiple individual tests 1 4 subcommand 1 3 test group execution 1 4 error counters 2 3 2 8 clear 2 8 error detection 3 28 error message bad ethernet address 3 46 driver error while initializing 3 44 driver error while receiving 3 45 driver error while sending 3 44 error writing 3 47 frame transmit time failure 3 47 incompatible packet sizes 3 46 lookup failed 3 47 no network driver node 3 44 send receive date miscompare 3 46 timeout error while receiving 3 45 transmit buffer size 3 45 error message buffer when cleared 2 2 error message flag default 2 2 error message mode 2 2 error messages 2 2 2 3 accumulating 2 2 error messages AM79C970 3 15 3 43 errors mode 2 2 ethernet address test for valid address 3 36 Ethernet controller tests 3 12 3 35 F failed test repeat without notification 2 7 failed tests repeating 2 6 firmware diagnostic 1 2 frequency of ethernet transmitter clock 3 41 H HE help command 2 4 Help Extended interactive use 2 5 Help Extended Command HEX 2 5 HEX help extended command 2 5 l I O tests for Super I O Parallel Port 3 12 182378 PCI ISA Bridge tests 3 9 ILPBCK test SCC 3 13 3 36 IndustryPack Interface Controller I
17. CPU is most likely to use over and over again and avoids accessing the slower hard or floppy disk drive CAS Column Address Strobe The clock signal used in dynamic RAMs to control the input of column addresses CD Compact Disc A hard round flat portable storage unit that stores information digitally CD ROM Compact Disk Read Only Memory CFM Cubic Feet per Minute CHRP See Common Hardware Reference Platform CHRP CHRP compliant See Common Hardware Reference Platform CHRP CHRP Spec See Common Hardware Reference Platform CHRP CISC Complex Instruction Set Computer A computer whose processor is designed to sequentially run variable length instructions many of which require several clock cycles that perform complex tasks and thereby simplify programming CODEC COder DECoder Color Difference CD The signals of R Y and B Y without the luminance Y signal The Green signals G Y can be extracted by these two signals Common Hardware Reference Platform CHRP A specification published by Apple IBM and Motorola which defines the devices interfaces and data formats that make up a CHRP compliant system using a PowerPC processor Composite Video Signal CVS CVBS Signal that carries video picture information for color brightness and synchronizing signals for both horizontal and vertical scans Sometimes referred to as Baseband Video cpi characters per inch cpl characters per line GL 3 lt DrPo
18. EPPCBug Diagnostic Firmware User s Guide EPPCDIAA UM1 Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes No part of this material may be reproduced or copied in any tangible medium or stored in a retrieval system or transmitted in any form or by any means radio electronic mechanical photocopying recording or facsimile or otherwise without the prior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph c 1 ii of the Rig
19. I Bridge to induce an interrupt from the PCI bridge to the CPU Response Messages After the command has been issued the following line is printed PCTB EROS INCEST ruUpt oeni sre die eiere Bid e E n el Sten s Running gt If all parts of the test are completed correctly then the test passes PCIBS TRO s INCEPE aeie eiad Save are ee eee ies Running gt PASSED If any failures occur the following is displayed more descriptive text then follows P IB TRO INterrupt sos cca eee ce eed eos eee Running gt FAILED If the test fails because an interrupt request from the PCI Bridge is pending and it is not expected the following is displayed PCIB IRO Test Failure Data Unexpected Interrupt SIPEND SIMASK 7 SIVEC INT_STAT If an interrupt has not been requested by the PCIB the following message is displayed PCIB IRQ Test Failure Data Interrupt Failed to Occur SIPEND SIMASK SIVEC INT_STAT Test Descriptions REG Register Command Input PPC1 Diag gt PCIB REG Description This test verifies that the PCIB registers can be written and read Data patterns verify that every read write bit can be modified Response Messages After the command has been issued the following line is printed PCTBV REGS REGUSCOT ese aid siete tor E O E aras Running gt If all parts of the test are completed correctly then the test passes PCIB REGS REGUSEORS ear
20. PIC tests 3 12 3 35 Interrupt IRQ 3 10 3 18 interrupt test for PCI Bridge 3 18 IPIC tests 3 12 3 35 ISA Bridge IN 16 interrupt test 3 10 ISAB resiters test 3 11 L LA loop always command 2 5 LC loop continue command 2 6 LE loop on error command 2 6 LF line feed suppression command 2 6 line feed suppression 2 6 Line Feed Suppression Mode Prefix LF 2 6 LN loop non verbose command 2 7 Local Parity Memory Error Detection PED 3 28 local RAM tests 3 20 LOOP tests signal path 3 38 Loop Always Mode Prefix LA 2 5 Loop Non Verbose Mode Prefix LN 2 7 Loop Continue Mode Prefix LC 2 6 Loop On Error Mode Prefix LE 2 6 LOOPQ signal path test with SCC1 3 39 M MBX boards using EPPCBug 1 1 Memory Addressing ADR 3 21 Memory Refresh Testing REF 3 32 messages suppression 2 7 MK48T08 RTC Tests 3 1 multiple test commands entering 1 5 multiple tests individual 1 4 N Non Verbose Mode Prefix NV 2 7 NV non verbose mode command 2 7 P pass count 2 4 2 8 PATS 3 27 PCI Bridge interrupt test 3 18 PCI ISA Bridge tests 3 17 PCI ISA bridge tests 3 9 3 17 PCIB register test 3 19 PED 3 28 PERM 3 30 Q Quick Write Read QUIK 3 31 QUIK 3 31 R RAM tests 3 20 Random Data RNDM 3 34 read write 3 31 REF 3 32 REGA transceiver control register access 3 40 Register REG 3 11 3 19 RNDM 3 34 root level commands utilities 2 1 RTC Configuration Parameters 3 3 RTC test command
21. Q Interrupt 3 18 REG Register 3 19 RAM Local RAM Tests 3 20 ADR Memory Addressing 3 21 ALTS Alternating Ones Zeros 3 23 BTOG Bit Toggle 3 24 CODE Code Execution Copy 3 26 PATS Data Patterns 3 27 PED Local Parity Memory Error Detection 3 28 PERM Permutations 3 30 QUIK Quick Write Read 3 31 REF Memory Refresh Testing 3 32 RNDM Random Data 3 34 SCC1ETH SCC1 Ethernet Tests 3 35 ADDR Ethernet Address 3 36 AULOOP AUI Connector External Loopback 3 37 LOOP Interface Transceiver Loopback 3 38 ILOOPQ Interface Transceiver Loopback SQE 3 39 REGA Transceiver Control Register Access 3 40 TCLK Transmit Clock Frequency 3 41 TPLOOP 10BaseT Connector External Loopback 3 42 SCCIETH Error Messages 3 43 Abbreviations Acronyms and Terms to Know GL 1 List of Figures Help Screen 2 5 Diagnostic Utilities 2 1 Diagnostic Test Groups 3 1 BBRAM Test Group 3 2 BBRAM Memoty Sizes 3 3 ISAB Test Group 3 9 LPT Test Group 3 12 LPT Error Messages 3 16 PCIB Test Group 3 17 RAM Test Group 3 20 SCC1ETH Test Group 3 35 SCC1ETH Error Messages 3 44 List of Tables xii General Information Introduction This manual describes the set of hardware diagnostics included in the EPPCBug Debugging Package intended for testing and troubleshooting of Motorola s MPC8XX based boards This member of the EPPCBug firmware family known as EPPCBug diagnostics is implemented on these Motorola MPC8XX based products
22. SCC1ETH driver The NIOT command must also show a non zero value for the Node Control Memory to prevent this failure Driver error while initializing SCCl status XXYY The initialization call of the SCCIETH driver returned an error code XX is the controller independent status code YY is the MPC8XX SCC1 ethernet controller dependent status code See the Network Communication Status Codes section of the PowerPC EPPCBUG Firmware Package Users Manual Driver error while sending packet on SCCl status XXYY The send packet call of the SCCI1ETH driver returned an error code XX is the controller independent status code YY is the MPC8XX SCC1 ethernet controller dependent status code See the Network Communication Status Codes section of the PowerPC EPPCBUG Firmware Package Users Manual 3 44 Test Descriptions Table 3 10 SCC1ETH Error Messages Continued Error Message Driver error while receiving packet on SCCl status XXYY Timeout error while receiving packet on SCC1 Symptom or Cause The packet receive call of the SCC1ETH driver returned an error code XX is the controller independent status code YY is the MPC8XX SCC1 ethernet controller dependent status code See the Network Communication Status Codes section of the PowerPC EPPCBUG Firmware Package Users Manual A loopback packet was not received within the time out period Indicates a malfunctioning circuit or conne
23. Test Descr iptions This verifies the frequency of the ethernet transmitter clock by measuring the average time it takes to transmit a frame while in internal loopback mode Response Messages After the command has been issued the following line is printed Running gt of the test are completed correctly then the test passes SCC1ETH TCLK Transmit Clock Frequency If all parts SCC1ETH TCLK Transmit Clock Frequency If any part of SCC1ETH TCLK Transmit Clock Frequency SCC1ETH TCLK Test Failure Data error message Running gt PASSI the test fails then the display appears as follows Running gt FAILI ED ED Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning 3 41 SCC1ETH SCC1 Ethernet Tests TPLOOP 10BaseT Connector External Loopback Command Input EPPC Diag gt SCCl1ETH TPLOOP Description This test verifies that the signal path through the 10BaseT connector is operating correctly by transmitting and receiving packets and comparing the data This test requires the presence of an external loopback plug in the 10BaseT connector Note Itis recommended that the board under test not be connected to a live network while this test is running The suggested loopback setup for this test is to connect pins of the RJ45 10BaseT connector as follows connect pin
24. Transceiver Loopback SOE Running gt PASSED If any part of the test fails then the display appears as follows Oo SCC1ETH ILOOPQ Interface Transceiver Loopback SQE Running gt FAILE SCC1ETH ILOOPQ Test Failure Data error message Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning SCC1ETH SCC1 Ethernet Tests REGA Transceiver Control Register Access Command Input EPPC Diag gt SCCl1ETH REGA Description This test verifies the write and read capability of the 5 bits in the board Control and Status Register 1 that interface to the ethernet interface transceiver chip Response Messages After the command has been issued the following line is printed SCC1ETH REGA Transceiver Control Register Access Running gt If all parts of the test are completed correctly then the test passes SCC1ETH REGA Transceiver Control Register Access Running gt PASSED If any part of the test fails then the display appears as follows SCC1ETH REGA Transceiver Control Register Access Running gt FAILED SCC1ETH REGA Test Failure Data error message Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning 3 40 TCLK Transmit Clock Frequency Command Input Description EPPC Diag gt SCClETH TCLK
25. a Inc under license from IBM GL 9 lt DrPonwory lt Dronoryn Glossary PowerPC 603 PowerPC 604 The second implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 64 entry buffer and an 8KB instruction and data cache It provides a selectable 32 bit or 64 bit data bus and a separate 32 bit address bus PowerPC 603 is used by Motorola Inc under license from IBM The third implementation of the PowerPC family of microprocessors currently under development PowerPC 604 is used by Motorola Inc under license from IBM PowerPC Reference Platform PRP A specification published by the IBM Power Personal Systems Division which defines the devices interfaces and data formats that make up a PRP compliant system using a PowerPC processor PowerStack RISC PC System Board PRP PRP compliant PRP Spec PROM PS 2 QFP RAM RAS A PowerPC based computer board platform developed by the Motorola Computer Group It supports Microsoft s Windows NT and IBM s AIX operating systems See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP Programmable Read Only Memory Personal System 2 IBM Quad Flat Package Random Access Memory The temporary memory that a computer uses to hold the instructions and data currently being worked with All data in RAM is lost when the computer is turned off
26. a command by entering NV NV ST would cause the monitor to run the self test but show only the names of the subtests and the results pass fail Switch Directories Command SD To leave the diagnostic directory and disable the diagnostic tests enter SD At this point only the commands for EPPCBug function When in the EPPCBug directory the prompt reads EPPC Bug gt To return to the diagnostic directory the command SD is entered again When in the diagnostic directory the prompt reads EPPC Diag gt The purpose of this feature is to allow you to access EPPCBug without the diagnostics being visible 2 7 2 Diagnostic Utilities Stop On Error Mode Prefix SE It is sometimes desirable to stop a test or series of tests at the point where an error is detected SE accomplishes that for most of the tests To invoke SE enter it before the test or series of tests that is to run in Stop On Error mode Self Test Command ST and QST The monitor provides an automated test mechanism called self test This mechanism runs all the tests included in an internal self test directory The command HE ST lists the top level of the self test directory in alphabetical order Each test is described later in this manual QST operates in the same manner as ST except a lesser number of RAM tests are run This reduces the amount of time needed to complete selftest Clear Zero Error Counters Command ZE The erro
27. ace Battery Backed up Random Access Memory Having big endian and little endian byte ordering capability A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered left to right 0 1 2 3 with 0 being the most significant byte Basic Input Output System This is the built in program that controls the basic functions of communications between the processor and the I O peripherals devices Also referred to as ROM BIOS Bit Boundary BLock Transfer A type of graphics drawing routine that moves a rectangle of data from one area of display memory to another The data specifically need not have any particular alignment BLock Transfer The term more commonly used to refer to a PCB printed circuit board Basically a flat board made of nonconducting material such as plastic or fiberglass on which chips and other electronic components are mounted Also referred to as a circuit board or card bits per inch bits per second The pathway used to communicate between the CPU memory and various input output devices including floppy and hard disk drives Available in various widths 8 16 and 32 bit with accompanying increases in speed A high speed memory that resides logically between a central processing unit CPU and the main memory This temporary memory holds the data and or GL 2 Glossary instructions that the
28. al interconnect bus which allows peripherals adhering to the standard to be plugged in and used without further system modification PCI Configuration Register Processor Direct Slot PCI Host Bridge A binary address that refers to the actual location of information stored in secondary storage PCI to ISA Bridge An acronym for picture element and is also called a pel A pixel is the smallest addressable graphic ona display screen In RGB systems the color of a pixel is defined by some Red intensity some Green intensity and some Blue intensity Phase Locked Loop PCI Mezzanine Card Performance Optimized With Enhanced RISC architecture IBM The trademark used to describe the Performance Optimized With Enhanced RISC microprocessor architecture for Personal Computers developed by the IBM Corporation PowerPC is superscalar which means it can handle more than one instruction per clock cycle Instructions can be sent simultaneously to three types of independent execution units branch units fixed point units and floating point units where they can execute concurrently but finish out of order PowerPC is used by Motorola Inc under license from IBM The first implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 256 entry buffer and a 32KB unified instruction and data cache It provides a 64 bit data bus and a separate 32 bit address bus PowerPC 601 is used by Motorol
29. an external loopback plug connected to the 1OBASE T connector The AULOOP test requires an external loopback plug connected to the AUI header SCC1ETH SCC1 Ethernet Tests ADDR Ethernet Address Command Input EPPC Diag gt SCCl1ETH ADDR Description This test verifies that the ethernet address stored in the Vital Product Data Serial ROM is a valid Motorola ethernet address Valid Motorola ethernet addresses start with 0x08003E Response Messages After the command has been issued the following line is printed SCC1ETH ADDR Ethernet Address Running gt If all parts of the test are completed correctly then the test passes SCC1ETH ADDR Ethernet Address Running gt PASSED If any part of the test fails then the display appears as follows SCC1ETH ADDR Ethernet Address Running gt FAILED SCC1ETH ADDR Test Failure Data error message Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning Test Descriptions AULOOP AUI Connector External Loopback Command Input EPPC Diag gt SCC1ETH AULOOP Description This test verifies that the signal path through the AUI header is operating correctly by transmitting and receiving packets and comparing the data This test requires the presence of an external loopback plug in
30. ay It provides up to 256 simultaneous colors and a screen resolution of 640 x 480 pixels A binary address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the virtual address See VESA Local bus VL bus MCG second generation VMEbus interface ASIC Motorola MCG ASIC that interfaces between the PCI bus and the VMEchip2 device A memory in which the data content is lost when the power supply is disconnected Video Dynamic Random Access Memory Memory chips with two ports one used for random accesses and the other capable of serial accesses Once the serial port has been initialized with a transfer cycle it can operate independently of the random port This frees the random GL 13 lt DrPonworya lt D gt rPownoryd Glossary Windows NT XGA Y Signal port for CPU accesses The result of adding the serial port is a significantly reduced amount of interference from screen refresh VRAMs cost more per bit than DRAMs The trademark representing Windows New Technology a computer operating system developed by the Microsoft Corporation EXtended Graphics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Luminance This determines the brightness of each spot pixel ona CRT screen
31. bugger system memory cannot be allocated for use as a save area for the BBRAM contents D1350 ADR Test Failure Data 3 4 Test Descriptions Test Initialization Error Not Enough Memory Need Actual If the BBRAM cannot be initialized with pattern a D1350 ADR Test Failure Data Data Verify Error Address Expected Actual __ Memory initialization error If a pattern b write affects any BBRAM location other than the test address D1350 ADR Test Failure Data Data Verify Error Address Expected Actual __ Memory addressing error DS13xxY Battery Backed Up RAM Tests Battery Low Test BTLOW Command Input EPPC Diag gt d1350 BTLOW Description D1350 BTLOW This test checks the status of the onboard battery of the D13xxY chip Response Messages After the command has been issued the following line is printed D1350 BT D1350 BT D1350 BT If any p LOW LOW art of the test fails LOW DS DS DS 350 Battery 350 Battery 350 Battery Low Battery Status Low Test Low Test Low Test Running gt If all parts of the test are completed correctly then the test passes Running gt PASSED then the display appears as follows Running gt FAILED 3 6 Test Descriptions Battery Backed Up RAM RAM D1350 RAM Command Input EPPC Diag gt d1350 RAM Description This test perf
32. byte boundary if necessary Memory in the test range is filled with all ones FFFFFFFF For each location in the test range the following patterns are used 00000000 01010101 03030303 07070707 SOFOFOFOF S1IF1F1F1F S3F3F3F3F 7F7F7F7F Each location in the test range is individually written with the current pattern and the 1 s complement of the current pattern Each write is read back and verified This test is coded to use only 32 bit data entities Response Messages After the command has been issued the following line is printed RAM PATS Patterns visi sssesesven Running gt If all parts of the test are completed correctly then the test passes RAM PATS Patieiniss no nbwiwsdscueet Running gt PASSED If the test fails then the display appears as follows RAI PATS Patten cs wcieis ese incie alee aie 9 6 Running gt FAILED Data Miscompare Error Address Expected Actual RAM Local RAM Tests PED Local Parity Memory Error Detection Command Input EPPC Diag gt RAM PED Description The memory range and address increment is specified by the RAM test directory configuration parameters Refer to CF Test Group Configuration Parameters Editor First each memory location to be tested has the data portion verified by writing verifying all zeros and all ones Each memory location to be tested is tested once with parity interrupt disabled and
33. ction describes the individual PCI ISA Bridge tests Entering ISAB without parameters causes all ISAB tests to execute in the order shown in the following table To run an individual test add that test name to the ISAB command The individual tests are described in alphabetical order on the following pages Table 3 4 ISAB Test Group Name Description REG Register IRQ Interrupt 3 9 ISAB PCI ISA Bridge Tests IRQ Interrupt Command Input PPC1 Diag gt ISAB IRQ Description This test verifies that the ISA Bridge can generate interrupts Response Messages After the command has been issued the following line is printed ISAB IRO ENtErrUpts iea ean aa erste a cere Running gt If all parts of the test are completed correctly then the test passes ISAB TRO INtCenrupt es ects eases eens Ba are Se Running gt PASSED If any failures occur the following is displayed more descriptive text then follows TSAB TRO Enternupts salves aioe 4 8 wal eid od asala Running gt FAILED If the test fails because an interrupt request from the ISA Bridge is pending after masking the interrupt in the IEN register the following is displayed ISAB IRQ Test Failure Data Unexpected ISAB IRQ pending Address Expected Actual This test makes use of the ISA Bridge counters to generate the test interrupt If after running the counters to terminal count an in
34. ction in the loopback path including the loopback connector if one is required If this error occurs during the TPLOOP test it may indicate that the length of the loopback cable is too short Transmit buffer size d should be d to d inclusive Proceeding anyway This warns the user that the transmit buffer size has been changed by using the CF SCCIETH command to a value outside of the range allowed by the protocol 3 45 SCCI1ETH SCC1 Ethernet Tests Table 3 10 SCC1ETH Error Messages Continued Error Message Sizes are dif ferent Sent packet size d t size d Received pack Symptom or Cause An incorrect number of bytes was received based on the size of the transmitted loopback packet Note that normally the size of the received packet is four bytes greater than the size of the transmitted packet due to the addition of the frame checksum Send receive Received d data miscompare XX The loopback packet received differs from the loopback packet transmitted at the index d Only the first few occurrences of this error will be displayed Bad ethernet address The ethernet address stored in the Vital Product Data Serial ROM does not begin with 0x08003E It may be un initialized or corrupted Bad ethernet address length Internal firmware error 3 46 Test Descriptions Table 3 10 SCC1ETH Error Messages Continued
35. dditional information such as digitized photographs on a CD ROM after a prior recording session has ended A video system in which every pixel is refreshed during every vertical scan A non interlaced system is normally more expensive than an interlaced system of the same resolution and is usually said to have a more pleasing appearance A memory in which the data content is maintained whether the power supply is connected or not National Television Standards Committee USA Non Volatile Random Access Memory Original Equipment Manufacturer Over Molded Pad Array Carrier Operating System The software that manages the computer resources accesses files and dispatches programs One Time Programmable The range of colors available on the screen not necessarily simultaneously For VGA this is either 16 or 256 simultaneous colors out of 262 144 A connector that can exchange data with an I O device eight bits at a time This port is more commonly used for the connection of a printer to a system Peripheral Component Interconnect local bus Intel A high performance 32 bit internal interconnect bus used for data transfer to peripheral controller components such as those for audio video and graphics GL 8 Glossary PCMCIA bus PCR PDS PHB physical address PIB pixel PLL PMC POWER PowerPC PowerPC 601 Personal Computer Memory Card International Association bus A standard extern
36. directory For example to bring up a menu of all the memory tests enter HE RAM When a menu is too long to fit on the screen it pauses until the operator presses the carriage return lt CR gt again To review a description of an individual test enter the full name i e HE RAM CODE displays information on the RAM Code Execution Copy test routine The Help screen is shown in the following figure EPPC Diag gt he AEM Append Error Messages Mode CEM Clear Error Messages CF Configuration Editor D1350 DS1350 BBRAM DIR DE Display Errors DEM Display Error Messages DP Display Pass Count HE Help on Tests Commands HEX Help Extended ISAB ISA Bridge Tests DIR LA Loop Always Mode Utilities LC Loop Continuous Mode LE Loop on Error Mode LF Line Feed Mode LN Loop Non Verbose Mode LPT Super I O Parallel Port DIR NV Non Verbose Mode PCIB PCI Bridge Tests DIR QST Quick Self Test DIR RAM Random Access Memory Tests DIR SCC1ETH SCC1 Ethernet DIR SE Stop on Error Mode ST Self Test DIR ZE Zero Errors ZP Zero Pass Count EPPC Diag gt Figure 2 1 Help Screen Help Extended Command HEX The HEX command goes into an interactive continuous mode of the HE command The syntax is HEX lt CR gt The prompt displayed for HEX is the You may then type the name of a directory or command Type QUIT to exit Loop Always Mode Prefix LA To endlessly repeat a test or series of tests enter t
37. dulation Musical Instrument Digital Interface The standard format for recording storing and playing digital music Multimedia Personal Computer The PowerPC to PCI bus bridge chip developed by Motorola for the Ultra 603 Ultra 604 system board It provides the necessary interface between the MPC603 MPC604 processor and the Boot ROM secondary cache the DRAM system memory array and the PCI bus Motorola s component designation for the PowerPC 601 microprocessor Motorola s component designation for the PowerPC 603 microprocessor Motorola s component designation for the PowerPC 604 microprocessor Multi Processor Interrupt Controller MicroProcessing Unit Mean Time Between Failures A statistical term relating to reliability as expressed in power on hours poh It was originally developed for the military and can be calculated GL 7 lt DrPonwory lt Dronoryd Glossary multisession non interlaced nonvolatile memory NTSC NVRAM OEM OMPAC Os OTP palette parallel port PCI local bus several different ways yielding substantially different results The specification is based on a large number of samplings in one place running continuously and the rate at which failure occurs MTBF is not representative of how long a device or any individual device is likely to last nor is ita warranty but rather a gauge of the relative reliability of a family of products The ability to record a
38. e bit at a time It may operate synchronously or asynchronously and may include start bits stop bits and or parity Serial Interface Module Single Inline Memory Module A small circuit board with RAM chips normally surface mounted on it designed to fit into a standard slot GL 11 lt DrPonworyn lt DrPonoryd Glossary SIO SMP SMT software SRAM SSBLT standard s SVGA Teletext thick Ethernet thin Ethernet twisted pair Ethernet UART Super I O controller Symmetric MultiProcessing A computer architecture in which tasks are distributed among two or more local processors Surface Mount Technology A method of mounting devices such as integrated circuits resistors capacitors and others on a printed circuit board characterized by not requiring mounting holes Rather the devices are soldered to pads on the printed circuit board Surface mount devices are typically smaller than the equivalent through hole devices A computing system is normally spoken of as having two major components hardware and software Software is the term used to describe any single program or group of programs languages operating procedures and documentation of a computer system Software is the real interface between the user and the computer Static Random Access Memory Source Synchronous BLock Transfer A set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware
39. e internal error message buffer of the diagnostic monitor The AEM command sets the internal append error messages flag of the diagnostic monitor When the internal append error messages flag is clear the diagnostic error message buffer is erased cleared of all character data before each test is executed The duration of this command is for the life of the command line being parsed by the diagnostic monitor The default of the internal append error messages flag is clear The internal flag is not set until it is encountered in the command line by the diagnostic monitor Clear Error Messages Command CEM This command clears the internal error message buffer of the diagnostic monitor 2 2 Utilities Test Group Configuration cf Parameters Editor Command CF The cf parameters control the operation of all tests in a test group For example the RAM test group has parameters such as starting address ending address parity enable etc At the time of initial execution of the diagnostic monitor the default configuration parameters are copied from the firmware into the debugger work page Here you can modify the configuration parameters using the CF command When you invoke the CF command you are prompted with a brief parameter description and the current value of the parameter You may enter a new value for that parameter or a carriage return to proceed to the next configuration parameter You may also specify one or more test grou
40. e complete television picture frame consists of 525 horizontal lines with the NTSC system One frame consists of two Fields On EGA and VGA a section of circuitry that can provide hardware assist for graphics drawing algorithms by performing logical functions on data written to display memory Hardware Abstraction Layer The lower level hardware interface module of the Windows NT operating system It contains platform specific functionality GL 5 lt DrPonworyn lt DrPonory Glossary hardware HCT 1 0 IBC IDC IDE IEEE interlaced IQ Signals ISA bus ISASIO A computing system is normally spoken of as having two major components hardware and software Hardware is the term used to describe any of the physical embodiments of a computer system with emphasis on the electronic circuits the computer and electromechanical devices peripherals that make up the system Hardware Conformance Test A test used to ensure that both hardware and software conform to the Windows NT interface Input Output PCI ISA Bridge Controller Insulation Displacement Connector Integrated Drive Electronics A disk drive interface standard Also known as ATA Advanced Technology Attachment Institute of Electrical and Electronics Engineers A graphics system in which the even scanlines are refreshed in one vertical cycle field and the odd scanlines are refreshed in another vertical cycle The advantage is that t
41. e san sirens ore dea asda die 8 Running gt PASSED If any failures occur the following is displayed more descriptive text then follows PCGIB REG REGU SECT stae ea i e a a Na Running gt FAILED If the test fails because the pattern written does not match the data read back from the PCIB register the following is printed PCIB REG Test Failure Data Data Miscompare Error Address Expected _ Actual _ RAM Local RAM Tests RAM Local RAM Tests These sections describe the individual Random Access Memory RAM tests Entering RAM without parameters causes all RAM tests to execute in the order shown in the table below To run an individual test add that test name to the RAM command The individual tests are described in alphabetical order on the following pages Table 3 8 RAM Test Group Name Description QUIK Quick Write Read ALTS Alternating Ones Zeros PATS Data Patterns ADR Memory Addressing CODE Code Execution Copy PERM Permutations RNDM Random Data BTOG Bit Toggle PED Parity Error Detection REF Memory Refresh Test Descriptions ADR Memory Addressing Command Input Description EPPC Diag gt RAM ADR This is the memory addressability test the purpose of which is to verify addressing of memory in the range specified by the configuration parameters for the RAM test group Addressing errors are sought by usi
42. followed by the name of an individual test from that group causes just that test to execute For example to call up a particular Random Access Memory RAM test enter EPPC Diag gt RAM ADR This causes the monitor to find the RAM test group subdirectory and then to execute the Memory Addressing test command ADR from that subdirectory To call up a particular SCC1ETH test enter EPPC Diag gt SCC1ETH ADDR This causes the monitor to find the SCC1ETH test group subdirectory and then to execute the ADDR subtest from that subdirectory Multiple Subdirectory Level Commands Individual Tests If the first part of acommand is a test group name any number and or sequence of tests from that test group may be entered after the test group name so long as the debugger s input buffer size limit is not exceeded For example EPPC Diag gt RAM PATS ADR This causes both the Data Patterns PATS and the Memory Addressing ADR tests from the RAM test group to execute 1 4 Overview of EPPCBug Firmware Multiple Root Level Commands Test Groups Multiple commands may be entered If a command expects parameters and another command is to follow it separate the two with a semicolon For example to invoke the command SCC1ETH ADDR after the command RAM ADR the command line would read EPPC Diag gt RAM ADR SCC1ETH ADDR Spaces are not required before or after the semicolon but are shown here for legibili
43. ght Motorola Inc 1998 All Rights Reserved Printed in the United States of America January 1998 Contents Introduction 1 1 Overview of EPPCBug Firmware 1 2 Debugger and Diagnostic Directories 1 2 Command Entry 1 3 Introduction 2 1 Utilities 2 1 Append Error Messages Mode Command AEM 2 2 Clear Error Messages Command CEM 2 2 Test Group Configuration cf Parameters Editor Command CF 2 3 Display Error Counters Command DE 2 3 Display Error Messages Command DEM 2 3 Display Pass Count Command DP 2 4 Help Command HE 2 4 Help Extended Command HEX 2 5 Loop Always Mode Prefix LA 2 5 Loop Continue Mode Prefix LC 2 6 Loop On Error Mode Prefix LE 2 6 Line Feed Suppression Mode Prefix LF 2 6 Loop Non Verbose Mode Prefix LN 2 7 Non Verbose Mode Prefix NV 2 7 Switch Directories Command SD 2 7 Stop On Error Mode Prefix SE 2 8 Self Test Command ST and QST 2 8 Clear Zero Error Counters Command ZE 2 8 Zero Pass Count Command ZP 2 8 DS13xxY Battery Backed Up RAM Tests 3 2 D1350 Configuration Parameters 3 3 BBRAM Addressing ADR 3 4 Battery Low Test BLOW vscsiatonseisssesenranscigatcaasanasibes D1350 BTLOW 3 6 Battery Backed Up RAM RAM cccsesssesssstssersesssssssenesenes D1350 RAM 3 7 ISAB PCI ISA Bridge Tests 3 9 IRQ Interrupt 3 10 REG Register 3 11 LPT Super I O Parallel Port Tests 3 12 IRQ Parallel Port Interrupt 3 13 LPT Error Messages 3 15 PCIB PCI ISA Bridge Tests 3 17 IR
44. he video bandwidth is roughly half that required for a non interlaced system of the same resolution This results in less costly hardware It also may make it possible to display a resolution that would otherwise be impossible on given hardware The disadvantage of an interlaced system is flicker especially when displaying objects that are only a few scanlines high Similar to the color difference signals R Y B Y but using different vector axis for encoding or decoding Used by some USA TV and IC manufacturers for color decoding Industry Standard Architecture bus The de facto standard system bus for IBM compatible computers until the introduction of VESA and PCI Used in the reference platform specification IBM ISA Super Input Output device GL 6 Glossary ISDN LAN LED LFM little endian MBLT MCA bus MCG MFM MIDI MPC MPC105 MPC601 MPC603 MPC604 MPIC MPU MTBF Integrated Services Digital Network A standard for digitally transmitting video audio and electronic data over public phone networks Local Area Network Light Emitting Diode Linear Feet per Minute A byte ordering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte Multiplexed BLock Transfer Micro Channel Architecture Motorola Computer Group Modified Frequency Mo
45. he following publications are applicable to the EPPC module series and may provide additional helpful information If not shipped with this product they may be purchased by contacting your Motorola sales office Motorola Document Title Publication Number EPPCBug Firmware Package User s Manual EPPCBUGA1 UMI1 Motorola and the Motorola symbol are registered trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders The software described herein and the documentation appearing herein are furnished under a license agreement and may be used and or disclosed only in accordance with the terms of the agreement The software and documentation are copyrighted materials Making unauthorized copies is prohibited by law No part of the software or documentation may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means without the prior written permission of Motorola Inc DISCLAIMER OF WARRANTY Unless otherwise provided by written agreement with Motorola Inc the software and the documentation are provided on an as is basis and without warranty This disclaimer of warranty is in lieu of all warranties whether express implied or statutory including implied warranties of merchantability or fitness for any particular purpose Copyri
46. he prefix LA The LA command modifies the way that a failed test is endlessly repeated The LA command has no effect until a test failure occurs at which time if the LA command has been previously encountered in the user command line the failed test is endlessly repeated Diagnostic Utilities To break the loop press the BREAK key on the diagnostic video display terminal Certain tests disable the BREAK key interrupt so pressing the RESET switch or power cycling the MBX board may become necessary Loop Continue Mode Prefix LC To endlessly repeat a test or series of tests enter the prefix LC This loop includes everything on the command line To break the loop press the BREAK key on the diagnostic video display terminal Certain tests disable the BREAK key interrupt so pressing the RESET switch or power cycling the MBX board may become necessary Loop On Error Mode Prefix LE Occasionally when an oscilloscope or logic analyzer is in use it becomes desirable to endlessly repeat a test loop while an error is detected The LE command modifies the way that a failed test is endlessly repeated The LE command has no effect until a test failure occurs at which time if the LE command has been previously encountered in the user command line the failed test is re executed as long as the previous execution returned failure status To break the loop press the BREAK key on the diagnostic video display terminal Certain tests d
47. hts in Technical Data and Computer Software clause at DFARS 252 227 7013 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 9602 Preface This manual provides general information and a description of the diagnostic firmware for the EPPCBUG Debugging Package Use of the EPPC debugger the debugger command set use of the one line assembler disassembler and system calls for the Debugging Package are all described in the EPPCBUG Debugging Package User s Manual This manual is intended for anyone who wants to design OEM systems supply additional capability to an existing compatible system or work in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed To use this manual you should be familiar with the publications listed in the Related Documentation section found in the following pages Manual Terminology Throughout this manual a convention has been maintained whereby data and address parameters are preceded by a character which specifies the numeric format as follows dollar specifies a hexadecimal number percent specifies a binary number amp ampersand specifies a decimal number For example 12 is the decimal number twelve and 12 is the decimal number eighteen Unless otherwise specified all address references are in hexadecimal throughout this manual An asterisk following the signal name for signals which are level signif
48. icant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows T Abyte is eight bits numbered 0 through 7 with bit 0 being the most significant T A two byte is 16 bits numbered 0 through 15 with bit 0 being the most significant For the MBX and other PowerPC modules this is called a half word T A four byte is 32 bits numbered 0 through 31 with bit 0 being the most significant For the MBX and other PowerPC modules this is called a word T An eight byte is 64 bits numbered 0 through 63 with bit 0 being the most significant For the MBX and other PowerPC modules this is called a double word Throughout this document it is assumed that the MPU on the MBX module series is always programmed with big endian byte ordering as shown below Any attempt to use little endian byte ordering will render the EPPCBug debugger unusable BIT BIT 00 07 08 15 16 23 24 31 ADRO ADR1 ADR2 ADR3 32
49. ifies the 16 byte block using 8 bit 16 bit and 32 bit access modes Response Messages After the command has been issued the following line is printed RAM PERM Permutations Running gt If all parts of the test are completed correctly then the test passes RAM PERM Permutations Running gt PASSED If the test fails then the display appears as follows RAI PERM Permutations Running gt FAILED Data Miscompare Error Address Expected Actual Test Descriptions QUIK Quick Write Read Command Input EPPC Diag gt RAM QUIK Description Each pass of this test fills the test range with a data pattern by writing the current data pattern to each memory location from a local variable and reading it back into that same register The local variable is verified to be unchanged only after the write pass through the test range This test uses a first pass data pattern of 0 and FFFFFFFF for the second pass This test is coded to use only 32 bit data entities Response Messages After the command has been issued the following line is printed RAI QUIK Quick Write Read Running gt If all parts of the test are completed correctly then the test passes RAI QUIK Quick Write Read Running gt PASSED If the test fails then the display appears as follows RAI QUIK Quick Write Read
50. is able to perform much faster than the standard ISA bus system Enhanced Parallel Port GL 4 Glossary EPROM ESCC ESD Ethernet Falcon fast Ethernet FDC FDDI FIFO firmware frame graphics controller HAL Erasable Programmable Read Only Memory A memory storage device that can be written once per erasure cycle and read many times Enhanced Serial Communication Controller Electro Static Discharge Damage A local area network standard that uses radio frequency signals carried by coaxial cables The DRAM controller chip developed by Motorola for the MVME2600 and MVME3600 series of boards It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144 bit ECC DRAM system memory array and or ROM Flash See 100Base TX Floppy Disk Controller Fiber Distributed Data Interface A network based on the use of optical fiber cable to transmit data in non return to zero invert on 1s NRZI format at speeds up to 100 Mbps First In First Out A memory that can temporarily hold data so that the sending device can send data faster than the receiving device can accept it The sending and receiving devices typically operate asynchronously The program or specific software instructions that have been more or less permanently burned into an electronic component such as a ROM read only memory or an EPROM erasable programmable read only memory On
51. is not functioning properly one of the following is printed RAM REF Test Failure Data RTC is stopped invoke SET command or Test Descriptions RAM REF Test Failure Data RTC is in write mode invoke SET command or RAM REF Test Failure Data RTC is in read mode invoke SET command If a data verification error occurs before the refresh wait cycle RAM REF Test Failure Data Immediate Data Miscompare Error Address Expected Actual If a data verification error occurs following the refresh wait cycle RAM REF Test Failure Data Unrefreshed Data Miscompare Error Address Expected Actual 3 33 RAM Local RAM Tests RNDM Random Data Command Input EPPC Diag gt RAM RNDM Description The test block is the memory range specified by the RAM test group configuration parameters The test proceeds as follows 1 A random pattern is written throughout the test block 2 The random pattern complemented is written throughout the test block 3 The complemented pattern is verified 4 The random pattern is rewritten throughout the test block 5 The random pattern is verified This test is coded to use only 32 bit data entities Each time this test is executed the random seed in the RAM test group configuration parameters is post incremented by 1 Response Messages After the command has been issued the following line i
52. isable the BREAK key interrupt so pressing the RESET switch or power cycling the MBX board may become necessary Line Feed Suppression Mode Prefix LF The LF command sets the internal line feed mode flag of the diagnostic monitor The default state of the internal line feed mode flag is clear which causes the executing test title status line s to be terminated with a line feed character scrolled The duration of the LF command is the life of the user command line in which it 2 6 Utilities appears The line feed mode flag is normally used by the diagnostic monitor when executing a system mode self test Although rarely invoked as a user command the LF command is available to the diagnostic user Loop Non Verbose Mode Prefix LN The LN command modifies the way that a failed test is endlessly repeated The LN command has no effect until a test failure occurs at which time if the LN command has been previously encountered in the user command line further printing of the test title and pass fail status is suppressed This is useful for more rapid execution of the failing test i e the LN command contributes to a tighter loop Non Verbose Mode Prefix NV Upon detecting an error the tests display a substantial amount of data To avoid having to watch the scrolling display EPPCBug includes a mode that suppresses all messages except PASSED or FAILED This mode is called non verbose and is invoked prior to calling
53. lobal random data seed is incremented after it is used by this test This test uses the following test data pattern generation algorithm 1 Random data seed is copied into a work register 2 Work register data is shifted right one bit position 3 Random data seed is added to work register using unsigned arithmetic 4 Data in the work register may or may not be complemented 5 Data in the work register is written to current memory location If the RAM test directory configuration parameter for code cache enable equals Y the microprocessor code cache is enabled This test is coded to operate using the 32 bit data size only Each memory location in the specified memory range is written with the test data pattern Each memory location in the specified memory range is then written with the test data pattern complemented before it is written The memory under test is read back to verify that the complement test data is properly retained Each memory location in the specified memory range is then written with the test data pattern The memory under test is read back to verify that the test data is properly retained Response Messages After the command has been issued the following line is printed Test Descriptions RAI BIOG Bit Toggle sess axe o cea erates 2 ne Ee us aE Running gt If all parts of the test are completed correctly then the test passes RAI BTOGs Bit Togglerssrt e ena ea a bi aE Running
54. ng a memory locations address as the data for that location This test is coded to use only 32 bit data entities The test proceeds as follows 1 2 A Locations Address is written to its location n The next location n 4 is written with its address complemented The next location 8 is written with the most significant MS 16 bits and least significant LS 16 bits of its address swapped with each other Steps 1 2 and 3 are repeated throughout the specified memory range The memory is read and verified for the correct data pattern s and any errors are reported The test is repeated using the same algorithm as above steps 1 through 5 except that inverted data is used to insure that every data bit is written and verified at both 0 and 1 Response Messages After the command has been issued the following line is printed RAM ADR Addressability Running gt If all parts of the test are completed correctly then the test passes RAM ADR Addressability Running gt PASSED If the test fails then the display appears as follows RAM Local RAM Tests RAM ADR Addressability Data Miscompare Address y Error Expected i TERESE ETES Running gt FAILI Actual 3 22 Test Descriptions ALTS Alternating Ones Zeros Command Input EPPC Diag gt RAM ALTS Description This
55. nworyn lt DrPonoryn Glossary CPU DCE DLL DMA DOS dpi DRAM DTE ECC ECP EEPROM EIDE EISA bus EPP Central Processing Unit The master computer unit in a system Data Circuit terminating Equipment Dynamic Link Library A set of functions that are linked to the referencing program at the time it is loaded into memory Direct Memory Access A method by which a device may read or write to memory directly without processor intervention DMA is typically used by block I O devices Disk Operating System dots per inch Dynamic Random Access Memory A memory technology that is characterized by extreme high density low power and low cost It must be more or less continuously refreshed to avoid loss of data Data Terminal Equipment Error Correction Code Extended Capability Port Electrically Erasable Programmable Read Only Memory A memory storage device that can be written repeatedly with no special erasure fixture EEPROMs do not lose their contents when they are powered down Enhanced Integrated Drive Electronics An improved version of IDE with faster data rates 32 bit transactions and DMA Also known as Fast ATA 2 Extended Industry Standard Architecture bus IBM An architectural system using a 32 bit bus that allows data to be transferred between peripherals in 32 bit chunks instead of 16 bit or 8 bit that most systems use With the transfer of larger bits of information the machine
56. once with parity interrupt enabled Parity checking is enabled and data is written and verified at the test location that causes the parity bit to toggle on and off verifying that the parity bit of memory is good Next data with incorrect parity is written to the test location The data is read and if a parity error exception does occur the fault address is compared to the test address If the addresses are the same the test passed and the test location is incremented until the end of the test range has been reached Response Messages After the command has been issued the following line is printed RAM PED Local Parity Memory Detection Running gt If the board under test does not support Parity error detection the test is bypassed RAI PED Local Parity Memory Detection Running gt BYPASS If all parts of the test are completed correctly then the test passes RAI PED Local Parity Memory Detection Running gt PASSED If any part of the test fails then the display appears as follows RAI PED Local Parity Memory Detection Running gt FAILED error message Here error message is one of the following Test Descriptions If a data verification error occurs RAM PED Test Failure Data Data Miscompare Error Address Expe cted Actual If an unexpected exception such as a parity error being detected as the parity bit was
57. or software development Super Video Graphics Array IBM An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 800 x 600 pixels One way broadcast of digital information The digital information is injected in the broadcast TV signal VBI or full field The transmission medium could be satellite microwave cable etc The display medium is a regular TV receiver See 10base 5 See 10base 2 See 10Base T Universal Asynchronous Receiver Transmitter GL 12 Glossary Universe UV UVGA ASIC developed by Tundra in consultation with Motorola that provides the complete interface between the PCI bus and the 64 bit VMEbus UltraViolet Ultra Video Graphics Array An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Vertical Blanking Interval VBI VESA bus VGA virtual address VL bus VMEchip2 VME2PCI volatile memory VRAM The time it takes the beam to fly back to the top of the screen in order to retrace the opposite field odd or even VBI is in the order of 20 TV lines Teletext information is transmitted over 4 of these lines lines 14 17 Video Electronics Standards Association or VL bus An internal interconnect standard for transferring video information to a computer display system Video Graphics Array IBM The third and most common monitor standard used tod
58. orms a data test on each RAM location of the Dallas DS13xxY Zeropower RAM RAM contents are unchanged upon completion of test regardless of pass or fail test return status This test is coded to test only byte data entities The test proceeds as follows 1 For each of the following patterns 55 aa 33 cc 0 and ff 2 For each valid byte of the Zeropower RAM 3 Write and verify the current data test pattern 4 Write and verify the complement of the current data test pattern Response Messages After the command has been issued the following line is printed D1350 RAM DS1350Y Battery Backed Up RAM Running gt If all parts of the test are completed correctly then the test passes D1350 RAM DS1350Y Battery Backed Up RAM Running gt PASSED If any part of the test fails then the display appears as follows D1350 RAM DS1350Y Battery Backed Up RAM Running gt FAILED error message Here error message is one of the following If debugger system memory cannot be allocated for use as a save area for the BBRAM contents 3 7 DS13xxY Battery Backed Up RAM Tests D1350 RAM Test Failure Data Test Initialization Error Not Enough Memory Need Actual If there is a problem with an address the location and values are printed out Address 00000 Expected 55 Actual 53 Test Descriptions ISAB PCI ISA Bridge Tests This se
59. ps as argument s immediately following the CF command If no arguments follow the CF command the parameters for all test groups are listed for possible change Display Error Counters Command DE Each test or command in the diagnostic monitor has an individual error counter As errors are encountered in a particular test that error counter is incremented If you were to run a self test or just a series of tests the results could be broken down as to which tests passed by examining the error counters To display all errors enter DE DE displays the results of a particular test if the name of that test follows DE Only nonzero values are displayed Display Error Messages Command DEM This command displays dumps the internal error message buffer of the diagnostic monitor 2 3 2 Diagnostic Utilities Display Pass Count Command DP A count of the number of passes in Loop Continue LC mode is kept by the monitor This count is displayed with other information at the conclusion of each pass To display this information without using LC enter DP Help Command HE On line documentation has been provided in the form of a Help command syntax HE command name This command displays a menu of the top level directory and test group names if no parameters are entered or a menu of the subdirectory if the name of a subdirectory is entered The top level directory lists DIR after the name of each command that has a sub
60. r counters originally come up with the value of zero but it is occasionally desirable to reset them to zero at a later time This command resets all of the error counters to zero The error counters can be individually reset by entering the specific test name following the command Example ZE RAM CODE clears the error counter associated with RAM CODE Zero Pass Count Command ZP Invoking the ZP command resets the pass counter to zero This is frequently desirable before typing in a command that invokes the Loop Continue mode Entering this command on the same line as LC results in the pass counter being reset every pass 2 8 Test Descriptions Detailed descriptions of EPPCBug s diagnostic tests are presented in this chapter The test groups are described in the order shown in the following table Table 3 1 Diagnostic Test Groups Test Group Description D1350 DS1350 BBRAM ISAB ISA Bridge Tests LPT Super I O Parallel Port PCIB PCI Bridge Tests RAM Random Access Memory Tests SCC1ETH SCC1 Ethernet Note You may enter command names in either uppercase or lowercase 3 1 DS13xxY Battery Backed Up RAM Tests DS13xxyY Battery Backed Up RAM Tests This section describes the battery backed up RAM tests These tests check the RAM and battery status of the DS13xxY chips Entering D1350 without parameters causes all BBRAM tests to execute in the order shown in the table below To run an indi
61. s RTC ADR 3 4 RTC RAM 3 7 RTC test group 3 1 S SCC Device Register Access ACCESS 3 39 IN 17 Index SCC External Loopback ELPBCK 3 39 SCC Internal Loopback ILPBCK 3 13 3 36 SCC tests 3 35 SD switch directories command 2 7 SE stop on error mode command 2 8 self test explained 2 8 Self Test Command ST 2 8 Self Test Mask 2 7 Serial Communication Controller SCC Z85230 Tests 3 12 signal path 10BaseT 3 42 spaces when entering multiple commands 1 5 SRAM tests 3 20 ST self test command 2 8 static RAM tests 3 20 Stop On Error Mode Prefix SE 2 8 Switch Directories Command SD 2 7 T test 10BaseT signal path 3 42 AUI connector 3 37 control register access 3 40 Ethernet controller 3 35 for valid ethernet address 3 36 frequency of ethernet transmitter clock 3 41 signal path 3 38 signal path with SCC1 3 39 test errors number encountered 2 3 Test Group Configuration cf Parame ters Editor Command CF 2 3 test group execution 1 4 test group names via Help 2 4 test groups diagnostic 3 1 test parameters examples 2 3 modifying 2 3 test repeating 2 5 tests disable 2 7 stop at fail 2 8 toggle bits 3 24 tuning D1350 test parameters 3 3 U utilities 2 1 utility commands AEM command 2 2 CEM command 2 2 CF command 2 3 DE command 2 3 DEM command 2 3 DP command 2 4 HEX command 2 5 LA prefix 2 5 LC prefix 2 6 LE prefix 2 6 LF prefix 2 6 LN prefix 2 7 NV prefix 2 7 SD command 2 7 SE
62. s of the test are SCC1ETH I OO If any part of the test fails then the dis SCC1ETH I OO SCC1ETH JI OO P Interfac P Interfac Transceiver completed Transceiver P Interfac Transceiver P Test Failure Data error message Loopbac Running gt correctly then the test passes Loopbac Loopbac play appears as follows Running gt PASSED Running gt FAILED Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning Test Descriptions ILOOPQ Interface Transceiver Loopback SQE Command Input EPPC Diag gt SCC1ETH ILOOPQ Description This test verifies the signal path through the on board ethernet transceiver device while Signal Quality Error testing is enabled in SCC1 and the transceiver The ethernet transceiver is operated in internal loopback mode The test transmits and receives packets and compares the data For Signal Quality Error testing the transceiver is configured to generate a collision detect pulse after each transmission and Heartbeat Checking is enabled in SCC1 Response Messages After the command has been issued the following line is printed SCC1ETH ILOOPQ Interface Transceiver Loopback SQE Running gt If all parts of the test are completed correctly then the test passes SCC1ETH ILOOPQ Interface
63. s printed RAI RNDM Random Data sere iene Se EER ra Running gt If all parts of the test are completed correctly then the test passes RAI RNDM Random Data soe sses aea Enae E Running gt PASSED If the test fails then the display appears as follows RAI RNDM Random Data eee eee ee eee Running gt FAILED Data Miscompare Error Address Expected Actual Test Descriptions SCC1ETH SCC1 Ethernet Tests These sections describe the individual on board SCC1 Ethernet Controller tests Entering SCC1ETH without parameters causes all SCC1ETH tests to run in the order shown in the table below except as noted To run an individual test add that test name to the SCCIETH command The individual tests are described in alphabetical order on the following pages Table 3 9 SCC1ETH Test Group Name Description ADDR Ethernet Address REGA Transceiver Control Register Access TCLK Transmit Clock Frequency ILOOP Interface Transceiver Loopback ILOOPQ Interface Transceiver Loopback SQE Executed only when specified TPLOOP 10BaseT Connector External Loopback AULOOP AUI Connector External Loopback The ADDR REGA TCLK ILOOP ILOOPQ tests do not require are not affected by and do not interfere with the connection to an active ethernet through the 10BASE T connector or the AUI connector The TPLOOP test requires
64. so referred to as thicknet Also known as thick Ethernet An Ethernet implementation in which the physical medium is a single shielded 50 ohm RG58A U coaxial cable capable of carrying data at 10 Mbps for a length of 185 meters also referred to as AUI or thinnet Also known as thin Ethernet An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters Also known as twisted pair Ethernet An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 100 Mbps for a maximum distance of 100 meters Also known as fast Ethernet Asynchronous Communications Interface Adapter Advanced Interactive eXecutive IBM version of UNIX The main overall design in which each individual hardware component of the computer system is interrelated The most common uses of this term are 8 bit 16 bit or 32 bit architectural design systems American Standard Code for Information Interchange This is a 7 bit code used to encode alphanumeric information In the IBM compatible world this is expanded to 8 bits to encode a total of 256 alphanumeric and control characters GL 1 lt DrPoOnoryD Glossary ASIC AUI BBRAM bi endian big endian BIOS BitBLT BLT board bpi bps bus cache Application Specific Integrated Circuit Attachment Unit Interf
65. t menu which may be called using the HE command In addition some utilities have subfunctions and as such have subfunction menus Debugger and Diagnostic Directories When using EPPCBug you operate out of either the debugger directory or the diagnostic directory a Ifyouare in the debugger directory the debugger prompt EPPC Bug gt is displayed and you have all of the debugger commands at your disposal a If you are in the diagnostic directory the diagnostic prompt EPPC Diag gt is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands To use the diagnostics you must be in the diagnostic directory If the prompt EPPC Bug gt is displayed you are in the debugger directory and must switch to the diagnostic directory by entering SD the debugger s Switch Directories command The diagnostic prompt EPPC Diag gt is then be displayed You may examine the commands in the particular directory that you are currently in by using the Help HE command The Help HE command displays a menu of all available diagnostic functions i e the tests and utilities Several tests have a subtest 1 2 Overview of EPPCBug Firmware menu which may be called using the HE command In addition some utilities have subfunctions and as such have subfunction menus Command Entry To invoke a diagnostic command enter the name of the diagnostic command when the prompt EPPC Diag gt appears
66. terrupt has not been requested by the ISAB the following message is displayed ISAB IRQ Test Failure Data ISAB IRQ not pending in IST register Address Expected Actual Test Descriptions REG Register Command Input PPC1 Diag gt ISAB REG Description This test verifies that the ISAB registers can be written and read Data patterns verify that every read write bit can be modified Response Messages After the command has been issued the following line is printed ISAB REG REGUSECL seek woes te oles ieee Soe ee ener de Running gt If all parts of the test are completed correctly then the test passes TSAB REG REgI SCEE a e erres sari ese dua ea a died Running gt PASSED If any failures occur the following is displayed more descriptive text then follows ISAB REG 2 REGUSECE ia cece d n e e EE E ES Running gt FAILED If the test fails because the pattern written does not match the data read back from the ISAB register the following is printed ISAB REG Test Failure Data Register xxx Miscompare Error Address Expected _ Actual _ LPT Super I O Parallel Port Tests LPT Super I O Parallel Port Tests This section describes the individual Super I O Parallel Port tests Entering LPT without parameters causes all LPT tests to run in the order shown in the table below except as noted To run an individual test add that test name to the LPT
67. test verifies addressing of memory in the range specified by the configuration parameters for the RAM test group Addressing errors are sought by using a memory locations address as the data for that location This test is coded to use only 32 bit data entities The test proceeds as follows 1 Location n is written with data of all bits 0 2 The next location 1 4 is written with all bits 1 3 Steps 1 and 2 are repeated throughout the specified memory range 4 The memory is read and verified for the correct data pattern s and any errors are reported Response Messages After the command has been issued the following line is printed RAM ALTS Alternating Ones Zeroes Running gt If all parts of the test are completed correctly then the test passes RAI ALTS Alternating Ones Zeroes Running gt PASSED If the test fails then the display appears as follows RAI ALTS Alternating Ones Zeroes Running gt FAILED Data Miscompare Error Address Expected Actual RAM Local RAM Tests BTOG Bit Toggle Command Input EPPC Diag gt RAM BTOG Description The memory range is specified by the RAM test directory configuration parameters Refer to CF Test Group Configuration Parameters Editor in Chapter 2 The RAM test directory configuration parameters also determine the value of the global random data seed used by this test The g
68. the AUI header Note Itis recommended that the board under test not be connected to a live network while this test is running The suggested loopback setup for this test is to connect pins of the 16 pin AUI header as follows connect pin 5 to pin 9 and connect pin 4 to pin 8 Response Messages After the command has been issued the following line is printed SCC1ETH AULOOP AUI Connector External Loopback Running gt If all parts of the test are completed correctly then the test passes SCC1ETH AULOOP AUI Connector External Loopback Running gt PASSED Dy If any part of the test fails then the display appears as follows SCC1ETH AULOOP AUI Connector External Loopback Running gt FAILE Dy iw SCC1ETH AULOOP Test Failure Data error message Refer to the section SCC1ETH Error Messages for a list of the error messages and their meaning SCC1ETH SCC1 Ethernet Tests LOOP Interface Transceiver Loopback Command Input Description EPPC Diag gt SCCl1ETH ILOOP This test verifies the signal path through the on board ethernet transceiver device The ethernet transceiver is operated in internal loopback mode The test transmits and receives packets and compares the data Response Messages After the command has been issued the following line is printed SCC1ETH I OO If all part
69. ty Spaces are required between commands and their arguments Several commands may be combined on one line General Information 1 6 Diagnostic Utilities Introduction This chapter contains descriptions and examples of the various diagnostic utilities available in EPPCBug The diagnostic tests are described in the Test Descriptions chapter Utilities In addition to individual or sets of tests the diagnostic package provides the utilities listed in the next table and described on the following pages These utilities are root level commands to the diagnostic monitor and do not require a preceeding test group name Table 2 1 Diagnostic Utilities Mnemonic Description AEM Append Error Messages Mode CEM Clear Error Messages CF Test Group Configuration cf Parameters Editor DE Display Error Counters DEM Display Error Messages DP Display Pass Count HE Help HEX Help Extended LA Loop Always Mode LC Loop Continue Mode 2 1 Diagnostic Utilities Table 2 1 Diagnostic Utilities Continued Mnemonic Description LE Loop On Error Mode LF Line Feed Suppression Mode LN Loop Non Verbose Mode NV Non Verbose Mode QST Quick Self Test SD Switch Directories SE Stop On Error Mode ST Self Test ZE Clear Zero Error Counters ZP Zero Pass Count Append Error Messages Mode Command AEM This command allows you to accumulate error messages in th
70. vidual test add that test name to the D1350 command The individual tests are described in alphabetical order on the following pages Table 3 2 BBRAM Test Group Mnemonic Description RAM Battery Backed Up RAM ADR BBRAM address test BTLOW Battery Low Test 3 2 Test Descriptions D1350 Configuration Parameters Command Input EPPC Diag gt cf d1350 D1350 Configuration Data ADR test Restore BBRAM contents on test exit N Y Y BBRAM SIZE 32 128 512 Kbytes 32 Description User configurable test parameters are available for the D1350 test group The CF command may be used to tune these parameters The DS1350 test parameters are listed in the command input block above and described below ADR test Restore BBRAM contents on test exit N Y Y If this parameter is Y then the contents of the Battery Backup RAM will be restored to its state prior to the running of this test upon exit Otherwise the RAM will be modified upon exit BBRAM SIZE 32 128 512 Kbytes 32 This parameter needs to contain the size of the BBRAM chip onboard or smaller in Kilobytes If a smaller size is specified the BBRAM will only be partially tested To determine the size of the specific BBRAM find the correct size to the corresponding part number in the following table Table 3 3 BBRAM Memory Sizes BBRAM Part Number BBRAM Size DS1330 32K DS1345 128K DS1350 512K 3 3 DS13xxY

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EPPCBug™ Diagnostic Firmware User's Guide - ps