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High-Speed Microcontroller User's Guide

1. ou mo 0 J o o 8 o s 0 __ hi TH 1 o0 E c Td 8Dh CKCON 90h 0 SPECIAL SPECIAL SPECIAL 91h scono 98h SBUO 9 __ SADDRO 2 0 SBUL 0 1 1 Ch 0 1 STATUS Im v 4 RCADL 0 m2 0 LI 0 DE Jj PSW
2. 153 TIMED ACCESS PROTECTS ak haa ha ka a aaa ak ku usa Rn 154 RESL TIME GLOG K reer re M da Ma 156 SIARTING AND STOPPING THE R O 157 SETTING AND READING THE RTC TIME 157 WSNG THE RTO ALARM MUR 158 USING THE DAY OF THE WEEK 9 159 ORS 159 a 160 en 161 ABAT IERT tu ac a 161 LITHIUM BATTERY CONSIDERATIONS 162 INSTRUCTION SET DETAILS i e idi 47 163 RR MERRRERME RMRR RE E MEM ERE MEM MEN ra REM MA MERKEN BREAK R En ME EUER ERE 171 DEVICE OPERATES AT ONE THIRD THE CRYSTAL 1 171 DEVICE RESETS FOR NO REASON ee rhe bb Pl Yee Efe ea e e or 171 ACCESS TO INTERNAL MOVX SRAM IS 0 171 REAL TIME CLOCK DOES NOT
3. 66 TIU EORL ener kb REDE Ea Rt La dica Dole dn ER IAE Mei n e bli 67 Three Cycle E E 69 Four Fr Fore Pe MN OT naana iE E i R 70 Ingimebon TIBI DR Hn RI iR RII HG C 71 Fogom Memory c Poe Pet 80 Program Memory SEES 80 Data Memory Imera O T TT 81 Full Speed MOVX quie utbs te tret 85 c3 MOVA NIS P 86 s Nera M e ENERO TU TT 87 Power Eo if v dr MEN to m 90 Internal Timing Relationships in PMM T tb i dh Febre BUR Ll ida Fabi lp aa 97 Interrupt Functional Descripflai us rege bcr aO po 110 Pono MOT DO m ETT 113 Lens eb forte Du e Tia Ao LIN Mna KT sai bon OON RN 114 VO Port Timing Tor MOV Ml iuri t 117 Timer Counter o and 1 Modes 0 and 121 Timer coume O and T eek 122 Timer Counter 0 Mode 3 2 1 00c02 cccccnecessecessaccesnncesnedessucnssnsensnecessucessecostadonsuetasnasestanceesnce 123 Timer Counter 2 with Optional 126 Timet Gounter 2 Auto Reload 128 Timer Counter 2 Baud Rate Generator
4. INSTRUCTION CODE MNEMONIC D D D D D D D HEX BYTE CYCLE EXPLANATION RLA 0 0 1 0 0 0 1 1 23 1 1 The contents of the accumulator are rotated left by one bit RLCA 0 0 1 0 0 1 33 1 1 2 The contents of the 2 accumulator are rotated E right by one bit 2 RRA 0 0 0 0 0 0 1 1 03 1 1 Laminin gt The contents of the Q accumulator are rotated O right by one bit Q lo 1 1 1 Ed The contents of the accumulator are rotated right by one bit SWAPA 1 1 0 0 0 10 0 C4 1 1 gt 1 1 1 0 m n E8 EF 1 1 Rn 1 1 1 0 0 10 1 5 2 2 A direct direct Byte 2 MOV A Ri 1 1 1 0 0 1 1 1 E6 E7 1 1 A Ri 0 1 1 1 0 10 0 74 2 2 A data data d 4 ds 4 4 d d do Byte 2 MOVRn A 1 1 1 1 m n F8 FF 1 1 1 0 1 0 1 mnm n no A8 AF 2 2 Rn direct direct Byte 2 0 1 1 1 1 mnm n no 78 7F 2 2 Rn data data d dg ds 4 4 d di do Byte 2 MOV direct 1 1 1 1 0 10 1 F5 2 2 direct A Byte2 MOV diret 1 0 0 0 1 m m m 888F 2 2 direct Rn 2 Rn as Byte 2 5 MOVdirectl 1 0 0 0 0 10 1 85 3 3 direct1 direct2 direct2 a 2 source
5. tA ate 137 i220 Seral Control 0 Register SCONO 98 AA 138 1222 Sena Por Gon 7 Register SCONT COP 139 1223 ME I n Regata PCON E T IT 140 1224 Watchdog Control Register DEEN uai en irren ape ra be rk 140 1225 Timer Two Regist r T2CON s or 140 12 3 qp ccc TP REE 140 HIS NE oo Do 140 HINCR EM o2 Do 141 ONE oo Pid E AEE 141 ENS ICH DESCRIPTION E opaca uU RACER TRIER E 143 D X oo e 143 EE o Ee 145 41 oo D E 147 2 ________ ___ _________ 149 030308 5 of 175 High Speed Microcontroller User s Guide 12 5 12 6 13 13 1 13 2 13 3 14 14 1 14 2 14 8 14 4 14 5 14 6 15 15 1 15 2 16 17 17 2 17 3 17 4 17 5 17 6 18 18 1 18 2 18 3 18 4 19 FRAMING ERROR 149 MULTIPROCESSOR COMMUNICATION 1 44 44 enhn ENES 151 TMED ACCESS PROTECTION iei Reb de abdo Rd dk RM dirti 153 153 PROTECTION
6. mp o Cb of o WDCON ACC ER o 030308 18 01175 High Speed Microcontroller User s Guide Table 4 0580 320 0580 323 SFR Locations REGISTER DPH DPLI SMO WD IE __ SEL P TLOO 1 5 0 SMODO 0 T 5 0 pod TFO M GATE CT 104 1 0 1 1 0 0 aC E 3 __ 5 IE M T T T MD T T M GAT C T T T T T TH1 T TOM MD RO T 0 0 THLS THI3 TOM MDI MDO RGMD RGSL BGS SCONO SBUFO SADDRO SADDRI P PS PT2 0 PXI PTO B8h SADENO SADENI SADENI7 SADENI6 SADENI5 SADENI4 SADENI3 SCONI SMOFE SBUFI _ SBUF1 7 2 RI RI RCAP2L 1 E 0 0 DO TFO MI TLO THO 1 5 0 T2M 4 IE3 5 ENIA ENI3 SM2_ 5 5 A 3 STATUS 1 7 T2CON TF2 Be T20E DCEN
7. a Rag oat x na 76 Bc INTERVAL DATA ENO 76 6 2 1 ROME NT poer mE Ga PROGRAM MEMORY INTERCONNECT 78 6 4 DATA MEMORY INTERCONNECT 4 1 00020 00000 000000 0001 00000000 79 ms DATA MENOR uota oH A FEE CER PR C TET DEI TRO 81 6 5 1 54 Byte Block Move With Dual Data isi ie edite tenis et E eee eee 82 852 b4 Byte Block Move Without Dual Data Pomer Mae E 83 De noo dna CRI DR ORE GATA 84 T POWER MANAGEMENT 88 7 1 POWER MANAGEMENT FEATURE G c 0ssesccscssercssensescusensnsensencesenceseusencusessencesusseneusaventensavensannars 88 d Warming POWER Fant II DE sen peti tr rer bye Be asian Fe iE 88 Rie FONR PI c Rv 89 PORNO M1 oc PROMPT 89 89 c c 91 Power Management Sd You ces berum rimi Ree ir e tpe EU Ha 91 T2 FOWER tet P TRE 93 721 rq MM Mp 93 GE oor oos c 93 fea S ior UNICI divis Pers T Ow 94 7 3 MANAGEMENT MODES re rk t aa RETE HE 95 7 8 1 Management Mode TNNG m innr EENAA 96 Loz uc vir P
8. sen EXIF e frr me ma ms ra mo Am SADDRIH SADDRDS SADDRUT Ash Lm pnr prm mo DE 1 L Scowi swomr swri so T RENT Tes T cm ems RMSI RMSO o o LXTOFF saus f me f ue xro serai spral serao meom ee OR a Lux om ome rr Acc ACC acce accs acca Accs ACC2 acci acco Eon HE s7 B B3 B2 Bo Fon m i CKCON ea Note Shaded bits are timed access protected Rev 030308 21 of 175 High Speed Microcontroller User s Guide Table 4 0583 520 0587 520 SFR Reset Values 8 1 1 31 1 __5 gt j 1 sh 0 0 wu o w o a L o o _ 0 5 ps 0
9. 0 0 8 bits with 5 bit prescale Mode 1 16 bits Mode 2 8 bits with auto reload 0 0 1 1 Mode 3 Timer 1 is halted but holds its count Timer 0 Gate Control This bit enables disables that ability of Timer 0 to increment 0 Timer 0 will clock when TRO 1 regardless of the state of INTO 1 Timer 0 will clock only when TRO 1 and INTO 1 Timer 0 Counter Timer Select 0 Timer 0 incremented by internal clocks 1 Timer 0 is incremented by pulses on TO when TRO TCON 4 is 1 Timer 0 Mode Select These bits select the operating mode of Timer 0 When Timer 0 is in mode 3 TLO is started stopped by TRO and THO is started stopped by Run control from Timer 1 is then provided via the Timer 1 mode selection M1 Mode Mode 0 8 bits with 5 bit prescale Mode 1 16 bits Mode 2 8 bits with auto reload olo Mode 3 Timer 0 is two 8 bit counters 29 of 175 High Speed Microcontroller User s Guide 4 2 11 Timer 0 LSB TLO 7 6 5 4 3 2 1 0 SFR 8Ah TLO 7 11 0 6 TLO 5 TLO 4 TLO 3 TLO 2 TLO 1 11 0 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset TL0 7 TLO0 0 Timer 0 LSB This register contains the le
10. 030308 110 of 175 High Speed Microcontroller User s Guide 9 7 Interrupt Register Conflicts During normal operation there is a small but finite probability that application software may try to read or modify a register associated with interrupt functions at the same time that the interrupt hardware is modifying the register In general these hardware software interrupt conflicts are resolved according to the hardware wins philosophy In the event of a conflict the hardware modification of a register will take precedence over the software action to ensure that the interrupt event is not missed Software should always use read modify write instructions when modifying registers associated with interrupt functions This special class of instructions evaluates and modifies register contents in a single instruction preventing the hardware from accidentally modifying a bit between the time it is read and when it is written back to the register One specific case involves a software write to the IP IE EIP or EIE registers while the internal interrupt hardware is processing an interrupt request Interrupt sources are normally executed i e the LCALL instruction is performed during the instruction following their detection If an interrupt is detected during a write to one of the previously mentioned registers it 1 possible that it will be delayed for one additional instruction When the instruction 18 processed the interrupt wil
11. 7 6 5 4 3 2 1 0 SFR BAh SADENI 7 SADENI 6 SADEN1 5 SADEN1 4 SADENI 3 SADENI2 1 SADEN1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SADENI 7 Slave Address Mask Enable Register 1 This register functions as a mask when SADEN1 0 comparing serial port 1 addresses for automatic address recognition When a bit in this Bits 7 0 register is set the corresponding bit location in the SADDRI register will be exactly compared with the incoming serial port 1 data to determine if a receiver interrupt should be generated When a bit in this register is cleared the corresponding bit in the SADDRI register becomes a don t care and is not compared against the incoming data All incoming data will generate a receiver interrupt when this register is cleared 4 2 29 Serial Port Control 5 1 7 6 5 4 3 2 1 0 SFR COh SMO FE_1 SMI 1 SM2 1 REN 1 TB8 1 RB8 1 TI 1 RI 1 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SM0 SM1 SM2 Serial Port 1 Mode These bits control the mode of serial port 1 as shown below In Bits 7 6 5 addition the 5 0 and SM2 bits have secondary functions as shown below B c xem ZI 1 2 Asynchronous with multiprocessor T 64tcLK SMOD 0 communication 3 SMOD 1 1 1 3 Asynchron
12. M1 0 0 0 Mode 0 8 bits with 5 bit prescale 0 1 Mode 1 16 bits 1 0 Mode 2 8 bits with auto reload 1 1 Mode 3 Timer 1 stopped Bit 3 Timer 0 Gate Control GATE When GATE 1 Timer 0 will clock only when INTO and TRO 1 When GATE 0 Timer 0 will clock only when TRO 1 irrespective of INTO Bit 2 Counter Timer Select C T When C T is set to a 0 Timer 0 is incremented by internal clocks When C T 1 set to a 1 Timer 0 counts based on the TO P3 4 pin Bits 1 and 0 Timer 0 Mode Select Bit 1 and 0 M 1 0 M1 0 0 0 Mode 0 8 bits with 5 bit prescale 0 1 1 16 bits 1 0 Mode 2 8 bits with auto reload 1 1 Mode 3 Timer 0 is two 8 bit timers 030308 119 of 175 High Speed Microcontroller User s Guide 11 1 2 Timer Counter Control Register TCON Summary 7 6 5 4 3 2 1 0 88h TF1 0 0 IE1 IT1 0 Bit 7 Timer 1 Overflow Flag TF1 Set to 1 when Timer 1 overflows from FFh and cleared when the processor vectors to the interrupt service routine Bit 6 Timer 1 Run Control TR1 Turns on Timer when this bit is set Bit 5 Timer 0 Overflow Flag TF0 Set to 1 when Timer 0 overflows from FFh and cleared when the processor vectors to the interrupt service routine Bit 4 Timer 0 Run Control TRO Turns on Timer 0 when this bit is set to 1 Bit 3 Interrupt
13. WDCON 0 SPECAL 0 __ 0 SPECIAL SPECIAL 0 ACC o 0o Eh 030308 22 of 175 High Speed Microcontroller User s Guide Table 4 G DS87C530 SFR Locations PO PO7 POS 4 PO2 POI POO DPLI D 5 un DPHI __ o o o M STOP DE 87h TRO ITI _ MO GATE MI 10 5 W E TMOD p TCON TRI MI TLOS TLL THO TFO MI TLO THL CKCON TIM TOM MDO 8Eh_ 6 TRM2 0 1 0 HO MD2 PL 90h EXIF 15 184 12 XT RG RGMD RGSL BGS 12 6 TRM2 TRM2 TRMO TRMO 96 SCONO 98h S i AD ODO T D 4 D PCON SMODO 5 G 0 0 0 TLO THO IE2 RM2 EN 0 SBUFO 99h SADDRO A9h SADDRI BOh L Po PII Pro SADENO SCONI ROMSIZE Ch PMR CDI cDo SWB XTOFF ALEOFF DME DMEO STATUS
14. Et em bait Em Pe La oa 48 Jio MORI E Aee E ME E ATUM 49 424 Control aspect E EE A 50 ZG DR AGGI Loud ssp 54 Enana EIE E 52 Lr er 52 4 246 Real Time Alarm Subsecond Register 95 52 4247 Real Time Alarm Second Register RTAS uu eei 53 4 2 48 Real Time Alarm Minute Register 53 4249 Hoa Time Hour Register esa eere antea eximi qb HAE MUR EX 53 4258 Extended PITONIY HERP 54 4201 RealTime Clock Control Register APC uie ee uae ERR EXE RR 55 4 2 52 Real Time Clock Subsecond Register RTCSS 56 425 RealTime Second Register IH TOS 57 4254 RealTime Clock Minute Register Laien tae 57 4295 RealTime Clock Hour Register R TCH AE 57 4256 RealTime Clock Day Reg
15. 030308 MAKII High Speed Microcontroller User s Guide SERIAL PORTS RUN UP TO 1Mbps MORE POWER INTERRUPT LATENCY UP TO 3x THROUGHPUT EFFICIENT lt 400ns WITH SAME CRYSTAL MAXIM Maxim Integrated Products 1 High Speed Microcontroller User s Guide TABLE OF CONTENTS 1 gir rl erg or eee eerte mette t 9 2 ORDERING INFORMA TIDN e iaiia dadddedddnd ded dndddeddndedekaddndddeddnddekadel ire 10 3 P H Y 11 11 FUNGON REGISTERS OFRO 11 ded JOURS enia D PRONUM UE 11 MEN E oomen if 22 Vo WE a eTA eae 11 med Za DE 11 doo o mt 11 coca MEER AU o c erm 11 o out so EA E eA A ERA 12 VC MEE I ________ _____ 12 12 ALT SBO 12 cos P 12 VR C MEL oi COUET er a R 12 BATS Addresa Data BUS 12 VR MEM eso TINO enaere aeaaee A i E a a a AEA 12 FOWE POE TAE 12 A
16. THEN PC rel and 1 CJNE Rn 1 0 1 1 m n 8 3 4 3 data rel d dg 5 4 4 4 do Byte 2 IF lt I Ig I5 1 B Byte 3 THEN PC rel and C 0 OR IF data gt Rn THEN PC rel and 1 QRi 1 0 1 1 0 1 1 i B6 B7 3 4 3 data rel d dg 5 4 4 4 di do Byte 2 IF lt Ri I I6 15 t Byte 3 THEN PC rel and C 0 OR IF data gt Ri THEN PC rel and 1 030308 169 175 High Speed Microcontroller User s Guide INSTRUCTION CODE MNEMONIC D D D D D D D D HEX BYTE CYCLE EXPLANATION DJNZ rel 1 1 0 1 1 m n n D8 Df 2 3 PC PC 2 I 15 14 I HH To Byte 2 Rn Rn 1 IF z 0 THEN PC PC rel DJNZ 1 1 0 1 0 10 1 05 3 4 3 a Byte2 direct direct 1 fj Te Ts T4 do Byte3 IF direct 0 THEN PC PC rel NOP 0 0 0 0 0 0 0 0 00 1 1 PO 1 030308 170 of 175 High Speed Microcontroller User s Guide 17 TROUBLESHOOTING 17 1 Device Operates at One Third the Crystal Speed The high speed microcontroller family operates from the primary or fundamental mode of the external crystal Many off the shelf high frequency cry
17. SAL SPICE SPECIAL SPECIAL SAL SHORE ER SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL 5 SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL S The descriptions for each bit indicates its read and write access as well as its state after a power on reset Bits that are affected by a no battery reset are also indicated Note that many bits and registers are unique to specific devices and their functions will vary between different members of the high speed microcontroller family 4 2 1 Port 0 PO 7 6 5 4 3 2 1 0 SFR 80h P0 7 P0 6 0 5 P0 4 P0 3 P0 2 1 0 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset P0 7 P0 0 Bits 7 0 Port 0 This port functions as a multiplexed address data bus during external memory access and as a generalpurpose port on devices which incorporate internal program memory During external memory cycles this port will contain the LSB of the address when ALE is high and data when ALE is low 4 2 2 Stack Pointer SP 7 6 5 4 3 2 1 0 SFR 81h SP 7 SP 6 SP 5 SP 4 SP 3 SP 2 SP 1 5 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset SP 7 SP 0 Bits 7 0 030308 Stack Pointer This stack pointer identifies t
18. 1 to 0 transition on this pin will cause the value in the 2 and T2MOD registers to be transferred into the capture registers if enabled by EXEN2 T2CON 3 When in auto reload mode a 1 to 0 transition on this pin will reload the timer 2 registers with the value in RCAP2L and RCAP2H if enabled by EXEN2 T2CON 3 Timer 2 External Input 1 0 0 transition on this pin will cause timer 2 increment or decrement depending on the timer configuration 32 of 175 High Speed Microcontroller User s Guide 4 2 17 SFR 91h External Interrupt Flag EXIF 7 6 5 4 3 2 1 0 5 4 2 XT RG RGMD RGSL BGS RW 0 RW 0 RW 0 RW 0 RW R RW RT 0 R Unrestricted Read W Unrestricted Write T 2 Timed Access Write Only n Value after Reset See description TES Bit 7 IEA Bit 6 Bit 5 Bit4 XT Bit 3 RGMD Bit 2 RGSL Bit 1 Rev 030308 External Interrupt 5 Flag This bit will be set when a falling edge is detected on INTS This bit must be cleared manually by software Setting this bit in software will cause an interrupt if enabled External Interrupt 4 Flag This bit will be set when a rising edge is detected on INT4 This bit must be cleared manually by software Setting this bit in software will cause an interrupt if enabled External Interrupt 3 Flag This bit will be set when a falling edge is detected on INT3 This bit must be cleared ma
19. EXF2 TIMER 2 pe T2CON 6 INTERRUPT 2 T2CON 3 11 8 Time Base Selection The high speed microcontroller allows the user to select either 4 or 12 clocks as the time base for each timer independently When using the 16 bit Timer Counters in timer mode the timer counter counts the oscillator cycles divided by a predetermined number In the standard 8051 the 8051 timers count the oscillator divided by 12 which is the standard 8051 machine cycle timing The high speed microcontroller allows the option of setting the timers to operate from a divide by 4 of the input clock to allow higher precision timing and faster baud rates This selection has no effect on CPU timing only on the timers Following a reset the timers default to 12 clocks as the time base to remain drop in compatible with the original 8051 The 4 or 12 clock decision is independent for each timer and the default is 12 clocks per timer tick As an example a user might select both the baud rate generator timer and one other timer to run at 12 clocks per timer tick with the third timer at 4 clocks per tick This allows one timer to measure higher speed events or to gain better resolution The control bits for the time base selection are located in the Clock Control register CKCON 8Eh Timer 2 will function at 2 clocks per tick when set for baud rate generation or clock output as described above When the time base is derived from an external source 1 the TO
20. RCAP2L RCAP2L7 RCAP2L6 2 5 RCAP2L4 RCAP2L3 RCADLI RCAP2LO CAh RCAPOH RCAP2H7 PSW AC ro RS OV FI P Doh WDCON SMOD 1 EX4 B B7 BS B2 BO PWD PXS PX3 Note Shaded bits are timed access protected 030308 19 of 175 High Speed Microcontroller User s Guide Table 4 D 0580 320 0580 323 SFR Reset Values L SP Sh o 88h pH 09 o 9 0 0 Ds 0 sh PCON o sh NM 0 865 8 o J o 9 o 8r m o Dh CKCON LP 1 1 9h _ scono oo m Ca T
21. o nu o i Rh o o 9 L WEE 0 0 60 0 0 0 _ 60 d PON ee TMOD L o J oo 0 r o 0o Joo ee ee ee ee _ sCh m 1 LP 1 _1 1 1 1 1 1 90 C lt JI 1 m scono 98 L Bom o o v 09 9 Lom qoo po 1 1E _ _ Tw _ SADDRO o 1 1 1 1 1 1 SADENO o o 0 1 f r 1 1 Ch ROFERIEEUOENONE E o o CA RCADH o o
22. 13 EE TNO Ca 13 IO ME Pu e X 13 a219 SUMMAN MP 13 4 PROGRAMMING MODEL ee 14 4 1 ORGANIZATION E 14 E N E EEN T EA E A N EIE E EE T 14 E RODEO T EEE EASE 14 42 SPECIAL FUNCTION REGISTERS 2 17 25 IIT 25 uc TT 26 EE inr spe 26 Do oe ue co EON c 26 ALD 26 5 0014 HT 27 TN 27 420 ssn sa sindbis HABE ba iaa ue xd bos dai hse Red B 28 Commo P 29 TOOLSE ie pe 30 30 30 30 Ve oct 21 FO TIE n tec 32 T A 33 113 RTO fs E Um 34 LEA HE olus wipes cu SCONO M EAEE 35 4220 EMEND EE HER 36 D
23. 52 of 175 High Speed Microcontroller User s Guide 4 2 47 SFR F3h Real Time Alarm Second Register RTAS 7 6 5 4 3 2 1 0 0 0 RTAS 5 RTAS 4 RTAS 3 RTAS 2 RTAS 1 RTAS 0 RW 0 RW 0 RW RW RW RW RW RW R Unrestricted Read W Unrestricted Write n Value after Reset See description Bits 7 6 Reserved These bits will be 0 when read RTAS 5 RTAS 0 Real Time Alarm Second These bits represent the second alarm that will be compared Bits 5 0 against the RTC Second register RTCS FBh The ability of a match between the two registers to cause an alarm is controlled by the RTC Second Register Compare Enable bit RTCC 6 This register should only be loaded with values from 0 to 3Bh 0 to 59 seconds The contents of this register will be indeterminate following a no battery reset except bits 7 6 and unchanged by all other forms of reset 4 2 48 Real Time Alarm Minute Register RTAM 7 6 5 4 3 2 1 0 SFR F4h 0 0 RTAM 5 4 RTAM 3 2 1 RTAM O 0 0 RW RW RW RW RW RW R Unrestricted Read W Unrestricted Write n Value after Reset See Description Bits 7 6 Reserved These bits will be 0 when read 5 0 Real Time Alarm Minute These bits represent the minute alarm that will be compared Bits 5 0 against the RTC Minute register RTCM FCh The abil
24. Bits 7 0 030308 Accumulator This register serves as the accumulator for arithmetic operations It is functionally identical to the accumulator found in the 80C32 51 of 175 High Speed Microcontroller User s Guide 4 2 44 SFR E8h Extended Interrupt Enable EIE 7 6 5 4 3 2 1 0 ERTCI EWDI EX5 EX4 EX3 EX2 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Bits 7 6 ERTCI Bit 5 EWDI Bit4 5 Bit 3 4 Bit 2 EX3 Bit 1 EX2 Bit 0 4 2 45 SFR FOh R Unrestricted Read W Unrestricted Write n Value after Reset B 7 B 0 Bits 7 0 4 2 46 SFR F2h Reserved Read data will be indeterminate Real Time Clock Interrupt Enable This bit enables disables the real time clock interrupt on the DS87C530 This bit will read 0 on all other devices 0 Disable the real time clock interrupt 1 Enable interrupt requests generated by the real time clock Watchdog Interrupt Enable This bit enables disables the watchdog interrupt 0 Disable the watchdog interrupt 1 Enable interrupt requests generated by the watchdog timer External Interrupt 5 Enable This bit enables disables external interrupt 5 0 Disable external interrupt 5 1 Enable interrupt requests generated by the INTS pin External Interrupt 4 Enable This bit enables disables external interrupt 4 0 Disable external interr
25. 2 030308 106 of 175 High Speed Microcontroller User s Guide 9 2 2 Timer Interrupts The high speed microcontroller incorporates three 16 bit programmable timers each of which can generate an interrupt In addition some members of the family incorporate a programmable watchdog timer The three programmable timers operate in the same manner as the 80C52 Each timer has an independent interrupt enable flag vector and priority The watchdog timer also has its own interrupt enable flag and priority Timers 0 1 and 2 will set their respective flags when the timer overflows from a full condition depending on its mode This flag will be set regardless of the interrupt enable state If the interrupt is enabled this event will also cause a jump to the corresponding interrupt vector For timers 0 and 1 the flags are cleared when the processor jumps to the interrupt vector Thus these flags are not available for use by the interrupt service routine ISR but are available outside of the ISR and in applications that do not acknowledge the interrupt 1 jump to the vector If the interrupt is not acknowledged then software must manually clear the flag bit In timer 2 jumping to the interrupt vector does not clear the flag so software must always clear it manually Timer 0 and 1 flag bits reside in the TCON register Timer 2 flag bit resides in the T2CON register The interrupt enables and priorities for timers 0 1 and 2 resid
26. The Program Counter PC is a 16 bit value that designates the next program address to be fetched On chip hardware automatically increments the PC value to move to the next ROM location 3 2 13 Address Data Bus The high speed microcontroller addresses a 64kB program and 64kB data memory area In the ROMless versions all memory is outside Other versions use a combination of internal and external memory When external memory is accessed Ports 0 and 2 are used as a multiplexed address and data bus Port 2 provides the address MSB Even versions with internal memory can use the bus on Ports 0 and 2 to access more memory 3 2 14 Watchdog Timer The watchdog timer provides a supervisory function for applications that cannot afford to run out of control The watchdog timer is a programmable free running timer If allowed to reach the termination of its count if enabled the watchdog resets the CPU Software must prevent this by cleaning or resetting the watchdog prior to its timeout 3 2 15 Power Monitor Some members of the high speed microcontroller family incorporate a bandgap reference and analog circuitry to monitor the power supply conditions When begins to drop out of tolerance the power monitor issues an optional early warning power fail interrupt If power continues to fall the power 030308 12 of 175 High Speed Microcontroller User s Guide monitor invokes a reset condition This remains until power returns to
27. DPHI 85h High byte new DPTRI DPS 86h DPTR Select LSb The example program listed below was original code written for an 8051 and requires a total of 1869 machine cycles on the DS80C320 This takes 299us to execute at 25MHz The new code using the Dual DPTR requires only 1097 machine cycles taking 175 5us The Dual DPTR saves 772 machine cycles or 123 5us for a 64 byte block move Since each pass through the loop saves 12 machine cycles when compared to the single DPTR approach larger blocks gain more efficiency using this feature A typical application of the Dual Data Pointer is moving data from an external RAM to a memory mapped display Another application would be to retrieve data from a stored table process it using a software algorithm and store the result in a new table 6 5 1 64 Byte Block Move With Dual Data Pointer SH and SL are high and low byte source address DH and DL are high and low byte of destination address DPS is the data pointer select Reset condition DPTRO CYCLES DPS EQU 86h TELL ASSEMBLER ABOUT DPS MOV R5 64 NUMBER OF BYTES TO MOVE 2 MOV DPTR DHDL LOAD DESTINATION ADDRESS 3 INC DPS CHANGE ACTIVE DPTR 2 MOV DPTR SHSL LOAD SOURCE ADDRESS 2 MOVE THIS LOOP IS PERFORMED R5 TIMES IN THIS EXAMPLE 64 MOVX A DPTR READ SOURCE DATA BYTE 2 INC DPS CHANGE DPTR TO DESTINATION 2 MOVX DPTR WRITE DATA TO DESTINATION 2 INC DPTR NEXT DESTINATION ADDRESS 3 INC DPS CHA
28. This may have one or two bytes Examples of both types are shown below ANL direct data 53h 3 bytes 247 480 47 40 SJMP rel 80h 2 bytes 7 A3h 1 byte In the first example the first memory fetch is the op code The second is the location of the destination register The third memory fetch is the operand that is used by the instruction This instruction has three memory accesses so it requires three machine cycles The second example has the operand in the first byte and the jump location in the second It requires three cycles to actually perform the jump The third example contains simply the op code which is 1 byte This instruction involves the manipulation of a 16 bit register so it takes longer than 8 bit operations Figure 5 5 shows the timing of all three types of three cycle instructions 030308 67 of 175 High Speed Microcontroller User s Guide 5 6 4 Four Cycle Instructions four cycle instructions require more time than the associated number of bytes These are all program branching instructions that can move program control to a new location The four cycle instructions use either 1 or 3 bytes as shown in the following examples Figure 5 6 shows the timing of both four cycle instructions RET 22h CJNE data addr B4h 47 40 7 0 5 6 5 Five Cycle Instructions There are only two five cycle instructions in the high speed microcontroller They are the multip
29. To do this the absolute address must be specified 030308 59 of 175 High Speed Microcontroller User s Guide 4 4 2 Direct Addressing Direct Addressing is the mode used to access the entire lower 128 bytes of Scratchpad RAM and the SFR area It is commonly used to move the value in one register to another Two examples are shown below MOV 72h 74h Move the value in register 74 to register 72 MOV 90h 20h Move the value in register 20 to the SFR at 90h Port 1 Note that there is no instruction difference between a RAM access and an SFR access The SFRs are simply register locations above 7Fh Direct Addressing also extends to bit addressing There is a group of instructions that explicitly use bits The address information provided to such an instruction is the bit location rather than the register address Registers between 20h and 2Fh contain bits that are individually addressable SFRs that end in 0 or 8 are bit addressable An example of Direct Bit Addressing is as follows SETB 008 Set bit 00 in the RAM This is the LSb of the register at address 20h as shown in Section 4 MOV C Move the contents of bit B7 to the Carry flag Bit B7 is the MSb of register BO Port 3 4 4 3 Register Indirect Addressing This mode is used to access the Scratchpad RAM locations above 7Fh It can also be used to reach the lower RAM 0h 7Fh if needed The address is supplied by the contents of t
30. _ 6 e e 6 se spa des 8 ME E o pM ye puc 41 52 174 of 175 High Speed Microcontroller User s Guide 19 REVISION HISTORY REVISION SECTION PAGES DATE NUMBER DESCRIETION CHANGED 42 In the Watchdog Control WDCON register description changed reset 45 031607 i values for bit 6 and bits 3 to 0 from W to T 16 In the EXPLANATION column for XCH A Rn XCH A direct SCH 159 Ri XCHD corrected to lt gt Removed note about DS87C550 micro incorporates several interrupt 9 vectors whose locations differ from those used by the high speed 99 042307 microcontroller family or other 8051 devices 18 In Table 18 A removed DS87C550 column and device data 167 030308 6 1 Removed sentence about the DS87000 microcontroller 72 Rev 030308 175 of 175 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 MAXIM a registered trademark of Maxim Integrated Products 2008 Maxim Integrated
31. allows a device to return to divide by 4 operation in time to receive incoming serial port data and process interrupts with no loss in performance 030308 95 of 175 High Speed Microcontroller User s Guide The DS87C520 and DS87C530 incorporate a Status register STATUS C5h to prevent the device from accidentally reducing the clock rate during the servicing of an external interrupt or serial port activity This register can be interrogated to determine if a high priority low priority or power fail interrupt is in progress or if serial port activity is occurring Based on this information the software can delay or reject a planned change in the clock divider rate In addition the DS87C520 and DS87C530 can operate from the internal ring oscillator during normal operation not only during the crystal warmup period Table 7 C summarizes the new control bits associated with the power management features Table 7 C Power Management and Status Bit Summary BIT NAME LOCATION FUNCTION RESET STATE ACCESS Clock Divider Control CDI Osc Cycles per Machine Cycle Write 0 1 anytime 0 0 Reserved 1 0 and 1 1 only when CDI CDO PMR 7 6 0 1 4 Reset Default 0 1 previously in 0 1 1 0 64 PMMI state 1 1 1024 gt Switchback Enable 0 Interrupts and serial port activity will not affect SWB PMR 5 clock divider control bits 0 Unrestricted 1 Enabled Interrupts and serial
32. and data memory areas are discussed in Section 4 1 1 Memory Map The registers are discussed in Section 4 1 2 Register Map 4 1 1 Memory Map The high speed microcontroller uses a memory addressing scheme that separates program memory ROM from data memory RAM Each area is 64kB beginning at address 0000h and ending at FFFFh as shown in Figure 4 1 The program and data segments can overlap since they are accessed in different ways Program memory is fetched by the microcontroller automatically These addresses are never written by software In fact there are no instructions that allow the ROM area to be written There is one instruction MOVC that is used to explicitly read the program area This is commonly used to read look up tables The data memory area is accessed explicitly using the MOVX instruction This instruction provides multiple ways of specifying the target address It is used to access the 64kB of data memory The address and data range of devices with on chip program and data memory overlap the 64k memory space When on chip memory is enabled accessing memory in the on chip range will cause the device to access internal memory Memory accesses beyond the internal range will be addressed externally via ports 0 and 2 The ROMSIZE feature allows software to dynamically configure the maximum address of on chip program memory This allows the device to act as a bootstrap loader for an external flash or NV SRAM Secondly this meth
33. moo TOE DCEN Ch RCAP2L RCAP2H TL2 TH2 CY AC J FO OV FI P Dh WDCON ERICI EWDI EX5 EX4 EX2 B 7 Fh F PX2 gt E Oh Oh B7 Bo BS B2 Bi O RTASS 54 RTAS 3 RTAS2 RTASO 0 5 RTAM3 RTAM2 1 RTAMO 0 4 RTAH3 RTAH2 RTAHO PRICI PWDI PXS PX4 RTCSS Hev 030308 23 of 175 High Speed Microcontroller User s Guide 0 55 RTCS4 RICS3 RTCS 2 RTCS 1 RTCS 0 RTCM 0 5 RTCM4 RTCM 2 RTCH RTCDO RTCDI Note Shaded bits timed access protected Table 4 H DS87C530 SFR Reset Values 11 1 1 2 __ __ 1 1 8Ih 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 90h 91h __ 1 o0 0 ECAL 0 ECIAL SPECIAL 96h 0 __ 0 0 1 SPECIAL CIAL mi SPECIAL TRIM SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL SP SCONO SBUFO Hj
34. serial transmission is initiated by writing to either the SBUFO or SBUFI location Most of the serial port controls are provided by the SCONO and SCONI registers For convenience these are provided in Table 12 A In addition other control bits that influence the Serial Port operation are also summarized below Table 12 A Serial I O Modes BAUD DATA MODE SYNCH ASYNCH CLOCK BITS START STOP 9TH BIT FUNCTION 0 Synch 4 or 8 1 Asynch Timer or 2 8 start 1 stop None 2 Asynch 32 or 64 9 1 start 1 stop 0 1 parity 3 Asynch Timer or 2 9 1 start 1 stop 0 1 parity use of or 2 will affect the baud clock Timer 2 available for Serial Port 0 only 030308 137 of 175 High Speed Microcontroller User s Guide 12 2 1 Serial Port Control 0 Register SCONO 98h This is the standard 80C32 serial port The new serial port is designated Serial Port 1 and is documented below SCONO 7 Serial Port 0 Mode Bit 0 or Framing Error Flag 5 0 PCON 6 SMODO determines whether this bit functions as SMO or FE The operation of SMO SMODO 0 is described in the table below When SMODO 1 the serial port will set FE to indicate an invalid stop bit When used as FE this bit must be cleared in software SCONO 6 Serial Port 0 Mode Select 1 5 1 0 The operation of SM1 is described in the table below SCONO 5 Mu
35. 1 a 1 10 0 transition on the T2EX P1 1 pin will cause the EXF2 T2CON 6 interrupt flag to be set If enabled this will cause a Timer 2 Interrupt to occur Therefore in this mode the T2EX pin may be used as an additional external interrupt if desired Another feature of the baud rate generator mode is that the crystal derived time base for the timer 1s the crystal frequency divided by 2 No other crystal divider selection is possible If a different time base 15 desired bit C T2 T2CON 1 may be set to a 1 sourcing the time base from an external clock source supplied by the user on pin T2 P1 0 Software should not access TL2 or TH2 while the timer is running TR2 1 in baud rate generator mode In this mode the timer is clocking so fast that a software read of or write to the TL2 and TH2 registers may corrupt the timer The RCAP registers may be read but not modified while TR2 1 Stop the timer TR2 0 to modify these registers 030308 129 of 175 High Speed Microcontroller User s Guide Figure 11 6 Timer Counter 2 Baud Rate Generator Mode OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC 2 TIMER 1 OVERFLOW DIVIDE 2 SMOD C T2 T2COD 1 2 WDCON 7 1 5 82 2 OSC 512 T2 P1 0 TR2 T2CON 2 T2EX P1 1 DIVIDE BY 16 TIMER 2 INTERRUPT EXF2 T2CON 6 EXEN2 T2CON 3 11 7 6 Timer Output Clock Generator Timer 2 can also be configured to drive a clock o
36. 1 1 0 1 0 0 0 0 DO 2 2 direct SP Byte 2 SP SP 1 XCH A Rn 1 1 0 0 1 m no C8 CF 1 1 A gt Rn XCH A 1 1 0 0 0 10 1 5 direct Byte 2 2 2 A lt gt direct Ri 1 1 0 0 0 1 C6 C7 1 1 lt gt RI 1 1 As Ri Rev 030308 166 of 175 High Speed Microcontroller User s Guide INSTRUCTION CODE MNEMONIC D D D D D D D HEX BYTE CYCLE EXPLANATION CLRC 1 1 0 0 0 0 1 1 1 1 0 gt CLR bit 1 1 0 0 0 0 1 0 C2 2 2 bit 0 b bs b b b bi bo Byte 2 E SETBC 1 1 0 1 0 0 1 D 1 1 1 3 SETB bit 1 1 0 1I 0 0 I 0 D 2 2 bit 1 ma b bg bs b4 bs b b bo Byte 2 2 CPLC 1 0 1 1 0 0 1 3 1 1 C C CPL bit 1 0 1 1 0 0 0 B2 2 2 b b b b b b bo Byte 2 ow bit E ANLC bit 10 0 0 0 0 9 82 2 2 AND bit 5 b be b b b b b bo Byte 2 hit 1 0 1 1 0 0 0 0 BO 2 2 hit lt ANLC bit C AND bit Z ORL C bit 1 1 I 0 0 I1 39 72 2 2 OR bit b bg bs b b b b bo Byte 2 5 li 0 1 0 0 0 0 0 0 2 2 E ORL C bit OR bit MOVC bt 1 1 0 I 0 2 2 2 bit b bg bs b b b b bo Byte 2 MOVbiiC I 0 1 0 92 2 2 bit C b bg bs b b b b bo
37. 1 9h Oh PTO PXO SADENO4 SADENO3 SADENO2 SADENOI SADENOO B9h STATUS pm x qp Wu Oen TCLK EXEN2 TR2 2 T2MOD TOB DCEN RCAPLA RCAP2L3 RCAP2L2 RCAPLI RCADLO CAh gt RCAP2L RCAP2H Rt RCAP2H6 RCAP2H5 RCAP2HA RCAP2H3 RCAP2H2 2 RCAP2HO CBh TL2 TL2 TH2 RO 0 IE2 N 0 ROA 1 0 MODO TFO C T MI i TLO 1 5 T2M IEA IE3 S 0 0 M2 0 S 57 615 EA SADDRO SADDRO7 SADDRO6 SADDROS PT2 UIS 6 SADENOS HIP LIP XF2 CLK RI 7 AP2L 6 5 7 RI 0 S SADDROO PXO _SADENO7 SADENO3 SADENOO 0 uM T2CON TF2 EXEN T2 CP RL2 C8h pm DCEN RCAP2LO RCAP2H7 RCAP2HO ATE TLO L0 7 OFE P2 1 SADENO F2 1 AP2L H 112 TH2 PSw CY AC Fo RS OV P Dh _ ou oom em _ ed CC I 4 EX2 Eh Bo BS B2 BO 5 PX2 F8h IP 030308 17 of 175 High Speed Microcontroller User s Guide Table 4 B DS80C310 SFR Reset Values REGISTER SP o rr 1 DL o
38. 1 Edge Detect Set by hardware when an edge level is detected on INTI Bit 2 Interrupt 1 Type Select INTI detects falling edge when this bit is set to 1 INTI detects a low level when this bit 15 0 Bit 1 Interrupt 0 Edge Detect Set by hardware when an edge level is detected on INTO Bit 0 Interrupt 0 Type Select ITO INTO detects a falling edge when this bit is set to 1 INTO detects a low level when this bit 15 0 11 2 Mode 0 Mode 0 configures either Timer 0 or Timer 1 for operation as a 13 bit Timer Counter As shown in Figure 11 1 bits MI 0 and MO 0 of the TMOD register select this operating mode When using Timer 0 TLO uses only bits 0 4 These bits serve as the 5 LSbs of the 13 bit timer THO provides the 8 MSbs of the 13 bit timer Bit 4 of TLO is used as a ripple out to THO bit 0 thereby completely bypassing bits 5 through 7 of TLO Once the timer is started using the TRO TCON 4 timer enable the timer will count as long as GATE TMOD 3 is 0 or 15 1 and pin INTO 15 1 It will count oscillator cycles if C T TMOD 2 is set to a logic 0 and 1 to 0 transitions on TO P3 4 if C T is set to a 1 When the 13 bit count reaches 1FFFh all ones the next count will cause it to roll over to 0000h The TCON 5 flag will be set and an interrupt will occur if enabled The upper three bits of TLO will be indeterminate Note that when used as a timer the time base may be either osc
39. 12 480ns 1 5 DEC Ri 16 17 4 160ns 12 480ns 3 MUL AB 4 20 800ns 48 1 92us 2 4 DIV 84 20 800ns 48 1 92us 2 4 DAA D4 4 160ns 12 480ns 3 ANL A Rn 58 5 4 16015 12 48015 3 ANL direct 55 8 320ns 12 48015 1 5 ANL 1 56 57 4 160ns 12 480ns 3 ANL A data 54 8 320ns 12 480ns 1 5 ANL direct A 52 8 320ns 12 480ns 1 5 ANL direct data 53 12 480ns 24 960ns 2 ORL A Rn 48 4 4 16015 12 48015 3 ORL A direct 45 8 320ns 12 480ns 1 5 ORL Ri 46 47 4 160ns 12 480ns 3 ORL A data 44 8 320ns 12 480ns 1 5 ORL direct A 42 8 320ns 12 480ns 1 5 ORL direct data 43 12 480ns 24 960ns 2 XRL A Rn 68 6F 4 160ns 12 480ns 3 XRL A direct 65 8 320ns 12 480ns 1 5 XRL A Ri 66 67 4 160ns 12 480ns 3 XRL A data 64 8 320ns 12 480ns 1 5 XRL direct A 62 8 320ns 12 480ns 1 5 XRL direct data 63 12 480ns 24 960ns 2 CLRA E4 4 160ns 12 480ns 3 CPLA F4 4 160ns 12 480ns 3 RLA 23 4 160ns 12 480ns 3 RLC A 33 4 160ns 12 480ns 3 Rev 030308 72 of 175 High Speed Microcontroller User s Guide HSM 8051 HSM vs 8051 INSTRUCTION CLOCK BELT SPEED CYCLES CYCLES ADVANTAGE RRA 03 4 160ns 12 480ns 3 RRCA 13 4 160ns 12 480ns 3 SWAPA 4 160ns 12 480ns 3 MOV A Rn E8 EF 4 160ns 12 480ns 3 MOV A direct 5 8
40. 123 EE C 124 146 1 Timer two Control Register ai erre ipee tra pa eias eo recs 124 11 6 2 Timer Two Mode Control Register T2MOD Summary 125 11 6 8 Timer 2 Capture Registers RCAP2L RCAP2H 2 2000202000000448 125 Jo ME od nr ce T CEN Pc E 126 uide 126 JEBE o AU UIS cou NM 126 LEGS ATAT 127 11 7 4 Up Down Count Auto Reload Timer Counter 129 129 NET CIR c P 130 ia mer H 131 11 9 IME DRE CK aaNet 132 1 97 Watchdog Control Register WDOCON E EE REM ERE 134 1192 Register 135 12 cid s 136 SERALMODE SUMMARY DESSEN 136 136 A Pc UU 136 Hwy 137 UAE MER es ro RUNE mcm 137 12 2
41. 1333 1 0 1 7 20 800 1667 1 1 0 8 24 960 2000 1 1 1 9 28 1120 2333 Note These numbers represent nominal values Actual timing may vary slightly Figure 6 4 Full Speed MOVX Instruction Last Cycle of First Second Next Previous gt lt Machine 4 lt Instruction Instruction Cycle Cycle Machine I instruction cal Instruction MOVX instructior Next Data MOVX Address Address Instruction Address Data Read Instruction DATA MEMORY WRITE 2 CYCLE STRETCH 0 030308 85 of 175 High Speed Microcontroller User s Guide Figure 6 5 Three Cycle MOVX Instruction I 1 ipse Second Third Instruction Previous gt gt Machine Pit Machine gt Instruction Cycle I MOVX Instruction p 2 2 ce 2 Instruction Data Instruction Address Address Address Next MOVX instruction Instruction structio Read THREE CYCLE DATA MEMORY WRITE RESET DEFAULT STRETCH VALUE 1 Rev 030308 86 of 175 High Speed Microcontroller User s Guide Figure 6 6 Four Cycle
42. 15 enabled WD1 WDO Interrupt Divider Reset Divider 0 0 Pd 2 4 512 0 1 7 220 512 1 0 2 223 512 1 1 2 226 512 The default watchdog timeout is the shortest WDO 0 Software can change this value easily so this should cause no inconvenience However the EWT WDIF and RWT bits are protected under the timed access procedure This prevents software from accidentally enabling or disabling the watchdog Most importantly it prevents errant code from accidentally clearing and restarting the watchdog More details are discussed in the section on timed access 030308 135 of 175 High Speed Microcontroller User s Guide 12 SERIAL The high speed microcontroller serial communication is compatible with the 80C32 This includes framing error detection and automatic address recognition The high speed microcontroller provides two fully independent UARTS serial ports for simultaneous communication over two channels The UARTs can be operated in identical or different modes and communication speeds In this documentation all descriptions apply to both UARTS unless stated otherwise Each serial port is capable of both synchronous and asynchronous modes In the synchronous mode the microcontroller generates the clock and operates in a half duplex mode In the asynchronous mode full duplex operation is available Receive data is buffered in a holding register This allows
43. 3 Is the appropriate timer reload value loaded 4 Is the appropriate timer mode selected 5 Is the appropriate timer running by setting TRO TR1 or TR2 bits 6 Is the correct serial port mode selected 7 If desired 15 the serial port doubler bit SMOD set 7 or WDCON 7 8 If desired 1 the receive enable bit REN 0 or REN 1 set 9 Is the serial port interrupt enabled 10 Is the global interrupt enable bit set 17 6 High Speed Microcontroller Does Not Work in Existing 8051 Design Although the high speed microcontroller family was designed as a drop in replacement for the 8051 family a developer may occasionally notice problems when inserting into an existing design Often these problems are related to slow memory interfaces that cannot keep up with the increased throughput of the faster microcontroller In addition software timing loops run faster possibly changing program operation These and other effects are described in Application Note 56 The DS80C320 as a Drop In Replacement for the 8051 8032 Microcontroller and Application Note 57 DS80C320 Memory Interface Timing Application Note 89 High Speed Micro Memory Interface Timing discusses interfacing other members of the high speed microcontroller family to external memory 172 of 175 High Speed Microcontroller User s Guide 18 MICROCONTROLLER DEVELOPMENT SUPPORT 18 1 Technical Support For technical support go to www maxim ic com support M
44. 5 Byte 3 destination lt MOV direct 1 0 0 0 0 1 1 i 86 87 2 2 direct Ri a Byte2 030308 165 of 175 High Speed Microcontroller User s Guide INSTRUCTION CODE MNEMONIC D D D D D D D D HEX BYTE CYCLE EXPLANATION MOV direct 0 1 1 1 0 1 0 1 75 3 3 direct data data Byte 2 d de 5 4 d d di do Byte 3 MOV Ri A 1 1 1 1 0 1 4 i F6 F7 1 1 Ri A MOV 1 0 1 0 0 1 1 1 A6 A7 2 2 R1 direct direct Byte 2 MOV 0 1 1 1 0 1 1 1 76 77 2 2 Ri data data d 4 dj di d 2 MOV DPTR 1 0 0 1 0 0 0 0 90 3 3 DPTR 1 lt 5 4 16 d ds dy di d dy 2 DPH zdata 5 s 40 4 ds dj dj 4 dy Byte3 DPL dataz o 1 0 0 1 0 0 1 93 1 3 DPTR QA DPTR 1 0 0 0 0 0 1 83 1 3 QA Z MOVX 1 1 1 0 0 0 1 i E2 E3 1 2 9 A Ri 2 1 1 1 0 0 0 0 0 0 1 2 9 A DPTR DPTR Ri 1 1 1 1 0 0 1 i F2 F3 1 2 9 Ri A A MOVX 1 1 1 1 0 0 0 0 FO 1 2 9 DPTR DPTR A PUSH direct 1 1 0 0 0 0 0 0 2 2 5 5 1 Byte2 SP direct POP direct
45. 7 RD Read strobe Rev 030308 117 of 175 High Speed Microcontroller User s Guide 11 PROGRAMMABLE TIMERS All members of the high speed microcontroller family incorporate three 16 bit programmable timers and some also have a watchdog timer with a programmable interval Because the watchdog timer is significantly different from the other timers it is described separately The 16 bit timers are referred to simply as timers In most modes the timers can be used as either counters of external events or timers When functioning as a counter 1 0 transitions on port pin are monitored and counted When functioning as timers they effectively count oscillator cycles The time base for the timer function is the main oscillator clock divided by either 4 or 12 This selection 1 described below Because each clock pulse must be sampled high for one machine cycle and low for one machine cycle to be recognized this sets the maximum sampling frequency on any timer input at 1 8 of the main oscillator frequency The three timers are compatible with the 80C32 That is they offer the same controls and I O functions that were available in the 80C32 As mentioned above the actual timing of these functions is user selectable to be compatible with the machine cycle of the older generation of 8051 family 12 clocks per tick or the new generation 4 clocks per tick The timing for each of the three timers can be selected independently and can be chan
46. B registers The ALU also provides status information in the program status register The SFRs are described below 3 2 Special Function Registers SFRs peripherals and operations that are not explicit instructions in the high speed microcontroller are controlled through SFRs SFRs are described in Section 4 The most commonly used registers that are basic to the architecture are also described below 3 2 1 Accumulator The Accumulator is the primary register ACC used in the high speed microcontroller It is the source and destination of most math data movement decisions and other operations Although it can be bypassed most high speed instructions require the use of the accumulator ACC as one argument 3 2 2 B Register The B register B is used as the second 8 bit argument in multiply and divide operations When not used for these purposes the B register can be used as a general purpose register 3 2 3 Program Status Word The program status word holds a selection of bit flags that include the carry flag auxiliary carry flag general purpose flag register bank select overflow flag and parity flag 3 2 4 Data Pointer s The data pointer is used to designate a memory address for the MOVX instruction This address can point to MOVX RAM location either on or off chip or a memory mapped peripheral When moving data from one memory area to another or from memory to a memory mapped peripheral a pointer is needed f
47. Byte 2 030308 167 of 175 High Speed Microcontroller User s Guide INSTRUCTION CODE MNEMONIC D D D D D HEX BYTE CYCLE EXPLANATION ACALL addr 1 0 0 0 1 Bytel 2 3 PC 2 11 ag Byte2 SP SP 1 SP PCz4 SP SP 1 SP PCiss PC page address LCALL addr 0 0 0 1 0 0 0 12 3 4 PC 3 16 5 AQ 2 SP SP 1 3 SP PC7 SP SP 1 SP PCiss 5 addrj5 9 Z RET 0 0 1 0 0 0 0 22 1 4 SP SP 1 gt SP 2 SP SP 1 eS RETI 0 0 1 1 0 0 0 32 1 4 gt SP SP 1 5 PCr SP O SP SP 1 E AJMP addr ag 0 0 0 0 1 Bytel 2 3 PC 2 11 Byte2 page addr LJMP addr 0 0 0 0 0 0 1 0 02 3 4 PC addr15 0 16 ais AQ ag 2 Byte 3 SJMP rel 1 0 0 0 0 0 0 0 80 2 3 PC 2 I 5 1 4 HH 10 Byte2 PC rel JMP A 0 1 1 1 0 0 1 73 1 3 PC DPTR DPTR JZ rel 1 0 0 0 0 0 0 0 60 2 3 PC 2 I I6 501 B t Byte2 IF A 0 THEN PC PC rel JNZ rel 1 0 0 0 0 0 0 0 70 2 3 2 I7 16 15 T4 13 Ti To
48. Guide 4 4 Addressing Modes The high speed microcontroller uses the standard 8051 instruction set which a wide range of third party assemblers and compilers supports Like the 8051 the high speed microcontroller uses three memory areas These are program memory data memory and registers Both the program and data areas are 64kB each They extend from 0000h to FFFFh The register areas are located between 00h and FFh but do not overlap with the program and data segments This is because the high speed microcontroller uses different modes of addressing to reach each memory segment These modes are described below Program memory is the area from which all instructions are fetched It is inherently read only This is because the 8051 instruction set provides no instructions that write to this area Read write access is for data memory and registers only No special action is required to fetch from program memory Each instruction fetch will be performed automatically by the on chip hardware In versions that contain on chip memory the hardware will decide whether the fetch is on chip or off chip based on the address Explicit addressing modes are needed for the data memory and register areas These modes determine which register area 15 accessed or if off chip data memory is used The high speed microcontroller supports eight addressing modes Register Addressing Direct Addressing Register Indirect Addressing Immediate Addressing Regis
49. INSTRUCTION FETCH OPERAND FETCH OPERAND FETCH DUMMY FETCH SINGLE CYCLE SINGLE CYCLE SINGLE CYCLE SINGLE CYCLE ci Ice les 2 54 2 c3 4 2 INSTRUCTION FETCH OPERAND FETCH OPERAND FETCH DUMMY FETCH SINGLE CYCLE SINGLE CYCLE SINGLE CYCLE SINGLE CYCLE c2 Ics 154 2 c3 4 2 4 2 54 CLK Rev 030308 70 of 175 High Speed Microcontroller User s Guide Figure 5 7 Five Cycle Instruction Timing Example MUL A4h DUMMY DUMMY FETCH DUMMY FETCH DUMMY FETCH E mac SU SINGLE CYCLE SINGLE CYCLE SINGLE CYCLE SINGLE CYCLE 62 les Ic2 lcs c lc2 ci les Ica k2 Shaded areas are held in a weak latch on the port until 5 7 Comparison to the 8051 The original 8051 had a 12 clock architecture A machine cycle needed 12 clocks and most instructions were either one or two machine cycles Thus except for the MUL and DIV instructions the 8051 used either 12 or 24 clocks for each instruction Furthermore each cycle in the 8051 used two memory fetches In many cases the second fetch was a dummy and the extra clock cycles were wasted The high speed microcontroller uses 4 clocks per cycle Since a cycle 1 now aligned with a memory fetch when possible most instructions have the same number of cycles as bytes This leads to more categories than
50. MOVX Instruction Last Cycle of First Second Third Fourth Next 1 i i i i Instruction Previous lt je Machine 4 Machine pie Instruction Cycle Cycle Cycle Cycle Machine MOVX Instruction eal 4 4 1 eo 2 es eal Instruction Instruction Data Address Address Address Next n Instruction structio Read FOUR CYCLE DATA MEMORY WRITE STRETCH VALUE 2 030308 87 of 175 High Speed Microcontroller User s Guide 7 MANAGEMENT The high speed microcontroller has several features that relate to power consumption and management They provide a combination of controlled operation in unreliable power applications and reduced power consumption in portable or battery powered applications The range of features is shown below with details to follow Power Management Early Warning Power Fail Interrupt Power Fail Power On Reset Bandgap Select Watchdog Wake Up from Idle Power Saving Idle Mode Stop Mode Ring Wake Up from Stop Power Management Modes Precision Voltage Monitor The high speed microcontroller uses a precision bandgap reference and other analog circuits to monitor the state of the power supply during power up and power down transitions Other microcontroller systems would require external circuits to perfo
51. Microcontroller User s Guide 7 2 Power Conservation The high speed microcontroller is implemented using full CMOS circuitry for low power operation It is fully static so the clock speed can be run down to DC Like other CMOS the power consumption 1 also function of operating frequency Although the high speed microcontroller is designed for maximum performance it also provides improved power versus work relationships compared with standard 8051 devices These topics are discussed in detail below The high speed microcontroller provides two power conservation modes They are similar but have different merits and drawbacks These modes are Idle and Stop In the original 8051 the Stop mode 15 called power down These modes are invoked in the same manner as the original 8051 series 7 2 1 Idle Mode Idle mode suspends all CPU processing by holding the program counter in a static state No program values are fetched and no processing occurs This saves considerable power versus full operation The virtue of Idle mode is that it uses half the power of the operating state yet reacts instantly to any interrupt conditions All clocks remain active so the timers Watchdog Serial Port and Power Monitor functions are all working Since all clocks are running the CPU can exit the Idle state using any of the interrupt sources Software can invoke the Idle mode by setting the IDLE bit in the PCON register at location 87h The bit is located at P
52. PWDI 5 PX3 PX2 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Bits 7 6 Reserved These bits will be 0 when read PRTCI Real Time Clock Interrupt Priority This bit controls the priority of the real time Bit 5 clock interrupt on the DS87C530 This bit will read 0 on all other devices 0 The real time clock interrupt is a low priority interrupt 1 The real time clock interrupt is a high priority interrupt PWDI Interrupt Priority This bit controls the priority of the watchdog interrupt Bit 4 0 The watchdog interrupt is a low priority interrupt 1 The watchdog interrupt is a high priority interrupt PX5 External Interrupt 5 Priority This bit controls the priority of external interrupt 5 Bit 3 0 External interrupt 5 is a low priority interrupt 1 External interrupt 5 is a high priority interrupt 4 External Interrupt 4 Priority This bit controls the priority of external interrupt 4 Bit 2 0 External interrupt 4 is a low priority interrupt 1 External interrupt 4 is a high priority interrupt PX3 External Interrupt 3 Priority This bit controls the priority of external interrupt 3 Bitl 0 External interrupt 3 is a low priority interrupt 1 External interrupt 3 is a high priority interrupt PX2 External Interrupt 2 Priority This bit controls the priority of external interrupt 2 Bit 0 0 External interrupt 2 is a low priority interrupt 1 Extern
53. Q w gig 98h 99h A8h A9h SADDRO SADDRI SADENO B9h SAD 5 SBUFI ROMSIZE PMR STATUS C2h C4h C5h 1 C8h 2 T2MOD RCAPZL RCAP2H TL2 __ o _bsw fo o_o WDCON 0 SPECIAL 0 SPECIAL 0 SPECIAL SPECIAL D8h LA 9 E0h EHE Rev 030308 24 of 175 SADENI CDh NEZ NEN ECAL 0 High Speed Microcontroller User s Guide L B RTASS RTAS 0 SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL RTAM O SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL RTAH 0 SPECIAL SPECIAL SPECIAL SPECIAL SPECIAL F5h eee E SPECIAL SPECIAL SPECIAL 0 0 SPECIAL SPECIAL F9h ECIAL NES o SPECIAL SPECIAL SPECIAL Peh RTCDO RTCD1 Most of the unique features of the high speed microcontroller family are controlled by bits in SFRs located in unused locations in the 8051 SFR map This allows for increased functionality while maintaining complete instruction set compatibility SPECIAL S SPECIAL SPECIAL SPECIAL SPECIAL 0 SPECIAL SPECIAL SPECIAL
54. START DO ARBS STOP NM N 0 Hn Hn m __ RI c 030308 150 of 175 High Speed Microcontroller User s Guide 12 6 Multiprocessor Communication Multiprocessor communication mode makes special use of the 9th data bit in Modes 2 and 3 In the original 8051 the 9th bit was restricted to 0 or 1 condition but had no special purpose In the 80C32 and the high speed microcontroller it can be used to signify that the incoming byte is an address This allows the processor to be interrupted only if the correct address appears The receive interrupt if enabled will only occur when a recognized address 1 received When a serial word is received with the 9th bit set and the appropriate SM2 1 the byte will be assumed to be an address The address will be compared to an internally stored address If it matches a receive interrupt will occur The internal address is derived from the contents of two registers The first register specifies an absolute address This is the user specified address of the device The second register tells the comparator which address bit s to actually use in the comparison This allows broadcast transmissions that reach groups of microcontrollers or all microcontrollers on a serial port The user defines this protocol There are two SFRs that support multiprocessor communication for each UART These are independent so that different addresses can be us
55. T2EX P1 1 pin 1 to 0 transition will force a reload if enabled by the EXEN2 T2CON 3 bit If EXEN2 is set to logic 1 then a 1 0 transition on T2EX will cause a reload Otherwise the T2EX pin will be ignored 030308 127 of 175 High Speed Microcontroller User s Guide Figure 11 5 Timer Counter 2 Auto Reload Mode DCEN 0 OSC INPUT TO TIMER DIVIDE a CKCON 5 TIMER INPUT 12 C T3 T2CON 1 4 05 ios 1 OSC 16 2 OSC 256 T2 P1 0 TR2 T2CON 2 T2EX P1 1 TIMER 2 INTERRUPT EXEN2 T2CON 3 b DCEN 1 DOWN COUNTING RELOAD VALUE OSC INPUT TO TIMER 12M _CLK MODE TIMERINPUT BY 12 DIVIDE BY 4 OSC 1 PMM1 OSC 16 PMM2 OSC 256 T2 1 0 2 T2CON 2 RCAP2L UP COUNTING RELOAD VALUE 1 UP 0 DOWN 2 P1 1 2 2 2 7 INTERRUPT 030308 128 of 175 High Speed Microcontroller User s Guide 11 7 4 Up Down Count Auto Reload Timer Counter The up down auto reload counter option is selected by the 2 0 bit and is illustrated in Figure 11 5 When DCEN is set to a logic 1 Timer 2 will count up or down as controlled by the state of pin T2EX P1 1 T2EX will cause upward counting when a logic 1 is applied and down counting when a logic 0 is applied When DCEN 0 Timer 2 only counts up When an upward counting over
56. Timer 178 resources 1 and TF1 Timer 1 can still be used in Modes 0 1 and 2 in this situation but its flexibility becomes somewhat limited While it maintains its basic functionality its inputs and outputs are no longer available Therefore when Timer 0 is in Mode 3 Timer 1 can only count oscillator cycles and it does not have an interrupt or flag With these limitations baud rate generation is its most practical application but other time base functions may be achieved by reading the registers 030308 123 of 175 High Speed Microcontroller User s Guide 11 6 Timer 2 Like Timers 0 and 1 Timer 2 is a full function timer counter however it has several additional capabilities that make it more useful Timer 2 has independent control registers in 2 and T2MOD and is based on count registers TL2 and TH2 these registers are described in detail below 11 6 1 Timer Two Control Register T2CON Summary 7 6 5 4 3 2 1 0 e TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit 7 Timer 2 Overflow Flag TF2 Hardware will set TF2 when the Timer 2 overflows from FFFFh to 0000h or from the count equal to the capture register in down count mode It must be cleared to 0 by software TF2 will only be set to a 1 if RCLK and TCLK both cleared to a 0 Bit 6 Timer 2 External Flag EXF2 Hardware will set EXF2 when a reload or capture is caused by a falling transition on the T2EX pin
57. can then disable the crystal and run from the lower power ring oscillator The control and status bits that support the new and or enhanced features are shown in Table 7 E Rev 030308 99 of 175 High Speed Microcontroller User s Guide Table 7 E Clock Control and Status Bit Summary BIT LOCATION FUNCTION RESET WRITE ACCESS Crystal Ring Clock Source Select This bit is not present on 0 anytime 1 when mE the DS80C320 XT RG 1 XTUP 1 and 1 Select crystal or external clock as clock source f 0 0 Select ring oscillator as clock source Ring Oscillator Mode Status RGMD EXIF2 1 Ring oscillator is current clock source 0 None 0 Crystal or external clock is current clock source Ring Oscillator Select Stop Mode 1 Ring oscillator will be the clock source when resuming from Stop mode 0 Crystal or external clock will be the clock source when RGSL EXIF 1 resuming from Stop mode Unrestricted Note Upon completion of crystal warmup period DS80C320 devices will switch to crystal DS87C520 and DS87C530 devices will switch to clock source designated by XT RG bit Crystal Oscillator Disable Disables crystal operation after ring mode has been selected This bit is not present on the 0 anytime 1 when XTOFF PMR 3 DS80C320 0 1 Crystal amplifier is disabled 0 Crystal amplifier is enabled Check XTUP for status Crystal Oscillator Warmup Status This bit is not pr
58. direct and immediate data no accumulator or working register These instructions tend to be three cycle instructions The largest number of improvements come from the single cycle instructions involving only the accumulator and working registers Also the two cycle data movement instructions involving the working registers are greatly improved 030308 71 of 175 High Speed Microcontroller User s Guide Table 5 A Instruction Timing Comparison Note HSM high speed microcontroller HSM 8051 HSM vs 8051 INSTRUCTION CLock HSM crock 501 TIME SPEED CYCLES CYCLES ADVANTAGE ADD A Rn 28 2F 4 160ns 12 480ns 3 ADD direct 25 8 320ns 12 480ns 1 5 ADD A Ri 26 27 4 160ns 12 480ns 3 ADD A 24 8 320ns 12 480ns 1 5 ADDC A Rn 38 3 4 16015 12 48015 3 ADDC direct 35 8 320ns 12 480ns 1 5 ADDC 36 37 4 160ns 12 480ns 3 ADDC A data 34 8 320ns 12 480ns 1 5 SUBB A Rn 98 9F 4 160ns 12 480ns 3 SUBB A direct 95 8 320ns 12 480ns 1 5 SUBB A QRi 96 97 4 160ns 12 480ns 3 SUBB A data 94 8 320ns 12 480ns 1 5 INCA 04 4 160ns 12 480ns 3 INC Rn 08 0F 4 160ns 12 480ns 3 INC direct 05 8 320ns 12 480ns 1 5 INC Ri 06 07 4 160ns 12 480ns 3 INC DPTR A3 12 480ns 24 960ns 2 DEC 14 4 160ns 12 480ns 3 DEC Rn 18 1 4 16015 12 48015 3 DEC direct 15 8 320ns
59. for a program access are shown in Figure 6 2 When implementing a high speed memory interface the F series or faster logic should be used HC logic will have worst case propagation delays that are too long Specifications for all devices should be checked More information on memory interface timing can be found in Application Note 57 DS80C320 Memory Interface Timing and Application Note 89 High Speed Microcontroller Interface Timing The first product in the family the DS80C320 provides an extremely high speed interface to external ROM or EPROM This assures that the user can use the slowest and least expensive memory device for a given crystal speed The DS80C320 provides very fast slew rates but controls ringing and overshoot 030308 78 of 175 High Speed Microcontroller User s Guide Fast slew rates allow the maximum possible time for memory access In most cases however these aspects will be transparent to the user Refer to the electrical specifications for exact timing of each product 6 4 Data Memory Interconnect As described in Section 4 the high speed microcontroller provides a small amount of RAM mapped as registers for on chip direct access This is not considered data memory and does not fall into the memory map Systems that require more RAM or memory mapped peripherals must use the data memory area This segment is a 64kB space located between 0000h and FFFFh It is reached using the MOVX instruction Any
60. gt INTERRUPT TIMER 1 FUNCTIONS SHOWN IN PARENTHESES Rev 030308 122 of 175 High Speed Microcontroller User s Guide 11 5 Mode 3 This mode provides an 8 bit timer counter and a second 8 bit timer as indicated in Figure 11 3 In Mode 3 TLO is an 8 bit timer counter controlled by the normal Timer 0 bits TRO TCON 4 and TFO TCON 5 TLO can be used to count oscillator cycles crystal 12 or crystal 4 or 1 0 transitions on pin TO as determined by C T TMOD 2 As in the other modes the GATE function can use INTO to give external run control of the timer to an outside signal THO becomes an independent 8 bit Timer in Mode 3 however it can only count oscillator cycles divided by 12 or 4 as shown in the figure In this mode some of Timer 175 control signals are used to manipulate THO That is TCON 6 and TCON 7 become the relevant control and flag bits associated with THO Figure 11 3 Timer Counter 0 Mode 3 DIVIDE n CKCON 3 OSC INPUT TO TIMER CLK MODE TIMER INPUT BY 12 im TMOD 2 DIVIDE BY 4 OSC 1 CLK TLO 1 OSC 16 DIVIDE PMM2 OSC 256 TO P3 4 TCON 5 INTERRUPT TRO TCON 4 1 TCON 7 PNE E INTERRUPT INTO P3 2 1 TCON 6 11111 THO In Mode 3 Timer 1 stops counting and holds its value Thus Timer 1 has practical application while in Mode 3 As mentioned above when Timer 0 15 in Mode 3 it uses some of
61. of 8 0 This bit must be manually cleared by software 4 2 20 Serial Data Buffer 0 SBUFO 7 6 5 4 3 2 1 0 SFR 99h SBUFO 7 SBUF0 6 SBUFO 5 SBUFO 4 5 SBUF02 SBUFO 1 SBUFO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SBUF0 7 SBUF0 0 Bits 7 0 4 2 21 SFR Serial Data Buffer 0 Data for serial port 0 is read from or written to this location The serial transmit and receive buffers are separate registers but both are addressed at this location Port 2 P2 7 6 5 4 3 2 1 0 P2 7 P2 6 2 5 P2 4 P2 3 P2 2 P2 1 P2 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset 2 7 2 0 Bits 7 0 030308 Port 2 This port functions as address bus during external memory access and as general purpose I O port on devices that incorporate internal program memory During external memory cycles this port will contain the MSB of the address The Port 2 latch does not control general purpose I O pins on the DS80C310 and DS80C320 but is still used to hold the address MSB during register indirect data memory operations such as MOVX A 36 of 175 High Speed Microcontroller User s Guide 4 2 22 SFR A8h Interrupt Enable IE 7 6 5 4 3 2 1 0 ESI ET2 ESO ETI EXI ETO RW 0 RW
62. opposed to 1 clock per internal clock cycle in divide by 4 mode This translates to 64 or 1024 external clocks per machine cycle in PMMI or 2 respectively Relative timing relationships of all signals when the device is operating in PMMI or 2 will remain the same as the 4 cycle timing Note that all internal functions on board 030308 96 of 175 High Speed Microcontroller User s Guide timers including serial port baud rate generation watchdog timer and software timing loops will also run at the reduced speed Most applications will not find it necessary to attend to this much detail but the information is provided for calculating critical timings Figure 7 2 demonstrates the internal timing relationships during PMMI Figure 7 2 Internal Timing Relationships in PMM1 lt SINGLE CYCLE INSTRUCTION HON CYCLES tH MACHINE CYCLE amp MACHINE CYCLE INTERNAL CLOCK PMM1 EXTERNAL CLOCK 64 CLOCK CYCLES gt and 2 are entered and exited by setting the Clock Rate Divider bits PMR 7 6 In addition it is possible use the switchback feature to affect a return to the divide by 4 mode from either power management mode This allows both hardware and software to cause an exit from PMM Entry to or exit from either PMM must be by the divide by 4 mode This means that to switch from divide by 64 to divide by 1024 and vice versa one must first switch
63. or subsecond This interrupt has the lowest priority of all interrupts but can be used to bring the device out of Stop mode if desired More information on this interrupt can be found in Section 14 9 2 5 Power Fail Interrupt Some devices can generate an interrupt when drops below a predetermined level These devices compare Vcc against an internal reference If Vcc drops below the level an interrupt will result if enabled Note that the power fail interrupt has the highest priority The user cannot alter the priority level but the interrupt can be disabled if not needed The level of Vprw is provided in the data sheet specifications associated with each product Note that the EPFI bit enables the power fail interrupt This bit is not subject to the global interrupt enable EA The power fail interrupt is a level sensitive interrupt and will remain set as long as Vcc remains below Vprw 030308 107 of 175 High Speed Microcontroller User s Guide 9 3 Simulated Interrupts Software can simulate any interrupt source by setting the corresponding flag bit This forces an interrupt condition that will be acknowledged if enabled and is otherwise indistinguishable from the real thing Thus an interrupt flag bit should never be set to a logic 1 by software inadvertently Once an interrupt has been acknowledged software cannot prevent or end the interrupt by clearing its flag However if for some reason the interrupt acknow
64. port activity will cause a switchback Power Fail Interrupt Status PIP STATUS 7 0 No power fail interrupt in progress 0 Read Only 1 Power fail interrupt in progress High Priority Interrupt Status HIP STATUS 6 0 No high priority interrupt in progress 0 Read Only 1 High priority interrupt in progress Low Priority Interrupt Status LIP STATUS 5 0 No low priority interrupt in progress 0 Read Only 1 Low priority interrupt in progress Serial Port 1 Transmitter Activity Status SPTAI STATUS 3 0 Serial port 1 transmitter inactive 0 Read Only Serial port 1 transmitter active Serial Port 1 Receiver Activity Status SPRAI STATUS 2 0 Serial port 1 receiver inactive 0 Read Only 1 Serial port 1 receiver active Serial Port 0 Transmitter Activity Status SPTAO STATUS 1 0 Serial port 0 transmitter inactive 0 Read Only Serial port 0 transmitter active Serial Port 0 Receiver Activity Status SPRAO STATUS 0 0 Serial port 0 receiver inactive 0 Read Only Serial port 0 receiver active 7 3 1 Power Management Mode Timing The two power management modes reduce power consumption by internally dividing the clock signal to the device causing it to operate at a reduced speed When 15 invoked the external crystal will continue to operate at full speed The difference is that the device uses 16 PMMI or 256 PMM2 external clocks to generate each internal clock cycle C1 C2 C3 or C4 as
65. priority interrupt PTO Timer 0 Interrupt This bit controls the priority of Timer 0 interrupt Bit 1 0 Timer 0 is determined by the natural priority order 1 Timer 0 is a high priority interrupt PX0 External Interrupt 0 This bit controls the priority of external interrupt 0 Bit 0 0 External interrupt 0 is determined by the natural priority order 1 External interrupt 0 is a high priority interrupt 4 2 27 Slave Address Mask Enable Register 0 SADENO 7 6 5 4 3 2 1 0 SFR B9h SADENO 7 SADENO 6 SADENO 5 SADENO 4 SADENO 3 SADENO2 SADENO 1 SADENO O RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SADENO 7 SADENO 0 Bits 7 0 030308 Slave Address Mask Enable Register 0 This register functions as a mask when comparing serial port 0 addresses for automatic address recognition When a bit in this register is set the corresponding bit location in the SADDRO register will be exactly compared with the incoming serial port 0 data to determine if a receiver interrupt should be generated When a bit in this register is cleared the corresponding bit in the SADDRO register becomes a don t care and is not compared against the incoming data incoming data will generate a receiver interrupt when this register is cleared 39 of 175 High Speed Microcontroller User s Guide 4 2 28 Slave Address Mask Enable Register 1
66. register RTCS FAh This register is automatically reset to 00h when the RTCWE bit is cleared either through software or the automatic timeout of the 1 95ms write window Writing an invalid time to these registers loading the RTCM register with 3Dh or 61 minutes for example will result in an inaccurate count by the RTC It is the responsibility of the software to ensure that only valid times are written to these registers The procedure for setting an RTC time register is as follows 1 Disable all interrupts by clearing the EA bit IE 7 2 Perform a timed access procedure 3 Set RTCWE bit RTCC 2 4 Wait 4 machine cycles 5 Write the appropriate register s within 1 95ms of RTCWE being set 6 Perform a timed access procedure 7 Clear the RTCWE bit RTCC 2 8 Enable interrupts by setting the EA bit IE 7 14 3 Using the RTC Alarm The RTC alarm function is used to generate an interrupt when the RTC value matches selected alarm register values An alarm can be triggered by a match on one or more of the following alarm registers subsecond RTASS F2h second RTAS F3h minute RTAM F4h and hour RTAH F5h Note that there is no alarm register associated with the RTC day count or day of week registers If an alarm is desired on a specific date an alarm can be executed once a day and user software can compare the current date against the day register It is not necessary to set the RTC write enable bit RTCWE when setti
67. reside in register locations 80h FFh and are reached using direct addressing SFRs that end in 0 or 8 are bit addressable standard SFR locations from the original 8051 are duplicated in the high speed microcontroller with several additions Following tables illustrate the locations of the SFRs for various devices Following each tables a description of the default reset conditions of all SFR bits The following information contains detailed descriptions of each SFR Table 4 A DS80C310 SFR Locations DPLI DPHI ps o o o o SE PCON SMOD 0 SMOD TFI TRI MI TLOS un f TRO ITI wo 888 TMOD Lor TLO TLO7 TLI THO T T C CKCON THIS THI3 __ TIM PLS i MD 1 5 P1 3 O 5 54 EX es m3 mo SCONO SMI SM2 0 RENO TB8 O RB8O RIO 98h T C C C SBUFO 99h R T R 550 ETO SADDRO4 SADDRO3 SADDRO2 SADDROI SADDROO P3 5 SAD SAD SAD E R R A8h B8h D2 B8 0 DRO ENO2 1 R2 2 2 ADENO SADENO T THI T R T E C T H1 3 T 0M M MDI SBUFO Oh ETO 3 SADDRO
68. state instantly when a reset is applied but will be taken high within two machine cycles of asserting a reset When the reset stimulus is removed program execution begins at address 0000h 8 3 No Battery Reset The battery backup feature of the DS87C530 introduces a new type of reset condition Most SFR bits are automatically reset to their default state upon a power on reset The external backup battery feature makes some bits non volatile however and these battery backed bits will not change state when a power on reset is applied Upon the loss or initial connection of battery power these bits will default to the state shown in Table 8 A Any bits not listed below are either unchanged or set to their default state by a power on reset 030308 103 of 175 High Speed Microcontroller User s Guide Table 8 A No Battery Reset Default NO BATTERY NO BATTERY BIT NAME LOCATION RESET STATE BIT NAME LOCATION RESET STATE EAK TRIM 7 0 SSCE 7 Indeterminate X12 6 TRIM 6 1 SCE RTCC 6 Indeterminate TRM2 TRIM 5 1 RTCC 5 Indeterminate TRM2 4 0 4 Indeterminate TRMI TRIM 3 0 RTCIF RTCC 1 Indeterminate TRMI TRIM 2 1 0 Indeterminate TRMO TRIM 1 0 RTCSS 7 0 RTCSS 7 0 Indeterminate TRMO 0 1 RTCS 7 0 RTCS 7 0 Indeterminate RTASS 7 0 RTASS 7 0 Indeterminate RTCM 7 0 RTCM 7 0 Indeterminate 5 7 0 5 7 0 Indetermi
69. the UART to receive an incoming word before software has read the previous value Each UART has an associated control register SCONO SCON1 and each has a transmit receive register SBUFO SBUF1 The SFR locations are SCON0 98h SBUFO 99h SCONI COh SBUF1 Clh The SBUF location provides access to both transmit and receive registers Reads are directed to the receive buffer and writes to the transmit buffer automatically 12 1 Serial Mode Summary Each port provides four operating modes These offer different communication protocols and baud rates These modes are summarized briefly as follows Detailed descriptions are provided later in this section The use of power management modes if supported will affect the internal clock rate and baud rate as shown in Table 7 D The following descriptions assume that power management modes are not in use 12 1 1 Mode 0 This mode provides synchronous communication with external devices It is commonly used to communicate with serial peripherals Serial I O occurs on the RXD pin The shift clock is provided on the TXD pin Note that whether transmitting or receiving the high speed microcontroller generates the serial clock Thus any device on the serial port in Mode 0 must accept the microcontroller as the master The baud rate in Mode 0 is a function of the oscillator input It will be the clock input divided by either 12 or 4 This is selected by the SM2 bit SCONO 5 or SCONI 5 as describ
70. the crystal frequency by a programmable value as shown below The divider value is expressed in clock crystal cycles The use of PMMI or PMM2 will further divide the clock cycle count by either 16 or 256 respectively Note that the reset timeout is 512 clocks longer than the interrupt regardless of whether the interrupt is enabled WDI WDO INTERRUPT DIVIDER 7 RESET DIVIDER 0 2 27 50 270 220 512 223 234512 0 1 1 0 1 0 1 226 226 512 MD2 MD1 Bits 2 1 0 030308 Timer 2 Clock Select This bit controls the division of the system clock that drives Timer 2 This bit has no effect when the timer is in baud rate generator or clock output modes Clearing this bit to 0 maintains 80C32 compatibility This bit has no effect on instruction cycle timing 0 Timer 2 uses a divide by 12 of the crystal frequency Timer 2 uses a divide by 4 of the crystal frequency Timer 1 Clock Select This bit controls the division of the system clock that drives Timer 1 Clearing this bit to 0 maintains 80C32 compatibility This bit has no effect on instruction cycle timing 0 Timer 1 uses a divide by 12 of the crystal frequency Timer 1 uses a divide by 4 of the crystal frequency Timer 0 Clock Select This bit controls the division of the system clock that drives Timer 0 Clearing this bit to 0 maintains 80C32 compatibility This bit has no effect on in
71. the original 8051 Where there were primarily one and two cycle instructions before there are now one two three and four cycle instructions Multiply and Divide require five cycles Note however that regardless of the number of cycles each instruction is at least 1 5 and most are 2 to 3 times faster than its original counterpart Table 5 A shows each instruction the number of clocks used in the high speed microcontroller and the number used in the 8051 for comparison The factor by which the high speed microcontroller improves on the 8051 is shown as the Speed Advantage A Speed Advantage of 3 0 means that the high speed microcontroller performs the same instruction three times faster that the 8051 Table 5 B provides a summary by instruction type Note that many of the instructions provide multiple op codes As an example the ADD A Rn instruction can act on one of 8 working registers There are 8 op codes for this instruction because it can be used on 8 independent locations Table 5 B shows totals for both number of instructions and number of op codes Averages are provided in the tables However the real speed improvement seen in any system will depend on the instruction mix Programs that use immediate or direct data combined with the accumulator or working registers will be improved the least These are two cycle two byte instructions Moderate performance improvement will be gained by emphasizing short branches and instructions that use only
72. to the shift clock frequency This be either oscillator divided by 4 or oscillator divided by 12 The relevant UART will begin transmitting when any instruction writes to SBUFO or SBUFI hex address 99h or Clh The internal shift register will then begin to shift data out The clock will be activated and will transfer data until the 8 bit value is complete Data will be presented one oscillator cycle prior to the falling edge of the shift clock TXD and an external device can latch the data using the rising edge The UART will begin to receive data when the REN bit in the SCON register SCONO 4 or SCONI 4 is set to logic 1 and the corresponding RI bit SCONO 0 or SCONI 0 is set to a logic 0 This condition tells the UART that there is data to be shifted in The shift clock TXD will activate and the UART will latch incoming data on the rising edge The external device should therefore present data on the falling edge This process will continue until 8 bits have been received The RI bit will automatically be set to logic 1 one machine cycle following the last rising edge of the shift clock on TXD This will cause reception to stop until the SBUF has been read and the RI bit cleared When RI is cleared another byte will be shifted in 12 4 2 Mode 1 This mode is asynchronous and full duplex using a total of 10 bits The 10 bits consist of a start bit logic 0 8 data bits and 1 stop bit logic 1 as illustrated in Figure 12 2 Th
73. use of this instruction automatically accesses the data area Although the original 8051 convention placed all data memory off chip many members of the high speed microcontroller family contain some data memory on chip From a software standpoint the physical location of the data area is not relevant because the same instructions are used Like the program segment if software accesses a data address that is above the on chip data area this access will automatically be routed to the expanded bus Thus data or peripherals that are off chip can be used in conjunction with on chip memory by selecting addresses that do not overlap As an example if the microcontroller has IkB of on chip data memory then a MOVX instruction at location 0400h will be directed off chip via the expanded bus The physical connection of off chip data memory is shown in Figure 6 3 This illustrates a 0580 320 with interfaced with an 8kB SRAM The data memory map begins at address 0000h since the DS80C320 has no on chip data memory A similar interconnection scheme would be implemented if a device with internal data memory such as the DS87C520 would be used Note that any external memory that overlapped the range of on chip data memory would not be used 030308 79 175 High Speed Microcontroller User s Guide Figure 6 1 Program Memory Interface 74F373 LBS ADDRESS LATCH 276256 32kB X 8 EPROM DATA BUS MSB ADDRESS Figure 6 2 Program Memo
74. 0 is set and DPHI are used in place of DPL DPH during DPTR operations 4 2 6 Data Pointer High 1 DPH1 7 6 5 4 3 2 1 0 SFR 85h 1 7 DPHI 6 DPH1 5 DPH1 4 DPH1 3 DPH1 2 DPH1 1 DPH1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset DPH1 7 DPH1 0 Bits 7 0 Data Pointer High 1 This register is the high byte of the auxiliary 16 bit data pointer When the SEL bit DPS 0 is set and DPHI used in place of DPL DPH during DPTR operations Rev 030308 26 of 175 High Speed Microcontroller User s Guide 4 2 7 Data Pointer Select DPS SFR 86h Bits 7 1 SEL Bit 0 SFR 87h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SEL R 0 R 0 R 0 R 0 R 0 R 0 R 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Reserved These bits will read 0 Data Pointer Select This bit selects the active data pointer 0 Instructions that use the DPTR will use DPL and DPH 1 Instructions that use the DPTR will use DPL1 and DPHI 4 2 8 Power Control PCON 7 6 5 4 3 2 1 0 SMOD 0 SMODO GF1 GFO STOP IDLE RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SMOD_0 Bit 7 SMOD0 Bit 6 Bits 5 4 GF1 Bit 3 0 Bit 2 STOP Bit 1 IDLE Bit 0 Rev 030308 Serial P
75. 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset EA Global Interrupt Enable This bit controls the global masking of all interrupts except Bit 7 power fail interrupt which is enabled by the EPFI bit WDCON 5 0 Disable all interrupt sources This bit overrides individual interrupt mask settings 1 Enable all individual interrupt masks Individual interrupts will occur if enabled ES1 Enable Serial Port 1 Interrupt This bit controls the masking of the serial port 1 interrupt Bit 6 0 Disable all serial port 1 interrupts 1 Enable interrupt requests generated by the RI 1 SCONI 0 or TI 1 SCONI 1 flags ET2 Enable Timer 2 Interrupt This bit controls the masking of the Timer 2 interrupt Bit 5 0 Disable all Timer 2 interrupts 1 Enable interrupt requests generated by the TF2 flag T2CON 7 ESO Enable Serial Port 0 Interrupt This bit controls the masking of the serial port 0 interrupt Bit 4 0 Disable all serial port 0 interrupts 1 Enable interrupt requests generated by the RI 0 SCONO 0 TI 0 SCONO 1 flags 1 Enable Timer 1 Interrupt This bit controls the masking of the Timer 1 interrupt Bit 3 0 Disable all Timer 1 interrupts 1 Enable all interrupt requests generated by the TF1 flag TCON 7 Enable External Interrupt 1 This bit controls the masking of external interrupt 1 Bit 2 0 Disable external interrupt 1 PE
76. 130 2 Glock Out ModE ia aa 131 Watehdog TIMET 132 id ELA 144 24 AE 146 senal Porn Moge Td TETUER 148 Sora PO 150 nter ream cnc a 154 7 of 175 High Speed Microcontroller User s Guide LIST OF TABLES 4 A DS80C310 udi 17 Table 4 B 580 310 SFR Reset Values 18 Table 4 580 320 580 323 SFR Locations 19 Table 4 0 D880C320 DS80C323 SFR Reset 20 Table 4 E DS583C520 D5870520 SFR trier Cur pica os prt Ras 21 Table 4 F D5930520 DS870920 SFR Reset Values 22 Table 4 5 SFR LOCATIONS 23 Table 4 H 587 530 SFR Reset 24 Table 4 Instructions That Affect Flag Settings nennen 62 Table 5 A Instruction Timing Comparison rtu ik teli Pel UE EK Ro KR 72 Tape SE sic uictor eee ae 75 Table 6 A Data Memory Access 77 Tab
77. 2 1 TxM 0 2 1 T2M 0 5 2 0 5 2 1 SMOD 0 SMOD 1 0 0 Reserved 0 1 4 4 12 2 2 12 4 64 32 0 0 64 192 32 32 3072 64 1024 512 1 1 1024 PMM2 1024 302 512 512 1024 1024 16348 8192 7 3 3 Switchback The switchback feature solves one of the most vexing dilemmas faced by power conscious systems Many applications are unable to use the Stop and Idle modes because they require constant computation Traditionally system designers could not reduce the operating speed below that required to process the fastest event This meant that system architects would be forced to operate their systems at the highest rate of speed even when it was not required The switchback feature allows a system to operate at a relatively slow speed and burst to a faster mode when required by an external event When this feature is enabled by setting the Switchback Enable bit SWB PMR 5 a qualified interrupt or serial port reception or transmission will cause the device to return to divide by 4 mode A qualified interrupt is defined as an interrupt that has occurred and been acknowledged This means that an interrupt must be enabled and also not blocked by a higher priority interrupt After the event is complete software can manually return the device to the appropriate PMM The following sources can trigger a switchback External interrupt 0 1 2 3 4 5 Serial start bit detected serial port 0 1 Tra
78. 320ns 12 480ns 1 5 MOV A Ri E6 E7 4 160ns 12 480ns 3 MOV A 74 8 320 5 12 480 5 1 5 MOV Rn A 8 4 16015 12 48015 3 Rn direct 8 8 32015 24 96015 3 78 7F 8 320ns 12 480ns 1 5 MOV direct A F5 8 320ns 12 480ns 1 5 MOV direct Rn 88 8F 8 320ns 24 960ns 3 MOV direct direct 85 12 480ns 24 960ns 2 MOV direct Ri 86 87 8 320ns 24 960ns 3 MOV direct data 75 12 480ns 24 960ns 2 MOV Ri A F6 F7 4 160ns 12 480ns 3 MOV Ri direct 7 8 32015 24 96015 3 MOV Ri data 76 77 8 320 5 12 480 5 1 5 DPTR data 16 90 12 480ns 24 960ns 2 MOVC A 93 12 480ns 24 960ns 2 MOVC A 83 12 480ns 24 960ns 2 Ri E2 E3 8 320ns 24 960 ns 3 MOVX A 0 8 320ns 24 960ns 3 MOVX Ri F2 F3 8 320ns 24 960ns 3 MOVX DPTR F0 8 320ns 24 960ns 3 PUSH direct 8 32015 24 96015 3 POP direct DO 8 320ns 24 960ns 3 XCH A Rn C8 CF 4 160ns 12 480ns 3 XCH A direct C5 8 320ns 12 480ns 1 5 XCH A Ri C6 C7 4 160ns 12 480ns 3 XCHD A Ri D6 D7 4 160ns 12 480ns 3 CLR C C3 4 160ns 12 480ns 3 CLR bit C2 8 320ns 12 480ns 1 5 SETB C D3 4 160ns 12 480ns 3 SETB bit D2 8 320ns 12 480ns 1 5 CPLC B3 4 160ns 12 480ns 3 CPL bit B2 8 320ns 12 480ns 1 5 ANL C bit 82 8 320ns 24 960ns 3 ANL C bit BO 8 320ns 24 960ns 3 ORL C bit 2 8 320ns 24 960ns 3 ORL C bit 0 8 320ns 24 960ns 3 MOV C bit A2 8 320ns 12 480ns 1 5 MOV bit C 92 8 320ns 24 960ns 3 ACA
79. 5 Setthe ERTCI enable bit EIE 5 030308 158 of 175 High Speed Microcontroller User s Guide Setting the alarm to cause an interrupt once during a 24 hour period is done by setting all the alarm registers to the desired value and enabling all compare bits A recurring alarm is enabled by clearing the compare enable bits associated with one or more alarm registers For example to specify an alarm to occur once a minute the SSCE and SCE bits would be set In general a recurring alarm is set using the next lower time increment than the desired interrupt period For example if an alarm was desired once an hour on the hour a compare on the real time alarm minute register would be performed because the real time clock minute register will match the corresponding alarm register only once an hour The RTASS RTAS and RTAM registers would be cleared to 00h and the SSCE SCE and MCE bits would all be set to 1 to match on the time xx 00 00 00 Writing an invalid time to these registers e g loading the RTAM register with 3Dh or 61 minutes will never cause a match by the RTC It is the responsibility of the software to ensure that only valid times are written to these registers It is important to remember that any RTC register whose corresponding compare enable bit is cleared to 0 will always be treated as a match The alarm registers are interrogated once per subsecond tick to check for an alarm condition If the SSCE bit was set to
80. 5 aa CORO ESO IE 4 PSO 4 Timer 2 Overflow 2Bh 6 TF2 T2CON 7 2 IE 5 PT2 IP 5 Serial Port 1 3Bh 7 i econ 1 IE 6 PS1 IP 6 Extemal Interrupt 2 43h 8 IE2 EXIF 4 EIE 0 PX2 EIP 0 External Interrupt 3 4Bh 9 5 EX3 EIE 1 PX3 Extemal Interrupt 4 53h 10 EXIF 6 EX4 PX4 EIP 2 External Tatem pt 5 SBh TES 7 EX5 EIE 3 5 EIP 3 Watchdog Interrupt 63h 12 WDIF WDCON3 EWDI EIE 4 PWDI 4 Real Time Clock 6Bh 13 RTCIF RTCC 1 ERTCI EIE 5 PRTCI EIP 5 Note Unless marked these flags must be cleared manually by software Cleared automatically by hardware when the service routine is vectored to If edge triggered cleared automatically by hardware when the service routine is vectored to If level triggered flag follows the state of the pin 91 Interrupt Overview An interrupt allows the software to react to unscheduled or asynchronous events When an interrupt occurs the CPU is expected to service the interrupt This service takes the form of an interrupt service routine ISR The ISR resides at a predetermined address as shown in Table 9 A When the interrupt occurs the CPU will vector to the appropriate location It will run the code found at this location staying in an interrupt service state until done with the ISR Once an ISR has begun it can be interrupted only by a higher priority interrupt The ISR is terminated by a return from inte
81. 6 5 4 3 2 1 0 4 X12 6 TRM2 TRM2 TRMI TRMI TRMO TRMO RT RT RT RT RT RT RT RT R Unrestricted Read W Unrestricted Write n Value after Reset See description E4K Bit 7 X12 6 Bit 6 TRM2 Bit 5 TRM2 Bit 4 Bit 3 Bit 2 0 Bit 1 TRMO Bit 0 Rev 030308 External 4096Hz RTC Signal Enable This bit enables the output of a 4096Hz signal on pin P1 7 derived from the RTC Setting this bit overrides any other function of the pin It is used for adjusting the frequency of the 32 768kHz RTC crystal oscillator using the trim bits This bit is cleared to 0 after any reset including a no battery reset 0 Calibration function disabled P1 7 pin will function per the normal pin description 1 4096Hz signal output on P1 7 RTC Crystal Capacitance Select This bit selects the internal loading capacitance of the RTC crystal amplifier This bit is set to 1 after a no battery reset and unchanged by all other forms of reset 0 loading is set for 6pF crystal loading is set for 12 5pF crystal RTC Trim Bit 2 This bit controls the relative adjustment of the RTC internal capacitance It is used to calibrate the RTC oscillator frequency This bit is set to 1 after a no battery reset and unchanged by all other forms of reset RTC Inverted Trim Bit 2 This bit controls the relative adjustment of the RTC internal capacitance It is used to calibrate the RTC osc
82. ANSMIT TIMING LDSBUF SHIFT START RECEIVE TIMING RXD BIT DETECTOR SAMPLING SERIAL INTERRUPT RECEIVE SHIFT REGISTER DIVIDE BY 16 BIT DETECTION Do Dt X D2 X X Ds X 06 AD X TB8 STOP START poX ADAX ARBS sur NM N N0 NM d NM MNM RI 40 030308 148 of 175 High Speed Microcontroller User s Guide Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin The pin is then sampled according to the baud rate speed The 9th bit is placed in the RBS bit location in SCON SCONO 2 or SCONI 2 When a stop bit has been received the data value will be transferred to the SBUF receive register hex address 99h or The RI bit SCONO 0 or SCONI 0 will be set to indicate that a byte has been received At this time the UART can receive another byte Once the baud rate generator is active reception can begin at any time The REN bit SCONO 4 or SCONI 4 must be set to logic 1 to allow reception The falling edge of a start bit on the RXD pin will begin the reception process Data must be shifted in at the selected baud rate At the middle of the 9th bit time certain conditions must be met to load SBUF with the received data 1 RI must 0 and either 2 If SM2 0 the state of the 9th bit does not matter or 3 If SM2 1 the state of the 9th bit must 1
83. BR1225 Lithium Polycarbon Monofluoride 3 38 Battery life can be calculated by dividing the rated battery capacity by the current specified on the device specific data sheet Note that this determines the minimum battery life while Vcc is applied to the device it draws negligible current from the battery and so battery life will be lengthened accordingly 030308 161 of 175 High Speed Microcontroller User s Guide Backup current is a function of temperature and therefore battery life is dependent on the operating environment The registers shown in Table 15 B are battery backed and one or more bits will be indeterminate following a no battery reset They should be initialized as part of a no battery reset procedure Table 15 B Battery Backed SFRs REGISTER NAME LOCATION TRIM 96h RTASS F2h RTAS F3h RTAM F4h RTAH F5h RTCC F9h RTCSS FAh RTCS FBh RTCM FCh RTCH FDh RTCDO FEh RTCDI FFh 15 2 Lithium Battery Considerations Lithium primary nonrechargeable batteries can fail and or rupture if subjected to reverse current from the device they are powering The battery switching circuitry inside the DS87C530 was designed to reduce or eliminate the need for external hardware required to meet battery safety regulations As shown in the DS87C530 data sheet a current limiting resistor is always in series with a switching field effect transistor regardless of whethe
84. Byte 2 IF A 0 THEN PC rel Rev 030308 168 of 175 High Speed Microcontroller User s Guide INSTRUCTION CODE MNEMONIC D D D D D D HEX BYTE CYCLE EXPLANATION JC rel 0 1 0 0 0 0 0 0 40 2 3 PC 2 I I6 501 4 B Byte2 IF C THEN PC PC rel JNC rel 0 1 0 1 0 0 0 0 50 2 3 PC 2 Ty T6 T5 T4 2 Ti Byte 2 IF C 0 THEN PC PC rel JB bit rel 0 0 1 0 0 0 0 0 20 3 4 PC 3 b b b b b bo Byte 2 IF bit THEN I fg 5 14 d 1 Ty Byte3 PC rel JNB bit rel 0 0 0 1 0 0 0 0 30 3 4 3 b b b b b b b 2 IF bit 0 THEN I s B f Ty Byte3 PC PC rel JBC bit rel 0 0 0 1 0 0 0 0 10 3 4 3 b b b b b bo Byte 2 IF bit THEN I Ig I5 1 B h ro Byte3 0 PC PC rel CJNE A 0 0 0 1 0 0 0 0 5 3 4 3 direct rel Byte2 IF direct lt Z I 15 t ro Byte 3 THEN PC PC T rel and C 0 S OR 2 IF direct gt A ca THEN PC PC gt rel and 1 2 CJNE 1 0 1 1 0 10 0 4 3 4 3 data rel d d ds dj dj d d Byte2 IF data lt A I 501 t Byte3 THEN PC rel and 0 OR IF gt
85. C INPUT TO TIMER BLADE CLK MODE TIMER INPUT BY 12 C T2 T2CON 1 DIVIDE BY 4 OSC 1 1 OSC 16 0 78 2 OSC 256 1 1 2 H2 PTET ELT T2 P1 0 TR2 2 2 RCAP2H T2EX P1 1 2 T2CON 3 T2CON 6 TIMER a INTERRUPT Rev 030308 126 of 175 High Speed Microcontroller User s Guide 11 7 3 16 Bit Auto Reload Timer Counter This mode is illustrated in Figure 11 5 When Timer 2 reaches an overflow state i e rolls over from FFFFh to 0000h it will set the TF2 Flag This flag can generate an interrupt if enabled In addition the timer will restore its starting value and begin timing or counting again The starting value is preloaded by software into the capture registers RCAP2L and RCAP2H These registers cannot be used for capture functions while also performing auto reload so these modes are mutually exclusive Auto reload is invoked by the CP RL2 T2CON 0 bit When set to logic 0 the timer is in auto reload mode When CP RL2 is set to a logic 1 the timer is in capture mode described above If the oscillator time base is used C T2 T2CON 1 0 the timer s input may be selected to be oscillator cycles divided by either 12 or 4 as determined by T2M CKCON 5 Otherwise pulses on pin T2 P1 0 are counted when C T2 1 As in other modes Counting or timing is enabled or disabled with TR2 T2CON 2 When in auto reload mode Timer 2 can also be forced to reload with the
86. CLK 0 causes Timer 1 overflow to be used as the receive clock T2CON 4 Transmit Clock Flag TCLK This bit determines whether Timer 1 or 2 1 used for Serial Port 0 timing of Transmit data in Serial Modes 1 or 3 TCLK 1 causes Timer 2 overflow to be used as the transmit clock TCLK 0 causes Timer 1 overflow to be used as the transmit clock 12 3 Baud Rates Each mode has a baud rate generator associated with it This generator is generally the same for each UART Several of the baud rate generation techniques have options and these options are independent for the two UARTS The baud rate descriptions given below are separated by mode 12 3 1 Mode 0 Baud rates for this mode are driven directly from the crystal speed divided by either 12 or 4 Mode 0 is synchronous so that the shift clock output frequency will be the baud rate The formula is simply as follows Oscillator Frequency Mode 0 Baud Rate 12 or Oscillator Frequency Mode 0 Baud Rate 4 The default case is divide by 12 The user can select by using the SM2 bit in the associated SCON register For Serial Port 0 the SM2 0 bit is SCONO 5 For Serial Port 1 the 5 2 0 bit is SCONI 5 When SM2 is set to logic 0 the baud rate is generated using a divide by 12 of the oscillator input When 5 2 is set to logic 1 the baud rate is generated using divide by 4 Note that this use of SM2 differs from a standard 80C32 In that device SM2 had no valid use when the UART was i
87. CON 0 The instruction that executes this step will be the last instruction prior to freezing the program counter Once in Idle all resources are preserved There are two ways to exit the Idle mode First any interrupt that 15 enabled will cause an exit This will result in a jump to the appropriate interrupt vector The IDLE bit in the PCON register will be cleared automatically On returning from this vector using the RETI instruction the next address will be the one immediately after the instruction that invoked the Idle state The Idle mode can also be removed using a reset Any of the three reset sources can do this On receiving the reset stimulus the CPU will be placed in a reset state and the Idle condition cleared When the reset stimulus is removed software will begin execution as for any reset Since all clocks are active there will be no delay after the reset stimulus is removed Note that if enabled the Watchdog Timer continues to run during Idle and must be supported 7 2 2 Stop Mode Stop mode is the lowest power state that the high speed microcontroller can enter This is achieved by stopping all on chip clocks resulting in a fully static condition No processing is possible timers are stopped and no serial communication is possible Processor operation will halt on the instruction that sets the STOP bit The internal amplifier that excites the external crystal will be disabled halting crystal oscillation in Stop mode Tabl
88. DDRESS RANGE MEMORY ACCESS 0000h FFFFh External Data Memory default 1 0000h 03FFh Internal SRAM Data Memory 0400h FFFFh External Data Memory Reserved Reserved 0000h 03FFh Internal SRAM Data Memory 0400h FFFBh Reserved FFFCh System Control Byte EPROM Read Only FFFDh FFFFh Reserved 4 2 32 1 System Control Byte Description EPROM FFFCh Bits 7 3 LB3 LB2 LB1 Bits 2 1 0 The System Control Byte is a special EPROM location that contains nonvolatile system information This byte is set during EPROM programming and is not alterable by software This register can only be read when both Data Memory Enable bits are set The user must be sure that this location is programmed by a special programming utility supplied with the programming device Reserved These bits will read 1 These bits should be set to 1 during programming EPROM Program Lock Bit to 1 These bits show the status of the firmware security of the on board EPROM Bit combinations other than shown are illegal EPROM PROTECTION MODE Unconditional verification full external operation Additional EPROM programming allowed without full device erasure Verification using encryption execution of external MOVC instruction on internal program memory is disabled All other program execution and data memory access allowed Device must be fully erased before EPROM can be programmed again Verification disabled execution of ext
89. DE 1 Enable all interrupt requests generated by the INTI pin ETO Enable Timer 0 Interrupt This bit controls the masking of the Timer 0 interrupt Bit 1 0 Disable all Timer 0 interrupts 1 Enable all interrupt requests generated by the flag TCON 5 0 Enable External Interrupt 0 This bit controls the masking of external interrupt 0 Bit 0 0 Disable external interrupt 0 1 Enable all interrupt requests generated by the INTO pin 4 2 23 Slave Address Register 0 SADDRO 7 6 5 4 3 2 1 0 SFR A9h SADDRO 7 SADDRO 6 SADDRO 5 SADDRO 4 SADDRO 3 SADDR02 SADDRO 1 SADDRO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SADDRO0 7 SADDR0 0 Bits 7 0 Rev 030308 Slave Address Register 0 This register is programmed with the given or broadcast address assigned to serial port 0 37 of 175 High Speed Microcontroller User s Guide 4 2 24 Slave Address Register 1 SADDR1 7 6 5 4 3 2 1 0 SFR SADDRI 7 SADDRI 6 SADDRI 5 SADDR1 4 SADDRI 3 SADDRI2 SADDRI 1 SADDRI O RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SADDRI 7 Slave Address Register 1 This register is programmed with the given or broadcast SADDRI 0 address assigned to serial port 1 Bits 7 0 4 2 25 Port 3 P3 7 6 5 4 3 2 1 0
90. DO located at PCON 6 When SMODO is set to logic 1 the framing error information is shown in SMO FE SCONO 7 or SCON1 7 When SMODO is set to logic 0 the SMO function 15 accessible The information for bits SMO and FE 15 actually stored in different registers Changing SMODO only changes which register is accessed not the contents of either The FE bit will be set to a 1 when a framing error occurs It must be cleared by software Note that the SMODO state must be 1 while reading or writing the FE bit Also note that receiving a properly framed serial word will not clear the FE bit This must be done in software 030308 149 of 175 High Speed Microcontroller User s Guide Figure 12 4 Serial Port Mode 3 TIMER 2 TIMER 1 OVERFLOW OVERFLOW DIVIDE BY2 SMOD 0 PCON 7 OR SMOD 1 Q WDCON 7 0 TCLK 2 4 AVAILABLE SERIAL PORT 0 ONLY RCLK T2CON 5 T1 FLAG SCONx 1 TRANSMIT TIMING SHIFT LDSBUF START TXD RECEIVE TIMING RXD BIT DETECTOR SAMPLING BY 16 TRANSMIT SHIFT REGISTER SERIAL BUFFER BAUD SERIAL BUFFER LOAD SERIAL CONTROI RESET R1 FLAG SCONx 0 SERIAL INTERRUPT DIVIDE BY 16 BIT DETECTION RD RB8 SCONx 3 P3 1 TXD LATCH PIN DATA BUS SBUF RECEIVE DATA BUFFER WR RECEIVE SHIFT REGISTER po Dt X D2 X X Ds 06 X07 TB8 STOP
91. EC MEE IS xit m Em 36 LE MU Codice PN UU TTE 37 4 223 slave Adoress Register OADIDPBU oa AT EAE a AE aA EIN DM o t 37 4224 Slave Address Register 1 SADDR 38 ALLS POUS P 00004 ___ __ __ _______ _ _ 38 Rev 030308 2 of 175 High Speed Microcontroller User s Guide dun MESH ne ae ety Datta aided bie ent 39 4 2 27 Slave Address Mask Enable Register 0 39 4 2 28 Slave Address Mask Enable Register 1 1 40 LA S c SCONTI DH 40 Sarat 41 EI FROM 42 4239 PowerManagement Register PPM e sess ABER 43 EIOS STATUS bx ELA Dn suse e 45 ZEE TIE ACCESS ka ua FAR M e ad ede id PA 46 CONO TECON mte 46 uS 47 4827 LSB 48 4288 MoB RCAF Rm 48 00 TROT ESB mpm 48 4240 TRO tn PER ERR eI HEIC
92. Fh are ignored Attempts to set the RTCRE and RTCWE bits simultaneously will be ignored When this bit is cleared software must wait 4 machine cycles before setting either the RTCRE or RTCWE bit again 1 Writes to the clock registers are permitted during a 1ms window starting from the time this bit is set Immediately after setting this bit software must wait 4 machine cycles to allow all time registers to synchronize The user should clear this bit when the desired updates are complete although it will clear automatically after 1 95ms 1 not cleared in software RTCIF RTC Interrupt Flag This bit indicates that a RTC alarm match has been made Bit 1 between all the enabled alarm registers and their corresponding clock registers This bit will generate an RTC Interrupt if the ERTCI bit EIE 5 is set and must be cleared by software following an interrupt Setting this bit cannot generate RTC interrupts Clearing all alarm compare enable bits RTCC 7 4 will also clear this bit This bit will be indeterminate following a no battery reset and is unaffected by all other resets This bit cannot be set in software 0 No RTC interrupts are pending 1 Interrupt is pending active RTCE RTC Enable This bit enables disables the RTC oscillator halting the RTC This bit Bit 0 must be accessed using a Timed Access procedure This bit will be indeterminate following a no battery reset and is unaffected by all other resets If RTC opera
93. If these conditions are true then SBUF will be loaded with the received byte RB8 will be loaded with the 9th bit and RI will be set If these conditions are false then the received data will be lost SBUF and RB8 not loaded and RI will not be set Regardless of the receive word status after the middle of the stop bit time the receiver will go back to looking for a 1 0 transition RXD Data is sampled in a similar fashion to Mode 1 with the majority voting on three consecutive samples Mode 2 uses the sample divide by 16 counter with either the oscillator divided by 2 or 4 12 4 4 Mode 3 This mode has the same operation as Mode 2 except for the baud rate source As shown in Figure 12 4 Mode 3 can use Timer 1 or 2 for Serial Port 0 and Timer 1 for Serial Port 1 The bit shifting and protocol are the same 12 5 Framing Error Detection A framing error occurs when a valid stop bit is not detected This results in the possible improper reception of the serial word The UART can detect a framing error and notify the software Typical causes of framing errors are noise and contention The Framing Error condition is reported in the SCON register for the corresponding UART The Framing Error bit FE is located in SCONO 7 or SCONI 7 Note that this bit normally serves as SMO and is described as SMO FE 0 or SMO FE 1 in the register description Framing Error information is made accessible by the Framing Error Detection Enable bit It is SMO
94. LL addr 11 Hex code M DE ee Byte 12 480ns 24 960ns 2 LCALL addr 16 12 16 640ns 24 960ns 1 5 RET 22 16 640ns 24 960ns 1 5 030308 73 of 175 High Speed Microcontroller User s Guide HSM 8051 HSM vs 8051 INSTRUCTION Cope CLOCK CLOCK 8 _ SPEED CYCLES CYCLES ADVANTAGE RETI 32 16 640ns 24 960ns 1 5 AJMP addr 11 Hex code et Byte 1 12 480ns 24 960ns D LJMP addr 16 2 16 480ns 24 960ns 1 5 JMP A DPTR 73 12 480ns 24 960ns 2 SJMP rel 80 12 480ns 24 960ns 2 JZ rel 60 12 480ns 24 960ns 2 JNZ rel 70 12 480ns 24 960ns 2 JC rel 40 12 480ns 24 960ns 2 JNC rel 50 12 480ns 24 960ns 2 JB bit rel 20 16 640ns 24 960ns 1 5 JNB bit rel 30 16 640ns 24 960ns 1 5 JBC bit rel 10 16 640ns 24 960ns 1 5 A direct rel B5 16 640ns 24 960ns 1 5 CJNE A data rel B4 16 640ns 24 960ns 1 5 CJNE Rn data rel B8 BF 16 640ns 24 960ns 1 5 CJNE Ri data rel B6 B7 16 640ns 24 960ns 1 5 DJNZ Rn rel D8 DF 12 480ns 24 960ns 2 DJNZ direct rel 05 16 640 5 24 960ns 1 5 NOP 00 4 160ns 12 480ns 3 030308 74 175 High Speed Microcontroller User s Guide Table 5 B Instruction Speed Summary INSTRUCTION CATEGORY QUANTITY SPEED ADVANTAGE Total Instructions One Cycle One Byte 37 3 0 Total Instructions Two Cycle One Byte 4 3 0 To
95. M 7 3 4 Clock Source Selection The high speed microcontroller family supports three different clock sources for operation As with most microcontrollers the device can be clocked from an external crystal using the on board crystal amplifier or a clock source can supplied by an external oscillator In addition some members of the high speed microcontroller family incorporate an on board ring oscillator to provide a quick resumption from Stop mode The ring oscillator is a low power digital oscillator internal to the microcontroller When enabled it provides an approximately 2MHz 4MHz clock source for device operation without external components The ring oscillator is not as stable as an external crystal and software should refrain from performing timing dependent operations including serial port activity while operating from the ring oscillator The ring oscillator provides many advantages to the designers of microcontroller based systems One is that it allows Maxim microcontrollers to perform a fast resume from Stop mode eliminating the crystal warmup delay when restarting the device As an added feature the DS87C520 and DS87C530 will also support extended operation from the ring oscillator not only during the crystal warmup period when resuming from Stop All devices in the high speed microcontroller family must begin operation following a power on reset from an external clock source either an external crystal or oscillator Software
96. N REGISTER LOCATION BIT POSITION EWT Enable Watchdog Timer Reset WDCON D 8h WDCON 1 RWT Reset Watchdog Timer WDCON D8h WDCON 0 WDI Watchdog Interval 1 CKCON 8Eh CKCON 7 WDO Watchdog Interval 0 CKCON 8Eh CKCON 6 WTRF Watchdog Timer Reset Flag WDCON D8h WDCON 2 EWDI Enable Watchdog Timer Interrupt EIE E8h EIE 4 WDIF Watchdog Interrupt Flag WDCON D8h WDCON 3 The watchdog timer is a free running timer and will be disabled by a power fail reset A watchdog timeout reset will not disable the watchdog timer but will restart the timer In general software should set the watchdog to whichever state is desired just to be certain of its state Control bits that support watchdog operation are described below 11 9 1 Watchdog Control Register Summary WDCON 3 Watchdog Interrupt Flag WDIF If the watchdog interrupt is enabled EIE 4 hardware will set this bit to indicate that the watchdog interrupt has occurred If the interrupt is not enabled this bit indicates that the timeout has passed If the watchdog reset is enabled WDCON 1 the user has 512 clocks to strobe the watchdog prior to a reset Software or any reset can clear this flag WDCON 2 Watchdog Timer Reset Flag WTRF Hardware will set this bit when the watchdog timer causes a reset Software can read it but must clear it manually A power fail reset will also clear the bit This bit assists software in determining the cause of a reset If EWT 0 the watchdo
97. NGE DATA POINTER TO SOURCE 2 INC DPTR NEXT SOURCE ADDRESS 3 DJNZ R5 MOVE FINISHED WITH TABLE 3 030308 82 of 175 High Speed Microcontroller User s Guide 6 5 2 64 Byte Block Move Without Dual Data Pointer SH and SL are high and low byte source address DH and DL are high and low byte of destination address CYCLES MOV R5 64 NUMBER OF BYTES TO MOVE 2 MOV DPTR SHSL LOAD SOURCE ADDRESS 3 MOV R1 51 SAVE LOW BYTE OF SOURCE 2 MOV R2 5 SAVE HIGH BYTE OF SOURCE 2 MOV R3 DL SAVE LOW BYTE OF DESTINATION 2 MOV DH SAVE HIGH BYTE OF DESTINATION 2 MOVE THIS LOOP IS PERFORMED R5 TIMES IN THIS EXAMPLE 64 MOVX DPTR READ SOURCE DATA BYTE 2 MOV R1 DPL SAVE NEW SOURCE POINTER 2 MOV R2 DPH 2 MOV DPL R3 LOAD NEW DESTINATION 2 MOV DPH R4 A 2 MOVX DPTR A WRITE DATA TO DESTINATION 2 INC DPTR NEXT DESTINATION ADDRESS 3 MOV R3 DPL SAVE NEW DESTINATION POINTER 2 MOV R4 DPH P 2 MOV DPL R1 GET NEW SOURCE POINTER 2 MOV DPH R2 2 2 NEXT SOURCE ADDRESS 3 DJNZ R5 MOVE FINISHED WITH TABLE 3 030308 83 of 175 High Speed Microcontroller User s Guide 6 6 Data Memory Timing Data memory timing refers to the execution of the MOVX instruction This instruction includes program fetch memory access then a read or write memory access The program fetch for MOVX instruction is no different from any other instruction The un
98. OPERATE OR KEEP ACCURATE 171 SERM DOES NOT WORK ulta 172 HIGH SPEED MICROCONTROLLER DOES NOT WORK IN EXISTING 8051 172 MICROCONTROLLER DEVELOPMENT 2 22 173 TECHNICAE S 173 TUR 173 SOFTWARE COMPATIBILITY 2 ccccnsnccccntessnccesnncosencossaconsnadasancesncassndensaccnsancassndansmcansnetasancerentensnece 173 HIGH LEVEL LANGUAGE 173 REVISION 175 030308 6 of 175 High Speed Microcontroller User s Guide Figure 4 1 Figure 4 2 Figure 4 3 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 7 1 Figure 7 2 Figure 9 1 Figure 10 1 Figure 10 2 Figure 10 3 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 11 7 Figure 11 8 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 13 1 030308 LIST OF FIGURES Memory 15 oclo c Ri CUN 16 Scratchpad Register OO EB MI 16 Sip EE nee DE ARCU Fork 64 oer callo joi fe To reer ae eee ne eer 64 cp
99. OVX is controlled by a value in a special function register described below This allows the user to select a stretch value between zero and seven A Stretch of zero will result in a two machine cycle MOVX This leaves one machine cycle to actually read or write data A Stretch of seven will result in a MOVX of nine cycles The time is added to the middle of the memory strobe creating a very long read or write cycle The Stretch value can be changed dynamically under software control depending on the type of memory or peripheral to be accessed On reset the Stretch value will default to a one resulting in a three cycle MOVX Therefore data memory access will not be performed at full speed This is a convenience to existing designs that may not have fast RAM in place When maximum speed is desired the software should select a Stretch value of zero Note that faster RAMs will be needed When using very slow RAM or peripherals a larger stretch value can be selected Note that this affects data memory only and the only way to slow program memory ROM access is to use a slower crystal Using a Stretch value between one and seven results in a wider read write strobe allowing more time for memory peripherals to respond The microcontroller stretches the read write strobe and all related timing The full speed access is shown in Figure 6 4 Note that this is not the reset default case A three cycle MOVX is shown in Figure 6 5 This is the reset default cond
100. P1 1 EXEN2 must be set for this function This flag must be cleared to 0 by software Writing a one to this bit will force a timer interrupt if enabled Bit 5 Receive Clock Flag RCLK This bit determines whether Timer 1 or 2 is used for Serial Port 0 timing of received data in Serial Modes 1 or 3 RCLK 1 causes Timer 2 overflow to be used as the receive clock RCLK 0 causes Timer 1 overflow to be used as the receive clock Bit 4 Transmit Clock Flag TCLK This bit determines whether Timer 1 or 2 is used for Serial Port 0 timing of Transmit data in Serial Modes 1 or 3 TCLK 1 causes Timer 2 overflow to be used as the transmit clock TCLK 0 causes Timer 1 overflow to be used as the transmit clock Bit 3 Timer 2 External Enable EXEN2 Setting this bit to a 1 allows a capture or reload to occur as a result of a falling transition on T2EX 1 1 if Timer 2 15 not generating baud rates for the serial port EXEN2 0 causes Timer 2 to ignore all external events at T2EX Bit 2 Timer 2 Run TR2 Setting this bit to a 1 starts Timer 2 Setting it to a 0 stops Timer 2 Bit 1 Counter Timer Select C T2 Setting this bit to a 0 selects a timer function for Timer 2 Setting it to a 1 selects a counter of falling transitions on T2 P1 0 Timer 2 runs at 4 clocks per tick or 12 clocks per tick as programmed by CKCON 5 This bit will be overridden and Timer 2 directed to use a divide by 2 clock if either the baud rate generator or clock outpu
101. P3 3 TOONS TF1 7 TIMER 1 FUNCTIONS SHOWN IN PARENTHESIS Rev 030308 121 of 175 High Speed Microcontroller User s Guide 11 4 Mode 2 This mode configures the timer as an 8 bit timer counter with automatic reload of the start value This configuration is shown in Figure 11 2 and is selected when bits 1 and MO of the TCON register are set to 1 and 0 respectively When configured in Mode 2 the timer uses TLn to count and THn to store the reload value Software must initialize both TLn and THn with the same starting value for the first count to be correct Once the TLn reaches FFh it will be automatically loaded with the value in THn The THn value remains unchanged unless modified by software Mode 2 is commonly used to generate baud rates since it runs without continued software intervention As in modes 0 and 1 mode 2 allows counting of either oscillator cycles crystal 12 or crystal 4 or pulses on pin Tn C T 1 when counting is enabled by TRn and the proper setting of GATE and INTn pins Figure 11 2 Timer Counter 0 and 1 Mode 2 TOM CKCON 3 T1M 4 C T TMOD2 OSC INPUT TO TIMER DIVIDE C T TMOD 6 CLKMODE INPUT BY 12 TLO DIVIDE BY 4 5 1 TL1 1 OSC 16 7 2 2 OSC 256 B TO P3 4 T1 P3 5 TRO TCON 4 TR1 TCON 6 GATE TMOD 3 GATE 7 INTO P3 2 TCON 5 P3 3 TCON 7 H
102. Products
103. ROL INTERNAL DATA BUS WRITE ENABLE TT READ LATCH PIN ENABLE 10 3 Ports 1 and 3 Ports 1 and 3 are general purpose I O ports with optional special functions associated with each pin Enabling the special function automatically converts the I O pin to that function To ensure proper operation each alternate function pin should be programmed to a logic 1 For example enabling the UART converts P3 0 and P3 1 to the serial I O functions The drive characteristics of these pins do not change when the pin is configured for general I O or as the special function associated with that pin The exceptions are pins P3 6 and P3 7 which employ the current limited transition drivers described later when used as RD and WR signals The drive characteristics of Port 1 and Port 3 are the same as for Port 2 non bus mode That 15 the logic 0 15 created by a strong pulldown The logic 1 is created by a strong transition pullup that changes to a weak pullup Using one or more I O pins of a port as special function pins will not affect the remaining port pins An extreme example is as follows P3 6 has the alternate function of WR and P3 7 of RD These strobes are used for expanded data memory access If a system used only the RD signal then P3 6 would still be available as an I O port This is not a practical suggestion but it illustrates how the special functions are independent 030308 114 of 175 High Speed Microcontroller User s Guid
104. RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset TF1 Bit 7 TR1 Bit 6 TFO Bit 5 TRO Bit4 IE1 Bit 3 Bit 2 TEO Bit 1 ITO Bit 0 Rev 030308 Timer 1 Overflow Flag This bit indicates when Timer overflows its maximum count as defined by the current mode This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine 0 No Timer 1 overflow has been detected 1 Timer 1 has overflowed its maximum count Timer 1 Run Control This bit enables disables the operation of Timer 1 0 Timer 1 is halted 1 Timer 1 is enabled Timer 0 Overflow Flag This bit indicates when Timer 0 overflows its maximum count as defined by the current mode This bit can be cleared by software and 1s automatically cleared when the CPU vectors to the Timer 0 interrupt service routine or by software 0 No Timer 0 overflow has been detected 1 Timer 0 has overflowed its maximum count Timer 0 Run Control This bit enables disables the operation of Timer 0 0 Timer 0 is halted 1 Timer 0 is enabled Interrupt 1 Edge Detect This bit is set when an edge level of the type defined by ITI is detected If IT1 1 this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine If IT1 0 this bit will inversely reflect the state of the INTI pin Interrupt 1 Type Select This bit s
105. SFR BOh P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 RD WR 1 TO INTI INTO RXDO RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset P3 7 P3 0 Bits 7 0 RD Bit 7 WR Bit 6 Bit 5 TO Bit4 INTI Bit 3 INTO Bit 2 Bit 1 RXDO Bit 0 Rev 030308 General Purpose I O Port 3 This register functions as a general purpose I O port In addition all the pins have an alternative function listed below Each of the functions is controlled by several other SFRs The associated Port 3 latch bit must contain a logic one before the pin can be used in its alternate function capacity External Data Memory Read Strobe This pin provides an active low read strobe to an external memory device External Data Memory Write Strobe This pin provides an active low write strobe to an external memory device Timer Counter External Input A 1 to 0 transition on this pin will increment Timer 1 Counter External Input A 1 10 0 transition on this pin will increment Timer 0 External Interrupt 1 A falling edge low level on this pin will cause an external interrupt 1 if enabled External Interrupt 0 A falling edge low level on this pin will cause an external interrupt 0 if enabled Serial Port 0 Transmit This pin transmits the serial port 0 data in serial port modes 1 2 3 and emits the synchronizing clock in serial port mode 0 Serial Port 0 Receive This pin receives t
106. SRAM access is denied Make sure that the battery voltage remains below the minimum 17 4 Real Time Clock Does Not Operate or Keep Accurate Time The state of the used on the DS87C530 15 undefined following a no battery reset or battery attach For the RTC to work the RTC oscillator must be enabled by setting the RTCE bit RTCC 0 The RTC is guaranteed to a minimum accuracy of 2 minutes per month over the rated temperature and voltage specifications If the time 15 found to be less accurate than this it 15 most likely due to the selection of crystal Make sure that the RTC crystal is 32 768kHz and either 12 5pF or 6pF capacitance The 12 6 bit TRIM 6 setting should correspond to the crystal in use Unlike other crystals external load capacitors should not be used with the RTC These will seriously distort the accuracy of the clock Additional information on design considerations with the RTC can be found in Application Note 79 Using the DS87C530 DS5250 Real Time Clock 171 of 175 High Speed Microcontroller User s Guide 17 5 Serial Port Does Not Work The serial port is not a complicated peripheral but there are many elements that need to be initialized The following checklist 1 provided to help in debugging 1 Have the appropriate port latch bits P3 0 P3 1 P1 2 or P1 3 been set to 1 to enable the serial port functions 2 Has the correct time base been selected 4 clocks per tick or 12 clocks per tick
107. T2 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset P1 7 P1 0 Bits 7 0 INTS Bit 7 INT4 Bit 6 INT3 Bit 5 INT2 Bit 4 TXD1 Bit 3 RXD1 Bit 2 T2EX Bit 1 T2 Bit 0 Rev 030308 General Purpose I O Port 1 This register functions as a general purpose I O port In addition all the pins have an alternative function listed below P1 2 7 contain functions that are new to the 80C32 architecture The Timer 2 functions on pins P1 1 0 are available on the 80C32 but not the 80C31 Each of the functions is controlled by several other SFRs The associated Port 1 latch bit must contain a logic one before the pin can be used in its alternate function capacity External Interrupt 5 A falling edge on this pin will cause an external interrupt 5 if enabled External Interrupt 4 A rising edge on this pin will cause an external interrupt 4 if enabled External Interrupt 3 A falling edge on this pin will cause an external interrupt 3 if enabled External Interrupt 2 A rising edge on this pin will cause an external interrupt 2 if enabled Serial Port 1 Transmit This pin transmits the serial port 1 data in serial port modes 1 2 3 and emits the synchronizing clock in serial port mode 0 Serial Port 1 Receive This pin receives the serial port 1 data in serial port modes 1 2 3 and is a bi directional data transfer pin in serial port mode 0 Timer 2 Capture Reload Trigger
108. TE statements or in a setup file Once defined these new SFRs receive the same treatment as any of the original 8051 registers This means that Maxim microcontrollers are compatible with almost every 8051 based software tool available 18 4 High Level Language Compilers Like assemblers compilers must be informed of the existence and location of the SFRs unique to Maxim microcontrollers When using C it is commonly necessary to identify the starting address for various read write segments such as XDATA and Stack In addition it is recommended that the large memory model be used in conjunction with C compilers This places the stack in off chip SRAM Microcontroller systems usually have an abundance of such SRAM compared to ROM based systems While off chip stack results in slower execution time the stack size becomes virtually unlimited 173 of 175 High Speed Microcontroller User s Guide Table 18 A Product Feature Matrix DS80C310 DS80C320 DSS0C323 0583 520 0587 520 0587 530 16kB Mask 16kB 16kB Internal Scratchpad RAM 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes Internal MOVX SRAM IKBSRAM IkB SRA M Serial Ports External Interrupts 16 Bit Timers Watchdog Timer Power Fail Precision Reset Power Fail Interrupt Data Pointers Data Pointer Decrement NV SRAM eaters 4 5V to 4 5V to 2 7V to 4 5V to 4 5V to 4 5V to iiu d 5 5V 5 5V 5 5V 5 5V 5 5V 5 5V 256byts pcm IKB SRAM
109. V that loads SBUFO or SBUFI Serial reception initiated switchbacks occur during the Cx cycle in which the falling edge was detected There are a few points that must be considered when using a serial port reception to generate a switchback Under normal circumstances noise on the line or an aborted transmission would cause the serial port to timeout and the data to be ignored This presents a problem if the switchback is used however because a switchback would occur but there is no indication to the 030308 98 of 175 High Speed Microcontroller User s Guide system that one has occurred If PMM and serial port switchback functions are used in a noisy environment the user is advised to periodically check if the device has accidentally exited PMM A similar problem can occur if multiprocessor communication protocols are used in conjunction with PMM The high speed microcontroller family supports both the use of the SM2 flag SCONO 5 or SCONI 5 and the slave address recognition registers SADDRO A9h SADDRI AAh SADENO B9h SADEN1 BAh for multiprocessor communications The problem is that an invalid address that should be ignored by a particular processor will still generate a switchback As a result it is not recommended to use a multiprocessor communication scheme in conjunction with PMM If the system power considerations will allow for an occasional erroneous switchback a polling scheme can be used to place the device back into PM
110. a Bus 0 07 When used to address expanded memory Port 0 functions as a multiplexed address data bus Port 0 must function as the address data bus on ROMIess devices Port 0 pins have extremely strong drivers that allow the bus to move 100pF loads with the timing shown in the electrical specifications Special circuit protection allows these pins to achieve the maximum slew rate without ringing eliminating excessive noise or interface problems Users that compare the high speed microcontroller family to 80C32 devices will find improved drive capability This power is available for dynamic switching only and should not be used to drive heavy DC loads such as LEDs 030308 112 of 175 High Speed Microcontroller User s Guide When used as an address bus the ADO 7 pins will provide true drive capability for both logic levels No pullups are needed In fact pullups will degrade the memory interface timing Members of the high speed microcontroller family employ a two state drive system on ADO 7 That is the pin is driven hard for a period to allow the greatest possible setup or access time Then the pin states are held in a weak latch until forced to the next state or overwritten by an external device This assures a smooth transition between logic states and also allows a longer hold time In general the data is held hold time on ADO 7 until another device overwrites the bus This latch effect is generally transparent to the user F
111. a don t care cleared to 0 in the above example a match and interrupt would occur during every subsecond of the minute in which the real time alarm minute register matched If an alarm occurs while in data retention state lt the RTCIF flag will be set and the interrupt will remain pending When power is reapplied to the device the device will execute an interrupt as soon as interrupts are enabled 14 4 Using the Day of the Week Bits The DS87C530 contains three day of the week bits DOW 2 0 located in the upper 3 bits of the real time clock hour register RTCH FDh These allow the processor to count from 1 to 7 The day of the week bits will increment anytime the hour register changes from 17h to 00h indicating a new day When the day of the week register reaches a count of 111b it will roll over to 001b If the day of the week feature is not needed writing 000b to the bits will disable the ability of an hour register rollover to change the day of the week The bits will remain at 000b This is very convenient from a software standpoint as it is not necessary to zero out the high order bits when determining the hour from the RTC hour register 14 5 Choosing an RTC Crystal The RTC clock source is provided by an external 32 768kHz crystal attached to the RTCX1 and RTCX2 leads of the 0587 530 The device be programmed to operate with a crystal rated for either a 6pF or 12 5pF load capacitance The RTC cr
112. ack the result to the latch Thus the operation takes place using the value that was originally written to the SFR without regard to the pin state The last three instructions listed above are read modify write because they read the entire port latch then write back the changed value In this case only one bit will be changed as specified by the instruction 10 9 I O Port Timing Figure 10 1 shows when port pins change in relationship to instruction timing The example shown uses a MOV command to change P1 0 from a logic 1 to a logic 0 This diagram is presented to aid the designer in determining the timing relationship for very critical designs Most designers will not need to consider this much detail Dummy NOP instructions are shown to illustrate subsequent instructions 030308 116 of 175 High Speed Microcontroller User s Guide Figure 10 3 Port Timing for MOV Instruction f Last Cycle o MOV Cycle 2 First NOP Previous Cycle amp lt amoy gt 1 4 PIE second NOP prefetch prefetc prefetch c2 cod MOV First NOP Instruction Op code MOV Operand MOV Instruction Nop Address Address Instruction Address Instruction Address Op code Operand Instruction Instruction Op code Op code 10 100ptional Functions Every port pin on the h
113. al crystal or oscillator 1 Device is operating from the ring oscillator Ring Oscillator Select This bit selects the clock source following a resume from Stop mode Using the ring oscillator to resume from Stop mode allows almost instantaneous startup This bit is cleared to 0 after a power on reset and unchanged by all other forms of reset The state of this bit will be undefined on devices that do not incorporate a ring oscillator 0 The device will hold operation until the crystal oscillator has warmed up 1 The device will begin operating from the ring oscillator and when the crystal warmup is complete will switch to the clock source indicated by the XT RG bit 33 of 175 High Speed Microcontroller User s Guide BGS Bit 0 4 2 18 SFR 96h Bandgap Select This bit enables disables the bandgap reference during Stop mode Disabling the bandgap reference provides significant power savings in Stop mode but sacrifices the ability to perform a power fail interrupt or power fail reset while stopped This bit can only be modified with a Timed Access procedure The state of this bit will be undefined on devices that do not incorporate a bandgap reference 0 The bandgap reference is disabled in Stop mode but will function during normal operation Vcc must fall below 0 4V to cause a reset when this bit is 0 1 The bandgap reference will operate in Stop mode RTC Trim Register TRIM 7
114. al interrupt 2 is a high priority interrupt Rev 030308 54 of 175 High Speed Microcontroller User s Guide 4 2 51 SFR F9h Real Time Clock Control Register RTCC 7 6 5 4 3 2 1 0 55 SCE MCE HCE RTCRE RTCWE RTCIF RTCE RW RW RW RW RW 0 RT 0 R RT R Unrestricted Read W Unrestricted Write T Timed Access Write Only n Value after Reset See Description SSCE Bit 7 SCE Bit 6 MCE Bit 5 HCE Bit4 RTCRE Bit 3 030308 RTC Subsecond Register Compare Enable This bit enables a match Bit 7 between the Real Time Alarm Subsecond Register RTASS F2h and the Real Time Clock Subsecond Register RTCSS FAh to contribute to the RTC interrupt request This bit will be indeterminate following a no battery reset and is unaffected by all other resets 0 The subsecond value is a don t care when evaluating the alarm If any other alarm register compare bits are enabled this will cause one interrupt per subsecond tick 1 256 second for as long as the other registers match 1 Include the subseconds along with any other registers when evaluating alarm compare conditions RTC Second Register Compare Enable This bit enables a match between the Real Time Alarm Second Register RTAS F3h and the Real Time Clock Second Register RTCS FBh to contribute to the RTC interrupt request This bit will be indeterminate following a no battery reset and is unaffe
115. alue after Reset SM0 SM1 SM2 Serial Port Mode These bits control the mode of serial port 0 In addition the SMO and Bits 7 6 5 SM2 0 bits have secondary functions as shown below LENGTH 8 j 0 1 Synchronous 8 te poo L X 1 J Asmhonu 10 or 2 baud rate equation 64terk SMOD 0 Asynchronous with multiprocessor 64 SMOD 0 communication 32tc LK 1 DOMMES imer 1 or 2 baud rate equation communication SMO FE 0 Framing Error Flag When SMODO PCON 6 0 this SMO is used to select the Bit 7 mode for serial port 0 When SMODO PCON 6 1 this bit FE will be set upon detection of an invalid stop bit When used as FE this bit must be cleared software Once the SMODO bit is set modifications to this bit will not affect the serial port mode settings Although accessed from the same register internally the data for bits SMO and FE are stored in different locations 5 0 No alternate function Bit 6 5 2 0 Multiple CPU Communications The function of this bit 15 dependent on the serial port Bit 5 0 mode Mode 0 Selects 12 or 4tc x period for synchronous serial port 0 data transfers Mode 1 When set reception is ignored RI 0 is not set if invalid stop bit received Mode 2 3 When this bit is set multiprocessor communications are enabled in modes 2 and 3 This will prev
116. apture mode RCAP2L is also used as the LSB of a 16 bit reload value when Timer 2 is configured in auto reload mode 11 6 3 2 Most Significant Byte Capture of Timer 2 RCAP2H 7 6 5 4 3 2 1 0 2 CBh RACP2H7 RACP2H6 RCAP2H5 RCAP2H4 RCAP2H3 RCAP2H2 RCAP2HI 2 Bits 7 to 0 Timer 2 Capture MSB RACP2H 7 0 This register is used to capture the TH2 value when Timer 2 15 configured in capture mode RCAP2H is also used as the MSB of a 16 bit reload value when Timer 2 is configured in auto reload mode 030308 125 of 175 High Speed Microcontroller User s Guide 11 7 Timer 2 Modes As is seen in the register descriptions Timer 2 has several abilities not found in Timers 0 and 1 However it does not offer the 13 bit and dual 8 bit modes thus running in 16 bit mode at all times Also note that instead of offering an 8 bit auto reload mode Timer 2 has a 16 bit auto reload mode This mode uses the Timer Capture registers to hold the reload values The modes available on Timer 2 are described below 11 7 1 16 Bit Timer Counter In this mode Timer 2 performs a simple timer or counter function where it behaves similarly to mode 1 of Timers 0 and 1 but uses 16 instead of 8 bits This mode along with the optional capture mode described below is illustrated in Figure 11 4 The 16 bit count values are found in TL2 and TH2 Special Function Registers addresses 0CCh and OCDh r
117. as the reason for a reset Software should clear the POR bit after reading it When a reset occurs software is able to determine if a power cycle was the cause In this way processing may take a different course for each of the three resets if applicable When power fails drops below the power monitor invokes the reset state again This reset condition remains while power is below the threshold When power returns above the reset threshold a full power on reset is performed A brownout that causes Vcc to drop below appears the same as a power up 8 1 2 Watchdog Timer Reset The watchdog timer is a free running timer with a programmable interval Software can clear the timer at anytime causing the interval to begin again The watchdog supervises CPU operation by requiring software to clear it before the timeout expires If the timer is enabled and software fails to clear it before this interval expires the CPU 15 placed into a reset state The reset state is maintained for two machine cycles Once the reset is removed the software resumes execution at 0000h The watchdog timer is fully described in Section 11 Software can determine that a watchdog timeout was the reason for the reset by using watchdog timer reset flag WTRF is located at WDCON 2 Hardware sets this bit to a logic 1 when the watchdog times out without being cleared by software if EWT 1 If a watchdog timer reset occurs software should clear t
118. ast significant byte of Timer 0 Bits 7 0 4 2 12 Timer 1 LSB TL1 7 6 5 4 3 2 1 0 SFR 8Bh TL1 7 TL1 6 1 5 TL1 4 TL1 3 TL1 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset TL1 7 TL 1 0 Timer 1 LSB This register contains the least significant byte of Timer 1 Bits 7 0 4 2 13 Timer 0 MSB THO 7 6 5 4 3 2 1 0 SFR 8Ch THO 7 THO 6 5 4 THO 3 2 THO 1 THO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset 0 7 0 0 Timer 0 MSB This register contains the most significant byte of Timer 0 Bits 7 0 4 2 14 Timer 1 MSB TH1 7 6 5 4 3 2 1 0 SFR 8Dh THI 7 1 6 1 5 1 4 1 3 1 2 THI 1 THI 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset 7 1 0 Timer 1 MSB This register contains the most significant byte of Timer 1 Bits 7 0 Rev 030308 30 of 175 High Speed Microcontroller User s Guide 4 2 15 Clock Control CKCON 7 6 5 4 3 2 1 0 SFR 8Eh WDI WDO T2M TIM MD2 MDI MDO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset WDI WDO Bits 7 6 T2M Bit 5 Bit4 Bit 3 Watchdog Timer Mode Select 1 0 These bits determine the watchdog timer timeout period The timer divides
119. ate Regardless of the source of the reset the state of the microcontroller is the same while in reset When in reset the oscillator is running but no program execution is allowed When the reset source is external the user must remove the reset stimulus When power is applied to the device the power on delay removes the stimulus automatically Resets do not affect the Scratchpad RAM Thus any data stored in RAM will be preserved The contents of internal MOVX data memory will also remain unaffected by a reset Note that 1f the power supply dips below approximately 2V the RAM contents may be lost The minimum voltage required for RAM data retention in not specified Since it is impossible to determine if the power was lower than 2V prior to the power on reset RAM must be assumed lost when POR is set The reset state of SFR bits are described in Section 4 Bits marked SPECIAL have conditions that can affect their reset state Consult the individual bit descriptions for more information Note that the stack pointer will also be reset The stack is effectively lost during a reset even though the RAM contents are not altered Interrupts and timers are disabled The state of the watchdog timer is dependent on the specific device in use Note that the watchdog timeout defaults to its shortest interval on any reset I O Ports are taken to a weak high state FFh This leaves each port pin configured with the data latch set to a 1 Ports do not go to the 1
120. axim maintains a presence on the Internet with its World Wide Web home page and an anonymous FTP site Data sheets are subject to revision and these services contain the most current data sheet information available The home page has access to company information data sheets application notes and product information The ftp server hosts software examples and development tool software Website www maxim ic com Microcontroller Products Home Page www maxim ic com microcontrollers Anonymous FIP Site ftp dalsemi com pub microcontroller 18 2 Development Tools Because the high speed microcontroller family was designed for maximum compatibility with existing 8051 microcontrollers users find that most of their existing 8051 tools work with our products To aid our customers Maxim maintains a list of development tool vendors on its website at www maxim ic com MicroDevTools This page is very useful when attempting to locate commonly used microcontroller aids such as compilers test clips sockets programmers programming adapters reference books emulators crystals and development boards 18 3 Software Compatibility Maxim microcontrollers execute the 8051 instruction set and are object code compatible with other 8051 based products The special features of Maxim microcontrollers are accessed via SFRs unique to our products but the devices do not use any new instructions The new SFRs can be easily defined in the user s software with EQUA
121. back to divide by 4 mode Attempts to execute illegal speed change will be ignored and the bits will remain unchanged It is the responsibility of the software to test for serial port activity before attempting to change speed as a modification of the clock divider bits during a serial port operation will corrupt the data 7 3 2 and Peripheral Functions Timers 0 1 and 2 will default on reset to a 12 clock per cycle operation to remain compatible with the original 8051 timing The timers can be individually configured to run at machine cycle timing divide by 4 by setting the relevant bits in the Clock Control Register CKCON 8Eh Because the timers derive their time base from the internal clock timers 0 1 and 2 operate at reduced clock rates during PMM This will also affect the operation of the serial ports in PMM In general it is not possible to generate standard baud rates while in PMM and the user is advised to avoid PMM or use the switchback feature if serial port operation is desired Table 7 D shows the effect of the clock divider value on timer operation 030308 97 of 175 High Speed Microcontroller User s Guide Table 7 D Effect of Clock Modes on Timer Operation osc OSC CYCLES DM OSC CYCLES PER OSC CYCLES PER CDO PER TIMER SERIAL PORT DUE 01 2 CLOCK 2 CLOCK 0 CLOCK MODE
122. baud rate The complete formula is as follows 4 x Oscillator Frequency Mode 1 3 Baud Rate 32 12 x 256 TH1 Rev 030308 141 of 175 High Speed Microcontroller User s Guide Note that the 12 in the denominator can be changed to a 4 as determined by the timer selection T1M CKCON 4 This formula provides the derived baud rate for a given and crystal Most users already know what baud rate is desired and want the timer reload value Thus the equation solves as follows when T1M 0 2 SMOD_X x Oscillator Frequency 2 32 x 12 x Baud Rate Note that the most common application is to use Timer 1 in 8 bit auto reload mode as a timer It can actually be used in any mode and can also be configured as a counter To use Timer 2 as baud rate generator for Serial Port 0 the Timer is configured in auto reload mode Then either TCLK or RCLK bit or both are set to a logic 1 TCLK 1 selects Timer 2 as the baud rate generator for the transmitter and RCLK 1 selects Timer 2 for the receiver Thus Serial Port 0 can have the transmit and receive operating at different baud rates by choosing 1 for one data direction and Timer 2 for the other Setting either RCLK or TCLK to a logic 1 selects Timer 2 for baud rate generation RCLK TCLK reside in T2CON 4 and TCON 5 respectively When using Timer 2 to generate baud rates the formula will be as follows Note that the reload value is a 16 bit number as compared
123. bering convention shown below Note that all combinations of devices are not currently available Refer to the individual data sheets for the available versions DS80C320 MCG L SPEED TEMPERATURE PACKAGE OPERATING VOLTAGE MEMORY TYPE 030308 tog KATO 18MHz 25MHz 33MHz 40MHz 0 to 70 40 to 85 C PLASTIC PLCC THIN PLASTIC QUAD FLAT PACK TQFP PLASTIC QUAD FLAT PACK QFP WINDOWED CERDIP WINDOWED CERQUAD 5V 3V OR WIDE VOLTAGE ROM EPROM 10 of 175 High Speed Microcontroller User s Guide 3 ARCHITECTURE The high speed microcontroller 1 based on the industry standard 80C52 The core is accumulator based architecture using internal registers for data storage and peripheral control It executes the standard 8051 instruction set This section provides a brief description of each architecture feature Details concerning the programming model instruction set and register description are provided in Section 4 3 1 ALU The ALU is responsible for math functions comparisons and general decision making in the high speed microcontroller The ALU is not explicitly used by software Instruction decoding prepares the ALU automatically and passes it the appropriate data The ALU primarily uses two special function registers SFRs as the source and destination for all operations These are the Accumulator and
124. cess Register TA C7h 5 Modify the ROMSIZE Select bits RMS 2 0 6 Delay 2 machine cycles 2 NOP instructions 7 Enable interrupts by setting the EA bit IE 7 If the of internal program memory setting is selected extra precautions must be taken In this case it will be necessary to duplicate the interrupt vector table in external program memory This is because the interrupt vector table is located in the lower 1 of memory and the device will automatically redirect any fetches from the interrupt vector table to external memory Care must be exercised when assembling or compiling the program so that all the modules are located at the correct starting address including the interrupt vector table 6 3 Program Memory Interconnect Figure 6 1 shows the program memory interconnect scheme for the high speed microcontroller family This example uses the 0580 320 and one 32kB x 8 EPROM The program store enable PSEN signal is used to provide an output enable to the EPROM It can also be used to provide a chip enable but this produces less favorable timing The address LSB and data are multiplexed on port 0 and the address MSB is provided on port 2 An external latch shown in the diagram as a 74F373 is used to latch the lower byte of the address to the memory device The Address Latch Enable ALE signal controls the timing of the latch so that the operation is performed in the proper sequence The signals and relative timing
125. ciated flag For edge triggered external interrupts and internal interrupt sources the interrupt flags are set automatically by hardware For level sensitive external interrupts the flags are actually under control of the external signal and the flag will rise and fall with the pin level Each interrupt flag is sampled once per machine cycle Later in the same machine cycle the samples are polled by hardware If the sample indicates a pending interrupt and the interrupt is enabled then on the next machine cycle it will be acknowledged by the hardware forcing an LCALL to the appropriate vector address This LCALL will occur unless blocked by one of the following conditions 1 An interrupt of equal or greater priority has already been invoked and the RETI instruction has not been issued to terminate it 2 The current machine cycle is not the final cycle in the execution of the current instruction 3 The instruction in progress is an RETI or a write to IP IE EIP or EIE The individual interrupt sources and associated enable and priority bits are shown in Figure 9 1 While the final selection of the appropriate interrupt vector address is referred to as a polling process this function is actually performed in a single machine cycle using combinatorial logic Rev 030308 108 of 175 High Speed Microcontroller User s Guide 9 6 Interrupt Latency Interrupt response will require a varying amount of time depending on the state of the micr
126. cific calendar date but rather a relative day count defined by the user This register can be read only when the RTCRE bit is set and can only be modified when the RTCWE bit is set Consult the description of the RTCWE bit for the programming protocol for this register The register counts from Oh to FFh No alarm corresponds to these bits 4 2 57 Real Time Clock Day Register 1 RTCD1 7 6 5 4 3 2 1 0 SFR FFh RTCD1 7 RTCD1 6 RTCDI 5 RTCD1 4 RTCDI 3 RTCD1 2 RTCD1 1 RTCD1 0 R W R w R Ww R w R Ww R Ww R Ww R Ww R Unrestricted Read W Unrestricted Write n Value after Reset See Description RTCD1 7 RTCD1 0 Real Time Clock Day Register 1 This register contains the most significant byte of Bits 7 0 the 16 bit current day count This is not an absolute value tied to a specific calendar date but rather a relative day count defined by the user This register can be read only when the RTCRE bit is set and can only be modified when the RTCWE bit is set Consult the description of the RTCWE bit for the programming protocol for this register The register counts from Oh to FFh A rollover of this register will clear RTCDI and RTCDO No alarm corresponds to these bits 4 3 Instruction Timing instructions in the high speed microcontroller perform the same functions as their 80C32 counterparts Their affect on bits flags and other status functions is identical However the timing of eac
127. controller provides two data pointers Thus software can load both a source and a destination address The MOVX instruction will use the active pointer to direct the off chip address The data pointers are called and DPTR1 is located at SFR addresses 82h and 83h These are the locations used by the original 8051 No modification of standard code is needed to use DPTRO The new DPTR is located at SFR 84h and 85h The Data Pointer Select bit SEL chooses the active pointer and is located at the LSb of the SFR location 86h No other bits in register 86h have any effect and are set to 0 When DPS is set to 0 the DPTRO is active When set to 1 DPTRI is used 030308 81 of 175 High Speed Microcontroller User s Guide The user switches between data pointers by toggling the SEL bit The INC instruction is the fastest way to accomplish this All DPTR related instructions use the currently selected DPTR for any activity Therefore only one instruction is required to switch from a source to a destination address Using the Dual Data Pointer saves code from needing to save source and destination addresses when doing a block move Once loaded the software simply switches between and DPTRI Sample code listed below illustrates the saving from using the dual DPTR The relevant register locations are summarized as follows DPL 82h Low byte original DPTR DPH 83h High byte original DPTR 84h Low byte new DPTRI
128. cted by all other resets 0 The second value is a don t care when evaluating an alarm If any other alarm register compare bits are enabled this will cause one interrupt per second as long as the other registers match 1 Include the second along with any other registers when evaluating alarm compare conditions RTC Minute Register Compare Enable This bit enables a match between Bit 5 the Real Time Alarm Minute Register RTAM F4h and the Real Time Clock Minute Register RTCM FCh to contribute to the RTC interrupt request This bit will be indeterminate following a no battery reset and is unaffected by all other resets 0 The minute value is a don t care when evaluating an alarm If any other alarm register compare bits are enabled this will cause one interrupt per minute as long as the other registers match 1 Include the minute along with any other registers when evaluating alarm compare conditions RTC Hour Register Compare Enable This bit enables a match between the Real Time Alarm Hour Register RTAH F5h and the Real Time Clock Hour Register RTCM FDh to contribute to the RTC interrupt request This bit will be indeterminate following a no battery reset and is unaffected by all other resets 0 The hour value is a don t care when evaluating an alarm If any other alarm register compare bits are enabled this will cause one interrupt per hour for as long as the other registers match 1 Include the
129. current count in TH2 TL2 0 Timer 2 is halted 1 Timer 2 is enabled Counter Timer Select This bit determines whether timer 2 will function as a timer or counter Independent of this bit timer 2 runs at 2 clocks per tick when used in either baud rate generator or clock output mode 0 Timer 2 function as a timer The speed of timer 2 is determined by the T2M bit CKCON 5 1 Timer 2 will count negative transitions on the T2 pin P1 0 Capture Reload Select This bit determines whether the capture or reload function will be used for timer 2 If either RCLK or TCLK is set this bit will not function and timer will function in an auto reload mode following each overflow 0 Auto reloads will occur when timer 2 overflows or a falling edge is detected on T2EX 1f EXEN2 1 1 Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 1 Timer 2 Mode T2MOD 7 6 5 1 0 2 DCEN RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Bits 7 2 T20E Bit 1 DCEN Bit 0 Rev 030308 Reserved Read data will be indeterminate Timer 2 Output Enable This bit enables disables the clock output function of the T2 pin P1 0 0 The T2 pin functions as either a standard port pin or as a counter input for timer 2 1 Timer 2 will drive the T2 pin with a clock output if C 2 0 Also timer 2 rollovers will not cause interrupt
130. d by a Timed Access write before the next reset of any kind or the software may erroneously determine that another power on reset has occurred This bit is set following a power on reset and unaffected by all other resets Note This bit is not Timed Access protected on the DS80C310 0 Last reset was from a source other than a power on reset 1 Last reset was a power on reset EPFI Enable Power Fail Interrupt This bit enables disables the ability of the internal Bit 5 bandgap reference to generate a power fail interrupt when falls below approximately 4 5V While in Stop mode both this bit and the Bandgap Select bit BGS EXIF 0 must be set to enable the power fail interrupt 0 Power fail interrupt disabled 1 Power fail interrupt enabled during normal operation Power fail interrupt enabled in Stop mode if BGS is set PFI Power Fail Interrupt Flag When set this bit indicates that a power fail interrupt has Bit4 occurred This bit must be cleared in software before exiting the interrupt service routine or another interrupt will be generated Setting this bit in software will generate a power fail interrupt if enabled WDIF Watchdog Interrupt Flag This bit in conjunction with the Watchdog Timer Interrupt Bit 3 Enable bit EWDI EIE 4 and Enable Watchdog Timer Reset bit WDCON 1 indicates if a watchdog timer event has occurred and what action will be taken This bit must be cleared in software before exiting the interrupt servic
131. d mode Timer 2 LSB TL2 7 6 5 4 3 2 1 0 TL2 7 TL2 6 TL2 5 TL2 4 TL2 3 TL2 2 TL2 1 TL2 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Timer 2 LSB This register contains the least significant byte of Timer 2 Timer 2 MSB TH2 7 6 5 4 3 2 1 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Timer 2 MSB This register contains the least significant byte of Timer 2 48 of 175 030308 High Speed Microcontroller User s Guide 4 2 41 SFR DOh Program Status Word PSW 7 6 5 4 3 2 1 0 F0 RSI RSO OV F1 P RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset CY Carry Flag This bit is set when if the last arithmetic operation resulted in a carry Bit 7 during addition or a borrow during subtraction Otherwise it is cleared to 0 by all arithmetic operations AC Auxiliary Carry Flag This bit is set to 1 if the last arithmetic operation resulted in a Bit 6 carry into during addition or a borrow during subtraction from the high order nibble Otherwise it is cleared to 0 by all arithmetic operations F0 User Flag 0 This is a bit addressable general purpose flag for software control Bit 5 RS1 RSO Registe
132. e A more practical application is the optional use of an interrupt If INTO P3 2 is enabled then an externally imposed logic 0 will cause an interrupt By then disabling the INTO P3 2 can be used as a general purpose I O pin This allows INTO to be used to wake up the system but does not eliminate another use of the pin 10 4 Output Functions Although 8051 I O ports appear to be true I O their output characteristics are dependent on the individual port and pin conditions When software writes a logic 0 to the port for output the port is pulled to ground When software writes a logic 1 to the port for output Ports 1 2 or 3 will drive weak pullups after the strong transition from 0 to 1 Port 0 will go three state Thus as long as the port is not heavily loaded true logic values will be output DC drive capability is provided in the electrical specifications Note that the DC current available from an port pin is a function of the permissible voltage drop Transition current is available to help move the port pin from a 0 to a 1 Since the logic 0 driver is strong no additional drive current is needed in the 1 to 0 direction The transition current is applied when the port latch is changed from a logic 0 to a logic 1 Simply writing a logic 1 where a 1 was already in place does not change the strength of the pullup This transition current is applied for one half a machine cycle The absolute current is not guaranteed but is app
133. e to address the upper RAM This value might be the result of another calculation 4 1 2 3 Stack Another use of the Scratchpad area is for the programmer s stack This area is selected using the Stack Pointer SP 81h SFR Whenever a call or interrupt is invoked the return address is placed on the Stack It also is available to the programmer for variables etc and since the Stack can be moved there is no fixed location within the RAM designated as Stack The Stack Pointer will default to 07h on reset The user can then move it as needed A convenient location would be the upper RAM area gt 7Fh since this is only available indirectly The SP will point to the last used value Therefore the next value placed on the Stack is put at SP 1 Each PUSH or CALL increments the SP by the appropriate value Each POP or RET will decrement as well Figure 4 1 Memory Map PROGRAM DATA MEMORY MEMORY 030308 15 of 175 High Speed Microcontroller User s Guide INDIRECT DIRECT RAM SFRs Figure 4 2 Register Map DIRECT RAM Figure 4 3 Scratchpad Register Addressing INDIRECT RAM DIRECT RAM 030308 16 of 175 High Speed Microcontroller User s Guide 4 2 Special Function Registers The high speed microcontroller like the 8051 uses special function registers SFRs to control peripherals and modes In many cases an SFR will control individual functions or report status on individual functions The SFRs
134. e 1 it is set after the last sample of the incoming stop bit subject to the state of SM2 1 In modes 2 and 3 RI 1 is set after the last sample of 1 It must be cleared manually by software SMO FE 0 6 0 MODE FUNCTION OST PERIOD 0 0 0 Sync 8 4 12 see SM2 0 1 1 Asynch 10 Timer 1 1 0 2 Asynch 11 64 32 1 1 3 Asynch 11 Timer 1 Initialization SCONI is set to 00h on a reset Read Write Access Unrestricted 030308 139 of 175 High Speed Microcontroller User s Guide 12 2 3 Power Control Register PCON 87h 7 Serial Port 0 Baud Rate Doubler Enable SMOD 0 Doubles the serial baud rate in modes 1 2 and 3 for Serial Port 0 the standard port when SMOD 1 PCON 6 Framing Error Detection Enable SMOD0 When SMODO is set to 1 SCONO 7 and SCON1 7 are converted to FE flag for the respective serial port When SMODO is 0 then SCONO 7 and SCON1 7 the SMO function as defined for the serial port 12 2 4 Watchdog Control Register WDCON D8h WDCON 7 Serial Modification SMOD 1 When set to logic 1 this bit doubles the baud rate of Serial Port 1 It works identically to PCON 7 12 2 5 Timer Two Control Register T2CON C8h T2CON 5 Receive Clock Flag RCLK This bit determines whether Timer 1 or 2 is used for Serial Port 0 timing of received data in Serial Modes 1 or 3 RCLK 1 causes Timer 2 overflow to be used as the receive clock R
135. e 7 A shows the state of the processor pins in Idle and Stop modes Stop mode can be exited in two ways First like the 8052 microcontrollers a non clocked interrupt such as the external interrupts or the power fail interrupt can be used Clocked interrupts such as the watchdog timer internal timers and serial ports will not operate in Stop mode Note that the bandgap reference must be enabled in order to use the power fail interrupt to exit Stop mode which will increase Stop mode current Processor operation will resume with the fetching of the interrupt vector associated with the interrupt that caused the exit from Stop mode When the interrupt service routine is complete an RETI will return the program to the instruction immediately following the one that invoked the Stop mode 030308 93 of 175 High Speed Microcontroller User s Guide A second method of exiting Stop mode is with a reset The watchdog timer reset 1s not available as a reset source because no timers are running in Stop mode An external reset via the RST pin will unconditionally exit the device from Stop mode If the BGS bit is set the device will provide a reset while in Stop mode if Vcc should drop below Vrsr level If the BGS bit is 0 then a dip in power below Vrsr will not cause a reset For example if Vcc should drop to a level of 0 5V then return to the full level no reset will be generated For this reason use of the bandgap reference is rec
136. e consists of four clocks when operating in divide by 4 mode The use of Power Management modes will cause the device to utilize 64 or 1024 external clock cycles per machine cycle Within a machine cycle there are four states called C1 C2 C3 and C4 Various operations take place during each C state Within this section and throughout others an event timing will be identified by its C state For example ALE rises at the beginning of the C1 time Since the clock source is the source of nearly all timing the electrical specifications are given in terms of clocks The time of a clock period is referred to as Most times in the electrical specifications are specified as some number of clocks from the edge of a signal The signal edges were also derived from the clock source and the C states 030308 64 of 175 High Speed Microcontroller User s Guide Due to the limited number of edges within a machine cycle selected events must occur between edges The high speed microcontroller employs sophisticated circuits to create half and quarter clock events That 1s some events occur between clock edges Such circuits assure that events occur as precisely as if a clock edge were available While being generally transparent to the user these circuits result in the use of fractional clocks in the electrical specifications For example a time can be specified as 2 5 As mentioned above a machine cycle is the basic timing unit
137. e data 15 transferred LSb first As described above the baud rates for Mode 1 are generated by either a divide by 16 of Timer 1 rollover a divide by 16 of the Timer 2 rollover or a divide by 16 of Timer 1 rollover 2 The UART begins transmission 5 oscillator cycles after the first rollover of the divide by 16 counter following a software write to SBUF Transmission takes place on the TXD pin It begins by the start bit being placed on the pin Data is then shifted out onto the pin LSb first The stop bit follows The TI bit is set two oscillator cycles after the stop bit 15 placed on the pin bits are shifted out at the rate determined by baud rate generator Once the baud rate generator is active reception can begin at any time The REN bit SCONO 4 or SCONI 4 must be set to logic 1 to allow reception The falling edge of a start bit on the RXD pin will begin the reception process Data is shifted in at the selected baud rate At the middle of the stop bit time certain conditions must be met to load SBUF with the received data 1 RI must 0 and either 2 If SM2 0 the state of the stop bit does not matter or 3 If 5 2 1 the state of the stop bit must 1 If these conditions are true then SBUF hex address 99h Clh will be loaded with the received byte the RB8 bit SCONO 2 or SCONI 2 will be loaded with the stop bit and the RI bit SCONO 0 SCON1 0 will be set If these conditions are false then the
138. e external interrupts allows greater flexibility in dealing with external events Some devices incorporate power management modes that allow the device to dynamically vary the internal clock speed from 4 clocks per cycle default to 64 or 1024 clocks per cycle Because power consumption is directly proportional to clock speed the device can reduce its operating frequency during periods of little or no activity This greatly reduces power consumption The switchback feature allows the device to quickly return in divide by 4 mode upon receipt of an interrupt or serial port activity allowing the device to respond to external events while in power management mode Various memory configurations are available with the high speed microcontroller family EPROM and Mask programmable ROM versions are available for program memory Some versions incorporate extended MOVX SRAM on chip reducing or eliminating the need for external data memory This memory can be made nonvolatile in the DS87C530 through the use of an external lithium battery Note Information contained in specific data sheets supersedes general information found in this user s guide Designers are cautioned to obtain and read carefully the data sheets this user s guide and any relevant supplements before using any Maxim microcontroller 030308 9 of 175 High Speed Microcontroller User s Guide 2 ORDERING INFORMATION The high speed microcontroller family follows the part num
139. e in the IE and IP registers respectively The watchdog interrupt usually has a different connotation than the timer interrupts Unless the watchdog is being used as a very long timer the interrupt means the software has failed to reset the counter and may be lost The ISR can attempt to determine the system state If the watchdog is not cleared the CPU will be reset in 512 clocks if EWT 1 Like other sources the watchdog timer has a flag bit an enable and a priority It also has its own vector These are summarized in Table 9 A 9 2 3 Serial Communication Interrupts Each UART is capable of generating an interrupt The UART has its own interrupt enable vector and priority The UART differs from other sources as it has two flags These are used by the ISR to determine whether the interrupt comes from a received word or a transmitted one Unlike the timers the UART flags are not altered when the interrupt is serviced Software must change them manually When a UART finishes the transmission of a word an interrupt will be generated 1f enabled Likewise the UART will generate an interrupt when a word is completely received The CPU will not be notified until the word is completely received or transmitted 9 2 4 Real Time Clock The DS87C530 real time clock RTC has the ability to assert an RTC interrupt if enabled The alarm can be programmed for a specific time once per day or can be a recurring alarm once per hour minute second
140. e make the high speed microcontroller minimize the effect of accidental code corruption Note Timed access is not optional and must be supported if the protected bits are used This example simply helps explain the category of problem that the timed access prevents 030308 154 of 175 High Speed Microcontroller User s Guide EXAMPLE A TRANSIENT CAUSES THE WATCHDOG TO BE DISABLED TABLE READ C2D2 900A 00 MOV DPTR 0A00H LOAD TABLE POINTER C2D5 79 MOV 20FFH LOAD COUNTER C2D7 7890 MOV RO 90H DESTINATION POINTER LOOP C2D9 MOVX A DPTR READ DATA BYTE C2DA F6 MOV SSTORE IT IN RAM C2DB 06 INC RO NEXT TABLE LOCATION C2DC A3 INC DPTR NEXT DATA VALUE C2DD 109 C2 09 DJNZ R1 LOOP NEXT BYTE OR DONE 2 A transient occurs while the op code is being fetched for the first instruction The transient causes one bit of the op code in the first instruction to be read as a 0 instead of 1 The resulting program is what the microcontroller would actually execute TABLE READ C2D2 800 00 SJMP OBH RELATIVE JUMP BY 10 LOCATIONS 205 79 R1 0FFH LOAD COUNTER C2D7 78 90 RO 90H DESTINATION POINTER LOOP C2D9 0 MOVX DATA BYTE C2DA F6 MOV RO A SSTORE IT IN RAM C2DB 06 INC RO NEXT TABLE LOCATION C2DC A3 INC DPTR NEXT DATA VALUE C2DD D9 C2 D9 DJNZ R1 LOOP NEXT BYTE OR DONE 2 The resulting jump is to address C2DE This is not even a real op code but
141. e off chip reference This gives access to the entire 64 data memory map An example is as follows MOVX DPTR A Write the value in the accumulator to the address referenced by the selected data pointer 4 4 4 Immediate Addressing Immediate Addressing is used when one of the operands is predetermined and coded into the software This mode is commonly used to initialize SFRs and to mask particular bits without affecting others An example is as follows ORL A 40h Logical OR the Accumulator with 40h 4 4 5 Register Indirect with Displacement Register Indirect Addressing with Displacement is used to access data in lookup tables in program memory space The location is created using a base address with an index The base address can be either the PC or the DPTR The index is the accumulator The result is stored in the accumulator An example is as follows MOVC A QA DPTR Load the accumulator with the contents of program memory pointed to by the contents of the DPTR plus the value in the accumulator 4 4 6 Relative Addressing Relative Addressing is used to determine a destination address for Conditional branch Each of these instructions includes 8 bit value that contains a two s complement address offset 127 to 128 which is added to the PC to determine the destination address This destination is branched to when the tested condition is true The PC points to the program memory location immediately following t
142. e routine or another interrupt will be generated Setting this bit in software will generate a watchdog interrupt if enabled This bit can only be modified using a timed access procedure EWT EWDI WDIF RESULT X X 0 No watchdog event has occurred 0 0 1 Watchdog timeout has expired No interrupt has been generated 0 1 1 Watchdog interrupt has occurred 1 0 1 Watchdog timeout has expired No interrupt has been generated Watchdog timer reset will occur in 512 cycles if RWT is not strobed 1 1 1 Watchdog interrupt has occurred Watchdog timer reset will occur in 512 cycles if RWT is not set using a Timed Access procedure WTRF Watchdog Timer Reset Flag When set this bit indicates that a watchdog timer reset Bit 2 has occurred It is typically interrogated to determine if watchdog timer reset caused a reset It is cleared by a power on reset but otherwise must be cleared by software before the next reset of any kind or software may erroneously determine that a watchdog timer reset has occurred Setting this bit in software will not generate a watchdog timer reset If the EWT bit 15 cleared the watchdog timer will have no effect on this bit 030308 50 of 175 High Speed Microcontroller User s Guide EWT Bit 1 RWT Bit 0 4 2 43 SFR E0h Enable Watchdog Timer Reset This bit enables disables the ability of the watchdog timer to reset the device This bit has no effect on the ability of th
143. e watchdog timer to generate a watchdog interrupt The watchdog timer mode select bits CKCON 7 6 control the timeout period of the watchdog timer Clearing this bit will disable the ability of the watchdog timer to generate a reset but have no affect on the timer itself or its ability to generate a watchdog timer interrupt This bit can only be modified using a Timed Access Procedure The default power on reset state of this bit is 0 on the devices If the device contains internal program memory the default power on reset state of EWT is determined by the Watchdog Default POR State bit WDPOR located in the System Control Byte or a mask option This bit is unaffected by all other resets 0 A timeout of the watchdog timer will not cause the device to reset 1 A timeout of the watchdog timer will cause the device to reset Reset Watchdog Timer Setting this bit will reset the watchdog timer count This bit must be set using a Timed Access procedure before the watchdog timer expires or a watchdog timer reset and or interrupt will be generated if enabled The timeout period is defined by the Watchdog Timer Mode Select bits CKCON 7 6 This bit will always be 0 when read Accumulator A or ACC 7 6 5 4 3 2 1 0 7 6 5 4 ACC 3 ACC 2 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset ACC 7 ACC 0
144. ea still provides the fastest general purpose access Within the 256 bytes of RAM there are several special purpose areas These are described as follows 4 1 2 1 Bit Addressable Locations In addition to direct register access some individual bits are also accessible These are individually addressable bits in both the RAM and SFR area In the Scratchpad RAM area registers 20h to 2Fh are bit addressable This provides 126 16 x 8 individual bits available to software A bit access 1s distinguished from a full register access by the type of instruction Addressing modes are discussed in Section 5 In the SFR area any register location ending in a 0 or 8 is bit addressable Figure 4 3shows details of the on chip RAM addressing including the locations of individual RAM bits 4 1 2 2 Working Registers As part of the lower 128 bytes of RAM there are four banks of Working Registers each The Working registers are general purpose RAM locations that can be addressed in a special way They are designated through R7 Since there are four banks the currently selected bank will be used by any instruction using RO R7 This allows software to change context by simply switching banks This is controlled via the Program Status Word register in the SFR area described below The Working Registers also allow their contents to be used for indirect addressing of the upper 128 bytes of RAM Thus an instruction can designate the value stored in RO for exampl
145. eceived it is stored in RB8 SCONO 2 or 5 1 2 The ninth bit can be a parity value by moving the P bit PSW 0 to TB8 The baud rate for Mode 2 is a function of the oscillator frequency It is either the oscillator input divided by 32 or 64 as programmed by the SMOD bit in the PCON register Mode 2 operation is identical to the standard 80C32 12 1 4 Mode 3 This mode has the same functionality as Mode 2 but generates baud rates like Mode 1 That is this mode transmits 11 bits but generates baud rates via the timers Like Mode 1 either Timer 1 or 2 can be used for Serial Port 0 and Timer 1 can be used for Serial Port 1 Mode 3 operation is identical to the standard 80C32 when Timers 1 or 2 use the default divide by 12 of the oscillator 12 2 Serial Port Initialization In order to use the UART function s the serial port must be initialized This involves selecting the mode and time base then initializing the baud rate generator if necessary Serial communication is then available Once the baud rate generator is running the UART can receive data In Mode 0 the high speed microcontroller provides the clock Serial reception is initiated by setting the RI bit to a logic 0 and REN to a logic 1 This will generate a clock on the TXD pin and shift in the 8 bits on the RXD pin In the other modes setting the REN bit to logic 1 will allow serial reception The external device must actually initiate it by sending a start bit In any mode
146. ed Read W Unrestricted Write n Value after Reset See description CDI 0 Bits 7 6 o 0 Clock Divide Control 1 0 These bits select the number of crystal oscillator clocks required to generate one machine cycle Switching between modes requires a transition through the divide by 4 mode CD1 CDO 01 For example to go from 64 to 1024 clocks per cycle the device must first go from 64 to 4 clocks per cycle and then from 4 to 1024 clocks per cycle Attempts to perform an invalid transition will be ignored The setting of these bits will affect the timers and serial ports as shown below OSC CYCLESPER OSCCYCLESPER OSC CYCLES PER OSC CYCLES PER TIMER 2 CLK SERIAL PORT TIMER 2 SERIAL PORT CLK BAUD RATE GEN _CLK MODE0 BAUD RATE GEN MODE 2 RESERVED 0 1 4 2 4 2 2 2 4 64 32 1 4 me 64 32 3 194 104 52 SWB Bit 5 Bit4 XTOFF Bit 3 ALEOFF Bit 2 030308 Switchback Enable This bit allows an enabled external interrupt or serial port activity to force the Clock Divide Control bits to the divide by 4 state 01 Upon internal acknowledgement of an external interrupt the device will switch modes at the start of the jump to the interrupt service routine Note that this means that an external interrupt must actually be recognized 1 be enabled and not masked by higher priority interrupts for the switchback to occur For serial port rec
147. ed below When set to a logic 0 the serial port runs at a divide by 12 When set to a logic 1 the serial port runs at a divide by 4 With the exception of the additional new divide by 4 of the oscillator supported by SM2 Mode 0 operation is identical to the 80C32 12 1 2 Mode 1 This mode provides standard full duplex asynchronous communication A total of 10 bits is transmitted including 1 start bit 8 data bits and 1 stop bit The received stop bit 1 stored bit location 8 in the relevant SCON register In Mode 1 the baud rate is a function of timer overflow This makes the baud rate programmable by the user Mode 1 has a difference for the two UARTS Serial Port 0 can use either Timer 1 or 2 to generate baud rates Serial Port 1 can use only Timer 1 Note that if both serial ports use the same timer they will be running at the same baud rate If they use different timers or different modes they can run at different rates Baud rates are discussed in more detail below Mode 1 operation is identical to the standard 80C32 when Timers 1 or 2 use the default divide by 12 of the oscillator 030308 136 of 175 High Speed Microcontroller User s Guide 12 1 3 Mode 2 This mode is an asynchronous mode that transmits a total of 11 bits These include 1 start bit 8 data bits a programmable ninth bit and 1 stop bit The ninth bit is determined by the value in TB8 SCONO 3 or SCON1 3 for transmission When the ninth bit is r
148. ed in ROM or EPROM Data memory is read write and is commonly implemented in SRAM Memory areas can be implemented either on chip off chip or by using a combination When using devices without internal program memory or if the maximum address of on chip program or data memory is exceeded the device will perform an external memory access using the Expanded memory bus on ports 0 and 2 While serving as a memory bus port 0 and port 2 do not function as I O ports following the standard 8051 convention of addressing external memory The PSEN signal goes active low to serve as a chip enable or output enable when performing a code fetch from external memory Products with no on chip program memory such as the DS80C320 always use the expanded bus These devices have no Port 0 latch since the port is dedicated for memory operations Devices that incorporate on chip MOVX data memory operate in a similar fashion except that the RD and WR signals serve as chip enables when accessing an external SRAM Program execution begins at the reset vector address 0000h Any reset causes the next program fetch to begin at this location Subsequent branches and interrupts determine how the memory fetch deviates from sequential addressing Since all programs begin at 0000h this is the beginning address of all program execution If on chip program memory is present program execution begins at internal location 0000h otherwise external program memory is used 6 1 In
149. ed in each The registers are SADDRO or SADDRI hex address A9h or AAh and SADENO or SADENI hex address B9h or BAh The SADDR register specifies the individual processor s address The SADEN identifies address bits that should be ignored in matching addresses Software will write an 8 bit address to the SADDR register This is the microcontroller s individual address Any bit in SADEN that contains logic 0 will cause the corresponding bit in SADDR to be ignored in comparison Thus logic 0 bits in SADEN create don t care bit states for address comparisons When an address is received each address bit that is not masked by a don t care will be compared to the SADDR The microcontroller will interrupt on any address that matches this comparison Any address that meets this comparison is called a given address The following example shows how one address can be directed to an individual processor or two out of three Micro 1 SADDR 11110000 SADEN 11111010 Given 11110x0x Micro 2 SADDR 11110001 SADEN 11111001 Given 11110 1 Micro 3 SADDR 11110010 SADEN 11111010 Given 11110 1 Note that an address of 11110000 reaches only microcontroller 1 An address of 11110001 reaches microcontroller 1 and microcontroller 2 An address of 11110010 reaches only microcontroller 3 The microcontroller also matches on any address that corresponds to the broadcast address This is the logical OR of the SADDR and SADEN registers
150. ed microcontrollers have three ways of entering a reset state power on power fail reset watchdog timer reset and external reset 8 1 1 Power On Fail Reset Members of the high speed microcontroller family incorporate an internal voltage reference that holds the CPU in the power on reset state while Vcc is out of tolerance Once rises above the threshold the microcontroller restarts the oscillation of the external crystal and count 65 536 clock cycles The processor will then begin software execution at location 0000h The voltage at which the reset state is entered depends on the specific device If the device does not contain a precision voltage reference the power on reset threshold may be anywhere between 0 8V and If the device incorporates a precision voltage reference the threshold will be as specified by the Vnsr parameter in the data sheet This helps the system maintain reliable operation by only permitting processor operation when voltage is in a know good state The processor will exit the reset condition automatically once the above conditions are met This happens automatically needing no external components or action Execution begins at the standard reset vector address of 0000h Software can determine that a power on reset has occurred using the power on reset flag POR It is located at WDCON 6 Since all resets cause a vector to location 0000h the POR flag allows software to acknowledge that power failure w
151. ed timing and drive strengths If either port SFR is accessed the port pins will revert to the characteristics described above This includes a strong pulldown a strong pullup for transitions and a weak pullup for static conditions versions of the high speed microcontroller dedicate Port 0 and 2 as the memory interface bus The Port 0 latch does not exist on ROMless devices The functions of these ports are described in more detail in the specific sections 10 1 Port 0 10 1 1 General Purpose Devices that have internal program memory have the ability to use Port 0 as a general purpose I O Data written to the port latch serves to set both level and direction of the data on the pin ROMless devices do not contain a Port 0 latch because at no time can it be manipulated as a port When used as an I O port it functions as an open drain output More detail on the functions of these pins is provided under the description of output and input functions in this section Even if internal memory is present the use of Port 0 as general purpose I O pins is not recommended if the device will be used to access external memory This is because the state of the pins will be disturbed during the memory access In addition the pullups needed to maintain a high state during the use as general purpose I O will interfere with the complementary drivers employed when the device operates as an expanded memory bus 10 1 2 Multiplexed Address Dat
152. elects whether the pin will detect edge or level triggered interrupts 0 INTI is level triggered 1 INTI is edge triggered Interrupt 0 Edge Detect This bit is set when an edge level of the type defined by ITO is detected If ITO 1 this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine If ITO 0 this bit will inversely reflect the state of the INTO pin Interrupt 0 Type Select This bit selects whether the INTO pin will detect edge or level triggered interrupts 0 INTO is level triggered 1 INTO is edge triggered 28 of 175 High Speed Microcontroller User s Guide 4 2 10 SFR 89h Timer Mode Control TMOD 7 6 5 4 3 2 1 0 C T MI 0 C T MI RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset GATE Bit 7 C T Bit 6 1 0 Bits 5 4 GATE Bit 3 C T Bit 2 M1 MO Bits 1 0 Rev 030308 Timer 1 Gate Control This bit enable disables the ability of Timer 1 to increment 0 Timer 1 will clock when TRI 1 regardless of the state of INT1 1 Timer 1 will clock only when 1 1 and INTI 1 Timer 1 Counter Timer Select 0 Timer 1 is incremented by internal clocks Timer 1 is incremented by pulses on when TR1 TCON 6 is 1 Timer 1 Mode Select These bits select the operating mode of Timer 1
153. elow for operation of the ring oscillator EXIF 1 Ring Oscillator Select RGSL When set to a 1 by software the high speed microcontroller will use a ring oscillator to come out of Stop mode without waiting for crystal startup This allows an instantaneous startup when coming out of Stop mode It is useful if software needs to perform a short task then return to Stop It is also useful 1f software must respond quickly to an external event After the crystal has performed 65 536 cycles hardware will switch to the crystal as its clock source The RGMD status bit reports on this changeover When RGSL is set to a 0 the high speed microcontroller will delay software execution until after the 65 536 clock crystal startup time RGSL 15 only cleared by a power on reset and is not altered by other forms of reset EXIF 0 Bandgap Select BGS Setting this bit to a 1 will allow the use of the bandgap voltage reference while in Stop mode Since this function uses as much as 50mA the bandgap 15 optional in Stop mode Setting this bit to a 0 will turn off the bandgap while in Stop mode When BGS 0 no power fail interrupt or power fail reset will be available in Stop mode PCON 1 Stop Mode Select STOP When this bit is set the program stops execution clocks are stopped and the CPU enters power down mode PCON 0 Idle Mode Select IDLE Program execution halts leaving timers serial ports and clocks running 030308 92 of 175 High Speed
154. ent the RI 0 bit from being set and an interrupt being asserted 1 the 9th bit received is not 1 REN 0 Receiver Enable This bit enable disables the serial port 0 receiver shift register Bira 0 Serial port 0 reception disabled 1 Serial port 0 receiver enabled modes 1 2 3 Initiate synchronous reception mode 0 8_0 9th Transmission Bit State This bit defines the state of the 9th transmission bit in Bit3 serial port 0 modes 2 and 3 8 0 9th Received Bit State This bit identifies that state of the 9th reception bit of received Bit 2 data in serial port 0 modes 2 and 3 In serial port mode 1 when SM2 0 0 8 0 15 the state of the stop bit 0 is not used in mode 0 030308 35 of 175 High Speed Microcontroller User s Guide TI 0 Transmitter Interrupt Flag This bit indicates that data in the serial port 0 buffer has Bit 1 been completely shifted out In serial port mode 0 TI_0 is set at the end of the 8th data bit In all other modes this bit is set at the end of the last data bit This bit must be manually cleared by software 0 Receiver Interrupt Flag This bit indicates that a byte of data has been received in the Bit 0 serial port 0 buffer In serial port mode 0 RI 0 is set at the end of the 8th bit In serial port mode 1 RI 015 set after the last sample of the incoming stop bit subject to the state of SM2 0 In modes 2 and 3 RI 015 set after the last sample
155. eption the switch occurs at the start of the instructions following the falling edge of the start bit Reserved When modifying the PMR register software must write a 0 to this bit Read data will be indeterminate Crystal Oscillator Disable This bit disables the CPU crystal oscillator It can only be set to 1 while running the ring oscillator XT RG 0 Clearing this bit restarts the crystal amplifier reset the crystal warmup counter and after 65 536 external crystal cycles the XTUP bit will be set 0 Crystal oscillator is enabled 1 Crystal oscillator is disabled ALE Disable This bit disables the expression of the ALE signal on the device pin during all on board program and data memory accesses External memory accesses will automatically enable ALE independent of ALEOFF 0 ALE expression is enabled 1 ALE expression is disabled 43 of 175 High Speed Microcontroller User s Guide DMEI DMEO Bits 1 0 DMEI ES 1 Data Memory Enable 1 0 These bits determine the functional relationship of the first 1024 bytes of data memory Three memory configurations are supported to allow either external data memory access through the expanded multiplexed address data bus of Ports 0 and Port 2 internal SRAM data memory access or read only access to programming information Note these bits are cleared after a reset so access to the internal SRAM is prohibited until these bits are modified DATA MEMORY DMEO0 A
156. er fail interrupt This is subject to its individual enable only The EA bit has no effect on the power fail interrupt 9 2 Interrupt Sources Various combinations of interrupt sources are available on different members of the high speed microcontroller family These are broken into several categories external timer based serial communication real time clock and power monitor Each type is described below Interrupt sources are sampled once per machine cycle If the source goes active after the sample it will not be registered until the next cycle 9 2 1 External Interrupts The high speed microcontroller has six external interrupt sources These include the standard 2 interrupts of the 8051 architecture and four new sources The original interrupts are INTO and INT1 These are active low but can be programmed to be edge or level sensitive Bits ITO and IT1 control the detection mode respectively When ITx 0 the interrupt is triggered by a logic 0 on the appropriate interrupt pin The interrupt condition remains in force as long as the pin is low When ITx 1 the interrupt is pseudo edge triggered This means that if on successive samples the pin is high then low the interrupt is activated Since the external interrupts are sampled the pin driver of an edge triggered interrupt should hold both the high condition then the low condition for at least one machine cycles each to ensure detection This means maximum sampling frequency
157. ernal MOVC instruction on internal program memory is disabled and access to internal MOVX data from external program is prohibited other program execution and data memory access allowed Device must be fully erased before EPROM can be programmed again Verification disabled external program execution prohibited Device must be fully erased before 1 1 1 programmed again 030308 44 of 175 High Speed Microcontroller User s Guide 4 2 33 SFR C5h Status Register STATUS 7 6 5 4 3 2 1 0 LIP XTUP SPTA1 SPRA1 SPTAO SPRAO R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Unrestricted Read W Unrestricted Write n Value after Reset See description PIP Bit 7 HIP Bit 6 LIP Bit 5 XTUP Bit4 5 1 SPRAI Bit 2 SPTAO Bit 1 SPRAO Bit 0 Rev 030308 Power Fail Priority Interrupt Status When set this bit indicates that software is currently servicing a power fail interrupt It is cleared when the program executes the corresponding RETI instruction This bit is indeterminate on devices that do not incorporate the power fail interrupt High Priority Interrupt Status When set this bit indicates that software is currently servicing a high priority interrupt It is cleared when the program executes the corresponding RETI instruction Low Priority Interrupt Status When set this bit indicates that software is currentl
158. esent on the DS80C320 XTUP STATUS 4 1 Oscillator warmup complete 1 None 0 Oscillator warmup still in progress crystal not available 7 3 5 Using the Ring Oscillator The ring oscillator is an internal 2MHz 4MHz clock source used to quickly exit Stop mode and resume operation without waiting for an external clock source to stabilize Some devices feature the additional capability of using the ring oscillator as the primary clock source during normal operation once the device has performed an initial power on reset using an external clock source Because the ring oscillator lacks the stability of a piezoelectric generated clock source high precision timing operations should be avoided while running from the ring oscillator This includes using the timers for pulse measurement and the use of the serial ports in asynchronous modes Serial ports operating in mode 0 are unaffected by the stability of the clock source because this mode utilizes a synchronizing clock XT RG 0 If the ring oscillator select RGSL EXIF 1 is set the device will resume operation immediately using the internal ring oscillator as the clock source The device will continue to run from the ring oscillator until the crystal warmup period of 65 536 clock cycles measured from the external source has completed At this time the device will switch to the clock source active before it entered Stop mode and continue operation This allows s
159. espectively The selection of whether a Timer or Counter function is performed is made using the bit C T2 T2CON 1 When C T2 1 set to a logic 1 Timer 2 behaves as a counter where it counts 1 to 0 transitions at the T2 P1 0 pin When 2 is set to a logic 0 Timer 2 functions as a timer where it counts the oscillator cycles divided by either 12 or 4 as determined by bit T2M T2CON 5 Timing or counting is enabled by setting bit TR2 T2CON 2 to 1 and disabled by setting it to 0 When the counter rolls over from FFFFh to 0000h the TF2 flag 2 7 is set and will cause an interrupt if Timer 2 s interrupt is enabled 11 7 2 16 Bit Timer with Capture A diagram of Timer 2 s Capture Mode is shown in Figure 11 4 In this mode the timer performs basically the same 16 bit timer counter function described above However a 1 to 0 transition on T2EX pin P1 1 causes the value in Timer 2 to be transferred into the capture registers if enabled by EXEN2 T2CON 3 The capture registers RCAP2L and RCAP2H correspond to TL2 and TH2 respectively The capture function is enabled by the CP RL2 T2CON 0 bit When set to logic 1 the timer is in capture mode as described When set to logic 0 the timer is in auto reload mode described later As was possible with Timers 0 and 1 the time base for Timer 2 can be selected to be oscillator cycles divided by either 12 or 4 when in this mode Figure 11 4 Timer Counter 2 with Optional Capture OS
160. flag each time the timer completes the selected timer interval as programmed WD1 CKCON 7 and WDO 030308 132 of 175 High Speed Microcontroller User s Guide CKCON 6 Restarting the timer using the RWT WDCON 0 bit allows software to use the timer in a polled timeout mode The WDIF bit is cleared by software or any reset The watchdog interrupt is also available for applications that do not need a true watchdog reset but simply a very long timer The interrupt is enabled using the enable watchdog timer interrupt EWDI EIE 4 bit When the timeout occurs the watchdog timer will set the WDIF bit WDCON 3 and an interrupt will occur if the global interrupt enable EA IE 7 is set Note that WDIF 15 set 512 clocks before a potential watchdog reset The watchdog interrupt flag will indicate the source of the interrupt and must be cleared by software Using the watchdog interrupt during software development can allow the user to select ideal watchdog reset locations Code 15 first developed without enabling the watchdog interrupt or reset functions Once the program is complete the watchdog Interrupt function 1s enabled to identify the required locations in code to set RWT WDCON 0 bit Incrementally adding instructions to reset the watchdog timer prior to each address location identified by the watchdog interrupt will allow the code to eventually run without receiving a watchdog interrupt At this point the watchdog ti
161. flow occurs the value in RCAP2L and RCAP2H will load into T2L and T2H In the down count direction an underflow occurs when T2L and T2H match the values in RCAP2L and RCAP2H respectively When an underflow occurs FFFFh is loaded into T2L and T2H and counting continues Note that in this mode the overflow underflow output of the timer is provided to an edge detection circuit as well as to the TF2 bit T2CON 7 This edge detection circuit toggles the EXF2 bit T2CON 6 on every overflow or underflow Therefore the EXF2 bit behaves as a 17th bit of the counter and may be used as such 11 7 5 Baud Rate Generator Timer 2 can be used to generate baud rates for Serial Port 0 in serial modes 1 or 3 Baud rate generator mode is invoked by setting either the RCLK or TCLK bit in the T2CON register to a logic 1 as illustrated in Figure 11 6 In this mode the timer continues to function in auto reload mode but instead of setting the interrupt flag T2F T2CON 7 and potentially causing an interrupt the overflow generates the shift clock for the serial port function As in normal auto reload mode an overflow causes RCAP2L and RCAP2H to be transferred into T2L and T2H respectively Note that when RCLK or TCLK is set to 1 the Timer 2 is forced into 16 bit auto reload mode regardless of the CP RL2 bit As explained above the timer itself cannot set the T2F interrupt flag and therefore cannot generate an interrupt However if EXEN2 T2CON 3 is set to
162. g timer will have no effect on this bit WDCON 1 Enable Watchdog Timer Reset EWT Setting this bit will turn on the watchdog timer reset function The interrupt will not occur unless the EWDI bit in the EIE register is set A reset will occur according to the WD1 and WDO bits in the CKCON register Setting this bit to a 0 will disable the reset but leave the timer running WDCON 0 Reset Watchdog Timer RWT This bit serves as the strobe for the watchdog function During the timeout period software must set the RWT bit if the watchdog is enabled Failing to set the RWT will cause a reset when the timeout has elapsed There is no need to set the RWT bit to a 0 because it is self clearing Read Write Access All bits have unrestricted read access POR EWT WDIF and RWT require a timed access write The remaining bits have unrestricted write access 030308 134 of 175 High Speed Microcontroller User s Guide 11 9 2 Clock Control Register CKCON Summary CKCON 7 Watchdog Timer Mode Select Bit 1 WD1 See table below for operation CKCON 6 Watchdog Timer Mode Select Bit 0 See table below for operation The WD select bits determine the timeout period of the watchdog timer The timer divides the crystal frequency by a programmable value as shown below The divider value is expressed in number of clock crystal cycles Note that the reset timeout is 512 clocks longer than the interrupt regardless of whether the interrupt
163. ged dynamically Each timer has 4 primary modes as discussed below The watchdog timer reset provides CPU monitoring by requiring software to clear the timer before the user selected interval expires If the timer is not cleared the watchdog resets the CPU The watchdog function is optional and is described below Since the high speed microcontroller timers have a variety of features the following summary table shows the capabilities TIMER 0 TIMER 1 TIMER 2 13 Bit Timer Counter 13 Bit Timer Counter 16 Bit Timer Counter 16 Bit Timer Counter 16 Bit Timer Counter 16 Bit Timer With Capture 8 Bit Timer with Auto 8 Bit Timer with Auto Reload 16 Bit Auto Reload Timer Counter Reload External Control Pulse Timer Counter 16 Bit Up Down Auto Reload Two 8 Bit Timer Counters Timer Counter Baud Rate Generator Baud Rate Generator Timer Output Clock Generator External Control Pulse Timer Counter 11 1 16 Bit Timers Timers 0 and 1 are nearly identical Timer 2 has several additional features such as up down counting capture values and an optional output pin that make it unique Timers 0 and 1 are described first Timer 2 is described separately As mentioned above the time base for each timer can be varied and this 1 also discussed in more detail below Timer 0 and Timer 1 have four operating modes They are 13 bit timer counter 16 bit timer counter 8 bit timer counter with auto reload and two 8 bit time
164. gh speed microcontroller family offers a combination of features and peripherals as shown in Table 18 A This user s guide is designed as a comprehensive guide covering all features available in the high speed microcontroller family The designer should investigate the specific data sheet to determine which features are available on a particular device Detailed information about newer members of the product family may be provided in separate documents until they can be assimilated into the High Speed Microcontroller User s Guide 030308 13 of 175 High Speed Microcontroller User s Guide 4 PROGRAMMING MODEL This section provides a programmer s overview of the high speed microcontroller core It includes information on the memory map on chip RAM SFRs and instruction set The programming model of the high speed microcontroller is very similar to that of the industry standard 80C52 The memory map is identical It uses the same instruction set though instruction timing is improved Several new SFRs have been added 41 Memory Organization The high speed microcontroller like the 8052 uses several distant memory areas These are registers program memory and data memory Registers serve to control on chip peripherals and as RAM Note that registers on chip are separate from data memory Registers are divided into three categories including directly addressed on chip RAM indirectly addressed on chip RAM and SFRs The program
165. gnal Enable m RTC Crystal Write Timed Access 08 MO Capacitance Select TRIM 5 TRM2 0 TRIM 3 RTC Trim Bit 2 0 Uichanged TRIM I Write Timed Access The RTC control and status registers can be subdivided into four groups RTC time registers RTCSS FAh RTCS FBh RTCM FCh RTCH FDh RTCDO FEh RTCD1 FFh RTC alarm registers RTASS F2h RTAS F3h RTAM F4h RTAH F5h RTC calibration TRIM 96h and RTC control RTCC F9h 030308 156 of 175 High Speed Microcontroller User s Guide 14 1 Starting and Stopping the RTC Setting the RTC enable bit RTCE RTCC 0 to 1 enables RTC operation This starts the RTC crystal amplifier and begins clocking the RTC Like all crystal oscillators the RTC crystal oscillator has a crystal warmup period Software should allow a minimum of 1 second between setting the RTCE bit to 1 and initializing the time This allows the clock to be guaranteed stable when timekeeping begins Although it may be desired to program the RTC time registers and then start the oscillator this sequence is not recommended because of the delay incurred by the RTC crystal warmup period There are two situations where the RTC will be started The first is the case where the RTC has been intentionally halted following normal operation When the RTCE bit is set the time registers will continue their count from the last setting when the clock was stopped The RTC time value will be
166. h instruction is different This applies both in absolute terms of nanoseconds for a given crystal and in relative terms of clocks For absolute timing of real time events the timing of software loops will need to be calculated using the data provided in Section 16 Instruction Set Details However timers default to run at the older 12 clocks per timer increment and timer based events need no modification The relative time of two instructions might be different in the new architecture than it was previously For example both the one byte two cycle MOVX A DPTR instruction and the three byte two cycle direct direct instruction used two cycles In the high speed microcontroller the MOVX instruction uses two cycles but the MOV direct direct uses three cycles While both are faster than their original counterparts they now have different execution times from each other because the high speed microcontroller typically uses one cycle for each byte This is generally true for all instructions except for MUL DIV MOVC MOVX and branch type instructions The timing of each instruction should be examined for familiarity with the changes Note that a machine cycle now requires just four clocks and provides one ALE pulse per cycle Many instructions require only one cycle but some require five In the original architecture all were one or two cycles except for MUL and 030308 58 of 175 High Speed Microcontroller User s
167. hat affect each flag 4 5 1 Bit Descriptions PSW 7 Carry CY Set when the previous operation resulted in a carry during addition or a borrow during subtraction otherwise cleared PSW 6 Auxiliary Carry AC Set when the previous operation resulted in a carry during addition or a borrow during subtraction from the high order nibble Otherwise cleared PSW 2 Overflow OV Set when a carry was generated into the high order bit but not a carry out of the high order bit OV is normally used with two s complement arithmetic PSW 0 Parity P Set to logic 1 to indicate an odd number of ones in the accumulator odd parity Cleared for an even number of ones This produces even parity these bits are cleared to a logic 0 for all resets Table 4 Instructions That Affect Flag Settings INSTRUCTION INSTRUCTION E CY OV AC CY OV AC ADD X X X CLRC 0 ADDC X X X CPLC X SUBB X X X ANLC bit X MUL 0 X ANL C bit X DIV 0 X ORL C bit X DA X ORL C bit X RRC X MOV C bit X RLC X CJNE X SETB C 1 Note X indicates the modification is according to the result of the instruction 030308 62 of 175 High Speed Microcontroller User s Guide 5 CPU TIMING The timing of the high speed microcontroller is the area with the greatest departure from the original 8051 series This section will briefly explain the timing and also compare it to the o
168. he Working Register specified in the instruction Thus one instruction can be used to reach many values by altering the contents of the designated Working Register Note that in general only RO and be used as pointers An example of Register Indirect Addressing is as follows ANL RO Logical AND the Accumulator with the contents of the register pointed to by the value stored in This mode is also used for Stack manipulation This is because all Stack references are directed by the value in the Stack Pointer register The Push and Pop instructions use this method of addressing An example is as follows PUSH A Saves the contents of the accumulator on the stack Register Indirect Addressing is used for all off chip data memory accesses These involve the MOVX instruction The pointer registers can be RO and DPTRI Both and reside in the Working Register area of the Scratchpad RAM They can be used to reference a 256 byte area of off chip data memory When using this type of addressing the upper address byte is supplied by the value in the Port 2 latch This value must be selected by software prior to the MOVX instruction An example is as follows MOVX RO A Write the value in the accumulator to the address pointed to by in the page pointed to by P2 Rev 030308 60 of 175 High Speed Microcontroller User s Guide The 16 bit Data pointers DPTRs can be used as an absolut
169. he branch instruction when the offset is added If the tested condition is not true the next instruction 1 performed An example is as follows 92 5 20 Branch to the location 2 20 if the contents of the accumulator 0 4 4 7 Page Addressing Page Addressing is used by the Branching instructions to specify a destination address within the same 2kB block as the next contiguous instruction The full 16 bit address is calculated by taking the five highest order bits for the next instruction 2 and concatenating them with the lowest order 11 bit field contained in the current instruction An example is as follows 0870h ACALL100h Call to the subroutine at address 100h plus the current page address In this example the current page address is 800h so the destination address 15 900h 030308 61 of 175 High Speed Microcontroller User s Guide 4 4 8 Extended Addressing Extended Addressing is used by the Branching instructions to specify a 16 bit destination address within the 64kB address space The destination address is fixed in software as an absolute value An example is as follows LJMP 0F732h Jump to address 0F732h 4 5 Program Status Flags program status flags are contained in the program status word at SFR location DOh It contains flags that reflect the status of the CPU and the result of selected operations The flags are summarized below The following bit descriptions show the instructions t
170. he changing of the Data Memory Enable bits Table 6 A Data Memory Access Control DME0 DATA MEMORY ADDRESS RANGE DATA MEMORY LOCATION 0 0 0000h FFFFh External Data Memory default 0 0000h 03FFh Internal Data Memory 0400h FFFFh External Data Memory 1 0 Reserved Reserved 0000h 03FFh Internal Data Memory 1 1 0400h FFFBh Reserved FFFCh System Control Byte Read only FFFDh FFFFh Reserved 6 2 1 ROMSIZE Feature Members of the high speed microcontroller family that incorporate internal program memory allow the system to dynamically vary the on chip memory size This permits the device to reconfigure the upper limit of on chip memory allowing a portion of the memory to be mapped off chip The size of on chip memory can vary from to the full range of memory allowing the device to behave like a device with less on chip memory This feature has two primary uses In the first instance it allows the device to act as a bootstrap loader for a flash memory or nonvolatile SRAM NV SRAM The internal program memory can contain a bootstrap loader which can program the external memory device Secondly this method can be used to increase the amount of available program memory from 64kB to 80kB without bank switching The maximum amount of on chip memory is selected by configuring the ROM Size Select register bits RMS2 RMSI 50 ROMSIZE 2 0 The modification of the ROMSIZE register mu
171. he location where the stack will begin The stack pointer is incremented before every PUSH operation This register defaults to 07h after reset 25 of 175 High Speed Microcontroller User s Guide 4 2 3 Data Pointer Low 0 DPL SFR 82h 7 6 5 4 3 2 1 0 DPL 7 DPL 6 DPL 5 DPL 4 DPL 3 DPL 2 DPL 1 DPL 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset DPL 7 DPL 0 Data Pointer Low 0 This register is the low byte of the standard 80C32 16 bit data Bits 7 0 4 2 4 Data Pointer High 0 DPH pointer DPL and DPH are used to point to non scratchpad data RAM 7 6 5 4 3 2 1 0 SFR 83h DPH 7 DPH 6 DPH 5 DPH 4 DPH 3 DPH 2 DPH 1 DPH 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset DPH 7 DPH 0 Bits 7 0 4 2 5 Data Pointer Low 1 DPL1 Data Pointer High 0 This register is the high byte of the standard 80C32 16 bit data pointer DPL and DPH are used to point to non scratchpad data RAM 7 6 5 4 3 2 1 0 SFR 84h DPL1 7 DPL1 6 DPLI 5 DPL1 4 DPL1 3 DPL1 2 DPLI 1 DL1H 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset DPL1 7 DPL1 0 Bits 7 0 Data Pointer Low 1 This register is the low byte of the auxiliary 16 bit data pointer When the SEL bit DPS
172. he serial port 0 data in serial port modes 1 2 3 and is a bidirectional data transfer pin in serial port mode 0 38 of 175 High Speed Microcontroller User s Guide 4 2 26 Interrupt Priority IP 7 6 5 4 3 2 1 0 SFR B8h PSI PT2 50 PXI PTO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset Bit 7 Reserved Read data 15 indeterminate PS1 Serial Port 1 Interrupt This bit controls the priority of the serial port interrupt Bit 6 0 Serial port 1 priority is determined by the natural priority order 1 Serial port 1 is a high priority interrupt PT2 Timer 2 Interrupt This bit controls the priority of Timer 2 interrupt Bit 5 0 Timer 2 is determined by the natural priority order Timer 2 is a high priority interrupt 50 Serial Port 0 Interrupt This bit controls the priority of the serial port 0 interrupt Bit4 0 Serial port 0 priority is determined by the natural priority order 1 Serial port 0 is a high priority interrupt Timer 1 Interrupt This bit controls the priority of Timer 1 interrupt Bit 3 0 Timer 1 is determined by the natural priority order Timer 1 is a high priority interrupt 1 External Interrupt 1 This bit controls the priority of external interrupt 1 Bit 2 0 External interrupt 1 is determined by the natural priority order External interrupt 1 is a high
173. his flag manually This allows software to detect the event if it occurs again 030308 102 of 175 High Speed Microcontroller User s Guide 8 1 3 External Reset If the RST input is taken to a logic 1 the CPU is forced into a reset state This does not occur instantaneously as the condition must be detected and then clocked into the microcontroller It requires a minimum of two machine cycles to detect and invoke the reset state Thus the reset is a synchronous operation and the crystal must be running to cause an external reset Once the reset state is invoked it is maintained as long as RST 1 When the RST is removed the CPU will exit the reset state within two machine cycles and begin execution at address 0000h AII registers default to their power on reset state There is no flag to indicate that an external reset was applied However since the other two sources have associated flags the RST pin is the default source when neither POR nor is set If a RST is applied while the processor is in the Stop mode the scenario changes slightly As mentioned above the reset is synchronous and requires a clock to be running Since the Stop mode stops all clocks the RST will first cause the oscillator to begin running and force the program counter to 0000h Rather than a two machine cycle delay as described above the processor applies the full power on delay 65 536 clocks to allow the oscillator to stabilize 8 2 Reset St
174. his register first followed within 3 cycles by writing 55h Timed access protected bits can then be modified for a period of 3 cycles measured from the writing of the 55h 4 2 35 Timer 2 Control T2CON 7 6 5 4 3 2 1 0 SFR C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset TF2 Bit 7 EXF2 Bit 6 Timer 2 Overflow Flag This flag will be set when Timer 2 overflows from FFFFh to 0000h or the count equal to the capture register in down count mode It must be cleared by software TF2 will only be set if RCLK and TCLK are both cleared to 0 Timer 2 External Flag A negative transition on the T2EX pin 1 1 or timer 2 underflow overflow will cause this flag to set based on the CP RL2 T2CON 0 EXEN2 T2CON 3 2 0 bits If set by a negative transition this flag must be cleared to 0 by software Setting this bit in software or detection of a negative transition on the T2EX pin will force a timer interrupt if enabled N DCEN RESULT Negative transitions on P1 1 will not affect this bit Negative transitions on P1 1 will set this bit Negative transitions on P1 1 will not affect this bit Negative transitions on P1 1 will set this bit Bit toggles whenever timer 2 underflows overflows and can be used as 17th bit of resolution In this mode EXF2 w
175. hour along with any other registers when evaluating alarm compare conditions RTC Read Enable This bit temporarily halts internal updating of the RTC to allow software to read the current time No loss of time will occur This bit will be cleared to 0 following any reset Attempts to set the RTCRE and RTCWE bits simultaneously will be ignored When this bit 15 cleared software must wait 4 machine cycles before setting either the RTCRE or RTCWE bit again 0 Reads of the RTC clock registers RTCSS FAh RTCS FBh RTCM FCh RTCH FDh RTCDO0 FEh RTCDI FFh are prohibited and will return erroneous values 55 of 175 High Speed Microcontroller User s Guide 1 Reads of the clock registers are permitted during a 1 ms window starting from the time the bit is set Immediately after setting this bit software must wait 4 machine cycles to allow all time registers to synchronize The user should clear this bit when the desired reads are complete although it will clear automatically within 1 95ms if not cleared in software RTCWE RTC Write Enable This bit temporarily halts the RTC to allow software to update the Bit 2 current time No loss of time will occur This bit can only be modified using a Timed Access procedure Changing this bit from 1 to 0 will reset the RTCSS register to 00h This bit will be cleared to 0 following any reset 0 Writes to RTC clock registers RTCSS FAh RTCS FBh RTCM FCh RTCH FDh RTCDO0 FEh RTCDI F
176. igh speed microcontroller has an optional special function These functions are individually selectable They can also be turned on and off dynamically to suit the application The optional function for each port pin is described briefly below More information about each optional function is available in the section dealing with that function or in the appropriate data sheet P0 0 ADO 0 Multiplexed Address data bus P1 0 T2 Timer 2 output pulse P2 0 A8 MSB Address bus P3 0 RXDO Serial Receive UARTO P0 1 ADO 1 Multiplexed Address data bus P1 1 T2EX Timer 2 capture reload input P2 1 A9 MSB Address bus P3 1 TXDO Serial Transmit UARTO 0 2 AD0J2 Multiplexed Address data bus 1 2 RXDI Serial Receive UARTI P2 2 10 MSB Address bus P3 2 INTO External Interrupt 0 active low 0 3 ADO0 3 Multiplexed Address data bus P1 3 TXDI Serial Transmit UARTI P2 3 A11 MSB Address bus P3 3 INT1 External Interrupt 1 active low P0 4 ADO0 4 Multiplexed Address data bus 1 4 INT2 External Interrupt 2 rising edge active P2 4 12 MSB Address bus P3 4 TO Timer 0 input 0 5 ADO 5 Multiplexed Address data bus P1 5 INT3 External Int 3 falling edge active P2 5 A13 MSB Address bus P3 5 T1 Timer 1 input P0 6 ADO0 6 Multiplexed Address data bus P1 6 External Interrupt 4 rising edge active P2 6 14 MSB Address bus P3 6 WR Write strobe 0 7 0 7 Multiplexed Address data bus P1 7 5 External Int 5 falling edge active P2 7 15 MSB Address bus 3
177. igure 10 1 Port 0 Functional Circuitry EXTERNAL ADDRESS ADDRESS DATA CONTROL INTERNAL DATA BUS LATCH PIN ENABLE 10 2 Port 2 10 2 1 General Purpose I O Devices that have internal program memory have the ability to use Port 2 for a general purpose I O Data written to the port latch serves to set both level and direction of the data on the pin When used as an I O port it has complementary outputs that will drive both high and low logic levels More detail on the functions of these pins is provided under the description of output and input functions in this section Even if internal memory is present the use of Port 2 as general purpose I O pins is not recommended if the device will be used to access external memory This is because the state of the pins will be disturbed during the memory access It is still possible however to use the Port 2 latch to hold the upper address byte for Register Indirect Addressing instructions Rev 030308 113 of 175 High Speed Microcontroller User s Guide 10 2 2 Most Significant Address Byte 8 15 When used to address expanded memory Port 2 functions as the most significant byte of the address bus Port 2 must function as the address bus on ROMless devices When serving as a bus Port 2 will be driven with strong drivers at all times except immediately after the rising edge of PSEN Figure 5 3 and Figure 5 4 Figure 10 2 Port 2 Functional Circuitry ADDRESS ADDRESS A8 A15 CONT
178. ility with the 8051 yet perform the same operations in fewer clock cycles Consequently more throughput is possible for the same crystal speed As an alternative the high speed microcontroller s more efficient design allows a much slower crystal speed to get the same results as an original 8051 using much less power The fundamental innovation of the high speed microcontroller is the use of only four clocks per instruction cycle compared with 12 for the original 8051 This results in up to three times improvement in performance In addition the high speed microcontroller is updated with several new peripherals and features while providing all of the standard features of an 80C32 These include 256 bytes of on chip RAM for variables and stack 32 I O ports three 16 bit timer counters and an on chip UART In addition to improved efficiency most devices can operate at a maximum clock rate of 33MHz or 40MHz Combined with the three times performance this allows for a maximum performance equivalent to a 99MHz or 120MHz 8051 This level of computing power is comparable to many 16 bit processors but without the added expense A number of peripherals were added to the original 80C32 core Some devices have a programmable watchdog timer to supervise the system It counts up to a user programmable interval and then reset the CPU unless cleared by software Other features such as a second full function UART and dual data pointers are available to minimiz
179. ill not cause an interrupt RCLK Bit 5 TCLK Bit4 030308 Receive Clock Flag This bit determines the serial port 0 time base when receiving data in serial modes 1 or 3 0 Timer 1 overflow is used to determine receiver baud rate for serial port 0 1 Timer 2 overflow is used to determine receiver baud rate for serial port 0 Setting this bit will force timer 2 into baud rate generation mode The timer will operate from a divide by 2 of the external clock Transmit Clock Flag This bit determines the serial port 0 time base when transmitting data in serial modes 1 or 3 0 Timer 1 overflow is used to determine transmitter baud rate for serial port 0 Timer 2 overflow is used to determine transmitter baud rate for serial port 0 Setting this bit will force timer 2 into baud rate generation mode The timer will operate from a divide by 2 of the external clock 46 of 175 High Speed Microcontroller User s Guide EXEN2 Bit 3 TR2 Bit 2 C T2 Bit 1 CP RL2 Bit 0 4 2 36 SFR C9h Timer 2 External Enable This bit enables the capture reload function on the 2 pin if Timer 2 is not generating baud rates for the serial port 0 Timer 2 will ignore all external events at 2 1 Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin Timer 2 Run Control This bit enables disables the operation of timer 2 Halting this timer will preserve the
180. illator cycles 12 or oscillator cycles 4 as selected by bits TnM n 0 or 1 of the CKCON register This feature is described in more detail below Mode 0 operates identically when Timer 1 is used The same information applies to TL1 and which form the 13 bit register TCON 6 INTI P3 3 P3 5 and the relevant C T TMOD 6 and GATE TMOD 7 bits have the same functions 030308 120 of 175 High Speed Microcontroller User s Guide 11 3 Mode 1 Mode 1 configures the timer for 16 bit operation as either a timer or counter Figure 11 1 shows that bits MI 0 and MO 1 of the TMOD register select this operating mode For Timer n all of the TLn and THn registers are used For example if Timer 1 is configured in mode 1 then TL1 holds the LSB and holds the MSB Rollover occurs when the timer reaches transitions from FFFFh to 0000h An interrupt will also occur if enabled and the relevant TFn flag is set Time base selection counter timer selection and the gate function operate as described in mode 0 Figure 11 1 Timer Counter 0 and 1 Modes 0 and 1 TOM CKCON 3 4 C T TMOD 2 OSC INPUT TO TIMER C T TMOD 6 CLK MODE TIMER INPUT DIVIDE BY 4 OSC 1 1 5 16 2 5 256 00 MODEO P3 4 M1 M0 TMOD 1 T1 P3 5 TMOD 0 TRO TCON 4 1 MO TMOD gt 5 TR1 6 TMOD 4 GATE TMOD 3 GATE TMOD 7 INTO P3 2
181. illator frequency This bit is set to 1 after a no battery reset and unchanged by all other forms of reset RTC Trim Bit 1 This bit controls the relative adjustment of the RTC internal capacitance It 15 used to calibrate the oscillator frequency This bit is set to 0 after no battery reset and unchanged by all other forms of reset RTC Inverted Trim Bit 1 This bit must always be set to the complement of the TRMI bit Incorrectly writing this bit will default bits TRIM 7 5 0 to their no battery reset value This bit is cleared to 1 after a no battery reset and unchanged by all other forms of reset RTC Trim Bit 0 This bit controls the relative adjustment of the RTC internal capacitance It is used to calibrate the oscillator frequency This bit is set to 0 after a no battery reset and unchanged by all other forms of reset RTC Inverted Trim Bit 0 This bit must always be set to the complement of the TRMO bit Incorrectly writing this bit will default bits TRIM 7 5 0 to their no battery reset value This bit is cleared to 1 after a no battery reset and unchanged by all other forms of reset 34 of 175 High Speed Microcontroller User s Guide 4 2 19 Serial Port 0 Control SCONO 7 6 5 4 3 2 1 0 SFR98h SMO FE 0 SMIO SM20 RENO 80 80 TI 0 RI 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n V
182. illator is stabilizing Once 65 536 clock cycles have been detected the CPU will automatically switch to the normal oscillator as its clock source Some 030308 94 of 175 High Speed Microcontroller User s Guide devices incorporate the option of continuing to run from the ring oscillator following Stop mode even after the 65 536 clock cycle period However if the required interrupt response is very short the software can re enter Stop mode before the crystal is even stable In this case Stop mode can be invoked and both oscillators will be stopped 7 2 3 1 Speed Reduction The high speed microcontroller is a fully CMOS 8051 compatible microcontroller It can use significantly less power than other 8051 versions because it is more efficient As an average software will run 2 5 times faster on the high speed microcontroller than on other 8051 derivatives The same job can be accomplished by slowing down the crystal by a factor of 2 5 For example an existing 8051 design that runs at 12 2 can run at approximately 4 8MHz on the high speed microcontroller At this reduced speed the high speed microcontroller will have lower power consumption than an 8051 yet perform the same job Using the 2 5x factor Table 7 B shows the approximate speed at which the high speed microcontroller can accomplish the same work as an 8051 The exact improvement will vary depending on the actual instruction mix Available crystal speeds must also be con
183. ills so aaa A EE EAEE 97 CIC irse A EE 98 gg MEE nM 99 UT Oo E RDI 0000 TN 100 SWiiching Between Clock SOM COS A 101 8 102 c ud et ec 102 8 1 1 tan cO IP Mp 102 EP MEM ee oT UT T TUUM 102 103 ET EU MM MEI ee 103 2220 NO BAERY REGET 103 Bo DISABLE MODE 104 9 105 9 1 ig Ste gt ONERE W oL rt eti 105 92 106 9 2 1 ENINA NOT EEE S EAE A Aa 106 E E EE 107 EAE A AA 107 fioa TNO S 107 107 H3 SIMEULATEDINTERBUBTE 108 INTERRUPT PRIORITIES 108 8n eo cata ed lette bene 108 ms INTERRUPT LATEN 109 9 7 INTERRUPT REGISTER CONFLICTS 2 212 10 026 0 nennen rennen 111 ous uum MOON DONNE BD qu du 112 10 1 dae didt DE dd ee ds 112 u
184. in is pulled weakly to a logic 1 This 1 state is easily overcome by external components Thus after software writes a 1 to the port pin the port is configured for input When the port is read by software the state of the pin will be read The only exception is the read modify write instructions described below If the external circuit is driving a logic 1 then the pin will be a logic 1 If the external circuit is driving a 0 then it will overcome the internal pullup The pin will be the same as the driven logic state Note that the port latch is not 030308 115 of 175 High Speed Microcontroller User s Guide altered by a read operation Therefore if a logic 0 is driven onto a port pin from an external source then removed the pin will revert to the weak pullup as determined by the internal latch 10 7 Read Modify Write Instructions The normal read instructions will read the pin state without regard to the output data latch The only exception 15 the read modify write category of instructions They are listed as follows 10 8 Instruction Description ANL Logical AND ORL Logical OR XRL Logical Exclusive OR XOR JBC Branch if bit set then clear bit CPL Complement bit INC Increment DEC Decrement DJNZ Decrement and branch if not zero MOV PX n C Move the carry bit to bit n of port X CLR PX n Clear bit n of port X SETB PX n Set bit n of port X The read modify write instructions read the state of the latch then write b
185. inaccurate although the settings of the RTC alarm registers and the RTCC register will remain intact The second case is following the application of battery power Most of the registers associated with the RTC are nonvolatile so that they will maintain their state while Vcc is removed When battery power is applied to the device however the battery backed registers and bits associated with the RTC will be in an indeterminate state and will need to be reinitialized This includes the RTC interrupt flag RTCIF RTCC 1 which should be cleared before setting the RTC interrupt enable bit EIE 5 Clearing the bit to 0 halts the This will immediately halt the and will freeze all the time registers at their current value and preserve all the RTC settings If RTC functions are not desired this can be used to reduce the power consumption of the device while in battery backed mode 14 2 Setting and Reading the RTC Time Registers Access to the RTC time registers RTCSS RTCS RTCM RTCH RTCDO and RTCD1 is enabled by the RTCRE RTCC 3 and RTCWE RTCC 2 bits Both user software and the internal clock directly write and read the RTC time To prevent the possibility of both user software and the internal timer accessing the same register simultaneously the DS87C530 incorporates a register locking mechanism Updates to the RTC time registers by the internal timer are temporarily suspended for up to 1 95ms during software read or wr
186. ique timing occurs for the second memory operation when data is accessed As described in Section 5 the high speed microcontroller uses four oscillator clocks for each machine cycle A machine cycle involves one memory access Generally an instruction using two memory accesses would be a two machine cycle instruction except for branches MUL DIV INC DPTR MOVC and MOVX The MOVX instruction is unique in that the user determines the time allowed for a data memory access This feature 1 called the Stretch MOVX instruction The high speed microcontroller allows the application software to adjust the speed of data memory access The microcontroller is capable of performing the MOVX in as little as two machine cycles Since one machine cycle is used for the program fetch this leaves one machine cycle to perform the actual data memory access However this value can be adjusted as needed so that both fast memory and slow memory or peripherals can be accessed with no glue logic Even in high speed systems it may not be necessary to perform data memory access at full speed In addition there are a variety of slower memory mapped peripherals such as LCD displays or UARTS When using a MOVX instruction the user controls the time for which a read or write strobe is kept active Setup and hold times are also adjusted The Stretch value will be selected to provide a long enough memory strobe to satisfy the access time of the target device The Stretch M
187. ister O GAT QU ssrdsn aaan Enna E aA aE EEE ANERER 58 4257 RealTime Clock Day Register T uiuis aE 58 23 US NT 58 ADDRESSING 59 4 4 1 AGIOS d ser USURIS AEAN 59 mter 60 448 60 ZG 61 249 Register Indirect with DIS DIQCENIGIN aient aaaea XR RDIA NM LR E RAM 61 2 Relative oo S4 9 X 61 o oo coco emm 61 e aae E EEE ELEA EAEE RESA 62 TIU FLN 62 BELESA PONE 0m 62 5 URS Tl cm O EE IOONI E I O OOE OEE EE T 63 Ea a TN 63 ron PPM 63 ug scc 63 QSCLLATOR CHARACTERISTICS O ES 63 MEE EN SELECTO gt 63 50 Mg cem 64 5 6 1 E A E 65 WOL o O ONS aa EE 65 S E E E TII EEUU 67 SOA 68 DES TO IO adi i 68 DOMPMAMBON TO THE ATE S TERE 71 Rev 030308 3 of 175 High Speed Microcontroller User s Guide 6 MEMORY e 76 6 1 INTERNAL PROGRAM MEMORY
188. ite operations If a subsecond timer tick should occur during the 1 95ms window it will be processed immediately as soon as either the RTCWE or RTCRE bit is cleared Because the subsecond timer tick interval 15 3 906ms the 1 95ms window allows sufficient time to complete any operations and process suspended timer ticks before the next timer tick occurs In this way no timer ticks can be lost and accessing the time registers will not affect the accuracy of the RTC To allow any pending timer ticks to propagate through the RTC circuitry software must wait 4 machine cycles after setting the RTCWE or RTCRE bits before accessing any of the RTC time registers The first timer tick following the clearing of the RTCWE bit will be approximately 1 95ms following timer ticks will be 3 90625ms Reading the current time from any or all of the RTC time registers is accomplished by the following procedure 1 Disable all interrupts by clearing the EA bit IE 7 2 Setthe RTCRE bit RTCC 3 3 Wait 4 machine cycles 4 Read the appropriate register s within 1ms of RTCRE being set 5 Clear the RTCRE bit RTCC 3 6 Enable interrupts by setting the EA bit IE 7 030308 157 of 175 High Speed Microcontroller User s Guide Writing to the clock registers sets the time on the DS87C530 The second minute hour day of the week and day count can be set by writing to the respective registers It is not possible to set the subsecond RTC
189. ition To modify the MOVX timing the Stretch value in the Clock Control register described below must be changed Figure 6 6 shows the timing for a four cycle MOVX Stretch 2 Table 6 C shows the resulting strobe widths for each Stretch value The memory stretch is implemented using the clock control SFR at SFR location 8Eh The stretch value is selected using bits CKCON 2 0 In the table these bits are referred to as M2 through 0 Note that the Stretch time can be dynamically 030308 84 of 175 High Speed Microcontroller User s Guide varied allowing fast RAM s but slow peripherals The first stretch allows the use of common 120ns or 150ns RAMs without dramatically lengthening the memory access Note that the first Stretch value does not follow the pattern of adding four clocks to the strobe This is because the first Stretch uses one clock to create additional setup and one clock to create additional hold time Systems using a Stretch cycle of Zero are presumed to be fast enough or to be running at a slower clock speed Since the Stretch is based on crystal timing the resulting pulse widths must be viewed on the basis of the real system timing Table 6 C Data Memory Cycle Stretch Values 2 0 MEMORY CYCLES RD OR WR STROBE WIDTH 2 M0 IN CLOCK tat25MHz ns tat 12MHz ns 0 0 0 2 2 80 167 0 0 1 3 default 4 160 333 0 1 0 4 8 320 667 0 1 1 5 12 480 1000 1 0 0 6 16 640
190. ity of a match between the two registers to cause an alarm is controlled by the RTC Minute Register Compare Enable bit RTCC 5 This register should only be loaded with values from 0 to 3Bh 0 to 59 minutes The contents of this register will be indeterminate following a no battery reset except bits 7 6 and unchanged by all other forms of reset 4 2 49 Real Time Alarm Hour Register RTAH 7 6 5 4 3 2 1 0 SFR F5h 0 0 0 4 RTAH2 RTAH O R 0 R 0 R 0 RW RW RW RW RW R Unrestricted Read W Unrestricted Write n Value after Reset See Description Bits 7 6 5 4 0 4 0 030308 Reserved These bits will be 0 when read Real Time Alarm Hour These bits represent the hour alarm which will be compared against the RTC Hour register RTCH FDh The ability of a match between the two registers to cause an alarm is controlled by the RTC Hour Register Compare Enable bit RTCC 4 This register should only be loaded with values from 0 to 17h 0 to 23 hours The day of week bits DOW2 0 located in RTCH 7 5 do not have a corresponding alarm feature The contents of this register will be indeterminate following a no battery reset except bits 7 6 5 and unchanged by all other forms of reset 53 of 175 High Speed Microcontroller User s Guide 4 2 50 Extended Interrupt Priority EIP 7 6 5 4 3 2 1 0 SFR F8h PRTCI
191. iuos DP Ed 112 10 1 2 Multiplexed Bus 112 030308 4 of 175 High Speed Microcontroller User s Guide 10 2 d rp oc CUTE 113 178 10 2 2 Most Signiticant Address Byla t d ie de En EE LRL FEE Ea 114 10 3 PORTS P ETE 114 PUNCTI B Tii IIa LG TRE 115 10 5 CURRENT LIMITED TRANSIMONS 202 cedet encor rc Re 115 10 6 CUE EH ___ 115 10 7 READ MODIFY WRITE INSTRUCTIONS 0 0 1 1 116 10 8 INSTRUCTION 252022 116 159 FORT S dA EAR EL oni 116 IGU ga ONIS dio 3 53 117 11 PROGRAMMABLE TIMENS REY ERE 118 11 1 BIT TIMERS 118 111 1 TimerMode Register TMOD Sur alty Lese cient ee sie le 119 1112 TimerGounter Control Register POON eikonal 120 11 2 MODE KV EE HER CREER UR KHU EDGE CEU Nanaia nies 120 11 3 PT 121 crore PT net 122 11 5 KODE c
192. ks to strobe the watchdog prior to a reset Software or any reset can clear this flag WDCON 2 Watchdog Timer Reset Flag WTRF Hardware will set this bit when the watchdog timer causes a reset Software can read it but must clear it manually A power fail reset will also clear the bit This bit assists software in determining the cause of a reset If EWT 0 the watchdog timer will have no affect on this bit WDCON 1 Enable Watchdog Timer Reset EWT Setting this bit will turn on the watchdog timer reset function The interrupt will not occur unless the EWDI bit in the EIE register is set A reset will occur according to the WD1 and WDO bits in the CKCON register Setting this bit to a 0 will disable the reset but leave the timer running WDCON 0 Reset Watchdog Timer RWT This bit serves as the strobe for the watchdog function During the timeout period software must set the RWT bit if the watchdog is enabled Failing to set the RWT will cause a reset when the timeout has elapsed There is no need to set the RWT bit to a 0 because it is self clearing EIE 4 Enable Watchdog Interrupt EWDI Setting this bit in software enables the watchdog interrupt 030308 91 of 175 High Speed Microcontroller User s Guide EXIF 2 Ring Oscillator Mode RGMD Hardware will set this status bit to a 1 when the clock source is the ring oscillator Hardware will set this status bit to a 0 when the crystal is the clock source Refer to RGSL b
193. l incorporate the new priority and enable values from the previous instruction If this situation occurs it will lengthen the interrupt latency by the length of the instruction that modified the register 030308 111 of 175 High Speed Microcontroller User s Guide 10 PARALLEL I O The high speed microcontroller method of implementing I O ports follows the standard 8051 convention This provides backward compatibility with existing designs All drive capabilities exceed or equal the original 80C32 and voltage levels are compatible The transitions between strong and weak drives are similar but not identical Differences are to accommodate higher speed timing and the associated demands on slew rates As with any new technology the high speed microcontroller should be evaluated in a system to see how subtle differences affect operation From a software perspective each port appears as SFR with a unique address Each port register is addressable as a byte or 8 individual bit locations The CPU distinguishes between a bit access and a byte access by the instruction type Except for the special cases mentioned below the register and port pins have identical states Reading or writing a port is the same as reading or writing the SFR for that port The microcontroller will distinguish between port and bus operations automatically If a memory fetch is decoded and requires external memory Port 0 and 2 will be driven as a bus with the associat
194. le 6 BOMSIZE Register GI dE RR MOTOR RR 78 Table 6 C Data Memory Cycle Stretch enne nnnm 85 Table 7 A Pin States in Power Saving Modes narii 94 Table 95 Table 7 Power Management and Status Bit 2 42000 8 96 Table 7 0 Effect of Clock Modes on Timer Operation o Eno dir tek acti 98 Table 7 E Clock Control and Status 2 lt 100 Table 8 A No Battery Reset PERRO om 104 AL 105 Toe OY ccc 137 Table 14 A Real Time Clock Control and Status Bit Summary 156 Table 15 A Suggested Batteries for the 05870530 161 Table 15 B Battery Backed SFRS ks IRR RR 162 Table Feature cog dmm 174 Rev 030308 8 of 175 High Speed Microcontroller User s Guide 1 INTRODUCTION Maxim high speed microcontrollers are 8051 compatible devices that provide improved performance and power consumption compared to the original version They retain instruction set and object code compatib
195. ledge is delayed software may clear the flag and thereby prevent the interrupt from occurring One exception is the real time clock interrupt flag RTCIF which cannot be set in software 9 4 Interrupt Priorities The high speed microcontroller has three interrupt priority levels highest high and low The power fail interrupt is the only source that has highest priority and this level is fixed The remaining sources are individually programmable to either high or low Low priority is the default A low priority interrupt can be interrupted by a high or highest priority interrupt A high priority interrupt can only be interrupted by the power fail interrupt When an interrupt occurs and is serviced its priority determines if its ISR can be interrupted No interrupt source of equal or lesser priority can interrupt another source That is an incoming interrupt must be of a higher priority than the one currently being serviced to have priority If two interrupt sources of equal priority levels are requested simultaneously the natural priority is used to arbitrate The natural priority is given in Table 9 A Note that natural priority is only used to resolve simultaneous requests Once an interrupt of a given priority is invoked only a source that is programmed with a higher priority can intercede 9 5 Interrupt Acknowledge Cycle The process of acknowledging an interrupt requires multiple machine cycles that begin with the setting of the asso
196. les multiprocessor communication in Modes 2 or 3 If the ninth bit is 0 the RI 1 will not be set In Mode 1 setting the 5 2 1 bit to a one causes the RI 1 bit not to be set if a valid stop bit is not received In the high speed microcontroller SM2 1 also has a new function In mode 0 the SM2 1 bit controls whether the serial port clock runs at a divide by 4 or a divide by 12 of the oscillator when not in PMM When set to logic 0 the serial port runs at a divide by 12 When set to logic 1 the serial port runs at a divide by 4 This results in much faster synchronous serial communication SCON1 4 Receive Enable REN 1 When set to 1 the receive shift register will be enabled SCON1 3 9th Transmission Bit State 8 1 Set clear to define the state of the ninth transmission data bit in modes 2 and 3 SCON1 2 9th Received Bit State 8 1 Indicates the state of an incoming ninth bit when in modes 2 3 In mode 1 when SM2 0 8 is the state of the stop bit received 8 is not used in mode 0 SCONI 1 Transmitter Interrupt Flag TI 1 Flag that indicates the transmitted word has been completely shifted out In mode 0 TI is set at the end of the eighth data bit In all other modes this bit 1s set at the end of the last data bit It must be cleared manually by software SCON1 0 Receiver Interrupt Flag RI 1 Flag that indicates serial word has been received In mode 0 RI 1 15 set at the end of the eighth bit In mod
197. llustrated in Figure 12 3 The 11 bits consist of one start bit a logic 0 8 data bits a programmable 9th bit and one stop bit a logic 1 Like Mode 1 the transmissions occur on the TXD signal pin and receptions on RXD For transmission purposes the 9th bit can be stuffed as logic 0 or 1 A common use is to put the parity bit in this location The 9th bit is transferred from the 8 bit position in the SCON register SCONO 3 or SCONI 3 during the write to SBUF Baud rates are generated as a fixed function of the crystal frequency as described above Like Mode 1 Mode 2 s transmission begins 5 oscillator cycles after the first rollover of the divide by 16 counter following a software write to SBUF It begins by the start bit being placed on the TXD pin The data is then shifted out onto the pin LSb first followed by the 9th bit and finally the stop bit The TI bit SCONO 1 or SCONI 1 is set when the stop bit is placed on the pin 030308 147 of 175 High Speed Microcontroller User s Guide Figure 12 3 Serial Port Mode 2 OSC 2 CRYSTAL 2 DIVIDE 2 0 SMOD 0 PCON 7 OR SMOD 1 Q LDSBUF WDCON 7 RDSBUF DIVIDE BY 16 T1 TRANSMIT SHIFT REGISTER P3 1 TXD LATCH PIN 8 SCONx 3 DATA BUS Lo LOAD SHIFT SBUF SERIAL READ SERIAL i RD RECEIVE DATA BUFFER WR BUFFER CLOCK LOAD RESET RB8 SCONx 2 R1 SERIAL CONTROI FLAG FLAG SCONx 1 SCONx 0 TR
198. ltiple MCU Communication SM2 0 Setting this bit to 1 enables multiprocessor communication in Modes 2 or 3 If the ninth bit is 0 the RI 0 will not be set In Mode 1 setting the 5 2 0 bit to one causes the RI 0 bit not to be set if a valid stop bit is not received the high speed microcontroller SM2 0 also has a new function In mode 0 the SM2 0 bit controls whether the serial port clock runs at a divide by 4 or a divide by 12 of the oscillator when not in PMM When set to a logic 0 the serial port runs at a divide by 12 When set to a logic one the serial port runs at a divide by 4 This results in much faster synchronous serial communication SCONO 4 Receiver Enable REN 0 When set to a 1 the receive shift register will be enabled SCONO 3 9th Transmission Bit State 8 0 Set clear to define the state of the ninth transmission data bit in modes 2 and 3 SCONO 2 9th Received Bit State RB8 0 Indicates the state of an incoming ninth bit when in modes 2 and 3 In mode 1 when SM2 0 8 0 is the state of the stop bit received RB8 0 is not used in mode 0 SCONO 1 Transmitter Interrupt Flag TI 0 Flag that indicates the transmitted word has been completely shifted out In mode 0 TI 0 is set at the end of the eighth data bit In all other modes this bit is set at the end of the last data bit It must be cleared manually by software SCONO 0 Receiver Interrupt Flag RI 0 Flag that indicates serial word has bee
199. ly MUL and divide DIV These are shown below Figure 5 7 shows the timing of five cycle instructions MUL A B A4h DIV B 84h Note that the five cycle instructions require only 1 byte They need 5 cycles to accomplish the math function 030308 68 of 175 High Speed Microcontroller User s Guide Figure 5 5 Three Cycle Instruction Timing Example 1 ANL direct data INSTRUCTION FETCH SINGLE CYCLE C1 les RETURN DATA 53h ADDRESS A15 A8 Example 2 SJMP rel INSTRUCTION FETCH SINGLE CYCLE E ci does lea Example 3 INC DPTR A3h INSTRUCTION FETCH SINGLE CYCLE 7 des Ica 53h a7 a0 47 40 RETURN DATA OPER ADDRESS A15 A8 80h a7 a0 OPERAND FETCH OPERAND FETCH OPERAND FETCH SINGLE CYCLE SINGLE CYCLE 2 Ica RETURN DATA IMMEDIATE 07 00 ADDRESS 15 8 DUMMY FETCH SINGLE CYCLE e SINGLE CYCLE gt Ics Ios lc Ica RETURN DATA OPER AND ADDR7 0 ADDRESS 15 DUMMY FETCH RETURN DATA DUMMY ADDRESS A15 A8 DUMMY FETCH SINGLE CYCLE ai SINGLE CYCLE gt Ics les les lea Shaded areas are held in a weak latch on the port until overdriven Rev 030308 ADDRESS 15 69 of 175 High Speed Microcontroller User s Guide Figure 5 6 Four Cycle Instruction Timing Example 1 CJNE A data addr B4h 97 40 7 0
200. machine cycles of writing AAh This opens a three machine cycle window after the write of 55h during which any timed access protected bits may be modified Failure to complete any of the required steps will also require the procedure to begin again starting with the write of AAh to the timed access register Attempts to modify timed access protected bits after the window has closed will be ignored This is regardless of 030308 153 of 175 High Speed Microcontroller User s Guide whether any bits were modified Figure 13 1 illustrates a number of examples of correct and incorrect use of the timed access procedure Figure 13 1 Timed Access Examples three machine cycles three machine cycles three machine cycles MOV 0C7h 0AAh MOV 0C7h 558 SETB EWT three machine cycles three machine cycles one machine cycle two machine cycles MOV 0C7h 0AAh MOV 0C7h 55h NOP SETB EWT three machine cycles three machine cycles three machine cycles MOV 0C7h 0AAh MOV OC7h 55h MOV WDCON 021 VALID TIMED ACCESS PROCEDURES three machine cycles one machine cycles three machine cycle two machine cycles MOV 0C7h 0AAh NOP MOV 0 7 55H SETB EWT Second write to TA register does not occur within 3 cycles of first write three machine cycles three machine cycles one machine cycle three machine cycles MOV 0C7h 0AAh MOV 0 7 55H NOP MOV WDCON 02h Modification of protected bit did not occur with cycles of
201. may be a short period of time before reset when the device is operating but could read erroneous data from the RTC or SRAM or fail to write to them One solution would be to use the power fail interrupt to halt reads or writes to the or SRAM when is dropping The best approach is to carefully select battery voltages to avoid the problem entirely 15 1 Selecting a Battery There are a number of battery chemistries and brands that are suitable for use with battery backed members of the high speed microcontroller family The use of lithium chemistry batteries such as Lithium Manganese Dioxide is preferred as their nominal voltage is approximately 3 0V Coin cells are particularly suited for use with the high speed microcontroller family because of their capacity low profile and small diameter Many are available with PC mount tabs attached for automated assembly Table 15 A shows a list of some common batteries and their capacities This list is by no means exhaustive and the inclusion or exclusion of any vendor from this list is in no way a comment on the suitability of a specific battery in a customer s application Table 15 A Suggested Batteries for the DS87C530 NOMINAL CAPACITY MANUFACTURER MODEL NUMBER TYPE VOLTAGE V mAh CR1620 Lithium Manganese Dioxide 3 70 CR1616 Lithium Manganese Dioxide 3 50 Panasonic 1220 Lithium Manganese Dioxide 3 35 BR1616 Lithium Polycarbon Monofluoride 3 48
202. mer reset can be enabled without the potential of generating unwanted resets At the same time the watchdog interrupt may also be disabled Proper use of the watchdog interrupt with the watchdog reset allows interrupt software to survey the system for errant conditions When using the watchdog timer as a system monitor the watchdog reset function should be used If the Interrupt function were used the purpose of the watchdog would be defeated For example assume the system is executing errant code prior to the watchdog interrupt The interrupt would temporarily force the system back into control by vectoring the CPU to the interrupt service routine Restarting the watchdog and exiting by an RETI or RET would return the processor to the lost position prior to the interrupt By using the watchdog reset function the processor is restarted from the beginning of the program and therefore placed into a known state The watchdog has four timeout selections based on the input crystal frequency as shown in the following table The selections are a preselected number of clocks Therefore the actual timeout interval is dependent on the crystal frequency Shown below are the four timeouts with some example periods for different crystal speeds Note that the time period shown is for the interrupt event The reset when enabled will occur 512 clocks later regardless of whether the interrupt is used Therefore the actual watchdog timeout period 15 the number sho
203. n Mode 0 Since it was generally set to a 0 for the divide by 12 there is no compatibility problem Rev 030308 140 of 175 High Speed Microcontroller User s Guide 12 3 2 Mode 2 In this asynchronous mode baud rates are also generated from the oscillator input This mode works identically to the original 8051 family The baud rate is given by the following formula 25MOD Oscillator Frequency Mode 1 3 Baud Rate 64 X 2x 256 THI The result of this formula generates a baud rate of either 1 32 x oscillator frequency or 1 64 x oscillator frequency In the formula the numerator is expressed as two to the power of SMOD where SMOD is either a 0 or 1 When 0 the numerator is a and when SMOD 1 the numerator is a 2 SMOD is a bit that effectively doubles the baud rate when set to logic 1 For Serial Port 0 SMOD 0 resides at PCON 7 This is the original location in the 8051 family For Serial port 1 SMOD 1 resides in WDCON 7 The SMOD bits are set to a logic 0 on reset which gives the lower speed baud rate If the application determines that Mode 0 or 2 must be used then the oscillator or crystal frequency must be selected to generate the correct baud rates since each mode offers two selections for a given frequency 12 3 3 Mode 1 or 3 These asynchronous modes are commonly used for communication with PCs modems and other similar interfaces The baud rates are programmable using the oscillator input and 16 bit Timer 2 o
204. n ports 0 and 2 For example if the on chip program memory is 1kB then it lies between 0000h and 03FFh in a contiguous area MOVX instruction affecting memory location 0400h would be directed to the expanded bus 030308 76 175 High Speed Microcontroller User s Guide Another advantage of internal data memory is that it guarantees a two machine cycle data memory access This data can be made nonvolatile on the DS87C530 through the use of an external battery Restricting memory operations within the on chip memory allows ports 0 and 2 to be used for general purpose I O For more information concerning memory size for a specific device consult the corresponding data sheet Upon a power on reset the internal data memory area is disabled and transparent to the system map Any memory access between 0000h and FFFFh will be directed to the Expanded bus This allows the device to remain drop in compatible with existing 87C52 designs To enable the internal SRAM area software must configure the Data Memory Enable bits DMEI DMEO 1 0 The three memory configurations shown in Table 6 A are supported to allow either external data memory access via the expanded bus internal data memory access or read only access to the EPROM System Control Byte Note that these bits are cleared after a reset so access to the internal data memory is prohibited until these bits are modified The contents of internal data memory are not affected by t
205. n received In mode 0 RI 0 15 set at the end of the 8th bit In mode 1 it is set after the last sample of the incoming stop bit subject to the state of SM2 0 In modes 2 and 3 RI 0 is set after the last sample of 8 0 It must cleared manually by software SMO FE 0 68 10 MODE FUNCTION poca PERIOD 0 0 0 Sync 8 4 12 see SM2 0 1 1 10 Timer 1 2 1 0 2 Asynch 11 64 32 1 1 3 Asynch 11 Timer 1 or 2 Initialization SCON is set to 00h on a reset Read Write Access Unrestricted Rev 030308 138 of 175 High Speed Microcontroller User s Guide 12 2 2 Serial Port Control 1 Register SCON1 COh Serial Port 1 performs identically to the standard Serial Port 0 on an 80C32 with one exception The baud rate generation from Timer 2 is not available in Modes 1 and 3 Timer 1 is used The port is located at P1 3 and P1 2 for TXD1 and RXDI respectively SCONI1 7 Serial Port 1 Mode Bit 0 or Framing Error Flag 5 0 1 PCON 6 SMODO determines whether this bit functions as SMO or FE The operation of SMO SMODO 0 is described in the table below When SMODO 1 the serial port will set FE to indicate an invalid stop bit When used as FE this bit must be cleared in software SCONI 6 Serial Port 1 Mode Select 1 5 1 1 The operation of SMI 1 is described in the table below SCONI 5 Multiple MCU Communication SM2 1 Setting this bit to a one enab
206. nate RTCH 7 0 RTCH 7 0 Indeterminate RTAM 7 0 RTAM 7 0 Indeterminate 0 7 0 1 7 0 Indeterminate RTAH 7 0 RTAH 7 0 Indeterminate RTCD1 7 0 RTCDI 7 0 Indeterminate 8 4 In System Disable Mode The high speed microcontroller family supports in circuit debugging of designs The in system disable ISD feature allows the device to be three stated for in circuit emulation or board testing During ISD mode the device pins will take on the following states DEVICE PIN STATE DURING ISD Port 0 1 2 3 RST EA True three state ALE PSEN Weak Pullup 10kQ XTALI XTAL2 Oscillator remains active The following procedure is used to enter ISD mode 1 Assert reset by pulling RST high 2 Pull ALE low and pull PSEN high 3 Verify that P2 7 P2 6 P2 5 are not being driven low 4 Release RST 5 Hold ALE low and PSEN high for at least two machine cycles 6 Device is now in ISD mode Release ALE and PSEN if desired Note that pins P2 7 P2 6 P2 5 should not be driven low when RST is released This will place the device into a reserved test mode Because these pins have a weak pullup during reset they can be left floating The test mode is only sampled on the falling edge of RST and once RST is released their state will not affect device operation In a similar manner the PSEN and RST pins can be released once ISD mode is invoked and their state will not affect device operation The RST pin will also be in a th
207. ned below 5 6 1 Single Cycle Instructions The standard single cycle instruction timing is shown in Figure 5 3 As previously mentioned there are 126 op codes that are single cycle instructions An example of a single cycle instruction is as follows DEC A 14h 5 6 2 Two Cycle Instructions two cycle instructions require two cycles because they involve two bytes or require two memory accesses The first byte is an op code that instructs the CPU This is the instruction itself The second byte is normally an operand or it specifies the location of the operand For example the instruction ANL A direct uses two cycles and requires two bytes Two examples are as follows ANL A direct 55h 7 0 54h 7 0 Note that the first example the first memory access is the op code second memory access is the location of the operand in the register map Since the result is stored in an internal register this operation does not require a memory access The second example is very similar Again the first byte represents the op code In this example the second byte is the operand itself This byte is used directly by the instruction The timing for a two cycle instruction is shown in Figure 5 4 030308 65 of 175 High Speed Microcontroller User s Guide One other type of two cycle instruction requires two cycles but only includes one byte This is because the second memory access is the re
208. ng the alarm registers The alarm can be set to occur on a match with any or all of the alarm registers An alarm can occur on a unique time of day or a recurring alarm can be programmed every subsecond second minute or hour Alarms can occur synchronously when the clock rolls over to match the alarm condition or asynchronously if the alarm registers are set to a value that matches the current time Note that only one alarm may occur per subsecond tick This means that if a synchronous alarm has already occurred during the current subsecond software cannot cause an asynchronous alarm in the same subsecond The specific alarm registers to be compared are selected by setting or clearing the corresponding compare enable bits RTCC 7 4 Any compare bit that is cleared will result in that register being treated as a don t care when evaluating alarm conditions Clearing all the compare enable bits will disable the ability of the RTC to cause an interrupt and will immediately clear the RTC interrupt flag RTCC 1 Unlike some interrupts the RTC flag is not cleared by exiting the RTC interrupt service routine and must be explicitly cleared in software The general procedure for setting the RTC alarm registers to cause a RTC interrupt is as follows 1 Clear the ERTCI enable bit EIE 5 2 Clear all RTC alarm compare enable bits ANL 0Fh 3 Write one or more RTC alarm registers 4 Setthe desired RTC alarm compare enable bits
209. normal operating voltage The power monitor also functions on power up holding the microcontroller in a reset state until power is stable 3 2 16 Interrupts The high speed microcontroller is capable of evaluating a number of interrupt sources simultaneously Each version of the high speed microcontroller provides a different number of interrupt sources Each interrupt has an associated interrupt vector flag priority and enable Each interrupt can be globally enabled or disabled 3 2 17 Timing Control The high speed microcontroller provides an on chip oscillator for use with an external crystal This can be bypassed by injecting a clock source into the XTAL 1 pin The clock source is used to create machine cycle timing four clocks ALE PSEN watchdog timer and serial baud rate timing In addition some devices incorporate an on chip ring oscillator which can be used to provide an approximately 2MHz to 4MHz clock source 3 2 18 Real Time Clock The DS87C530 incorporates a real time clock that is accessed by the SFR locations The 15 divided into hour minute second and subsecond registers and also incorporates a 65 536 day calendar Alarm registers allow the RTC to issue interrupts at a specific time once a day or as a recurring alarm every hour minute or second An external watch crystal and lithium power source allow the processor to maintain timekeeping in the absence of 3 2 19 Feature Summary The hi
210. nsmit buffer loaded serial port 0 1 Watchdog timer reset Power on reset External reset In the case of a serial port initiated switchback the switchback is not generated by the associated interrupt This is because a device operating in PMM will not be able to correctly receive a byte of data to generate an interrupt Instead a switchback is generated by a serial port reception on the falling edge associated with the start bit if the associated receiver enable bit SCONO 4 or SCON1 4 is set For serial port transmissions a switchback is generated when the serial port buffer SBUF0 99h or SBUF1 C1h 15 loaded This ensures the device will be operating in divide by 4 mode when the data is transmitted and eliminates the need for a write to CD1 CDO bits to exit before transmitting The switchback feature is unaffected by the state of the serial port interrupt flags RI 0 TI 0 RI 1 TI 1 The timing of the switchback is dependent on the source Interrupt initiated switchbacks will occur at the start of the first C1 cycle following the event initiating the switchback In PMM each internal Cx cycle is 16 external clock cycles for PMMI and 256 cycles for 2 If the current instruction in progress is a write to the IE IP EIE or EIP registers interrupt processing will be delayed until the completion of the following instruction Serial transmit initiated switchbacks occur at the start of the instruction following the MO
211. ntal mode The oscillator employs a high gain amplifier to assure a clean waveform at high frequency Due to the high performance nature of the product both clock edges are used for internal timing Therefore the duty cycle of the clock source is of importance A crystal circuit will balance itself automatically Thus crystal users will not need to take extra precautions concerning duty cycle 5 5 Crystal Selection The high speed microcontroller family was designed to operate with fundamental mode crystals for improved stability Although most high speed 1 greater than 25MHz crystals operate from their third overtone fundamental mode crystals are available from most major crystal suppliers Designers are cautioned to ensure that high speed crystals being specified for use in their application do operate at the rated frequency in their fundamental mode The use of a third overtone crystal will typically result in oscillation rates at one third the desired speed 030308 63 of 175 High Speed Microcontroller User s Guide Figure 5 1 Crystal Connection HIGH SPEED MICROCONTROLLER TO INTERNAL CIRCUITS Figure 5 2 Clock Source Input HIGH SPEED MICRO CLOCK OSCILLATOR TO INTERNAL CIRCUITS 5 6 Instruction Timing The clock source whether crystal or oscillator supplies the internal functions with a precise time base The clock is used to create the basic unit of timing called a machine cycle One machine cycl
212. nually by software Setting this bit in software will cause an interrupt if enabled External Interrupt 2 Flag This bit will be set when a rising edge is detected on INT2 This bit must be cleared manually by software Setting this bit in software will cause an interrupt if enabled Crystal Ring Source Select This bit selects the crystal oscillator or ring oscillator as the desired clock source This bit will be the inverse of RGMD except during the crystal warmup period when executing a ring oscillator resume from Stop XTUP STATUS 4 must be set to 1 and XTOFF PMR 3 must be cleared to 0 before this bit can be set Attempts to modify this bit when these conditions are not met will be ignored This bit must be cleared before XTOFF can be set to 1 This bit is set to 1 after a power on reset and unchanged by all other forms of reset This bit is not used on the DS80C310 or DS80C320 and will be 1 when read 0 The ring oscillator is selected as the clock source This setting is unaffected by XTUP STATUS 4 XTOFF PMR 3 1 The crystal oscillator is selected as the clock source This setting is invalid unless XTUP 1 and XTOFF 0 Ring Mode Status This bit indicates the current clock source for the device This bit is cleared to 0 after a power on reset and unchanged by all other forms of reset The state of this bit will be undefined on devices that do not incorporate a ring oscillator 0 Device is operating from the extern
213. ocontroller when the interrupt occurs If the microcontroller is performing an ISR with equal or greater priority the new interrupt will not be invoked In other cases the response time depends on the current instruction The fastest possible response to an interrupt is 5 machine cycles This includes one cycle for detecting the interrupt and four cycles to perform the LCALL that is inherent in the interrupt request The maximum response time if no other interrupt is in service occurs if the microcontroller is performing an RETI instruction and then executes a MUL or DIV as the next instruction From the time an interrupt source is activated not detected the longest reaction time is 13 machine cycles This includes 1 cycle to detect the interrupt 3 cycles to finish the RETI 5 to perform the MUL or DIV then 4 for the LCALL to the ISR The maximum latency of 13 machine cycles is 52 clocks 13 x 4 Note that the maximum interrupt latency of an 8051 is 96 clocks 8 machine cycles at 12 clocks per machine cycle The maximum latency for the high speed microcontroller at 25MHz is about 2 8 The use of power management modes further increase the interrupt latency 030308 109 of 175 High Speed Microcontroller User s Guide Figure 9 1 Interrupt Functional Description INTERRUPT INTERRUPT SELECTION HARDWA HIGHEST PRIORITY INTERRUPT VECTOR INT5 WATCHDOG REAL TIME CLOCK 1 INDIVIDUAL GLOBAL ENABLES ENABLE
214. od can also be used to increase the amount of available program memory from 64kB to 80kB without bank switching Section 6 Program and data memory can also be increased beyond the 64kB limit using bank switching techniques This is described in Application Note 81 Memory Expansion with the High Speed Microcontroller Family 4 1 2 Register Map The register map is illustrated in Figure 4 2 It is entirely separate from the program and data memory areas mentioned above A separate class of instructions is used to access the registers There are 256 potential register location values In practice the high speed microcontroller has 256 bytes of Scratchpad RAM and up to 128 special function registers SFRs This is possible since the upper 128 Scratchpad RAM locations can only be accessed indirectly That is the contents of a Working Register described below will designate the RAM location Thus a direct reference to one of the upper 128 locations must be an SFR access Direct RAM is reached at locations 0 to 7Fh 0 to 127 030308 14 of 175 High Speed Microcontroller User s Guide SFRs are accessed directly between 80h and FFh 128 to 255 The RAM locations between 128 and 255 can be reached through an indirect reference to those locations Scratchpad RAM is available for general purpose data storage It is commonly used in place of off chip RAM when the total data contents are small When off chip RAM is needed the Scratchpad ar
215. of most functions in the high speed microcontroller A machine cycle of the high speed microcontroller is the time required to execute a single cycle instruction Almost half the op codes of the 8051 instruction set are implemented in a single machine cycle in the high speed microcontroller The remaining instructions require multiple machine cycles The power management modes implemented on some devices modify the number of clock cycles needed to execute an instruction Instead of 4 clocks per machine cycle power management mode 1 and power management mode 2 PMM2 use 64 and 1024 clocks per cycle respectively to conserve power A full description of the power management modes and their effect on CPU operation is provided in Section 7 instructions are coded within an 8 bit field called an op code This single byte must be fetched from program memory The CPU decodes the op code It determines what action the microcontroller takes and whether more information is needed from memory If no other memory is needed then only one byte was required Thus the instruction is called a one byte instruction In some cases more data is needed These will be two or three byte instructions In most cases the number of memory accesses bytes needed by an instruction 15 equal to the number of machine cycles Thus single cycle instructions contain one byte and two cycle instructions have two bytes This is true except for the special cases mentio
216. oftware execution to begin immediately upon resuming from Stop mode The ring oscillator mode bit RGMD EXIF 2 indicates the current clock source In Stop mode enabled interrupts become true edge triggered interrupts compared with the sampled edge detection used during normal operation This means that external interrupts are more sensitive to noise in Stop mode than during normal operation Applications should be carefully designed to ensure that noise will not cause an erroneous exit from Stop mode Rev 030308 100 of 175 High Speed Microcontroller User s Guide 7 3 6 Switching Between Clock Sources DS87C520 and DS87C530 incorporate the ability to run the device from the ring oscillator after the crystal warmup period has elapsed Immediately following a reset including initial power up all devices must operate from an external crystal or oscillator At this point software may switch to the ring oscillator by clearing the XT RG bit EXIF 3 If there is no expectation that the crystal oscillator will be needed soon the crystal oscillator can be disabled by setting the Crystal Oscillator Disable Bit XTOFF PMR 3 Note that switching to the ring oscillator does not automatically disable the crystal amplifier and thus it is possible to be operating the device from the ring oscillator and have the external crystal amplifier operating at the same time In some cases this may be desired to take advantage of the low frequency low power fea
217. ommended if a brownout condition is possible in Stop mode If power fails completely Vcc then a power on reset will still be performed when is reapplied regardless of the state of the BGS bit Processor operation will resume execution from address 0000h like any other reset 7 2 2 1 Crystal Resume from Stop Mode If the microcontroller does not contain a ring oscillator or if the RGSL bit is 0 a device exiting Stop mode must restart operation using the external crystal as a clock source The device will experience a power on reset delay of 65 536 external clock cycles to allow the crystal to begin oscillation and the frequency to stabilize Once this delay is complete software will begin execution from either address 0000h or the appropriate interrupt vector depending on the stimulus to exit Stop mode The same 65 536 external clock cycle delay is performed if an external crystal oscillator is used instead of an external crystal Table 7 A Pin States in Power Saving Modes PO MODE ALE PSE 1 2 DEVICE SEN 0 7 P1 P2 P3 DS80C310 1 2 3 2 Idle or Sto 1 1 Latched Port data Latch Port data DS80C320 p greu idu Others Internal Program Idle or Stop 1 1 Port data Port data Port data Port data Execution Others External Program Idle 1 1 Latched Port data Latched Port data Execution Others External Program Stop 1 1 Port data Port data Por
218. on any interrupt pin is 1 8 of the main oscillator frequency It is important to note that level sensitive interrupts are not latched If the interrupt is level sensitive the condition must be present until the processor can respond to the interrupt This is most important if other interrupts are being used with a higher or equal priority If the device is currently processing another interrupt the condition must be present until the present interrupt is complete This is because the level sensitive interrupt will not be sampled until the RETI instruction is executed The remaining four external interrupts are similar in nature with two differences First INT2 and INT4 are active high instead of active low Second all of the four new interrupts are edge detect only They do not have level detect modes All associated bits and flags operate the same and have the same polarity as the original two A logic indicates the presence of a condition not the logic state of the pin If the Power Management Modes are utilized the designer must remember that edge triggered interrupts must be high and low for one machine cycle before being recognized This means that in PMMI it will require 128 external clock cycles to recognize a level sensitive interrupt Similarly in 2 it will require 2048 external clock cycles to recognize a level sensitive interrupt As a result the interrupt latency for these interrupts will be slightly longer in or
219. or T2 pins the timer operates at the frequency of the external source and is not affected by the setting of the TOM or T2M bits The only limitation is that the external source frequency can be no faster than 1 8 of the main oscillator frequency The use of power management modes will affect the input clock to the timer as shown in the illustrations In general they will divide the input clock by either 16 or 256 for PMMI and 2 respectively Timer 2 when operating in baud rate generator or clock out mode normally uses the input clock frequency divided by 2 but when and 2 are used it will operate from a time base of the input clock divided by 32 and 512 respectively 030308 131 of 175 High Speed Microcontroller User s Guide 11 9 Watchdog Timer The watchdog timer is a user programmable clock counter that can serve as a time base generator an event timer or a system supervisor can be seen in the diagram of Figure 11 8 the main system clock drives the timer that is supplied to a series of dividers The divider output is selectable and determines the interval between timeouts When the timeout is reached an interrupt flag will be set and 1f enabled a reset will occur The interrupt flag will cause an interrupt to occur if its individual enable bit is set and the global interrupt enable is set The reset and interrupt are completely discrete functions that may be acknowledged or ignored togethe
220. or both the source and destination Thus the high speed microcontroller offers two data pointers The user selects the active pointer via a dedicated SFR bit 3 2 5 Stack Pointer The microcontroller provides a stack in the scratchpad RAM area The stack pointer denotes the register location at the top of the stack which is the last used value The user can place the stack anywhere in scratchpad RAM by setting the stack pointer to that location 3 2 6 Ports The standard high speed microcontroller offers four 8 bit I O ports ROM less versions use Port 0 and Port 2 as address and data buses In those versions only two ports are available for general purpose I O Each I O port is a SFR that can be written or read The I O port has a latch that retains the value which software writes In general during a read operation software reads the state of the external pin Each port is represented by a SFR location 030308 11 of 175 High Speed Microcontroller User s Guide 3 2 7 Timer Counters Three 16 bit Timer Counters are available in the high speed microcontroller Each timer is contained in two SFR locations that can be written or read by software The timers are controlled by other SFRs described in Section 4 3 2 8 The high speed microcontroller provides or two UARTS These are controlled and accessed as SFRs Each UART has an address that is used to read or write the UART Both read and write operations u
221. ors to location 33h At this time software can disable the interrupt save any critical data clear PFI and then continually poll the status of the power supply via the PFI flag As long as PFI is set power is still below Vprw If power returns to the proper level PFI will not be set once cleared by software This indicates a safe operating condition If power continues to fall a power fail reset will be invoked automatically 030308 88 of 175 High Speed Microcontroller User s Guide 7 1 2 Power Fail Reset Devices that incorporate the power fail reset will automatically invoke a reset when drops below Vnsr This will halt device operation and place all outputs in their reset state This state will continue to be held until drops below the voltage necessary to power the port pins Because is lower than Vprw the microcontroller has the option to use the power fail interrupt to place the device into a safe state before the device halts operation with a power fail reset This feature is automatic on devices that incorporate the power fail reset feature and cannot be disabled except during Stop mode when the BGS bit is 0 7 1 3 Power On Reset When is applied to a system using the high speed microcontroller the device will hold itself in reset until power is within tolerance and stable It requires no external circuits to accomplish this As power rises the processor will stay in a reset state un
222. ort 0 Baud Rate Doubler Enable This bit enables disables the serial baud rate doubling function for Serial Port 0 0 Serial Port 0 baud rate will be that defined by baud rate generation equation 1 Serial Port 0 baud rate will be double that defined by baud rate generation equation Framing Error Detection Enable This bit selects function of the SCONO 7 and SCON1 7 bits 0 5 0 7 and SCONI 7 control the SMO function defined for the SCONO and SCONI registers 1 SCONO 7 and SCONI 7 are converted to the Framing Error FE flag for the respective Serial Port Reserved Read data is indeterminate General Purpose User Flag 1 This is a general purpose flag for software control General Purpose User Flag 0 This is a general purpose flag for software control Stop Mode Select Setting this bit will stop program execution halt the CPU oscillator and internal timers and place the CPU in a low power mode This bit will always be read as a 0 Setting this bit while the Idle bit is set will place the device in an undefined State Idle Mode Select Setting this bit will stop program execution but leave the CPU oscillator timers serial ports and interrupts active This bit will always be read as a 0 27 of 175 High Speed Microcontroller User s Guide 4 2 9 Timer Counter Control TCON SFR 88h 7 6 5 4 3 2 1 0 1 0 0 0 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0
223. ous with multiprocessor T Timer 1 baud rate equation communication 5 1 Framing Error Flag When SMODO PCON 6 0 this bit SMO is used to select the Bit 7 mode for serial port 1 When SMODO PCON 6 1 this bit FE will be set upon detection of an invalid stop bit When used as FE this bit must be cleared in software Once the SMODO bit is set modifications to this bit will not affect the serial port mode settings Although accessed from the same register internally the data for bits SMO and FE are stored in different locations 1 No alternate function Bit 6 Rev 030308 40 of 175 EE memes High Speed Microcontroller User s Guide 5 2 1 Multiple CPU Communications The function of this bit is dependent on the serial port 1 Bit 5 mode Mode 0 Selects 12tc or Atc period for synchronous port 1 data transfers Mode 1 When this bit 15 set reception is ignored RI 1 is not set if invalid stop bit received Mode 2 3 when this bit is set multiprocessor communications are enabled in mode 2 and 3 This will prevent RI 1 from being set and an interrupt being asserted if the 9th bit received is not 1 REN 1 Receive Enable This bit enables disables the serial port 1 receiver shift register Bit4 0 Serial port 1 reception disabled Serial port 1 receiver enabled modes 1 2 3 Initiate synchronous reception mode 0 8 1 9th Transmission Bit S
224. ower On Reset Flag WDCON EWT Watchdog Reset Enable WDCON 0 RWT Reset Watchdog Timer WDCON 3 WDIF Watchdog Interrupt Flag TRIM 7 4096Hz Output TRIM 6 X12 6 12pF 6pF Crystal Select TRIM 5 TRM2 Capacitance Trim Bit 2 TRIM 4 TRM2 Inverse Capacitance Trim Bit 2 TRIM 3 TRMI Capacitance Trim Bit 1 TRIM 2 TRMI Inverse Capacitance Trim Bit 1 TRIM 1 TRMO Capacitance Trim Bit 0 TRIM 0 TRMO Inverse Capacitance Trim Bit 0 ROMSIZE 2 RMS2 ROM Size Select Bit 2 ROMSIZE 1 RMSI ROM Size Select Bit 1 ROMSIZE 0 RMSO ROM Size Select Bit 0 RTCC 2 RTCWE RTC Write Enable 0 RTC Enable 13 2 Protection Scheme Each bit mentioned above is protected against an accidental write by requiring the software to perform a procedure before writing the bit Timed access requires the software to write two specific values to the timed access register during two consecutive instruction cycles The values AAh then 55h must be written in consecutive instructions to the TA register at SFR location C7h If the writes are performed correctly the write access window will open for three machine cycles During this window the software may modify a protected bit The suggested code to open a timed access window 15 MOV 0 7 0AAh MOV 558 The procedure to modify a timed accessprotected bit begins by writing the value AAh to the timed access register TA C7h The value 55h must then be written to the timed access register within three
225. r 8 bit Timer 1 The respective timer is placed in auto reload mode Each time the timer reaches its rollover condition FFFFh 0000h Timer 2 or FFh 00h Timer 1 a clock is sent to the baud rate circuit This clock 15 then divided by 16 to generate the exact baud rate For Serial Port 0 either Timer 1 or 2 can be used to generate baud rates Note that there are differences between the timers when used as baud rate generators Serial Port 1 can use Timer 1 as a baud rate generator Thus in Mode 1 or 3 the two serial ports can run at the same frequency if Timer 1 is used for both but different frequencies if both timers are used Also note that the user can determine the speed at which Timer 1 runs 4 clocks or 12 clocks In most cases 12 clocks will be used for baud rate generation Timer 2 runs from a two clock scheme when used for baud rate generation This is compatible with the 80C32 The baud rates for Mode 1 or 3 are given by these formulas Serial Port 0 or 1 2 SMOD x Mode 1 3 Baud Rate 32 X Timer 1 Overflow Serial Port 0 Timer 2 Overflow Mode 1 3 Baud Rate 16 To use Timer 1 as the baud rate generator it is commonly put into the 8 bit auto reload mode In this way the CPU is not involved in baud rate generation Note that the timer interrupt should not be enabled In the 8 bit auto reload mode Timer 1 Mode 2 the reload value is stored in TH1 Thus the combination of crystal frequency and determine the
226. r Bank Select 1 0 These bits select which register bank is addressed during Bits 4 3 register accesses RS1 RSO REGISTER BANK ADDRESS 0 0 0 00 07 0 1 1 08h 0Fh 1 0 2 10 17 1 1 3 18h 1Fh OV Overflow Flag This bit is set to 1 if the last arithmetic operation resulted in a carry Bit 2 addition borrow subtraction or overflow multiply or divide Otherwise it is cleared to 0 by all arithmetic operations 1 User Flag 1 This is a bit addressable general purpose flag for software control Bit 1 Parity Flag This bit is set to 1 if the modulo 2 sum of the eight bits of the accumulator Bit 0 is 1 odd parity and cleared to 0 on even parity Rev 030308 49 of 175 High Speed Microcontroller User s Guide 4 2 42 Watchdog Control WDCON 7 6 5 4 3 2 1 0 SFR D8h SMOD POR EPFI PFI WDIF WTRF EWT RWT RW 0 RT RW 0 RW RT 0 RT RT RT 0 R Unrestricted Read W Unrestricted Write T Timed Access Write Only n Value after Reset See Description SMOD Serial Modification This bit controls the doubling of the serial port 1 baud rate in Bit 7 modes 1 2 and 3 0 Serial port 1 baud rate operates at normal speed 1 Serial port 1 baud rate 1s doubled POR Power On Reset Flag This bit indicates whether the last reset was a power on reset Bit 6 This bit is typically interrogated following a reset to determine if the reset was caused by a power on reset It must be cleare
227. r can be read only when the RTCRE bit is set and can only be modified when the RTCWE bit is set Consult the description of the RTCWE bit for the programming protocol for this register This register counts from lh to 7h and increments when the hour value of the RTC RTCH 4 0 rolls over from 17h to Oh Writing a Oh to these bits will disable the day of week function and the count will remain 0 No alarm corresponds to these bits Real Time Clock Hours These bits represent the hour value of the RTC This register Bits 4 0 can be read only when the RTCRE bit 15 set and can only be modified when the RTCWE bit is set Consult the description of the RTCWE bit for the programming protocol for this register This register counts from Oh to 17h 0 to 23 hours and any writes outside of that range will generate an inaccurate count Hev 030308 57 of 175 High Speed Microcontroller User s Guide 4 2 56 Real Time Clock Day Register 0 RTCDO 7 6 5 4 3 2 1 0 SFR RTCDO 7 0 6 RTCDO 5 RTCDO 4 0 3 RTCDO 2 RTCDO 1 RTCDO 0 R w R W R W R Ww R w R w R W R Ww R Unrestricted Read W Unrestricted Write n Value after Reset See Description RTCDO0 7 RTCD 0 Real Time Clock Day Register 0 This register contains the least significant byte of the Bits 7 0 16 bit current day count This is not an absolute value tied to a spe
228. r or separately for various applications Figure 11 8 Watchdog Timer RWT WDCON 0 Reset Watchdog DIVIDE BY DIVIDE BY DIVIDE BY uri BY 1 16 256 WD1 CKCON 7 TIMEOUT TIMEOUT WDO 6 SELECTOR CLOCK DIVIDE CONTROL CD1 CDO DIVISOR WDIF C WATCHDOG Dn PMR WDCON 3 INTERRUPT 1 0 16 EWDI EIE 4 1 1 256 Enable Watchdog Interrupt 512 CLOCK DELAY EWT WDCON 1 WTRF Enable Watchdog Timer Reset WDCON 2 The watchdog timer reset function works as follows After initializing the correct timeout interval discussed below software first restarts the watchdog using RWT WDCON 0 and then enables the reset mode by setting the enable watchdog timer reset EWT WDCON 1 bit At any time prior to reaching its user selected terminal value software can set the reset watchdog timer RWT WDCON 0 bit If RWT is set before the timeout 1s reached the timer will start over If the timeout is reached without RWT being set the watchdog will reset the CPU Hardware will automatically clear RWT after software sets it When the reset occurs the watchdog timer reset flag WTRF WDCON 2 will automatically be set to indicate the cause of the reset however software must clear this bit manually The watchdog timer is a free running timer When used as a simple timer with both the reset and interrupt functions disabled EWT 0 and EWDI 0 the timer will continue to set the watchdog interrupt
229. r the DS87C530 is drawing current from pins This satisfies the two mechanism requirement of most safety codes 030308 162 of 175 High Speed Microcontroller User s Guide 16 INSTRUCTION SET DETAILS Details of flags modified by each instruction are located in Section 4 INSTRUCTION CODE MNEMONIC D D D Ds D D D D HEX BYTE CYCLE EXPLANATION ADD A Rn 0 0 1 0 1 n n no 282F 1 1 A Rn ADD direct 0 0 1 0 0 1 0 1 25 2 2 direct a Byte 2 ADD Ri 0 0 1 0 0 1 1 26 27 1 1 A R1 ADD 0 0 1 0 0 1 0 0 24 2 2 A A data d d ds dy dj 4 2 ADDC A Rn 0 0 1 1 m n 38 1 1 A C Rn ADDC A 0 0 1 1 0 1 0 1 35 2 2 A C direct direct a Byte 2 ADDCA gRi 0 0 1 1 0 1 1 36 37 1 1 1 ADDC 0 0 1 1 0 1 0 0 34 2 2 A A C data d de ds 4 4 dz d do Byte 2 E SUBB A Rn 1 0 0 1 1 m n 98 9 1 1 A C Rn 2 5 1 0 0 1 0 1 0 1 95 2 2 A 7 A C direct w direct a Byte 2 5 SUBB A Ri 1 0 0 1 0 1 1 1 96 97 1 1 1 O SUBB A 1 0 0 1 0 1 0 0 94 2 2 A A C data data d d d d dj d dy B
230. receive buffers are separate registers but both are addressed at this location 41 of 175 High Speed Microcontroller User s Guide 4 2 31 ROM Size Select ROMSIZE 7 6 5 4 3 2 1 0 SFR C2h RMS2 RMS1 RMSO RT 1 RT 0 RT 1 R Unrestricted Read W Unrestricted Write n Value after Reset Bits 7 3 These bits are reserved Read data is indeterminate RMS2 RMSI ROM Size Select 2 0 This register is used to select the maximum on chip decoded RMS0 address for ROM Care must be taken that the memory location of the current program Bits 2 1 0 counter will be valid both before and after modification These bits can only be modified using a timed access procedure The EA pin will override the function of these bits when asserted forcing the device to access external program memory only Configuring this register to a setting that exceeds the maximum amount of internal memory may corrupt device operation These bits will default on reset to the maximum amount of internal program memory 1 16 for DS87C520 o po o La 1 ___ 030308 42 of 175 High Speed Microcontroller User s Guide 4 2 32 Power Management Register PMR 7 6 5 4 3 2 1 0 SFR C4h CDI SWB XTOFF ALEOFF DMEI DMEO RW 0 RW 1 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestrict
231. received data will be lost SBUF and not loaded and RI will not be set Regardless of the receive word status after the middle of the stop bit time the receiver will go back to looking for a 1 to 0 transition on the RXD pin Each data bit received is sampled on the 7th 8th and 9th clock used by the divide by 16 counter Using majority voting two equal samples out of the three determines the logic level for each received bit If the start bit was determined to be invalid 71 then the receiver goes back to looking for a 1 to 0 transition on the RXD pin in order to start the reception of data 030308 145 of 175 High Speed Microcontroller User s Guide Figure 12 2 Serial Port Mode 1 TRANSMIT SHIFT REGISTER TIMER 2 P3 1 TXD TIMER 1 OVERFLOW LATCH PIN OVERFLOW DATA BUS WDCON 7 TCLK LOAD SHIFT T2CON 4 ioi RCLK BY 16 BUFFER CLOCK 0 Tad RESET RB8 SCONx 2 T1 R1 FLAG FLAG SCONx 1 SCONx 0 SERIAL CONTROL SERIAL INTERRUPT DIVIDE BY 16 BIT DETECTION TRANSMIT TIMING LDSBUF SHIFT s start Do X Di X X X ps X STOP TI RECEIVE TIMING RXD N Do Dt X 05 X 06 BIT DETECTOR SAMPLING RI IS NN SHIFT 030308 146 of 175 High Speed Microcontroller User s Guide 12 4 3 Mode 2 This mode uses a total of 11 bits in asynchronous full duplex communication as i
232. recommended to be below The DS87C530 automatically enters data retention mode when lt When in data retention mode the and SRAM contents are powered from the energy source connected to the pin and electrically isolated from the rest of the device This means that writes to battery backed SFRs and SRAM are ignored and reads return erroneous data while in data retention mode The DS87C530 data sheet contains a functional diagram of the internal battery switching circuitry The data retention switch voltage the point at which the device switches into data retention mode is a function of the battery voltage not an absolute reference Care must be taken when selecting a battery so that its voltage stays below during normal operation to prevent an unplanned lockout of the and SRAM Although it is unlikely that such a situation would occur it could become an issue if a relatively high voltage battery is used For example suppose a 4 5V battery 15 used with a device operating at a of 5 0V During normal operation is above so no problem occurs Suppose that a loss of power occurs and begins to drop Under normal circumstances the device continues to operate until it reaches 4 0 to 4 25V at which time device operation halts If is higher than however RTC and SRAM access are prohibited before the device enters reset This means that there
233. rect A 0 1 0 1 0 0 1 0 52 2 2 direct Byte 2 direct AND A ANL direct 0 1 0 1 0 0 1 1 53 3 3 direct data a a Byte2 direct AND data d dg 5 4 4 d di do Byte 3 ORL A Rn 0 1 0 0 1 n no 48 4F 1 1 A OR Rn ORL A direct 0 1 0 0 0 1 1 I 45 2 2 A 2 OR direct ORL A Ri 0 1 0 0 0 1 1 i 46 47 1 1 A A OR Ri lt ORL A data 0 1 0 0 0 10 0 44 2 2 A OR data s d d d d d d 4 d Byte2 ORL direct 0 1 0 0 0 0 0 42 2 2 direct 2 direct OR A 5 ORL direct 0 1 0 0 0 0 1 1 43 3 3 direct data a Byte 2 direct OR data d dg 5 4 4 d di do Byte 3 i XRL A Rn 0 1 1 0 1 n n 68 6F 1 1 A Rn XRL A direct 0 1 1 0 0 10 1 65 2 2 a Byte 2 direct XRL 0 1 1 0 0 1 1 i 66 67 1 1 A A R1 XRL A data 0 1 1 0 0 10 0 64 2 2 direct Byte 2 data direct 0 1 1 0 0 0 1 0 62 2 2 direct Byte 2 direct XOR A XRL direct 0 1 1 0 0 0 1 1 63 3 3 direct data a a Byte 2 direct XOR data d dg ds dy 4 d d do Byte 3 CLR A 1 1 1 0 0 10 0 4 1 1 0 CPLA 1 1 1 1 0 10 0 4 1 1 030308 164 of 175 High Speed Microcontroller User s Guide
234. red when the internal hardware sets the RI 1 bit Do not alter the Clock Divide Control bits PMR 7 6 while this bit is set or serial port data may be lost Serial Port 0 Transmit Activity Monitor When set this bit indicates that data is currently being transmitted by serial port 0 It is cleared when the internal hardware sets the TI 1 bit Do not alter the Clock Divide Control bits PMR 7 6 while this bit is set or serial port data may be lost On the DS8xC520 and DS8xC530 this bit does not accurately indicate serial port 0 transmit activity 1f a character is written to SBUFO while TI 0 is high If software intends to poll this bit first clear the 0 bit before writing each character to SBUFO Serial Port 0 Receive Activity Monitor When set this bit indicates that data is currently being received by serial port 0 It is cleared when the internal hardware sets the RI 1 bit Do not alter the Clock Divide Control bits PMR 7 6 while this bit is set or serial port data may be lost 45 of 175 High Speed Microcontroller User s Guide 4 2 34 SFR C7h Timed Access Register TA 7 6 5 4 3 2 1 0 7 6 5 4 3 2 TA 1 0 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W Unrestricted Write n Value after Reset 7 0 Timed Access Correctly accessing this register permits modification of timed access Bits 7 0 protected bits Write AAh to t
235. ree state mode but asserting it in ISD mode will return the device to normal operation Rev 030308 104 of 175 High Speed Microcontroller User s Guide 9 INTERRUPTS The high speed microcontroller family utilizes a three priority interrupt system The number of interrupts varies according to the specific device Each source has an independent priority bit flag interrupt vector and enable In addition interrupts can be globally enabled or disabled The system 1 compatible with the original 8051 family of the original interrupts are available Several new sources have been added with new associated control and status bits and new interrupt vectors Note that the interrupt vector table can extend from 0000h to 006Bh so existing code may require a relocation of the start address to avoid a conflict with the upper end of the vector table A summary of all interrupts appears in Table 9 A Table 9 A Interrupt Summary INTERRUPT NATURAL PRIORITY INTERRUET VECTOR PRIORITY FLAG ENABLE CONTROL Power Fail Indicator 33h 0 4 5 N A External Interrupt 0 03h 1 TCON IE 0 IP 0 Timer 0 Overflow OBh 2 TCON 5 PTO IP 1 External Interupt 1 13h 3 TCON 3 IE2 PXI IP2 Timer 1 Overflow 4 TFI TCON 7 3 3 Serial Port 0 23h
236. riginal 5 1 Oscillator The high speed microcontroller provides an on chip oscillator circuit that can be driven by an external crystal or by an off chip TTL clock source The oscillator circuit provides the internal clocking signals to the on chip CPU and circuits Figure 5 1 shows the required connections for a crystal In most cases a crystal will be the preferred clock source For very low power applications a low frequency ceramic resonator may also be used The capacitors shown in Figure 5 1 typical values If a resonator is used higher capacitance such as 47pF may be needed For higher frequency designs an off chip clock oscillator is preferred Figure 5 2 When using an off chip oscillator the duty cycle becomes important As nearly as possible a 50 duty cycle should be supplied 5 2 XTAL1 This pin is the input to an inverting high gain amplifier It also serves as the input for an off chip oscillator Note that when using an off chip oscillator XTAL2 is left unconnected 5 3 XTAL2 This pin is the output of the crystal amplifier It can be used to distribute the clock to other devices on the same board If using a crystal the loading on this pin should be kept to a minimum especially capacitive loading 5 4 Oscillator Characteristics The high speed microcontroller was designed to operate with a parallel resonant AT cut crystal The crystal should resonate at the desired frequency in its primary or fundame
237. rm these functions The bandgap reference provides a precise voltage to compare with Vcc When begins to drop the power monitor compares it to its reference This enables the analog circuits to detect when passes through predetermined thresholds Vprw and These are specified in the individual product data sheets 71 Power Management Features 7 1 1 Early Warning Power Fail Interrupt Devices that incorporate the precision voltage reference have the ability to generate a power fail interrupt and or reset in response to a low supply voltage When Vcc reaches the threshold the microcontroller can generate a power fail interrupt This early warning of supply voltage failure allows the system time to save critical parameters in nonvolatile memory and put external functions in a safe state The power fail interrupt is optional and is enabled using the enable power fail warning interrupt EPFI bit at WDCON 5 If enabled Vcc dropping below Vprw will cause the device to vector to address 33h The power fail Interrupt status bit PFI WDCON 4 will be set anytime Vcc transitions below Vprw This flag is not cleared when Vcc is above Vprw and software should clear it immediately after reading it As long as the condition exists PFI will be immediately set again by hardware A typical application of the PFI is to place the device into a safe mode when a power loss appears imminent When the interrupt occurs the code vect
238. rogramming protocol for this register This register counts from Oh to 3Bh 0 to 59 seconds and any writes to this register out side of that range will generate an inaccurate count Real Time Clock Minute Register RTCM 7 6 5 4 3 2 1 0 0 0 RTCM 5 4 RTCM2 RTCM 1 0 R 0 R 0 R W R w R w R Unrestricted Read W Unrestricted Write n Value after Reset See Description Bits 7 6 RTCM 5 RTCM 0 Reserved These bits will be 0 when read Real Time Clock Minutes This register represents the minute value of the RTC This Bits 5 0 register can be read only when the RTCRE bit is set and can only be modified when the RTCWE bit is set Consult the description of the RTCWE bit for the programming protocol for this register This register counts from Oh to 3Bh 0 to 59 minutes and any writes to this register out side of that range will generate an inaccurate count 4 2 55 Real Time Clock Hour Register RTCH 7 6 5 4 B 2 1 0 SFR DOW 2 DOW 1 DOW 0 4 3 2 RTCH 1 0 R Ww R W R W R W F R W R W R Unrestricted Read W Unrestricted Write n Value after Reset See Description DOW 2 DOW 0 Bits 7 6 5 RTCH 4 RTCH 0 Real Time Clock Day of the Week These bits represent the current day of the week This registe
239. roximately 2mA at 5V When serving as an port the drive will vary as follows For a logic 0 the port will invoke a strong pulldown For a logic 1 the port will invoke a strong pullup for two oscillator cycles to assist with the logic transition Then the port will revert to a weak pullup This weak pullup will be maintained until the port transitions from a 1 to a 0 External circuits can overdrive the weak pullup This allows the output 1 state to serve as the input state as well Substantial DC current is available in both the high and low levels However the power dissipation limitations make it inadvisable to heavily load multiple pins In general sink and source currents should not exceed 10mA total per port 8 bits and 25mA total per package 10 5 Current Limited Transitions The high speed microcontroller family incorporates special circuitry to limit the current consumed by the device when the expanded memory bus is used These signals employ current limited drivers that step the transition from a logic 0 to a logic 1 to reduce ringing and electromagnetic interference When expanded memory operations are in progress the following pins will exhibit the current limiting feature Port 0 Port 2 PSEN During program memory accesses ALE RD During data memory read cycles WR During data memory write cycles 10 6 Input Functions The input state of the I O ports is the same as that of the output logic 1 That is the p
240. rrupt instruction When RETI is performed the processor will return to the instruction that would have been next when the interrupt occurred Each interrupt source has an associated vector This is the address to which the CPU will jump when the interrupt occurs When the interrupt condition occurs the processor will also indicate this by setting a flag bit This bit is set regardless of whether the interrupt is enabled or not That is the flag responds to the condition not the interrupt Most flags must be cleared manually by software However IEO and are cleared automatically by hardware when the service routine is vectored to if the interrupt was edge triggered In level triggered mode the flag follows the state of the pin Flags and are always cleared automatically when the service routine is vectored to Refer to the individual bit descriptions for 030308 105 of 175 High Speed Microcontroller User s Guide more details In order for the processor to acknowledge the interrupt and vector to the ISR the interrupt must be enabled Each source has an independent enable as shown in Table 9 A Prior to using any source interrupts must be globally enabled This is done using the EA bit at location IE 7 Setting this bit to a logic 1 allows individual interrupts to be enabled Setting it to a logic 0 disables all interrupts regardless of the individual interrupt enables The only exception is the pow
241. rs The latter mode is available to Timer 0 only These modes are controlled by the TMOD register Each timer can also serve as a counter of external pulses 1 to 0 transition on the corresponding Tn pin This selection is controlled by the TMOD register One other option is to gate the timer counter using an external control signal This allows the timer to measure the pulse width of external signals Timers 0 and 1 are enabled using the TCON register which is also the 030308 118 of 175 High Speed Microcontroller User s Guide location of their flags The registers are described below Following this is a detailed explanation of the four operating modes Each timer consists of a 16 bit register in two bytes These are called TLO THO TL1 and 1 As shown each timer is broken into low and high bytes Software can read or write any of these locations at any time 11 1 1 Timer Mode Control Register TMOD Summary 7 6 5 4 3 2 1 0 TMOD 89h GATE C T MI 0 C T MI 0 Bit 7 Timer 1 Gate Control GATE When GATE 1 Timer 1 will clock only when and 1 When GATE 0 Timer 1 will clock only when TRI 1 irrespective of INTI Bit 6 Counter Timer Select C T When C T is set to a 0 Timer 1 is incremented by internal clocks When 1 set to a 1 Timer 1 counts based on the T1 P3 5 pin Bits 5 and 4 Timer 1 Mode Select Bit 1 and 0 M 1 0
242. ry Signals 4 SINGLE CYCLE 1 1 1 1 5 ADDRESS UU UU UU UU Rev 030308 80 of 175 High Speed Microcontroller User s Guide Figure 6 3 Data Memory Interface 74F373 LBS ADDRESS LATCH DATA BUS DS80C320 MSB ADDRESS WR P3 6 6 5 Data Memory Access As mentioned above the high speed microcontroller uses the MOVX instruction for data memory access This includes off chip RAM and memory mapped peripherals needing read write access Several aspects of the MOVX operation have been enhanced as compared to the original 8051 The principal improvements are in the areas of the MOVX timing and the data pointer The instruction is used to generate read write access to off chip address locations It has several addressing modes The first uses the MOVX Ri command to reach a 256 byte block This instruction uses the value in the designated working register to address one of 256 locations The upper byte of the address is supplied by the value in the Port 2 latch A second way to access data is the Data Pointer DPTR This 16 bit register provides an absolute address for data memory access 16 615 cover the entire 64kB area thus the DPTR serves as a pointer to memory Using the DPTR the relevant instruction is MOVX DPTR The original 8051 contained one DPTR While this provides access to the entire memory area it is difficult to move data from one address to another The high speed micro
243. s Down Count Enable This bit in conjunction with the T2EX pin controls the direction that timer 2 counts in 16 bit auto reload mode DUM DIRECTION 47 of 175 High Speed Microcontroller User s Guide 4 2 37 Timer 2 Capture LSB RCAP2L 7 6 5 4 3 2 1 0 SFR RCAP2L 7 RCAP2L 6 RCAP2L 5 RCAP2L 4 RCAP2L3 RCAP2L2 RCAP2L 1 RCAP2L 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset RCAP2L 7 Timer 2 Capture LSB This register is used to capture the TL2 value when timer 2 15 RCAP2L 0 configured in capture mode RCAP2L is also used as the LSB of a 16 bit reload value Bits 7 0 when timer 2 is configured in auto reload mode 4 2 38 Timer 2 Capture MSB RCAP2H 7 6 5 4 3 2 1 0 SFR RCAP2H 7 RCAP2H 6 RCAP2H 5 RCAP2H 4 RCAP2H 3 2 2 2 1 RCAP2H 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset RCAP2H RCAP2H Bits 7 0 4 2 39 SFR CCh TL2 7 TL2 0 Bits 7 0 4 2 40 SFR CDh TL2 7 TL2 0 Bits 7 0 7 Timer 2 Capture MSB This register is used to capture the TH2 value when timer 2 is 0 configured in capture mode RCAP2H is also used as the MSB of a 16 bit reload value when timer 2 is configured in auto reloa
244. s directly generated from the it can be used to determine the actual frequency of the RTC By adjusting the value of the TRMx bits the internal capacitance of the RTC can be varied slightly slowing or speeding up the RTC frequency The combination of TRMx bits TRIM 5 0 that causes the output on pin P1 7 to most closely approximate 4096Hz provides the most accurate setting of RTC capacitance As a precaution against accidental corruption of the oscillator trim bit settings the TRMx bits must be programmed in the same instruction to the inverse of their respective TRMXx bits For example if a trim bit setting of 5 101 was desired the TRMx bits should be set to 2 010 An illegal combination will automatically reset the TRIM register to 0x100101b This will disable the E4K signal on P1 7 but leave the X12 6 bit unmodified Refer to Application Note 79 Using the DS87C530 DS5250 Real Time Clock for more information about calibrating the RTC oscillator for improved accuracy 030308 160 of 175 High Speed Microcontroller User s Guide 15 BATTERY BACKUP The DS87C530 incorporates a feature that can maintain timekeeping and on chip SRAM contents in the absence of Vcc An external energy source such as a lithium battery or 0 47F super cap can be connected to the pin The nominal battery voltage should be For proper operation the battery voltage must always be at least a diode drop 0 7V below and is
245. se the same address The microcontroller distinguishes between a read and a write by the instruction Its own SFR control register controls each UART 3 2 9 Scratchpad Registers RAM The high speed core provides 256 bytes of Scratchpad RAM for general purpose data and variable storage The first 128 bytes are directly available to software The second 128 are available through indirect addressing discussed below Selected portions of this RAM have other optional functions 3 2 10 Stack The stack is a RAM area that the microcontroller uses to store return address information during Calls and Interrupts The user can also place variables on the stack when necessary The stack pointer mentioned above designates the RAM location that is the top of the stack Thus depending on the value of the stack pointer the stack can be located anywhere in the 256 bytes of RAM A common location would be in the upper 128 bytes of RAM as these are accessible through indirect addressing only 3 2 11 Working Registers The first 32 bytes of the Scratchpad RAM can be used as four banks of eight Working Registers for high speed data movement Using four banks software can quickly change context by simply changing to a different bank In addition to the Accumulator the working registers are commonly used as data source or destination Some of the working registers can also be used as pointers to other RAM locations indirect addressing 3 2 12 Program Counter
246. second write to TA register three machine cycles three machine cycles two machine cycle two machine cycles MOV 0C7h 0AAh MOV 0C7h 558 SETB EWT SETB EWT Modification of second protected bit did not complete within 3 cycles of second write to TA register INVALID TIMED ACCESS PROCEDURES 13 3 Timed Access Protects Watchdog Any microcontroller based system can be faced with environmental conditions that are beyond its designed abilities These include external signal transients due to component failure fluctuating power conditions massive electrostatic discharge ESD and other unexpected system events When a microcontroller is exposed to such conditions program execution can become corrupted Members of the high speed microcontroller family that incorporate a watchdog timer can initiate a reset to recover from these conditions The primary function of the timed access feature is to protect against accidental disabling of the watchdog timer by an out of control device This allows the watchdog timer to reset the system in the event of program execution failure The following hypothetical example demonstrates how a single bit change can corrupt program execution The timed access procedure protects against an accidental write to the EWT bit by the errant code allowing the watchdog timer reset function to reset the device While this is a purely fictitious example it illustrates how the watchdog timer and timed access featur
247. sidered See Section 16 for information on instruction timing Table 7 B Crystal vs MIPS Comparison ORIGINAL 8051 HIGH SPEED CRYSTAL SPEED MIPS MICROCONTROLLER MHz CRYSTAL SPEED MHz 3 57 0 3 1 4 7 37 0 6 2 0 11 0592 0 9 4 4 14 318 12 2 1 16 1 3 6 4 20 1 6 8 0 24 2 0 9 6 33 2 7 132 40 33 16 73 Power Management Modes Power consumption in CMOS microcontrollers is a function of operating frequency The Power Management Mode feature available with some members of the high speed microcontroller family allows software to dynamically match operating frequency and current consumption with the need for processing power Instead of the default 4 clocks per machine cycle power management mode 1 and power management mode 2 PMM2 utilize 64 and 1024 clocks per cycle respectively to conserve power A number of special features have been added to enhance the function of the power management modes The switchback feature allows the device to almost instantaneously return to divide by 4 mode upon acknowledgment of an external interrupt or a falling edge on a serial port receiver pin The advantages of this become apparent when one calculates the increased interrupt service time of a device operating in PMM In addition a device operating in PMM would normally be unable to sample an incoming serial transmission to properly receive it The switchback feature explained below
248. sing the 16 bit timers Software that uses the watchdog as a wake up alarm should only enable the watchdog interrupt and not the reset Note that the watchdog cannot be used to wake the system while in Stop mode since no clocks are running Stop mode is described below 7 1 6 Power Management Summary The following is a summary of the power management bits and those that are useful or related They are contained in the register locations WDCON D8h EIE E8h EXIF 91h and PCON 87h WDCON 6 Power On Reset POR Hardware will set this bit on a power up condition Software can read it but must clear it manually This bit assists software in determining the cause of a reset WDCON 5 Enable Power Fail Interrupt EPFI Setting this bit to 1 enables the power fail interrupt This will occur when Vcc drops to approximately 4 5V and the processor vectors to location 33h Setting this bit to a 0 turns off the power fail interrupt WDCON 4 Power Fail Interrupt Flag PFI Hardware will set this bit to a 1 when a power fail condition occurs Software must clear the bit manually Writing a 1 to this bit will force an interrupt if enabled WDCON 3 Watchdog Interrupt Flag WDIF If the watchdog interrupt is enabled EIE 4 hardware will set this bit to indicate that the Watchdog Interrupt has occurred If the interrupt is not enabled this bit indicates that the timeout has passed If the watchdog reset is enabled WDCON 1 the user has 512 cloc
249. st be followed by a two machine cycle delay such as executing two NOP instructions before jumping to the new address range Interrupts must be disabled during this operation because a jump to the interrupt vector during the changing of the memory map can cause erratic results In addition modification of the ROMSIZE register must be done from a location that will be valid both before and after the on chip memory configuration If off chip memory access 15 planned it is recommended that ports 0 and 2 not be used as general purpose as their state will be disturbed by the memory operations The settings for the ROMSIZE register are shown in Table 6 B Note that the memory configurations shown are not available on all devices 030308 77 of 175 High Speed Microcontroller User s Guide Table 6 B ROMSIZE Register Settings MAX ON CHIP ROM RMS2 RMS1 RMSO kB 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 4 1 0 0 8 1 0 1 16 1 1 0 32 1 1 1 64 After reset device with internal program memory will reset the ROMSIZE bits to their default setting This will be the maximum amount of on chip memory for that device The procedure to reconfigure the amount of on chip memory is as follows 1 Jump to a location in program memory that will be unaffected by the change 2 Disable interrupts by clearing the EA bit IE 7 3 Write AAh to the Timed Access Register TA C7h 4 Write 55h to the Timed Ac
250. stals are specified to operate from their third overtone When used with a high speed microcontroller these crystals will resonate in their primary mode which appear to be one third of the rated crystal speed Make sure that any crystals used operate at their rated speed in primary mode 17 2 Device Resets for No Reason During the debugging process it may be necessary to isolate the cause of an unexpected device reset Because resets are initiated by a limited number of sources it is relatively easy to determine their source by interrogating a few bits These bits should be interrogated early in the code following a reset to determine its source As a debug tool software could set the state of one or more port pins to indicate the type of reset to the designer Note that power supply problems or glitches appear as unplanned power on resets POR BIT WTRF BIT SOURCE WDCON 6 WDCON 3 Power On Reset 1 0 Watchdog Reset 0 1 External Reset 0 0 17 3 Access to Internal MOVX SRAM Is Unsuccessful The internal MOVX SRAM available on some members of the high speed microcontroller family is disabled after any reset To enable the on chip SRAM the software should configure the data memory enable bits PMR 1 0 as needed When Vcc drops below access to the SRAM is disabled to prevent corruption of the data If the battery voltage is greater than this means that the processor can continue to operate while
251. struction cycle timing On the DS8xC520 and DS8xC530 Timer 0 will use a divide by 4 of the crystal frequency if Timer 0 15 configured in mode 3 regardless of the setting of this bit This bit functions normally if Timer 0 is configured for any mode other than mode 3 0 Timer 0 uses a divide by 12 of the crystal frequency 1 Timer 0 uses a divide by 4 of the crystal frequency Stretch MOVX Select 2 0 These bits select the time by which external MOVX cycles are to be stretched This allows slower memory or peripherals to be accessed without using ports or manual software intervention The RD or WR strobe will be stretched by the specified interval which will be transparent to the software except for the increased time to execute to MOVX instruction All internal MOVX instructions on devices containing MOVX SRAM are performed at the two machine cycle rate MD2 MD1 MD0 STRETCH VALUE MOVX DURATION 0 0 0 0 Machine Cycles Machine Cycles reset default Machine Cycles Machine Cycles Machine Cycles Machine Cycles Machine Cycles ol WO Oo I Machine Cycles 31 of 175 High Speed Microcontroller User s Guide 4 2 16 SFR 90h Port 1 P1 7 6 5 4 3 2 1 0 17 1 6 1 5 P1 4 P13 P1 2 P1 1 P1 0 INT5 INT4 INT3 INT2 TXDI RXDI T2EX
252. sult of the instruction These are the MOVX instructions An example is as follows MOVX DPTR A FOh The second cycle in this instruction is the write to data memory at the address pointed to by the data pointer Thus this instruction is a two cycle one byte instruction but requires two memory accesses The timing 15 a special case since the user can control it with the Stretch MOVX feature The timing for the Stretch MOVX is discussed in Section 6 Memory Access Figure 5 3 Single Cycle Instruction Timing 4 SINGLE CYCLE gt C1 C2 C3 C4 PSEN RETURN DATA PORT2 gt ADDRESS 15 8 Shaded areas are held a weak latch on the port until overdriven 030308 66 of 175 High Speed Microcontroller User s Guide Figure 5 4 Two Cycle Instruction Timing xample ANL A direct 55h addr7 0 INSTRUCTION FETCH OPERAND FETCH SINGLE CYCLE gt lt SINGLE CYCLE C1 c2 C4 C1 C2 c3 C4 PSEN ADO 7 DATA AND ADDRESS 7 0 PORT2 D ADDRESS A15 A8 AD ADDRESS A15 A8 Shaded areas are held in a weak latch on the port until overdriven 5 6 3 Three Cycle Instructions Three cycle instructions come in two varieties The first requires three memory accesses These are similar to one and two cycle instructions in that the number of bytes equals the number of cycles The second variety is a three cycle instruction that simply requires 12 clocks to perform the function
253. t Port data Execution Note 1 Port exhibits op code following instruction that sets the STOP bit Port 0 is operating in true bidirectional mode and will drive both a logic 1 and a logic 0 Note 2 Port reflects data stored in corresponding port SFR Port 0 functions as an open drain output in this mode Note 3 Port exhibits address MSB of op code following instruction that sets the STOP bit Note 4 Port reflects data stored in corresponding port SFR In this mode the port uses weak pullups If a bit in the P2 SFR is a 1 the corresponding device pin will transition slowly to a high when the reset state is entered 7 2 3 Ring Oscillator Wake Up from Stop A typical low power application method is to keep the processor in Stop mode most of the time Periodically the system will wake up using an external interrupt take a reading of some condition then return to sleep The duration of full power operation is as short as possible One disadvantage to this method is that the clock must be restarted prior to performing a meaningful operation This startup period is a waste of time and power since no work can be performed The high speed microcontroller provides an alternative If the Ring Select RGSL is enabled the high speed microcontroller can exit Stop mode running from an internal Ring Oscillator Upon receipt of an interrupt this oscillator can start instantaneously allowing software execution to begin immediately while the osc
254. t p of EE SADDRO LSADRI L JE SADNO 5 spuri Cl STATUIS o 1 1 1 1 1 Lp 31 1 1 _ gt ah CON Doe qoo 4 o o 0 WDCON 0 SPECIAL 0 SPECIAL 0 SPECIAL SPECIAL 0 0 NN 030308 20 of 175 High Speed Microcontroller User s Guide Table 4 D883C520 DS87C520 SFR Locations Po Poe pos Pol Poo son omi bms mis bens DPHI pemo f eh DPLI DPHI DPS A PCON SMOD om STOP me sm TCON mo Gare CT m
255. t power state Since the bandgap is inactive there can be no power fail interrupt and no power fail reset similar to a traditional 8051 If the use of the power fail features are desired in Stop mode the BGS bit EXIF 91h may be used When set to a logic 1 by software the bandgap reference and associated power monitor circuits will remain active in Stop mode The price of this feature 15 higher power supply current requirements BGS allows the user to decide whether the control circuitry and its associated power consumption are needed If the application is such that power will not fail while in Stop or if it does not matter that power fails the BGS should be set to 0 default If power can fail at any time and cause problems the BGS should be set to 1 030308 89 of 175 High Speed Microcontroller User s Guide Figure 7 1 Power Cycle Operation INTERRUPT SERVICE ROUTINE INTERNAL RESET 030308 90 of 175 High Speed Microcontroller User s Guide 7 1 5 Watchdog Wake Up The watchdog wake up is more of an application than a feature It allows a system to enter the Idle mode for power savings then to wake up periodically to sample the external world Idle mode is a low power state described below Any of the programmable timers can perform this function but the watchdog allows a much longer period to be selected At 12MHz the maximum watchdog timeout is over 5 5 seconds This contrasts with 0 78 seconds u
256. t clock line TXD used for communication The shift clock is used to shift data into and out of the microcontroller and the remote device Mode 0 requires that the microcontroller 15 the master because the microcontroller generates the serial shift clocks for both directions As described above the shift clock may be selected to be either divide by 12 or divide by 4 of the oscillator as determined by the SM2 SCONO 5 or SCONI 5 bit 030308 143 of 175 High Speed Microcontroller User s Guide Figure 12 1 Serial Port Mode 0 OUTPUT SHIFT REGISTER P3 0 Q C aooodaoaaonao DIVIDE DIVIDE BY 12 BY4 0 1 LDSBUF DATA BUS SM2 SCONx 5 RDSBUF SHIFT READ SERIAL RD RECEIVE DATA BUFFER WR BUFFER SERIAL I O CONTROL RECEIVE BUFFER LOAD RECEIVE SHIFT REGISTER SERIAL TXD INTERRUPT PIN TRANSMIT TIMING LDSBUF WRITE TO SBUF SHIFT RXD DATA OUT Do Dt X 05 06 TXD DATA CLOCK TI RECEIVE TIMING RDSBUF WRITE TO SCON CLEAR RI SHIFT P 51 DATA CLOCK ER os 030308 144 of 175 High Speed Microcontroller User s Guide The signal is used for both transmission and reception TXD provides the shift clock Data bits enter and exit LSb first The baud rate 15 equal
257. t mode is used Bit 0 Capture Reload Flag CP RL2 When this bit is set to 1 Timer 2 captures will occur on 1 to 0 transitions of T2EX P1 1 if EXEN2 1 When this bit is set to 0 auto reloads will occur when Timer 2 overflows or when 1 to 0 transitions occur on if EXEN2 1 If either RCLK or TCLK is set toa 1 this bit will not function and the timer will function in an auto reload mode following each overflow 030308 124 of 175 High Speed Microcontroller User s Guide 11 6 2 Timer Two Mode Control Register T2MOD Summary 7 6 5 4 3 2 1 0 T2MOD C9h 2 DCEN Bit 1 Timer 2 Output Enable T2OE Setting this bit to a 1 enables the Timer 2 to drive the T2 P1 0 pin with a clock output When T2OE 0 the T2 P1 0 pin 1 used as either an input for Timer 2 or a standard port pin Bit 0 Down Count Enable DCEN When this bit is set to 1 the Timer 2 function counts up or down when in 16 bit auto reload mode depending on T2EX 1 1 When is set to a 0 the Timer 2 counts up only 11 6 3 Timer 2 Capture Registers RCAP2L RCAP2H Summary 11 6 3 1 Least Significant Byte Capture of Timer 2 RCAP2L 7 6 5 4 3 2 1 0 RCAP2L CAh RACP2L7 RACP2L6 RCAP2L5 RCAP2IA RCAP2L3 RCAP2L2 RCAP2L1 RCAP2L0 Bits 7 to 0 Timer 2 Capture LSB RACP2L 7 0 This register is used to capture the TL2 value when Timer 2 is configured in c
258. tal Instructions Two Cycle Two Bytes X1 5 27 1 5 Total Instructions Two cycle Two Bytes X3 0 11 3 0 Total Instructions Three Cycle One Byte 4 2 0 Total Instructions Three Cycle Two Bytes 8 2 0 Total Instructions Three Cycle Three Bytes 7 2 0 Total Instructions Four Cycle One Byte 2 1 5 Total Instructions Four Cycle Three Bytes 9 1 5 Total Instructions Five Cycle One Byte 2 24 Average Across Instructions 111 2 3 INSTRUCTION CATEGORY QUANTITY SPEED ADVANTAGE Total Op Codes One Cycle One Byte 126 3 0 Total Op Codes Two Cycle One Byte 6 3 0 Total Op Codes Two Cycle Two Bytes X1 5 35 1 5 Total Op Codes Two Cycle Two Bytes X3 0 27 3 0 Total Op Codes Three Cycle One Byte 4 2 0 Total Op Codes Three Cycle Two Bytes 29 2 0 Total Op Codes Three Cycle Three Bytes 7 2 0 Total Op Codes Four Cycle One Byte 2 1 5 Total Op Codes Four Cycle Three Bytes 17 1 5 Total Op Codes Five Cycle One Byte 2 2 4 Average Across Instructions 255 2 5 Rev 030308 75 of 175 High Speed Microcontroller User s Guide 6 MEMORY ACCESS The high speed microcontroller follows the memory interface convention established for the industry standard 80C51 80C31 Products in the family may vary so refer to the specific product data sheet for any potential differences Like the 8051 series the high speed microcontroller uses two memory segments These are program memory and data memory Program memory is read only and is usually implement
259. tate This bit defines the state of the 9th transmission bit in serial Bit 3 port 1 modes 2 and 3 8 1 9th Received Bit State This bit identifies the state for the 9th reception bit received data in Bit 2 serial pot 1 modes 2 and 3 In serial port mode 1 when SM2 1 0 8 1 is the state of the stop bit RB8 1 is not used in mode 0 TI 1 Transmitter Interrupt Flag This bit indicates that data in the serial port 1 buffer has been Bitl completely shifted out In serial port mode 0 TI 1 is set at the end of the 8th data bit In all other modes this bit is set at the end of the last data bit This bit must be manually cleared by software RI 1 Receiver Interrupt Flag This bit indicates that a byte of data has been received in the Bit 0 serial port 1 buffer In serial port mode 1 RI 1 is set at the end of the 8th bit In serial port mode 1 RI 1 is set after the last sample of the incoming stop bit subject to the state of 5 2 1 In modes 2 and 3 RI 1 is set after the last sample of 8 1 This bit must be manually cleared by software 4 2 30 Serial Data Buffer 1 SBUF1 7 6 5 4 3 2 1 0 SBUFI 7 SBUFI 6 SBUFI 5 SBUFI 4 SBUFI 3 SBUFI 2 SBUF1 1 SBUF1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset SBUF1 7 SBUF1 0 Bits 7 0 Rev 030308 Serial Data Buffer 1 Data for serial port 1 is read from or written to this location The serial transmit and
260. ter Indirect Addressing with Displacement Relative Addressing Page Addressing Extended Addressing Five of the eight are used to address operands The remaining are used for program control and branching When writing assembly language instructions that use arguments the convention is destination source Each mode of addressing is summarized below Note that many instructions such as ADD have multiple addressing modes available 4 4 1 Register Addressing Register Addressing is used for operands that are located in one of the eight Working Registers R7 RO These are the currently selected Working Register bank which reside in the lower 32 bytes of Scratchpad RAM A register bank is selected using two bits in the Program Status Word PSW DOh This addressing mode is powerful since it uses the active bank without knowing which bank is selected Thus one instruction can have multiple uses by simply switching banks Register Addressing is also a high speed instruction requiring only one machine cycle Two examples of Register Addressing are provided below ADD A R4 Add Accumulator to register R4 INC R2 Increment the value in register R2 In the first case the value in R4 15 the source of the operation In the later R2 is the destination These instructions do not consider the absolute address of the register They will act on whichever bank has been selected Direct Addressing described below may also access any Working Register
261. ternal Program Memory Some members of the high speed microcontroller family incorporate internal EPROM or ROM for program storage On chip program memory begins at address 0000h and is contiguous through the amount of on chip memory Exceeding the maximum address of on chip memory causes the device to perform an external memory access using the Expanded memory bus on ports 0 and 2 For example if the on chip program memory is 16kB then it lies between 0000h and 3FFFh in a contiguous area Therefore a fetch at data memory location 4000h would be directed to the Expanded bus Restricting memory operations within the on chip memory allows ports 0 and 2 to be used for general purpose I O For more information concerning memory size for a specific device consult the specific data sheet The high speed microcontroller family was designed to be compatible with industry standard 87C51FB programming tools A number of third party device programmers are available that support Maxim products 6 2 Internal Data Memory Some members of the high speed microcontroller family incorporate internal SRAM for additional data storage This memory is addressed via MOVX commands and is in addition to the 256 bytes of scratchpad memory On chip data memory begins at address 0000h and is contiguous through the amount of on chip memory Exceeding the maximum address of on chip memory will cause the device to perform an external memory access using the Expanded memory bus o
262. til gt As rises above Vast internal analog circuits will detect this and activate the on chip crystal oscillator On chip hardware will then count 65 536 oscillator clocks During this count Vcc must remain above or the process restarts If an off chip clock source is used clock counting still begins once Vcc gt This count period is used to make certain that power 1 within tolerance and that the oscillator has time to stabilize This provides a very controlled and predictable startup condition Once the 65 536 count period has elapsed the reset condition is removed automatically and software execution will begin at the reset vector location of 0000h Software will be able to detect the power on reset condition using the power on reset POR flag POR is located at WDCON 6 This bit will be high to indicate that a power on reset has occurred It should then be cleared by software The complete power cycle operation is shown in Figure 7 1 Note that the interrupt threshold is fixed but the interrupt itself is optional Reset thresholds are also fixed and the reset operation is transparent It requires no external components and no action by software to control reset operation 7 1 4 Bandgap Select When present the bandgap reference will provide a precise voltage reference for the power fail monitor circuitry The bandgap is normally disabled automatically upon entering Stop mode to provide the lowes
263. tion is desired it must be enabled following battery application 0 oscillator is disabled 1 oscillator is enabled 4 2 52 Real Time Clock Subsecond Register RTCSS 7 6 5 4 3 2 1 0 RTCSS 7 RTCSS 6 RTCSS 5 RTCSS 4 RTCSS 3 RTCSS 2 RTCSS 1 RTCSS 0 R R R R R R R R R Unrestricted Read W Unrestricted Write n Value after Reset See Description RTCSS 7 RTCSS 0 Real Time Clock Subseconds This register represents the subsecond value of the Bits 7 0 It can be read only when the RTCRE bit is set and writes are not permitted It 15 reset to 00h when the RTCWE bit is cleared The register counts from Oh to FFh 030308 56 of 175 High Speed Microcontroller User s Guide 4 2 53 Real Time Clock Second Register RTCS 7 6 5 4 3 2 1 0 SFR FBh 0 0 RTCS 5 RTCS4 RTCS3 RTCS2 RTCS 1 0 0 0 R Ww R Ww R W R Unrestricted Read W Unrestricted Write n Value after Reset See Description Bits 7 6 RTCS 5 RTCS 0 Bits 5 0 4 2 54 SFR FCh Reserved These bits will be 0 when read Real Time Clock Seconds This register represents the second value of the RTC This register can be read only when the RTCRE bit is set and can only be modified when the RTCWE bit is set Consult the description of the RTCWE bit for the p
264. ture of the ring oscillator but still have the capability of quickly switching back to the external crystal to perform timing or serial port operations Switching from the ring oscillator to the crystal oscillator is more involved due to the startup delays inherent in the external crystal To prevent an accidental disabling of the device the XTUP bit must be set by internal hardware indicating an enabled stable crystal before setting the XT RG bit The procedure to switch to the crystal oscillator when running from the ring oscillator is as follows 1 Clear the crystal oscillator disable bit XTOFF 3 to restart the crystal oscillator and start the crystal warmup period 2 Wait for the crystal oscillator warmup status bit XTUP STATUS 4 to be set indicating that the external crystal warmup period is complete This will take 65 536 external clock cycles 3 Set the crystal oscillator ring oscillator select bit XT RG EXIF 3 to select the crystal as the clock source 030308 101 of 175 High Speed Microcontroller User s Guide 8 RESET CONDITIONS The high speed microcontroller provides several ways to place the CPU in a reset state It also offers the means for software to determine the cause of a reset The reset state of most processor bits is not dependent on the type of reset but selected bits do depend on the reset source The reset sources and the reset state are described below 8 1 Reset Sources High spe
265. ummary NAME LOCATION FUNCTION RANGE RESET READ WRITE ACCESS ERTCI EIE 5 RTC Interrupt Enable 0 Unrestricted PRTCI EIP 5 RTC Interrupt Priority 0 Unrestricted RTASS 7 0 RTASS RTC Alarm Subsecond 0 FFh Unchanged Unrestricted RTAS 5 0 RTAS RTC Alarm Second 0 3Bh Unchanged Unrestricted RTAM 5 0 RTAM RTC Alarm Minute 0 3Bh Unchanged Unrestricted RTAH 4 0 RTAH RTC Alarm Hour 0 17H Unchanged Unrestricted Read only if RTCRE 1 RTCSS 7 0 RTCSS RTC Subsecond 0 FFh Unchanged Cannot be written Cleared when RTCWE 1 gt 0 RTCS 5 0 RTCS RTC Second 0 3Bh Unchanged RTCM 5 0 RTCM RTC Minute 0 3Bh Unchanged Read only if RTCRE 1 4 0 4 0 Hour 0 17 Unchanged Write only if RTCWE 1 DOW 2 0 RTCH 7 5 RTC Day of Week 0 7h Unchanged 1 95118 Read Write window RTCD1 7 0 RTCDI MSB RTCD0 7 0 RTCDO LSB RTC Day O FFFFh Unchanged SRCE RTCC 7 Rud Unchanged Unrestricted Compare Enable SCE RTCC 6 Unchanged Unrestricted Enable MCE RTCC 5 dd Unchanged Unrestricted Enable HCE 4 Hour Compare Unchanged Unrestricted Enable RTCRE 3 Read Enable 0 Unrestricted Read Unrestricted RTCWE RTCC 2 RTC Write Enable 0 Write Timed Access RTCIF RTCC 1 RTC Interrupt Flag Unchanged Unrestricted RTCE RTCC 0 RTC Enable Unchanged E4K TRIM 7 P ERIE 0 Read Unrestricted Si
266. upt 4 1 Enable interrupt requests generated by the INT4 pin External Interrupt 3 Enable This bit enables disables external interrupt 3 0 Disable external interrupt 3 1 Enable interrupt requests generated by the INT3 pin External Interrupt 2 Enable This bit enables disables external interrupt 2 0 Disable external interrupt 2 1 Enable interrupt requests generated by the INT2 pin B Register B 7 6 5 4 3 2 1 0 B 7 B 6 5 4 B 3 B 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 B Register This register serves as a second accumulator for certain arithmetic operations It is functionally identical to the B register found in the 80C32 Real Time Alarm Subsecond Register RTASS 7 6 5 4 3 2 1 0 RTASS 7 RTASS 6 RTASS 5 RTASS 4 RTASS 3 RTASS2 RTASS 1 RTASS O RW RW RW RW RW RW RW RW Unrestricted Read W Unrestricted Write n Value after Reset See description RTASS 7 RTASS 0 Bits 7 0 030308 Real Time Alarm Subsecond These bits represent the subsecond alarm which will be compared against the RTC Subsecond register RTCSS FAh The ability of a match between the two registers to cause an alarm is controlled by the RTC Subsecond Register Compare Enable bit RTCC 7 The contents of this register will be indeterminate following a no battery reset and unchanged by all other forms of reset
267. utput on port pin P1 0 T2 as shown in Figure 11 7 To configure Timer 2 for this mode first it must be set to 16 bit auto reload timer mode CP RL2 0 0 Next T2OE T2MOD 1 bit must set to logic 1 TR2 T2CON 2 must also be set to a logic 1 to enable the timer This mode will produce a 50 duty cycle square wave output The frequency of the square wave is given by the formula in the figure Each timer overflow causes an edge transition on the pin i e the state of the pin toggles Note that this mode has two somewhat unique features in common with the baud rate generation mode First the time base is the crystal frequency divided by 2 and no other divider selection is possible Second the timer itself will not generate an interrupt but if needed an additional external interrupt may be caused using T2EX as described above Because of the two mode s similarities the timer can be used to generate both an external clock and a baud rate clock simultaneously Once the clock out mode is established either TCLK or RCLK is set to 1 and the RCAP2 registers are loaded the timer will provide a clock to both functions 030308 130 of 175 High Speed Microcontroller User s Guide Figure 11 7 Timer Counter 2 Clock Out Mode OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC 2 1 OSC 32 2 OSC 512 F_OUT BE RCAP2L RCAP2H OSC INPUT TO TIMER RCAP2L T2MOD 1 2 P1 1
268. with Timer 1 which uses only 8 bits OscillatorFrequency Mode 1 3 Baud Rate 32 x 65 536 RCAP2H RCAP2L Note that the 32 in the denominator is a result of the timer being run at a divide by 2 combined with the divide by 16 applied to timer overflows as mentioned above Timer 2 normally runs at a divide by either 12 or 4 in auto reload mode Setting RCLK or TCLK causes the divide by 2 operation This formula provides the derived baud rate for a given RCAP2H RCAP2L and crystal Most users already know what baud rate is desired and want the timer reload value Thus the equation solves as follows Oscillator Frequency RCAP2H RCAP2L 65 536 32 x Baud Rate The Timer 2 interrupt is automatically disabled when either RCLK or TCLK is set Also the TF2 TCON 7 flag will not be set on a timer rollover The manual reload pin T2EX P1 1 will not cause a reload either 030308 142 of 175 High Speed Microcontroller User s Guide 12 4 Serial Description A detailed description of each serial mode is given below A description of framing error detection and multiprocessor communication follows this section 12 4 1 Mode 0 This mode is used to communicate in synchronous half duplex format with devices that accept the high speed microcontroller as a master A functional block diagram and basic timing of this mode are shown in Figure 12 1 As can be seen there is one bidirectional data line RXD and one shif
269. with any zeros defined as don t cares In most cases the broadcast address will be FFh The broadcast address feature is not available on the DS8xC520 or the DS8xC530 Hev 030308 151 of 175 High Speed Microcontroller User s Guide The multiprocessor communication is always enabled However the SADEN registers default to 001 which means all address bits are don t care so all match Thus if no multiprocessor communication is used these registers can be ignored 030308 152 of 175 High Speed Microcontroller User s Guide 13 TIMED ACCESS PROTECTION The high speed microcontroller uses a protection feature called timed access to prevent accidental writes to critical SFR bits These bits could cause a system failure or prevent the watchdog timer from doing its job if improperly written The timed access involves opening a timing window during which the protected bit can be modified If the window is opened correctly it remains open long enough to alter one protected bit This section explains which bits are protected why and how to use the timed access feature 13 1 Protected Bits Bits that are protected by the timed access feature are shown below Only critical function bits that are unique to the high speed microcontroller family are protected assuring code compatibility with the original 80C51 or 80C52 A full description of the function of each bit 1 provided in Section 4 EXIF 0 BGS Bandgap Select WDCON 6 P
270. wn below plus 512 clocks Watchdog generated resets will last for two machine cycles WATCHDOG NUMBER TIMEAT TIME AT TIME AT TIME AT TIME AT WDI WDO INTERVAL OF 1 8432MHz 11 0592MHz 16MHz 20MHz 25MHz CLOCKS ms ms ms ms ms 0 0 2H 131 072 71 11 11 85 8 19 6 55 5 24 0 1 229 1 048 576 568 89 94 81 65 54 52 43 41 94 1 0 23 8 388 608 4551 11 758 52 524 29 419 43 335 54 1 1 2 67 108 864 36408 88 6068 15 4194 30 3355 44 2684 35 watchdog timeout selection is made using bits CKCON 7 and WDO CKCON 6 as shown in the table The timeout selections possible are shown in the bit descriptions that follow The watchdog timeout period is affected by the use of power management modes The slower clock rate either divide 030308 133 of 175 High Speed Microcontroller User s Guide by 64 or divide by 1024 is used as the input source for the watchdog timer This allows the watchdog period to remain synchronized with device operation As discussed the watchdog timer has several SFR bits that contribute to its operation It can be enabled to function as either a reset source interrupt source software polled timer or any combination of the three Both the reset and interrupt have status flags The watchdog also has a bit that restarts the timer A summary table showing the bit locations is below A description follows NAME DESCRIPTIO
271. would be treated as such The resulting fetch is the value C2 D9 This 15 the op code for CLR D9h The bit addressable location D9h corresponds to the EWT If the timed access procedure did not prevent it this errant instruction would disable the watchdog Note that now the program execution is completely lost Real op codes are being replaced by operands data and garbage In the high speed microcontroller the watchdog will recover from this state as soon as it times out since it could not have been disabled in this way In the high speed microcontroller it is very hard to contrive a situation that will accidentally disable the watchdog Note that the timed access prevents accidentally writing a bit It cannot prevent accidentally calling the correct code that writes a bit This is much more unlikely however 030308 155 of 175 High Speed Microcontroller User s Guide 14 REAL TIME CLOCK The DS87C530 incorporates a real time clock onto the high speed microcontroller family core This allows the device to perform real time related functions such as data logging and timestamping without an external timer In addition the RTC includes an alarm function that can execute a software interrupt or resume operation from Stop mode at a specified time The RTC features are controlled by 12 new SFRs These registers as well as two new interrupt control bits are shown in Table 14 A Table 14 A Real Time Clock Control and Status Bit S
272. y servicing a low priority interrupt It is cleared when the program executes the corresponding RETI instruction Crystal Oscillator Warmup Status This bit indicates whether the CPU crystal oscillator has completed the 65 536 cycle warmup and is ready to operate from the external crystal or oscillator This bit 18 cleared each time the crystal oscillator is restarted following an exit from Stop mode or the XTOFF bit PMR 3 is set While cleared this bit prevents software from setting the XT RG bit EXIF 3 to enable operation from the crystal Note that XTUP differs from the RGMD bit EXIF 2 in that XTUP shows the status of the crystal while RGMD shows the current clock source This bit is set to 1 following a power on reset but is unaffected by other forms of reset Serial Port 1 Transmit Activity Monitor When set this bit indicates that data 15 currently being transmitted by serial port 1 It is cleared when the internal hardware sets the TI 1 bit Do not alter the Clock Divide Control bits PMR 7 6 while this bit is set or serial port data may be lost On the DS8xC520 and DS8xC530 this bit does not accurately indicate serial port 1 transmit activity if a character is written to SBUF1 while TI 1 is high If software intends to poll this bit first clear the 1 bit before writing each character to SBUFI Serial Port 1 Receive Activity Monitor When set this bit indicates that data is currently being received by serial port 1 It is clea
273. ystal capacitance select bit TRIM 6 determines the crystal selection The default state of this bit after a no battery reset is for a 12 5pF crystal In general a lower capacitance crystal will consume less power but will be more susceptible to noise Unlike the processor crystal inputs X1 X2 the RTC crystal does not require external load capacitors Placing load capacitors on the RTC crystal input pins will cause the RTC to keep incorrect time To prevent system noise from affecting the the RTCX1 and RTCX2 pins should be guard ringed with the GND2 signal 030308 159 of 175 High Speed Microcontroller User s Guide 14 6 Calibrating the RTC Oscillator Although the DS87C530 RTC accuracy is guaranteed for 2 minutes month users may occasionally require greater accuracy The RTC incorporates the ability to adjust the internal capacitance of the crystal amplifier via the RTC Trim Bits TRM2 TRMO and TRM2 TRMO This allows the user to more accurately match the capacitance of the crystal amplifier to the crystal Note that under most circumstances no adjustment of the RTC crystal capacitance is necessary as it will default to a minimum accuracy of 2 minutes per month of the crystal capacitance controls are located in the trim register TRIM 96h Setting the 4 bit will enable the output of a 4096Hz signal on P1 7 This signal is derived from a divide by 8 of the 32 768kHz crystal Because this i
274. yte2 0 0 0 0 0 1 0 0 04 1 1 1 Rn 0 0 0 0 m n ng 08 0F 1 1 Rn 1 INC direct 0 0 0 0 0 1 0 1 05 2 2 direct direct 1 lt 46 a Byte 2 INC Ri 0 0 0 0 0 1 1 1 06 07 1 1 Ri Ri 1 INC DPTR 1 0 1 0 0 0 1 1 1 3 DPTR DPTR 1 DEC A 0 0 0 1 0 1 0 0 14 1 1 1 DEC Rn 0 0 0 1 n m 18 1 1 Rn Rn 1 DEC direct 0 0 0 1 0 1 0 1 15 2 2 direct direct 1 a Byte2 DEC 0 0 0 1 0 1 1 1 16 17 1 RD 1 MUL AB 1 0 1 0 0 1 0 0 4 1 5 A X B DIV AB 1 0 0 0 0 1 0 0 84 1 5 A B 030308 163 of 175 High Speed Microcontroller User s Guide INSTRUCTION CODE MNEMONIC D D D Ds D D HEX BYTE CYCLE EXPLANATION DAA 1 1 0 1 0 1 0 0 D4 1 1 Contents of Accumulator BCD IF gt 9 OR 1 THEN E 6 AND IF gt 9 OR C 1 THEN gt A74 A4 6 ANL A Rn 0 10 1 1 n n 58 5 1 1 A AND ANL A direct 0 1 0 1 0 10 1 55 2 2 AND direct Byte 2 ANL A Ri 0 1 0 1 0 1 1 i 56 57 1 1 AND R1 data 0 1 0 1 0 10 0 54 2 2 A A AND data d dg 5 d 4 d di do Byte 2 ANL di

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