ezLINX™ iCoupler® Isolated Interface
Contents
1. 4 3 14 VIA VOA JP37 Dk von 18 B voc vic H2 R23 VOD VID 33R 3 3V SPIOSEL2 pM nu ver ves i9 _ R24 33R 2 9 GND1 GND2 SPIOSEL3 SE 1 8 GNp1 GND2 A SPIOSS lt 4 x E ADuM3402 ey GND SPI_M_ISO_GND n 3 3V 3 3V SPI M ISO 3 3V SPI M ISO 3 3V JP21 C180 C182 C183 C181 0 1uF 0 1uF 0 1uF 0 1uF D l 8 E c ka Ka Nu GND GND GND SPI M ISO GND SPI M ISO GND 8 Figure 8 ADuM3401 ADuM3402 ADuM5000 Isolated SPI1 Implementation Rev 0 Page 10 of 20 UG 400 3 3V SPI S ISO 3 3V U25 1 10 e a viso Ae A VDD1 VISO 6 13 L RCSEL vseL 3 2 0 pen 3 RCOUT NC1 L n NC2 42 Wl neg 4X 2 GND1 anpiso 1 8 GND1 GNDISO 3 zx ADuM5000 GND SPI S ISO GND 3 3V SPI S ISO 3 3V 3 3V i i oeo 3 R108 C192 C191 C190 C195 C194 C193 10K 10uF O tuF Gut iOuF O iuF 0 1uF E 3 3V SPI S ISO 3 3V GND SPI S Iso0 GND JP38 u42 1 16 Gung CL von VDD2 33R JP22 J25 SPI2SCK lt lt Zu vi VOA H Wc x 1S 5 VIB V2. 4 GND1 GND2 les T ADuM1250 SCREW 3 E Dj 3 3V ND I2C ISO GND GC ISO 3 3V I2C ISO GND c172 C173 0 01uF 0 01uF GND I2C ISO GND 3 3V I2C ISO 3 3V U19 1 10 vDD1 viso 4g 1 vpp1 VISO 6 13 gt RCSEL VSEL gt 4 2X 5 RCIN 3 2 RCOUT NC1 131 NC2 L2 NC3 44 NA X 2 9 GND1 GNDISO His 4 GND1 GNDISO d ADuM5000 GND I2C ISO GND 3 3V I2C ISO 3 3V 4 e 9 34 C168 C167 C166 iOuF O iuF 0 1uF Ci71 C170 C169 10uF out 0 1uF E 5 GN 3 I2C ISO GND 8 Figure 7 ADuM1250 and ADuM5000 Isolated PC Implementation Rev 0 Page 8 of 20 ISOLATED SPI Two isolated SPI ports are implemented using the ADuM3401 the ADuM3402 iCoupler signal isolators and the ADuM5000 isoPower isolated dc to dc converter The isolated SPIO imple mentation on the ezLINX hardware uses the ADuM3401 The ADuM3401 connects to SPIO of the Blackfin ADSP BF548 and is used to isolate the SCLK MISO SSEL1 and MOST lines The ADuM3402 is used for isolating the SPI slave select lines Figure 8 shows a circuit diagram of the implementation of isolated SPI1 using the ADuM3401 ADuM3402 and ADuM5000 on the ezLINX hardware The isolated SPI2 implementation on the ezLINX hardware uses the ADuM3401 The ADuM3401 connects to SPI2 of the ADSP BF548 and is used to isolate the SCLK MISO SSEL1 and MOSI l
3. When the JP2 jumper is fitted it implements a loopback of the frequency switching elements to transfer power through the isolated RS 232 transmitter output Pin Tori to the receiver transformer Special care must be taken during PCB layout to input Pin Rm meet emissions standards Refer to the AN 0971 Application Note Recommendations for Control of Radiated Emissions with Th d Pin BL l i eps En A EA D A ea Soa isoPower Devices for details on board layout considerations are powered with 3 3 V and generate an isolated 3 3 V on the JP2 JUMPER J6 U44 18 D1 D11 UART3TX gt gt E gt TINI TOUT re 2 lt gt TIN2 TOUT2 X UARTSRX ei Rout mu __ ut Ki Kn 2 ROUT2 RIN2 WT caos SSES 0 1uF CH RS232 ISO GND C14 E11 en C126 0 1uF G11 C24 G10 3 3V e RS232 ISO 3 3V B1 A10 RQo VCC VISO 1 eg n2 vec viso Gig vec viso SL cii 0 1uF B11 Ve Tun V A c2 MI To Z C142 D2 GND NC2 X 0 1uF ji pn GND A11 t e GND DNC1 Fun X rp2 GND DNC2 RS232 ISO GND e GND T e CND D10 o GND GNDISO es jr GND GNDISO Ten T T 32 GND GNDISO Ho 4 T X2 GND GNDISO jg 9 T 12 GND GNDISO wan e GND GNDISO 119 GND GNDISO a ADM3252E GND RS232 ISO GND 3 3V RS232_ISO_3 3V e 4 C130 C
4. isoPower digital isolator technology The hardware of the ezLINX iCoupler isolated interface develop ment environment contains the ADSP BF548 Blackfin processor with 64 MB of RAM and 32 MB of flash memory The isolated physical layer communication standards are implemented using Analog Devices isolated transceivers with integrated iCoupler and isoPower technology Devices used to implement these isolated physical layer communication standards include the following e Isolated USB using the ADuM3160 PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS EZLINX IIIDE EBZ 10649 001 Io P TAUTA Figure 1 e Isolated CAN using the ADM3053 signal and power isolated CAN transceiver e Isolated RS 485 and RS 422 using the ADM2587E signal and power isolated RS 485 RS 422 transceiver e Isolated RS 232 using the ADM3252E signal and power isolated RS 232 transceiver e Isolated DC using the ADuM1250 and ADuM5000 e Isolated SPI using the ADuM3401 ADuM3402 and ADuM5000 e Isolated LVDS using the ADuM3442 ADuM5000 ADN4663 and ADN4664 This evaluation board contains multiple parts with isoPower technology which uses high frequency switching elements to transfer power through the transformer Special care must be taken during PCB layout to meet emissions standards See the AN 0971 Application Note Recommendations for Control of Radiated Emissions with isoPower Devices for board layout recommendations
5. 1 ADuM3442 H H RMK i 3o a x ROUT gt 1 1 7 vobi VISO e 1 GND LVDS ISO_GND RINI E VDD1 VISO 3 6 ouz 2 RNC 1 L 9 ResEL ven z 4 4 ZG RNZ K 4 RCIN 3 3V LVDS ISO 3 3V 1 ouer X 5 REDE wel 100R NG2 12 3 nea 14 T Our T Gaur LVDS ISO GND X A S Lv 2 oup enne ds GND1 GNDISO Nu ADuM5000 GND LVDS ISO GND G rd iOS ISO Sav GND LVDS ISO GND Wc 3 3V LVDS ISO 3 3V 1 e U29 ed 9 7 Ca C211 C210 C215 C214 C213 San 8 Poum S 10uF 0 1uF 0 tuF 10uF O1uF 0 1uF pour A DOUT2 6 GND LVDS_ISO_GND 3 DIN2 2 5 D Dour2 3 3V LVDS ISO 3 3V 2 ADNA4663 U27 16 3 3V LVDS ISO 3 3V 2 4 vDD1 VDD2 4 va DW ap LVDS ISO GND I T yee veo Eee a ma 3 TFS2 VIB VOB 6 13 KOE voc vci EE bum lc MESI RFS2 VOD VID e RCIN 3 LVDS ISO 3 3V 2 T RCOUT BEL L ves OR NC3 H2 R82 MGA x 9 100R GND2 co GND2 9 4 ES 5 2 2 GND1 eNpisQ Ze ADuM3442 fmouri S RINT GND1 GNDISO S 1 ADuM5000 LVDS ISO GND KAN S SZ 3 GND LVDS ISO GND 3 3V LVDS ISO 3 3V 2 nour 2 ES S if 3 3V LVDS ISO 3 3V 2 D mmh ADNA664 lt R81 nn gt 100R C208 C209 C218 C217 C216 C221 C220 C219 0 1uF 0 1uF LVDS_ISO_GND 10uF 0 1uF Out 10uF 0 1uF 0 1uF ES T t i br e GND LVDS ISO GND GND Lupi GND LVDS ISO 3 3V 1 LVDS ISO 3 3V 1 LVDS ISO 3 3V 2 LVDS ISO 3 3V 2 C198 C200 C201 C202 C203 C204 C205 0 1u
6. 236 C140 C237 0 1uF 10uF 0 1uF 10uF e C GND RS232 ISO GND 8 Figure 6 ADM3252E Isolated RS 232 Implementation Rev 0 Page 7 of 20 ISOLATED lC The isolated DC port is implemented using the ADuM1250 C isolator and the ADuM5000 isoPower isolated dc to dc converter The ADuM1250 connects to TWI1 of the ADSP BF548 and is capable of functioning at a maximum frequency of 1 MHz Figure 7 shows a circuit diagram of the implementation of the ADuM1250 and ADuM5000 on the ezLINX hardware The Von pin Pin 1 of the ADuM1250 and the Vpn pins Pin 1 and Pin 7 of the ADuM5000 are powered by 3 3 V The ADuM5000 generates an isolated 3 3 V which is used to supply power to the Von pin Pin 8 of the ADuM1250 A 3 pin screw terminal connector J22 is used for easy access to the SDA Pin 1 of J22 SCL Pin 2 of J22 and DC ISO GND Pin 3 of J22 signals The ADuM5000 contains isoPower technology that uses high frequency switching elements to transfer power through the transformer Special care must be taken during PCB layout to meet emissions standards See the AN 0971 Application Note Recommendations for Control of Radiated Emissions with isoPower Devices for board layout recommendations 3 3V I2C ISO 3 3V U18 R73 R74 1 8 em wens 120R gt 120R J22 2 7 R m mM Da ja TE SCL1 SCL1 SCL2 A 2
7. 3 3 V which is used to supply power to the Von pin Pin 16 of the ADuM3442 the Vcc pin Pin 1 of the ADN4663 and the Vcc pin Pin 8 of the ADN4664 A 32 pin header connector is used for easy access to the isolated LVDS signals The ADuMS000 contains isoPower technology that uses high frequency switching elements to transfer power through the transformer Special care must be taken during PCB layout to meet emissions standards See the AN 0971 Application Note Recommendations for Control of Radiated Emissions with isoPower Devices for board layout recommendations Rev 0 Page 12 of 20 LVDS ISO 3 3V 1 UG 400 us J24 2 Doum 1 2 DNI s 8 3 L DOUT1 7 5 9 10 3 a DOUT24 L 5 Hz 33 DIN2 S 5 154 DG DOUT2 17 3 3V LVDS ISO 3 3V 1 ADNA663 19 U26 m za 1 vppi vons 8 x L 54 S E LVDS ISO GND SECH DT2PR K VIA VOA DT2SE ME woe H Header 32 5 12 S DR2RRI voc vic DR2SE 5 vob vip ka j LVDS ISO 3 3V 1 m LVDS ISO_GND L VE ves 9 2 eup GND2 S Se NG QND2 15 U30 d S 3 3V Ss LVDS ISO 3 3V
8. 9 JP31 JP33 JP34 JP39 JP22 JP24 JP26 JP28 JP30 JP32 JP35 JP38 Warning JP20 and JP21 should never both be connected because doing so will create a short circuit between 3 3 V and GND Warning JP34 and JP35 should never both be connected because doing so will create a short circuit between 3 3 V and GND Rev 0 Page 19 of 20 NOTES C refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors ESD Caution A ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection ia circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support materials the Evaluation Board you are agreeing to be bound by the terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the Agreement This Agreement is made by and between you Customer and Ana
9. ANALOG DEVICES Hardware User Guide UG 400 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com ezLINX iCoupler Isolated Interface Development Environment FEATURES Plug and play system evaluation Easy evaluation of 8 isolated physical layer communication standards Open source hardware Open source software iCoupler and isoPower technology ADSP BF548 Blackfin processor running uClinux Sample PC application Sample embedded uClinux application 64 MB RAM 32 MB flash Extender connector for additional functionality APPLICATIONS Isolated interfaces EVALUATION KIT CONTENTS EZLINX IIIDE EBZ Power supply ezLINX software DVD USB A to mini USB B cable GENERAL DESCRIPTION The ezLINX iCoupler isolated interface development environment provides developers with a cost effective plug and play method for evaluating eight digitally isolated physical layer communication standards USB RS 422 RS 485 RS 232 CAN SPI PC and LVDS The Blackfin ADSP BF548 processor runs the uClinux operating system and allows for easy customi zation through the open source hardware and software platform Development time is significantly reduced for embedded designers and system architects who are designing and evaluating isolated communication standards The interfaces on ezLINX use Analog Devices Inc isolated transceivers with integrated iCoupler and
10. C7 C245 gt 220uF 4 7uF 0 01uF R4 255K A_GND P_GND P_GND P_GND P_GND GND A_GND w2 wi COPPER COPPER 4A 7 i A GND P_GND GND Figure 12 3 3 V Power Supply Rev 0 Page 14 of 20 1 2 V 2 5 V AND 5 V POWER SUPPLIES low dropout regulator is used to regulate the UNREG IN input A P channel MOSFET is used to regulate the 3 3 V input to Ibo V see Pigure 15 1 2 V see Figure 13 The ADP1706 linear regulator is used to regulate the 3 3 V input to 2 5 V see Figure 14 The ADP3335 3 3V vm D T U3 12V n 1 5 L3 M 2 6 i 10uH E 3 SE IR e a AYA 4 8 VROUT gt e e e j D4 R a e eS A HA FDS9431A ZHCS1000 TR 7 e9 S C1 Luci 100uF 100uF 10uF 0 1uF o e GND GND GND 8 Figure 13 1 2 V Power Supply 33V 25V TP6 U39 2 5V 3 5 T IN OUT e 4 6 ha IN OUT 2 1 7 ha gt EN SENS f S a GND ss 3j e Ca ADP1706 4 7uF ui C231 16233 10nF 4 7uF Kc gt z GND GND GND GND GND Figure 14 2 5 V Power Supply UNREG IN 5V O TP5 U38 5V e l e a IN OUT IN our o B e OUT S 4 5 5 GND NR OO C229 ADP3335 C230 1uF 1uF GND GND GND 8 Figure 15 5 V Power Supply Rev 0 Page 15 of 20 EXTENDER CONNECTOR shows the circuit implementation of the J23 and J26 extender connec
11. DR2 SPORT DRO DR3PRI X pg SPORT DR3 SPORT RSCLK RSCLK3 27 GND GND ki PPIO_FS1 Ge PAR FS PAR CLK PPIO_CLK X z5 PAR_FS3 PAR_FS2 PPIO_FS2 X p4 PAR A PAR A0 aa PAR A3 PAR A2 k 22 GND GND aT PAR_CS PAR_INT on PAR RD PAR WR PPIO Di 49 PAR Di PAR DO PPIO DO PPIO D3 4g PAR D PAR D2 PPIO D2 PPIO D5 17 PAR D5 PAR D4 PPIO D4 e 16 GND GND PPIO D7 15 PAR D7 PAR D6 PPIO D6 PPIO D 14 PAR D9 PAR D8 PPIO D8 PPIO D11 1g PAR Di PAR D10 PPIO D10 PPIO D13 12 PAR D13 PAR D12 PPIO D12 PPIO D14 q1 PAR D GND bi 10 GND PAR D15 PPIO D15 PPIO D17 9 PAR D17 PAR D16 PPIO D16 PPIO D19 a PAR Di9 PAR D18 PPIO D18 PPIO D21 7 PAR_D21 PAR D20 PPIO D20 3 3V PPIO D23 e PAR D23 PAR D22 115 PPIO D22 k 5 GND GND Ce 3 USB VBUS VIO 43 3V 417 3 GND GND 19 2 GND GND 449 i X NC NC15 120 lt lt VIN NCi6 HIROSE i E GND GND Figure 16 Extender Connector Using Hirose FX8 120P SV 91 Rev 0 Page 16 of 20 RS 232 CONSOLE DB 9 connector J4 A circuit implementation of the RS 232 The RS 232 console connector is used for accessing the console SEET of the uClinux kernel running on the ADSP BF548 processor It The RS 232 console is used to directly access the uClinux kernel uses the ADM3202 RS 232 line driver and receiver to connect running on the ADSP BF548 When the console is connected to to UARTI of the ADSP BF548 The RS 232 signals connect to a a RS 232
12. ED3 PD8 General purpose indicator that can be turned on and off through software LED4 PD9 General purpose indicator that can be turned on and off through software LED5 PD10 General purpose indicator that can be turned on and off through software LED6 PD11 General purpose indicator that can be turned on and off through software LED7 Not Applicable Illuminates when the 3 3 V power supply is available LED8 Not Applicable Illuminates when the reset button is pressed LED10 Not Applicable Illuminates when the VBUS voltage from the USB host is connected Rev 0 Page 18 of 20 JUMPER CONFIGURATIONS Table 4 Interface Configuration Jumpers Fitted Jumpers Open RS 485 RS 422 RS 232 CAN SPIO SPI2 Half duplex configuration Full duplex configuration 120 O termination Loopback Tour to Bun Split terminate the bus with 120 O and a common mode 47 nF capacitor No termination Master mode Slave mode Master mode Slave mode JP3 JP4 JP40 Not applicable JP19 JP2 JP17 JP18 Not applicable JP5 JP7 JP9 JP11 JP13 JP15 JP20 JP36 JP6 JP8 JP10 JP 12 JP14 JP16 JP21 JP37 JP22 JP24 JP26 JP28 JP30 JP32 JP35 JP38 JP23 JP25 JP27 JP29 JP31 JP33 JP34 JP39 Not applicable JP3 JP4 JP40 Not applicable Not applicable Not applicable JP17 JP18 JP6 JP8 JP10 JP12 JP14 JP16 JP21 JP37 JP5 JP7 JP9 JP11 JP13 JP15 JP20 JP36 JP23 JP25 JP27 JP2
13. F 0 01uF 0 1uF 0 01uF 0 1uF 0 01uF 0 1uF p 4 e LVDS iso GND Kea LVDS ISO GND LVDS iso GND LVDS ISO GND Figure 10 ADuM3442 ADN4663 ADN4664 and ADuM5000 Isolated LVDS Implementation Rev 0 Page 13 of 20 10649 010 POWER INPUT An ac to dc desktop power supply is used to supply 7 5 V input to the J1 barrel connector on the ezLINX hardware This supply connects to the UNREG IN node of the circuit through a protection circuit as shown in Figure 11 3 3 V POWER SUPPLY The ADP1864 constant frequency current mode step down dc to dc controller is used with an external P channel MOSFET to generate the regulated 3 3 V power supply for the ezLINX hardware The circuit implementation of the 3 3 V power supply is shown in Figure 12 UNREG IN F1 L1 D2 J1 5A 190R MBRS540T3G 1 O c D 3 ro NO L E 2 4 3 3 D9 PWR CONN SMBJ24CA La C1 C2 FER1 inF inF 600R E le 11 PWR_SH_GND FER2 GND 600R ET HE L a E T T bos S PWR SH GND GND E Figure 11 Power Input UNREG IN g C3 10uF i P_GND R2 R1 24 9K U1 0 05R 1 5 U2 COMP IN C 3 3V TP1 TP2 4 1 5 L2 3 3V GND C4 c5 g csi 1 2 1 2 5uH 470pF 68pF 3 fB 9 poate d 7 1 4 ii ADP1864 R3 D3 a 80 6K SI4411DY P MBRS540T3G 71 C6
14. LLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners UG10649 0 8 12 0 DEVICES www analo g com Rev 0 Page 20 of 20
15. OB 712 JP23 R104 gt VIC voc 28 33R JP24 6 11 CM VOD VID k 3 SPI2MOSK lt a JP28 S JP25 7 10 T T NT 48 R105 ayer VER JP29 33R 58 2 9 SPI2SEL 8 GND1 GND2 6 GND1 GND2 1 E N ADuM3401 T on 78 JP26 xr JP31 SCREW 7 SPI2MISO 4 GND SPI_S_ISO_GND A JP27 JP32 SPI S ISO GND E3 Eeer JP33 E 3 3V SPI S ISO 3 3V T u43 1 vppi vons 18 4 R109 i 10K VIA VOA 5 vig vos D voc vic k 43 JP39 VOD VID v S 3 3V Bis M 1 ver ves 9 33R SPI2SEL2 E Jui Z GND1 GND2 Hs Ga LE en E e 33R RUM ADuM3402 SPI2SELJ GND SPI S ISO GND sSPI2SS 4 33V 3 3V SPI S ISO 3 3V SPI S ISO 3 3V Y JP35 C196 C234 C235 197 0 1uF Ou Out 0 tuF lt l E GND GND GND SPI S ISO GND SPI S ISO GND Figure 9 ADuM3401 ADuM3402 ADuM5000 Isolated SPI2 Implementation Rev 0 Page 11 of 20 ISOLATED LVDS The isolated LVDS port is implemented using the ADuM3442 iCoupler signal isolator the ADN4664 dual LVDS receiver the ADN4663 dual LVDS transmitter and the ADuM5000 isoPower isolated dc to dc converter The ADuM3442 is connected to SPORT2 of the ADSP BF548 Figure 10 shows a circuit diagram of the implementation of the isolated LVDS using the ADuM3442 ADN4663 ADN4664 and ADuM5000 on the ezLINX hardware The Von pin Pin 1 of the ADuM3442 and the Von pin Pin 1 and Pin 7 of the ADuMS000 are powered by 3 3 V The ADuM5000 generates an isolated
16. The ezLINX PCB layout has not been verified to pass radiated emissions specifications Rev 0 Page 1 of 20 TABLE OF CONTENTS Features eere eU eC ME Applications uie t UR er RD IER Evaluation Kit Contents ettet iere e tt Z LINX DEE BZ sioe eseso costes ai EN General Description ses ice RESI ya a a a a eet R VISIOPAETISEOEY E System Architect te eite eite es Isolated CAN EE Isolated RS 485 and RS 422 ees Isolated DS E REVISION HISTORY 8 12 Revision 0 Initial Version P R trt tede e 8 Isolat d Eerst ERR NOE ERE 9 Is lated VEER 12 POWEE INPUt M 14 3 3 V Power Supp et ceteri ee 14 1 2 V 2 5 V and 5 V Power Supplies ENNEN 15 Extender Conn ctot eue aei edens 16 E 17 BER 18 Jumper Configurations eerte 19 Rev 0 Page 2 of 20 SYSTEM ARCHITECTURE The system architecture block diagram of the ezLINX hardware SV 91 is added for additional functionality The Ethernet is shown in Figure 2 An extender connector Hirose FX8 120P option is not fitted on the standard ezLINX hardware ETHERNET NOT FITTED Ji ADSP BF548 IMP H 10649 002 Figure 2 ezLINX Hardware Block Diagram Rev 0 Page 3 of 20 ISOLATED CAN The isolated CAN port is implemented using the ADM3053 signal and power isolated CAN transceiver The ADM3053 connects to CANO of the ADSP BF548 and is capable of functioning at data rates of up to 1 Mbit sec Figure 3 shows a circuit diagram of the implementa
17. and JP40 To configure the node as a half duplex RS 485 node connect JP3 JP4 and JP40 When JP3 and JP4 are fitted A to Y are connected and B to Z are connected When JP3 and JP4 are removed the node is configured as a full duplex RS 422 node When JP19 is fitted the A and B pins are terminated with 120 Q If termination is not required remove JP19 When JP40 is connected a pull up resistor of 10 kO is connected to the RxD pin Pin 4 of the ADM2587E Table 4 shows jumper configurations for all the interfaces on ezLINX The 3 3 V supply is connected to the Vcc pins Pin 2 and Pin 8 to power the isoPower isolated power supply and the iCoupler signal isolation of the ADM2587E This generates an isolated 3 3 V on the Visoovr pin Pin 12 ofthe ADM2587E which is connected to the Vison pin Pin 19 A 6 pin screw terminal connector J7 is used for easy access to the A Pin 2 of J7 B Pin 3 of J7 Z Pin 4 of J7 Y Pin 5 of J7 and R S 485 ISO GND Pin 1 and Pin 6 of J7 signals The AN 960 Application Note RS 485 RS 422 Circuit Imple mentation Guide provides more information about implementing RS 485 and RS 422 circuits The ADM2587E contains isoPower technology that uses high frequency switching elements to transfer power through the transformer Special care must be taken during PCB layout to meet emissions standards Refer to the AN 0971 Application Note Recommendations for Control of Radiated Emission
18. ed SPI2 as a slave connect Jumpers JP23 JP25 JP27 JP29 JP31 JP33 JP34 and JP39 while leaving Jumpers JP22 JP24 JP26 JP28 JP30 JP32 JP35 and JP38 open see the Warnings section Table 2 Isolated SPI2 Connections Jumper SPI2 Master SPI2 Slave JP22 Connect Open JP23 Open Connect JP24 Connect Open JP25 Open Connect JP26 Connect Open JP27 Open Connect JP28 Connect Open JP29 Open Connect JP30 Connect Open JP31 Open Connect JP32 Connect Open JP33 Open Connect JP34 Open Connect JP35 Connect Open JP38 Connect Open JP39 Open Connect Jumper SPIO Master SPIO Slave JP5 Connect Open JP6 Open Connect JP7 Connect Open JP8 Open Connect JP9 Connect Open JP10 Open Connect JP11 Connect Open JP12 Open Connect JP13 Connect Open JP14 Open Connect JP15 Connect Open JP16 Open Connect JP20 Open Connect JP21 Connect Open JP36 Connect Open JP37 Open Connect The ADuMS000 contains isoPower technology that uses high frequency switching elements to transfer power through the transformer Special care must be taken during PCB layout to meet emissions standards See the AN 0971 Application Note Recommendations for Control of Radiated Emissions with isoPower Devices for board layout recommendations Warnings JP20 and JP21 JP20 and JP21 should never both be connected because doing so will create a short circuit between 3 3 V and GND JP34 and JP35 JP34 and JP35 should never both be connected because d
19. ines The ADuM3402 is used for isolating the SPI slave select lines Figure 9 shows a circuit diagram of the implementation of the isolated SPI2 using the ADuM3401 ADuM3402 and ADuM5000 on the ezLINX hardware The Von pin Pin 1 ofthe ADuM3401 and ADuM3402 and the Vpn pins Pin 1 and Pin 7 of the ADuM5000 are powered by 3 3 V The ADuM5000 generates an isolated 3 3 V which is used to supply power to the Vp pin Pin 16 of the ADuM3401 and ADuM3402 Two 7 pin screw terminal connectors J10 and J25 are used for easy access to the SPISCK Pin 1 of J10 and J25 SPIMOSI Pin 2 of J10 and J25 SPISELI SPISS Pin 3 of J10 and J25 SPIMISO Pin 4 of J10 and J25 SPISEL2 Pin 5 of J10 and J25 SPISEL3 Pin 6 of J10 and J25 and SPI ISO GND Pin 7 of J10 and J25 signals To connect the isolated SPIO as a master connect Jumpers JP5 JP7 JP9 JP11 JP13 JP15 JP21 and JP36 while leaving Jumpers JP6 JP8 JP10 JP12 JP14 JP16 JP20 and JP37 open see the Warnings section To connect the isolated SPIO as a slave connect Jumpers JP6 JP8 JP10 JP12 JP14 JP16 JP20 and JP37 while leaving Jumpers JP5 JP11 JP13 JP15 JP21 and JP36 see the Warnings section Table 1 Isolated SPIO Connections To connect the isolated SPI2 as a master connect Jumpers JP22 JP24 JP26 JP28 JP30 JP32 JP35 and JP38 while leaving Jumpers JP23 JP25 JP27 JP29 JP31 JP33 JP34 and JP39 open see the Warnings section To connect the isolat
20. io pin Pin 6 to power the iCoupler signal isolation of the ADM3053 This is to ensure compatibility with 3 3V 5V CAN_ISO_5V U17 8 12 vec VISOOUT 34 48 L Ba vio vison 1Q 2 DAMM 10 TxD CANH A CANORXC amp RxD CANL 3Q AQ dus lis 18 JP18 JP17 ls VREF E 1 a GND1 E g GND1 GND2 43 1 g GND1 GND2 46 1 R68 R69 1 10 GND1 GND2 59 7 60R4 gt 60R4 GND1 GND2 ADM3053 C165 47nF boca NU A GND CAN ISO GND CAN ISO GND CAN ISO GND CAN IO GND 5V 3 3V CAN_ISO_5V oe L C159 C163 C157 C158 C162 C161 C164 C160 10uF 0 1uF O 1uF 0 01uF 10uF 0 1uF 0 1uF 0 01uF L e L gt E gt gt NO 3 GND GND CAN_ISO_GND EH Figure 3 ADM3053 Isolated CAN Implementation Rev 0 Page 4 of 20 ISOLATED RS 485 AND RS 422 The isolated RS 485 and RS 422 port is implemented using the ADM2587E signal and power isolated CAN transceiver The ADM2587E connects to UART2 of the ADSP BF548 and is capable of functioning at data rates of up to 500 kbit sec Figure 4 shows a circuit diagram of the implementation of the ADM2587E on the ezLINX hardware The RS 485 RS 422 node can be configured using Jumpers JP3 JP4 JP19
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23. oing so will create a short circuit between 3 3 V and GND Rev 0 Page 9 of 20 U6 400 3 3V SPI M ISO 3 3V U22 1 10 I T VDD VISO 36 3 VDD1 VISO 6 13 L RCSEL VSEL 34 RCIN 3 lt 24 Rcour NC 54 NC2 7 X NC3 m7 X NC4 2 eu aNpiso 7 1 3 Gup GNDISO nam d ADuM5000 E K V7 Kg GND SPI M ISO GND 3 3V SPI M ISO 3 3V R106 10K E gf C176 C175 C174 C179 C178 C177 10uF 0 1uF 0 1uF 10uF O tuF 0 1uF JP36 3 3V SPI M ISO 3 3V 4 se M U20 gt ed 1 16 GND SPI_M_ISO_GND R75 vDD1 VDD2 33R JP5 J10 SPIOSCK gt e 3 VIA VOA 5 a 1S 5 VIB VOB 5 JP6 R76 VIC voc 28 33R JP7 6 11 T VOD VID 3G SPIOMOSIS JETE JP8 7 10 T es 4G R77 a VET WEST JP12 5Q 33R Ee SPIOSELY GND1 oups 9 Sg Ke GND1 GND2 A ADuM3401 a 78 JP9 K JP14 SCREW 7 SPIOMISO 4 t SPLM ISO GND e 5 x JP10 JP15 SPI M ISO GND L4 3 3V JP16 3 3V SPI M ISO 3 3V R107 10K U21 1 16 VDD1 VDD2
24. port on the PC the kernel can be accessed through a terminal program 3 3V 3 3V 3 3V R56 R58 J4 10K 10K f ec som ws P m s __o riis 3 TO n g nour 2 10 7 7 11 SUARTIRTS A TN S aour 3 2 12 1 UART1RX g RIOUT R1IN s S o UARTICTS R20UT R2IN Y 9 X 0O C112 3 3V e R57 0 tuF H DB9 10K 1 3 3V i 3v 3 Ct GND C113 S e115 0 1uF 0 1uF E c2 a ve LS Gii OND 3 cp v S 0 01uF ADM3202 2 e114 0 1uF GND i Ki i GND GND Figure 17 RS 232 Console Implementation Rev 0 Page 17 of 20 LEDs There die i LEDs ontheez INX evatuatipn board The ted The orange LEDI illuminates to indicate when the uClinux LED6 illuminates to indicate when the reset button is being kernel and application finishes booting up pressed The orange LED 10 illuminates to indicate when the Table 4 describes the functionality and connections of the LEDs isolated USB port is connected to a USB port on the PC The for the ADSP BF548 and other circuitry green LED7 illuminates to indicate when the board is powered Table 3 LED ADSP BF548 Port Function LED1 PD6 Illuminates when the uClinux kernel and application finishes booting up This LED can also be used as a general purpose indicator that can be turned on and off through software LED2 PD7 General purpose indicator that can be turned on and off through software L
25. s with isoPower Devices for details on board layout considerations 33V R111 10K JP3 3 3V RS485 ISO 3 3V EE u16 JUMPER 4 2 vee visoour 12 4 iss JP40 1 8 vec 4 EET vison S JUMPER UART2TX E TxD v H3 J7 4 15 UART2RX X amp RxD z 19 HE go E Hz j 29 DE DE B JP19 s 30 il GND1 GND2 n AQ ra GND1 GND2 j6 1 0 GND1 GND2 29 1 5G 1 GND1 GND2 4 ADM2587E R66 eG 120R SCREW 6 EXE i RS485 ISO GND GND RS485 ISO GND 3 3V RS485 ISO 3 3V e i e e k p C151 C150 C155 C149 C154 C153 C156 C152 10uF our Gut 0 01uF 10uF out 0 1uF 0 01uF L e SE m Kass GND RS485 ISO GND Figure 4 ADM2587E Isolated RS 485 and RS 422 Implementation Rev 0 Page 5 of 20 ISOLATED USB The Vous pin Pin 1 and Vpn pin Pin 3 ofthe ADuM3160 are The isolated USB port is implemented using the ADuM3160 full powered from the 5 V VBUS line of the USB mini connector and speed USB isolator The ADuM3160 connects to the integrated can only be connected to a USB master The Vsus pin Pin 16 PHY of the ADSP BF548 s USB controller and is capable of fun and Vp pin Pin 14 are powered from the 3 3 V generated by ctioning at data rates of up to12 Mbit sec Figure 5 sho
26. tion of the ADM3053 on the ezLINX hardware the 3 3 V logic of the Blackfin ADSP BF548 The Rs pin Pin 18 is connected through a 0 O resistor to CAN_ISO_GND to deactivate slew rate limiting A 4 pin screw terminal connector J8 is used for easy access to the CANH Pin 1 of J8 CANL Pin 3 of J8 and CAN_ISO_GND Pin 2 and Pin 4 of J8 signals The AN 1123 Application Note Controller Area Network CAN Implementation Guide provides more information about imple menting CAN nodes The CAN node can be configured using Jumpers JP17 and JP18 When both Jumpers JP17 and JP 18 are fitted the CAN node is split terminated with 120 O and a common mode capacitor of 47 nF If termination is not required remove JP17 and JP18 Table 4 The ADM3053 contains isoPower technology that uses high shows the jumper configurations for all the interfaces on ezLINX frequency switching elements to transfer power through the transformer Special care must be taken during printed circuit board PCB layout to meet emissions standards Refer to the AN 0971 Application Note Recommendations for Control of Radiated Emissions with isoPower Devices for details on board layout considerations The 5 V supply is connected to the Vcc pin Pin 8 to power the isoPower isolated power supply of the ADM3053 This generates an isolated 5 V on the Visoour pin Pin 12 of the ADM3053 and must be connected to the Vison pin Pin 19 The 3 3 V supply is connected to the V
27. tors Connector J26 is a 3 pin header connector that The Hirose FX8 120P SV 91 extender connector used for allows the CAN1 signals of the ADSP BF548 to be routed to an daughter board connections This allows additional external daughter board functionality to be added to the ezLINX hardware Figure 16 S J26 J23 3 60 61 L S CAN1RX sHIROSE RESET i 553 RESET IN BMODE1 62 BMODE1 z lt CANITX LAN_IRQ UARTORX gt 58 UART_RX UART_TX 63 UARTOTX 57 GND GND 64 X 56 NC7 NC8 es CON3 GND 55 EEPROM A0 NC9 Tee X 54 NC6 NC10 Fez R71 Jg NC5 Mom es 100K aa NC4 NC12 leo e 51 GND GND Tag X 50 NC3 NC13 a X 39 NC2 NC14 72 GE TMR8 4g TMR_C TMR D a TMR9 GND TMR10 a7 IMR A TMR B 74 PD12 4g GPIO6 GPIO7 re lt lt PD13 45 GND GND 76 b PC12 44 GPIO4 GPIO5 zs PC13 Fein 4g GPIO2 GPIO3 ze PC11 PC8 42 GPIOO GPIO1 29 Peg PC5 aa SCLA SCLO an SCLO PC6 40 DA 1 SDA 0 Ca SDAO k 39 GND GND Ca a HSPHSS ze SPI_SEL1 SPI_SS SPI CLK 4SPHSCK onie 37 SPLSEL C SPI MISO SPHMISO sfSPHSEL2 36 SPLSEL B SPI MOSI iig 35 GND SPI SEL A gc S SPHSEL1 PC7 55 SPORT INT GND a X 33 SPORT DT3 SPORT TSCLK TSCLK3 X 32 SPORT DT2 SPORT DTO DT3PRI DT3SEC 23 SPORT DT SPORT TFS TFS3 DR3SEC lt lt SPORT DI SPORT RFS RFS3 X zg SPORT
28. ws a circuit the ezLINX power supply diagram of the implementation of the ADuM3160 on the ezLINX hardware S00 6r901 USB MINI B F A Rss ih oe D g EL ee os oz 6S 25 g 5a 285 6 s Tt ry SES VA as ES z FET e S 2 E zt 9 E o t d D2 m 3 S 5 L Z SS Lien g Z o S l S 2 B e o S aa EJ t s 4 a ag S uz ES o p D2 i S s a GE E os o NO g5 Pol gors o d Oe 2 ge se p 2 fama S o n a S LC 6 Si 4 n PDEN SPU CG 2 Rema UD UD VDD1 VBUS2 VBUS1 a BB aad S ep 2268 Soa gt amp 6 Go 5 a I o a E ada GND lt e N w o S gt S e Figure 5 ADuM3160 Isolated USB Implementation 2 R14 10K v4 Rev 0 Page 6 of 20 ISOLATED RS 232 Viso pins Pin A10 Pin B10 and Pin C10 using Analog Devices isoP technology The isolated RS 232 port is implemented using the ADM3252E EE signal and power isolated RS 232 transceiver The ADM3252E con A 3 pin screw terminal connector J6 is used for easy access to the nects to UART3 of the ADSP BF548 and is capable of functioning Toun Pin 2 of J6 Rau Pin 3 of J6 and R5232 ISO GND at data rates of up to 460 kbit sec Figure 6 shows a circuit diagram Pin 1 of J6 signals of the implementation of the ADM3252E on the ezLINX hardware The ADM3252E contains isoPower technology that uses high
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