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UC1394a-1 Bridge User Guide

1. LN USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 46 UC1394a 1 with generic streaming BSP UO pins ERRDTCT ERRCLR 22 23 ERR 2 0 optional Figure 15 Diagnostic interface over I O pins Please note that an error can also be acknowledged over the HPI This will read out the next error code so that the error code displayed by the I O pins also changes Therefore acknowledging an error should be done exclusively by either the host or by I O pins Diagnostics over I O pins are intended for e error statistics by local hardware e g counting errors e displaying the error condition on a front panel LED error presence or error code e control of local hardware e g aborting operation on error Diagnostic signal MCM connector pin ERRDTCT ERRO ERR1 Table 15 Diagnostics interface pin assignments Encoding of ERR 2 0 is shown in Table 16 3 5 3 Diagnostic Interface over the HPI The output of the error code FIFO is routed to the error bits in the HPI control register 2 see chapter 3 3 3 3 The host can poll for an error by checking the ERRDTCT bit If an error is present ERR 2 0 contain the error code The host must acknowledge the error by writing a 1 to ERRDTCT This clears ERRDTCT immediately and reads out the next error code from the FIFO After that the host can poll ERRDTCT for further errors Please note
2. esseeeeeeeeeeeeese 63 Figure 29 Alternative wiring for customized confguraton eee eect eeeee cette tee eteeteeeeeeeeeeeeeneeeenaaae 64 Figure 30 Setting device and partner ID over I O pins sseesseem eee een 64 Figure 31 Wiring OF UART TEE 65 Figure 32 Wiring of the DSP JTAG interface eessessesseseseseeeeeeeeeeeennneee nennen 66 Figure 33 Required connections EE 67 Figure 34 Dimensions of the UC1394a 1 including connector pins u 76 Figure 35 Recommended PCB footprint of the UC1394a 1 esssseees 76 Figure 36 Soldering temperature example AEN 77 Figure 37 Streaming port transmit timing AEN 80 Figure 38 Streaming port receive TIMING E 81 Figure 39 Streaming port transmit timing imaging mode cece ee eeeeteeeeeeeeeeeeteeeeeeeeeeeneeees 82 Figure 40 HPI write UMI scis iei en a eee eth NR MSRP Reseau pang duo equa Mbps t vance Ede E Kies RE 83 Figure 41 HPI read TM rtr c L 84 fy UsER s GUIDE SANETI UT 2008 VS PARALLEL Bus To IEEE1394 BRIDGE ES E orsys Ge 8 1 Preface This document describes the Parallel Bus to IEEE1394 Bridge that is implemented on the UC1394a 1 multi chip module It is intended for first time users as well as for users that want to migrate from the Parallel Bus to IEEE1394 Bridging Kit to a customized solution 1 1 Document Organization This document is organized as follows e Chapter 2 gives a bri
3. o 9 s 9 E 330R 43 3 o 10k GND configuration mode open configuration service closed normal operation IE as 13 EE1394 pin connector defined in 94a 2000 TPA TPB GND 4 3 TPA 2 1 TPB shield DSP JT recomn AG connector ended for service 13 1i EMUO UC1394a 1 BSP01 14 12 EMU1 GND GND TCK ts TCK RET GND GND 51 TDO avo 14 TDI TMS 8 GND GND 3 8 5V GND 1GND TRST Emulator connector 2x 0 pi 7 pin 1 spacing n 6 removed ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG us PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 68 7 Technical Data 7 11 Connector Pinout Tables The tables below show the complete MCM pinout sorted by pin number as well as the pinout for each supported interface McBSP1 DR TPB1 1 McBSP1 DX TPB1 2 McBSPO DR STR DO McBSP1 CLKR TPA1 8 McBSPO DX STR D1 McBSP1 CLKX TPA14 4 5 McBSPO CLKR STR D2 McBSP1 FSR GND B 6 McBSPO CLKX STR D3 McBSP1 FSX Ooo HDO 6 7 McBSPO FSR STR D4 GND VO1 HD1 IL 18 McBSPO FSX STR_D5 McBSP2 DR VO2 HD2 48 9 RESET OUT STR_D
4. UsER s GUIDE Date 25 October 2006 CY Doc no Bridge UG t Iss Rev 1 1 orsys Page zd User s Guide Parallel Bus to IEEE1394 Bridge using the UC1394a 1 MCM with Generic Streaming BSP Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany http www orsys de Date 25 October 2006 gt sys PARALLEL E S EEI 394 BRIDGE St qe Contents 1 P EFAC E c km 8 14 Document Eiere 8 12 Documentation Overview eorr nitent un ihn a Dana NS NA KR a u KA R na A o H da en a RM ERIS 8 1 3 Notatlonal Conventions cw cain a ccc wand nance cece cic ease hte ddim auaenncnce 8 1 4 E En E CTT 9 15 REVISION HISIOTy iscritta eei rin o nad Aa Ah RSA K AA A 10 2 SYSTEM OVERVIEW ana o oa A a A B i S S 11 2 1 Virtual Connection Protocol EM 12 22 Streaming POrE is metz aaa 13 2 3 UART Rn c 13 2 4 Host Port Interface HPI lt eeeeeeeereeeeee eee eee enne nnne n nnn nnn nnn nn nnn nnn nnn n nnn nnn n nn nn nnn 13 2 5 WO PS ia 13 2 5 IEEET1394 InIBITADO umu ol ku sd n i aka eau mou aa aa k ash 13 ME TTT E 14 SR ee ueri er Eege 14 14 Sco occ 14 2 10 Diagnostic INIGTTACG iussu niin aai dan IX GUN ma da Ex vix E indus rad SUCRE E kakaa EE ERU MER KC MEAN
5. 3 2 2 12 UART Hardware FIFO Sizes uart rx fifo size uart ix fifo size These parameters are read only They define how many characters can be buffered by the UART hardware and are used for informational purposes only 3 3 Host Port Interface HPI The host port interface is a 8 or 16 bit bi directional parallel interface for easy connection to an external host such as a microcontroller In contrast to the I O pins or the UART interface HPI data transfers are always initiated by the external host The HPI shares its signals with those of the I O pins Depending on the HPI configuration a different number of I O pins are available see chapter 3 4 1 Virtual HPI connections use either a fixed connection as defined by the configuration parameters or a dynamic addressing where the host specifies the destination device HPI data is buffered by 16 word deep FIFOs in either direction Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 i Orsys Page 29 Q External host microcontroller VCP IEEE1394 HPI data data events Interface 8 16 lines Flow qontrol events HPI control 5 4 lines HPI handshake 0 1 2lines Figure 9 HPI block diagram 3 3 4 HPI Signals HRRDY HRDY HTRDY Figure 10 HPI signals HPI signal Direction Connector Available when HPI is Alternative function HDO i bi directional D6 HD2 bidirecional D8 HDi bidirectionsl De
6. Ah ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG us PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 104 7 9 10 Configuration Mode 9 31 MBps Predefined Configuration This configuration is used by the bridging kit 1 for maximum bandwidth requirements Please note that in this mode it is strongly recommended that data transfers are synchronized by means of the streaming port flags STR FLAGO and or STR_FLAG1 Device common parameters dev id partner dev fpga ver fpga rev SW ver indicates current FPGA revision indicates current firmware version sw rev indicates current firmware revision vcp ver VCP V1 4 Streaming port r ix pktsize 4096 bytes 1024 quadlets use devic o alale eo o eo eo o ba D str id is read from pin 1 026 str_ch e_id partner_dev partner dev use common device parameter partner dev str partner inst 0 16 bit a UO pins 0 7 5 o D 5 c D o Uu D zi EEG str xfertype str width str iftype str blksize S Q S virtual connection to partner pin enabled a use common device parameter partner dev S enabled 8 15 respectively enabled io dir io otype IP Block size limited in order to still have FIFO space after one block has been written to the FIFO from either side 2 S e o bojvo EIER SEEN O jo S Q9 c SE o lt Date 25 October 2
7. Luart partner dev use common device parameter partner der uart partner inst 10 uart resume 0 0 0 0 0 0 0 uart resume 0 uart rx fifo size 16 i hpi width hpi handshake hpi connect hpi partner dev hpi partner inst O O hpi tx pktsize hpi tx timeout hpi ev bufsize hpi rx bufsize hpi flowctl hpi suspend hpi resume hpi rx fifo size hpi tx fifo size Configuration interface gt 5 Registration interface reg partner dev accept any device reg partner inst accept any instance Table 54 Predefined configuration mode 4 ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 96 7 9 6 Configuration Mode 5 31 KBps Predefined Configuration This configuration is used by the bridging kit 1 for low bandwidth requirements Setting Device common parameters partner dev foga ver Da rev partner dev foga ver indicates current FPGA revision sw ver indicates current firmware version sw rev indicates current firmware revision vcp ver 0001000445 VCP V1 4 Streaming port 4 bytes 1 quadlet str dir str idis read from pin O26 use device id partner dev isochronous streaming sir partner dev use common device parameter partner dev i str_width 16 bit generic interface str_auto manual start oy VCP API 4 bytes 1 quadlet 0 no sync pattern UO pin
8. hpi tx fifo size Diagnostic interface no hardware signaling diag connect enabled use common device parameter partner dev accept any instance Configuration interface accept any device accept any instance 5 Registration interface reg partner dev accept any device reg partner inst accept any instance Table 55 Predefined configuration mode 5 Le orsys USER S GUIDE PARALLEL Bus To IEEE1394 BRIDGE Date 25 October 2006 Doc no Bridge_UG Iss Rev 1 1 Page 98 7 9 7 Configuration Mode 6 313 kBps Predefined Configuration This configuration is used by the bridging kit 1 for low to medium bandwidth requirements Parameter name dev id partner dev foga ver Da rev VCH ver str ix pkisize str dir str ch sir xfertype sir partner dev str partner inst Setting Device common parameters indicates current FPGA revision indicates current firmware version indicates current firmware revision 001000446 VCP V1 4 Streaming port 40 bytes 10 quadlets str idis read from pin O26 use device id partner dev isochronous streaming use common device parameter partner dev str width str iftype str blksize str frmsync io dir io otype io connect io partner dev io partner inst 16 bit generic interface manual start by VCP API 40 bytes 10 quadlets 0 no sync pattern UO pins 0 7 input open drain output high virtual connection to partner pi
9. This parameters defines how many bytes are transferred to the partner device in one data event Allowed value range for this parameter is 1 to 2040 however when the HPI is operated in 16 bit configuration hpi width 16 only multiples of 2 should be used A special value for this parameter also exists When hpi tx pktsize is set to variable packet size as many characters as possible are transferred dynamic packet size The suggested default value for this parameter is variable packet size when another MCM is used as partner device When a PC is used as partner device hpi tx pktsize should be set to its maximum value of 2040 together with a timeout see chapter 3 3 2 8 This limits the maximum event rate and is required because flow control cant be used due to the limited real time behavior of Windows Alternatively smaller packet sizes or less timeout can be used if a modified event FIFO setting on the PC is used Please refer to the description of the function VCP_EnableEventFifo in 7 3 3 2 8 HPI Transmit Timeout hpi tx timeout This parameter works in conjunction with fixed transmit packet sizes greater than 1 If hpi tx pktsize is set to O dynamic packet size or 1 this parameter has no effect see also hpi ix pktsize chapter 3 3 2 7 hpi tx timeout defines the maximum time in milliseconds for waiting until a packet is complete If this time expires a data event is sent to the partner device interface using a smaller
10. UART TxD o TXO1 TXH UART RxD 10 TXO2 TXI2 o ro u co oo s co o o 11 Qe s Xx Xx RXI1 RXO1 UART RTS UART CTS SUB D 9 connector RXI2 RXO2 READY INVALID FORCEON FORCEOFF pm f 9v MAX3225CAP Figure 33 Required connections McBSPO DR Ag McBSPO DX Ag McBSPO_CLKR 45 McBSPO_CLKX Ag McBSPO_FSR X MoBSPO FSX ze McBSP1 DR Gg McBSP1 DX X G4 McBSP1_CLKR X G5 McBSP1 CLKX Ge McBSP1 FSR X McBSP1 FSX X G9 McBSP2 DR Gig McBSP2 DX eet McBSP2 CLKR C11 McBSP2 CLKX X 13 McBSP2_FSR SEI MeBSP2 FSX PBS voo xB O1 PRY 102 pi 03 D11 e xB vos BI vos D41 O7 X pis vos BY vos D17 O10 X pra IO X Bag W012 RTC D21 13 RTC X Pe VO14 RTC X 25 s D24 VO16 X 5551 i017 xD25 Voie D27 VO19 X 6571 020 V021 XLR psp xri xD31 2c SDA XDA GC soL X C28 AIN 0 XC AIN 1 S il AN 2 X As 43 3V 43 3V 3 3V 43 3V GND GND GND GND GND GND GND GND GND GND GND GND RESET OUT RESET IN 1 022 10 23 1 024 1 025 1 026 1394_TPA0 1394 TPAO 1394 TPBO 1394 TPBO 1894 TPA1 1394 TPA1 1394 TPB1 1394 TPB1 USB DP USB DN JTAG DSP EMU1 JTAG DSP EMUO JTAG DSP TRST JTAG DSP TCK JTAG DSP TDO JTAG DSP TDI JTAG DSP TMS JTAG FPGA TOK JTAG FPGA TDO JTAG FPGA TDI JTAG FPGA TMS 100nF 100nF 100nF 100nF 0 3 3V AS 0 3 3V SL O43 3V 0 3 3V
11. When the streaming port is configured for imaging interface mode and receive direction CAM FEN will be ignored and no streaming operation is possible STR CLK CAM PCLK Clock input for streaming data With each clock one data word is transferred between the streaming port interface and external hardware When the streaming port is configured as an imaging interface CAM PCLK is the pixel clock All timings of the streaming port are related to this clock In transmit direction from the streaming port to the IEEE1394 network data on STR D 15 0 or CAM D 15 0 is clocked in with each rising edge of STR CLK CAM PCLK In receive direction from IEEE1394 network to the streaming port a falling edge on STR CLK while STR RE is low causes the next data to be clocked out of the FIFO while the current data at STR D 15 0 is being held The new data of the FIFO output is transferred to the output STR D 15 0 after the next rising edge of STR CLK Connected hardware should sample STR D 15 0 at the rising edge of STR CLK STR FLAGO CAM FLAGO This signal is active low It works as a synchronization flag for word synchronized data transfers Data can only be transferred from to the streaming port while STR FLAGO or CAM FLAGO is low In receive direction from IEEE1394 network to the streaming port a low level on STR FLAGO indicates that at least one 16 bit data word is available at the streaming port This is independent of the configured
12. further errors won t be written to the FIFO This ensures that the FIFO contains the very first error and not subsequent errors that resulted from the first errors Optionally an error notification event can be sent to a remote device The error FIFO can be read out by any remote device The user has to ensure that only one device reads diagnostic information Details about the diagnostic FIFO can be found in 3 The detailed error codes supported by the detailed error FIFO are listed in Table 17 The error FIFO can also be completely cleared by a diagnostic host This allows to restart error statistics after an error condition has been removed without resetting the whole system This clear command not only clears the detailed error FIFO but also the error code FIFO so that error statistics can be restarted on all interfaces Diagnostics over IEEE1394 are intended for e central diagnosis and error statistics in a distributed system e detailed error investigation during development Diagnostics over IEEE1394 are supported by the VCP SDK VCPDEMO allows to reading out and clearing the detailed error FIFO 3 5 2 Diagnostic Interface over Dedicated UO Pins The output of the error code FIFO can be routed to I O pins 22 to 26 of the UC1394a 1 MCM by configuration ERRDTCT signals that an error is present External hardware can acknowledge the error by activating ERRCLR This clears the current error and reads the next error code from the FIFO
13. 16 26 respectively UART 115200 baud ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 orsys Page 101 Setting luart handshake RTS CTS handshake enabled uart ev bufsize none I O 21 20 enabled virtual connection to partner device disabled hpi partner dev use common device parameter partner dev use dynamic packet size hpi tx_timeout hpi flowctl disabled hpi suspend hpi rx fifo size hpi tx fifo size diag iftype no hardware signaling hpi ev bufsize Diagnostic interface enabled use common device parameter partner dev accept any instance Configuration interface accept any device accept any instance cfg ev bufsize 5 Registration interface reg partner dev accept any device reg partner inst accept any instance Table 57 Predefined configuration mode 7 ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG us PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 102 7 9 9 Configuration Mode 8 15 MBps Predefined Configuration This configuration is used by the bridging kit 1 for up to 5096 of the maximum bandwidth This is the highest bandwidth that can be transmitted without synchronization by STR FLAGO STR FLAG1 partner dev PO foga ver foga rev vcp ver str ix pktsize str xfertype str partner dev use common device parameter partner dev str partner
14. Figure 8 UART signals MERI w S 25 Figure 9 HPI block OOA sss nas s le cc okaud io Akad dieat Hip Enea 29 elei DCL el e Let 29 Figure 11 I O pin block diagram E 39 Figure 12 142 pini Con tiguf altioris getest aa etea MH jd nas RETENE EE 40 Figure 13 Example for a virtual connection between two I O pins een 40 Figure 14 Diagnostic interface block diagram cccsseeeeneneeeeeeeeeeseneeeeeeeeeeeeeenseeeeeeeneneeeeneeseeees 45 Figure 15 Diagnostic interface over I O pinS EEN 46 Figure 16 Isochronous data recorded from the IEEE1394 bus with an analyzer 52 Figure 17 Isochronous packet assembly sampling at 100kHz 16bit packet size 40 bytes 52 Figure 18 Configuration TOO 345 A be 55 Figure 19 Virtual connection between two hardware interfaces A 57 Figure 20 Virtual connection between a host PC and a hardware interface eee 58 Figure 21 VCP RE 59 Figure 22 VCP demo PICO E 60 Figure 23 6 pin IEEET1394 co0nNeCIOTS E 62 Figure 24 4 pin IEEET3948 connector EE 62 Figure 25 Pin numbering for 6 pin and 4 pin IEEE1394 connectors top view 62 Figure 26 Supplying the MCM from IEEET 204 62 Figure 27 Supplying power to the IEEE1394 cable eee eee eee eee nenene 63 Figure 28 Minimum required wiring for customized configuration
15. New error code added supported in firmware V2 6 or higher Cross referenced footnotes reformatted were missing in the PDF version Updated to RoHS compliant production Documentation overview exchanged document names corrected Implementation guidelines for IEEE1394 connectors revised Minimum pulse width specification for MCM internal reset on RESETIN removed Configuration mode overview auto start vs manual start corrected was exchanged UART interface Rx Tx FIFO mentioned f UsER S GUIDE Date 25 October 2006 d Doc no Bridge UG uf PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 11 2 System Overview The Parallel bus to IEEE1394 Bridge is a ready to use solution for interfacing an 8 bit or 16 bit parallel port called streaming port throughout this document to the IEEE1394 bus The bridge also provides some auxiliary interfaces e up to 27 general purpose I O pins e an UART interface e a 8 16 bit host port interface The bridge is implemented on a UC1394a 1 Multi Chip Module MCM that is equipped with the generic streaming Board Support Package BSP High level access to the hardware interfaces over IEEE1394 is provided by the Orsys Virtual Connection Protocol VCP A VCP SDK for Windows based PCs provides easy development of application software Interface configuration and communication parameters can be adjusted and permanently stored in the MCM s Flash memory using a configura
16. io otype io state io connect io partner dev use common device parameter partner dev io partner inst 8 15 respectively io enable o o Q bi E Z a o Oo CC o GIS o Q S 2 2 D o I O pins 8 15 EN Q S o lt lt io otype open drain output lo state high lo connect virtual connection to partner pin enabled io partner dev io partner inst 0 7 respectively io enable enabled io dir io otype o partner inst 10 Date 25 October 2006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 orsys Page 193 Q Setting uart partner inst 10 uart suspend 4096 uart resume 0o 0 0 0 0 0 0 O HPI hpi en isabled hpi width hpi handshake none 1 O 21 20 enabled hpi_connect hpi partner dev co partner inst O o hpi_tx_pktsize hpi tx timeout Joe O hpi ev bufsize 2048 hpi rx bufsize 40906 Cd hpi flowctl hpi suspend OS hpi_rx_fifo_size hpi tx fifo size ag iftype ag connect diag partner dev diag partner inst c g partner dev cfg partner inst ev bufsize Table 53 Predefined configuration mode 3 no o R Co 4096 hpi connect hpi partner dev hpi ix pktsize Lhpi tx timeout 0 ms hp flowctl hpi suspend gt S 3 o W C Ah ly USER S GUIDE Date 25 Octobe
17. o SRS MOO Mn Pe 75 po PANO GAG ecc c R n ase eee eds eee 75 p X MEL SIT NUNT ETT 75 ENER BO IK O m 75 7 3 Dimensions Of the UC1394a 1 M 76 7 4 Environmental Condlilorns n s ns eo no dada da s once astu EHP nnna 76 Zb E E 76 pc Ambient HUMAY asiain ee en a a ee ee anat 76 7 43 Ambient LEE een nen ee ee 77 75 Soldering PROCCS mee S 77 rise ote 77 ZZ Signal Levels and Loads e intesa ten dub unix ER e n iaeia raiadas P S YER SE 78 re NE III Iro 78 7 7 2 Streaming Be ge a EE 78 Z UART SIUS ceres pna sarta bat ana aeted d Can cau st SC dida ES NE 79 DNA Ae Reset Signals p 79 Z Other OOM ter T t 80 ZB Signal TIMIN S e L 80 7 8 1 Streaming EE 80 e AR VEER 83 K VO Pin TIMNgS SR S o o 0 S TUE 84 fw USER S GUIDE Date 25 October 2006 LJ PARALLEL BUS To IEEE1394 BRIDGE E nl Orsys Page 25 ZB MUNDI Saas o ee ee 85 7 9 Predefined Configuration Tables ecoute pint ne Kasa nau oa ach aua peu eaa una Ku ERR p REX RR dna 85 7 9 1 Configuration Mode 0 31 KBps Predefined Configuration sesesessse 86 7 9 2 Configuration Mode 1 313 KBps Predefined Configuration u eee 88 7 9 8 Configuration Mode 2 3 MBps Predefined Configuration 90 7 9 4 Configuration M
18. 1 Page 100 7 9 8 Configuration Mode 7 3 MBps Predefined Configuration This configuration is used by the bridging kit 1 for medium to high bandwidth requirements Parameter name dev id partner dev foga ver Da rev VCH ver str ix pkisize str dir str ch sir xfertype sir partner dev str partner inst Setting Device common parameters indicates current FPGA revision indicates current firmware version indicates current firmware revision 001000446 VCP V1 4 Streaming port 400 bytes 100 quadlets str idis read from pin O26 use device id partner dev isochronous streaming use common device parameter partner dev str width str iftype str blksize str frmsync io dir io otype io connect io partner dev io partner inst 16 bit generic interface manual start by VCP API 400 bytes 100 quadlets 0 no sync pattern UO pins 0 7 input open drain output high virtual connection to partner pin enabled use common device parameter partner dev 0 7 respectively io enable De io connect io partner dev io partner inst enabled IO pins 8 15 output open drain output igh virtual connection to partner pin enabled use common device parameter partner dev 8 15 respectively io connect io partner dev io partner inst io en enabled I O pins 16 26 input open drain output igh virtual connection to partner pin enabled use common device parameter partner dev
19. 4 7kQ pull up f USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 76 73 Dimensions of the UC1394a 1 36 6 Vi CH OU o d top and side view ko o all dimensions in millimeters mm Figure 34 Dimensions of the UC1394a 1 including connector pins 37 08 1 46 C1 C1 Se o o A1 a eg A 5 SE s S 5 i s TOTO TIT maT TTT Ta mnm 1 016 208 0 04 on all dimensions are in milimeters mm all dimensions are in inches compatible square layout for future versions Figure 35 Recommended PCB footprint of the UC1394a 1 Please note The PCB area below the UC1394a 1 should not be used for components 7 4 Environmental Conditions 7 4 4 Storage The UC1394a 1 can be stored in its original packaging for one year at the conditions given in chapters 7 4 2 and 7 4 3 7 4 2 Ambient Humidity Parameter storage non condensing operating non condensing rs USER S GUIDE Date 25 October 2006 4 Doc no Bridge_UG M PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 77 7 4 3 Ambient Temperature storage temperature operating temperature 0 C Please note The ambient temperature can be higher than 60 C if the FPGA case temperature is limited to 80 C by appropriate cooling methods such as ventilation heat sinks and good thermal design of the
20. C F G H J K L N O dnce wf rwO0 rwo rwo r w 0102 r 0 r wc 0 w r w 0 rc 0 r w 0 r w 0 accessibility and default value legend r bit is readable w bit is writeable r W bit is readable and writeable but has different meanings for read and write can t be read back rc this bit is cleared after a read wc writing a 1 to this bit clears it 0 default value 1 4 Trademarks TI Code Composer DSP BIOS and TMS320C5000 are registered trademarks of Texas Instruments Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries All other brand or product names are trademarks or registered trademarks of the respective companies or organizations fy UsER s GUIDE Date 25 October 2006 Doc no Bridge UG uM PARALLEL Bus TO IEEE 1394 BRIDGE s Rev iL Orsys Page 10 1 5 Hevision History First issue Replaces Generic Streaming Kit PnP pdf and GS BSP PnP pdf Required FPGA Version V4 08 or higher Required firmware version revision V2 01 or higher Required VCP version 1 4 Table I O pin states for configuration mode corrected Minor typos corrected UART amp HPI Tx packet size suggested value and description revised UART amp HPI Tx timeout suggested value reduced to 100ms max value added str ch receive all also not allowed for VCP usage Module and footprint dimensions revised
21. CAM CLK io CAM LEN inactive between two lines Table 43 Streaming port transmit timing parameters imaging mode 7 8 2 HPI Timings 7 8 2 1 HPI Write Timing HA 1 0 HD 15 0 HCS HxRDY HWR Figure 40 HPI write timing Parameter HA 1 0 HD 15 0 HCS valid before falling edge of HWR HA 1 0 HD 15 0 HCS valid after rising edge of HWR HWR low pulse width HRD high pulse width HRD frequency bs 0 HxRDY inactive after rising edge of HWR tat HxRDY active after rising edge of HWR n a n a asynchronous Table 44 HPI write timing parameters ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 84 7 8 2 2 HPI Read Timing Please note the first data word is automatically clocked out of the FIFO and is therefore immediately available HA 1 0 HD 15 0 HCS HxRDY HRD Figure 41 HPI read timing Parameter HA 1 0 HCS valid before falling edge of HRD HD 15 0 valid after HRD low HRD low pulse width HRD high pulse width HRD freguency HA 1 0 HCS valid after HRD high HD 15 0 floating after HRD high HRDY HRRD inactive after falling edge of HRD HRDY HRRD active Table 45 HPI read timing parameters ct let a pe ims O a L ck LR e o ir fale olo lols 5 5 5 2 o o o ho o 2 o 0 MHz hi 0 ns H
22. FIFO are ignored so that the FIFO contents isn t changed When using dynamic addressing hpi partner dev set to dynamic addressing the HPI data register works in conjunction with the ID bit field in HPIC1 3 3 3 2 HPI Control Register 1 HPIC1 This register is used to control communication between host and the MCM The host accesses this register for e determining the state of the HPI FIFOs TRDY RRDY TEMPTY OV UN e control handshake or error signaling over dedicated HPI signals TRDY EN RRDY EN ERR EN e control the destination ID for outgoing data if dynamic addressing is selected hpi partner dev use dynamic addressing e retrieve the source of incoming HPI data if dynamic addressing is selected hpi partner dev use dynamic addressing e switch to HPIC2 by setting HPICA 15 14 13 8 5 4 3 2 1 0 7 6 HPICA RSV ID ERR EN RRDY EN TRDY ENT UN OV TEMPTY RRDY TRDY wf nO r w 000000 wn r w 0 r w 0 r wc 0 r we 0 W ro H Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 96 TRDY This bit indicates that the HPI FIFO can accept at least two more data words from the host TRDY 1 TRDY is inactive when there is space for less than two data words in the FIFO TRDY is read only The host should check the TRDY bit before writing to the HPID register RRDY This bit indicates that the HPI FIFO ha
23. O pin For example if the HPI is enabled I O pin 0 is no longer available and io enable of l OO is set to disabled 3 5 Diagnostic Interface The diagnostic interface stores every error or abnormal condition in two error FIFOs One error FIFO contains detailed information about an abnormal condition including the interface that the error is related to and a timestamp when the error happened This FIFO is connected to the IEEE1394 interface for diagnosis at a central point in the IEEE1394 network The other error FIFO contains an error code that is forwarded to the following interfaces e UC1394a 1 MCM LED output as a blink code e dedicated I O pins e HPI This error FIFO can be used by local hardware for error handling and simple error statistics e g counting the errors fy USER S GUIDE Date 25 October 2006 Doc no Bridge_UG PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 45 IEEE1394 bus IEEE 1394 Interface Read FIFO ULL Clear errors L Grror notification Diagnostic Host error polling interrupt error acknowledge external microcontroller Host Port Interface VO Pins red LED external logic e g CPLD error signaling error acknowledge Figure 14 Diagnostic interface block diagram 3 5 4 Diagnostic Interface over IEEE1394 When an abnormal condition occurs it is stored in the detailed error FIFO If the FIFO is full
24. aeg HD5 HD6 HD7 enabled and configured as 16 bit i directional i directional i directional i directional i directional o o o o o All signals shown HD 15 8 only available in 16 bit mode HAO only available in 8 bit mode The alternative functions reside on a different connector Please refer to the description of the I O Pins 5 O8 is used as HAO in 8 bit mode and as HD8 in 16 bit mode UsER s GUIDE Date 25 October 2006 fy USER S GUIDE Ge l a 2006 NA PARALLEL Bus TO IEEE1394 BRIDGE s Rev A1 Orsys Page 30 HPI signal Direction Connector Available when HPI is Alternative function bi directional 1 014 bi directional 1 015 O16 enabled O17 O18 enabled and configured as 8 bit 1 O8 enabled 1 019 enabled with any handshake O20 output C27 enabled with separate l O21 handshake lines Table 6 HPI connector pin assignments HD 15 0 HPI data bus When the HPI is configured for 8 bit operation hpi width set to 8 HD 15 8 are not available The respective pins are used as HAO and l O 15 9 Please note that the first data word is immediately available at HD 15 0 A falling edge on HRD causes the current data to be placed on HD 15 0 as well as reading out the next data from the HPI FIFO However the next data is transferred to HD 15 0 only after the next falling edge on HRD HCS Active low chip select input The host must activate this signal before it can
25. all local diagnostic interfaces I O pins HPI and LED blink code Further error information is provided by the diagnostic interface over IEEE1394 see Table 17 for a list of detailed error codes Table 16 Available error codes 3 5 5 1 1 Configuration Setup Error This error happens if the MCM is set to configuration mode 1419 or 1510 customized configurations and e there is no configuration present in the MCM s flash memory e the configuration data stored in flash memory is corrupted e the configuration data stored in flash memory is not compatible with this firmware version probably generated by an older firmware version e The FPGA version of the FPGA code in stored flash memory is not supported by this firmware version This happens for example if an old firmware version that uses FPGA version 1 x is updated by a newer version that requires a V4 x FPGA Change of streaming port direction from receive to transmit via the streaming control register has failed because str ch is set to receive all channels which is not allowed for transmit 3 5 5 1 2 Initialization of IEEE1394 Subsystem Failed An error occurred during initialization of the IEEE1394 API or while the address ranges for the VCP are mapped into the IEEE1394 address range 3 5 5 1 3 IEEE1394 Error The IEEE1394 API signaled an error Possible reasons are IEEE1394 transmission errors cable problems trouble with the remote device operation 3 5 5 1 4 Missi
26. and ERR 2 0 define the type of the error The host can read this bit to check if an error has occurred ERRDTCT 1 When an error has occurred the host should examine ERR 2 0 for the cause of the error and then take the appropriate action After that the host should acknowledge the error by writing a 1 to the ERRDTCT bit The UC1394a 1 immediately clears ERRDTCT If more errors are present the next error code is read from the error FIFO the error code is written to ERR 2 0 and ERRDTCT is set again Please note that this error interface is connected to the same error FIFO as the hardware diagnostic interface When an error is acknowledged on either interface the next error code is written to both interfaces Therefore only one of both interfaces diagnostic interface over dedicated I O pins chapter 3 5 2 or HPI should be used Code example HPI registers address map define HPID HPI BASE ADDRESS 0 HPI data register define HPIC1 HPI BASE ADDRESS 1 HPI control register 1 define HPIC2 HPI BASE ADDRESS 1 HPI control register 2 define HPIC3 HPI BASE ADDRESS 2 HPI control register 3 carrier board HPI register bit definitions define HPICX HPIC1 0x0000 HPICA setting for HPIC1 HPICA is present in HPIC1 and HPIC2 define HPICX HPIC2 0x8000 HPICA setting for HPIC2 HPICA is present in HPIC1 and HPIC2 define HPIC2 ERRDTCT 0x0008 error detedct error acknowledge def
27. at system startup A jumper or some programmable logic can define the startup state of 1 026 to define the direction of str4eaming transfers To use this feature configuration parameter str dir ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 rsys Page A3 must be set to read from UO pin Please note For applications that reguire to change streaming direction during runtime the method described in chapter 3 1 3 3 is preferred The streaming direction is encoded as follows Startup state of l O26 Streaming direction high 3 4 4 UO Pin Configuration I O pin configuration can be divided into two sections Parameters o dir and io otype are used to configure the behavior of the physical pin The remaining parameters deal with the virtual connection Table 14 lists the available configuration parameters io dir pin direction i partner instance partner pin on the partner device associated with this pin tells if the I O pin is available or used by an alternative interface Table 14 I O pin parameter overview partner device for this UO pin io 3 4 4 1 UO Pin Direction io dir This parameter determines whether the associated I O pin is an input or an output 3 4 4 2 UO Pin Output Type io otype This parameter affects I O pin behavior when it is configured as an output It can be set to e Push pull output e Open drain output
28. be transferred using different bandwidths packet sizes How to use the configuration interface is described in chapter 3 6 2 12 Registration Interface The registration interface is a software only interface that allows non VCP devices to access the interfaces of a VCP device The registration interface is described in chapter 3 7 fy USER S GUIDE Date 25 October 2006 Doc no Bridge_UG PARALLEL BUS TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 215 3 Detailed Interface description 3 1 Streaming Port The streaming port is the main interface of the bridge It allows high speed data transfers up to 32 768 000 bytes per second A 2048x16 bit FIFO buffers the data so that the streaming port can operate at a speed that is independent of the IEEE1394 timing Synchronization flags signal when data is to be transferred from or to the streaming port The streaming port can be easily connected to synchronous interfaces e g customized FPGA implementations as well a asynchronous interfaces e g microcontroller buses Data transfer direction must be set up by configuration or over VCP before streaming operation is started Streaming port data is transferred over IEEE1394 using isochronous streaming by default Please refer to chapter 3 8 1 for a discussion of the IEEE1394 data transfer methods VCP IEEE 1394a chipset Unidirectional transfer of IEEE1394 streaming data Porto 2048x16 FI
29. defines the device that is used as partner for the streaming port The partner device is allowed to control streaming operation of the local device by writing to the STR CTL software register see 3 for details This allows to control streaming operation as described in chapter 3 1 3 str partner dev can be set to e The device ID of a remote device 0 6210 e Accept any device as partner Use configuration parameter partner dev from the device global parameters see chapter 4 3 2 Suggested default value for this parameter is to use configuration parameter partner dev from the device global parameters 3 1 4 6 Streaming Port Partner Interface Instance str partner inst This parameter is used when multiple streaming ports exist on a device It defines which streaming port of the partner device is used as partner for the streaming port Together with str partner dev str partner inst acts as a filter for incoming streaming start streaming stop events over VCP For isochronous streaming which is the default transfer method for the streaming port no other function is associated with this parameter str partner inst can be set to e A interface instance number of the streaming port between 0 and 255 e Accept any streaming port of the partner device Suggested default value for this parameter is interface instance 0 since there is usually only one streaming port per device A stream ID of 3110 is reserved by the IEEE1
30. greater than 1 If uart ix pktsize is set to 0 dynamic packet size or 1 this parameter has no effect see also uart ix pktsize chapter 3 2 2 6 uart tx timeout defines the maximum time in milliseconds for waiting until a packet is complete If this time expires a character event is sent to the partner device interface using a smaller packet size than adjusted by uart tx pktsize If no data at all is present no packet is sent The timeout starts to expire with the first available data When the timeout is set to 0 the timeout feature is disabled and character events to the partner are only sent if enough data is available The maximum value for this parameter is 60 000 1 minute The suggested default for this parameter is 100 ms for a PC as partner device and 0 disabled for a MOM as partner device 3 2 2 8 UART Virtual Connection Event Buffer Size uart ev bufsize This parameter is read only and is used for informational purposes only It specifies the maximum size in bytes for incoming character events This information is useful for situations where the VCP SDK is not available 3 2 2 9 UART Virtual Connection Receive Buffer Size uart rx bufsize This parameter is read only and is used for informational purposes only It specifies the number of characters that can be buffered by software This information is useful for situations where the VCP SDK is not available 3 2 2 10 UART Virtual Connection Flow Control uart rx flowcti T
31. handshake type signals connect HPI of local device with partner node partner node for virtual HPI connection partner instance interface number on the partner device size of the event packets that are transmitted to the partner maximum time in ms until pending data is sent size of the buffer for incoming data events size of the software buffer for incoming HPI data enable disable virtual connection flow control hpi suspend used for HPI flow control used for HPI flow control number of data words that can be buffered in the HPI number of data words that can be buffered in the HPI Table 8 HPI parameter overview 3 3 2 1 HPI Enable hpi en This parameter enables the HPI It has two possible values enabled shared pins are used as host port interface e disabled shared pins are used as I O pins 3 3 2 2 HPI Bus Width hpi width This parameter controls whether the HPI is an 8 bit or a 16 bit interface In 8 bit mode data transfers use only 8 data bits HD 7 0 the HPI registers are split into two 8 bit registers and HPI addressing uses an additional address line HAO 3 3 2 3 HPI Handshake Type hpi handshake This parameter defines how the signals HRRDY HRDY and HTRDY are used Possible settings are e No handshake HRRDY HRDY and HTRDY are used as general purpose UO pins I O pins 20 and 21 e Common handshake HRRDY HRDY is used as common handshake line HRDY function selected HTRDY is used as general pu
32. is described in chapter 4 A second method for configuration exists over the configuration interface See chapter 3 6 2 9 LEDs The red LED of the UC1394a 1 MCM is used as a part of the diagnostic interface to indicate error conditions by a blink code The blink codes are described in chapter 3 5 5 2 10 Diagnostic Interface The diagnostic interface is not an interface for data transfer Instead it is used for troubleshooting when things don t work as expected In end application environment the diagnostic interface can be used to collect long term statistics Errors and warnings that appear during operation are stored in an error FIFO together with the interface they re related to and some classification flags The error FIFO can be read out by a virtual connection from anywhere in the IEEE1394 network Severe error conditions can be signaled to local hardware through dedicated UO pins or through the host port interface Local hardware can use these mechanisms to detect potential problems and take the appropriate action A third mechanism for signaling error conditions is the red LED It signals errors through a blink code The diagnostic interface is described in chapter 3 5 2 11 Configuration Interface The configuration interface is a software only interface that allows to configure the bridge over IEEE1394 It is intended for situations where operating parameters must be adjusted at runtime e g when two bursts of streaming data have to
33. level converter An example is shown in Figure 33 If RTS CTS handshake is enabled see chapter 3 2 2 2 a logic low level on this signal indicates that the UART interface can accept more data If RTS CTS handshake is disabled RTS is always active UART CTS Handshake input of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 33 If RTS CTS handshake is enabled see chapter 3 2 2 2 a logic low level on this input indicates that the MCM may transmit further data to the connected hardware If RTS CTS handshake is disabled this input is ignored 3 2 2 UART Configuration UART configuration can be divided into two sections Parameters uart baud and uart handshake configure the behavior of the UART interface itself The remaining parameters deal with the virtual connection Table 5 lists the available configuration parameters baud rate configuration uart handshake enable disable hardware handshake connect UART interface of local device with partner node uart partner dev partner node for virtual UART connection uart partner inst size of the buffer for incoming data events uart flowctl enable disable virtual connection flow control number of bytes that can be buffered in the receiver hardware uart tx fifo size number of bytes that can be buffered in the transmitter hardware Table 5 UART parameter overview 3 2 2 1 UART Baud Rate uart baud This parameter defin
34. runtime There are two solutions for such a system 1 Use the maximum bandwidth packet size e accommodates any data rate up to the maximum e causes high latency at low data rates due to packet assembly at the streaming port see Figure 17 2 Configure the streaming bandwidth before acquisition is started e allows to adapt the transfer bandwidth to the actual system requirements e data is transferred with low latency f USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page Di 3 6 4 Configuration Interface Configuration The configuration interface is not configurable It has a minimal set of parameters that is reguired for VCP operation 3 6 2 Configuration Interface Usage The configuration interface can be accessed over its software registers The layout of the software registers is defined in 3 With the VCP SDK the function vce writeRemoteRegisters Can be used to access the software registers The distribution media contains an example that changes configuration parameter str tx pktsize from user input 3 7 Registration Interface The Registration interface is not a hardware interface Instead it allows non VCP devices such as a host PC to establish a VCP connection to a specific interface on a specific device The VCP SDK automatically serves this interface so here no user action is reguired When a non VCP device is added to the system it
35. system Polarity Built in termination Handling when not used n a power RESET IN Reset input and software reset output If this pin is set to logic low level the UC1394a 1 is reset An internal 4 7 kQ resistor to 3 3V is provided on the MCM This pin should only be driven by an open drain output or a pushbutton connected to ground When software or the watchdog timer of the UC1394a 1 trigger a reset RESET IN is pulled low by the MCM for a short time Externally applied resets must have a minimum pulse width of 1us and must be driven by an open collector source An active RESETIN input immediately activates RESET OUT RESET IN can be left open if not used Polarity Built in termination Handling when not used bi directional 4 7 kQ pull up RESET_OUT This output is pulled low whenever a system reset is active thus e after power on e when RESET IN is externally pulled low e when the firmware of the UC1394a 1 performs a software reset e when the watchdog timer of the UC1394a 1 triggers a reset RESET OUT will stay low for 140ms 300ms after the reset condition is removed After that time the output is pulled high It can be used to reset external hardware Polarity Built in termination Handling when not used n a always driven leave open 7 2 2 Streaming Port Signals STR D 15 0 CAM D 15 0 Bi directional streaming port data lines for both generic interface or imaging mode When not driven a keeper bus holde
36. that an error can also be acknowledged over the I O pins This will also read out the next error code so that the ERR 2 0 in HPIC2 also changes Therefore acknowledging an error should be done exclusively by either the host or by I O pins The host can enable error notification over the HPI receiver ready condition by setting the ERR EN bit If this notification is enabled and the HPI signals a receiver ready condition there is either new data in the HPI data register or an error has occurred and can be read from ERR 2 0 Diagnostics over HPI are intended for error statistics by a local microcontroller 3 5 4 Diagnostic Interface over the LED The LED of the UC1394a 1 MCM is also connected to the output error code FIFO When an error is present in the FIFO the LED displays this error by blinking 1 to 7 times according to the error code defined in Table 16 After that the LED stays off for some time and then the sequence is repeated When an error is acknowledged by either the HPI or over the I O pins the next error code is read from the FIFO and the LED displays this error code f USER S GUIDE Date 25 October 2006 e Doc no Bridge UG k PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 47 Diagnostics over LED blink codes are provided for a fast visual error detection without additional hardware required 3 5 5 Description of Available Error Codes Table 16 lists the error codes that are used for
37. user mode DLL provides the VCP API The user accesses an interface s address space thus its software registers or receives incoming accesses to its own software registers For example the class library makes the following call to the API in order to send a pin state event to an output pin of a remote device stat writeRemoteRegisters 0 1 amp reg API level programming is more complicated than using the interface class library since it requires knowledge of the software register layout of the accessed interface documented in 3 On the other hand API level programming is more flexible When a new interface is added on a remote device its software registers can be used with the API provided that the user knows about layout of the software registers The VCP SDK comes along with a demo application This allows a quick and easy start without the need for programming Quick start examples are shown in 1 and can also be used with the UC1394a 1 MCM provided that the respective hardware is connected f USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 60 E Yirtual Connection Protocol Demo x File Output Window Diagnostics Info Device Incoming Stream Outgoing Stream 1 0 Pins UART Host Port Local Device ID 0 Set Devices Close Device m Interfaces Open All Close All TE Partner ID 1 Close G i
38. 006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 105 Q etting 6 26 respectivel io en nabled UART 115200 baud RTS CTS handshake enabled us el g O JE SH JE ds JE GIE D virtual connection to partner device enabled Se e common device parameter partner dev rt partner inst CGI t tx pktsize use dynamic packet ge c o o lt gt D 3 o o o P o N 0 ms 096 Q A O HPI isabled bit virtual connection to partner device disabled i partner dev i partner inst AsO n2 c c a lolo oo o o o o A oO D 2 Oo o o S Sloe ba ge 3 O o N o 5 o o N D o o lt X Oo 2 o z o KE o N a o 3 6 D D S 3 T lt Diagnostic interface B E m a Z ev bufsi SS S accept any instance hpi en hpi_tx_timeout 01 SISS Koko fo o o SRI Ss 3 amp C o d mE m Ns ae Bye EIN D O G lo o A 3 5 jlo sla a 2 Table 59 Predefined configuration mode 9 ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 106 7 9 11 Configuration Mode 10 13 Reserved and 14 15 Factory Default These configuration modes use a passive parameter set that minimizes signal conten
39. 16 bit word is written to the streaming port configured for transmit direction no data is sent on the IEEE1394 interface since the amount of data is less that the minimum packet size of 4 bytes The transmitted data must be a multiple of the configured transmit packet size see configuration parameter str tx pktsize in chapter 3 1 4 1 Otherwise the reaming data stays in the streaming port s transmit FIFO forever For isochronous streaming which is the default transfer method transmit operation is further limited to one packet each 125ys See also chapter 3 8 1 for further information 3 1 2 3 Streaming Port Synchronization Streaming port data transfers can be synchronized by using STR FLAGO and STR FLAG1 Synchronization is required e for receive operation in general e for transmit operation at high bandwidths 3 1 2 4 Streaming Port Synchronization in Receive Direction In receive direction STR FLAGO or STR FLAG1 must be checked to be active before data is read out of the streaming port Otherwise a FIFO underrun error will occur The code example below shows how to check for receive data assuming that the UC1394a 1 MCM is connected to a micro line C6x11CPU module as follows e STR FLAGO connected to interrupt INTO e STR FLAG1 connected to interrupt INT1 e STR RE connected to CS1 e STR CLK connected to IOSTRB single word synchronized transfers define STR_RX DATA AVATL C6X11CPU_INT_STAT amp C6X11CPU_I
40. 394 standard and should not be used f USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 24 3 1 4 7 Streaming Port Data Width str width This parameter controls the number of data bits of the streaming port number of supported STR Dxlines The data width is given in bits It can be set to e 8 bit interface one byte per clock is transferred on the streaming port STR D 7 0 are used STR D 15 8 are ignored for transmit operation and set to 00 6 for receive operation e 16 bit interface one 16 bit word per clock is transferred on the streaming port All data lines STR D 15 0 are used Please note that when 8 bit operation is configured the maximum data rate is limited See chapter 7 8 1 1 5 for details 3 1 4 8 Streaming Port Interface Type str iftype This parameter controls the function of the streaming port signals It can be set to e generic interface external hardware accesses the streaming port word by word using asynchronous or synchronous timing e imaging interface external hardware writes data to the streaming port using a pixel clock and frame line enable signals Only valid for transmit operation Please refer to chapter 3 1 1 for a description of the interface types 3 1 4 9 Streaming Port Startup Behavior str auto This parameter decides whether streaming operation is automatically started after system startup set to auto st
41. 5 Table 50 Predefined configuration mode OQ reet eens ene ER ees ee en EE Exe Y RE n ER ERE REP ax 87 Table 51 Predefined configuration mode 1 89 Table 52 Predefined configuration mode 2 91 Table 53 Predefined configuration mode EE 93 Ce USER S GUIDE Date 25 October 2006 LJ PARALLEL BUS TO IEEE1394 BRIDGE les ov P ER Orsys Page 7 Table 54 Predefined configuration mode 4 e e eeeeeeeeereeeeeeee eee eee aaa een nn 95 Table 55 Predefined configuration mode 5 uuu kua Had bod rait en tk bin Eee RS Eads DeL HRS n E UM een de 97 Table 56 Predefined configuration mode 8 99 Table 57 Predefined configuration mode 7 101 Table 58 Predefined configuration mode 8 eeeeeeeeccceeeeeeeeeeenseeeeeeeeeeeeeeeeeneneneeneeeeeeenseeeneeaees 103 Table 59 Predefined configuration mode EE 105 Table 60 Passive ele Wie UI EE 107 List of Figures Figure 1 Parallel bus to EEE 1394 Bridge overview eeeeeeeeneeeeeee 11 Figure 2 Bridge block diagram e TL oo DOT 12 Figure 3 VCP demo DEENEN iunc etat obest tata extr nC cR Eo un tina aed eds au ueni bcd ied 13 Figure 4 Streaming port block diagram reet ettet reae ka e Ras Rr 15 Figure 5 Streaming port signals in generic mode ENEE 16 Figure 6 Streaming port signals in imaging mode ENEE 16 Figure 7 UART interface block CIBO BITI sis uico ash trt sais do or ruo Y ee REA cuts EEN 25
42. 6 McBSP2 DX O3 HD3 9 10 RESET IN STR D7 McBSP2 CLKR 1 04 10 McBSP2 CLKX O5 HD5 M i12 1 022 ERRDTCT STR D McBSP2 FSR VO6 He 12 13 1 023 ERRCLR STR D9 McBSP2 FSX VO7 HD7 Jus 114 1 024 ERRO STR D10 GND VO8 HD8 HAO0 14 15 1 025 ERR1 STR D11 JTAG DSP EMU W O9 Hp 15 116 1 026 ERR2 STR D12 JTAG DSP EMUO 1 O10 HD10 16 17 UART TxD STR D13 JTAG DSP TRST O11 HD11 17 UART RxD STR D14 JTAG DSP TCK 18 19 UART RTS STR D15 JTAG DSP TDO lI O12 HD12 19 i20 UART CTS GND JTAG DSP TDI O13 HD13 20 21 GND STR WE JTAG DSP TMS 1 014 HD14 21 i22 TPAO STR RE JTAG FPGA TCK 1 015 HD15 22 23 TPAO STR CLK JTAG FPGA TDO 1 O16 HCS 23 124 TPBO STR FLAGO JTAG FPGA TDI 1 017 HRD 24 25 TPBO STR FLAG1 JTAG FPGA TMS 1 018 HWR 25 DSP XF1 1 019 26 1 021 HTRDY 1 020 HRDY HRRDY 27 28 AINO USB DP 29 AIN1 USB DN 30 AIN2 I2C SDA 31 AIN3 l2C_SCL 32 Table 24 Pinout sorted by pins i BSP independent or not used with this BSP 13 imaging mode signals not shown here ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 69 RESET IN RESET OUT Signal Generic STR DO STR D1 STR D2 STR D3 STR D4 STR D5 STR D6 STR D7 STR D8 STR D9 STR D10 STR D11 STR D12 STR D13 STR D14 STR D15 STR CLK STR WE STR RE STR FLAGO STR FLAG1 Imaging CAM D
43. 9 Table 28 UART interface sigrials roka Nano s n ou KA ANANKE Aa da ake 69 Table 29 DSP al TAG SiG air E 69 REI 6d MEDII RR RES Io SI 70 Table 31 Diagnostic signals E 70 Table 32 Ke TT 70 Table 33 power requirements E 77 Table 34 Signal levels and loads for UO pins l O 11 0 and l O 26 15 eee 78 Table 35 Signal levels and loads for I O pins l O 14 12 sse 78 Table 36 Signal levels and loads for the streaming port signals STR xxx ee 79 Table 37 Signal levels and loads for the UART interface signals UART sx 79 Table 38 RESET Ee CHE 79 Table 39 RESET OUT signal levels tut ERI pida Ein eee td Ex euet NEE ndo px cH PERF DERE EXE SERE pNTE 79 Table 40 Streaming port transmit timing parameters cceceeeeeeeeeee eee eeeeeeeeeeeeeeeeeeeteeeeeeeeenaeeeeee 80 Table 41 Streaming port receive timing parameters en 81 Table 42 Maximum achievable streaming banchwidthes AAA 82 Table 43 Streaming port transmit timing parameters imaging model 83 Table 44 HPI write timing hel 83 Table 45 HPI read timing parameters ce iba rera eau no hera EEN ESA eet 84 Table 46 UO pin timings for single I O pin virtual connection ssssesssseeerenrtttteeeeerrnrnnnnnnnnrrrrn rnrn 85 Table 47 UO pin timings for virtual connection with 8 I O pins seeeseeeeeeeeere 85 Table 48 Reset timing EE 85 Table 49 Differences between the predefined amp passive parameter sets 8
44. C1394a 1 MCM has up to 27 general purpose I O pins available They can be configured and used individually and are intended for low speed bit level I O Maximum switching speed strongly depends on IEEE1394 bus traffic and is around 1kHz A detailed description of the I O pins can be found in chapter 3 4 2 6 IEEE1394 Interface The UC1394a 1 MCM has two 400Mbps IEEE1394 ports The IEEE1394 interface connects the bridge to other devices such as other bridges or host PCs During IEEE1394 bus enumeration the bridge identifies itself as a device running the Virtual Connection Protocol VCP This guarantees Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 14 interoperability with other IEEE1394 devices and allows a Windows based host PC to recognize the bridge The host PC will then automatically load the appropriate high level driver which is included in the VCP SDK 2 7 Power Supply The UC1394a 1 MCM requires a single regulated 3 3 V power supply See chapter 7 6 for details 2 8 Configuration Operation of the UC1394a 1 MCM can be adjusted by a set of parameters one for each interface plus one set of common device parameters Adjusting the parameters is done by a configuration tool using the UART interface The UC1394a 1 MCM also has some predefined parameter sets that can be selected by the startup state of certain I O pins Device configuration
45. D 15 0 floating after HRD high Ire 15 ns 0 ns 70 ns n a asynchronous 3 a 7 8 3 I O Pin Timings Please note The timing of the virtual I O pin connections strongly depends on software processing Therefore if the default firmware is busy e g by handling other virtual connections it will take more time to control an I O pin The tables below give I O pin timings under different operating conditions 7 8 3 1 Single UO Pin Timing Measurement conditions e Two UC1394a 1 with default firmware mounted on carrier board e Default virtual connection IO 7 0 to IO 15 8 e 100 on first UC1394a is driven with a 50 duty cycle square wave signal e No other transfers or virtual connections active ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 85 Parameter Value Min Max total delay pin to pin maximum frequency for a virtual UO pin connection Table 46 I O pin timings for single UO pin virtual connection 7 8 3 2 UO Pin Timing with 8 Pins Two UC1394a 1 with default firmware mounted on carrier board Default virtual connection IO 7 0 to IO 15 8 100 on first UC1394a is driven with a 50 duty cycle square wave signal No other transfers or virtual connections active Parameter 48 us total delay pin to pin 48 us maximum freguency for a virtual UO pin connection 800 Hz Table 47 I O pi
46. EMU1 JTAG_DSP_EMUO JTAG DSP TRST JTAG DSP TCK JTAG DSP TDO JTAG DSP TDI JTAG DSP TMS Figure 32 Wiring of the DSP JTAG interface 6 7 Unused Signals Signals that are not used can be left unconnected Most inputs have pull up resistors or keeper circuits see chapter 7 2 for details For the McBSP signals external pull up resistors can be added to avoid unnecessary power consumption caused by floating inputs The same applies to the USB interface here a pull up can be added to DP and a pull down to DN 6 8 Minimal Connection Example Figure 33 shows the minimum required connections for basic operation of the UC1394a 1 MCM The configuration mode is set by the module s pull up resistors and an external jumper to 1440 or 1510 orsys USER S GUIDE PARALLEL Bus TO IEEE1394 BRIDGE Date 25 October 2006 Doc no Bridge UG Iss Rev 1 1 Page 67 RS 232 interface 3 3VO recommended for configuration and service 19 3 7 100nF 100nF 100nF 18 48 5V C 5 5V 5 5V C1 C2 PT NI tt o GND C2 100nF ea 100nF X 511 STR Do ge STR D1 Be STR D2 X 87 STR D3 X pg STR D4 X 591 STR D5 gio STR D6 STA D7 STR D8 giz STR D9 STR D10 Bre STR D11 B17 STR D12 STR D13 Bie STR D14 X STR D15 X Bo2 SIR WE CAM FEN X Bos STR RE CAM LEN STR CLK CAM CLK Xgos SIR FLAGO xX STR FLAG1
47. FO 8 16 bit Reset direction control from partner interface data mover port physical layer transceiver IEEE1394 logic Port1 Tx Streaming start stop from partner interface Control Control logic Figure 4 Streaming port block diagram 3 1 1 Streaming Port Signals The streaming port uses a generic parallel interface to transfer the data using a data width of 8 or 16 bit Data is transferred using a clock signal This allows connection of both synchronous interfaces as well as asynchronous interfaces Connector locations are listed in Table 1 Streaming port timings are described in chapter 7 8 1 By default the streaming port acts as a generic interface that can be connected to a wide range of interfaces Data will be transferred transparently without further information For use with image data sources such as cameras the streaming port can be configured as an imaging input where the incoming data is controlled by frame and line synchronization signals Frame synchronization information is transferred over IEEE1394 and is therefore available at the receiver In imaging mode the incoming data stream is synchronized to the start of the next frame after a reset of the streaming port This allows to restart streaming at frame boundaries Please note For transmit operation at bandwidths above 10 Megabytes per second usage of the synchronization flags is strongly recommended The FIFO has an output register whic
48. Figure 12 illustrates the output types Selecting a push pull output causes the output to be pulled low or high by low impedance according to the state of the I O pin An open drain output pulls down the I O pin with low impedance when the state is low logic 0 When the state is set high logic 1 the I O pin is pulled high with high impedance pull up resistor Using open drain outputs allows to connect several outputs together without signal contention On the other hand a push pull output allows more switching speed and faster low to high transitions especially at high capacitive loads 3 4 4 3 I O Pin Startup Output State io state This parameter selects the startup state of an I O pin when it is configured as an output This state is overwritten by the first incoming VCP event from the partner pin Allowed values for this parameter are e low pulled to 0 V e high pulled to 3 3 V 3 4 4 4 UO Pin Virtual Connection Control io connect This parameter defines if an I O pin generates pin state events configured as input or whether the I O pin accepts incoming pin state events configured as output The suggested default for this parameter is to enable the virtual connection Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 44 3 4 4 5 O Pin Partner Device for Virtual Connections io partner dev This parameter defines the partner devi
49. L Bus TO IEEE1394 BRIDGE Date 25 October 2006 Doc no Bridge_UG Iss Rev 1 1 Page 90 7 9 3 Configuration Mode 2 3 MBps Predefined Configuration This configuration can be used for standalone UC1394a 1 configurations with medium to high bandwidth requirements Parameter name Device common parameters partner dev Da ver Dga rev vcp ver sir sir sir sir str_ str_ str_ str_ str_ str_ str_ tx_pktsize dir ch xfertype partner dev partner inst width iftype auto blksize frmsync io dir io connect io partner dev io partner inst Setting own ID is read from pins l O 18 16 partner ID is read from pins l O 21 19 4 indicates current FPGA revision indicates current firmware version indicates current firmware revision 001000446 VCP V1 4 Streaming port 400 bytes 100 guadlets str idis read from pin O26 use device id partner dev isochronous streaming use common device parameter partner dev 16 bit generic interface auto start enabled 00 bytes 100 quadlets no sync pattern UO pins 0 7 input open drain output high virtual connection to partner pin enabled use common device parameter partner dev 8 15 respectively io connect io partner dev enabled I O pins 8 15 output open drain output virtual connection to partner pin enabled use common device parameter partner dev 0 7 respectively io partner inst io state io connec
50. O CAM D1 CAM D2 CAM D3 CAM D4 CAM D5 CAM D6 CAM D7 CAM D8 CAM D9 CAM D10 CAM D11 CAM D12 CAM D13 CAM D14 CAM D15 CAM PCLK CAM FLAGO CAM FLAG1 Table 26 Streaming port signals Pin number UART RTS UART OTS Pin number Table 29 DSP JTAG signals ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 70 Table 31 Diagnostic signals Table 32 IEEE1394 signals ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page v 7 2 Individual Signal Description This chapter briefly describes the individual signals of the MCM for each signal group interface and lists their electrical properties Most of the signals are described in the respective sections of chapter 3 Timings and allowed voltage levels are shown in chapters 7 7 and 7 8 7 2 1 Power Supply and Reset Signals 3 3V Power supply for the UC1394a 1 These pins provide the power supply for the UC1394a 1 All necessary internal voltages are generated from this voltage Please refer to chapter 7 6 for voltage limits and recommended operating conditions Polarity Built in termination Handling when not used n a power GND These pins are the power supply and signal ground pins of the UC1394a 1 They should be directly connected to the ground plane of the
51. O standards 5V TTL 3 3V LVTTL 2 5V CMOS High input level 20V 55V Low input level High output level in 2 Low output level 0 maximum DC load Table 37 Signal levels and loads for the UART interface signals UART xxx 7 7 4 Reset Signals RESET IN is an open drain signal that is used as an input and that is driven low for about 1us in case of a software reset Compatible I O standards 3 3V LVTTL High input level min 2 31 V Low input level max 0 99 V Table 38 RESET_IN signal levels RESET_OUT is a push pull output which is directly driven from the onboard reset generator Value 3 3V LVTTL 2 5V CMOS Parameter Parameter Compatible I O standards High output level Low output level min 2 64 V maximum DC load maximum DC load Table 39 RESET_OUT signal levels ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 80 7 7 5 Other Signals The remaining signals are intended to be used with the appropriate interfaces only For example the FPGA JTAG signals should only be used with programming eguipment from XILINX so that correct signal levels and loads are guaranteed The interfaces for use with dedicated eguipment are IEEE1394 signals USB lC signals JTAG signals for the DSP JTAG signals for the FPGA 78 Signal Timings 7 8 1 Streaming Port Timings 7 8 1 1 Generic Interface Isoc
52. Partner ID pen 1 0 Pins Partner ID Open GSE Open Close BOSE Open UART Partner ID ene k l k ke E Host Port Partner ID Device ID 1 opened Figure 22 VCP demo application 5 2 Using VCP Without the SDK The VCP SDK allows accessing the bridging kit 1 or the UC1394a 1 MCM from a Windows based PC using the Microsoft driver stack However when a different driver stack another operating system or even a non PC hardware is used the VCP SDK can t be used and the VCP must be implemented on the host system according to 3 This can be done in two ways 1 Partial implementation The host only implements the software registers of the interfaces it wants to use No Configuration ROM entries and no descriptor lists are required The software registers must be located at the same address as those of the accessed device and the host must connect to the remote device using the Registration interface see chapter 3 7 2 Full VCP implementation including configuration ROM entries device and parameter descriptor lists This method doesn t require host registration but requires more implementation effort A detailed description of how to implement the VCP is given in 3 Ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG iu PARALLEL Bus TO IEEE1394 BRIDGE a De i14 Orsys Page 61 6 Hardware Implementation Guidelines This chapter shows how t
53. RDY output on HRRDY HTRDY together with the RRDY condition e hpi handshake set to no handshake no TRDY signaling To enable transmitter ready signaling the host must set the TRDY EN bit Then HTRDY or HRRDY HTRDY is active low when the HPID register can accept at least two more data words RRDY EN This bit controls whether the receiver ready condition is signaled on HRDY HRRDY Please note that e the HRDY HRRDY pin is disabled when hpi handshake is set to no handshake e the HRDY HRRDY pin is shared with the transmitter ready condition when hpi handshake is set to common handshake and with error signaling when ERR EN is set to 1 see description or ERR EN for details To enable receiver ready signaling the host must set the RRDY EN bit Then HRDY HRRDY is active low when the HPID register holds valid data ERR EN This bit controls whether error conditions are signaled over the HPI signal HRDY HRRDY Please note that this signaling is disabled when the configuration parameter hpi handshake is set to no fy USER S GUIDE Date 25 October 2006 Doc no Bridge UG uM PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 Orsys Page 37 handshake The host must set ERR EN to enable error signaling When error signaling is enabled HRDY HRRDY will get active low whenever an error occurs The host can enable this feature to get informed about errors Alternatively the host can poll the ERRDTCT
54. S 14 2 11 Configuratlon Interface sss cie Roh ao ae cei anna o anana ENeEE 14 2 12 Registration Interface EN 14 3 DETAILED INTERFACE DESCRIPTION nn oss e n ha ka ks k nun nnn 15 3 1 Stre ming E Vu E 15 3 1 1 Streaming Be ge z 3 ae5a3adioskadikadzi S n ced oscaaans ch ugue sa so Seas add eS n pasa uou usa deni nde 15 3 1 2 Streaming Port ODOFCailOIn usce irieceip Stt bees Sent a dux ra dus a cus sua GR vu dub k ra da zona bd RE Ea pS 19 3 1 3 Controlling Streaming Port Operation over VCP eeeeeeeeeeee een eee 20 3 1 4 Streaming Port Configuration Pes 21 32 UART E 24 32d UART SIGNAS seien E a E 25 3 2 2 VART COMMGUrATON eegene 26 3 3 Host Port Interface API deeg rentrer iniri AKA KA RAKA A ASN RAKA AA KARA EAA SEENEN 28 LOO UsER s GUIDE Date l 25 Mrd 2006 LJ PARALLEL BUS TO IEEE1394 BRIDGE eta Orsys Page 3 a tee 29 me AP Meet le Tu EE 31 CH E EE 34 Mel S 39 34 1 VO Pin I zoo b t 41 3 4 2 I O Pin Alternative FunctionS EEN 41 3 43 WO Pin Startup State Options seu ENEERSEEEEEEREEEETEKESENEENERNEEEEESESNEEEEEEIEESEEE name pu a rE Ek a an GE 42 3 4 4 JR Pin Configuration eerste 43 3 9 Diagnose un EEN 44 3 5 1 Diagnostic Interface over IEEE1394 ieie eren nere teet rnt nn tci 45 3 5 2 Diagnostic Interface over Dedicated I O Pins 45 3 5 3 Diagnostic Interface over the PPI rnit eret ee rette putas d Ges o ene ue tii need de etes 46 3 5 4 Diagno
55. SR_INTO l 0 define STR_READ volatile INT32U C6X11CPU CS1 BASE wait for data while STR RX DATA AVAIL read data from streaming port pBuffer STR READ block synchronized transfers define STR RX BLOCK AVAIL C6X11CPU INT STAT amp C6X11CPU ISR INT1 0 define STR READ volatile INT32U C6X11CPU CS1 BASE define STR BLKSIZE 10 10 bytes 5 16 bit words Note MCM must be configured accordingly wait for next data block while STR RX BLOCK AVAIL read one block of data from the streaming port Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 20 for i 0 i lt STR BLKSIZE i pBuffer STR READ Please note Due to the flag timing data transfer bandwidth is limited when STR FLAGO is checked before each access Therefore for operation with STR CLK frequencies above 10 MHz block based synchronization with STR FLAG1 is required When using STR FLAG1 for synchronization streaming port operation should follow these guidelines e Starting and stopping transfer on the externally connected hardware must be done at block boundaries only e Before resetting the streaming port over VCP the external hardware must be stopped 3 1 2 5 Streaming Port Synchronization in Transmit Direction In transmit direction data written to the streaming port is buffered in the stream
56. T of the configured partner device and sends character and flow control events using the local interface instance The suggested default for this value is 0 since typically there is only one UART interface per device 3 2 2 0 UART Transmit Packet Size uart 1x pktsize This parameters defines how many UART characters are transferred to the partner device in one VCP character event Allowed values are 1 to 2040 characters per event Further a special value for this parameter exists When uart tx pktsize is set to variable packet size as many characters as possible are transferred dynamic packet size The suggested default value for this parameter is variable packet size when another MCM is used as partner device When a PC is used as partner device uart tx pktsize should be set to its maximum value of 2040 together with a timeout see chapter 3 2 2 7 This limits the maximum event rate and is required because flow control cant be used due to the limited real time behavior of Windows Alternatively smaller packet sizes or less timeout can be used if a modified event FIFO setting on the PC is used Please refer to the description of the function VCP_EnableEventFifo in 7 f USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 28 3 2 2 7 UART Transmit Timeout uart tx timeout This parameter works in conjunction with fixed transmit packet sizes
57. The VCP can be used in standalone configurations with two or more embedded systems where or in a host based system where one end point of a virtual connection is implemented in software IEEE1394 bus VCP device 1 VCP device 1 VO pin 1 WO pin 1 input output Virtual connection over IEEE1394 Figure 19 Virtual connection between two hardware interfaces Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG RSI PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 58 IEEE1394 bus VCP device 1 VO pin 1 output Virtual connection Host PC I 1 VCP SDK or over IEEE1394 other VCP implementation Figure 20 Virtual connection between a host PC and a hardware interface When using the VCP with the UC1394a 1 MCM and or the VCP SDK no special knowledge of the VCP is required However below is a short overview of how the VCP is implemented VCP devices have an entry in the device s configuration ROM that tells that this device has the VCP implemented Further the configuration ROM of these devices has an entry that points to the base address of the VCP specific register space The register space of a VCP device usually consists of Adevice descriptor list that contains all interfaces that are available on this device e Several parameter descriptor lists one for each interface that reflect the current settings of this interface e A set of softwa
58. ace are sent Further it defines from which device events are accepted and therefore from which device characters are transmitted on the UART interface Allowed values for this parameter are e The device ID of a remote device 0 6210 e Broadcast Accept any device Incoming UART data will be sent to all devices in the network via a IEEE1394 broadcast transaction Incoming data over IEEE1394 will be accepted from all devices Use common partner device the partner ID for the virtual UART connection will be taken from the common parameter partner dev see chapter 4 3 2 The suggested default for this value is to use the common partner device 3 2 2 5 UART Virtual Connection Partner Interface Instance uart partner inst This parameter defines the interface instance interface number within the partner device for virtual UART connections This parameter is used for addressing the partner interface within the partner device outgoing character events flow control events e filtering out the allowed partner for incoming character events The instance of an interface is a simple number starting at 0 The first UART interface of a device has an instance of 0 the second of 1 etc Together with uart partner dev this parameter defines the virtual connection of this UART interface One special value is available for this parameter Accept any UART The UART interface accepts character and flow control events from any UAR
59. ardware change transfer direction of the external hardware change transfer direction at the streaming port reset the streaming port start streaming operation at the connected hardware Controlling the external hardware enable disable direction can be implemented for example by using O pins 3 1 4 Streaming Port Configuration Operation of the streaming port is affected by a number of configuration parameters These parameters can be adjusted using the UART interface and the configuration tool or over VCP Table 2 lists all parameters for the streaming port sorted by importance The subsequent sections describe the streaming port parameters The configuration process is described in chapter 4 transfer direction for streaming data partner device for streaming data width ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 rsys Page 22 str iftype identifies the type of hardware interface on the streaming port auto start feature str blksize transfer block size on streaming port interface synchronization bit pattern for frame start imaging interface only Table 2 streaming port parameter overview 3 1 4 4 Streaming Port Transmit Bandwidth Packet Size str tx pktsize This parameter defines the amount of data that can be transmitted in one second Since data is transferred in packets the packet size defines the transmit bandwidth For rece
60. arity Built in termination Handling when not used active high pull up FPGA JTAG_FPGA_TMS Test mode select Polarity Built in termination Handling when not used pull up FPGA ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page SEL 7 2 8 External Flag The external flag pin of the DSP is currently not used by the Parallel bus to IEEE1394 Bridge DSP XF1 External Flag output Polarity Built in termination Handling when not used active high n a always driven 7 2 9 Analog Inputs The analog inputs of the DSP are currently not used by the Parallel bus to IEEE1394 Bridge AIN 3 0 ADC inputs 7 2 10 USB Signals The analog inputs of the DSP are currently not used by the Parallel bus to IEEE1394 Bridge USB DP Positive USB data line Polarity Built in termination Handling when not used bi directional high active 10kQ pull up recommended USB_DN Negative USB data line Polarity Built in termination Handling when not used bi directional 10kQ pull down recommended 7 2 11 FC Signals The I C interface is currently not used by the Parallel bus to IEEE1394 Bridge I2C SDA Serial Data Direction Polarity Built in termination Handling when not used bi directional high active 4 7kO pull up lac SCL Serial Clock Polarity Built in termination Handling when not used bi directional
61. art or if streaming must be enabled by the partner device manual start Streaming control by the partner device is always possible independent of str auto The suggested default value for this parameter is to use manual start especially when a PC with the VCP SDK is used as partner device 3 1 4 10 Streaming Port Block Size str blksize This parameter defines the block size for transfers between the streaming port and external hardware independent of the packet size on the IEEE1394 network str blksize is specified in bytes However only multiples of two bytes are allowed Minimum block size is two bytes maximum block size is 4096 bytes equal to the FIFO size In receive direction a low level on STR FLAG1 or CAM FLAG signals the availability of at least one block of data In transmit direction a low level on STR FLAG1 or CAM FLAG signals that the streaming port can accept at least one more block of data from external hardware Block based data transfers are faster than single word transfers since the availability of data or space for data needs only the be checked once per block See also chapters 3 1 1 and 3 1 2 3 for details on STR FLAG1 behavior 3 1 4 11 Streaming Port Frame Synchronization Pattern str frmsync This parameter is used when the streaming port is configured as an imaging interface see str iftype The first packet of a frame contains the str frmsync bit pattern in its header sy field see 4 All othe
62. ased synchronization with STR FLAG1 is required When using STR FLAG for synchronization streaming port operation should follow these guidelines e Starting and stopping transfer on the externally connected hardware must be done at block boundaries only e Before resetting the streaming port over VCP the external hardware must be stopped 3 1 3 Controlling Streaming Port Operation over VCP Streaming operation can be controlled over VCP The configured partner interface can control the following aspects of streaming operation e Start and stop of streaming operation e reset of the streaming port e direction of the streaming transfer 3 1 3 1 Start and Stop of Streaming Operation Starting and stopping streaming transfers controls the data transfer between the FIFO and the IEEE1394 chipset In transmit direction operation is started and stopped at packet boundaries in order to prevent invalid packets on the IEEE1394 interface Receive operation is started and stopped immediately f USER S GUIDE Date 25 October 2006 e Doc no Bridge UG k PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 21 Controlling streaming port operation in this way allows to implement a simple flow control mechanism When streaming operation is stopped data is still transferred between external hardware and the streaming port FIFO In transmit direction external hardware will fill the FIFO until it is stopped by a high
63. bit in the HPIC2 register Please note that the HRDY HRRDY signal can be shared with the receiver ready condition see description of RRDY EN and the transmitter ready condition see description of TRDY EN ID This bit field has a different meaning for each access direction e When reading HPIC1 ID holds the device ID of that device that supplied the current data in the HPID register The ID bit field is updated when the associated data is read Therefore the ID must be read before the data is read The ID field is used when both the partner device and the local device are configured for dynamic addressing by configuration parameter hpi partner dev e When writing to HPIC1 ID determines the destination ID for the next data that is written to HPID When the configuration parameter bo partner dev is set to dynamic addressing this ID will be used to address the partner device for this data The host must set this bit field to the ID of the device that should receive the next data before the data itself is written to the HPID register ID needs to be set only when the destination ID changes Subsequent writes to HPID will use the same ID The ID bit field is FIFO buffered such as the HPI data register HPID for both directions HPICA This bit is the HPIC address bit If set to 0 HPIC1 is selected and the remaining bits of this register behave as described above When HPICA is set to 1 HPIC2 is selected and the remaining bits behave as d
64. carrier PCB 7 5 Soldering Process The UC1394a 1 is designed to be placed and soldered like an integrated circuit allowing mass production The UC1394a 1 can be soldered using vapor phase or reflow processes just like BGA packages Figure 36 shows an example of a temperature curve that was measured during production of the UC1394a 1 using a lead free reflow process Please note that the UC1394a 1 starting with S N 012231 is RoHS compliant and therefore produced using a lead free process For mounting older versions of the UC1394a 1 please contact Orsys Unless otherwise noted on the packaging baking is required before soldering Figure 36 Soldering temperature example 7 6 Power Requirements 450mA Table 33 power reguirements Date 25 October 2006 gt USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 78 7 7 Signal Levels and Loads In general all digital logic pins are compatible with 3 3 V LVTTL This is the preferred UO standard for all logic signals of the UC1394a 1 Other signal levels are only required by the IEEE1394 and the USB interface CAUTION Applying more than 3 6 V to inputs that are not 5 V tolerant will damage the device 7 7 1 VO Pin Signals These signals are connected to the FPGA They use a 5V input tolerant LVTTL UO standard However three of them can be connected to the DSP s RTC and are therefore not allo
65. ce for this I O pin Together with o partner inst this parameter defines the virtual connection of this pin Allowed values for this parameter are e The device ID of a remote device 0 6210 e Accept any device The I O pin accepts pin state events from any device configured as input and sends pin state events as broadcasts configured as output Use common partner ID The partner device ID is taken from the device parameter partner dev see chapter 4 3 2 The suggested default for this parameter is to use the common partner ID 3 4 4 6 UO Pin Partner Pin for Virtual Connections io partner inst This parameter defines the interface instance that is used as partner for this UO pin The interface instance is the number of the I O pin For example I O pin O has an interface instance of 0 etc Together with o partner dev this parameter defines the virtual connection of this pin One special value is available for this parameter e Accept any Pin The I O pin accepts pin state events from any I O pin of the configured partner device if configured as output or sends pin state events to the same UO pin if configured as input The suggested default for this parameter is to set it to the own pin number thus jo partner inst of O0 is set to jo partner inst of l O1 is set to 1 and so on 3 4 4 7 I O Pin Presence Control io enable This parameter is not writeable Instead it is controlled by the alternative functions of the I
66. defined by hpi suspend When the HPI receive buffer fill level drops below a specific level defined by hpi resume the receiving device sends a start request to the transmitting device to re enable data transfer In order to use this feature the partner device must be real time capable so that it can disable transmission within a reasonable time The suggested default value for this parameter is to disable flow control when a PC is used as partner and to enable flow control when another MCM is used as partner Flow control is not available with the VCP SDK due to the limited real time behavior of Windows 3 3 2 12 HPI Buffer Fill Levels for Flow Control hpi rx suspend hpi rx resume These parameters define at which fill levels the receiver suspends and resumes transmission for a virtual connection hpi rx suspend defines the fill level in bytes which generates a stop event for the transmitting device so that the transfer is suspended hpi rx resume defines the fill level in bytes which generates a start event for the transmitting device so that the transfer is resumed To use this feature hpi rx flowctl must be set to enabled The suggested default values are hpi rx bufsize hpi tx pktsize for hpi rx suspend and hpi tx pktsize for hpi rx resume 3 3 2 13 HPI Hardware FIFO Sizes hpi rx fifo size hpi tx fifo size These parameters are read only They define how many data words can be buffered by the HPI hardware and are used for inf
67. device 0 can use I O pin 3 on device as a partner interface and vice versa This defines a virtual connection between the two I O pins 2 2 Streaming Port The streaming port is the main interface of the bridge It allows unidirectional high speed data transfers of up to 32 768 000 bytes per second The interface is built as a 8 or 16 bit parallel interface that can be accessed by external hardware using either synchronous or asynchronous access timings Streaming data is FIFO buffered so that external hardware can operate independent of the IEEE1394 bus A detailed description of the streaming port can be found in chapter 3 1 2 3 UART Interface The UART interface is used for two purposes It can be used for device configuration using a host PC running the configuration tool or it can be used as a general purpose UART interface e g for command and status exchange between the bridge and external hardware A detailed description of the UART interface can be found in chapter 3 2 2 4 Host Port Interface HPI The Host port interface is a parallel 8 or 16 bit interface intended for low to medium speed control and status exchange with an external host Transfer bandwidths strongly depend on IEEE1394 bus traffic and allow up to around 500KBps The HPI supports dynamic addressing so that different devices can be addressed by the host without reconfiguration A detailed description of the HPI can be found in chapter 3 3 2 5 LO Pins The U
68. dwidth UC1394a 1 MCM standalone 16 384 000 byte s bandwidth UC1394a 1 MCM standalone 32 768 000 byte s bandwidth MOM carrier board 32 000 byte s bandwidth MOM carrier board 320 000 byte s bandwidth MOM carrier board 3 200 000 byte s bandwidth MOM carrier board 32 768 000 byte s bandwidth reserved reserved reserved reserved reserved customized parameter set customized parameter set with UART configuration option 4 1 1 Customized Configuration When configuration mode 14 or 15 is selected the UC1394a 1 MCM uses a customized configuration set that is stored in a dedicated area of the MCM s flash memory In factory default configuration this memory is cleared and the MCM uses a passive configuration as documented in chapter 7 9 11 This allows for integration into arbitrary hardware environments To set up customized configuration the module must be started with configuration mode 15 In this mode the UART interface is reserved for communication with the configuration tool Incoming data on the UART interface is interpreted as configuration commands However UART character events from VCP are still output on the UART interface All parameters can be set up by the configuration tool and can be tested When the configuration has been successfully verified it can be saved to the flash memory of the MCM The configuration tool also allows to save the configuration parameters to a file so that this file can be used for conf
69. e CAM FEN works as a clock enable thus data can only be written to the streaming port when CAM FEN is active high Together with CAM LEN CAM FEN works as a clock enable for CAM PCLK For correct transmission of synchronization information CAM FEN must be inactive low between two picture frames e for atleast 1 period of STR PCLK if str tx pktsize is set to 4096 bytes 4096 sr pede se 125 us for other settings of str tx pktsize e Tor at least inf See chapter 3 1 4 1 for a description of configuration parameter str tx pktsize Example str ix pktsize is set to 520 bytes 4 160 000MBps 4096 Required idle time between two picture frames inf 520 j 125 us int 7 877 125 us 7 125 us 875 us When the streaming port is configured for imaging interface mode and receive direction CAM FEN will be ignored and no streaming operation is possible CAM LEN When the streaming port is configured for imaging interface mode and transmit direction from the streaming port to the IEEE1394 network CAM LEN is the high active line enable signal that indicates that one line of a picture frame is currently being transferred Together with CAM FEN it enables that data is clocked into the streaming port Data can only be clocked into the streaming f USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 18 port when CAM LEN is active high
70. e functions for HRDY HRRDY u 000000000 nn nennen nnn nnns 31 Table 8 HPI parameter OVErvieW eee eee eee KKK KKK KK KKK KKK K Kn 32 Table 9 HPI address map in 16 bit configuration is oriretur so ege 34 Table 10 HPI address map in 8 bit configuration nna rire rre ene kis 35 Table 11 HPI register layout in 16 bit configuration lt lt lt 35 Table 12 HPI register layout in 8 bit configuration eee 35 Table 13 I O pin ASSIGNING eessen 41 Table 14 UO pin parameter overview sssssssssssseseeeennneeennnen nennen K R KERR nnne nennen 43 Table 15 Diagnostics interface pin assignments eseeeseeeeeeeeeeeeeenene nnne 46 Table 16 Available error 660685 pee SEP EENEG 47 Table 17 Available detailed error codes ccccceeeeseeecneceeeeeeeeeeeseeeeeeeeeeeeeesesnsneeeeeeeeseneneeseessaeeees 49 Table 18 Diagnostic interface parameter overview esseee mm 50 Table 19 Available configuration modes cnin tetti ehem Ex Rob EM La Rr ERR D Eng 54 Table 20 Common device parameters overview EE 55 Table 21 Pinning of the IEEE1394 CONNECtoTS eee ener 61 Table 22 IEEE1394 connector part numbers iei ret senex i REB Ex SER Fe rade ER PER EE EEE UE 61 Table 23 Required cable connection to a host PC 65 Table 24 Pinout sorted BY DIIS sso Eegeregie 68 Table 25 Power supply and Mee TE 69 Table 26 Streaming een S 31s sedi C EE 69 Table 27 VO pin SIGMA E 6
71. e permanently stored in flash memory These configurations can be selected by a hardware setting called configuration mode On the UC1394a 1 MCM configuration mode is selected by the startup state of I O pins 25 22 see 6 3 for wiring examples Table 19 lists the available configuration modes They are grouped into four sections e Predefined parameter sets for using the UC1394a 1 MCM standalone with other UC1394a 1 MCMs configuration mode 0 to 4 e Predefined parameter sets for usage with the bridging kit 1 and a PC as partner device running VCPDEMO configuration mode 5 8 ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 54 e A customized parameter set for individual system configuration configuration mode 14 and 15 e A passive parameter set that is used if a reserved configuration mode is selected or if the customized parameter set is invalid Since the customized configuration is not present when the modules are shipped the passive parameter set is the factory default for configuration mode 14 and 15 This also prevents signal contention at the first startup in a customized environment Table 19 gives an overview of the available configuration modes A detailed listing of all parameters for each mode is contained in chapter 7 9 UC1394a 1 MCM standalone 320 000 byte s bandwidth UC1394a 1 MCM standalone 3 200 000 byte s ban
72. e used for standalone UC1394a 1 configurations with low bandwidth requirements Parameter name Device common parameters partner dev Da ver Dga rev vcp ver str tx pktsize str dir str ch str xfertype str partner dev str partner inst str width str iftype str auto str blksize str frmsync io dir io connect io partner dev io partner inst Setting own ID is read from pins l O 18 16 partner ID is read from pins l O 21 19 4 indicates current FPGA revision indicates current firmware version indicates current firmware revision 001000446 VCP V1 4 Streaming port 4 bytes 1 quadlet str idis read from pin O26 use device id partner dev isochronous streaming use common device parameter partner dev 16 bit generic interface auto start enabled bytes 1 quadlet no sync pattern UO pins 0 7 input open drain output high virtual connection to partner pin enabled use common device parameter partner dev 8 15 respectively io connect io partner dev enabled I O pins 8 15 output open drain output virtual connection to partner pin enabled use common device parameter partner dev 0 7 respectively io partner inst io state io connect io partner dev io partner inst io en O pins 16 26 input open drain output virtual connection to partner pin disabled use common device parameter partner dev UART Date 25 October 2006 e USER S GUIDE Doc n
73. eature is useful if the end user must be able to change the partner ID e g when the end user builds a pure embedded system that consists of several MCMs When using this option the partner ID is restricted to values of 0 7 To use this option configuration parameter partner dev must be set to read from I O pin Please note that this feature is still available even when the HPI is used instead of the I O pins since the I O pins are sampled before the HPI is enabled The partner device ID is encoded as follows 1 019 partner device ID Bit 0 1 020 partner device ID Bit 1 1 021 partner device ID Bit 2 partner device ID Bit 3 5 are set to 0 3 4 3 3 Setting the Configuration Mode over UO Pins The configuration mode is a basic setting that is always used independent of the configuration Therefore setting up the configuration mode must be done in any implementation See also chapter 6 3 for wiring examples The available configuration modes are described in chapter 4 1 The configuration mode is read from 1 O 25 22 as follows 1 022 configuration mode Bit 0 1 023 configuration mode Bit 1 1 024 configuration mode Bit 2 1024 1 025 configuration mode Bit 3 3 4 3 4 Setting the Streaming Direction over I O Pins This feature is used by the bridging kit 1 to allow quick start examples without configuration required It can also used for systems where the streaming direction is not known during production but later on
74. ef overview of the module and its interfaces Chapter 3 describes each interface in detail Chapter 4 describes how to configure the module Chapter 5 describes the protocol that is used for communication between modules Chapter 6 shows how to integrate the module in custom hardware Chapter 7 lists the technical data of the module Chapter 8 explains the abbreviations used in this document Chapter 9 contains a list of reference documents that contain further information 1 2 Documentation Overview This chapter lists the documentation from Orsys that is shipped together with the Parallel Bus to IEEE1394 Bridge Further documents from other vendors are listed in chapter 9 and are referenced throughout the document in square brackets Parallel Bus to IEEE1394 Bridge User s Guide Bridge vc pat this document Describes the function of the UC1394a 1 MCM when equipped with the streaming board support package BSP This is the recommended starting point for reading Parallel Bus to IEEE1394 Bridging Kit User s Guide 1 Bridging Kit vc pat Describes the Bridging Kit Complete system for quick and easy start with the UC1394a 1 mounted on a Carrier board Listed here for reference only Protocol specification Virtual Connection Protocol 3 vcp spec pat Describes the protocol that is used for communication over IEEE1394 Required for advanced programming with the VCP SDK or for own VCP implementations on embedded systems or non Windows
75. en UART_RxD Receive data input of the UART interface Polarity Built in termination Handling when not used pull up FPGA UART_RTS Handshake output of the UART interface ready to send See chapter 3 2 1 for a functional description Polarity Built in termination Handling when not used n a always driven Ly UsER s GUIDE Date 25 October 2006 VS PARALLEL Bus To IEEE1394 BRIDGE re gt Orsys Page 78 UART CTS Handshake input of the UART interface clear to send See chapter 3 2 1 for a functional description Polarity Built in termination Handling when not used pull up FPGA 7 2 5 EEE1394 Signals TPA 1 0 TPA 1 0 TPB 1 0 TPB 1 0 Signals for the IEEE1394 cable twisted pairs A and B Built in termination Handling when not used 1100 differential 7 2 6 McBSP Signals Please note the McBSP Signals are currently not used with the Parallel bus to IEEE1394 Bridge McBSP 2 0 DR Receive data or general purpose input McBSP 2 0 DX Transmit data or general purpose output McBSP 2 0 CLKR Receive clock or general purpose I O Polarity Built in termination Handling when not used bi directional programmable 10k pull up to 3 3V recommended McBSP 2 0 CLKX Transmit clock or general purpose I O McBSP 2 0 FSR Receive frame synchronization or general purpose I O Polarity Built in termination Handling when not used bi directional programmable 10k pull up
76. environments Virtual Connection Protocol API 7 vcexetman pat Describes how to use the Windows based VCP SDK Required for software development on a Windows based PC 1 3 Notational Conventions Names of registers bit fields and single bits are written in capital letters Example LLC VERSION Names of signals are also given in capital letters active low signals are marked with a at the beginning of the name Example RESETIN Configuration parameters and function names are written in italic typeface Example dev id source code examples are given in a small fixed width typeface Example int a 10 Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 9 The members of a bit field or a group of signals are numbered starting at zero which is the least significant bit Example CFG 4 0 identifies a group of five signals where CFGO is the least significant bit and CFG4 is the most significant bit If necessary numbers are represented with a suffix that specifies their base Example 12AB15 is a hexadecimal number base 16 hexadecimal and is equal to 477910 The bit fields of a register are displayed with the most significant bit to the left Below each bit field is a description of its read write accessibility and its default value 15 lt 12 1 9 8 7 5 3 2 1 0 D e E 6 4 A B
77. es the baud rate of the UART interface It can be set to e 19200 baud e 38400 baud e 115200 baud 3 2 2 2 UART Handshake uart_handshake This parameter controls the handshake type on the UART interface It can be set to e none no handshake used e RTS CTS handshake Please refer to the signal description in chapter 3 2 1 to see how this parameter affects operation of UART_RTS and UART_CTS f USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 27 3 2 2 3 UART Virtual Connection Control uart connect This parameter is used to establish a virtual connection of the local UART interface to a UART interface on a remote device If virtual connections are enabled incoming UART data will be sent over IEEE1394 to the configured partner device see uart partner dev uart partner inst On the partner device this data will be output on its UART interface if the partner device also has virtual connections enabled For receive direction if virtual connections are enabled UART character events from the partner device will be transmitted on the local UART interface The suggested default setting for this parameter is to enable virtual connections 3 2 2 4 UART Virtual Connection Control Partner Device uart partner dev This parameter defines the partner device for virtual UART connections It defines the device to which the characters received on the UART interf
78. escribed in the following chapter The host uses HPICA to switch between HPIC1 and HPIC2 The HPICA bit is present in both registers so that it is always accessible independent of which register is selected When writing to HPIC1 the HPICA bit is modified after the access Therefore the current write access is not affected by a change of the HPICA bit Code example define HPID HPI BASE ADDRESS 0 HPI data register define HPIC1 HPI BASE ADDRESS 1 HPI control register 1 define HPIC2 HPI BASE ADDRESS 1 HPI control register 2 define HPIC3 HPI BASE ADDRESS 2 HPI control register 3 carrier board HPI register bit definitions define PICX HPICA 0x8000 HPICA bit define HPICX HPIC1 0x0000 HPICA setting for HPIC1 HPICA is present in HPIC1 and HPIC2 define HPICX HPIC2 0x8000 HPICA setting for HPIC2 HPICA is present in HPIC1 and HPIC2 define HPIC1 RRDY EN 0x0040 Receiver ready handshake enable define HPIC2 ERRDTCT 0x0008 error detect error acknowledge define HPI READ reg volatile unsigned int reg define HPI WRITE reg val volatile unsigned int reg val get currently addressed HPIC register unsigned int uiReg HPI_READ HPIC1 if current state of HPICA is not known use this to determine which register is selected if uiReg amp HPICX HPICA HPICX HPIC2 ERRDTCT is cleared by setting it so clear this bit
79. g HPI isabled bit none I O 21 20 enabled virtual connection to partner device disabled use common device parameter partner dev gt S 9g 9 a gt hpi handshake hpi connect hpi partner dev hpi partner inst hpi tx pktsize use dynamic packet size hpi tx timeout hpi ev bufsize hpi rx bufsize hpi flowctl hpi suspend isabled 096 hpi rx fifo size hpi tx fifo size hpi resume alolalolalrlo olo olo o R3 olola Diagnostic interface no hardware signaling diag_connect disabled diag partner dev use common device parameter partner dev diag partner inst accept any instance Configuration interface accept any device accept any instance Q W S S b cfg partner dev cfg partner inst cfg ev bufsize C1 Registration interface reg partner dev accept any device reg partner inst accept any instance Table 60 Passive configuration a Date 25 October 2006 USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 108 8 List of Abbreviations and Acronyms Used in This Document API BSP CPU DSP FIFO firmware FPGA HPI FC KB KBps LED LLC LSB MCM MB MBps Mbps McBSP MSB n a quadlet ROM SDK TI UART VCP application programming interface board support package a combination of software and FPGA design that provides a dedicated functionality to the UC1394a 1 Central Processing Unit processor D
80. h increases the FIFO size to 2049 words UsER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 rsys Page 16 UC1394a 1 UC1394a 1 data lines data lines STR D 15 0 CAM D 15 0 Streaming control lines Streaming Synchronization flags ISTR FLAGO0 ISTR FLAG1 Figure 5 Streaming port signals in generic Figure 6 Streaming port signals in imaging mode mode MCM connector pin CAM DO CAM D1 E S CAM D3 B6 B10 CAM D6 B9 STR_D7 CAM D7 STR D13 CAM D13 B17 Table 1 Streaming port connector pin assignments STR D 15 0 CAM D 15 0 These are the data lines of the streaming port They carry 8 or 16 bit of streaming data between user hardware and the IEEE1394 network If the streaming port is configured for receiving data from the IEEE1394 network STR D 15 0 are tri state outputs controlled by STR RE Image mode is not allowed for receive direction When configured for 8 bit receive operation STR D 15 8 are always driven low In transmit direction STR D 15 0 or CAM D 15 0 are inputs Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 117 STR WE When the streaming port is configured for generic interface mode and transmit direction from the streaming port to the IEEE1394 network STR WE is used to wri
81. he corresponding cycle will be empty thus no packet is transmitted Figure 17 shows an example for this Ef FireSpy Recorder E Dl xl File Search FireSpy Recorder View e ee lelelcl lge 134129640 of 120 MB ajaj dies drlzlslslzlsl Time View 8 mmm E a mmm Al gt Ru gp E Packets View packet event size source destination label retry response code Packet Type Stream E CycleStart 20 E mm Streaming 4104 E Show As Packet Stream PS CycleStart 20 E Streaming 4104 pb C tb AGO C LBUUMB PS CycleStart 20 MM Streaming 4104 Fields Layout PS CycleStart 20 mm Streaming 4104 field value E CycleStart 20 data length 4032 ms Streaming 4104 tag 0 m CycleStart 20 channel 0 mm Streaming 4104 tcode Stream Ill CycleStart 20 synchronisation 0 omn A ie header CRC Ox99FSFE1F Sec data 0 04094 60947 BE CycleStart 20 data 1 0x09480949 m Streaming 4104 data 2 0x094 40948 BE CycleStart 20 data 3 Ox094CO94D m Streaming 4104 data 4 0x094E094F E CycleStart 20 Streaming 4104 Acknowledge code J none Z Figure 16 Isochronous data recorded from the IEEE1394 bus with an analyzer one isochronous one 16 bit packet 20 samples sample empty cycles UC1394a 1 Streaming FIFO IEEE1394 A B O m port 2Kx16 interface fb l l 10us M 125us one isochronous Transfer direction cycle Figure 17 Isochronous packet a
82. he necessary connections for integrating the UC1394a 1 into a customized hardware environment A complete wiring example is shown in chapter 6 8 6 1 Power Supply The UC1394 1 requires a stabilized 3 3 V supply All of the supply and ground pins must be connected The carrier PCB must have a ground plane with short connections to the MCM s ground pins Decoupling capacitors of 100nF are recommended at each of the supply pins Additional decoupling capacitors can be placed between the VCC and ground planes near the GND pins of the MCM If the carrier PCB uses a voltage regulator to generate the 3 3 V follow the instructions of the regulators manufacturer for the type and value of the regulator s output capacitor s If the carrier PCB is directly supplied with 3 3 V from a cable a 10 100uF capacitor in parallel with a 100nF capacitor is recommended at the point where the cable is connected 6 2 IEEE1394 Interface For connection to the IEEE1394 network the 4 pin and 6 pin connectors defined in the IEEE standards 4 5 should be used The PCB traces to the connector TPA and TPB signal pairs e must be kept as short as possible e must be routed as a differential pair e must have a differential impedance of 110 60 Please note that the cable shield usage differs between the 4 pin and the 6 pin connector See Figure 26 or Figure 27 and Figure 33 for connection details of the 6 pin and 4 pin connectors Signal H 5 pin connector
83. his parameter controls flow control for virtual UART connections If enabled the receiving device sends a stop event to the transmitting device when the receive buffer gets filled over a specific level defined by uart suspend When the UART receive buffer fill level drops below a specific level defined by uart resume the receiving device sends a start request to the transmitting device to re enable data transfer In order to use this feature the partner device must be real time capable so that it can disable transmission within a reasonable time The suggested default value for this parameter is to disable flow control when a PC is used as partner and to enable flow control when another MCM is used as partner Flow control is not available with the VCP SDK due to the limited real time behavior of Windows 3 2 2 11 UART Buffer Fill Levels for Flow Control uart rx suspend uart rx resume These parameters define at which fill levels the receiver suspends and resumes transmission for a virtual connection uart rx suspend defines the fill level which generates a stop event for the transmitting device so that the transfer is suspended uart rx resume defines the fill level which generates a start event for the transmitting device so that the transfer is resumed To use this feature uart rx flowctl must be set to enabled The suggested default values are uart rx bufsize uart tx pktsize for uart rx suspend and uart ix pktsize for uart rx resume
84. hout this document require FPGA revision 8 or higher 0000000015 000000FF35 0000010046 FFFFFFFF15 not allowed 4 3 5 Software Version sw ver This parameter is used for informational purposes only It is read only and identifies the firmware that is currently installed on the UC1394a 1 The features described in this manual require sw ver 2 or higher ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG iu PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 rsys Page 57 0000000046 experimental or user defined firmware 0000000115 streaming BSP V1 no HPI no IEEE1394 flow control 0000000246 streaming BSP V2 0000000346 000000FF35 reserved for future use 0000010046 FFFFFFFF g not allowed 4 3 6 Software Revision sw rev This parameter is used for informational purposes only It is read only and identifies the firmware revision that is currently installed on the UC1394a 1 sw rev Meaning 0000000046 000000FF35 0000010045 FFFFFFFF g not allowed 4 3 7 VCP Version vcp ver This parameter identifies which version of the virtual connection protocol is supported by the module s firmware The features described in this document are supported by VCP Version 1 4 VCH ver Meaning 0001000346 VCP V1 3 0001000446 VCP V1 4 others reserved 5 Virtual Connection Protocol As formerly mentioned the VCP allows to connect interfaces across the IEEE1394 network
85. hronous Transfer Measured with FPGA version 4 Revision 7 7 8 1 1 1 Configuration Settings str iftype 0 str xfertype 0 7 8 1 1 2 Transmit Timing STR D 15 0 STR WE STR FLAGI1 0 STR CLK STR WE active before rising edge of STR CLK STR D 15 0 valid before rising edge of STR CLK STR D 15 0 valid after rising edge of STR CLK STR WE active after rising edge of STR CLK STR CLK low pulse width STR CLK high pulse width STR_FLAG 1 0 active after rising edge of STR CLK n a n a asynchronous Table 40 Streaming port transmit timing parameters 7 8 1 1 3 Receive Timing ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG iu PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 Orsys Page 81 Please note the first data word is automatically clocked out of the FIFO and is therefore immediately available STR D 15 0 STR RE STR FLAG 1 0 STR CLK Figure 38 Streaming port receive timing Parameter STR RE active before falling edge of STR CLK Gu 5ns STR D 15 0 valid after STR RE low lta t2ns STR D 15 0 new data valid after rising edge of STR CLK t 20ns STR CLK low pulse width i t2ns STR CLK high pulsewidth le i2ns STR CLK frequency tgs MHZ STR_D 15 0 floating after STR REhigh ts m 6 n a Table 41 Streaming port receive timing parameters 7 8 1 1 4 Latency T
86. idis read from pin O26 use device id partner dev isochronous streaming use common device parameter partner dev 16 bit generic interface auto start enabled 0 bytes 10 quadlets no sync pattern UO pins 0 7 input open drain output high virtual connection to partner pin enabled use common device parameter partner dev 8 15 respectively io connect io partner dev enabled I O pins 8 15 output open drain output virtual connection to partner pin enabled use common device parameter partner dev 0 7 respectively io partner inst io state io connect io partner dev io partner inst io en O pins 16 26 input open drain output virtual connection to partner pin disabled use common device parameter partner dev UART Date 25 October 2006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 orsys Page 89 Q uart baud 115200baud 1 1 1 luari partner nst 0 use dynamic packet size uart_ev_bufsize uart resume Io none I O 21 20 enabled use common device parameter partner dev pi partner inst Io a j HPI hpi resume JO diag iftype no hardware signaling diag connect diag partner dev diag partner inst cfg partner dev cfg partner inst c g ev bufsize Table 51 Predefined configuration mode 1 hpi rx bufsize hpi flowctl disabled Le orsys USER S GUIDE PARALLE
87. igital Signal Processor first in first out a special type of memory software installed on the UC1394a 1 MOM firmly installed software field programmable gate array host port interface inter integrated circuit a low speed interface between integrated circuits kilobyte 1024 byte KB per second light emitting diode IEEE1394 link layer controller least significant bit or byte multi chip module megabyte 1204 KB 1048576 byte MB per second Megabits per second 10 bits per second multi channel buffered serial port a peripheral of the TMS320VC5509 DSP most significant bit or byte not available not applicable a data word that consists of 32 bits 4 bytes read only memory software development kit Texas Instruments universal asynchronous receiver transmitter Virtual Connection Protocol 9 Literature References Further information that is not covered in this user s guide can be found in the documents listed below References to this list are given in square brackets throughout this document The documents are listed by title author and literature number or file name 1 Parallel Bus to IEEE1394 Bridging Kit User s Guide OrsyS Bridging Kit UG pdf 2 Spartan Il FPGA Family Product Specification Xilinx Dsoo1 3 Protocol specification Virtual Connection Protocol Orsys vcp_spec pdf 4 EEE Standard for a High PerformanceSerial Bus IEEE sta 1394 1995 5 EEE Standard for a High Performance Serial B
88. iguration of further MCMs during production After configuration has been saved to flash memory the module can be switched to mode 14 After the next reset or power up the module will use the parameters stored in flash memory for all of its interfaces including the UART interface For use of the UC1394a 1 MCM in customized hardware it is recommended to use customized configuration to avoid signal contentions after the first power up Further it is strongly recommended that the UART interface is externally available for configuration and firmware updates See chapter 6 5 for details ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 rsys Page 55 4 2 Configuration Tool The configuration tool can be used to e retrieve the current settings of the UC1394a 1 MCM using the Query button e modify common settings of the UC1394a 1 MCM using the control elements of the Common Parameters tab e modify the settings of each interface using the control elements of the appropriate interface tab such as streaming port e store the parameters permanently to the UC1394a 1 MCM s flash memory Save To Flash button e save the parameters to a file using the Save File command from the File menu e load a configuration file using the Save File command from the File menu The configuration tool starts up with COM1 selected as a default This setting
89. ine HPIC2 ERR MASK 0x0007 error detedct error acknowledge define HPI REG reg volatile unsigned int reg get current HPIC configuration and switch to HPIC2 if HPIC1 is currently selected prev hpic HPI REG HPIC1 if prev hpic amp HPICX HPIC2 0 HPI REG HPIC2 HPICX HPIC2 check for errors if HPI REG reg volatile unsigned int reg get the error code error HPI_REG HPIC2 amp HPIC2 ERR MASK error handling acknowledge error HPI_REG HPIC2 HPIC2 ERRDTCT switch back to HPIC1 if neccessary if prev hpic amp HPICX HPIC2 HPI REG HPIC2 prev hpic USER S GUIDE Date 25 October 2006 Doc no Bridge UG A PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 39 HPICA This bit is the HPIC address bit If set to 0 HPIC1 is selected and the remaining bits of this register behave as described in chapter 3 3 3 2 When HPICA is set to 1 HPIC2 is selected and the remaining bits of this register behave as described above in this chapter The host uses HPICA to switch between HPIC1 and HPIC2 The HPICA bit is present in both registers so that it is always accessible independent of which register is selected For further details please refer to the description of HPICA in chapter 3 3 3 2 3 3 3 4 HPI Control Register 3 HPIC3 The HPIC3 register is implemented on the carrier board and therefore neither available no
90. ing port s FIFO until at least str tx pktsize bytes are available Only then the IEEE1394 chipset start arbitrating for transmission For isochronous streaming transmission starts at the next isochronous cycle Therefore the FIFO must be able to buffer one packet plus a little bit more than 125 us provided that data is written to the streaming port without synchronization The resulting bandwidths and packet size limits are listed in chapter 7 8 1 1 5 In order to use higher bandwidths data may only be written to the streaming port if the FIFO has free space The code example below shows how to implement this on a micro line C6x11CPU module with the following connections e STR_FLAG1 connected to interrupt INT1 e STR WE connected to CS2 e STR CLK connected to IOSTRB block synchronized transmit transfer define STR TX BLOCK FREE C6X11CPU INT STAT amp C6X11CPU ISR INT1 0 define STR WRITE data volatile INT32U C6X11CPU CS2 BASE data define STR BLKSIZE 1024 1024bytes 512 16 bit words Note MCM must be configured accordingly wait for 1 block of free space in FIFO while STR TX BLOCK FREE write one block of data to the streaming port for i 0 i lt STR BLKSIZE i STR WRITE pBuffer Please note Due to the flag timing data transfer bandwidth is limited when STR FLAGO is checked before each access Therefore for operation with STR CLK frequencies above 10 MHz block b
91. inst 0 str width 16 bit str iftype str auto str blksize str frmsync o di io otype io state io connect io partner dev use common device parameter partner dev io partner inst 0 7 respectively io enable o o Q bi E SIE amp o Oo CC o GIS o Q S 2 2 D I O pins 8 15 EN Q S o lt lt io otype open drain output lo state high lo connect virtual connection to partner pin enabled io partner dev io partner inst 8 15 respectively io enable enabled io dir io otype Date 25 October 2006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 orsys Page 103 Q Setting uart partner inst 10 uart suspend 4096 uart resume 0o 0 0 0 0 0 0 O HPI hpi en isabled hpi width hpi handshake none 1 O 21 20 enabled hpi_connect hpi partner dev co partner inst O o hpi_tx_pktsize hpi tx timeout Joe O hpi ev bufsize 2048 hpi rx bufsize 40906 Cd hpi flowctl hpi suspend OS hpi_rx_fifo_size hpi tx fifo size ag iftype ag connect diag partner dev diag partner inst c g partner dev cfg partner inst ev bufsize Table 58 Predefined configuration mode 8 no o R Co 4096 hpi connect hpi partner dev hpi ix pktsize Lhpi tx timeout 0 ms hp flowctl hpi suspend gt S 3 o W C
92. ion Partner Device diag partner dev This parameter defines the device ID of the partner device for virtual connections called diagnostic host The diagnostic host e receives error notification events if diag connect is set to enabled e can clear the error FIFOs This parameter can be set to e The device ID of a remote device 0 6249 e accept any transmit broadcast error notifications are sent as broadcasts any device may clear the error FIFOs e use common partner device the ID that is commonly used as a partner for virtual connections parameter partner dev see 4 3 2 3 5 7 4 Diagnostic Virtual Connection Partner Interface Instance diag partner inst This parameter defines the interface instance interface number within the partner device for virtual connections of the diagnostic interface Since there is only one diagnostic interfaces this parameter is read only and set to accept any instance It is implemented for compatibility reasons only 3 6 Configuration Interface The configuration interface is not a hardware interface Instead it provides support for changing configuration parameters over IEEE1394 It is intended for situations where configuration parameters must be changed during device operation An example for this is a data acquisition system that transfers the acquired data to a host PC using the UC1394a 1 s streaming port The acquisition speed is not known when the system is built but only later at
93. ive operation the bandwidth can t be adjusted since it is defined by the transmitter The packet size is expressed in terms of bytes however only multiples of 4 bytes are allowed Table 3 shows the relationship between packet size and bandwidth The bandwidth must be set so that it is never exceeded A good choice is to set the bandwidth 2096 higher than the maximum data rate at the streaming port str tx pktsize bytes bytes per second 1 Table 3 streaming port transfer bandwidth examples 12 3 1 4 2 Streaming Port Direction str dir This parameter defines the transfer direction of the streaming port The direction must be configured since the streaming port can transfer data in one direction only str dir can be set to e Receive from IEEE1394 to streaming port e Transmit from streaming port to IEEE1394 e Direction determined by the startup state of l O26 The UC1394a 1 MOM allows to define the streaming port direction by the startup state of one of its I O pins 1 026 When 1 O26 is high at system startup streaming direction will be set to transmit Otherwise direction will be set to receive Please note that the streaming port direction can also be controlled over VCP at runtime see chapter 3 1 3 3 3 1 4 3 Streaming Port Channel str ch This parameter identifies the data stream within the IEEE1394 network str ch identifies the outgoing data stream or is used to filter out incoming data streams For isochr
94. level on STR FLAGO or STR FLAG If no handshake is used the FIFO will overflow In receive direction external hardware can read out the remaining data from the FIFO If the hardware is not synchronized by STR FLAGO or STR FLAG1 an underflow condition will be generated Depending on the application and the connected hardware it may be necessary to reset the streaming port prior to restarting streaming operation This clears the FIFO from previous data When the streaming port is operated in imaging mode especially when STR FLG 1 0 are not used a reset must be performed before restarting after a stop This triggers synchronization to the next start of a picture frame With the VCP SDK start and stop of streaming can be done by the functions VCP StartStreaming VCP StopStreaming 3 1 3 2 Resetting the Streaming Port Resetting the streaming port causes the following actions e The streaming port s FIFO is cleared Transmission is stopped at the next packet boundary error flags are cleared the streaming port is set up with the current operation parameters 8 bit operation 8 16 bit conversion is reset to start with the MSB imaging mode synchronization to the next picture frame is triggered 3 1 3 8 Changing Transfer Direction of the Streaming Port This feature allows to implement time multiplexed bi directional transfers For changing the direction the following sequence is necessary stop streaming operation stop the external h
95. mbering for 6 pin and 4 pin IEEE1394 connectors top view Power supply 3 3 V 6 pin IEEE1394 4 8 30 V Voltage IL Figure 26 Supplying the MCM from IEEE1394 GND IEEE1394 TPB TPB TPA TPA USER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 orsys Page 63 local supply 8 30V Diode prevents current flow L 1A fuse back into local power supply protects Power against supply excessive currents 3 3V Voltage M GND 6 pin IEEE1394 connector IEEE1394 TPB TPB TPA TPA Figure 27 Supplying power to the IEEE1394 cable 6 3 Configuration Mode Configuration mode setting necessary for the UC1394a 1 MCM to start with the correct configuration Further it is strongly recommended that for service purposes configuration mode 15 is selectable Figure 28 shows the minimum reguired wiring for customized configuration when IO 25 22 are not used for other purposes normal operation uses configuration mode 14 whereas service configuration and or firmware update is done in mode 15 In both cases the module starts up using the customized configuration set from flash memory The 3300 resistor prevents excessive current in case of a faulty configuration IO22 configured as push pull output with default state high 3 3V closed mode14 normal
96. must be changed when the UC1394a 1 MCM is connected to a different COM port using the COM menu Figure 18 shows the appearance of the configuration tool Configuration Tool ls x File COM Device Parameters Streaming Port 10 Pins UART Host Port Diagnostic ID Settings Device ld Do A ren Partner Id I 0 From Device Information Serial Number FPGA Version FPGA Revision Firmware Version Firmware Revision VCP Version SS Gerten AVE To Flash Start Streaming Remote Conti Close Figure 18 Configuration tool 4 3 Common Device Parameters Some configuration parameters affect device operation globally They are listed in Table 20 Meaning Device ID Default partner device FPGA version FPGA revision Firmware version Firmware revision Supported VCP version Table 20 Common device parameters overview Date 25 October 2006 CX USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 l Orsys Page 56 4 3 4 Device ID dev id This parameter defines the ID of the UC1394a 1 The device ID is used by the VCP for addressing It can be set to e avalue from 0 to 6210 e read from I O pin The upper 3 bits of the device ID are set to zero and the lower 3 bits are read from IO 18 16 see chapter 6 4 for wiring examples In systems where one single UC1394a 1 MCM and one PC running the VCP SDK is used dev id should be set to 1 In systems wi
97. must use the registration interface in order to connect to the desired interfaces of the remote device The registration interface is accessed over its software registers The layout and usage of the software registers is described in 3 3 7 4 Registration Interface Configuration The registration interface is not configurable It has a minimal set of parameters that is required for VCP operation 3 8 IEEE1394 Interface The UC1394a 1 MCM has two 400 Mbps IEEE1394 ports These ports can be connected to either a 4 pin or a 6 pin IEEE1394 connector Using these two ports the UC1394a 1 MCM can be inserted anywhere in an existing IEEE1394 network Since the IEEE1394 physical layer acts as a repeater no processing power is required for transferring data from one port to the other For transferring data between the MCM and the IEEE1394 network three transfer methods are available which are described in the following chapter 3 8 14 IEEE1394 Data Transfer Methods IEEE1394 provides three different methods for transferring data e isochronous streaming e asynchronous streaming e asynchronous transactions Asynchronous transactions are used for all virtual connections except the streaming port The streaming port uses isochronous streaming by default 3 8 1 1 Isochronous Streaming In isochronous streaming data is transferred in regular intervals called cycles In each cycle one data packet can be transferred The size of these data packet
98. n BB26 7 If HPI handshake is disabled or common handshake used this pin can be used as general purpose output on BB25 f USER S GUIDE Date 25 October 2006 e Doc no Bridge UG k PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 31 e transmit data request The FIFO has one or more data words of free space that can be written by the host The above listed conditions are only signaled if the respective bit in the HPIC1 register is enabled by the host see chapter 3 3 3 2 description of HPICA for details hpi handshake HPIC1 7 HPIC1 6 HPIC 5 HRDY HRRDY function ER EN RRDY EN TRDY EN X 1 020 separate receive data indicator Transmit ready indicator Table 7 Available functions for HRDY HRRDY HRDY HRRDY is an active low output When the above listed condition s are no longer true HRDY HRRDY is driven high for a short time and then left floating This minimizes signal contention when this signal is used as an interrupt output that is connected together with other interrupt signals See chapter 7 8 2 for details When all signaling on this pin is disabled this pin is not driven stays in high impedance HTRDY The function of this signal depends on HPI configuration parameter hpi handshake See chapter 3 3 2 3 for details When hpi handshake is set to none or common handshake HTRDY is not available and the respective pin is used as l O21 When hpi handshake is set to
99. n enabled use common device parameter partner dev 0 7 respectively io enable _Olype io connect io partner dev io partner inst enabled IO pins 8 15 output open drain output igh virtual connection to partner pin enabled use common device parameter partner dev 8 15 respectively io connect io partner dev io partner inst io en enabled I O pins 16 26 input open drain output igh virtual connection to partner pin enabled use common device parameter partner dev 16 26 respectively UART 115200 baud ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 orsys Page 99 Setting luart handshake RTS CTS handshake enabled uart ev bufsize none I O 21 20 enabled virtual connection to partner device disabled hpi partner dev use common device parameter partner dev use dynamic packet size hpi flowctl disabled hpi suspend Diagnostic interface dag iftype no hardware signaling enabled use common device parameter partner dev accept any instance Configuration interface accept any device accept any instance cfg ev bufsize 5 Registration interface reg partner dev accept any device reg partner inst accept any instance Table 56 Predefined configuration mode 6 Le orsys USER S GUIDE PARALLEL Bus To IEEE1394 BRIDGE Date 25 October 2006 Doc no Bridge_UG Iss Rev 1
100. n timings for virtual connection with 8 I O pins 7 8 4 Reset Timing Parameter Value Min Max RESETIN input pulse width 1us RESETOUT pulse width 140ms Table 48 Reset timing 7 9 Predefined Configuration Tables This chapter lists the predefined parameter sets for configuration mode 0 9 and the passive parameter set which is used in the reserved configuration modes 10 13 and as a factory default for configuration modes 14 15 Table 49 lists the main differences between these parameter sets A complete listing of each parameter set is given in the subsequent tables Modes O to 4 are intended for standalone operation that is MCM to MCM virtual connections whereas Modes 5 to 9 are intended for usage with the VCP SDK and MCM to PC virtual connections T Tele delet fe fee e Parameter read from O 18 16 1 read from O 18 16 read from O 21 19 read from 1 O 21 19 auto start manual start sir ix pktsize 4096 4096 4 ENDURO 4 40 400 2000 Fogg 4 40 400 2000 Laus disabled enabled disabled Table 49 Differences between the predefined amp passive parameter sets 14 The values given here are factory defaults only user configuration overwrites these values Le orsys USER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Page 86 7 9 1 Configuration Mode 0 31 KBps Predefined Configuration This configuration can b
101. nd the diagnostic interface so their presence depends on the configuration of these interfaces See chapters 3 3 1 3 3 2 1 through 3 3 2 3 and 3 5 2 for details Some of the I O pins are sampled at system startup Their startup state defines a part of the UC1394a 1 MCM configuration as shown in Figure 11 ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG Uu PARALLEL BUS TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 41 3 4 4 I O Pin Signals HD12 partner ID HRRDY HRDY HRRDY HRDY HTRDY HTRDY configuration mode Table 13 I O pin assignments 3 4 2 I O Pin Alternative Functions If the host port is enabled configuration parameter hpi_enable 1 O 8 0 and l O 21 16 are disabled independent of the HPI configuration The availability of O 15 9 depends on the HPI configuration parameter hpi width In 8 bit mode l O 15 9 are still available whereas in 16 bit mode O 15 9 are also disabled A similar situation exists for the usage of IO 26 22 If the diagnostic interface is enabled parameter diag iftype set to Error signal only or Error code output I O 23 22 are always used for diagnostics and are no longer available as I O pins Further if the diagnostic interface is configured for error code output diag iftype set to Error code output O 26 24 are also used for diagnostics If one of the alternative functions is enabled the respective UO pin is no l
102. ng Partner Interface The configured partner interface is not reachable because The partner device does not exist The partner device is a PC which hasn t registered yet see note below There is an error when reading the parameters of the remote device The partner interface defined by xxx partner inst does not exist on the partner device The configuration of the partner interface does not allow a virtual connection for one of the following reasons o Parameter xxx partner dev of the partner interface is set to a device other than the local device Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 48 o Parameter xxx partner dev of the partner interface set to use common partner device and partner dev is set to a device other than the local device o Parameter xxx partner inst of the partner interface set to an instance other than the local interface o Parameter xxx enable of the partner interface set to disabled probably due to configuration o Parameter xxx connect of the partner interface set to disabled o Parameter o dir of the partner interface is set to the wrong direction input connected to input Please note that this error is very likely to occur when a PC is used as a partner The PC must register at the VCP device before it is accepted as a partner At startup of the MCM the PC most likely hasn t registered yet and the related vir
103. ng direction is receive and the FIFO holds at least str blksize data b streaming direction is transmit and the FIFO has free space for at least str blksize data See chapter 3 1 4 10 for a description of str blksize Please note The behavior of this signal is not affected by the configured streaming port data width str width Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 19 A typical use of STR FLAG is to set the block size to 4 bytes and to check STR FLAG after every second access in 16 bit configuration This provides a quadlet based synchronization which can be used for transfers at full speed 3 1 2 Streaming Port Operation 3 1 2 1 Streaming Port Word Byte Order On the IEEE1394 interface streaming port data is transferred in units of quadlets 32 bit words Most significant parts of a quadlet are transferred first Therefore when receiving a guadlet of data from the IEEE1394 bus Bit 31 16 16 bit interface width or Bit 31 24 8 bit interface width are the first data that can be read at the streaming port 3 1 2 2 Streaming Port Packetizing It is important to know that streaming port data is transferred in packets of fixed sizes The packet size is always defined by the transmitter and affects streaming port transmit operation as follows Data only gets sent if enough data for one packet is available If exactly one
104. o Bridge UG PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 orsys Page 87 Q uart baud 115200baud 1 1 1 luari partner nst 0 use dynamic packet size uart_ev_bufsize uart resume Io none I O 21 20 enabled use common device parameter partner dev pi partner inst Io a j HPI hpi resume JO diag iftype no hardware signaling diag connect diag partner dev diag partner inst cfg partner dev cfg partner inst c g ev bufsize Table 50 Predefined configuration mode 0 hpi rx bufsize hpi flowctl disabled Le orsys USER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Page 88 7 9 2 Configuration Mode 1 313 KBps Predefined Configuration This configuration can be used for standalone UC1394a 1 configurations with low to medium bandwidth requirements Parameter name Device common parameters partner dev Da ver Dga rev vcp ver str tx pktsize str dir str ch str xfertype str partner dev str partner inst str width str iftype str auto str blksize str frmsync io dir io connect io partner dev io partner inst Setting own ID is read from pins l O 18 16 partner ID is read from pins l O 21 19 4 indicates current FPGA revision indicates current firmware version indicates current firmware revision 001000446 VCP V1 4 Streaming port 40 bytes 10 quadlets str
105. ode 3 15 MBps Predefined Configuration 4 eee 92 7 9 5 Configuration Mode 4 31 MBps Predefined Configuration 94 7 9 6 Configuration Mode 5 31 KBps Predefined Configuration sseseeesessss 96 7 9 7 Configuration Mode 6 313 kBps Predefined Configuration eee 98 7 9 8 Configuration Mode 7 3 MBps Predefined Configuration 100 7 9 9 Configuration Mode 8 15 MBps Predefined Configuration 102 7 9 10 Configuration Mode 9 31 MBps Predefined Configuration eee 104 7 9 11 Configuration Mode 10 13 Reserved and 14 15 Factory Default 106 8 LIST OF ABBREVIATIONS AND ACRONYMS USED IN THIS DOCUMENT 108 9 LITERATURE REFER ENG ES indic riked ictu iesus n ol ada I RM RET k E DUE DIN ED M VON IUE n HERE 108 O Date 25 October 2006 USER S GUIDE Doc no Bridge UG PARALLEL BUS TO IEEE1394 BRIDGE JRev 1 orsys SC List of Tables Table 1 Streaming port connector pin assignments eee4 2eeeeeeeeeeeeeeeeeee eee eee nenene 16 Table 2 streaming port parameter OVErvieW eee eee nn 22 Table 3 streaming port transfer bandwidth examples ee eeeeeern 22 Table 4 UART connector pini SSES eege 25 Table 5 UART parameter overview eee eee KKK RKK KKK KKK KKK KRK KRK 26 Table 6 HPI connector pin assignments eeeesseeeieeeeeeeeeee e eeeeee enne 30 Table 7 Availabl
106. on Incoming data from IEEE1394 will be accepted from all devices Use common partner device the partner ID for the virtual HPI connection will be taken from the common parameter partner dev see chapter 4 3 2 Use dynamic addressing The host defines the partner device for outgoing HPI data events See description of the ID bit field in chapter 3 3 3 2 for details The suggested default for this value is to use the common partner device 3 3 2 6 HPI Virtual Connection Partner Interface Instance hpi partner inst This parameter defines the interface instance interface number within the partner device for virtual HPI connections This parameter is used for e addressing the partner interface within the partner device outgoing data events flow control events e filtering out the allowed partner for incoming events The instance of an interface is a simple number starting at 0 The first HPI interface of a device has an instance of 0 the second of 1 etc Together with hpi partner dev this parameter defines the virtual connection of this HPI One special value is available for this parameter e Accept any HPI The HPI interface accepts data and flow control events from any HPI of the configured partner device and sends data and flow control events using the local interface instance The suggested default for this value is 0 since typically there is only one HPI per device 3 3 2 7 HPI Transmit Packet Size hpi tx pktsize
107. onger available Only used if dev id is set to read from UO pin Only used if partner devis set to read from I O pin Only used if str diris set to read from 1 026 UsER s GUIDE Date 25 October 2006 CY Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 42 3 4 3 UO Pin Startup State Options Some of the I O Pins are sampled at system startup Their state can be used to configure operation of the MCM After system startup the I O pins can be used for other purposes In order to avoid conflicts with later usage the startup state should be defined by pull up pull down resistors or by a driver that is disabled after system startup see wiring examples in chapters 6 3 and 6 4 3 4 3 1 Setting the Device ID over I O Pins This feature is useful if the end user must be able to change the device ID e g when the end user builds a system that consists of several MCMs When using this option the device ID is restricted to values of 0 7 To use this option configuration parameter dev id must be set to read from I O pin Please note that this feature is still available even when the HPI is used instead of the I O pins since the I O pins are sampled before the HPI is enabled The device ID is encoded as follows 1 016 device ID Bit 0 1 017 device ID Bit 1 1 018 device ID Bit 2 device ID Bit 3 5 are set to 0 3 4 3 2 Setting the Partner Device ID over I O Pins This f
108. onous streaming which is the default transfer method for the streaming port str ch determines the isochronous channel number It can be set to Ce USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 23 e avalue of 0 63 e receive all channels not allowed for transmit or for use with the VCP SDK derive the channel number ID from other configuration parameters as follows transmit direction channel number is equal to configuration parameter dev id receive direction channel number is equal to configuration parameter str partner dev Configuration parameters dev id and str partner dev are described in chapters 4 3 1 and 3 1 4 5 respectively Suggested default value for str ch is to derive the channel number automatically from other configuration parameters Please note the configuration tool displays str ch as stream Id 3 1 4 4 Streaming Port Transfer Method This parameter defines how streaming port data is transferred over IEEE1394 Currently implemented are e isochronous streaming e asynchronous streaming affects transmit operation only Please note that asynchronous streaming is different from asynchronous transactions Asynchronous transactions are currently not implemented for the streaming port A description of the transfer methods can be found in chapter 3 8 1 3 1 4 5 Streaming Port Partner Device str partner dev This parameter
109. operation open mode 15 service H Figure 28 Minimum reguired wiring for customized configuration When the 10 25 22 are also used for other purposes the wiring has to be modified as follows UsER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 64 O 1 service normal i operation to external E hardware Figure 29 Alternative wiring for customized configuration 6 4 Device and Partner ID from I O Pins For systems with several UC1394a 1 MCM s it may be useful that the end user assigns the device IDs In this case the device and partner ID must be configurable by the startup state of I O pins Therefore configuration parameters dev id and partner dev must be set to read from I O pin The required wiring is shown in Figure 30 for the case where no other function of these signals I O or HPI is used The jumpers could also be implemented as a binary encoded rotary switch Again the 3300 resistors prevent excessive current in case of a faulty configuration 3 3V 6x 3300 D H n E E O O O TT ST J l J partner ID device ID jumpers or jumpers or rotary switch rotary switch Figure 30 Setting device and partner ID over UO pins When the I O pins must also be used for other purposes wiring as shown for IO22 in Figure 29 can be used fy UsER s GUIDE PARALLEL Bus TO IEEE1394 BRIDGE
110. originator of the transfer must be informed about the status of each single transfer 3 8 2 IEEE1394 Cable Power Option The 6 pin IEEE1394 connectors allow to distribute power over the IEEE1394 network This option can be used to supply remote devices from the local device and vice versa Please refer to chapter 6 2 for wiring examples 4 Configuration Configuration is necessary to set up the required virtual connections and interface parameters In contrast to the bridging kit 1 the UC1394a 1 MCM is delivered without a predefined customized configuration Customers can use one of the predefined configurations configuration mode 0 9 see chapter 4 1 or must set up their own customized configuration during system production Pre configured MCMs are also available on request Configuration is usually done over the UART interface using a graphical front end called configuration tool Therefore a Windows based host PC with a RS 232 interface is required Further a level converter from 3 3V LVTTL to RS 232 is required see Figure 33 for wiring examples An alternative way for configuration is to use the configuration interface over IEEE1394 The configuration interface allows to set single configuration parameters over the VCP API However for this method no graphical user interface is available 4 1 Configuration Mode The UC1394a 1 MCM provides a number of predefined configurations as well as a customized configuration that can b
111. ormational purposes only 3 3 8 HPI Registers Host Side An external host has access to one HPI data register HPID and two HPI control registers HPIC1 HPIC2 In 8 bit configuration the HPI registers are split into two 8 bit halves and HAO switches between these register halves Addressing of the two HPI control registers is done by the HPICA bit which is present in both HPIC registers HPICA Table 9 HPI address map in 16 bit configuration ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG L PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 295 HPID 7 0 reserved HPIC1 7 0 HPIC1 15 8 HPIC2 7 0 HPIC2 15 8 Table 10 HPI address map in 8 bit configuration The layout of the HPI registers is shown in Table 11 and Table 12 EES HPID HPI DATA HPIC1 HPICA RSV DST ID ERR EN RRDY EN TRDY EN TEMPTY RRDY TRDY HPIC2 HPICA RESERVED ERRCLR Table 11 HPI register layout in 16 bit configuration C HPID 7 0 HPI DATA 7 0 UN RRDY HPIC1 15 8 DST ID HPIC2 7 0 RESERVED ERRCLR HPIC2 15 8 HPICA Table 12 HPI register layout in 8 bit configuration 3 3 3 1 HPI Data Register The HPI data register allows to access the HPI FIFOs Any read of the HPI data register reads out one 8 bit or one 16 bit word from the HPI FIFO A read from an empty FIFO yields the last read value Writes to HPID transfer one data word 8 bit or 16 bit the HPI FIFO Writes to a full
112. orsys Date 25 October 2006 Doc no Bridge_UG Iss Rev 1 1 Page 65 6 5 RS 232 Level Converter Even when the UART interface is not used it is strongly recommended to implement it preferably with a RS 232 level converter This allows for configuration as well as for firmware updates If the UART interface is used in the end application it should be externally accessible e g by using connectors or jumpers Figure 31 shows a wiring example and Table 23 shows the required cable wiring A detailed schematic example is shown in Figure 33 Using a 3 3V type is recommended to other hardware service connector Figure 31 Wiring of UART interface as Table 23 Required cable connection to a host PC 6 6 JTAG Interface The JTAG Interface is not needed during operation or configuration However it provides a possibility for debugging or for firmware updates in situations where the firmware loader doesn t work If the application permits the JTAG signals of the DSP should be available for service purposes The FPGA JTAG signals are not required Figure 32 shows the wiring of the JTAG connector that can be used with the standard development tools fy USER S GUIDE orsys PARALLEL Bus To IEEE1394 BRIDGE Date 25 October 2006 Doc no Bridge_UG Iss Rev 1 1 Page 66 standard 2x7 header 0 1 inch spacing Pin 6 removed JTAG interface JTAG_DSP_
113. out device configuration Please note that the UART interface is not available for virtual connections when it is used for configuration Incoming UART data is then interpreted for configuration commands However incoming VCP character events are still forwarded to the UART interface External External hardware hardware 3 3V RS 232 UART IEEE1394 FIFO Level Interface 2x 16 char converter character events flow control events Host PC configuration tool Figure 7 UART interface block diagram 3 2 1 UART Signals The UART interface uses 2 data lines and 2 handshake lines UART TxD UART RxD UART interface UART RTS UART CTS Figure 8 UART signals MCM connector pin UART TxD A17 UART RxD UART RTS UART CTS Table 4 UART connector pin assignments UART TxD Transmit data output of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 33 This signal is high when no data is transmitted Date 25 October 2006 CX USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 l Orsys Page 26 UART RxD Receive data input of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 33 This input must be high when idle UART RTS Handshake output of the UART interface For RS 232 usage this signal must be connected to a
114. packet size than adjusted by hpi tx pktsize If no data at all is present no packet is sent The timeout starts to expire with the first available data When the timeout is set to 0 the timeout feature is disabled and character events to the partner are only sent if enough data is available The maximum value for this parameter is 60 000 1 minute The suggested default for this parameter is 100 ms for a PC as partner device and 0 disabled for a MOM as partner device f USER S GUIDE Date 25 October 2006 e Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 34 3 3 2 9 HPI Virtual Connection Event Buffer Size hpi ev buffer size This parameter is read only and is used for informational purposes only It specifies the maximum size in bytes for incoming data events This information is useful for situations where the VCP SDK is not available 3 3 2 10 HPI Virtual Connection Receive Buffer Size hpi rx bufsize This parameter is read only and is used for informational purposes only It specifies the number of bytes that can be buffered by software This information is useful for situations where the VCP SDK is not available 3 3 2 11 HPI Virtual Connection Flow Control hpi flowctl This parameter controls flow control for virtual HPI connections If enabled the receiving device sends a stop event to the transmitting device when the receive buffer gets filled over a specific level
115. perform a read or write cycle HRD Active low read strobe When HCS is low data is read out of the host port when HRD is low Reading from an empty FIFO causes a FIFO underflow condition HWR Active low write strobe When HCS is low data is written to the host port on a rising edge of HWR Writing to a full FIFO causes a FIFO overflow condition HA 1 0 These signals select which HPI register is accessed by the host see chapter 3 3 3 HAO is only available when the host port is configured for 8 bit operation Otherwise this pin is used as HD8 HA 1 0 must be stable during a HPI access HRDY HRRDY The function of this signal depends on HPI configuration parameter hpi handshake See chapter 3 3 2 3 for details When hpi handshake is set to none HRDY HRRDY is not available and the respective pin is used as l O20 When hpi handshake is set to separate handshake this signal is used as a receive data indicator HRRDY function and can indicate two conditions e receive data available at least one data word is available in the HPI FIFO to be read by the host e error occurred An error code is present in the HPI control register 2 an can be read by the host Additionally if hpi handshake is set to common handshake this signal is used as a host transfer request indicator HRDY function and can indicate the above described conditions plus If HPI handshake is disabled this pin can be used as general purpose output o
116. pin connector TPB TPA signal ground cable power chassis ground connector shield n a n a ma signal ground cable power chassis ground connector shield Table 21 Pinning of the IEEE1394 connectors Table 22 shows part number examples for both connector types Connector type Molex part No 6 pin IEEE1394 1995 53462 xxx 6 pin with latch 55395 xxx 4 pin IEEE1394a 2000 54515 xxx Table 22 IEEE1394 connector part numbers 12 IEEE1394 1995 requires an isolation circuit such as shown in Figure 26 between cable shield and chassis ground whereas IEEE1394a removed the requirement for an isolated cable shield connection my USER S GUIDE Date 25 October 2006 Doc no Bridge_UG PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 62 When cable power is required the 6 pin connector defined by IEEE1394 1995 must be used as shown in Figure 23 Otherwise the 4 pin connector defined by IEEE1394a can be used Figure 24 This connector is smaller and is often used in laptop computers For industrial environment 6 pin connectors with a robust case and latch are also available Figure 26 shows an example for supplying the MCM from IEEE1394 Figure 27 shows how to additionally supply power to IEEE1394 Further information about cable power usage can be found in 4 5 and 6 Figure 24 4 pin IEEE1394a connector O3 Or o N L 7 M Figure 25 Pin nu
117. r necessary on the MCM 3 4 VO Pins The UC1394a 1 MCM has up to 27 general purpose I O pins IEEE 1394a chipset IEEE1394 Port 0 IEEE1394 Port 1 physical layer transceiver data mover port Microcontroller interface 1 2 3 4 5 6 7 8 Figure 11 O pin block diagram Each I O pin can be individually configured to be an e input e push pull output e open drain output _ Startup state can define device ID Startup state can define partner ID Startup state defines configuration mode Startup state can define streaming direction USER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 orsys Page 40 c gt Input Push pull output Open drain output Figure 12 O pin configurations The VCP allows connection between any two UO pins on any two devices When two I O pins are virtually connected one pin must be output and one must be input State changes on the input pin generate an event that is sent to the output pin Polling the current state of an I O pin is also supported by the VCP VO pin 0 Input WO pin 8 output VO pin 0 IEEE1394 IEEE1394 H Interface Interface VCP Pin state pvents VO pin 8 optional Pin state polling 4 Figure 13 Example for a virtual connection between two I O pins On the UC1394a 1 MOM the I O pins are shared with the HPI a
118. r circuit holds each signal in its previous state Can be left unconnected if unused See chapter 3 1 1 for more details Polarity Built in termination Handling when not used bi directional active high keeper FPGA ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page WG STR WE CAM FEN Streaming port write enable or camera frame enable input Polarity Built in termination Handling when not used pull up FPGA STR_RE CAM_LEN Streaming port read enable or camera line enable input STR_CLK CAM_PCLK Streaming port clock for bot generic and imaging mode Polarity Built in termination Handling when not used pull up FPGA STR FLAG 1 0 Streaming port flags related to FIFO fill level 7 2 3 UO Pins Host Port and Diagnostic Interface O 26 0 HD 15 0 HA 1 0 HCS HRD HWR HRDY HRRDY HTRDY ERRDTCT ERRCLR ERR 2 0 General purpose I O or alternative function as specified in chapter 3 4 3 3 or 3 5 2 Polarity Built in termination Handling when not used bi directional configuration pull up FPGA 7 2 4 UART Signals For RS 232 usage the UART signals must be converted to the appropriate level An example is shown in Figure 33 UART_TxD Transmit data output of the UART interface Polarity Built in termination Handling when not used output active high n a always driv
119. r 2006 e Doc no Bridge UG us PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 94 7 9 5 Configuration Mode 4 31 MBps Predefined Configuration This is the maximum bandwidth configuration Please note that in this mode it is strongly recommended that data transfers are synchronized by means of the streaming port flags STR FLAGO and or STR FLAG1 Device common parameters partner dev fpga ver 4 foga rev vcp ver str tx pktsize str xfertype str partner dev use common device parameter partner dev str partner inst 0 str width 16 bit str iftype str auto str blksize str frmsync o di io otype io state io connect io partner dev use common device parameter partner dev io partner inst 8 15 respectively io enable enabled I O pins 8 15 o o Q bi E Z a o Oo CC o GIS o Q S 2 5 Q S o c io otype open drain output lo state high lo connect virtual connection to partner pin enabled io partner dev use common device parameter partner dev io partner inst 0 7 respectively io enable enabled O pins 16 26 io otype open drain output io dir 15 Block size limited in order to still have FIFO space after one block has been written to the FIFO from either side Date 25 October 2006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 orsys Page 95 Q Ho partner inst O
120. r packets have the synchronization bits cleared When the streaming port is configured as a generic interface all packets will have the sync pattern defined by this parameter in their header Frame synchronization requires a minimum inactive time for the CAM FEN signal see description of the CAM FEN signal above Allowed values for the sync pattern are O F46 Application software on the receiver side can use this feature to synchronize to an already running data stream 3 2 UART The UC1394a 1 MCM has an UART interface that can be used for standard asynchronous communication Different baud rates are supported as well as RTS CTS handshake The signals of the UART interface operate with LVTTL logic levels therefore a level converter is required for usage as an RS 232 interface see chapter 6 5 for details Incoming and outgoing characters are buffered by a 16 character FIFO The virtual connections use a software buffer and event based flow control fy USER S GUIDE Date 25 October 2006 Doc no Bridge_UG PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 225 The UART interface is also used for device configuration To enable UART configuration the UC1394a 1 MCM must have UART configuration enabled This is done by selecting configuration mode 1510 of the MCM The configuration mode is determined by the startup state of I O pins IO 25 22 as shown in chapter 6 3 Please refer to chapter 4 for information ab
121. ransmit latency Measurement conditions e time from last word of a packet written to the transmit FIFO until start of the data packet on the IEEE1394 network Min Max Receive latency Measurement conditions e Carrier board data sink active e packet size 4096 bytes e block size 4 bytes 1 quadlet e time from packet start on the IEEE1394 network to STR FLAG1 active first quadlet in FIFO Date 25 October 2006 USER S GUIDE Doc no Bridge UG LJ P B IEEE1394 BRIDGE ARALLEL BUS TO Rev 1 orsys Page e 7 8 1 1 5 Maximum Bandwidth The table below gives the maximum achievable bandwidths Please note that for transmit operation the packet size does not include any margin see chapter 3 1 4 1 Condition Packet size Max bandwidth in bytes in byte s receive synchronized with STR FLAG1 4096 32 768 000 operation transmit operation Table 42 Maximum achievable streaming bandwidths 7 8 1 2 Imaging Interface Isochronous Transfer Measured with FPGA version 4 Revision 0 7 8 1 2 1 Configuration Settings str iftype 1 str xfertype 0 7 8 1 2 2 Transmit Timing CAM_D 15 0 C ja CAM FEN CAM LEN CAM FLAG 1 0 CAM CLK Figure 39 Streaming port transmit timing imaging mode ly USER S GUIDE Date 25 October 2006 Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 83 Parameter CAM LEN valid after rising edge of
122. re 2 Bridge block diagram 2 1 Virtual Connection Protocol Up to 27 bit The Virtual Connection Protocol VCP is an interface based protocol for connecting two or more devices over the IEEE1394 bus Each of the device s interfaces can be connected to an interface of the same type on a remote device using a virtual connection over IEEE1394 On a Windows based host PC the VCP SDK provides access to these interfaces on API level For the first steps a VCP demo application is included in the SDK This demo application uses a graphical user interface for accessing the interfaces of remote devices f USER S GUIDE Date 25 October 2006 Doc no Bridge UG iJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 13 File Output Window Info Device Incoming Stream Outgoing Stream 1 0 Pins UART Count received bytes only discard data Save Stream to File I Sopete 0 MB C Compare with Pattern enter bytes sep by space Ox prefix for hex El Useless enn Dump Snapshot Bytes Start Streaming Stop Streaming Idle Device ID 63 opened Figure 3 VCP demo application The VCP defines device IDs and interface instances for addressing The interface instance enumerates interfaces of the same type such as I O pins A virtual connection can be made between any two interfaces of the same type on any two devices on the IEEE1394 network For example I O pin 5 on
123. re registers These software registers are specific to each interface and are used during operation to exchange information between interfaces In most cases an event register or event buffer exists that receives data events from the partner interface 5 1 Accessing the UC1394a 1 MCM Using the VCP SDK The VCP SDK provides API level access to the VCP It consists of A device driver for the VCP A user mode DLL that provides generic access to any interface A class library that contains a class specific to each known interface A demo application with graphical user interface that uses the class library fy USER S GUIDE Date 25 October 2006 Doc no Bridge UG M PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 orsys GR User uo n Application pplication Source Code V Z Interface Class Library User VCPLIB Application Source Code VCP User Mode API Documentation l VCP DLL VCP_API DLL User Mode Kernel Mode VCP Device Driver VCP_1394 SYS Windows IEEE1394 Driver Stack IEEE1394 PC Hardware Figure 21 VCP SDK structure Two entry points exists for software development The class library provides a interface specific access This is the most easiest approach The user works directly with interface specific functions such as m IoPin 0 SetState Pinstate High The class library is provided as self explanatory source code The
124. receive FIFO underflow host to HPI Table 17 Available detailed error codes 3 5 7 Diagnostic Interface Configuration Configuration allows e if and how diagnostic information is output over some dedicated UO pins e to enable error notification events to a diagnostic host e to set up which device is the diagnostic host Table 18 lists all available configuration parameters f USER S GUIDE Date 25 October 2006 e Doc no Bridge UG k PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 OrSsSys Page 50 dag iftype controls diagnostic output on IO 26 22 controls whether error notification events are sent partner device for virtual connections diagnostic host partner instance interface number on the diagnostic host Table 18 Diagnostic interface parameter overview 3 5 7 1 Diagnostics interface Type diag iftype This parameter controls if and how diagnostic information is output on dedicated UO pins It can be set to e disabled no diagnostic information O 26 22 used as I O pins e error presence signaling using the signals ERRDTCT and ERRCLR e error code output using the signals ERRDTCT and ERRCLR and ERR 2 0 3 5 7 2 Diagnostics Error Event Enable diag connect When set to enabled this parameter causes error notification events sent to the diagnostic host The diagnostic host is determined by configuration parameter diag partner dev 3 5 7 3 Diagnostic Virtual Connect
125. rpose I O I O pin 21 e Separate handshake HRRDY HRDY is used as receive ready HRRDY function selected HTRDY is used as transmit ready 3 3 2 4 HPI Virtual Connection Control hpi connect This parameter is used to establish a virtual connection of the local HPI to a HPI interface on a remote device If virtual connections are enabled incoming HPI data from the host will be sent over IEEE1394 to the configured partner device see hpi partner dev hpi partner inst On the partner device this data will be output on its HPI interface if the partner device also has virtual connections enabled In receive direction if virtual connections are enabled HPI data events from the partner device will be transmitted to the local HPI interface The suggested default setting for this parameter is to enable virtual connections 3 3 2 5 HPI Virtual Connection Partner Device hpi partner dev This parameter defines the partner device for virtual HPI connections It defines the device to which the data received from the host is sent Further it defines from device data and flow control events are accepted Allowed values for this parameter are f USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 33 e The device ID of a remote device 0 6210 Accept any device Incoming data will be sent to all devices in the network via a IEEE1394 broadcast transacti
126. s 0 7 io dir input io otype open drain output io state high io connect virtual connection to partner pin enabled use common device parameter partner dev io partner dev io partner inst 0 7 respectively enabled UO pins 8 15 o D o 5 l Q n o O open drain output _olype lo connect virtual connection to partner pin enabled io partner dev use common device parameter partner dev io partner inst 8 15 respectively o 2 D s gg els O pins 16 26 S o o o o jola 3 lz 9 8 o S 3 m aS S W I o open drain output virtual connection to partner pin enabled use common device parameter partner dev 16 26 respectively io connect io partner dev io partner inst UART 15200 baud uart handshake TS CTS handshake enabled ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG J PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 OrsSys Page 97 Setting uart connect virtual connection to partner device enabled uart partner dev use common device parameter partner dev uart ix pktsize 0 ms 2048 4096 uart flowctl i hpi width 8 bit hpi handshake none I O 21 20 enabled virtual connection to partner device disabled use common device parameter partner dev Lhpi partner inst use dynamic packet size disabled hpi resume hpi rx fifo size
127. s at least one more data word to be read by the host RRDY 1 RRDY goes inactive after the host has read the last data from the HPI and no new data has arrived at the HPI RRDY is read only The host should check RRDY before reading the HPID register TEMPTY This bit indicates that all data from the host has been processed by the UC1394a 1 The host can use this bit to initiate a block write to the HPI data register When TEMPTY is active 1 as many data words as defined by hpi tx fifosize can be written to the HPID register without checking for the TRDY bit OV This bit indicates that the host has written to the HPID register while the HPI FIFO was full Therefore OV indicates that data got lost The host can clear the OV bit by writing a 1 to it The host should check the OV bit periodically to detect handshaking errors UN This bit indicates that the host has read from the HPID register while the RRDY was inactive Therefore UN indicates that invalid data was read from HPID The host can clear the UN bit by writing a 1 to it The host should check the UN bit periodically to detect handshaking errors TRDY EN This bit controls whether the transmitter ready condition is signaled on one of the HPI handshake signals Please note that configuration parameter hpi handshake controls the behavior of the handshake signals e hpi handshake set to separate handshake TRDY output on HTRDY e hpi handshake set to common handshake T
128. s determines the maximum data bandwidth see Table 3 The cycle clock is 8kHz therefore packets get sent every 125 us Before transmission is started the transmitter reserves the necessary amount of bus bandwidth at a central location on the bus the isochronous resource manager This and the fact that isochronous packets have precedence over asynchronous packets guarantees that the bus provides enough capacity for the transfer Isochronous streaming is an excellent solution for transferring image data from a camera Isochronous transfers are multicast transfers which are identified by a channel so there is always one talker but there may be one or more listeners The transfer is typically done without any software overhead and is therefore quite fast Error detection is done at the receiver side Isochronous streaming is well suited for e large amounts of data rs USER S GUIDE Date 25 October 2006 f Doc no Bridge UG A PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 52 e data distribution to several devices e data that occurs in regular intervals Figure 16 shows a part of an isochronous stream recorded with an analyzer The large blocks are isochronous packets with maximum size 4096 bytes The isochronous packets are preceded by a cycle start packet which indicates the start of a new cycle On the UC1394a 1 MCM packets are only transmitted when enough data is present in the FIFO Otherwise t
129. separate handshake this signal is used as a host transfer request indicator and can indicate the following condition e Transmit data request The FIFO has one or more data words of free space that can be written by the host This condition is only signaled if the respective bit in the HPIC1 register Bit 5 TRDY EN is enabled by the host see chapter 3 3 3 2 for details HTRDY is an active low output When the above listed condition is no longer true HTRDY is driven high for a short time and then left floating This minimizes signal contention when this signal is used as an interrupt output that is connected together with other interrupt signals See chapter 7 8 2 for details When signaling on this pin is disabled this pin is not driven stays in high impedance 3 3 2 HPI Configuration From a hardware point of view the HPI can be configured to use 8 or 16 data bits hpi width and one to of three handshake types hpi handshake e none e common handshake signal HRDY e separate handshake signals for each direction HRRDY HTRDY Further the HPI can be totally disabled parameter hpi en Other parameters of the HPI configure virtual connection operation Table 8 lists all available configuration parameters Ly UsER s GUIDE Date 25 October 2006 iJ PARALLEL Bus To IEEE1394 BRIDGE a aa SsS Rev 1 OrSys Page 32 bo en switches between UO pin and HPI usage hpi width number of bits hpi handshake
130. ssembly sampling at 100kHz 16bit packet size 40 bytes f USER S GUIDE Date 25 October 2006 Doc no Bridge UG LJ PARALLEL Bus To IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 53 3 8 1 2 Asynchronous Streaming Asynchronous streaming is similar to isochronous transfers Asynchronous streaming uses the same data packets as an isochronous transfer At the receiver side it makes no difference whether isochronous or asynchronous streaming is used Packets may be sent anytime provided that the bus is free Bus bandwidth is not guaranteed here so the transmission of a packet may be blocked by other transfers on the bus Asynchronous streaming should be used when latency requirements don t allow isochronous streaming and bus bandwidth can be guaranteed by system design 3 8 1 3 Asynchronous Transactions Asynchronous transactions are handled by transaction layer software Each data packet that is sent receives a response from the addressed device Asynchronous transfers can occur at any time provided that the bus is free They are point to point transfers so the originator of the transfer must know who to talk to An asynchronous transfer consists of a request that is sent to the destination device and a response that the destination device sends back This enables error checking at the sender Asynchronous transfers are well suited for e data that occurs randomly e g control and status information e transfers where the
131. stic Interface over the LED see En rotta near eege EH abeng EEN ESE E 46 3 5 5 Description of Available Error Codes AAA 47 3 5 6 Description of Available Detailed Error Codes 00 ccecceeceeeeeeeeeeeeeeeeeeaeeeeeseaeeeeesenaaeeeeenaas 48 3 5 7 Diagnostic Interface Configuration suona nona Rer Rh ennt Ri hanc mrt HS olia B Rita duce 49 3 6 Configuration Inlenace cet M 50 3 6 1 Configuration Interface Configuration nenene anne nene n nn nn 51 3 6 2 Configuration Interface DISAIS osea ratto nbus oen Rem btt et tpa Eme pausa 51 3 7 Registration Interface iuis sx sur oic non Gs xd ces ERR h k aan m sss RM SFR NER 51 3 7 1 Registration Interface Contouraiion nnne 51 3 8 IEEET394 interface zeru u aa ae QU ER REV E rc rop dE ER a n nA A 51 3 8 1 IEEET394 Data Transfer MethodS EE 51 3 8 2 EEE1394 Cable Power ODD iret net tete esce tick itk ned 53 4 CONFIGURBATION n n n n n n n a a a ana 53 41 Configuration Mode isa css etek ees eee ee ee eee 53 4 1 1 Customized Configuration ENEE 54 42 e nrismp 55 4 3 Common Device Parameters eeeeeeeeeeeeeeeeeeeene nennen tnn A unen nnn nna nnne nnn nasse nnns nn 55 43 A Device ID GOV Enger EE 56 43 2 Default Partner Device partner dev iuieuiieca rie tede rides cse Hia B Ese MER dee 56 4 3 3 e 56 4 3 4 FPGA Revision TIBUS TOV EE 56 4 3 5 Sof
132. streaming port data width Therefore in 16 bit configuration one data word is available and in 8 bit mode two data words are available In transmit direction from the streaming port to the IEEE1394 network a low level on STR FLAGO or CAM FLAGO indicates that the streaming port s FIFO can accept at least one more 16 bit data word This is independent of the configured streaming port data width Therefore in 16 bit configuration the FIFO can accept at least one more data word and in 8 bit mode it can accept at least two more data words This signal can be used as e synchronization flag e underrun overrun indicator for unsynchronized transfers In case of isochronous transfers which is the default transfer method for the streaming port the FIFO gets filled or emptied with each isochronous cycle every 125ys See also chapter 3 8 1 for a description of isochronous packetizing Please note Due to timing of STR FLAGO only transfers of limited speed are possible see chapter 7 8 1 for timing details For full speed transfers STR FLAG1 must be used STR FLAG1 CAM FLAG1 This signal is active low It works as a synchronization flag for block synchronized data transfers A low level on STR FLAG1 or CAM FLAG indicates that one more block of data can be transferred between external hardware and the streaming port A block of data is defined by configuration parameter str blksize STR FLAG1 or CAM FLAG1 is active low when a streami
133. t io partner dev io partner inst io en O pins 16 26 input open drain output virtual connection to partner pin disabled use common device parameter partner dev UART Date 25 October 2006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 orsys Page WEN Q uart baud 115200baud 1 1 1 luari partner nst 0 use dynamic packet size uart_ev_bufsize uart resume Io none I O 21 20 enabled use common device parameter partner dev pi partner inst Io a j HPI hpi resume JO diag iftype no hardware signaling diag connect diag partner dev diag partner inst cfg partner dev cfg partner inst c g ev bufsize Table 52 Predefined configuration mode 2 hpi rx bufsize hpi flowctl disabled ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG us PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 92 7 9 4 Configuration Mode 3 15 MBps Predefined Configuration This is a high bandwidth configuration with up to 5096 of the maximum bandwidth This is the highest bandwidth that can be transmitted without synchronization by STR FLAGO STR_FLAG1 Device common parameters partner dev foga ver foga rev VCD ver str tx pktsize str xfertype str partner dev use common device parameter partner dev str partner inst 0 str width 16 bit str iftype str auto str blksize str frmsync o di
134. te data into the transmit FIFO of the streaming port Data on STR D 15 0 is clocked in with each rising edge of STR CLK If the FIFO can no longer accept data indicated by a high level on STR FLAGO because it is full any data written to it will be ignored STR WE is ignored when the streaming port is configured for receive operation STR RE When the streaming port is configured for generic interface mode and receive direction from IEEE1394 network to the streaming port STR RE is used to read data from the receive FIFO of the streaming port Data on STR D 15 0 is driven while STR RE is active low If the receive FIFO is empty no data has yet been received the data on STR D 15 0 is invalid The first data received from the IEEE1394 network will be automatically read out of the FIFO and its availability will be indicated by STR FLAGO This means the first read operation already reads out the first data word without any clock required This feature is similar to the first word fall through mode of discrete FIFO components CAM FEN When the streaming port is configured for imaging interface mode and transmit direction from the streaming port to the IEEE1394 network CAM FEN is the high active frame enable signal that indicates that a picture frame is currently being transferred An active CAM FEN signal has two effects e A rising edge of CAM FEN causes that the current data is transferred with the synchronization information
135. th up to 7 MCMs dev id should be set to read from I O pin and jumpers or switches should be implemented to set the ID 4 3 2 Default Partner Device partner dev This parameter defines the default partner device for virtual connections of the local device In order to use this parameter the respective interface must have its xxx partner dev parameter set to use common partner Allowed values for partner dev are e The device ID of a remote device 0 6210 e read from UO pin The upper 3 bits of the device ID are set to zero and the lower 3 bits are read from IO 21 19 see chapter 6 4 for wiring examples In systems where one single UC1394a 1 MCM and one PC running the VCP SDK is used partner dev should be set to 0 since this is the default setting for the PC s device ID 4 3 8 FPGA Version fpga ver This parameter is used for informational purposes only It is read only and identifies the version of the currently loaded FPGA For the UC1394a 1 MCM equipped with the streaming BSP version 4 is required 0000000046 experimental or user defined FPGA 0000000115 streaming BSP V1 no HPI no IEEE1394 flow control 00000002 000000036 000000046 0000000516 000000FF18 000001006 FFFFFFFF 16 4 3 4 FPGA Revision fpga rev This parameter is used for informational purposes only It is read only and identifies the revision of the currently loaded FPGA Newer revisions have higher numbers The features described throug
136. tion tool The UC1394a 1 MCM is designed for end application use It can be directly integrated into customer hardware allowing mass production with small form factor and low cost For easy system integration a bridging kit is available as a separate product providing quick and easy start by using a carrier board that provides all necessary connectors and power supply 1 For applications that require a customized version of the bridge various development kits for software and FPGA development are available Parallel bus to IEEE1394 Bridge Streaming 8 16 bit high speed port data streaming main interface gt i Up to 27 bit I O Pins Virtual Connection general purpose UC Protocol VCP IEEE1394 Host Port 8 16 bit host port interface for control purposes UART interface for control and status exchange Configuration tool Figure 1 Parallel bus to IEEE1394 Bridge overview USER S GUIDE Date 25 October 2006 Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 orsys Page 12 IEEE1394a chipset Streaming Port IEEE1394 9 D 20 o Port 0 S A Data IEEE1394 o S Port 1 o Beet a Control Control Microcontroller logic flags interface UART interface 8 character RxD Rx FIFO Control logic TxD Handshake RTS CTS Host port interface Data Reset input Control 8 16 bit ontro Reset ouput i Control logic Handshake Power 3 3 V supply Figu
137. tion when a module is operated in a customized hardware environment for the first time Please note that in configuration mode 15 the UART interface is used for configuration and firmware update and is therefore not available The passive configuration for mode 14 and 15 can be overridden by configuration Device common parameters dev id own ID is read from pins l O 18 16 partner dev partner ID is read from pins l O 21 19 foga ver indicates current FPGA revision indicates current firmware version sw rev indicates current firmware revision vcp ver 001000446 VCP V1 4 str idis read from pi 0 sw ver Di o str ch partner inst eneric interface bytes 1 quadlet no sync pattern I O pins 0 26 io dir io otype io state io connect io partner dev i io_enable 15200 baud TS CTS handshake enabled virtual connection to partner device disabled use common device parameter partner dev use dynamic packet size 0 ms ize Ko o 2 Istr ch Str auto m Ho dir lo otype o state Lio connect Lio partner dev io enable uart_tx uart t uart_ev_bufsize 2048 4096 isabled uart_suspend 096 uart_resume uart rx fifo size uart tx fifo size AO c time v bufs wctl Date 25 October 2006 e USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE 1394 BRIDGE Iss Rev 1 1 Orsys Page 107 Q Parameter name ettin
138. to 3 3V recommended McBSP 2 0 FSX Transmit frame synchronization or general purpose I O Polarity Built in termination Handling when not used bi directional programmable 10k pull up to 3 3V recommended 7 2 7 JTAG Signals Please note although not used with the Parallel bus to IEEE1394 Bridge the DSP JTAG pins should be available for service purposes see Figure 33 The FPGA JTAG signals are not required ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG us PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 Orsys Page 74 JTAG DSP EMU 1 0 Emulator control Polarity Built in termination Handling when not used Bidifectional lactveshigh Jaco JTAG DSP TRST Test reset input Polarity Built in termination Handling when not used pull down DSP JTAG DSP TCK Test clock Polarity Built in termination Handling when not used pull up DSP JTAG DSP TDO Test data output Polarity Built in termination Handling when not used active high JTAG DSP TDI Test data input Built in termination Handling when not used pull up DSP JTAG DSP TMS Test mode select Polarity Built in termination Handling when not used pull up DSP JTAG FPGA TCK Test clock JTAG FPGA TDO Test data output Polarity Built in termination Handling when not used active high 10k pull up to 3 3V recommended JTAG FPGA TDI Test data input Pol
139. to leave it untouched uiReg amp HPIC2 ERRDTCT clear HPICA bit uiReg amp HPICX HPICA switch to HPIC1 HPI REG HPIC2 ulReg dif 0 slow but more readable version get HPIC1 uiReg HPI READ HPIC1 enable RRDY handshake in HPIC1 and stay in HPIC1 uiReg HPIC1 RRDY EN HPI WRITE HPICI1 ulReg switch to HPIC2 set HPICA bit uiReg HPICX HPIC2 HPI WRITE HPICI1 ulReg else fast version enable RRDY handshake in HPIC1 and switch to HPIC2 uiReg HPIC1 RRDY EN HPICX HPIC2 HPI WRITE HPICI1 ulReg Date 25 October 2006 CS USER S GUIDE Doc no Bridge UG PARALLEL Bus TO IEEE1394 BRIDGE k Iss Rev 1 1 Orsys Page 38 endif clear ERRDTCT in HPIC2 acknowledge the last error uiReg HPI READ HPIC2 uiReg HPIC2 ERRCLR HPI WRITE uiReg 3 3 3 3 HPI Control Register 2 HPIC2 This register is used for diagnostic purposes It provides an alternative access to the 3 bit error code see Table 16 The host uses this register to check for errors e determine the error type e acknowledge an error See also chapter 3 5 for using the diagnostic interface 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPICA RESERVED ERRDTCT ERR rw 0 r 00000000000 r wc 0 r 000 ERR This bit field contains the current error code as defined by Table 16 ERRDTCT This bit indicates that an error is present
140. tual connections can t be established Therefore PC users should implement the following start up sequence e open the device open the required interfaces read out the error FIFO ignore any errors about missing partner interfaces where the PC is the partner device clear the error FIFOs to achieve a clean startup state e g no LED blinking 3 5 6 Description of Available Detailed Error Codes Diagnostics over IEEE1394 provide a more detailed error code Each of the detailed error codes is associated with an error code of the local diagnostic interfaces from Table 16 LN USER S GUIDE Ge l a 2006 NI PARALLEL Bus TO IEEE1394 BRIDGE Boo i Orsys Page 49 Detailed ERR 2 0 Meaning error code 0000 0 No error No or invalid valid user defined configuration FPGA version stored in flash not supported by this firmware Error during configuration User defined configuration was created with other VCP version Receive all is not allowed for transmit operation reserved Remote interface disabled xxx enable disabled Remote interface disabled VCP xxx connect disabled Remote interface configured to wrong direction io dir reserved Streaming port FIFO overflow Streaming port FIFO underflow read from empty FIFO IEEE1394 chipset signals an error streaming port only UART event buffer overflow UART receiver FIFO overflow HPI event buffer overflow HPI transmit FIFO overflow HPI to host HPI
141. tware En EE 56 4 3 6 Software Revision Eeer 57 AS NGP Ee WEE 57 5 VIRTUAL CONNECTION PROTOCOL z mn K K nn 57 5 1 Accessing the UC1394a 1 MCM Using the VCP SDK eee 58 5 2 Using VCP Without the SDK san o aha nasa eode nk p tice c kule EES 60 6 HARDWARE IMPLEMENTATION GUIDELINES eere 61 LS USER S GUIDE un l a 2006 LJ PARALLEL Bus To IEEE1394 BRIDGE Isc Den iL Orsys Page 4 6 1 Power SUpPIV ee 61 6 2 JEEET394 Interface sam ana a r r a oh FR 61 6 3 e ut d UE Un 63 6 4 Device and Partner ID from UO PinS lt eeeneeeeeeeneneee eee ne aaa ae ana nennen nnne 64 6 5 RS 232 Level GonVert f mos man ns mimo M 65 SOME EE 65 6 7 Un sed KE EC 66 6 8 Minimal Connection Example rro enu iir eno n apo nk tena an atak ak Sena x Ina eaa n ap nudn k nna kaz nnana 66 F TECHNICAL DATA eT 68 7 1 Connector Pinout Tables nietos l sm n a ae esk kine pe ads n a iE A Ru na 68 7 2 Individual Signal Description inerte tran rane eicit i n rua eere k ined 71 7 2 1 Power Supply and Reset Signals AEN 71 7 2 2 Streaming Port le E 71 7 2 8 UO Pins Host Port and Diagnostic Interface 72 Te UART SONAS oeren a a A E M E ME Mu ee ne 72 725 EEE TOGA Signals sencon a a ere 73 726 escis 78 prova oP Ale Boj o pr c Ia 73 7 2 8 External
142. us Amendment 1 IEEE sca 13942 2000 6 FireWire System architecture by Don Anderson Mind Share Inc ISBN 0 201 48535 x 7 Virtual Connection Protocol API Thesycon vcPrefman pdf
143. wed for being connected to a 5V system Please refer to 2 for a detailed description of the FPGA s LVTTL signal levels Parameter Value Compatible I O standards 5V TTL 3 3V LVTTL 2 5V CMOS High input level 20V 295 V Low input level 0 5V 0 8V High output level Low output level max 0 4 V maximum DC load Table 34 Signal levels and loads for I O pins O 11 0 and l O 26 15 Parameter Value Compatible I O standards 3 3V LVTTL 2 5V CMOS High input level 2 0V 3 6V High output level Low output level maximum DC load Table 35 Signal levels and loads for I O pins O 14 12 Low input level 0 5 V 0 8V 7 7 2 Streaming Port Signals These signals are connected to the FPGA They use a 5V input tolerant LVTTL I O standard Please refer to 2 for a detailed description of signal levels ly USER S GUIDE Date 25 October 2006 e Doc no Bridge UG uU PARALLEL Bus TO IEEE1394 BRIDGE Iss Rev 1 1 OrsSys Page 79 Value Parameter Compatible I O standards 5V TTL 3 3V LVTTL 2 5V CMOS 2DV DBV High input level Low input level High output level Low output level maximum DC load Table 36 Signal levels and loads for the streaming port signals STR xxx 0 5V 0 8V 7 7 8 UART Signals These signals are connected to the FPGA They use a 5V input tolerant LVTTL I O standard Please refer to 2 for a detailed description of signal levels Parameter Value Compatible I

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