Home

Texas Instruments TMS320TCI648x User's Manual

1. www ti com SRIO Functional Description Figure 6 1x 4x RapidlO Packet Data Stream Streaming Write Class n 64 80 gt PHY TRA LOG TRA LOG PHY _ WwW 72 4 _ 6 _ n 64 32 16 a e et m p a Se 2 a Ze as SC ES ep s d Ce di x De ee ve ackiD rsv prio tt ftype destiD sourcelD address rsrv xamsbs double word 0 double word 1 double word n 2 double word n 1 crc PHY Physical layer TRA Transport layer 5 3 2 24 8 8 a 1 2 64 64 464 64 64 16 LOG Logical layer le n 64 96 gt PHY TRA LOG TRA LOG PHY LOG PHY CC 16 9 64 32 16 n 9 64 ns a x ea o ee a a N N gt SC i i 2 a Fre Z pr SS N a _ SS N KI a A _ SON acklD rsv prio tt ftype destID sourcelD address rsrv xamsbs double word 0 double word d doubie word 8 double word 9 CRC double word 10 double word 11 m double word n 2 double word n 1 CRC 5 3 2 2 4 8 8 29 1 2 64 64 5 64 64 64 16 64 64 n 13 64 64 64 16 Note Figure 6 assumes that addresses are 32 bit and device IDs are 8 bit The device ID being an 8 bit field will address up to 256 nodes in the system If 16 bit addresses were used the system could accommodate up to 64k nodes The data stream includes a Cyclic Redundancy Code CRC field to ensure the data was correctly received
2. lt TX_Queue_Map3 gt lt TX_Queue_Map2 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 3h R W 0 R W 2h lt TX_Queue_Map1 gt lt TX_Queue_Map0 gt 15 12 11 8 7 4 3 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 1h R W Oh R W Oh TX_QUEUE_CNTL1 Address Offset 07E4h lt TX_Queue_Map7 gt lt TX_Queue_Map6 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W 0 R W 7h R W Oh R W 6h Be TX_Queue_Map5 gt sr TX_Queue_Map4 gt 15 12 11 817 43 Y Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 5h R W Oh R W 4h TX_QUEUE_CNTL2 Address Offset 07E8h eege TX_Queue_Map11 Gees TX_Queue_Map10 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W Bh R W Oh R W Ah Be TX_Queue_Map9 gt rn TX_Queue_Map8
3. 31 24 23 18 17 16 ERROR_RATE_ ERROR_RATE_BIAS Reserved RECOVERY R W FFh R 00h R W 00 15 8 7 0 PEAK_ERROR_RATE ERROR_RATE_COUNTER R W 00h R W 00h LEGEND R W Read Write R Read only n Value after reset Table 173 Port Error Rate CSR n SPn_ERR_RATE Field Descriptions Bit Field Value Description 31 24 ERROR_RATE_BIAS These bits provide the error rate bias value 00h Do not decrement the error rate counter Oth Decrement every 1ms nominal 03h Decrement every 10ms nominal 07h Decrement every 100ms OFh Decrement every 1s nominal 1Fh Decrement every 10s nominal 3Fh Decrement every 100s nominal 7Fh Decrement every 1000s nominal FFh Decrement every 10000s nominal Other Reserved 23 18 Reserved 00h These read only bits return Os when read 17 16 ERROR_RATE_RECOVERY These bits limit the incrementing of the error rate counter above the failed threshold trigger 00b Only count 2 errors above 01b Only count 4 errors above 10b Only count 16 errors above 11b Do not limit incrementing the error rate count 15 8 PEAK_ERROR_RATE 00h FFh This field contains the peak value attained by the error rate counter 7 0 ERROR_RATE_COUNTER 00h FFh These bits maintain a count of the number of transmission errors that have occurred If this value equals the value contained in the error rate threshold trigger register then an error will be reported 228 Serial RapidlO SRIO SPR
4. PHY TRA LOG TRA LOG PHY 10 Fi 2 Be 2 16 7 32 b 6 7 3 e D M o ra P d Fa ye r Pr 1 ra Be x a Es 1 fy E y F fy b F 7 D e j o gf L x a Z PA ze X a a x D ackID rsv prio tt 1010 destID sourcelD Reserved srcTID info msb info Isb CRC 5 3 2 2 4 8 8 8 8 8 8 16 De DH S 1 7 1 7 1 as 1 a H a Ze 1 7 9 2 1 4 H Reserved Doorbell Reg rsv Doorbell bit The DOORBELL packet s 16 bit INFO field indicates which DOORBELL register interrupt bit to set There are four DOORBELL registers each currently with 16 bits allowing 64 interrupt sources or circular buffers see Table 23 Each bit can be assigned to any core as described below by the Interrupt Condition Routing Registers Additionally each status bit is user defined for the application For instance it may be desirable to support multiple priorities with multiple TID circular buffers per core if control data uses a high priority for example priority 2 while data packets are sent on priority O or 1 This allows the control packets to have preference in the switch fabric and arrive as quickly as possible Since it may be required to interrupt the CPU for both data and control packet processing separately separate circular buffers are used and DOORBELL packets need to distinguish between them for interrupt servicing If any reserved bit in the DOORBELL info field is set an error respo
5. gt 15 12 11 8 7 4 3 4 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 9h R W Oh R W 8h TX_QUEUE_CNTL3 Address Offset 07ECh lt TX_Queue_Map15 gt lt TX_Queue_Map14 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W Fh R W Oh R W Eh lt TX_Queue_Map13 gt lt TX_Queue_Map12 gt 15 12 11 8 7 4 3 S Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W Dh R W Oh R W Ch 174 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Table 117 SRIO Registers Transmit CPPI Weighted Round Robin Control Register Field Descriptions Field Pair Register Bits Field Value Description TX_Queue_Map0 TX_QUEUE_CNTLO 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 7 4 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map1 TX_Queue_Map1 TX_QUEUE_CNTLO 1 1 8 Queue Pointer Oh to Fh Pointer to a queue This pointer c
6. 184 Bit Field Value Description 31 16 ASSY_IDENTITY 0000h Assembly identifier Vendor specific 15 0 ASSY_VENDORIDENTITY 0030h Assembly vendor identifier assigned by RapidlO Trade Association Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i EXAS INSTRUMENTS www ti com SRIO Registers 5 55 Assembly Information CAR ASBLY_INFO The assembly information CAR ASBLY_INFO is shown in Figure 118 and described in Table 126 This register is used by SERDES vendor to designate endpoints among the various function blocks of registers Writes have no effect to this register The values are hard coded and will not change from their reset state 31 Figure 118 Assembly Information CAR ASBLY_INFO Address Offset 100Ch 16 15 ASSYREV EXTENDEDFEATURESPTR LEGEND R Read only n Value after reset R 0000h R 0100h Table 126 Assembly Information CAR ASBLY_INFO Field Descriptions Bit Field Value Description 31 16 ASSYREV 0000h Assembly revision level 15 0 EXTENDEDFEATURESPTR 0100h Pointer to first entry in extended features list SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 185 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 56 Processing Element Features CAR PE_FEAT The processing element features CAR PE_FEAT is shown in Figure 119 and described in Table 127 Figure 119 Proces
7. 31 16 Reserved HO 15 3 2 1 0 Reserved PEREN SOFT FREE HO R W 0 R W 0 R W 1 LEGEND R W Read Write R Read only n Value after reset Table 29 Peripheral Control Register PCR Field Descriptions Bit Field Value Description 31 3 Reserved 0 These read only bits return Os when read 2 PEREN Peripheral enable Controls the flow of data in the logical layer of the peripheral As an initiator it will prevent TX transaction generation as a target it will disable incoming requests This should be the last enable bit to toggle when bringing the device out of reset to begin normal operation 0 Data flow control is disabled 1 Data flow control is enabled 74 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com SRIO Functional Description Table 29 Peripheral Control Register PCR Field Descriptions continued Bit Field Value Description 1 SOFT Soft stop This bit and the FREE bit determine how the SRIO peripheral behaves during emulation halts 0 Hard stop All status registers are frozen in default state This mode is not supported on the SRIO peripheral 1 Soft stop 0 FREE Free run 0 The SOFT bit takes effect 1 Free run Peripheral ignores the emulation suspend signal and functions normally 2 3 12 Free Run Mode default mode Peripheral does not respond to an emulation suspend asser
8. 31 30 16 RESPONSE VALID Reserved HO HO 15 10 9 5 4 0 Reserved ACKID_STATUS LINK_STATUS R 0 R 0 R 0 LEGEND R Read only n Value after reset Table 143 Port Link Maintenance Response CSR n SPn_LM_RESP Field Descriptions Bit Field Value Description 31 RESPONSE_VALID If the link request causes a link response this bit indicates that the link response has been received and the status fields are valid If the link request does not cause a link response this bit indicates that the link request has been transmitted This bit automatically clears on read 30 10 Reserved 0 These read only bits return Os when read 9 5 ACKID_STATUS 00000b 11111b AcklD status field from the link response control symbol 4 0 LINK_STATUS 00000b 11111b Link status field from the link response control symbol SPRUE13A September 2006 Serial RapidlO SRIO 201 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com 5 71 Port Local AckID Status CSR n SPn_ACKID_STAT Each of the four ports is supported by a register of this type see Table 144 The port local ackID status CSR n SPn_ACKID_STAT is shown in Figure 134 and described in Table 145 Table 144 SPn_ACKID_STAT Registers and the Associated Ports Register Address Offset Associated Port SPO_ACKID_STAT 1148h Port 0 SP1_ACKID_STAT 1168h Port 1 SP2_ACKID_STAT 1188h Port 2 SP3_ACKID_STAT 11A8h Port 3 Figure
9. SPRUE13A September 2006 Serial RapidlO SRIO 235 Submit Documentation Feedback SRIO Registers 5 96 Port Control Independent Register n SPn_CTL_INDEP da TEXAS INSTRUMENTS www ti com Each of the four ports is supported by a register of this type see Table 182 The port control independent register n SPn_CTL_INDEP is shown in Figure 159 and described in Table 183 Table 182 SPn_CTL_INDEP Registers and the Associated Ports Register Address Offset Associated Port SPO_CTL_INDEP SP1_CTL_INDEP SP2_CTL_INDEP SP3_CTL_INDEP 14004h Port 0 14104h Port 1 14204h Port 2 14304h Port 3 Figure 159 Port Control Independent Register n SPn_CTL_INDEP 31 30 29 28 27 26 25 24 Reserved TX_FLW SOFT_REC Reserved FORCE_REINIT TRANS MODE R 0 R W 0 R W 0 R 0 W 0 R W 01 23 22 21 20 19 18 17 16 SEND DBG_ ILL TRANS ILL TRANS MAX_RETRY_ MAX RETRY DEBUG PKT EN ERR Reserved EN ERR R W 0 R W 0 R W 0 R W 0 R 0 R W 0 R W 0 15 8 MAX RETRY THR R W 00h 7 6 5 0 IRQ_EN IRQ_ERR Reserved R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n Value after reset Table 183 Port Control Independent Register n SPn_CTL_INDEP Field Descriptions Bit Field Value Description 31 Reserved 0 This read only bit returns 0 when read 30 TX_FLW Transmit Link Flow Control enable Disables transmit flow control
10. 20 124 56 SERDES_CFGRXn_CNTL Registers and the Associated Porte 125 57 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions 125 58 EQ Bits nun dee dE E EELER 126 59 SERDES_CFGTXn_CNTL Registers and the Associated Porte 128 60 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL Field Descriptions 128 61 DE Bits of SERDES CFGTXN e HE 129 62 SWING Bits of SERDES_CFGTXn_ONTL u2usassnnannnnn nun mann ann nun nun nannn eee eee ee eee eee eee 129 63 SERDES_CFGn_CNTL Registers and the Associated Portes 130 64 SERDES Macro Configuration Register n SERDES_CFGn_CNTL Field Descripogons 130 65 aigle ET ET 132 66 DOORBELL Interrupt Condition Status Register DOORBELLn_ICSR Field Descriptions 132 67 DOORBELL AIG GR EE 133 68 DOORBELLn Interrupt Condition Clear Register DOORBELLn_ICCR Field Descipttons 133 69 RX CPPI Interrupt Condition Status Register RX_CPPI_ICSR Field Descriptions 134 70 RX CPPI Interrupt Condition Clear Register RX_CPPI_ICCR Field DescriptionS sssssssnnsnrerssrnnns 135 71 TX CPPI Interrupt Condition Status Register TX_CPPI_ICSR Field Descriptions seseeeeeeeeeeeees 136 72 TX CPPI Interrupt Condition Clear Register TX_CPPI_ICCR Field Descriptions 0 sseeeeeeeeeeeeeees 137 73 LSU Interrupt Condition Status Register LSU_ICSR Field Descriptons sees erence eeeeeeeeee 138 74 LSU Interrupt Condition Clea
11. Register Address Offset Associated LSU LSU1_REG4 0410h LSU1 LSU2_REG4 0430h LSU2 LSU3_REG4 0450h LSU3 LSU4_REG4 0470h LSU4 Figure 98 LSUn Control Register 4 LSUn_REG4 31 30 29 28 27 26 25 24 23 OUTPORTID PRIORITY XAMSB ID_SIZE DESTID R W 00 R W 00 R W 00 R W 00 R W 0000h 8 7 1 0 INTERRUPT_ DESTID Reserved REQ R W 0000h R 00h R W 0 LEGEND R W Read Write R Read only n Value after reset Table 96 LSUn Control Register 4 LSUn_REG4 Field Descriptions Bit Field Value Description 31 30 OUTPORTID 00b 11b Indicates the number of the output port 0 1 2 or 3 from which the packet is to be transmitted Specified by the CPU along with the node ID The output port value is not included in the RapidlO header 29 28 PRIORITY 00b 11b Supplies the prio field of the RapidlO packet header to indicate packet priority To avoid system deadlock it is recommended that request packets not be sent with priority level 3 It is the responsibility of the software to assign the appropriate outgoing priority 27 26 XAMSB 00b 11b Supplies the xamsb field of the RapidlO packet header to specify the 2 MSBs of the extended RapidlO address 25 24 ID_SIZE Supplies the tt field of the RapidlO packet header to specify whether 8 bit or 16 bit DevicelDs are used 00b 8 bit device IDs 01b 16 bit device IDs 1xb Reserved 23 8 DESTID 0000h Supplies the destination ID field of the RapidlO
12. W Doorbell 0 ICSR 15 0 gt W Doorbell 1 ICSR 15 0 gt WM Doorbell 2 ICSR 15 0 K Doorbell 3 ICSR 15 0 gt A Please note that bits 0 through 15 of this ICSR correspond to bits 31 through 16 of the ISDR For example bit 15 of the ICSR corresponds to bit 31 of the ISDR and so on B Please note that bits 15 through 0 of this ICSR correspond to bits 15 through 0 of the ISDR For example bit 15 of the ICSR corresponds to bit 15 of the ISDR and so on As an example of reading an ISDR if bit 29 of the ISDR is set this indicates that there is a pending interrupt on either the TX CPPI queue 2 or RX CPPI queue 2 Figure 61 illustrates the decode routing for this example 98 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback ii INSTRUMENTS www ti com Interrupt Conditions Figure 61 Example Diagram of Interrupt Status Decode Register Mapping TX CPPI ICRR TX CPPI ICSR Interrupt Status Decode Registers 29 INTDSTO o 29 INTDST1 eo 29 INTDST2 e Ze 29 INTDST3 TX CPPIICRR 29 INTDST4 RX CPPI ICSR ee 29 INTDST5 ee 29 INTDST6 oO 29 INTDST7
13. HO HO R 0 HO HO HO R 0 HO HO HO HO HO HO HO HO HO RX CPPI Interrupt Condition Clear Register RX_CPPI_ICCR Address Offset 0248h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO WO WO WO WO WO WO WO WO W 0 W 0 WO WO W 0 WO WO WO LEGEND R Read only W Write only n Value after reset Figure 51 TX CPPI Interrupt Condition Status and Clear Registers TX CPPI Interrupt Condition Status Register TX_CPPI_ICSR Address Offset 0250h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO HO R 0 R 0 HO R 0 R 0 R 0 HO HO R 0 R 0 HO R 0 R 0 R 0 HO TX CPPI Interrupt Condition Clear Register TX_CPPI_ICCR Address Offset 0258h 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO LEGEND R Read only W Write only n Value after reset 4 3 3 LSU Interrupt Condition Status and Clear Registers The ICSR and the ICCR for the LSUs are shown in Figure 5
14. Figure 80 RX CPPI Interrupt Condition Clear Register RX_CPPI_ICCR Address Offset 0248h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO W 0 W 0 W 0 W 0 WO W 0 W 0 W 0 WO W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n Value after reset Table 70 RX CPPI Interrupt Condition Clear Register RX_CPPI_ICCR Field Descriptions Bit Field Value Description 31 16 Reserved 0 These read only bits return 0 when read 15 0 ICCx RX CPPI interrupt clear x Taian 0 No effect 1 Clear bit x of RX_CPPI_ICSR Serial RapidlO SRIO 135 SPRUE13A September 2006 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 20 TX CPPI Interrupt Status Register TX_CPPI_ICSR The bits in this register indicate any active interrupt requests from TX buffer descriptor queues TX_CPPI_ICSR is shown in Figure 81 and described in Table 71 Figure 81 TX CPPI Interrupt Condition Status Register TX_CPPI_ICSR Address Offset 0250h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO R W 0 R W 0 R W 0 R W 0 R W 0 R
15. 10 ICS10 LSU2 interrupt condition not detected LSU2 interrupt condition detected Transaction was not sent due to Xoff condition ICS9 Oj O LSU2 interrupt condition not detected LSU2 interrupt condition detected Non posted transaction received ERROR response or error in response payload ICS8 LSU2 interrupt condition not detected LSU2 interrupt condition detected Transaction complete No errors posted non posted Enable for this interrupt is ultimately controlled by the Interrupt Req bit of LSU2_REG4 This allows enabling disabling on a per request basis For optimum LSU performance interrupt pacing should not be used on the LSU interrupts ICS7 LSU1 interrupt condition not detected LSU1 interrupt condition detected Packet not sent due to unavailable outbound credit at given priority ICS6 _ LSU1 interrupt condition not detected LSU1 interrupt condition detected Retry Doorbell response received or Atomic test and swap was not allowed semaphore in use ICS5 LSU1 interrupt condition not detected LSU1 interrupt condition detected Transaction was not sent due to DMA data transfer error ICS4 LSU1 interrupt condition not detected LSU1 interrupt condition detected Transaction timeout occurred ICS3 Oj O O LSU1 interrupt condition not detected LSU1 interrupt condition detected Transaction was not sent due to unsupported transaction type or invalid fi
16. 10b Alignment jog The symbol alignment will be adjusted by one bit position when this mode is selected that is the ALIGN value changes from Oxb to 1xb 11b Reserved 11 Reserved 0 This read only bit returns 0 when read 10 8 TERM 001b Input termination The only valid value for this field is 001b all other values are reserved The value 001b sets the common point to 0 8 VDDT and supports AC coupled systems using CML transmitters The transmitter has no effect on the receiver common mode which is set to optimize the input sensitivity of the receiver Common mode termination is via a 50 pF capacitor to VSSA 7 INVPAIR Invert polarity Inverts polarity of RIORXn and RIORXn 0 Normal polarity RIORXn is considered to be positive data and RIORXn negative 1 Inverted polarity RIORXn is considered to be negative data and RIORXn positive 6 5 RATE Operating rate Selects full half or quarter rate operation 00b Full rate Two data samples taken per PLL output clock cycle O1b Half rate One data sample taken per PLL output clock cycle 10b Quarter rate One data sample taken every two PLL output clock cycles 11b Reserved Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 9 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions continued Bit Field Value Description 4 2 BUSWIDTH 000b
17. 31 1 0 Reserved EN HO R W 1 LEGEND R W Read Write R Read only n Value after reset Table 47 Block n Enable Register BLKn_EN Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 EN Block n enable 0 Logical block n is to be reset with its clock off Logical block nis to be enabled with its clock running SPRUE13A September 2006 Serial RapidlO SRIO 119 Submit Documentation Feedback SRIO Registers Block n Enable Status Register BLKn_EN_STAT There are nine of these registers one for each of nine logical blocks in the peripheral The registers and the blocks they support are listed in Table 48 The general form for a block n enable status register BLKn_EN_STAT is shown in Figure 69 and described in Table 49 For additional programming information see Section 2 3 10 5 8 da TEXAS INSTRUMENTS www ti com Table 48 Block n Enable Status Registers and the Associated Blocks Register Address Offset Associated Block BLKO_EN_STAT 003Ch Logical block 0 the set of memory mapped control registers for the SRIO peripheral BLK1_EN_STAT 0044h Logical block 1 the Load Store module the four LSUs and supporting logic BLK2_EN_STAT 004Ch Logical block 2 the memory access unit MAU BLK3_EN_STAT 0054h Logical block 3 the message transmit unit TXU BLK4_EN_STAT 005Ch Logical block 4 the message receive unit RXU BLK5_EN_STAT 0064h Logical block 5 SRIO port 0
18. 31 16 15 0 Reserved FLOW_MASK R 00h R W FFh LEGEND R W Read Write R Read only n Value after reset Table 102 LSUn Congestion Control Flow Mask Register LSUn_FLOW_MASKS Field Descriptions Bit Field Value Description 31 16 Reserved 00h These read only bits return Os when read 15 0 FLOW_MASK 00h FFh Flow mask for LSUn Figure 102 LSUn FLOW_MASK Fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FL15 FL14 FL13 FLi2 FL11 FL10 FLO FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FLO R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R Read W Write n Value after reset Table 103 LSUn FLOW_MASK Fields Bit Field Value Description 15 FL15 0 LSUn does not support Flow 15 from table entry 1 LSUn supports Flow 15 from table entry 14 FL14 0 LSUn does not support Flow 14 from table entry 1 LSUn supports Flow 14 from table entry 13 FL13 0 LSUn does not support Flow 13 from table entry 1 LSUn supports Flow 13 from table entry 12 FL12 0 LSUn does not support Flow 12 from table entry 1 LSUn supports Flow 12 from table entry 11 FL11 0 LSUn does not support Flow 11 from table entry 1 LSUn supports Flow 11 from table entry 10 FL10 0 LSUn does not support Flow 10 from table entry 1 LSUn supports Flow 10 from table entry 9 FL9 0 LSUn does not support
19. 5 4 Peripheral Settings Control Register DER GET ONT 11a 5 5 Peripheral Global Enable Register GBL_EN ecseeeeeeeeee eee seen eee eee seen eee eeeeeeeeeeneeeaees 116 5 6 Peripheral Global Enable Status Register OGBL EN GIAT 117 5 7 Block n Enable Register BLKn_EN EE 119 5 8 Block n Enable Status Register Glkn EN SGIAT eee neces nun nn nn nun nun nann nennen 120 5 9 RapidlO DEVICEID1 Register DEVICEID_REGY uruuusunnennennnannnnnannnnnnnnnnnn nn nun nun 121 5 10 RapidlO DEVICEID2 Register DEVICEID REG eee eee eee eee eee eee nun nen nn nun nun nen 122 5 11 Packet Forwarding Register n for 16 Bit Device IDs PE 1IGbp CNTLm 44H nn Rn nn nn 123 5 12 Packet Forwarding Register n for 8 Bit Device IDs PE op CNTlm HH n nn nn nennen 124 5 13 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL eeeeeeee 125 5 14 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL seeeeeeee 128 5 15 SERDES Macro Configuration Register n SERDES_CFGn_CNTL eeeeeeeeeeeee eee nun nn 130 5 16 DOORBELLn Interrupt Condition Status Register DOORBELLnN_ICSR zz uuunneunnan nn nennen 182 5 17 DOORBELLn Interrupt Condition Clear Register DOORBELLnN _ICOR urnannennennnannen nennen 133 5 18 RX CPPI Interrupt Status Register RX_CPPI_ICSR eceeeeeee sees eee ee nun nun ann nun nun ann nen 134 5 19 RX CPPI Interrupt Clear Register DX CPP CHL 135 5 20 TX CPPI Interrupt
20. ICC10 ICC9 ICC8 Reserved ICC2 ICC1 ICCO R 0 W 0 WO WO WO HO WO WO WO LEGEND R Read only W Write only n Value after reset Table 37 Interrupt Conditions Shown in ERR_RST_EVNT_ICSR and Cleared With ERR_RST_EVNT_ICCR Bit Interrupt Condition 31 17 Reserved 16 Device reset interrupt from any port 15 12 Reserved 11 Port 3 error TMS320TCI6482 Only 10 Port 2 error TMS320TCI6482 Only 9 Port 1 error 8 Port 0 error 7 3 Reserved 2 Logical layer error management event capture 1 Port write in request received on any port 0 Multi cast event control symbol interrupt received on any port SPRUE13A September 2006 Serial RapidlO SRIO 91 Submit Documentation Feedback Interrupt Conditions da TEXAS INSTRUMENTS www ti com The interrupt status bits found in the ERR_RST_EVNT 0x0270 can be cleared by writing to the ICCR register 0x0278 in the same manner as other interrupts However in order for new event detection and interrupt generation to occur for these special interrupts additional register bits must be cleared The following table notes the additional interrupt source register bits that need to be cleared and the appropriated sequence These are all the bits that can cause the ERR_RST_EVNT status bits to be set Table 38 Interrupt Clearing Sequence for Special Event Interrupts Interrupt Function 1st Step 2nd Step 3rd Step Multicast Event Control Symbol Write 1 to clear Write 1 to clear rece
21. ISD1 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 1 bit 1 of DOORBELLO_ICSR e Doorbell 1 bit 1 bit 1 of DOORBELL1_ICSR e Doorbell 2 bit 1 bit 1 of DOORBELL2_ICSR e Doorbell 3 bit 1 bit 1 of DOORBELL3_ICSR ISDO No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 0 bit O of DOORBELLO_ICSR e Doorbell 1 bit O bit O of DOORBELL1_ICSR e Doorbell 2 bit 0 bit O of DOORBELL2_ICSR e Doorbell 3 bit 0 bit O of DOORBELL3_ICSR SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 153 SRIO Registers da TEXAS INSTRUMENTS www ti com 5 32 INTDSTn Interrupt Rate Control Register INTDSTn_RATE_CNTL There are eight interrupt rate control registers one for each interrupt destination see Table 85 Figure 93 and Table 86 provide a general description for an interrupt rate control register These registers are used to set the rate at which an interrupt can be generated for each interrupt destination A write to one of the registers reloads a counter and immediately starts the counter decrementing When the counter value reaches 0 after counting down or after a CPU write of 0 the interrupt logic generates a single interrupt pulse if any bits in the corresponding ICSR are set or become set after the zero count is reached For additional
22. www ti com Table 18 RX Buffer Descriptor Field Descriptions continued Field Description ownership Ownership Indicates ownership of the message and is valid only on sop This bit is set by the DSP core and cleared by the port when the message has been transmitted The DSP core uses this bit to reclaim buffers 0 The message is owned by the DSP core 1 The message is owned by the port eoq End Of Queue Set by the port to indicate that the RX queue empty condition exists This bit is valid only on eop The port determines the end of queue condition by a zero next_descriptor_pointer 0 The RX queue has more buffers available for reception 1 The Descriptor buffer is the last buffer in the last message in the queue teardown_complete Teardown Complete Set by the port to indicate that the host commanded teardown process is complete and the channel buffers may be reclaimed by the host 0 The port has not completed the teardown process 1 The port has completed the commanded teardown process message_length Message Length Initially written by the DSP core to specify the maximum number of double words the buffer can receive Updated by the peripheral after receiving a message to indicate the actual number of double words in the entire message Message payloads are limited to a maximum size of 512 double words 4096 bytes 000000000b 512 double words 000000001b 1 double word 00000001 0b 2 doub
23. 0003h Switch 196 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 66 Port Link Time Out Control CSR SP_LT_CTL The port link time out control CSR SP_LT_CTL is shown in Figure 129 and described in Table 137 Figure 129 Port Link Time Out Control CSR SP_LT_CTL Address Offset 1120h 31 TIMEOUT_VALUE R W FFFFFFh 8 7 0 TIMEOUT_VALUE Reserved R W FFFFFFh R 00h LEGEND R W Read Write R Read only n Value after reset Table 137 Port Link Timeout Control CSR SP_LT_CTL Field Descriptions Bit Field Value Description 31 8 TIMEOUT_VALUE Timeout value for all ports on the device This timeout is for link events such as sending a packet to receiving the corresponding ACK Max value represents 3 6 seconds Timeout duration 205 ns Timeout Value where Timeout value is the decimal representation of this register value FFFFFFh 3 45 OFFFFFh 215 ms OOFFFFh 13 4 ms OOOFFFh 839 5 us 0000FFh 52 3 us 00000Fh 3 1 us 000001h 205 ns for simulation only 000000h Timer disabled 7 0 Reserved 00h These read only bits return Os when read SPRUE13A September 2006 Serial RapidlO SRIO 197 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 67 Port Response Time Out Control CSR SP_RT_CTL The port response time out control CSR SP_RT_CTL is shown in Figure 130 and des
24. Assert the PEREN bit to enable logical layer data flow SRIO_REGS gt PCR 0x00000004 peren 2 3 14 Bootload Capability 2 3 14 1 Configuration and Operation Figure 41 illustrates the system components involved in bootload operation It is assumed that an external device will initiate the bootload data transfer and master the DMA interface Upon reset the following sequence of events must occur 1 DSP is placed in SRIO boot mode by HW mode pins 2 Host takes DSP out of reset POR or RST The peripheral s state machines and registers are reset 3 Internal boot strap ROM configures device registers including SERDES and DMA DSP executes internal ROM code to initialize SRIO e Choice of 4 pin selectable configurations e Optionally I2C boot can be used to configure SRIO SPRUE13A September 2006 Serial RapidlO SRIO 79 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description 4 DSP executes idle instruction RapidlO ports send Idle control symbols to train PHYs Host enabled to explore system with RapidlO Maintenance packets Host identifies enumerates and initializes the RapidlO device Host controller configures DSP peripherals through maintenance packets e SRIO Device IDs are set for DSPs either by pin strapping or by host manipulation 9 Boot Code sent from host controller to DSP L2 memory base address via NWRITE 10 DSP CPU is awakened by an interrupt such as a RapidIO DO
25. BLK6_EN_STAT 006Ch Logical block 6 SRIO port 1 BLK7_EN_STAT 0074h Logical block 7 SRIO port 2 BLK8_EN_STAT 007Ch Logical block 8 SRIO port 3 Figure 69 Block n Enable Status Register BLKn_EN 31 1 g Reserved EN_STAT HO R W 1 LEGEND R W Read Write R Read only n Value after reset Table 49 Block n Enable Status Register BLKn_EN_STAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 These read only bits return Os when read 0 EN_STAT Block n enable status 0 Logical block n is reset with its clock off Logical block nis enabled with its clock running 120 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 9 RapidlO DEVICEID1 Register DEVICEID_REG1 The RapidlO DEVICEID1 register DEVICEID_REG1 is shown in Figure 70 and described in Table 50 Figure 70 RapidlO DEVICEID1 Register DEVICEID_REG1 Offset 0080h 31 24 23 16 Reserved 8BNODEID R 00h R W FFh 15 0 16BNODEID R W FFFFh LEGEND R W Read Write R Read only n Value after reset Table 50 RapidlO DEVICEID1 Register DEVICEID_REG1 Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 8BNODEID 00h FFh This value is equal to the value of the RapidlO Base Device ID CSR The CPU must read the CSR value and set this register so that outgoing packets
26. For output swing settings above 750mV this reduced common mode can cause distortion of the waveform Under these conditions this bit should be set high to offset some of the common mode reduction 0 Normal common mode Common mode not adjusted 1 Raised common mode Common mode raised by 5 of difference between RIOTXn and RIOTXn 7 INVPAIR Invert polarity Inverts the polarity of RIOTXn and RIOTXn 0 Normal polarity RIOTXn is considered to be positive data and RIOTXn negative 1 Inverted polarity RIOTXn is considered to be negative data and RIOTXn positive 6 5 RATE Operating rate Selects full half or quarter rate operation 00b Full rate Two data samples taken per PLL output clock cycle 01b Half rate One data sample taken per PLL output clock cycle 10b Quarter rate One data sample taken every two PLL output clock cycles 11b Reserved 4 2 BUSWIDTH 000b Bus width Always write 000b to this field to indicate a 10 bit wide parallel bus to the clock All other values are reserved See Section 2 3 2 1 for an explanation of the bus 1 Reserved 0 Always write 0 to this reserved bit 0 ENTX Enable transmitter 0 Disable this transmitter 1 Enable this transmitter 34 Serial RapidlO SRIO Table 12 DE Bits of SERDES_CFGTXn_CNTL Amplitude Reduction DE Bits dB 0000b 0 0 0001b 4 76 0 42 0010b 9 52 0 87 0011b 14 28 1 34 0100b 19 04 1 83 0101b 23 8 2 36 0110b 28 56 2 92 0111b 33 32 3 52 1000b 38 08 4
27. Highest precision frequency offset matching but poorest response to changes in frequency offset and longest lock time Suitable for use in systems with fixed frequency offset 010b Second order Medium precision frequency offset matching frequency offset change response and lock time 011b Second order Best response to changes in frequency offset and fastest lock time but lowest precision frequency offset matching Suitable for use in systems with spread spectrum clocking 100b First order with fast lock Phase offset tracking up to 1953 ppm in the presence of 10101010 training pattern and 448 ppm otherwise 101b Second order with fast lock As per setting 001 but with improved response to changes in frequency offset when not close to lock 110b Second order with fast lock As per setting 010 but with improved response to changes in frequency offset when not close to lock 111b Second order with fast lock As per setting 011 but with improved response to changes in frequency offset when not close to lock SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 125 SRIO Registers 126 da TEXAS INSTRUMENTS www ti com Table 57 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions continued Bit Field Value Description 15 14 LOS Loss of signal Enables loss of signal dete
28. LSU1_REGO 0400h LSU1 LSU2_REGO 0420h LSU2 LSU3_REGO 0440h LSU3 LSU4_REGO 0460h LSU4 Figure 94 LSUn Control Register 0 LSUn_REGO 31 0 ADDRESS_MSB R W 00h LEGEND R W Read Write n Value after reset Table 88 LSUn Control Register 0 LSUn_REGO Field Descriptions Bit Field Value Description 31 0 ADDRESS_MSB 00000000h 32 bit most significant bits of an extended address specified through LSUn to FFFFFFFFh SPRUE13A September 2006 Serial RapidlO SRIO 155 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 34 LSUn Control Register 1 LSUn_REG1 There are four of these registers one for each LSU see This register s content is shown in Figure 95 and described in Table 90 For additional programming see Section 2 3 3 Table 89 LSUn_REG1 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG1 0404h LSU1 LSU2_REG1 0424h LSU2 LSU3_REG1 0444h LSU3 LSU4_REG1 0464h LSU4 Figure 95 LSUn Control Register 1 LSUn_REG1 31 0 ADDRESS_LSB CONFIG_OFFSET R W 00000000h LEGEND R W Read Write n Value after reset Table 90 LSUn Control Register 1 LSUn_REG1 Field Descriptions Bit Field Value Description 31 0 ADDRESS_LSB CONFIG_OFFSET 00000000h For packet types 2 5 and 6 to The 32 bit destination address or the 32 least significant bits of FFFFFFFFh an extended destination address This value is
29. PROMISCUOUS Promiscuous access Mapper n checks the incoming sourcelD access is restricted to one sender When determining which transactions to service the mapper checks the sourcelD in addition to the mailbox and letter qualifications Mapper n ignores the incoming sourcelD access is available to any sender When determining which transactions to service the mapper checks only the mailbox and letter qualifications SEGMENT_MAPPING Segment mapping Single segment messaging Up to 64 mailboxes are available All six bits of the MAILBOX and MAILBOX_MASK fields of RXU_MAP_Ln are valid Multi segment messaging Up to 4 mailboxes are available Only the 2 LSBs of the MAILBOX and MAILBOX_MASK fields of RXU_MAP_Ln are valid 180 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 51 Flow Control Table Entry Register n FLOW_CNTLn There are sixteen of these registers see Table 121 FLOW_CNTLn is shown in Figure 114 and described in Table 122 For additional programming information see Section 2 3 8 Table 121 FLOW_CNTLn Registers Register Address Offset FLOW_CNTLO 0900h FLOW_CNTL1 0904h FLOW_CNTL2 0908h FLOW_CNTL3 090Ch FLOW_CNTL4 0910h FLOW_CNTL5 0914h FLOW_CNTL6 0918h FLOW_CNTL7 091Ch FLOW_CNTL8 0920h FLOW_CNTL9 0924h FLOW_CNTL10 0928h FLOW_CNTL11 092Ch FLOW_CNTL12 0930h FLOW_CNTL13 0934h FLOW_CNTL14
30. PW_CAPT1 00000000h Word 1 bits 32 to 63 of the Port Write payload to FFFFFFFFh PW_CAPT2 00000000h Word 2 bits 64 to 95 of the Port Write payload to FFFFFFFFh PW_CAPT3 00000000h Word 3 bits 96 to 127 of the Port Write payload to FFFFFFFFh 234 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 95 Port Reset Option CSR n SPn_RST_OPT Each of the four ports is supported by a register of this type see Table 180 SPn_RST_OPT is shown in Figure 158 and described in Table 181 Table 180 SPn_RST_OPT Registers and the Associated Ports Register Address Offset Associated Port SPO_RST_OPT 14000h Port 0 SP1_RST_OPT 14100h Port 1 SP2_RST_OPT 14200h Port 2 SP3_RST_OPT 14300h Port 3 Figure 158 Port Reset Option CSR n SPn_RST_OPT 31 gt Reserved R 0000h 15 87 0 Reserved PORT_ID R 00h R imp LEGEND R Read only n Value after reset imp Value after reset is implementation defined Table 181 Port Reset Option CSR n SPn_RST_OPT Field Descriptions Bit Field Value Description 31 8 Reserved 0 These read only bits return Os when read 7 0 PORT ID Port ID defines unique number for port in Switch The Port ID is used for port write request The ID coincides with ISF port of connection Example 00_0000_01 _ port 1 Impl IPO port 1 00_0001_11 port 7 Impl IP1 port 3
31. R W 0000h Mailbox to Queue Mapping Register H n RXU_MAP_H n 31 Reserved R 0 10 9 87 65 2 1 0 SEGMENT Reserved TT Reserved QUEUE_ID PROMISCUOUS MAPPING R 0 R W 01 R 00 R W 0000 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset 46 The packet manager maintains the RX DMA state of free and used data buffers within the memory space It directs the data to specific addresses within the memory and maintains and updates the buffer descriptor queues There is a single buffer descriptor per RapidlO message For example single segment messages have one buffer descriptor as do multi segment messages with up to 4K byte payloads There can be multiple RX buffer descriptor queues per core It is suggested that one queue be dedicated to single segment messages and additional queues be dedicated to multi segment messages Each multi segment message queue can support only one incoming message at a time Depending on the application it may be necessary to support multiple simultaneous segmentation and reassembly SAR operations per core In this case a buffer descriptor queue is allocated for each desired simultaneous message The peripheral supports a total of 16 assignable RX queues and their associated RX DMA state registers Each of the queues can be assigned to single or multi segment messages Table 16 and Table 17 describe the RX DMA State Registers Table 16 RX DMA State Head Descriptor Pointer HDP Address Offset
32. Reserved HO 7 4 3 2 1 0 STOP_PORT_ DROP_ PORT Reserved FLD_ENC_ PACKET_ LOCKOUT PORT_TYPE ENABLE ENABLE HO R W 0 R W 0 R W 0 R 1 LEGEND R W Read Write R Read only n Value after reset Table 149 Port Control CSR n SPn_CTL Field Descriptions Bit Field Value Description 31 30 PORT_WIDTH Port width This read only field indicates the hardware width of the port 00b Single lane port valid for all ports 01b Four lane port valid for port 0 only 1xb Reserved 29 27 INITIALIZED_PORT_WIDTH Initialized port width This read only field indicates the width of the ports after initialization 000b Single lane port lane 0 001b Single lane port lane 2 See RapidlO Serial Spec 1 2 Chapter 4 4 10 010b Four lane port 011b 111b Reserved 206 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 149 Port Control CSR n SPn_CTL Field Descriptions continued Bit Field Value Description 26 24 PORT_WIDTH_OVERRIDE 000b 001b 010b 011b 100b 111b Port width override This read only field is available as a software means to override the hardware width No override Reserved Force single lane lane 0 Force single lane lane 2 Reserved 23 PORT_DISABLE Port disable Port receivers drivers are enabled Port receivers drivers are disabled and are unable to receive transmit any packets or control
33. Reset and Special Event Interrupt Condition Status and Clear Registers 0csseeeeeeeeeeeeeees 91 54 Doorbell 0 Interrupt Condition Routing Registers uuzuusssnennnannannnnnnannunnnnnnunnnnnnunnnunnnn nun nun nun nen 94 55 RX CPPI Interrupt Condition Routing Heolsters nen 94 56 TX CPPI Interrupt Condition Routing Registers nen 95 57 LSU Interrupt Condition Routing Registers AN 96 58 Error Reset and Special Event Interrupt Condition Routing Registers urzussunnennnnnnannnnnnnnnan nun ann nen 97 59 Interrupt Status Decode Register INTDSTn_DECODE eee e nun nennen nn nenn nun nun nenn nun nennen 98 60 Interrupt Sources Assigned to ISDR Bits uuz2ususnennnnnnnnnannnnnnunnnnnnennnn nun nennen nnunnennannnnn nun nun nen 98 61 Example Diagram of Interrupt Status Decode Register Mapping nennen nnunnnnnannnnnnnnnnnn nen 99 62 INTDSTn_RATE_CNTL Interrupt Rate Control Register ecceeeeeeeee nen nnan nun nun nun nun nun nnnnunn nun nenn 100 63 Peripheral ID Register PID Address Offset 0000h uusu usn ununnnnnnnnnannnnnnnunnnn nun nn un nun nun nannnn 111 64 Peripheral Control Register PCR Address Offset OOOA nun une nn 112 65 Peripheral Settings Control Register PER_SET_CNTL Address Offset O020b 113 66 Peripheral Global Enable Register GBL_EN Address Offset 0030h nun nun nennen 116 67 Peripheral Global Enable Status Register GBL_EN_STAT Address 0034h nusununennnnnnnnnnnn nennen 117 68 Bloc
34. complete explanation of the programming of these registers Table 56 SERDES_CFGRXn_CNTL Registers and the Associated Ports Register Address Offset Associated Port SERDES_CFGRXO_CNTL 0100h Port 0 SERDES_CFGRX1_CNTL 0104h Port 1 SERDES_CFGRX2_CNTL 0108h Port 2 TMS320TC16482 Only SERDES_CFGRX3_CNTL 010Ch Port 3 TMS320TC16482 Only Figure 74 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL 31 26 25 24 23 22 19 18 16 Reserved Reserved write Os EQ CDR R 0 R W 0 R 0 R W 0 R W 0 15 14 13 12 141 10 8 7 6 54 1 0 LOS ALIGN TERM INVPAIR RATE BUSWIDTH ENRX write 001b write 0 RIW 0 R W 0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 57 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions Bit Field Value Description 31 26 Reserved 000000b These read only bits return Os when read 25 24 Reserved 00b Always write Os to these reserved bits 23 Reserved 0 This read only bit returns 0 when read 22 19 EQ 0000b 1111b Equalizer Enables and configures the adaptive equalizer to compensate for loss in the transmission media For the selectable values see Table 58 18 16 CDR Clock data recovery Configures the clock data recovery algorithm 000b First order Phase offset tracking up to 488 ppm 001b Second order
35. eceeeeeee eee e eee e erent nun nun ann nun nun nn nn 161 101 LSUn_FLOW_MASKS Registers and the Associated LGUe eee eeeeee nn nenn nn nn nennen nun 162 102 LSUn Congestion Control Flow Mask Register LSUn_FLOW_MASKS Field Descriptions 162 103 CSUA FLOW MASK Fields 2 rnanca aa aE aa 162 104 OUEHEn TXDMA HDP ReGistels sg csteccncitneened oe aa aan eda ai 164 105 Queue n Transmit DMA Head Descriptor Pointer Register QUEUEn_TXDMA_HDP Field Descriptions 164 106 QUEWENR TXDMA CP ReOiSterS age eageeuENge eggg geg ENN ENES Ee ae nennen 165 107 Queue Transmit DMA Completion Pointer Registers QUEUEn_TXDMA_CP Field Descriptions 165 108 QUEUER RXDMA HDBP Registers n n ans ENEE EN ANEREN SEENEN ANE AANEREN AN 166 109 Queue n Receive DMA Head Descriptor Pointer Register QUEUEn_RXDMA_HDP Field Descriptions 166 110 QUEWER RXDMA_CP Registers una ee 167 111 Queue n Receive DMA Completion Pointer Register QUEUEn_RXDMA_CP Field Descriptions 167 112 Transmit Queue Teardown Register TX_QUEUE_TEAR_DOWN Field Descriptions seeeeeeeeeeee 168 113 TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues eee teen nun nenn nn nen 169 114 TX Queue n FLOW_MASK Field Descrtpottons cece ee eee eee nun eee eee e eee nun nun nun nnnn nun nun en nun 170 115 Receive Queue Teardown Register RX_QUEUE_TEAR_DOWN Field Descriptions 000e 172 116 Receive CPPI Control Register RX_CPPI_CNTL
36. endpoint device Save and lock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs 26 Reserved 0 Always write 0 to this reserved bit 25 MSG_REQ_TIMEOUT_ENABLE Message request time out error reporting enable Disable reporting of a message request time out error Enable reporting of a message request time out error endpoint device only Save and lock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs for the last message segment request packet received 212 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 152 Logical Transport Layer Error Enable CSR ERR_EN Field Descriptions continued Bit Field Value Description 24 PKT_RESP_TIMEOUT_ENABLE Packet response time out error reporting enable 0 Disable reporting of a packet response time out error 1 Enable reporting of a packet response time out error endpoint device only Save and lock original request address in Logical Transport Layer Address Capture CSRs Save and lock original request Destination ID in Logical Transport Layer Device ID Capture CSR 23 UNSOLICITED_RESP_ENABLE Unsolicited response error reporting enable 0 Disable reporting of an unsolicited response error 1 Enable reporting of an unsolicited response error switch or endpoint device Save and l
37. fabric devices Control symbols are used to manage the flow of transactions in the SRIO physical interconnect Control symbols are used for packet acknowledgment flow control information and maintenance functions Figure 5 shows how a packet progresses through the system Figure 5 Operation Sequence Initiator Operation Operation Issued By Request Acknowledge Completed for Master Packet Issued Symbol Master LL OO Acknowledge Response Symbol S Packet 7 Forwarded Acknowledge Request Packet Symbol Forwarded Response Packet Acknowledge Issued Symbol Target Completes Operation 2 1 2 2 Example Packet Streaming Write An example packet is shown as two data streams in Figure 6 The first is for payload sizes of 80 bytes or less while the second applies to payload sizes of 80 to 256 bytes SRIO packets must have a length that is an even integer of 32 bits If the combination of physical logical and transport layers has a length that is an integer of 16 bits a 16 bit pad of value 0000h is added to the end of the packet after the CRC not shown Bit fields that are defined as reserved are assigned to logic Os when generated and ignored when received All request and response packet formats are described in the RapidlO Input Output Logical Specification and Mlessage Passing Logical Specification SPRUE13A September 2006 Serial RapidlO SRIO 23 Submit Documentation Feedback d TEXAS INSTRUMENTS
38. gt 4 6 4 7 The following are suggestions for minimizing the number of register reads to identifying the interrupt source e Dedicate each doorbell ICSR to one core The CPU can then determine the interrupt source from a single read of the decode register e Assign the RX and TX CPPI queues orthogonally to different cores The CPU can then determine the interrupt source from a single read of the decode registers The only exceptions to this are bits 31 and 30 which are also logically ORed with LSU and port interrupt sources Interrupt Generation Interrupts are triggered on a 0 to 1 logic signal transition Regardless of the interrupt sources the physical interrupts are set only when the total number of set ICSR bits transitions from none to one or more The peripheral is responsible for setting the correct bit within the ICSR The ICRR register maps the pending interrupt request to the appropriate physical interrupt line The corresponding CPU is interrupted and reads the ISDR and ICSR registers to determine the interrupt source and appropriate action Interrupt generation is governed by the interrupt pacing discussed Section 4 7 Interrupt Pacing The rate at which an interrupt can be generated is controllable for each physical interrupt destination Rate control is implemented with a programmable down counter The load value of the counter is written by the CPU into the appropriate interrupt rate control register see
39. port control symbol transmit registers 240 port error and status CSR 203 port error capture CSR 1 224 port error capture CSR 2 225 port error capture CSR 3 226 port error capture CSR 4 227 port error detect CSR 219 port error rate CSR 228 port error rate enable CSR 221 port error rate threshold CSR 229 port general control CSR 199 port ID field for port write request at portn 235 port IP discovery timer for 4x mode register 230 port IP mode CSR 231 port IP prescaler register 233 port link maintenance request CSR 200 port link maintenance response CSR 201 port link time out control CSR 197 port local ackID status CSR 202 250 Index port multicast event control symbol request registers 239 port n error capture control information field 224 packet header bytes 0 to 3 field 224 packet header bytes 4 to 7 field 225 packet header bytes 8 to 11 field 226 packet header bytes 12 to 15 field 227 type of error field 223 type of information field 223 valid information field 223 port reset option CSR 235 port response time out control CSR 198 ports enable bits 119 enable status bits 120 in SRIO component block diagram 26 port silence timer registers 238 port write error reporting disable field 231 port write generation support for destination device 189 port write generation support for source device 188 port write in capture CSR 234 port write in capture payload 234 port write in interrupt enable field 232 port write in interrupt status fi
40. programming see Section 4 4 1 1 TX CPPI Interrupt Condition Routing Register TX_CPPI_ICRR Address Offset 02D0h 31 Figure 89 TX CPPI Interrupt Condition Routing Registers 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 TX CPPI Interrupt Condition Routing Register 2 TX_CPPI_ICRR2 Address Offset 02D4h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset Table 80 TX CPPI Interrupt Condition Routing Register Field Descriptions Field Value Description ICRx Interrupt condition routing Routes the interrupt request from TX buffer descriptor queue x to one of x 0 to 15 eight interrupt destinations INTDSTO INTDST7 0000b INTDSTO 0001b INTDST1 0010b INTDST2 0011b INTDST3 0100b INTDST4 0101b INTDST5 0110b INTDST6 0111b INTDST7 1xxxb Reserved 146 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 5 29 LSU Interrupt Condition Routing Registers LSU_ICRRO LSU_ICRR3 SRIO Registers Figure 90 shows the ICRRs for the LSU interrupt requests and Table 81 shows the general description for an ICRx field in any of the four r
41. size physical address y P Transport specification gt Common Information to transport packet from end t ransport to end in the system i e routing address spec Physical specification Future Information necessary to move packet 8 16 1x 4x hvsical between two physical devices i e electrical LP LVDS LP serial P SS interface flow control P Inter Compliance operability checklist specification SPRUE13A September 2006 Serial RapidlO SRIO 17 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Overview 1 1 2 1 1 3 RapidlO Interconnect Architecture The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation Figure 2 illustrates the interconnection system Figure 2 RapidlO Interconnect Architecture Host Subsystem nz Host Host Processor Processor UO Control Subsystem Processor InfiniBand HCA IO Processor Memory To System Area t Network InfiniBand RapidlO RapidlO ee ee EI kenn ee emm emm emm ee ee m RapidlO 3 RapidlO RapidlO RER Sep Switch Switch Backplane RapidiO a Im e e e e e e a P e e e rw e RapidlO i RapidlO to d es SC Il Il L ll Jee Il w Il I Il Il TDM GMIl Utopia DSP Farm Communications Subsystem rc Ke D OO lt v Q PCI Subsystem 1 InfiniBand is a trademark of
42. transmit flow control enable field for portn 236 transmit queue teardown register 168 transmit receive lockout field for portn 207 Index 253 SRIO Registers transmitter enabling for SERDES macro introduction 33 transmitter enable bit 129 transport error handling and logging 83 transport layer content in SRIO data stream 22 definition 16 in Load Store module data flow diagram 39 transport type field for message reception 179 TRA See transport layer 23 TT field of FLOW_CNTLn 181 tt field of RX buffer descriptor 47 TT field of RXU_MAP_Hn 178 tt field of TX buffer descriptor 52 TTYPE field of CTRL_CAPT 217 Ttypes of SRIO packets 25 TX_CP field of QUEUEn_TXDMA_CP 165 TX_CPPI_LFLOW_MASKSI O 7 169 TX_CPPI_ICCR 137 TX_CPPI_ICRR 146 TX_CPPI_ICRR2 146 TX_CPPILICSR 136 TX_FIFO_BYPASS field of SP_IP_MODE 231 TX_FLW field of SPn_CTL_INDEP 236 TX_HDP field of QUEUEn_TXDMA_HDP 164 TX_PRIn_WM fields of PER_SET_CNTL 113 TX_QUEUE_CNTL 0 3 174 TX_QUEUE_TEAR_DOWN 168 TX buffer descriptor fields 52 TX buffer descriptor link list figure 62 TX buffer descriptor queue teardown 59 TX buffers credit and packet re ordering 75 TX shared buffer in direct O TX WRITE transaction 40 in SRIO component block diagram 26 TXU enable bit 119 enable status bits 117 120 handling of unavailable outbound credit 76 in SRIO component block diagram 26 type field for portn 208 TYPE field of PID 111 type of error field for port n error capture 223 type of infor
43. write 0 R W 0 R W 0 R 0 R W 0 R W 0 R W 0 R W 0 RIW 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 9 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions Bit Field Value Description 31 26 Reserved 000000b These read only bits return Os when read SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 31 SRIO Functional Description 32 da TEXAS INSTRUMENTS www ti com Table 9 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions continued Bit Field Value Description 25 24 Reserved 00b Always write Os to these reserved bits 23 Reserved 0 This read only bit returns 0 when read 22 19 EQ 0000b 1111b Equalizer Enables and configures the adaptive equalizer to compensate for loss in the transmission media For the selectable values see Table 10 18 16 CDR Clock data recovery Configures the clock data recovery algorithm 000b First order Phase offset tracking up to 488 ppm 001b Second order Highest precision frequency offset matching but poorest response to changes in frequency offset and longest lock time Suitable for use in systems with fixed frequency offset 010b Second order Medium precision frequency offset matching frequency offset change response and lock time 011b Second order Best
44. 0 R 0 15 8 Reserved R 0 7 6 5 4 3 2 1 0 NON UNSOLICITED PROTOCOL DELINEATION LINK Reserved OUTSTANDING_ Reserved ACK_CNTL_ ACKID_EN ERROR_EN ERROR_EN SYM EN TIMEOUT_EN R 0 R W 0 R W 0 R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 161 Port Error Rate Enable CSR n SPn_RATE_EN Field Descriptions Bit Field Value Description 31 EN_IMP_SPECIFIC Rate counting enable for implementation specific errors 0 Disable error rate counting of implementation specific errors 1 Enable error rate counting of implementation specific errors 30 23 Reserved 0 These read only bits return Os when read 22 CORRUPT_CNTL_SYM_ENABLE Rate counting enable for corrupt control symbols 0 Disable error rate counting of a corrupt control symbol 1 Enable error rate counting of a corrupt control symbol 21 CNTL_SYM_UNEXPECTED_ACKID_EN Rate counting enable for control symbols with unexpected ackIDs 0 Disable error rate counting of an acknowledge control symbol with an unexpected acklD 1 Enable error rate counting of an acknowledge control symbol with an unexpected acklD 20 RCVED_PKT_NOT_ACCPT_EN Rate counting enable for packet not accepted control symbols 0 Disable error rate counting of received packet not accepted control symbols 1 Enable error rate counting of received packet not accepted control symbols SPRUE13A September 2006 Serial RapidlO SRIO 221 Submit Documentat
45. 0 These read only bits return Os when read 7 FLOW_CONTROL_SUPPORT PE supports congestion flow control mechanism 0 PE does not support flow control 1 PE supports flow control 6 RETRANSMIT_SUPPRESS PE supports suppression of error recovery on packet CRC errors 0 PE does not support suppression 1 PE supports suppression 5 CRF_SUPPORT This bit indicates PE support for the Critical Request Flow CRF Function 0 PE does not support CRF Function 1 PE supports CRF Function 4 LARGE_SUPPORT Support of common transport large systems 0 PE does not support common transport large systems 1 PE supports common transport large systems 3 EXTENDED_FEATURES a extended features list the extended features pointer is valid 186 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 127 Processing Element Features CAR PE_FEAT Field Descriptions continued Bit Field Value Description 2 0 EXTENDED_ADDRESSING_SUPPORT Indicates the number address bits supported by the PE both as a source and target of an operation All PEs shall at minimum support 34 bit addresses Encodings other than below are reserved 001b PE supports 34 bit addresses 011b PE supports 50 and 34 bit addresses 101b PE supports 66 and 34 bit addresses 111b PE supports 66 50 and 34 bit addresses Other Reserved SPRUE13A September 2006 Serial RapidlO SRIO 187 Submit Documentat
46. 00000 R 00000h 43 1 0 IMP_SPECIFIC Reserved CAPTURE_ VALID_INFO R 00000h R 00 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 163 Port n Attributes Error Capture CSR 0 SPn_ERR_ATTR_CAPT_DBGO Field Descriptions Bit Field Value Description 31 30 INFO_TYPE Type of information logged 00b Packet 01b Control symbol only error capture register 0 is valid 10b Implementation specific capture register contents are implementation specific 11b Reserved 29 Reserved 0 This read only bit returns 0 when read 28 24 ERROR_TYPE 00000b 11111b Encoded value of captured error bit in the Port n Error Detect Register 23 4 IMP_SPECIFIC 00000h FFFFFh Implementation Dependent Error Information 3 1 Reserved 0 These read only bits return Os when read 0 CAPTURE_VALID_INFO Valid information captured 0 The packet control symbol capture registers do not contain valid information 1 The packet control symbol capture registers contain valid information For control symbols only capture register 0 contains meaningful information A software write of 0 clears this bit and subsequently unlocks all the capture registers of the port SPRUE13A September 2006 Serial RapidlO SRIO 223 Submit Documentation Feedback SRIO Registers 5 85 Port n Error Capture CSR 1 SPn_ERR_CAPT_DBG1 Each of the four ports is supported by a register of this type see Table 164 SPn_ERR_CAPT_DBG1 is shown in Figur
47. 012Ch Not Used Program as 0x00000000 Figure 76 SERDES Macro Configuration Register n SERDES_CFGn_CNTL 31 16 Reserved R 0 15 10 9 87 65 1 0 Reserved LB Reserved MPY ENPLL HO R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 64 SERDES Macro Configuration Register n SERDES CFGn_CNTL Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 8 LB Loop bandwidth Specify loop bandwidth settings Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impairing system performance Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock via the LB field 00b Frequency dependent bandwidth The PLL bandwidth is set to a twelfth of the frequency of RIOCLK RIOCLK This setting is suitable for most systems that input the reference clock via a low jitter input cell and is required for standards compliance 01b Reserved 10b Low bandwidth The PLL bandwidth is set to a twentieth of the frequency of RIOCLK RIOCLK or 3MHz whichever is larger In systems where the reference clock is directly input via a low jitter input cell but is of lower quality this setting may offer better performance It will reduce the amount of reference clock jitter transferred through the PLL However it also increases the susceptibility to loop noise generated
48. 1 R 1 R 1 R 1 R 1 R 1 LEGEND R Read only n Value after reset SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 71 da TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 27 Global Enable and Global Enable Status Field Descriptions Register Bit Field Value Description GBL_EN 31 1 Reserved 0 These read only bits return Os when read GBL_EN 0 EN Global enable This bit controls reset to all clock domains within the peripheral 0 The peripheral is to be disabled held in reset with clocks disabled 1 The peripheral is to be enabled GBL_EN_STAT 31 10 Reserved 0 These read only bits return Os when read GBL_EN_STAT 9 BLK8_EN_STAT Block 8 enable status Logical block 8 is SRIO port 3 0 Logical block 8 is in reset with its clock off 1 Logical block 8 is enabled with its clock running GBL_EN_STAT 8 BLK7_EN_STAT Block 7 enable status Logical block 7 is SRIO port 2 0 Logical block 7 is in reset with its clock off 1 Logical block 7 is enabled with its clock running GBL_EN_STAT 7 BLK6_EN_STAT Block 6 enable status Logical block 6 is SRIO port 1 0 Logical block 6 is in reset with its clock off 1 Logical block 6 is enabled with its clock running GBL_EN_STAT 6 BLK5_EN_STAT Block 5 enable status Logical block 5 is SRIO port 0 0 Logical block 5 is in reset with its clock off 1 Logical block 5 is enabled with its clock running GBL_EN_STAT 5 BLK4_
49. 125 amplitude reduction de emphasis field 128 ASBLY_ID 184 ASBLY_INFO 185 assembly identity CAR 184 assembly information CAR 185 ASSY_IDENTITY field of ASBLY_ID 184 ASSY_VENDORIDENTITY field of ASBLY_ID 184 ASSYREV field of ASBLY_INFO 185 ATOMIC_CLEAR field of DEST_OP 189 ATOMIC_CLEAR field of SRC_OP 188 ATOMIC_DCRMNT field of DEST_OP 189 ATOMIC_DCRMNT field of SRC_OP 188 ATOMIC_INCRMNT field of DEST_OP 189 ATOMIC_INCRMNT field of SRC_OP 188 ATOMIC_SET field of DEST_OP 189 ATOMIC_SET field of SRC_OP 188 ATOMIC_TEST_AND_SWAP field of DEST_OP 189 ATOMIC_TEST_AND_SWAP field of SRC_OP 188 Atomic operations overview 65 packet Ftypes and Ttypes 25 Atomic operations support for destination device 189 Atomic operations support for source device 188 Index 241 SRIO Registers B bad CRC in control symbol at port n rate counting enable field 221 status field 219 bad CRC in packet at port n rate counting enable field 222 status field 220 bandwidth per differential pair based on 1x 4x LP Serial specification 18 BASE_DEVICEID field of BASE_ID 193 BASE_ID 193 base address registers for local configuration space 191 192 base device IDCSR 193 base device ID for host PE 194 Big Endian versus Little Endian 68 binary notational convention 14 BLKO_EN_STAT field of GBL_EN_STAT 117 BLK1_EN_STAT field of GBL_EN_STAT 117 BLK2_EN_STAT field of GBL_EN_STAT 117 BLK3_EN_STAT field of GBL_EN_STAT 117 BLK4_EN_STAT field of GBL_EN_STAT 117 BLK5_EN_ST
50. 16 1001b 42 85 4 86 1010b 47 61 5 61 1011b 52 38 6 44 1100b 57 14 7 35 1101b 61 9 8 38 1110b 66 66 9 54 1111b 71 42 10 87 SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com 2 3 2 4 SRIO Functional Description Table 13 SWING Bits of SERDES_CFGTXn_CNTL SWING Bits Amplitude MV gop 000b 125 001b 250 010b 500 011b 625 100b 750 101b 1000 110b 1125 111b 1250 SERDES Configuration Example full sample rate at 3 125 Gbps SERDES reference clock RIOCLK 125 MHz MPY 12 5 125MHz 3 125 Gbps 5 MPY SRIO_REGS gt SERDES_CFGO_CNTL 0x0000000F SRIO_REGS gt SERDES_CFG1_CNTL 0x00000000 SRIO_REGS gt SERDES_CFG2_CNTL 0x00000000 SRIO_REGS gt SERDES_CFG3_CNTL 0x00000000 SRIO_REGS gt SERDES_CFGI_CNTL not used SRIO_REGS gt SERDES_CFG2_CNTL not used SRIO_REGS gt SERDES_CFG3_CNTL not used four ports enabled SRIO_REGS gt SERDES_CFGRXO_CNTL 0x00081101 SRIO_REGS gt SERDES_CFGRXI1_CNTL 0x00081101 SRIO_REGS gt SERDES_CFGRX2_CNTL 0x00081101 SRIO_REGS gt SERDES_CFGRX3_CNTL 0x00081101 SRIO_REGS gt SERDES_CFGTXO_CNTL 0x00010801 SRIO_REGS gt SERDES_CFGTX1_CNTL 0x00010801 SRIO_REGS gt SERDES_CFGTX2_CNTL 0x00010801 SRIO_REGS gt SERDES_CFGTX3_CNTL 0x00010801 2 3 3 SPRUE13A September 2006 Direct UO Operation The direct I O Load Store module serves as the source of all outgoing dire
51. Address Offset OPO 136 82 TX CPPI Interrupt Condition Clear Register TX_CPPI_ICCR Address Offset 0258h 20eeeeeeeee 137 83 LSU Interrupt Condition Status Register LSU_ICSR Address Offset 0260h 138 84 LSU Interrupt Condition Clear Register LSU_ICCR Address Offset 0268h 4 444 HR HH nenn nennen 141 85 Error Reset and Special Event Interrupt Condition Status Register ERR_RST_EVNT_ICSR Address ELE In RE en en ee Re 142 86 Error Reset and Special Event Interrupt Condition Clear Register ERR_RST_EVNT_ICCR Address eet DE Blees ae ee er a a EB 143 87 Doorbell n Interrupt Condition Routing Registers urruununnennnennannnnnnannannnunnnnnnnnnunnnnnnun nun nennen 144 88 RX CPPI Interrupt Condition Routing Registers cceeeeeee eee cece nun eee nnnnnn nun nun nun nun nun nun nun nenn 145 89 TX CPPI Interrupt Condition Routing Registers ursunnunnennnannnnnnnnnannnnnnnnnnnnnennun nun nun nnnnnnn nenne 146 90 LSU Interrupt Condition Routing Heotsiers nun nun n nenn 147 91 Error Reset and Special Event Interrupt Condition Routing Heoleters nun nennen 149 92 Interrupt Status Decode Register INTDSTn_ DECOD I eect ence eee ee ee eeeee nun nennnn nun nun en nun 150 93 INTDSTn Interrupt Rate Control Register INTDSTn_RATE_CNTL ann 154 94 LSU Control Register UE SU REGO sate 02 200 een aaa geed nein 155 95 LSUA Control Register LSU REGI sssri nn ENEE REENEN EEN NEE semis anne 156 96 LSU C
52. Although a request is generated for each packet transaction so that the DMA can transfer the data to L2 memory an interrupt is only generated after the final packet of the message This interrupt notifies the CPU that data is available in L2 Memory for processing As an endpoint device the peripheral accepts packets based on the destination ID Two options exist for packet acceptance and are mode selectable The first option is to only accept packets whose DestIDs match the local devicelD in 0x0080 This provides a level of security The second option is is system multicast operation When multicast is enabled in SP_IP_MODE offset 12004h bit 5 incoming packets matching the devicelD in the registers shown in are accepted Table 2 Registers Checked for Multicast DevicelD Registers Checked For Multicast DevicelD Device Name Address Offset TMS320TCI6482 Local DevicelD Register 0080h Multicast DevicelD Register 0084h Data flow through the peripheral can be explained using the high level block diagram shown in Figure 4 High speed data enters from the device pins into the RX block of the SERDES macro The RX block is a differential receiver expecting a minimum of 175mV peak to peak differential input voltage Vid Level shifting is performed in the RX block such that the output is single ended CMOS The serial data is then fed to the SERDES clock recovery block The sole purpose of this block is to extract a clock signal from the da
53. Bus width Always write 000b to this field to indicate a 10 bit wide parallel bus to the clock All other values are reserved See Section 2 3 2 1 for an explanation of the bus 1 Reserved 0 Always write 0 to this reserved bit 0 ENRX Enable receiver 0 Disable this receiver 1 Enable this receiver 2 3 2 3 Table 10 EQ Bits CFGRX 22 19 Low Freq Gain Zero Freq at ee min 0000b Maximum 0001b Adaptive Adaptive 001xb Reserved O1xxb Reserved 1000b Adaptive 1084MHz 1001b 805MHz 1010b 573MHz 1011b 402MHz 1100b 304MHz 1101b 216MHz 1110b 156MHz 1111b 135MHz Enabling the Transmitter To enable a transmitter for serialization the ENTX bit of the associated SERDES_CFGTXn_CNTL registers 110h 10Ch must be set high When ENTX is low all digital circuitry within the transmitter will be disabled and clocks will be gated off with the exception of the transmit clock TXBCLK n output which will continue to operate normally All current sources within the transmitter will be fully powered down with the exception of the current mode logic CML driver which will remain powered up if boundary scan is selected Figure 11 shows the fields of SERDES_CFGTXn_CNTL and Table 11 describes them Figure 11 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL 31 17 16 Reserved ENFTP R 0 R W 1 1
54. DEVICE_VENDORIDENTITY 0030h Device Vendor ID assigned by RapidlO Trade Association 182 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i3 TEXAS INSTRUMENTS www ti com 5 53 Device Information CAR DEV_INFO The device information CAR DEV_INFO is shown in Figure 116 and described in Table 124 Writes have no effect to this register The values are hard coded and will not change from their reset state SRIO Registers Figure 116 Device Information CAR DEV_INFO Address Offset 1004h 31 DEVICEREV LEGEND R Read only n Value after reset R 00000000h Table 124 Device Information CAR DEV_INFO Field Descriptions Bit Field Value Description 31 0 DEVICEREV 00000000h Vendor supply device revision SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 183 d TEXAS INSTRUMENTS www ti com SRIO Registers 5 54 Assembly Identity CAR ASBLY_ID The assembly identity CAR ASBLY_ID is shown in Figure 117 and described in Table 125 Writes have no effect to this register The values are hard coded and will not change from their reset state Figure 117 Assembly Identity CAR ASBLY_ID Address Offset 1008h 16 15 31 0 ASSY_IDENTITY ASSY_VENDORIDENTITY R 0000h R 0030h LEGEND R Read only n Value after reset Table 125 Assembly Identity CAR ASBLY_ID Field Descriptions
55. DMA Head Descriptor Pointer Register 14 Section 5 43 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 105 da TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section 063Ch QUEUE15 RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 15 Section 5 43 0680h QUEUEO_RXDMA_CP Queue Receive DMA Completion Pointer Register 0 Section 5 44 0684h QUEUE1_RXDMA_CP Queue Receive DMA Completion Pointer Register 1 Section 5 44 0688h QUEUE2 RXDMA_CP Queue Receive DMA Completion Pointer Register 2 Section 5 44 068Ch QUEUE3_ RXDMA_CP Queue Receive DMA Completion Pointer Register 3 Section 5 44 0690h QUEUE4 RXDMA_CP Queue Receive DMA Completion Pointer Register 4 Section 5 44 0694h QUEUE5 RXDMA_CP Queue Receive DMA Completion Pointer Register 5 Section 5 44 0698h QUEUE6_RXDMA_CP Queue Receive DMA Completion Pointer Register 6 Section 5 44 069Ch QUEUE7_RXDMA_CP Queue Receive DMA Completion Pointer Register 7 Section 5 44 O6A0h QUEUE8_RXDMA_CP Queue Receive DMA Completion Pointer Register 8 Section 5 44 06A4h QUEUES RXDMA_CP Queue Receive DMA Completion Pointer Register 9 Section 5 44 O6A8h QUEUE10 RXDMA_CP Queue Receive DMA Completion Pointer Register 10 Section 5 44 06
56. Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Functional Description SRIO_REGS gt SERDES_CFGO_CNTL 0x00000013 SRIO_REGS gt SERDES_CFG1_CNTL 0x00000000 SRIO_REGS gt SERDES_CFG2_CNTL 0x00000000 SRIO_REGS gt SERDES_CFG3_CNTL 0x00000000 SRIO_REGS gt SERDES_CFGRXO_CNTL 0x00081121 enable rx half rate SRIO_REGS gt SERDES_CFGRX1_CNTL 0x00081121 enable rx half rate SRIO_REGS gt SERDES_CFGRX2_CNTL 0x00081121 enable rx half rate SRIO_REGS gt SERDES_CFGRX3_CNTL 0x00081121 enable rx half rate SRIO_REGS gt SERDES_CFGTXO_CNTL 0x00010821 enable tx half rate SRIO_REGS gt SERDES_CFGTX1_CNTL 0x00010821 enable tx half rate SRIO_REGS gt SERDES_CFGTX2_CNTL 0x00010821 enable tx half rate SRIO_REGS gt SERDES_CFGTX3_CNTL 0x00010821 enable tx half rate 2 3 13 3 Peripheral Initializations Set Device ID Registers rdata SRIO_REGS gt DEVICEID_REG1 wdata 0Ox00ABBEEF mask Ox00FFFFFF mdata wdata amp mask rdata amp mask SRIO_REGS gt DEVICEID_REGl mdata id 16b BEEF id 08b AB rdata SRIO_REGS gt DEVICEID_REG2 wdata Ox00ABBEEF mask Ox00FFFFFF mdata wdata amp mask rdata amp mask SRIO_REGS gt DEVICEID_REG2 mdata id 16b BEEF id 08b AB rdata SRIO_REGS gt PER_SET_CNTL data 0x00000000 mask 0x01000000 mdata wdata amp mask rdata amp mask S
57. Doorbell3 interrupts RX CPPI interrupts TX CPPI interrupts LSU interrupts Error Reset and Special Event interrupts To reduce the number of reads up to 5 reads required to find the source bit an Interrupt Status Decode Register ISDR is implemented for each supported physical interrupt destination The device supports up to eight interrupt destinations INTDSTO INTDST7 The names of the ISDRs and their address offsets are e INTDSTO_DECODE Address offset 0300h e INTDST1_DECODE e INTDST2_DECODE e INTDST3_DECODE e INTDST4_DECODE e INTDST5_DECODE e INTDST6_DECODE Address offset 0304h Address offset 0308h Address offset 030Ch Address offset 0310h Address offset 0314h Address offset 0318h mann ee A e INTDST7_DECODE Address offset 031Ch Aside from supporting different interrupt destinations the ISDRs are the same in content and functionality The register fields are shown in Figure 59 Figure 60 shows which interrupt sources can be mapped to SPRUE13A September 2006 Serial RapidlO SRIO 97 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Interrupt Conditions each bit in the ISDR Bits within the LSU interrupt condition status register ICSR are logically grouped for a given core and ORed together into a single bit bit 31 of the decode register Similarly the bits within the Error Reset and Special Event ICSR are ORed together into bit 30 of the decode register The TX CPPI and RX CPPI int
58. ENEE Ek 45 18 Mailbox to Queue Mapping Register Pair nun nun nun nun nun nn 46 19 RX Buffer Descriptor FieldS aesanianai nun a a a a ek ENK de ETA a 47 20 RX CPPI Mode Explanation uuuussunsennennnannnnnnnnnunnnnnnnnnunnnunnun nun nunnunnnnnnennennnunnnnnnnnnnnnnnnnnn nen 49 21 GCPPI Boundan Diagrami ers na ee ee 51 22 TX Buffer Descriptor Fields ENNEN a EE ENER ENEE nenn nennen anne nun nenn nenn nennen 52 23 Weighted Round Robin Programming Registers Address Offset 7EOh 7ECh uuzuuu4usennnan nn ann nn 56 24 RX B fferDescriptofsa uu cc ses san nn daub a ann E AE nee 62 25 TX Buffer Descriptors a susanne a a a 63 26 Reegele le 64 27 Flow Control Table Entry Registers Address Offset 0900h 093Ch ceceeee eee eee eect ee eee seen eeeeeeeeeees 66 28 Transmit Source Flow Control Masks ENEE 67 29 Fields Within Each Flow Mask seceseteeeeeeeeee senor ene ERKENNEN KENE ENKER ENEE ENEE NEE nennen nun nn anne nn 67 30 Configuration Bus Example EEN 69 31 DMA Example ET 69 32 GBL EN Re ATI EE 71 33 GBL EN STAT Address 0034Ah 2 u eenaa lan 71 34 BERO IEN Address TEE 72 35 BLKO EN STAT Address 003Ch eisioes anne nn a a an ann cnet eau 73 36 BK EN Address DOUD eeueueu ege ee cence en ceed nn a ra ae 783 37 BLK1_EN STAT Address 0044h 4 u 444um0 anna na nn nn a anni nn m nenn 783 38 BERS EN Address LTE 73 39 BERKS EN STAT Address EE ee ee ea E ee 73 40 Peripheral Control Register PCR Address Offset 000
59. Enables receive link flow control Reserved 29 SOFT_REC Software controlled error recovery Transmission of error recovery sequence is performed by the hardware Transmission of error recovery sequence is performed by the software By default the transmission error recovery sequence is performed by the hardware If this bit is set the hardware recovery is disabled and the hardware transmission logic must wait until software has written the register Port n Local ackID Status CSR 28 27 Reserved These read only bits return Os when read 26 FORCE_REINIT Force reinitialization process In 4x mode this bit affects all 4 lanes This bit is write only and reads always return 0 25 24 TRANS_MODE 00b 01b 1xb Describes the transfer mode for each port Reserved Cut Through Mode Store amp Forward Mode Reserved 236 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 183 Port Control Independent Register n SPn_CTL_INDEP Field Descriptions continued Bit Field Value Description 23 DEBUG Mode of operation Normal mode Debug mode The debug mode unlocks capture registers for write and enable debug packet generator feature 22 SEND_DBG_PKT Send debug packet Write 1 to force the sending of a debug packet This bit is set by software and cleared after debug pac
60. Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map10 TX_Queue_Map10 TX_QUEUE_CNTL2 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map11 TX_Queue_Map11 TX_QUEUE_CNTL2 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map12 TX_Queue_Map12 TX_QUEUE_CNTL3 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 7 4 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map13 TX_Queue_Map13 TX_QUEUE_CNTL3 1 1 8 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3
61. Flow 7 from table entry 6 FL6 0 TX source does not support Flow 6 from table entry 1 TX source supports Flow 6 from table entry 5 FL5 0 TX source does not support Flow 5 from table entry 1 TX source supports Flow 5 from table entry 4 FL4 0 TX source does not support Flow 4 from table entry 1 TX source supports Flow 4 from table entry 3 FL3 0 TX source does not support Flow 3 from table entry 1 TX source supports Flow 3 from table entry 2 FL2 0 TX source does not support Flow 2 from table entry 1 TX source supports Flow 2 from table entry 1 FL1 0 TX source does not support Flow 1 from table entry 1 TX source supports Flow 1 from table entry 0 FLO 0 TX source does not support Flow 0 from table entry 1 TX source supports Flow 0 from table entry 2 3 9 Endianness 68 RapidlO is based on Big Endian This is discussed in detail in Section 2 4 of the Rapid O Interconnect Specification Essentially Big Endian specifies the address ordering as the most significant bit byte first For example in the 29 bit address field of a RapidlO packet shown in Figure 6 the left most bit that is transmitted first in the serial bit stream is the MSB of the address Likewise the data payload of the packet is double word aligned Big Endian which means the MSB is transmitted first Bit O of all the RapidlO defined MMR registers is the MSB All Endian specific conversion is handled within the peripheral For double word aligned payloads the data should be writ
62. Flow 9 from table entry 1 LSUn supports Flow 9 from table entry 162 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 103 LSUn FLOW_MASK Fields continued Bit Field Value Description 8 FL8 0 LSUn does not support Flow 8 from table entry 1 LSUn supports Flow 8 from table entry 7 FL7 0 LSUn does not support Flow 7 from table entry 1 LSUn supports Flow 7 from table entry 6 FL6 0 LSUn does not support Flow 6 from table entry 1 LSUn supports Flow 6 from table entry 5 FL5 0 LSUn does not support Flow 5 from table entry 1 LSUn supports Flow 5 from table entry 4 FL4 0 LSUn does not support Flow 4 from table entry 1 LSUn supports Flow 4 from table entry 3 FL3 0 LSUn does not support Flow 3 from table entry 1 LSUn supports Flow 3 from table entry 2 FL2 0 LSUn does not support Flow 2 from table entry 1 LSUn supports Flow 2 from table entry 1 FL1 0 LSUn does not support Flow 1 from table entry 1 LSUn supports Flow 1 from table entry 0 FLO 0 LSUn does not support Flow 0 from table entry 1 LSUn supports Flow 0 from table entry SPRUE13A September 2006 Serial RapidlO SRIO 163 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com 5 41 Queue n Transmit DMA Head Descriptor Pointer Register QUEUEn_TXDMA_HDP There are sixteen of these registers see Table 104 QUEUEn_TXDMA_HDP is shown
63. HO R 0 HO HO HO R 0 HO HO R 0 R 0 HO HO R 0 R 0 LEGEND R Read only n Value after reset Table 73 LSU Interrupt Condition Status Register LSU_ICSR Field Descriptions Bit Field Value Description 31 ICS31 0 LSU4 interrupt condition not detected 1 LSU4 interrupt condition detected Packet not sent due to unavailable outbound credit at given priority 30 ICS30 0 LSU4 interrupt condition not detected LSU4 interrupt condition detected Retry Doorbell response received or Atomic test and swap was not allowed semaphore in use _ 29 ICS29 LSUA interrupt condition not detected LSU4 interrupt condition detected Transaction was not sent due to DMA data transfer error 28 ICS28 LSU4 interrupt condition not detected LSU4 interrupt condition detected Transaction timeout occurred 27 ICS27 LSU4 interrupt condition not detected Oj Oj O LSU4 interrupt condition detected Transaction was not sent due to unsupported transaction type or invalid field encoding 26 ICS26 LSU4 interrupt condition not detected LSU4 interrupt condition detected Transaction was not sent due to Xoff condition 25 ICS25 LSU4 interrupt condition not detected Oj O LSU4 interrupt condition detected Non posted transaction received ERROR response or error in response payload 24 ICS24 0 LSU4 interrupt condition not detected LSU4 interrupt condition detected Transaction c
64. ICR4 0000b in LSU_ICRRO LSU1 has generated a transaction timeout interrupt request and that request is routed to interrupt destination 0 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 95 da TEXAS INSTRUMENTS www ti com Interrupt Conditions Figure 57 LSU Interrupt Condition Routing Registers LSU Interrupt Condition Routing Register 0 LSU_ICRRO Address Offset 02E0h 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 LSU Interrupt Condition Routing Register 1 LSU_ICRR1 Address Offset 02E4h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LSU Interrupt Condition Routing Register 2 LSU_ICRR2 Address Offset 02E8h 31 28 27 24 23 20 19 16 ICR23 ICR22 ICR21 ICR20 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR19 ICR18 ICR17 ICR16 R W 0000 R W 0000 R W 0000 R W 0000 LSU Interrupt Condition Routing Register 3 LSU_ICRR3 Address Offset 02ECh 31 28 27 24 23 20 19 16 ICR31 ICR30 ICR29 ICR28 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 43 0 ICR27 ICR26 ICR25 ICR24 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset 4 4 1 3 E
65. ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO R 0 R 0 R 0 HO HO HO R 0 HO HO HO HO HO HO HO HO HO Doorbell 1 Interrupt Condition Clear Register DOORBELL1_ICCR Address Offset 0218h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO WO WO WO WO WO WO WO WO W 0 WO WO WO W 0 W 0 WO WO LEGEND R Read only W Write only n Value after reset SPRUE13A September 2006 Serial RapidlO SRIO 87 Submit Documentation Feedback Interrupt Conditions da TEXAS INSTRUMENTS www ti com Figure 48 Doorbell 2 Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status Register DOORBELL2_ICSR Address Offset 0220h 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO R 0 R 0 R 0 HO HO HO R 0 R 0 R 0 R 0 R 0 HO HO HO R 0 R 0 Doorbell 2 Interrupt Condition Clear Register DOORBELL2_ICCR Address Offset 0228h 31 16 Reserved
66. LEGEND R W Read Write R Read only n Value after reset Table 187 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS Field Descriptions Bit Field Value Description 31 0 MULT_EVNT_CS Write to send Control Symbol data is ignored Reads return 000000h SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 239 SRIO Registers 5 99 Port Control Symbol Transmit n Register SPn_CS_TX Each of da TEXAS INSTRUMENTS www ti com the four ports is supported by a register of this type see Table 188 The port control symbol transmit n register SPn_CS_TX is shown in Figure 162 and described in Table 189 Table 188 SPn_CS_TX Registers and the Associated Ports Register Address Offset Associated Port SPO_CS_TX 14014h Port 0 SP1_CS_TX 14114h Port 1 SP2_CS_TX 14214h Port 2 SP3_CS_TX 14314h Port 3 Figure 162 Port Control Symbol Transmit n Register SPn_CS_TX 31 29 28 24 23 19 18 16 STYPE_O PAR_O PAR_1 STYPE_1 R W 0 R W 0 R W 0 R W 0 15 13 12 11 0 CMD CS_EMB Reserved R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n Value after reset Table 189 Port Control Symbol Transmit n Register SPn_CS_TX Field Descriptions Bit Field Value Description 31 29 STYPE_O Encoding for control symbol that makes use of parameters PAR_O and PAR_1 2
67. R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO LEGEND R Read only W Write only n Value after reset Figure 49 Doorbell 3 Interrupt Condition Status and Clear Registers Doorbell 3 Interrupt Condition Status Register DOORBELL3_ICSR Address Offset 0230h 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO HO HO R 0 HO HO HO R 0 HO HO HO R 0 HO HO HO R 0 HO Doorbell 3 Interrupt Condition Clear Register DOORBELL3_ICCR Address Offset 0238h 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO LEGEND R Read only W Write only n Value after reset 4 3 2 CPPI Interrupt Condition Status and Clear Registers The ICSRs and the ICCRs for the RXU and the TXU are shown in Figure 50 and Figure 51 These interrupt condition registers are used when the SRIO peripheral receives and transmits data message packets Each ICS bit corresponds to the interrupt for one of the buffer descriptor queues For example the bits ICS15 ICS8 and ICSO of RX_CPPI_ICSR correspond to RX buffer descriptor queues 15 8
68. Reserved 0 These read only bits return 0 when read 15 0 ICCx TX CPPI interrupt clear x 15 to 0 0 No effect 1 Clear bit x of TX_CPPI_ICSR SPRUE13A September 2006 Serial RapidlO SRIO 137 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 22 LSU Interrupt Condition Status Register LSU_ICSR Each of the status bits in this register indicates the occurrence of a particular type of transaction interrupt condition for a particular LSU LSU_ICSR is shown in Figure 83 and described in Table 73 For additional programming information see Section 4 3 3 Figure 83 LSU Interrupt Condition Status Register LSU_ICSR Address Offset 0260h Sam Bits for LSU4 gt gem Bits for LSU3 gt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 lt Bits for LSU2 gt gem Bits for LSU1 gt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO HO HO
69. SPn_LM_REQ Registers and the Associated Ports Register Address Offset Associated Port SPO_LM_REQ 1140h Port 0 SP1_LM_REQ 1160h Port 1 SP2_LM_REQ 1180h Port 2 SP3_LM_REQ 11A0h Port 3 Figure 132 Port Link Maintenance Request CSR n SPn_LM_REQ 31 3 2 0 Reserved COMMAND HO R W 000 LEGEND R W Read Write R Read only n Value after reset Table 141 Port Link Maintenance Request CSR n SPn_LM_REQ Field Descriptions Bit Field Value Description 31 3 Reserved 0 These read only bits return Os when read 2 0 COMMAND 000b 111b A write to this register generates a link request control symbol on the corresponding port interface Command to be sent in the link request control symbol When read this field returns the last written value 200 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 70 Port Link Maintenance Response CSR n SPn_LM_RESP Each of the four ports is supported by a register of this type see Table 142 The port link maintenance response CSR n SPn_LM_RESP is shown in Figure 133 and described in Table 143 Table 142 SPn_LM_RESP Registers and the Associated Ports Register Address Offset Associated Port SPO_LM_RESP 1144h Port 0 SP1_LM_RESP 1164h Port 1 SP2_LM_RESP 1184h Port 2 SP3_LM_RESP 11A4h Port 3 Figure 133 Port Link Maintenance Response CSR n SPn_LM_RESP
70. Submit Documentation Feedback INSTRUMENTS www ti com SRIO Functional Description Figure 17 Message Request Packet la n 64 64 gt PHY TRA LOG TRA LOG PHY Pe 10 7 20 7 4 7 16 7 n 64 16 16 A oe a 7 7 7 N es S BS ae 7 i ae gt x N Big oe ae gar pete N EE ae we i Pa git N e BEN Ee sae a Ge ie ar u ir Pr N Pua jji r SE Pad Le A at er wie Bag a ser E Be k ackID rsv_ prio tt ftype destID sourcelD msglen ssize letter mbox msgseg xmbox double word 0 double word 1 I er I double word n 2 double word n 1 CRC 5 3 2 2 4 8 8 4 4 2 2 4 64 64 n 4 64 64 64 16 ftype 1011 This enables the letter and mailbox fields to instead allow four concurrent single segment messages to sixty four possible mailboxes 256 total locations for a source and destination pair The mailbox mapper directs the inbound messages to the appropriate queue based on a pre programmed routing table It bases the decision on the SOURCEID MSGLEN the size indicates whether the message is segmented MBOX LETTER and XMBOX fields of the RapidlO packet There are 32 programmable look up table entries for mapping mailboxes to queues Each entry consists of two registers RXU_MAP_Ln and RXU_MAP_Hn which are shown in Figure 18 A detailed summary of these register s field is in Section 5 50 In total there are 64 registers at addr
71. TX_CPPI_ICSR e RX buffer descriptor queue 11 bit 11 of RX_CPPI_ICSR 19 ISD19 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 12 bit 12 of TX_CPPI_ICSR e RX buffer descriptor queue 12 bit 12 of RX_CPPI_ICSR 18 ISD18 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 13 bit 13 of TX_CPPI_ICSR e RX buffer descriptor queue 13 bit 13 of RX_CPPI_ICSR 17 ISD17 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 14 bit 14 of TX_CPPI_ICSR e RX buffer descriptor queue 14 bit 14 of RX_CPPI_ICSR 16 ISD16 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 15 bit 15 of TX_CPPI_ICSR e RX buffer descriptor queue 15 bit 15 of RX_CPPI_ICSR SPRUE13A September 2006 Serial RapidlO SRIO 151 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com Table 84 Interrupt Status Decode Register INTDSTn_DECODE Field Descriptions continued Bit Field Value Description 15 ISD15 0 1 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 15 bit 15 of DOORBELLO_I
72. The CRC value protects the entire packet except the ackID and one bit of the reserved PHY field The peripheral checks the CRC automatically in hardware If the CRC is correct a Packet Accepted control symbol is sent by the receiving device If the CRC is incorrect a Packet Not Accepted control symbol is sent so that transmission may be retried 2 1 2 3 Control Symbols Control symbols are physical layer message elements used to manage link maintenance packet delimiting packet acknowledgment error reporting and error recovery All transmitted data packets are delimited by start of packet and end of packet delimiters SRIO control symbols are 24 bits long and are protected by their own CRC see Figure 7 Control symbols provide two functions stypeO symbols convey the status of the port transmitting the symbol and stype1 symbols are requests to the receiving port or transmission delimiters They have the following format which is detailed in Section 3 of the RapidlO Physical Layer 1x 4x LP Serial Specification Figure 7 Serial RapidlO Control Symbol Format Delimiter 1st Byte 2nd Byte 3rd Byte SC or PD stypeO ParameterO parameter1 stype1 cmd CRC 8 3 5 5 3 3 5 Control symbols are delimited by special characters at the beginning of the symbol If the control symbol contains a packet delimiter start of packet end of packet etc the special character PD K28 3 is used If the control symbol does not contain
73. W 00 R W 000000 15 0 SOURCEID R W 0000h Mailbox to Queue Mapping Register H n RXU_MAP_H n 31 Reserved R 0 10 9 8 7 6 5 2 1 0 SEGMENT_ Reserved TT Reserved QUEUE_ID PROMISCUOUS MAPPING R 0 R W 01 R 00 R W 0000 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 119 Mailbox to Queue Mapping Register Ln RXU_MAP_Ln Field Descriptions Bit Field Value Description 31 30 LETTER_MASK 00b 11b Letter mask Each 0 in this field indicates a don t care bit in the letter number This allows mapper n to handle a set or range of letter numbers rather than only one 29 24 MAILBOX_MASK Mailbox mask Each 0 in this field indicates a don t care bit in the mailbox number This allows mapper n to handle a set or range of mailbox numbers rather than only one For a single segment message 000000b 111111b 6 bit mailbox mask value For a multi segment message xxxx00b xxxx11b 3 bit mailbox mask value 23 22 LETTER 00b 11b Letter number If LETTER_MASK 11b this is the only letter number handled by mapper n If LETTER_MASK is not 11b mapper n handles the set of letter numbers formed with the mask bit s 21 16 MAILBOX Mailbox number If MAILBOX_MASK 111111b this is the only mailbox number handled by mapper n If MAILBOX_MASK is not all 1s mapper n handles the set of mailbox numbers formed with the mask bit s For a single segment message 000000b 111111b 6 bit mailbox number 0 to 63 For
74. W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset SPRUE13A September 2006 Serial RapidlO SRIO 147 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers Table 81 LSU Interrupt Condition Routing Register Field Descriptions Field Value Description ICRx Interrupt condition routing Routes the associated LSU interrupt request to one of eight interrupt x 0 to 31 destinations INTDSTO INTDST7 Bits ICRO ICR7 are for LSU1 bits ICR8 ICR15 for LSU2 bits ICR16 ICR23 for LSU3 bits ICR24 ICR31 for LSU4 0000b INTDSTO 0001b INTDST1 0010b INTDST2 0011b INTDST3 0100b INTDST4 0101b INTDST5 0110b INTDST6 0111b INTDST7 1xxxb Reserved 148 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 30 Error Reset and Special Event Interrupt Condition Routing Registers ERR_RST_EVNT_ICRR ERR_RST_EVNT_ICRR2 and ERR_RST_EVNT_ICRR3 The ICRRs shown in Figure 91 route port interrupt requests from ERR_RST_EVNT_ICSR to interrupt destinations For example if ICS8 1 in ERR_RST_EVNT_ICSR and ICR8 0001b in ERR_RST_EVNT_ICRR2 port 0 has generated an error interrupt request and that request is routed to interrupt destination 1 Table 82 gives a general description for an ICRx field in any of the three registers For additional programming see Section 4 4 1 3 Figure 91 Error Rese
75. a packet delimiter the special character SC K28 0 is used This use of special characters provides an early warning of the contents of the control symbol The CRC does not protect the special characters but an illegal or invalid character is recognized and flagged as Packet Not Accepted Since control symbols are known length they do not need end delimiters 24 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description The type of received packet determines how the packet routing is handled Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks This prevents erroneous allocation of resources to them Unsupported packet types are responded to with an error response packet Section 2 1 2 4 details the handling of such packets 2 1 2 4 SRIO Packet Type The type of SRIO packet is determined by the combination of Ftype and Ttype fields in the packet Table 3 lists all supported combinations of Ftype Ttype and the corresponding decoded actions on the packets Table 3 Packet Types Ftype Ttype Packet Type Ftype 0 Ttype don t care Ftype 2 Ttype 0100b NREAD Ttype 1100b Atomic increment Ttype 1101b Atomic decrement Ttype 1110b Atomic set Ttype 1111b Atomic clear Ttype others Ftype 5 Ttype 0100b NWRITE Ttype 0101b NWRITE_R Ttype 1110b Atomic tes
76. and 0 Similarly the bits ICS15 ICS8 and ICSO of TX_CPPI_ICSR support TX buffer descriptor queues 15 8 and 0 The 16 ICC bits of each interrupt condition clear register ICCR are used to clear the corresponding bits in the ICSR For reception the clearing of any ICSR bit depends on the CPU writing the value of the last buffer descriptor processed to the completion pointer CP register for the queue QUEUEn_RXDMA_CP Port hardware clears the ICSR bit only if the CP value written by the CPU equals the port written value in the CP register 88 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Interrupt Conditions For transmission the clearing of any ICSR bit is dependent on the CPU writing to the CP register for the queue QUEUEn_TXDMA_CP The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value This value is compared against the port written value in the CP register If the values are equal the interrupt is deasserted Figure 50 RX CPPI Interrupt Condition Status and Clear Registers RX CPPI Interrupt Condition Status Register RX_CPPI_ICSR Address Offset 0240h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO
77. compared against the CRC value at the end of the received packet After the packet reaches the logical layer the packet fields are decoded and the payload is buffered Depending on the type of received packet the packet routing is handled by functional blocks which control the DMA access SRIO Packets The SRIO data stream consists of data fields pertaining to the logical layer the transport layer and the physical layer e The logical layer consists of the header defining the type of access and the payload if present e The transport layer is partially dependent on the physical topology in the system and consists of source and destination IDs for the sending and receiving devices e The physical layer is dependent on the physical interface i e serial versus parallel RapidlO and includes priority acknowledgment and error checking fields 2 1 2 1 Operation Sequence 22 SRIO transactions are based on request and response packets Packets are the communication element between endpoint devices in the system A master or initiator generates a request packet which is transmitted to a target The target then generates a response packet back to the initiator to complete the transaction Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i3 TEXAS INSTRUMENTS www ti com SRIO Functional Description SRIO endpoints are typically not connected directly to each other but instead have intervening connection
78. contain the correct SOURCEID value 15 0 16BNODEID 0000h FFFFh This value is equal to the value of the RapidlO Base Device ID CSR The CPU must read the CSR value and set this register so that outgoing packets contain the correct SOURCEID value SPRUE13A September 2006 Serial RapidlO SRIO 121 Submit Documentation Feedback i TEXAS INSTRUMENTS www ti com SRIO Registers 5 10 RapidlO DEVICEID2 Register DEVICEID_REG2 The RapidlO DEVICEID2 register DEVICEID_REG2 is shown in Figure 71 and described in Table 51 For additional programming information see Section 2 3 15 1 and Section 2 3 15 3 Figure 71 RapidlO DEVICEID2 Register DEVICEID_REG2 Offset 0x0084 31 24 23 16 Reserved 8BNODEID R 00h R W FFh 15 16BNODEID R FFFFh LEGEND R W Read Write R Read only n Value after reset Table 51 RapidlO DEVICEID2 Register DEVICEID_REG2 Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 8BNODEID 00h FFh This is a secondary supported DevicelD checked against an incoming packet s DestID field Typically used for Multi cast support 15 0 16BNODEID 0000h FFFFh This is a secondary supported DevicelD checked against an incoming packet s DestID field Typically used for Multi cast support 122 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 11 Pa
79. control symbol The port did not receive an unexpected acknowledge control symbol The port received an unexpected acknowledge control symbol LINK_TIMEOUT Link timeout The port did not experience a link timeout The port experienced a link timeout The port did not receive an acknowledge or link response control symbol within the specified time out interval The capture registers do not have valid information during this error detection 220 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 83 Port Error Rate Enable CSR n SPn_RATE_EN Each of the four ports is supported by a register of this type see Table 160 The port error rate enable CSR n SPn_RATE_EN is shown in Figure 146 and described in Table 161 Table 160 SPn_RATE_EN Registers and the Associated Ports Register Address Offset Associated Port SPO_RATE_EN 2044h Port 0 SP1_RATE_EN 2084h Port 1 SP2_RATE_EN 20C4h Port 2 SP3_RATE_EN 2104h Port 3 Figure 146 Port Error Rate Enable CSR n SPn_RATE_EN 31 30 24 ERR_IMP_ SPECIFIC NEE R W 0 R 00h 23 22 21 20 19 18 17 16 CORRUPT_ CNTL_SYM_ RCVED_ PKT_ RCVED_PKT_ RCVED_ Reserved CNTL_SYM_ UNEXPECTED_ PKT_NOT_ UNEXPECTED WITH_BAD PKT_OVER Reserved EN ACKID_EN ACCPT_EN ACKID_EN CRC_EN 276B_EN R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W
80. default only K A and R characters are available If input receives any other characters in idle sequence it should enter the Input Error stopped state 1 Error checking disabled all not idle or invalid characters during idle sequence are ignored 28 TX_FIFO_BYPASS Transmit FIFO bypass 0 The TX_FIFO is operational default The TX_FIFO is bypassed The txbclk and the sys_clk must be locked during operation but the phase variation up to 1 clock cycle is allowable The 4 deep FIFO is used to accommodate the phase difference 27 PW_DIS Port write error reporting disable 0 Enable Port Write Error reporting default Disable Port Write Error reporting 26 TGT_ID_DIS Destination ID Decode Disable Definition of packet acceptance by the physical layer 0 Packet accepted if DestID Base ID When DestID is not equal to Base ID the packet is ignored Le it is accepted by RapidlO port but is not forwarded to logical layer 1 Packet accepted with any DestID and forwarded to the logical layer 25 SELF_RST Self reset interrupt enable when 4 link request reset control symbols are accepted 0 Self reset interrupt disabled default interrupt signal is asserted Self reset interrupt enabled the reset signal is asserted by the reset controller When the SELF_RST is set to 1 the SERDES macro resets and all register values from address offset 1000h and higher are returned to default value All initialized values are lost 24 6
81. described in Table 147 Table 146 SPn_ERR_STAT Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_STAT 1158h Port 0 SP1_ERR_STAT 1178h Port 1 SP2_ERR_STAT 1198h Port 2 SP3_ERR_STAT 11B8h Port 3 Figure 135 Port Error and Status CSR n SPn_ERR_STAT 31 27 26 25 24 OUTPUT_ OUTPUT_ OUTPUT_ Reserved PKT_ FLD_ DEGRD_ DROP ENG ENC R 0 R W 0 R W 0 R W 0 23 21 20 19 18 17 16 OUTPUT _ auteur OUTPUT_ OUTPUT_ OUTPUT_ Reserved RETRY es RETRY ERROR ERROR ENC STP ENC STP R 0 R W 0 R 0 R 0 R W 0 R 0 15 11 10 9 8 INPUT_ INPUT_ INPUT_ Reserved RETRY_ ERROR_ ERROR_ STP ENC STP R 0 R 0 R W 0 R 0 7 5 4 3 2 1 0 PORT PORT_ PORT_ PORT_ Meer m un ERROR OK UNINITIALIZED Do RIW 0 R 0 R W 0 R 0 ER LEGEND R W Read Write R Read only n Value after reset Table 147 Port Error and Status CSR n SPn_ERR_STAT Field Descriptions Bit Field Value Description 31 27 Reserved 0 These read only bits return Os when read 26 OUTPUT_PKT_DROP Output packet drop switch devices only 0 The output port has not discarded a packet The output port has discarded a packet 25 OUTPUT_FLD_ENC Output failed condition encountered Once set the OUTPUT_FLD_ENC bit remains set until software writes a 1 to it 0 The output port has not encountered a failed condition The output port has encountered a failed condition The f
82. encountered bit is set the port sets the Port Error bit in the Port n Error and Status CSR and stops attempting to send packets to the connected device Packets are discarded if the Drop Packet Enable bit is set 2 DROP_PACKET_ENABLE Drop packet enable The output port continues to try to transmit packets that have been rejected due to transmission errors The output port drops packets that are acknowledged with a packet not accepted control symbol when the error failed threshold is exceeded If the port heals and the current error rate falls below the failed threshold the output no longer drops packets switch devices only 1 PORT_LOCKOUT Port lockout The port is enabled to issue any packets The port is stopped and is not enabled to issue or receive any packets The input port can still follow the training procedure and can still send and respond to link requests All received packets return packet not accepted control symbols to force an error condition to be signaled by the sending device SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 207 da TEXAS INSTRUMENTS www ti com SRIO Registers Table 149 Port Control CSR n SPn_CTL Field Descriptions continued Bit Field Value Description 0 PORT_TYPE 1 Port type This read only bit indicates that the port is a serial port rather than a parallel port 208 Serial RapidlO SRIO SPRUE13A Septembe
83. has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met therefore no electrical data timing information is supplied here for this interface TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 gives an introduction to the TMS320C62x and TMS320C67x DSPs development tools and third party support TMS320C6000 Programmer s Guide literature number SPRU198 describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples TMS320C6000 Code Composer Studio Tutorial literature number SPRU301 introduces the Code Composer Studio integrated development environment and software tools Code Composer Studio Application Programming Interface Reference Guide literature number SPRU321 describes the Code Composer Studio application programming interface API which allows you to program custom plug ins for Code Composer TMS320C64x Megamodule Reference Guide literature number SPRU871 describes the TMS320C64x digital signal processor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory protection bandwidth management and the memory and cache TMS320TCI648x Bootloader User s Guide literature number SPRUEC7 describes the features of the on chip Bootloader provided with the TMS320TCI648x Digital
84. in Figure 103 and described in Table 105 For additional programming information see Section 2 3 4 2 31 Table 104 QUEUEn_TXDMA_HDP Registers Register Address Offset QUEUEO_TXDMA_HDP QUEUE1_TXDMA_HDP QUEUE2_TXDMA_HDP QUEUE3_TXDMA_HDP QUEUE4_TXDMA_HDP QUEUE5_TXDMA_HDP QUEUE6_TXDMA_HDP QUEUE7_TXDMA_HDP QUEUE8_TXDMA_HDP QUEUE9_TXDMA_HDP QUEUE10_TXDMA_HDP QUEUE11_TXDMA_HDP QUEUE12_TXDMA_HDP QUEUE13_TXDMA_HDP QUEUE14_TXDMA_HDP QUEUE15_TXDMA_HDP 0500h 0504h 0508h 050Ch 0510h 0514h 0518h 051Ch 0520h 0524h 0528h 052Ch 0530h 0534h 0538h 053Ch Figure 103 Queue n Transmit DMA Head Descriptor Pointer Register QUEUEn_TXDMA_HDP TX_HDP LEGEND R W Read Write n Value after reset R W 00000000h Table 105 Queue n Transmit DMA Head Descriptor Pointer Register QUEUEn_TXDMA_HDP Field Descriptions Bit Field Value Description 31 0 TX_HDP 00000000h This field is the memory address for the first buffer descriptor in the transmit to queue This field is written by the DSP core to initiate queue transmit operations FFFFFFFCh and is zeroed by the port when all packets in the queue have been transmitted An error condition results if the DSP core writes this field when the current field value is nonzero The address must be 32 bit word aligned the 2 LSBs must be Os 164 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS IN
85. is also reported in the register SPO_ERR_DET 15 8 MAX_RETRY_THR 00h Oth 02h FFh Maximum Retry Threshold Trigger These bits provide the threshold value for reporting an error condition due to possibly broken partner behavior Disable the max_retry_error reporting Set the max_retry_threshold to 1 Set the max_retry_threshold to 2 Set the max_retry_threshold to 255 IRQ_EN Interrupt error reporting enable If enabled the interrupt signal is high when the IRQ_ERR is set to 1 Interrupt error report disable Interrupt error report enable IRQ_ERR Interrupt error status An error has not occurred and or there is not a Port Write condition An error occurred and there is a Port Write condition IRQ_ERR remains at 1 until software writes a 1 to it Reserved These read only bits return Os when read SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 237 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 97 Port Silence Timer n Register SPn_SILENCE_ TIMER Each of the four ports is supported by a register of this type see Table 184 The port silence timer n register SPn_SILENCE_TIMER is shown in Figure 160 and described in Table 185 Table 184 SPn_SILENCE_TIMER Registers and the Associated Ports Register Address Offset Associated Port SPO_SILENCE_TIMER 14008h Port 0 SP1_SILENCE_TIMER 14108h Port 1 SP2_SILENCE_TIMER 14208h Port 2 SP3_SILENC
86. is held low the corresponding transmitter is powered down In this state both outputs TXP and TXN will be pulled high to VDDT Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com SRIO Functional Description 2 3 10 1 Reset and Power Down Summary After reset the state of the peripheral depends on the default register values Software can also perform a hard reset of each logical block within the peripheral via the GBL_EN and BLKn_EN bits The GBL_EN bit resets the peripheral while the rest of the device is not reset The BLKn_EN bits shut down unused portions of the peripheral which minimizes power by resetting the appropriate logical block s and gating off the clock to the appropriate logical block s This should be considered an abrupt reset that is independent of the state of the peripheral and that resets the peripheral to its original state Upon reset of the peripheral the device must reestablish communication with its link partner Depending on the system this may include a discovery phase in which a host processor reads the peripheral s CAR CSR registers to determine its capabilities In its simplest form it involves retraining the SERDES and going through the initialization phase to synchronize on bit and word boundaries by using idle and control symbols as described in Section 5 5 2 of the Part VI of the RapidlO Interconnect Specification Until the peripheral and i
87. is written by the DSP core with the buffer descriptor address for the last FFFFFFFFh buffer processed by the DSP core during interrupt processing The port uses the value written to determine if the interrupt should be deasserted SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 167 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 45 Transmit Queue Teardown Register TX_QUEUE_TEAR_DOWN Each bit in this register corresponds to one of the 16 TX buffer descriptor queues If a 1 is written to a bit the teardown process is initiated for the associated queue TX_QUEUE_TEAR_DOWN is shown in Figure 107 and described in Table 112 Figure 107 Transmit Queue Teardown Register TX_QUEUE_TEAR_DOWN Address Offset 0700h 31 16 Reserved R 0000h 15 14 13 12 11 10 9 8 QUEUE15_ QUEUE14_ QUEUE13_ QUEUE12_ QUEUE11_ QUEUE10_ QUEUE9_ QUEUE8_ TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN W 0 W 0 W 0 W 0 WO WO WO WO 7 6 5 4 3 2 1 0 QUEUE7_ QUEUE6_ QUEUE5_ QUEUE4_ QUEUE3_ QUEUE2_ QUEUE1_ QUEUEO_ TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN W 0 W 0 W 0 W 0 W 0 WO WO WO LEGEND R Read only W Write only n Value after reset Table 112 Transmit Queue Teardown Register TX_QUEUE_TEAR_DOWN Field Descriptions Bit Field Value Description 31 16 Reserved 0 These read
88. mapping registers fully define the configuration for that mapper a low register RXU_MAP_Ln and a high register RXU_MAP_Hn Table 118 lists all of these register pairs and the associated RX mappers The general form of an RXU_MAP register pair is summarized by Figure 113 Table 119 and Table 120 For additional programming information see Section 2 3 4 1 Table 118 Mailbox to Queue Mapping Registers and the Associated RX Mappers Register Address Offset Associated RX Mapper RXU_MAP_LO 0800h Mapper 0 RXU_MAP_HO 0804h Mapper 0 RXU_MAP_L1 0808h Mapper 1 RXU_MAP_H1 080Ch Mapper 1 RXU_MAP_L2 0810h Mapper 2 RXU_MAP_H2 0814h Mapper 2 RXU_MAP_L3 0818h Mapper 3 RXU_MAP_H3 081Ch Mapper 3 RXU_MAP_L4 0820h Mapper 4 RXU_MAP_H4 0824h Mapper 4 RXU_MAP_L5 0828h Mapper 5 RXU_MAP_H5 082Ch Mapper 5 RXU_MAP_L6 0830h Mapper 6 RXU_MAP_H6 0834h Mapper 6 RXU_MAP_L7 0838h Mapper 7 RXU_MAP_H7 083Ch Mapper 7 RXU_MAP_L8 0840h Mapper 8 RXU_MAP_H8 0844h Mapper 8 RXU_MAP_L9 0848h Mapper 9 RXU_MAP_H9 084Ch Mapper 9 RXU_MAP_L10 0850h Mapper 10 RXU_MAP_H10 0854h Mapper 10 RXU_MAP_L11 0858h Mapper 11 RXU_MAP_H11 085Ch Mapper 11 RXU_MAP_L12 0860h Mapper 12 RXU_MAP_H12 0864h Mapper 12 RXU_MAP_L13 0868h Mapper 13 RXU_MAP_H13 086Ch Mapper 13 RXU_MAP_L14 0870h Mapper 14 RXU_MAP_H14 0874h Mapper 14 RXU_MAP_L15 0878h Mapper 15 RXU_MAP_H15 087Ch Mapper 15 RXU_MAP_L16 0880h Mapper 16 RXU_MAP_H16 0884h Mapper 16 RXU_MAP_L17 0888h Mapper 17 RXU_MAP_H17 088Ch
89. may only become available after the initial segment s of a message have had to be retried The peripheral can accept out of order segments and track completion of the overall message Scenario A in Figure 20 shows this concept For applications that are set up for specific message flows between a single source and destination it may require in order delivery of messages This is described in scenario B of Figure 20 This scenario is similar to scenario A although one message may be retried due to a lack of receiver resources subsequent pipelined messages may arrive just as resources are freed up This is a problem for systems requiring in order message delivery In this case the peripheral needs to record the Src_id mailbox letter of the first retried message and retry all subsequent new requests until resources are available and a segment for that Src_id mailbox letter is received As long as all messages are from the same source and that source sends and retries packets in order then all messages will be received in order Note that this solution is less effective when multiple sources share an RX queue The RX CPPI Control register Address offset 0744h sets this mode of operation on all receive queues Once this mode is set and a retry is issued the queue will continue to wait for an incoming message that matches the Src_id mailbox letter combination If no such packet arrives the RX queue is unusable in a locked state To reenable the queue t
90. microprocessors memory and memory mapped UO devices that operate in networking equipment memory subsystems and general purpose computing Principle features of RapidlO include e Flexible system architecture allowing peer to peer communication e Robust communication with error detection features e Frequency and port width scalability e Operation that is not software intensive e High bandwidth interconnect with low overhead e Low pin count e Low power e Low latency RapidlO Architectural Hierarchy RapidlO is defined as a 3 layer architectural hierarchy e Logical layer Specifies the protocols including packet formats which are needed by endpoints to process transactions e Transport layer Defines addressing schemes to correctly route information packets within a system e Physical layer Contains the device level interface information such as the electrical characteristics error management data and basic flow control data In the RapidlO architecture a single specification for the transport layer is compatible with differing specifications for the logical and physical layers see Figure 1 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Overview Figure 1 RapidlO Architectural Hierarchy Logical specification Information necessary for the end point Message pre En to process the transaction i e transaction passing memor GE type
91. must still write 00000000h into the INTDSTn_RATE_CNTL register after clearing the corresponding ICSR bits to acknowledge the physical interrupt If an ICSR is not mapped to an interrupt destination pending interrupt bits within the ICSR maintain current status When enabled the interrupt logic re evaluates all pending interrupts and re pulses the interrupt signal if any interrupt conditions are pending The down counter is based on the DMA clock cycle man NT eNO Figure 62 INTDSTn_RATE_CNTL Interrupt Rate Control Register 31 0 32 bit Count Down Value R W 0 LEGEND R W Read Write n Value after reset 4 8 Interrupt Handling Interrupts are either signaled externally through RapidlO packets or internally by state machines in the peripheral CPU servicing interrupts are signaled externally by the DOORBELL RapidlO packet in direct UO mode or internally by the CPPI module in the message passing mode Error Status interrupts are signaled when error counting logic within the peripheral have reached their thresholds In either case it is the peripheral that signals the interrupt and sets the corresponding status bits When the CPU is interrupted it reads the ICSR registers to determine the source of the interrupt and appropriate action to take For example if it is a DOORBELL interrupt the CPU will read from an L2 address that is specified by its circular buffer read pointer that is managed by software There may be more than o
92. notify the local processor that the data is available for processing To avoid erroneous data being processed by the local CPU the data transfer must complete through the DMA before the CPU interrupt is serviced This condition could occur since the data and interrupt queues are independent of each other and DMA transfers can stall To avoid this condition all data transfers from the peripheral through the DMA use write with response DMA bus commands allowing the peripheral to always be aware that outstanding transfers have completed Interrupts are generated only after all DMA bus responses are received Since all RapidlO packets are handled sequentially and submitted on the same DMA priority queue the peripheral must keep track of the number of DMA requests submitted and the number of responses received Thus a simple counter within the peripheral ensures that data packets have arrived in memory before submitting an interrupt The sending device initiates the interrupt by using the RapidlO defined DOORBELL message The DOORBELL packet format is shown in Figure 45 The DOORBELL functionality is user defined This packet type is commonly used to initiate CPU interrupts A DOORBELL packet is not associated with a particular data packet that was previously transferred so the INFO field of the packet must be configured to reflect the DOORBELL bit to be serviced for the correct TID info to be processed Figure 45 RapidlO DOORBELL Packet for Interrupt
93. oinly bits return Os when read 15 0 QUEUEn TEAR_DWN Queue n tear down m i 10 0 0 No effect Tear down Queue n 168 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 46 Transmit CPPI Supported Flow Mask Registers TX_CPPIl_FLOW_MASKS 0 7 Each of the eight TX CPPI flow mask registers holds the flow masks for two TX descriptor buffer queues see Table 113 Figure 108 shows the registers and Figure 109 shows the general form of a flow mask Each bit of a flow mask selects or deselects a flow for the associated TX queue see Table 114 For additional programming information see Section 2 3 8 Table 113 TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues Register Address Offset Associated TX Queues TX_CPPI_FLOW_MASKSO 0704h Queues 0 and 1 TX_CPPI_FLOW_MASKS1 0708h Queues 2 and 3 TX_CPPI_FLOW_MASKS2 070Ch Queues 4 and 5 TX_CPPI_FLOW_MASKS3 0710h Queues 6 and 7 TX_CPPI_FLOW_MASKS4 0714h Queues 8 and 9 TX_CPPI_FLOW_MASKS5 0718h Queues 10 and 11 TX_CPPI_FLOW_MASKS6 071Ch Queues 12 and 13 TX_CPPI_FLOW_MASKS7 0720h Queues 14 and 15 SPRUE13A September 2006 Serial RapidlO SRIO 169 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers Figure 108 Transmit CPPI Supported Flow Mask Registers Transmit
94. or invalid programming encoding for one or more LSU register fields 101b DMA data transfer error 110b Retry DOORBELL response received or Atomic Test and swap was not allowed semaphore in use 111b Transaction complete packet not sent due to unavailable outbound credit at given priority 1 Il Status available only when busy BSY signal 0 Four LSU register sets exist This allows four outstanding requests for all transaction types that require a response i e non posted For multi core devices software manages the usage of the registers A shared configuration bus accesses all register sets A single core device can utilize all four LSU blocks Figure 13 shows the timing diagram for accessing the LSU registers The busy BSY signal is deasserted LSUn_REG1 is written on configuration bus clock cycle TO LSUn_REG2 is written on cycle T1 LSUn_REGS is written on cycle T2 and LSUn_REG4 is written on cycle T3 The command register LSUn_REGS is written on cycle T4 The extended address field in LSUn_REGO is assumed to be constant in this example Upon completion of the write to the command register next clock cycle T5 the BSY signal is asserted at which point the preceding completion code is invalid and accesses to the LSU registers are not allowed Once the transaction completes either as a successful transmission or unsuccessfully such as flow control prevention or response timeout and any required interrup
95. points to an inactive queue the peripheral recognizes this and moves to the next mapper In order for an active queue to transmit packets at least one mapper must be pointing to that queue The default settings dictate an equally weighted round robin that starts on queueO and increments by one until reaching queue15 The round robin scheme does not provide precise control over the order of data sent out of the device The ordering of the messages provided by the entries in the Weighted Round Robin Programming Registers is not an absolute guarantee of the actual transmission order or receive order of the messages For example take a case where there are two active queues and the TX_Queue_Map registers are setup to continuously send 2 messages from Queue 0 followed by 1 message from Queue 1 If the first message from Queue 0 attempts to reuse a mailbox letter combination already in use Content Addressable Memory CAM violation or fails to gain outbound credit due to buffer congestion at a given priority then the state machine will re evaluate the TX_Queue_Map to decide on the next step Since the Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Functional Description TX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1 it will re attempt to send the same message from Queue 0 before moving on Whether it is successful or not the next attempt
96. port 8 per priority buffers UDI Port 0 Port 1 Port 2 Port 3 Physical layer 8 x 276 TX 8 x 276 TX 8 x 276 TX 8 x 276 TX Ge 8 x 276 RX 8 x 276 RX 8 x 276 RX 8 x 276 RX 4x mode data path SERDES 0 SERDES 1 SERDES 2 SERDES 3 SERDES differential signals SPRUE13A September 2006 Serial RapidlO SRIO 27 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description 2 3 2 SERDES Macro and its Configurations SRIO offers many benefits to customers by allowing a scalable non proprietary interface With the use of Tl s SERDES macros the peripheral is very adaptable and bandwidth scalable The same peripheral can be used for all three frequency nodes specified in V1 2 of the Rapid O Interconnect Specification 1 25 2 5 and 3 125 Gbps This allows you to design to only one protocol throughout the system and selectively choose the bandwidth thus eliminating the need for user s proprietary protocols in many instances and providing a faster design turn and production ramp Since this interface is serial the application space is not limited to a single board It will propagate into backplane applications as well Integration of these macros on an ASIC or DSP allows you to reduce the number of discrete components on the board and eliminates the need for bus driver chips Additionally there are some valuable features built into TI SERDES System optimization can be
97. programming see Section 4 7 31 Table 85 INTDSTn_RATE_CNTL Registers and the Associated Interrupt Destinations Register Address Offset Associated Interrupt Destination INTDSTO_RATE_CNTL 0320h INTDSTO INTDST1_RATE_CNTL 0324h INTDST1 INTDST2_RATE_CNTL 0328h INTDST2 INTDST3_RATE_CNTL 032Ch INTDST3 INTDST4_RATE_CNTL 0330h INTDST4 INTDST5_RATE_CNTL 0334h INTDST5 INTDST6_RATE_CNTL 0338h INTDST6 INTDST7_RATE_CNTL 033Ch INTDST7 Figure 93 INTDSTn Interrupt Rate Control Register INTDSTn_RATE_CNTL COUNT_DOWN_VALUE LEGEND R W Read Write R Read only n Value after reset R W 00000000h Table 86 INTDSTn Interrupt Rate Control Register INTDSTn_RATE_CNTL Field Descriptions Bit Field Value Description 31 0 COUNT_DOWN_VALUE 00000000h The value written to this field is immediately transferred to the interrupt to rate counter which starts counting down or causes an interrupt if 0 is FFFFFFFFh written 154 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 33 LSUn Control Register 0 LSUn_REGO There are four of these registers one for each LSU see Table 87 The general description for an LSU control register 0 is shown in Figure 94 and described in Table 88 For additional programming see Section 2 3 3 Table 87 LSUn_REGO Registers and the Associated LSUs Register Address Offset Associated LSU
98. quality reference clock and to isolate it and the PLL from all noise sources Since RapidlO requires 8 bit 10 bit encoded data the 8 bit mode of the SERDES PLL is not be used The SERDES macro is configured with the register SERDES_CFGO_CNTL SERDES_CFGRXn_CNTL and SERDES_CFGTXn_CNTL where nis the number of the macro To enable the internal PLL the ENPLL bit of SERDES_CFGO_CNTL see Figure 9 and Table 5 must be set After setting this bit it is necessary to allow 1us for the regulator to stabilize Thereafter the PLL will take no longer than 200 reference clock cycles to lock to the required frequency provided RIOCLK and RIOCLK are stable Registers SERDES_CFG1_CNTL SERDES_CFG2_CNTL and SERDES_CFG3_CNTL are not used Figure 9 SERDES Macro Configuration Register 0 SERDES_CFGO_CNTL 31 16 Reserved R 0000h 15 10 9 8 7 6 5 1 0 Reserved LB Reserved MPY ENPLL R 00h R W 0 HO R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset 28 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 5 SERDES Macro Configuration Register 0 SERDES_CFGO_CNTL Field Descriptions Bit Field Value Description 31 10 Reserved 0000h Reserved 9 8 LB Loop bandwidth Specify loop bandwidth settings Jitter on the reference clock will degrade both the transmit eye and receiver jitter toler
99. response to changes in frequency offset and fastest lock time but lowest precision frequency offset matching Suitable for use in systems with spread spectrum clocking 100b First order with fast lock Phase offset tracking up to 1953 ppm in the presence of 10101010 training pattern and 448 ppm otherwise 101b Second order with fast lock As per setting 001 but with improved response to changes in frequency offset when not close to lock 110b Second order with fast lock As per setting 010 but with improved response to changes in frequency offset when not close to lock 111b Second order with fast lock As per setting 011 but with improved response to changes in frequency offset when not close to lock 15 14 LOS Loss of signal Enables loss of signal detection with 2 selectable thresholds 00b Disabled Loss of signal detection disabled 01b High threshold Loss of signal detection threshold in the range 85 to 195MVqipp This setting is suitable for Infiniband 10b Low threshold Loss of signal detection threshold in the range 65 to 175mVatpp This setting is suitable for PCI E and S ATA 11b Reserved 13 12 ALIGN Symbol alignment Enables internal or external symbol alignment 00b Alignment disabled No symbol alignment will be performed while this setting is selected or when switching to this selection from another 01b Comma alignment enabled Symbol alignment will be performed whenever a misaligned comma symbol is received
100. run 0 The SOFT bit takes effect Free run Peripheral ignores the emulation suspend signal and functions normally SPRUE13A September 2006 112 Serial RapidlO SRIO Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 4 Peripheral Settings Control Register PER_SET_CNTL The peripheral settings control register PER_SET_CNTL is shown in Figure 65 and described in Table 43 For additional programming information see Section 2 3 12 Figure 65 Peripheral Settings Control Register PER_SET_CNTL Address Offset 0020h 31 27 26 25 24 SW_MEM_SLEEP_ BOOT Reserved OVERRIDE LOOPBACK COMPLETE R 0 RIW 1 R W 0 R W 0 23 21 20 18 17 16 Reserved TX_PRI2 WM TX PR WM R 0 R W 01h R W 02h 15 14 12 11 9 8 TX_PRI1_WM TX_PRIO_WM CBA TRANS PRI 1X_MODE R W 02h R W 03h R W 0 R W 0 7 4 3 2 1 0 PRESCALER SELECT ENPLL4 ENPLL3 ENPLL2 ENPLL1 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 43 Peripheral Settings Control Register PER_SET_CNTL Field Descriptions Bit Field Value Description 31 27 Reserved 00000b These read only bits return Os when read 26 SW_MEM_SLEEP_OVERRIDE Software memory sleep override 0 Memories are put in sleep mode while in shutdown Memories are not put in sleep mode while in shutdown 25 LOOPBACK Loopback mode 0 Normal operation Loop back
101. sent The interrupt approach to the messaging protocol is somewhat different Since the source device is unaware of the data s physical location in the destination device and since each messaging packet contains size and segment information the peripheral can automatically generate the interrupt after it has successfully received all packet segments comprising the complete message This DMA interface uses the Communications Port Programming Interface CPPI This interface is a link listed approach versus a circular buffer approach Data buffer descriptors which contain information such as start of Packet SOP end of packet EOP end of queue EOQ and packet length are built from the RapidlO header fields The data buffer descriptors also contain the address of the corresponding data buffer as assigned by the receive device The data buffer descriptors are then link listed together as multiple packets are received Interrupts are generated by the peripheral after all segments of the messages are received and successfully transferred through the DMA bus with the write with response commands Interrupt pacing is also implemented at the peripheral level to manage the interrupt rate as described in Section 4 7 Error handling on the RapidlO link is handled by the peripheral and as such does not require the intervention of software for recovery This includes CRC errors due to bit rate errors that may cause erroneous or invalid operations The excepti
102. status registers 71 enable bit s for access to read only registers during boot loading 113 for adaptive equalizer 125 for entire SRIO peripheral 116 for fixed phase transmit clocking 128 for flow control 112 for logical blocks 119 for port idle error checking 231 for port illegal transfer error reporting 237 for port multicast event interrupt 231 for portn 207 for port reset interrupt 232 for port self reset interrupt 231 for port write error reporting 231 for port write in interrupt 232 for SERDES PLLs 115 131 for SERDES receivers 126 for SERDES transmitters 129 enable input only for portn 207 enable multicast event participation for portn 207 enable output only for portn 207 enable status bit s for entire SRIO peripheral 117 for logical blocks O through 8 117 120 endianness 68 EN field of BLKn_EN 119 EN field of GBL_EN 116 ENFTP field of SERDES_CFGTXn_CNTL 128 ENPLL1 field of PER_SET_CNTL 113 SPRUE13A September 2006 Submit Documentation Feedback ENPLL2 field of PER_SET_CNTL 113 ENPLL3 field of PER_SET_CNTL 113 ENPLL4 field of PER_SET_CNTL 113 ENPLL field of SERDES_CFGn_CNTL 130 ENRX field of SERDES_CFGRXn_CNTL 125 ENTX field of SERDES_CFGTXn_CNTL 128 eop field of RX buffer descriptor 47 eop field of TX buffer descriptor 52 eoq field of RX buffer descriptor 47 eoq field of TX buffer descriptor 52 EQ field of SERDES_CFGRXn_CNTL 125 equalizer control field 125 ERR_DET 210 ERR_EN 212 ERR_MSG
103. the InfiniBand Trade Association Physical Layer 1x 4x LP Serial Specification Currently there are two physical layer specifications recognized by the RapidlO Trade Association 8 16 LP LVDS and 1x 4x LP Serial The 8 16 LP LVDS specification is a point to point synchronous clock sourcing DDR interface The 1x 4x LP Serial specification is a point to point AC coupled clock recovery interface The two physical layer specifications are not compatible SRIO complies with the 1x 4x LP Serial specification The serializer deserializer SERDES technology in SRIO also aligns with that specification The RapidlO Physical Layer 1x 4x LP Serial Specification currently covers three frequency points 1 25 2 5 and 3 125 Gbps This defines the total bandwidth of each differential pair of I O signals An 8 bit 10 bit encoding scheme ensures ample data transitions for the clock recovery circuits Due to the 8 bit 10 bit encoding overhead the effective data bandwidth per differential pair is 1 0 2 0 and 2 5 Gbps respectively Serial RapidlO only specifies these rates for both the 1x and 4x ports A 1x port is defined as 1 TX and 1 RX differential pair A 4x port is a combination of four of these pairs This document describes a 4x RapidlO port that can also be configured as four 1x ports thus providing a scalable interface capable of supporting a data bandwidth of 1 to 10 Gbps Figure 3 shows how to interface two 1x devices and two 4x devices Each positi
104. to avoid large parallel searches of a centralized congested route table for each outgoing packet request The congested route table requirements and subsequent searches would be overwhelming if each possible DESTID and PRIORITY combination had its own entry To implement a more basic scheme the following assumptions have been made e A small number of flows constitute the majority of traffic and these flows are most likely to cause congestion e HOL blocking is undesired but allowable for TX CPPI queues e Flow control will be based on DESTID only regardless of PRIORITY The congested route table is therefore more static in nature Instead of dynamically updating a table with each CCP s flow information as it arrives a small finite entry table is set up and configured by software to reflect the more critical flows it is using Only these flows have a discrete table entry A 16 entry table reflects 15 critical flows leaving the sixteenth entry for general other flows which are categorized together Figure 27 and Table 24 summarize the DESTID table entries that are programmable by the CPU through dedicated flow control registers A 3 bit hardware counter is implemented for table entries 0 through 14 to maintain a count of Xoff CCPs for that flow The other flows table entry counts Xoff CCPs for all flows other than the discrete entries The counter for this table entry has 5 bits All outgoing flows with non zero Xoff counts are disabled The count
105. with 1x operation 75 multiply field for SERDES PLL 131 N next_descriptor_pointer field of RX buffer descriptor 47 next_descriptor_pointer field of TX buffer descriptor 52 next expected acknowledge ID field 202 next transmitted acknowledge ID field 202 node ID field to compare to incoming destination ID 122 to supply outgoing source ID 121 NON_OUTSTANDING_ACKID_EN field of SPn_RATE_EN 221 NON_OUTSTANDING_ACKID field of SPn_ERR_DET 219 non posted WRITE operations during direct I O transmission 41 normal mode selection for portn 237 notational conventions 14 NREAD packet Ftype and Ttype 25 number of data bytes field for LSUn 158 Number of Msgs fields of TX_QUEUE_CNTLn 174 NWRITE_R packet Ftype and Ttype 25 NWRITE packet Ftype and Ttype 25 O OK status bit for ports 205 operating rate field for SERDES receiver 126 for SERDES transmitter 128 operation sequence for SRIO packets 22 OUT_BOUND_ PORT field of PF_8B_CNTL 124 SPRUE13A September 2006 Submit Documentation Feedback OUTBOUND_ACKID field of SPn_ACKID_STAT 202 outbound credit 75 outbound port number for packet forwarding 124 out of order reception of message packets 49 out of order responses during message passing TX operation 58 OUTPORTID field of LSUn_REG4 159 OUTPUT_DEGRD_ENC field of SPn_ERR_STAT 203 OUTPUT_ERROR_ENC field of SPn_ERR_STAT 203 OUTPUT_ERROR_STP field of SPn_ERR_STAT 203 OUTPUT_FLD_ENC field of SPn_ERR_STAT 203 OUTPUT_PKT_DROP field of SPn_ER
106. 0 only after all segment responses are received or alternatively if a response timeout occurs Timeouts and response evaluation have high priority in the state machine since they are the only means to release TX packet resources The CC is set in the buffer descriptor to indicate the response status to the CPU If there is a RETRY response the TX CPPI module will immediately retry the packet before continuing to the next queue in the round robin loop as long as the RETRY_COUNT is not exceeded Once this limit is exceeded the buffer can be released back to CPU control with the appropriate CC set Retry of a message segment does not imply retrying a whole message Only segments for which a RETRY response is received should be re transmitted This will involve calculating the correct starting point within the TX data buffer based on the failed segment number and message length To achieve respectable performance the peripheral must not wait for a message segment response before sending out the next packet Since RapidlO allows for out of order responses the TX CPPI hardware must support this functionality As responses are received the hardware updates the corresponding TX buffer descriptor to reflect the status However if the response is out of order the hardware does not update the CP or set the corresponding interrupt Only after all preceding outstanding message responses are received will the CP and interrupt be updated This ensures that a con
107. 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n Value after reset 90 Table 36 Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR Bit Associated LSU Interrupt Condition 31 LSU4 Packet not sent due to unavailable outbound credit at given priority 30 LSU4 au Doorbell response received or Atomic test and swap was not allowed semaphore in use 29 LSU4 Transaction was not sent due to DMA data transfer error 28 LSU4 Transaction timeout occurred 27 LSU4 Transaction was not sent due to unsupported transaction type or invalid field encoding 26 LSU4 Transaction was not sent due to Xoff condition 25 LSU4 Non posted transaction received ERROR response or error in response payload 24 LSU4 Transaction complete No errors posted non posted 1 23 LSU3 Packet not sent due to unavailable outbound credit at given priority 22 LSU3 E Doorbell response received or Atomic test and swap was not allowed semaphore in use 21 LSU3 Transaction was not sent due to DMA data transfer error 20 LSU3 Transaction timeout occurred 19 LSU3 Transaction was not sent due to unsupported transaction type or invalid field encoding 18 LSU3 Transaction was not sent due to Xoff condition
108. 0 and described in Table 153 Figure 140 Logical Transport Layer High Address Capture CSR H_ADDR_CAPT Address Offset 2010h 31 0 ADDRESS _63_32 R 00000000h LEGEND R Read only n Value after reset Table 153 Logical Transport Layer High Address Capture CSR H_ADDR_CAPT Field Descriptions Bit Field Value Description 31 0 ADDRESS_63_32 00000000h to FFFFFFFFh Most significant 32 bits of the address associated with the error only valid for devices supporting 66 bit and 50 bit addresses 214 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 78 Logical Transport Layer Address Capture CSR ADDR_CAPT The logical transport layer address capture CSR ADDR_CAPT is shown in Figure 141 and described in Table 154 Figure 141 Logical Transport Layer Address Capture CSR ADDR_CAPT Address Offset 2014h 31 ue ADDRESS _31_3 R 0000h 15 3 2 1 0 ADDRESS _31_3 Reserved XAMSBS R 0000h HO R 00 LEGEND R W Read Write R Read only n Value after reset Table 154 Logical Transport Layer Address Capture CSR ADDR_CAPT Field Descriptions Bit Field Value Description 31 3 ADDRESS_31_3 00000000h Least significant 29 bits of the address associated with the error to 1FFFFFFFh 2 Reserved 0 This read only bit returns 0 when read 1 0 XAMSBS 00b 1
109. 0 datapath Port 1 datapath Port 2 datapath Port 3 datapath lt lt lt lt _ lt lt lt lt _ Reset of the SERDES macros is handled independently of the registers discussed in this section The SERDES can be configured to shutdown unused links or fully shutdown SERDES TX and RX channels may be enabled disabled by writing to bit 0 of the SERDES_CFGTXn_CNTL and SERDES_CFGRXn_CNTL registers The PLL and remaining SERDES functional blocks can be controlled by writing to the ENPLL signal in the SERDES_CFGO_CNTL register This bit will drive the SERDES signal input which will gate the reference clock to these blocks internally This reference clock is sourced from a device pin specifically for the SERDES and is not derived from the CPU clock thus it resets asynchronously ENPLL will disable all SERDES high speed output clocks Since these clocks are distributed to all the links ENPLL should only be used to completely shutdown the peripheral It should be noted that shutdown of SERDES links in between normal packet transmissions is not permissible for two reasons First the serial RapidlO sends idle packets between data packets to maintain synchronization and lane alignment Without this mechanism the RapidlO RX logic can be mis aligned for both 1X and 4X ports Second the lock time of the SERDES PLL would need to reoccur which would slow down the operation When the SERDES ENTX signal
110. 010b 6x 00011b Reserved 00100b 8x 00101b 10x 00110b 12x 00111b 12 5x 01000b 15x 01001b 20x 01010b 25x 01011b Reserved 01100b Reserved 01111b Reserved 1xxxxb Reserved 0 ENPLL Enable PLL 0 PLL disabled 1 PLL enabled Based on the MPY value the line rate versus PLL output clock frequency can be calculated This is summarized in Table 6 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 29 d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 6 Line Rate versus PLL Output Clock Frequency Rate Line Rate PLL Output Frequency RATESCALE Full x Gbps 0 5x GHz 0 5 Half x Gbps x GHz 1 Quarter x Gbps 2x GHz 2 RIOCLK and RIOCLKgreg LINERATE x RATESCALE MPY The rate is defined by the RATE bits of the SERDES_CFGRXn_CNTL register and the SERDES_CFGTXn_CNTL register respectively The primary operating frequency of the SERDES macro is determined by the reference clock frequency and PLL multiplication factor However to support lower frequency applications each receiver and transmitter can also be configured to operate at a half or quarter of this rate via the RATE bits of the SERDES_CFGRXn_CNTL and SERDES_CFGTXn_CNTL registers as described in Table 7 Table 7 Effect of the RATE Bits RATE Description 00b Full rate Two data samples taken per PLL output clock cycle 01b Half rate One data sample taken per PLL output clock cycle 10b Quarter rate
111. 0938h FLOW_CNTL15 093Ch Figure 114 Flow Control Table Entry Register n FLOW_CNTLn 31 18 17 16 Reserved TT R 0 R W 01 15 a FLOW_CNTL_ID R W 0000h LEGEND R W Read Write R Read only n Value after reset Table 122 Flow Control Table Entry Register n FLOW_CNTLn Field Descriptions Bit Field Value Description 31 18 Reserved 0 These read only bits return Os when read 17 16 TT Transfer type for flow n 00b 8 bit destination IDs 01b 16 bit destination IDs 1xb Reserved 15 0 FLOW_CNTL_ID 0000h FFFFh Destination ID for flow n When 8 bit destination IDs are used TT 00b the 8 MSBs of this field are don t care bits SPRUE13A September 2006 Serial RapidlO SRIO 181 Submit Documentation Feedback SRIO Registers 5 52 Device Identity CAR DEV_ID The device identity CAR DEV_ID is shown in Figure 115 and described in Table 123 Writes have no effect to this register The values are hard coded and will not change from their reset state Figure 115 Device Identity CAR DEV_ID Address Offset 1000h d TEXAS INSTRUMENTS www ti com 16 15 31 DEVICEIDENTITY DEVICE_VENDORIDENTITY R 0000h LEGEND R Read only n Value after reset Table 123 Device Identity CAR DEV_ID Field Descriptions R 0030h Bit Field Value Description 31 16 DEVICEIDENTITY 0000h Identifies the type of device Vendor specific 15 0
112. 1 Transaction was not sent due to DMA data transfer error 4 LSU1 Transaction timeout occurred 3 LSU1 Transaction was not sent due to unsupported transaction type or invalid field encoding 2 LSU1 Transaction was not sent due to Xoff condition 1 LSU1 Non posted transaction received ERROR response or error in response payload 0 LSU1 Transaction complete No errors posted non posted 4 3 4 Error Reset and Special Event Interrupt Condition Status and Clear Registers The ICSR and the ICCR for the SRIO ports are shown in Figure 53 As described in Table 37 each of the nonreserved status and clear bits corresponds to a particular interrupt condition in one or more of the SRIO ports The ICS bits of ERR_RST_EVNT_ICSR indicate the occurrence of the conditions The ICC bits of ERR_RST_EVNT_ICCR are used to clear the corresponding ICS bits Figure 53 Error Reset and Special Event Interrupt Condition Status and Clear Registers Error Reset and Special Event Interrupt Condition Status Register ERR_RST_EVNT_ICSR Address Offset 0270h 31 17 16 Reserved ICS16 HO HO 15 12 11 10 9 8 7 3 2 1 0 Reserved ICS11 ICS10 ICS9 ICS8 Reserved ICS2 ICS1 ICSO R 0 HO HO HO HO HO HO HO HO Error Reset and Special Event Interrupt Condition Clear Register ERR_RST_EVNT_ICCR Address Offset 0278h 31 17 16 Reserved ICC16 R 0 WO 15 12 11 10 9 8 7 3 2 1 0 Reserved ICC11
113. 134 Port Local AckID Status CSR n SPn_ACKID_STAT 31 29 28 24 23 16 Reserved INBOUND_ACKID Reserved HO R W 0 HO 15 13 12 8 7 3 4 0 Reserved OUTSTANDING_ACKID Reserved OUTBOUND_ACKID HO R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 145 Port Local AckID Status CSR n SPn_ACKID_STAT Field Descriptions Bit Field Value Description 31 29 Reserved 0 These read only bits return Os when read 28 24 INBOUND_ACKID 00000b 11111b Input port next expected ackID value 23 13 Reserved 0 These read only bits return Os when read 12 8 OUTSTANDING_ACKID 00000b 11111b Output port unacknowledged acklD status Next expected acknowledge control symbol ackID field that indicates the ackID value expected in the next received acknowledge control symbol 7 5 Reserved 0 These read only bits return Os when read 4 0 OUTBOUND_ACKID 00000b 11111b Output port next transmitted ackID value Software writing this value can force retransmission of outstanding unacknowledged packets in order to manually implement error recovery 202 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 72 Port Error and Status CSR n SPn_ERR_STAT Each of the four ports is supported by a register of this type see Table 146 The port error and status CSR n SPn_ERR_STAT is shown in Figure 135 and
114. 143 Logical Transport Layer Control Capture CSR CTRL_CAPT Address Offset 201Ch 31 28 27 24 23 16 FTYPE TTYPE MSGINFO R Oh R Oh R 00h 15 o IMP_SPECIFIC R 0000h LEGEND R Read only n Value after reset Table 156 Logical Transport Layer Control Capture CSR CTRL_CAPT Field Descriptions Bit Field Value Description 31 28 FTYPE Oh Fh Format type associated with the error 27 24 TTYPE Oh Fh Transaction type associated with the error 23 16 MSGINFO 00h FFh Letter mailbox and message segment for the last message request received for the mailbox that had an error message errors only 15 0 IMP_SPECIFIC 0000h FFFFh Implementation specific information associated with the error SPRUE13A September 2006 Serial RapidlO SRIO 217 Submit Documentation Feedback SRIO Registers 5 81 Port Write Target Device ID CSR PW_TGT_ID The port write target device ID CSR PW_TGT_ID is shown in Figure 144 and described in Table 157 For additional programming information see Section 2 3 5 da TEXAS INSTRUMENTS www ti com Figure 144 Port Write Target Device ID CSR PW_TGT_ID Address Offset 2028h 31 24 23 16 DEVICEID_MSB DEVICEID R W 00h R W 00h 15 0 Reserved R 0000h LEGEND R W Read Write R Read only n Value after reset Table 157 Port Write Target Device ID CSR PW_TGT_ID Field Descriptions Bit Field Value Description 31 24 DE
115. 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map14 TX_Queue_Map14 TX_QUEUE_CNTL3 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map15 TX_Queue_Map15 TX_QUEUE_CNTL3 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map0 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 50 Mailbox to Queue Mapping Registers RXU_MAP_Ln and RXU_MAP_Hn Messages addressed to any of the 64 mailbox locations can be received on any of the RapidlO ports simultaneously Packets are handled sequentially in order of receipt A block of 32 mappers directs the inbound messages to the appropriate RX queues After a device reset software must configure each of the mappers to map incoming messages with selected mailbox and letter numbers to the desired queue For a given mapper n a pair of mailbox to queue
116. 17 LSU3 Non posted transaction received ERROR response or error in response payload 16 LSU3 Transaction complete No errors posted non posted 15 LSU2 Packet not sent due to unavailable outbound credit at given priority 14 LSU2 EE Doorbell response received or Atomic test and swap was not allowed semaphore in use 13 LSU2 Transaction was not sent due to DMA data transfer error 12 LSU2 Transaction timeout occurred 11 LSU2 Transaction was not sent due to unsupported transaction type or invalid field encoding 10 LSU2 Transaction was not sent due to Xoff condition 9 LSU2 Non posted transaction received ERROR response or error in response payload 8 LSU2 Transaction complete No errors posted non posted 1 7 LSU1 Packet not sent due to unavailable outbound credit at given priority Il Enable for this interrupt is ultimately controlled by the Interrupt Req register bit of LSUn_REG4 This allows enabling disabling on a per request basis For optimum LSU performance interrupt pacing should not be used on the LSU interrupts Section 4 7 describes interrupt pacing Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Interrupt Conditions Table 36 Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR continued Bit Associated LSU Interrupt Condition 6 LSU1 et Doorbell response received or Atomic test and swap was not allowed semaphore in use 5 LSU
117. 18h FLOW_CNTL6 Flow Control Table Entry Register 6 Section 5 51 091Ch FLOW_CNTL7 Flow Control Table Entry Register 7 Section 5 51 0920h FLOW_CNTL8 Flow Control Table Entry Register 8 Section 5 51 0924h FLOW_CNTL9 Flow Control Table Entry Register 9 Section 5 51 0928h FLOW_CNTL10 Flow Control Table Entry Register 10 Section 5 51 092Ch FLOW_CNTL11 Flow Control Table Entry Register 11 Section 5 51 0930h FLOW_CNTL12 Flow Control Table Entry Register 12 Section 5 51 0934h FLOW_CNTL13 Flow Control Table Entry Register 13 Section 5 51 0938h FLOW_CNTL14 Flow Control Table Entry Register 14 Section 5 51 093Ch FLOW_CNTL15 Flow Control Table Entry Register 15 Section 5 51 1000h DEV_ID Device Identity CAR Section 5 52 1004h DEV_INFO Device Information CAR Section 5 53 1008h ASBLY_ID Assembly Identity CAR Section 5 54 100Ch ASBLY_INFO Assembly Information CAR Section 5 55 1010h PE_FEAT Processing Element Features CAR Section 5 56 1018h SRC_OP Source Operations CAR Section 5 57 101Ch DEST_OP Destination Operations CAR Section 5 58 104Ch PE_LL CTL Processing Element Logical Layer Control CSR Section 5 59 1058h LCL_CFG_HBAR Local Configuration Space Base Address 0 CSR Section 5 60 105Ch LCL_CFG_BAR Local Configuration Space Base Address 1 CSR Section 5 61 1060h BASE_ID Base Device ID CSR Section 5 62 1068h HOST_BASE_ID_LOCK Host Base Device ID Lock CSR Section 5 63 106Ch COMP_TAG Component Tag CSR Section 5 64 1100h SP_MB_ HEAD 1x 4x
118. 1b Extended address bits of the address associated with the error SPRUE13A September 2006 Serial RapidlO SRIO 215 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 79 Logical Transport Layer Device ID Capture CSR ID_CAPT The logical transport layer device ID capture CSR ID_CAPT is shown in Figure 142 and described in Table 155 Figure 142 Logical Transport Layer Device ID Capture CSR ID_CAPT Address Offset 2018h 31 24 23 16 MSB_DESTID DESTID R 00h R 00h 15 87 0 MSB_SOURCEID SOURCEID R 00h R 00h LEGEND R Read only n Value after reset Table 155 Logical Transport Layer Device ID Capture CSR ID_CAPT Field Descriptions Bit Field Value Description 31 24 MSB_DESTID 00h FFh Most significant byte of the destinationID associated with the error large transport systems only 23 16 DESTID 00h FFh The destinationID associated with the error 15 8 MSB_SOURCEID 00h FFh Most significant byte of the source ID associated with the error large transport systems only 7 0 SOURCEID 00h FFh The sourcelD associated with the error 216 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 80 Logical Transport Layer Control Capture CSR CTRL_CAPT The logical transport layer control capture CSR CTRL_CAPT is shown in Figure 143 and described in Table 156 Figure
119. 2 These interrupt condition registers are used when the SRIO peripheral transmits direct I O packets As described in Table 36 each of the status and clear bits corresponds to a particular type of transaction interrupt condition for a particular LSU The ICS bits of LSU_ICSR indicate the occurrence of the conditions The ICC bits of LSU_ICCR are used to clear the corresponding ICS bits SPRUE13A September 2006 Serial RapidlO SRIO 89 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com Interrupt Conditions Figure 52 LSU Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status Register LSU_ICSR Address Offset 0260h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16 HO HO HO HO HO HO HO HO HO HO HO HO HO HO HO HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO HO HO HO R 0 HO HO HO HO HO HO HO R 0 HO HO HO HO LSU Interrupt Condition Clear Register LSU_ICCR Address Offset 0268h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ICC31 ICC30 ICC29 ICC28 ICC27 ICC26 ICC25 ICC24 ICC23 ICC22 ICC21 ICC20 ICC19 ICC18 ICC17 ICC16 W 0 W 0 W
120. 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 RX CPPI Interrupt Condition Routing Register 2 RX_CPPI_ICRR2 Address Offset 02C4h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset 94 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TX CPPI Interrupt Condition Routing Register TX_CPPI_ICRR Address Offset 02D0h 31 Interrupt Conditions Figure 56 TX CPPI Interrupt Condition Routing Registers 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 TX CPPI Interrupt Condition Routing Register 2 TX_CPPI_ICRR2 Address Offset 02D4h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset 4 4 1 2 LSU Interrupt Condition Routing Registers Figure 57 shows the ICRRs for the LSU interrupt requests These registers route LSU interrupt requests to interrupt destinations For example if ICS4 1 in LSU_ICSR and
121. 24 definition 16 in Load Store module data flow diagram 39 specifications 18 Physical Layer 1x 4x LP Serial specification 18 physical layer buffers in packet transmission discussion 75 Index 249 SRIO Registers in SRIO component block diagram 26 PID register 111 pins differential signals 25 PKT_RESP_TIMEOUT_ENABLE field of ERR_EN 212 PKT_RSPNS_TIMEOUT field of ERR_DET 210 PKT_UNEXPECTED_ACKID_EN field of SPn_RATE_EN 221 PKT_UNEXPECTED_ACKID field of SPn_ERR_DET 219 PLL block for SERDES 21 28 PLL enable bit 131 PLL multiply field for SERDES macro 131 PLL output clock frequency versus line rate 29 pointer to the next block in the data structure 196 polarity inversion bit for RIORX and RIORX reception 126 for RIOTX and RIOTX transmission 128 port 0 enable status bit 117 port 1 enable status bits 117 port 2 enable status bits 117 port 3 enable status bits 117 PORT_DISABLE field of SPn_CTL 206 PORT_ERROR field of SPn_ERR_STAT 203 PORT_ID field of SPn_RST_OPT 235 port_id field of TX buffer descriptor 52 PORT_LOCKOUT field of SPn_CTL 206 PORT_OK field of SPn_ERR_STAT 203 PORT_TYPE field of SPn_CTL 206 PORT_UNINITIALIZED field of SPn_ERR_STAT 203 PORT_WIDTH_OVERRIDE field of SPn_CTL 206 PORT_WIDTH field of SPn_CTL 206 PORT_WRITE_PND field of SPn_ERR_STAT 203 PORT_WRITE field of DEST_OP 189 PORT_WRITE field of SRC_OP 188 port attributes error capture CSRO 223 port control CSR 206 port control independent register 236
122. 3 15 and and Section 2 3 15 3 da TEXAS INSTRUMENTS www ti com Table 54 PF_8B_CNTL Registers Register Address Offset PF_8B_CNTLO 0094h PF_8B_CNTL1 009Ch PF_8B_CNTL2 00A4h PF_8B_CNTL3 00ACh Figure 73 Packet Forwarding Register n for 8 Bit Device IDs PF_8B_CNTLn 31 18 17 16 OUT BOUND Reserved PORT HO R W 3 15 8 8BIT_DEVID_UP_BOUND R W FFh 7 0 8BIT_DEVID_LOW _BOUND LEGEND R W Read Write R Read only n Value after reset R W FFh Table 55 Packet Forwarding Register n for 8 Bit DevicelDs PF_8B_CNTLn Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reserved 17 16 OUT_BOUND_PORT 0 3 Output port number for packets whose DestID falls within the 8 bit or 16 bit range for this table entry 15 8 8BIT_DEVID_UP_BOUND 00h FFh Upper 8 bit DevicelD boundary DestID above this range cannot use the table entry 7 0 8BIT_DEVID_LOW_BOUND 00h FFh Lower 8 bit DevicelD boundary DestID lower than this number cannot use the table entry 124 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 13 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL There are four of these registers to support four ports see The general form for a SERDES receive channel configuration register is summarized by Figure 74 and Table 57 See Section 2 3 2 2 fora
123. 3Ch Bit Name Description 31 0 TX Queue Head Descriptor Pointer TX Queue Head Descriptor Pointer This field is the DSP core memory address for the first buffer descriptor in the transmit queue This field is written by the DSP core to initiate queue transmit operations and is zeroed by the port when all packets in the queue have been transmitted An error condition results if the DSP core writes this field when the current field value is nonzero The address must be 32 bit word aligned SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 51 SRIO Functional Description da TEXAS INSTRUMENTS www ti com Table 20 TX DMA State Completion Pointer CP Address Offset 58h 5BCh Bit Name Description 31 0 TX Queue Completion Pointer TX Queue Completion Pointer This field is the DSP core memory address for the transmit queue completion pointer This register is written by the DSP core with the buffer descriptor address for the last buffer processed by the DSP core during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Word Figure 22 TX Buffer Descriptor Fields Bit Fields Pi es me eo Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 14 10 9 8 7 6 5 4 3 2 1 Jo next_descriptor_pointer buffer_pointer 0 Em OD 3 SO OS OO am OD c
124. 4 LSBs 4 bit trans field for packet types 2 5 and 8 OutPortID Not available in RapidlO header Indicates the output port number for the packet to be transmitted from Specified by the CPU along with NodelD Drbll Info RapidlO doorbell info field for type 10 packets see Table 23 Hop Count RapidlO hop_count field specified for Type 8 Maintenance packets Interrupt Req Not available in RapidlO header CPU controlled request bit used for interrupt generation Typically used in conjunction with non posted commands to alert the CPU when the requested data status is present 0 An interrupt is not requested upon completion of command 1 An interrupt is requested upon completion of command Table 15 LSU Status Register Fields LSU Register Field Function BSY Indicates status of the command registers 0 Command registers are available writable for next set of transfer descriptors 1 Command registers are busy with current transfer Completion Code Indicates the status of the pending command 000b Transaction complete no errors Posted Non posted 001b Transaction timeout occurred on Non posted transaction 010b Transaction complete packet not sent due to flow control blockade Xoff 011b Transaction complete non posted response packet type 8 and 13 contained ERROR status or response payload length was in error 100b Transaction complete packet not sent due to unsupported transaction type
125. 4h 2 cece cece cece ence nennen nun nun n nn nnn nn nn nen 74 41 Bootload Operation E 80 42 Packet Forwarding Register n for 16 Bit Device IDs PF_16B_CNTLn Offsets 0x0090 0x0098 0x00A0 OXOOAB aaa a a en 81 43 Packet Forwarding Register n for 8 Bit Device IDs PF_8B_CNTLn Offsets 0x0094 0x009C 0x00A4 dAn 82 44 Logical Transport Layer Error Detect CSR ERR_DET cceeeeeee seen eee eeeee nun nnnnnnn nun nnnnnnn mann nennen 83 45 RapidlO DOORBELL Packet for Interrupt Ugen 85 46 Doorbell 0 Interrupt Condition Status and Clear Registers 0cceceeeeeee eee eee ee eee eee eee e eee eeeeeeeeeeeeeeaeeee 87 47 Doorbell 1 Interrupt Condition Status and Clear Registers cceceeeeeeee eee eee eee ee eens eee e eee eeeeeeeneeeaeeee 87 48 Doorbell 2 Interrupt Condition Status and Clear Registers ecceceeee eee e eee eee ee eee eeeeeeeeeeeeeeeeeeeaeeee 88 49 Doorbell 3 Interrupt Condition Status and Clear Registers csceeeeeeeeee eee eee tees eeeeee nun nen nnnn nun nnnn nen 88 List of Figures SPRUE13A September 2006 Submit Documentation Feedback 50 RX CPPI Interrupt Condition Status and Clear Hegtsiers ence eee ee ences eee eeeeeeeeeeeeeeeeeneeeeeeee 89 51 TX CPPI Interrupt Condition Status and Clear Registers eceeeeeee eee eee ee ence eeee eee eeeenee nenn nnunnnn nen 89 52 LSU Interrupt Condition Status and Clear Registers zurusssunnennannnnnnannannnnnnnnnannnunnnnnnnn nenn nennen 90 53 Error
126. 5 12 11 8 7 5 4 1 0 DE SWING CM INVPAIR RATE BUSWIDTH write 0 ENTX R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 11 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL Field Descriptions Bit Field Value Description 31 17 Reserved 0 These read only bits return Os when read 16 ENFTP 1 Enables fixed phase relationship of transmit input clock with respect to transmit output clock The only valid value for this field is 1b all other values are reserved SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 33 SRIO Functional Description da TEXAS INSTRUMENTS www ti com Table 11 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL Field Descriptions continued Bit Field Value Description 15 12 DE 0000b 1111b De emphasis Selects one of 15 output de emphasis settings from 4 76 to 71 42 De emphasis provides a means to compensate for high frequency attenuation in the attached media It causes the output amplitude to be smaller for bits which are not preceded by a transition than for bits which are See Table 12 11 9 SWING 000b 111b Output swing Selects one of 8 outputs amplitude settings between 125 and 1250MVgipp See Table 13 8 CM Common mode Adjusts the common mode to suit the termination at the attached receiver
127. 5 71 1198h SP2_ERR_STAT Port 2 Error and Status CSR Section 5 72 119Ch SP2_CTL Port 2 Control CSR Section 5 73 11A0h SP3_LM_REQ Port 3 Link Maintenance Request CSR Section 5 69 11A4h SP3_LM_RESP Port 3 Link Maintenance Response CSR Section 5 70 11A8h SP3_ACKID_STAT Port 3 Local AckID Status CSR Section 5 71 11B8h SP3_ERR_STAT Port 3 Error and Status CSR Section 5 72 11BCh SP3_CTL Port 3 Control CSR Section 5 73 2000h ERR_RPT_BH Error Reporting Block Header Section 5 74 2008h ERR_DET Logical Transport Layer Error Detect CSR Section 5 75 200Ch ERR_EN Logical Transport Layer Error Enable CSR Section 5 76 2010h H_ADDR_CAPT Logical Transport Layer High Address Capture CSR Section 5 77 2014h ADDR_CAPT Logical Transport Layer Address Capture CSR Section 5 78 2018h ID_CAPT Logical Transport Layer Device ID Capture CSR Section 5 79 201Ch CTRL_CAPT Logical Transport Layer Control Capture CSR Section 5 80 2028h PW_TGT_ID Port Write Target Device ID CSR Section 5 81 2040h SPO_ERR_DET Port 0 Error Detect CSR Section 5 82 2044h SPO_RATE_EN Port 0 Error Enable CSR Section 5 83 2048h SPO_ERR_ATTR_CAPT_DBGO Port 0 Attributes Error Capture CSR 0 Section 5 84 204Ch SPO_ERR_CAPT_DBG1 Port 0 Packet Control Symbol Error Capture CSR 1 Section 5 85 2050h SPO_ERR_CAPT_DBG2 Port 0 Packet Control Symbol Error Capture CSR 2 Section 5 86 2054h SPO_ERR_CAPT_DBG3 Port 0 Packet Control Symbol Error Capture CSR 3 Section 5 87 2058h SPO_ERR_CAPT_DBG4 Po
128. 6 format type associated with logical transport error 217 FREE field of PCR 112 free run bit 112 free run emulation mode 75 frequency points of 1x 4x LP Serial specification 18 frequency prescaler select field 114 frequency range versus MPY value 30 FTYPE field of CTRL_CAPT 217 Ftypes of SRIO packets 25 Index 245 SRIO Registers G GBL_EN 116 GBL_EN_STAT 117 global enable bit 116 global enable status bit 118 global enabling disabling of all logical blocks 71 H H_ADDR_CAPT 214 head descriptor pointer field for RX queuen 166 head descriptor pointer field for TX queue n 164 header fields doorbell operation 64 message request packet 44 hexadecimal notational convention 14 HOP_COUNT field of LSUn_REG5 160 host base device ID lock CSR 194 host device mode field 199 l ID_CAPT 216 ID_SIZE field of LSUn_REG4 159 idle error checking disable field for ports 231 ILL_TRANS_EN field of SPn_CTL_INDEP 236 ILL_TRANS_ERR field of SPn_CTL_INDEP 236 illegal transaction at LSU TXU MAU or RXU reporting enable field 212 status field 210 illegal transfer error at port n reporting enable field 237 status field 237 INBOUND_ACKID field of SPn_ACKID_STAT 202 INFO_TYPE field of SPn_ERR_ATTR_CAPT_DBGO 223 initialization example for message passing 61 initialization example for the SRIO peripheral 77 INITIALIZED_PORT_WIDTH field of SPn_CTL 206 initialized status bit for ports 205 initialized width field for port np 206 in order reception o
129. 600h 63Ch Bit Name Description 31 0 RX Queue Head RX Queue Head Descriptor Pointer This field is the memory address for the first buffer descriptor Descriptor Pointer in the channel receive queue This field is written by the DSP core to initiate queue receive operations and is zeroed by the port when all free buffers have been used An error condition results if the DSP core writes this field when the current field value is nonzero The address must be 32 bit word aligned Table 17 RX DMA State Completion Pointer CP Address Offset 680h 6BCh Bit Name Description 31 0 RX Queue RX Queue Completion Pointer This field is the memory address for the receive queue completion Completion Pointer pointer This register is written by the DSP core with the buffer descriptor address for the last buffer processed by the DSP core during interrupt processing The port uses the value written to determine if the interrupt should be deasserted If a multi segment buffer descriptor queue is not currently free and an RX port receives another multi segment message that is destined for that queue the RX CPPI sends a RETRY RESPONSE packet type 13 to the sender indicating that an internal buffering problem exists If a multi segment buffer descriptor queue is busy and there is another incoming multi segment message with the same SOURCEID MAILBOX and LETTER an ERROR response is sent This usually indicates that
130. 8 24 PAR_O Used in conjunction with stypeO encoding 23 19 PAR_1 Used in conjunction with stypeO encoding 18 16 STYPE_1 Encoding for control symbol that makes use of parameter CMD 15 13 CMD Used in conjunction with stype1 encoding to define the link maintenance commands 12 CS_EMB When set forces the outbound flow to insert control symbol into packet Used in debug mode 11 0 Reserved 0 These read only bits return Os when read 240 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS 1x 4x LP serial port maintenance block header register 196 1x 4x mode selection field for ports 231 1X_MODE field of PER_SET_SNTL 113 2 MSBs of address for LSUn 159 4x 1x mode selection field for ports 231 4x mode data path in SRIO component block diagram 26 discovery timer period field 230 8 bit 10 bit coding and decoding 21 8BIT_DEVID_LOW_BOUND field of PF_8B_CNTL 124 8BIT_DEVID_UP_BOUND field of PF_8B_CNTL 124 8 bit device IDs lower boundary for packet forwarding 124 node ID field to compare to incoming destination ID 122 node ID field to supply outgoing source ID 121 upper boundary for packet forwarding 124 8 bit node ID field to compare to incoming destination ID 122 to supply outgoing source ID 121 8BNODEID field of DEVICEID_REG1 121 8BNODEID field of DEVICEID_REG2 122 16BIT_DEVID_LOW_BOUND field of PF_16B_CNTLn 123 16BIT_DEVID_UP_BOUND field of PF_16B_CNTLn 123 16 bit device IDs lower boundar
131. 9 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset Table 78 DOORBELLn Interrupt Condition Routing Register Field Descriptions Field Value Description ICRx Interrupt condition routing Routes the interrupt request from doorbell n bit x to one of eight x 0 to 15 interrupt destinations INTDSTO INTDST7 For example if ICS6 1 in DOORBELL2_ICSR and ICR6 0010b in DOORBELL2_ICRR the interrupt request from doorbell 2 bit 6 is sent to interrupt destination 2 0000b INTDSTO 0001b INTDST1 0010b INTDST2 0011b INTDST3 0100b INTDST4 0101b INTDST5 0110b INTDST6 0111b INTDST7 1xxxb Reserved 144 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 27 RX CPPI Interrupt Condition Routing Registers RX_CPPI_ICRR and RX_CPPI_ICRR2 Figure 88 and Table 79 summarize the ICRRs for the RXU These registers route queue interrupts to interrupt destinations For example if ICS6 1 in RX_CPPI_ICSR and ICR6 0010b in RX_CPPI_ICRR the interrupt request from RX buffer descriptor queue 6 is sent to interrupt destination 2 For additional programming see Section 4 4 1 1 Figure 88 RX CPPI Interrupt Condition Routing Registers RX CPPI Interrupt Condition Routing Register RX_CPPI_ICRR Address Offset 02C
132. 93 SOFT_REC field of SPn_CTL_INDEP 236 SOFT field of PCR 112 soft stop bit 112 soft stop emulation mode 75 software memory sleep override bit 113 software requirements for message passing 60 software shutdown details 74 sop field of RX buffer descriptor 47 sop field of TX buffer descriptor 52 source address field for LSUn 157 source ID associated with logical transport error 216 source ID check or ignore field for message reception 180 SOURCEID field of ID_CAPT 216 SOURCEID field of RXU_MAP_Ln 178 source operations CAR 188 SP_GEN_CTL 199 SP_IP_DISCOVERY_TIMER 230 SP_IP_IPW_IN_CAPTn 234 SP_IP_MODE 231 SP_LT_CTL 197 SP_MB_HEAD 196 SP_MODE field of SP_IP_MODE 231 SP_RT_CTL 198 SPn_ACKID_STAT 202 SPn_CS_TX 240 SPn_CTL 206 SPn_CTL_INDEP 236 SPn_ERR_ATTR_CAPT_DBGO 223 SPRUE13A September 2006 Submit Documentation Feedback SPn_ERR_CAPT_DBG1 224 SPn_ERR_CAPT_DBG2 225 SPn_ERR_CAPT_DBG3 226 SPn_ERR_CAPT_DBG4 227 SPn_ERR_DET 219 SPn_ERR_RATE 228 SPn_ERR_STAT 203 SPn_ERR_THRESH 229 SPn_LM_REQ 200 SPn_LM_RESP 201 SPn_MULT_EVNT_CS 239 SPn_RATE_EN 221 SPn_RST_OPT 235 SPn_SILENCE_TIMER 238 src_id field of RX buffer descriptor 47 SRC_OP 188 SRIO peripheral component block diagram 26 data flow overview 21 emulation halt behavior 74 initialization example 77 packets 22 packet types 25 peripheral block diagram 21 pins differential signals 25 RapidlO features not supported 20 RapidlO features supported 19 reset and power do
133. ACh QUEUE11_RXDMA_CP Queue Receive DMA Completion Pointer Register 11 Section 5 44 O6BOh QUEUE12 RXDMA_CP Queue Receive DMA Completion Pointer Register 12 Section 5 44 06B4h QUEUE13 RXDMA_CP Queue Receive DMA Completion Pointer Register 13 Section 5 44 O6B8h QUEUE14 RXDMA_CP Queue Receive DMA Completion Pointer Register 14 Section 5 44 06BCh QUEUE15 RXDMA_CP Queue Receive DMA Completion Pointer Register 15 Section 5 44 0700h TX_QUEUE_TEAR_DOWN Transmit Queue Teardown Register Section 5 45 0704h TX_CPPI_LFLOW_MASKSO Transmit CPPI Supported Flow Mask Register 0 Section 5 46 0708h TX_CPPI_FLOW_MASKS1 Transmit CPPI Supported Flow Mask Register 1 Section 5 46 070Ch TX_CPPI_FLOW_MASKS2 Transmit CPPI Supported Flow Mask Register 2 Section 5 46 0710h TX_CPPI_FLOW_MASKS3 Transmit CPPI Supported Flow Mask Register 3 Section 5 46 0714h TX_CPPI_FLOW_MASKS4 Transmit CPPI Supported Flow Mask Register 4 Section 5 46 0718h TX_CPPI_FLOW_MASKS5 Transmit CPPI Supported Flow Mask Register 5 Section 5 46 071Ch TX_CPPI_FLOW_MASKS6 Transmit CPPI Supported Flow Mask Register 6 Section 5 46 0720h TX_CPPI_FLOW_MASKS7 Transmit CPPI Supported Flow Mask Register 7 Section 5 46 0740h RX_QUEUE_TEAR_DOWN Receive Queue Teardown Register Section 5 47 0744h RX_CPPI_CNTL Receive CPPI Control Register Section 5 48 07EOh TX_QUEUE_CNTLO Transmit CPPI Weighted Round Robin Control Register 0 Section 5 49 07E4h TX_QUEUE_CNTL1 Transmit CPPI Weighted Round Robin Contro
134. AR_DWN fields of RX_QUEUE_TEAR DOWN 172 QUEUEn_TEAR_DWN fields of TX_QUEUE_TEAR_DOWN 168 QUEUEn_TXDMA_CP 165 QUEUEn_TXDMA_HDP 164 queue n receive DMA completion pointer register 167 queue n receive DMA head descriptor pointer register 166 queue n transmit DMA completion pointer register 165 queue n transmit DMA head descriptor pointer register 164 Queue Pointer fields of TX_QUEUE_CNTLn 174 queue teardown bits for message reception 172 queue teardown bits for message transmission 168 queue transmission order 54 R RapidlO architectural hierarchy 16 external device requirements 20 features 16 features supported in SRIO peripheral 19 interconnect architecture 18 standards 20 RapidlO DEVICEID1 register 121 RapidlO DEVICEID2 register 122 RATE fields effect on data rate 30 RATE field of SERDES_CFGRXn_CNTL 125 RATE field of SERDES_CFGTXn_CNTL 128 rate select field for SERDES receiver 126 rate select field for SERDES transmitter 128 RCVD_PKT_NOT_ACCPT field of SPn_ERR_DET 219 RCVD_PKT_OVER_276B field of SPn_ERR_DET 219 RCVD_PKT_WITH_BAD_CRC field of SPn_ERR_DET 219 RCVED_PKT_NOT_ACCPT_EN field of SPn_RATE_EN 221 RCVED_PKT_OVER_276B_EN field of SPn_RATE_EN 221 RCVED_PKT_WITH_BAD_CRC_EN field of SPn_RATE_EN 221 READ field of DEST_OP 189 READ field of SRC_OP 188 SPRUE13A September 2006 Submit Documentation Feedback SRIO Registers read support for destination device 189 read support for source devic
135. AT field of GBL_LEN STAT 117 BLK6_EN_STAT field of GBL_EN_STAT 117 BLK7_EN_STAT field of GBL_EN_STAT 117 BLK8_EN_STAT field of GBL_EN_STAT 117 BLKn_EN 119 BLKn_EN_STAT 120 block 0 enable status bit 118 block 1 enable status bit 117 block 2 enable status bit 117 block 3 enable status bit 117 block 4 enable status bit 117 block 5 enable status bit 117 block 6 enable status bit 117 block 7 enable status bit 117 block 8 enable status bit 117 block diagram of SRIO components 26 block diagram of SRIO peripheral 21 block enable registers 119 block enable status registers 120 BOOT_COMPLETE field of PER_SET_CNTL 113 bootloading access to read only registers 113 configuration and operation 79 data movement 80 device wakeup afterwards 80 BRIDGE field of PE_FEAT 186 bridge present field 186 BSY field of LSUn_REG6 161 buffer_pointer field of RX buffer descriptor 47 buffer_pointer field of TX buffer descriptor 52 BUSWIDTH field of SERDES_CFGRXn_CNTL 125 BUSWIDTH field of SERDES_CFGTXn_CNTL 128 busy BSY signal of an LSU 39 busy status field for LSUn 161 242 Index BYTE_COUNT field of LSUn_REG3 158 Cc CAPTURE field of SPh_ERR_CAPT_DBG1 224 CAPTURE 1 field of SPn_ERR_CAPT_DBG2 225 CAPTURE2 field of SPn_ERR_CAPT_DBG3 226 CAPTURES field of SPn_ERR_CAPT_DBG4 227 CAPTURE_VALID_INFO field of SPn_ERR_ATTR_CAPT_DBGO 223 CBA_TRANS_PRI field of PER_SET_CNTL 113 cc field of RX buffer descriptor 47 cc field of TX buffer descriptor 52 CDR field of
136. B0B1B2B3 C0C1C2C3D0D1D2D3 Double word0 Double word1 Big gl Little Endian Byte Byte Byte Byte address 0 address 3 address 3 address 0 L2 offset 0x0 A0 A1 A2 A3 L2 offset 0x0 A3 A2 A1 AO L2 offset 0x4 BO B1 B2 B3 L2 offset 0x4 B3 B2 B1 BO L2 offset 0x8 CO C1 C2 C3 L2 offset 0x8 C3 C2 C1 CO L2 offset 0xC DO D1 D2 D3 L2 offset 0xC D3 D2 D1 DO SPRUE13A September 2006 Serial RapidlO SRIO 69 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description 2 3 10 70 Reset and Power Down The RapidlO peripheral allows independent software controlled shutdown for the logical blocks listed in Table 26 With the exception of BLKO_EN for the memory mapped registers MMRs when the BLKn_EN signals are deasserted the clocks are gated to these blocks effectively providing a shutdown function Table 26 Reset Hierarchy Bus GBL BLKO BLK1 BLK2 BLK3 BLK4 BLK5 BLK6 BLK7 BLK8 Logical Block Reset EN EN EN EN EN _EN _EN _EN _EN _EN DMA interface y V MMRs y Reset power down control registers MMRs y Non reset power down control registers Interrupt handling V unit IHU Traffic flow logic V V Congestion y control unit CCU LSU Direct I O V V y initiator MAU Direct I O y V target TXU message V passing initiator RXU message V y passing target Port
137. CCR 141 LSU_ICRRO to LSU_ICRR3 147 SPRUE13A September 2006 Submit Documentation Feedback SRIO Registers LSU_ICSR 138 LSU congestion control flow mask register 162 LSU control register 0 155 LSU control register 1 156 LSU control register 2 157 LSU control register 3 158 LSU control register 4 159 LSU control register 5 160 LSU control register 6 161 LSU interrupt condition clear register 141 LSU interrupt condition routing registers 147 LSU interrupt condition status register 138 LSUn_FLOW_MASKS 162 LSUn_REGO 155 LSUn_REG1 156 LSUn_REG2 157 LSUn_REG3 158 LSUn_REG4 159 LSUn_REG5 160 LSUn_REG6 161 LSUs data path description 39 enable bit 119 enable status bits 117 120 handling of unavailable outbound credit 76 in Load Store module data flow diagram 39 in SRIO component block diagram 26 register introduction 35 register load timing diagram 37 register programming example 38 RX operation 42 TX operation 40 M MAILBOX_MASK field of RXU_MAP_Ln 178 mailboxes and letters 43 mailbox field of RX buffer descriptor 47 MAILBOX field of RXU_MAP_Ln 178 mailbox field of TX buffer descriptor 52 mailbox number associated with logical transport error 217 mailbox number masking 45 mailbox to queue mapping during message reception introduction 44 register descriptions 177 maintenance packets Ftypes and Ttypes 25 introduction 63 masking mailbox and letter numbers 45 master device mode field 199 MAU enable bit 119 enable status bit
138. CPPI Supported Flow Mask Register 0 TX_CPPI_FLOW_MASKS0 31 16 15 0 QUEUE1_FLOW_MASK QUEUEO_FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 1 TX_CPPI_FLOW_MASKS1 31 16 15 0 QUEUE3_FLOW_MASK QUEUE2_FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 2 TX_CPPI_FLOW_MASKS2 31 16 15 0 QUEUE5 FLOW_MASK QUEUE4 FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 3 TX_CPPI_FLOW_MASKS3 31 16 15 0 QUEUE7_FLOW_MASK QUEUE6_FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 4 TX_CPPI_FLOW_MASKS4 31 16 15 0 QUEUE9_FLOW_MASK QUEUE8_FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 5 TX_CPPI_FLOW_MASKS5 31 16 15 0 QUEUE11_FLOW_MASK QUEUE10_FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 6 TX_CPPI_FLOW_MASKS6 31 16 15 0 QUEUE13_FLOW_MASK QUEUE12_FLOW_MASK R W FFh R W FFh Transmit CPPI Supported Flow Mask Register 7 TX_CPPI_FLOW_MASKS7 31 16 15 0 QUEUE15 FLOW_MASK QUEUE14_FLOW_MASK R W FFh R W FFh LEGEND R W Read Write n Value after reset Figure 109 TX Queue n FLOW_MASK Fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FL15 FL14 FL13 FL12 FL11 FL10 FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FLO R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write n Value after reset Table 114 TX Queue n FLOW_MA
139. CSR e Doorbell 1 bit 15 bit 15 of DOORBELL1_ICSR e Doorbell 2 bit 15 bit 15 of DOORBELL2_ICSR e Doorbell 3 bit 15 bit 15 of DOORBELL3_ICSR 14 ISD14 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 14 bit 14 of DOORBELLO_ICSR e Doorbell 1 bit 14 bit 14 of DOORBELL1_ICSR e Doorbell 2 bit 14 bit 14 of DOORBELL2_ICSR e Doorbell 3 bit 14 bit 14 of DOORBELL3_ICSR 13 ISD13 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 13 bit 13 of DOORBELLO_ICSR e Doorbell 1 bit 13 bit 13 of DOORBELL1_ICSR e Doorbell 2 bit 13 bit 13 of DOORBELL2_ICSR e Doorbell 3 bit 13 bit 13 of DOORBELL3_ICSR 12 ISD12 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 12 bit 12 of DOORBELLO_ICSR e Doorbell 1 bit 12 bit 12 of DOORBELL1_ICSR e Doorbell 2 bit 12 bit 12 of DOORBELL2_ICSR e Doorbell 3 bit 12 bit 12 of DOORBELL3_ICSR 11 ISD11 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 11 bit 11 of DOORBELLO_ICSR e Doorbell 1 bit 11 bit 11 of DOORBELL1_ICSR e Doorbell 2 bit 11 bit 11 of DOORBELL2_ICSR e Doorbell 3 bit 11 bit 11 of DOORBELL3_ICSR 10 ISD10 No interrupt request routed to this bit Interru
140. DBG2 31 0 CAPTURE1 R 00000000h LEGEND R Read only n Value after reset Table 167 Port n Error Capture CSR 2 SPn_ERR_CAPT_DBG2 Field Descriptions Bit Field Value Description 31 0 CAPTURE1 00000000h Bytes 4 to 7 of the packet header that corresponds to the error to FFFFFFFFh SPRUE13A September 2006 Serial RapidlO SRIO 225 Submit Documentation Feedback SRIO Registers d TEXAS INSTRUMENTS www ti com 5 87 Port n Error Capture CSR 3 SPn_ERR_CAPT_DBG3 Each of the four ports is supported by a register of this type see Table 168 SPn_ERR_CAPT_DBGS3 is shown in Figure 150 and described in Table 169 Table 168 SPn_ERR_CAPT_DBG3 Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_CAPT_DBG3 2054h Port 0 SP1_ERR_CAPT_DBG3 2094h Port 1 SP2_ERR_CAPT_DBG3 20D4h Port 2 SP3_ERR_CAPT_DBG3 2114h Port 3 Figure 150 Port n Error Capture CSR 3 SPn_ERR_CAPT_DBG3 31 CAPTURE2 LEGEND R Read only n Value after reset R 00000000h Table 169 Port n Error Capture CSR 3 SPn_ERR_CAPT_DBG3 Field Descriptions Bit Field Value Description 31 0 CAPTURE2 00000000h Bytes 8 to 11 of the packet header that corresponds to the error to FFFFFFFFh 226 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i3 TEXAS INSTRUMENTS www ti com 5 88 Port n Error Capture CSR 4 SPn_ERR_CAPT_DB
141. DestID above this range cannot use the table entry 15 0 16BIT_DEVID_LOW_BOUND 0000h FFFFh Lower 16 bit DevicelD boundary DestID lower than this number cannot use the table entry SPRUE13A September 2006 Serial RapidlO SRIO 81 Submit Documentation Feedback SRIO Functional Description da TEXAS INSTRUMENTS www ti com Figure 43 Packet Forwarding Register n for 8 Bit Device IDs PF_8B_CNTLn Offsets 0x0094 0x009C 0x00A4 0x00AC 31 18 17 16 OUT BOUND Reserved PORT R 0 R W 3 15 8 8BIT_DEVID_UP_BOUND R W FFh 7 0 8BIT_DEVID_LOW_BOUND R W FFh LEGEND R W Read Write R Read only n Value after reset Table 33 Packet Forwarding Register n for 8 Bit DevicelDs PF_8B_CNTLn Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reserved 17 16 OUT_BOUND_PORT 0 3 Output port number for packets whose DestID falls within the 8 bit or 16 bit range for this table entry 15 8 8BIT_DEVID_UP_BOUND 00h FFh Upper 8 bit DevicelD boundary DestID above this range cannot use the table entry 7 0 8BIT_DEVID_LOW_BOUND 00h FFh Lower 8 bit DevicelD boundary DestID lower than this number cannot use the table entry 82 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Logical Transport Error Handling and Logging 3 Logical Transport Error Handling and Logging Err
142. EN_STAT Block 4 enable status Logical block 4 is the message receive unit RXU 0 Logical block 4 is in reset with its clock off 1 Logical block 4 is enabled with its clock running GBL_EN_STAT 4 BLK3_EN_STAT Block 3 enable status Logical block 3 is the message transmit unit TXU 0 Logical block 3 is in reset with its clock off 1 Logical block 3 is enabled with clock running GBL_EN_STAT 3 BLK2_EN_STAT Block 2 enable status Logical block 2 is the memory access unit MAU 0 Logical block 2 is in reset with its clock off 1 Logical block 2 is enabled with its clock running GBL_EN_STAT 2 BLK1_EN_STAT Block 1 enable status Logical block 1 is the Load Store module which is comprised of the four Load Store units LSU1 LSU2 LSU3 and LSU4 0 Logical block 1 is in reset with its clock off 1 Logical block 1 is enabled with its clock running GBL_EN_STAT 1 BLKO_EN_STAT Block 0 enable status Logical block 0 is the set of memory mapped control registers for the SRIO peripheral 0 Logical block 0 is in reset with its clock off 1 Logical block 0 is enabled with its clock running GBL_EN_STAT 0 GBL_EN_STAT Global enable status 0 The peripheral is in reset with all its clocks off 1 The peripheral is enabled with all its clocks running The 18 block specific registers are represented by Figure 34 through Figure 39 These register pairs have bits with the same functions which are described i
143. ESH Port 2 Error Rate Threshold CSR Section 5 90 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 109 SRIO Registers 110 da TEXAS INSTRUMENTS www ti com Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section 2100h SP3_ERR_DET Port 3 Error Detect CSR Section 5 82 2104h SP3_RATE_EN Port 3 Error Enable CSR Section 5 83 2108h SP3_ERR_ATTR_CAPT_DBGO Port 3 Attributes Error Capture CSR 0 Section 5 84 210Ch SP3_ERR_CAPT_DBG1 Port 3 Packet Control Symbol Error Capture CSR 1 Section 5 85 2110h SP3_ERR_CAPT_DBG2 Port 3 Packet Control Symbol Error Capture CSR 2 Section 5 86 2114h SP3_ERR_CAPT_DBG3 Port 3 Packet Control Symbol Error Capture CSR 3 Section 5 87 2118h SP3_ERR_CAPT_DBG4 Port 3 Packet Control Symbol Error Capture CSR 4 Section 5 88 2128h SP3_ERR_RATE Port 3 Error Rate CSR Section 5 89 212Ch SP3_ERR_THRESH Port 3 Error Rate Threshold CSR Section 5 90 12000h SP_IP_DISCOVERY_TIMER Port IP Discovery Timer in 4x mode Section 5 91 12004h SP_IP_MODE Port IP Mode CSR Section 5 92 12008h IP_PRESCAL Port IP Prescaler Register Section 5 93 12010h SP_IP_PW_IN_CAPTO Port Write In Capture CSR Register 0 Section 5 94 12014h SP_IP_PW_IN_CAPT1 Port Write In Capture CSR Register 1 Section 5 94 12018h SP_IP_PW_IN_CAPT2 Port Write In Capture CSR
144. E_TIMER 14308h Port 3 Figure 160 Port Silence Timer n Register SPn_SILENCE_TIMER 31 28 27 16 SILENCE_TIMER Reserved R W Bh R 0 15 Q Reserved R 0 LEGEND R W Read Write R Read only n Value after reset Table 185 Port Silence Timer n Register SPn_SILENCE_TIMER Field Descriptions Bit Field Value Description 31 28 SILENCE_TIMER Silence timer Defines the time of the port in the SILENT state 0000b 64 ns for debug 0001b 13 1 us 0010b 13 1 us x 2 26 2 us 1011b 13 1 us x 11 144 1 us default 1111b 13 1 us x 15 196 5 us 27 0 Reserved 0 These read only bits return Os when read 238 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback ii www ti com Each of the four ports is supported by a register of this type see Table 186 The port multicast event TEXAS INSTRUMENTS SRIO Registers 5 98 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS control symbol request register n SPn_MULT_EVNT_CS is shown in Figure 161 and described in Table 187 Table 186 SPn_MULT_EVNT_CS Registers and the Associated Ports Register Address Offset Associated Port SPO_MULT_EVNT_CS 1400Ch Port 0 SP1_MULT_EVNT_CS 1410Ch Port 1 SP2_MULT_EVNT_CS 1420Ch Port 2 SP3_MULT_EVNT_CS 1430Ch Port 3 Figure 161 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS 31 MULT_EVNT_CS WO
145. FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FLO R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write n Value after reset SPRUE13A September 2006 Serial RapidlO SRIO 67 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 25 Fields Within Each Flow Mask Bit Field Value Description 15 FL15 0 TX source does not support Flow 15 from table entry 1 TX source supports Flow 15 from table entry 14 FL14 0 TX source does not support Flow 14 from table entry 1 TX source supports Flow 14 from table entry 13 FL13 0 TX source does not support Flow 13 from table entry 1 TX source supports Flow 13 from table entry 12 FL12 0 TX source does not support Flow 12 from table entry 1 TX source supports Flow 12 from table entry 11 FL11 0 TX source does not support Flow 11 from table entry 1 TX source supports Flow 11 from table entry 10 FL10 0 TX source does not support Flow 10 from table entry 1 TX source supports Flow 10 from table entry 9 FL9 0 TX source does not support Flow 9 from table entry 1 TX source supports Flow 9 from table entry 8 FL8 0 TX source does not support Flow 8 from table entry 1 TX source supports Flow 8 from table entry 7 FL7 0 TX source does not support Flow 7 from table entry 1 TX source supports
146. Field Descriptions ceeeeeeeee eee eeeeeeeeeeeeeeeee 173 117 Transmit CPPI Weighted Round Robin Control Register Field Descriptions eceeeeeeeeeeeeeeeeeeeeeeee 175 118 Mailbox to Queue Mapping Registers and the Associated RX Mappers 177 119 Mailbox to Queue Mapping Register Ln RXU_MAP_Ln Field Descriptions Han nenn nn en nenn 179 120 Mailbox to Queue Mapping Register Hn RXU_MAP_Hn Field Descripotlons HR Rn nn nenn 179 121 EWEN TEE TEE ee eene 181 122 Flow Control Table Entry Register n FLOW_CNTLn Field Descriptions 0ceeeeeee seen eee ee nn nn an nn 181 123 Device Identity CAR DEV_ID Field Descriptions zuruuusunnennannnnnnnnnannnannnnnnnnnunnnnnnun nun nennen 182 124 Device Information CAR DEV_INFO Field Descriptions nun ann nun nun nannnn 183 125 Assembly Identity CAR ASBLY_ID Field Descriptions cceeeeee eee eee eee ee ee ee nun n an nn nn nun nun nennen 184 126 Assembly Information CAR ASBLY_INFO Field Descriptions c ceceee eee e scene eee eens nn nn un nun ann nn 185 127 Processing Element Features CAR PE_FEAT Field Descriptions cceeeeeeeeeeee nenn nn nun nun nennen 186 128 Source Operations CAR SRC_OP Field Descriptions ecceeee ee eee eee eee eee nese ee ease eeeee nun nennen 188 129 Destination Operations CAR DEST_OP Field Descriptions seen eee eee eee eee eeeeeeeeeeeeeneee 189 130 Processing Element Logical Layer Control CSR PE_LL_CTL Field Des
147. Figure 62 The counter reloads and SPRUE13A September 2006 Serial RapidlO SRIO 99 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Interrupt Conditions immediately starts down counting each time the CPU writes these registers When the rate control counter register is written and the counter value reaches zero note that the CPU may write zero immediately for a zero count the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the corresponding ICSR register bits are set or become set after the zero count is reached The counter remains at zero When the single pulse is generated the logic will not generate another pulse regardless of interrupt status changes until the rate control counter register is written again An interrupt rate control register INTDSTn_RATE_CNTL is implemented for each supported physical interrupt destination The device supports up to eight interrupt destinations INTDSTO INTDST7 The names of the registers and their address offsets are e INTDSTO_RATE_CNTL Address offset 0320h e INTDST1_RATE_CNTL Address offset 0324h e INTDST2_RATE_CNTL Address offset 0328h e INTDST3_RATE_CNTL Address offset 032Ch e INTDST4_RATE_CNTL Address offset 0330h e INTDST5 RATE_CNTL Address offset 0334h e INTDST6_RATE_CNTL Address offset 0338h e INTDST7_RATE_CNTL Address offset 033Ch If interrupt pacing is not desired for a particular interrupt destination the CPU
148. G4 SRIO Registers Each of the four ports is supported by a register of this type see Table 170 The port n packet control symbol error capture CSR 4 SPn_ERR_CAPT_DBG4 is shown in Figure 151 and described in Table 171 Table 170 SPn_ERR_CAPT_DBG4 Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_CAPT_DBG4 SP1_ERR_CAPT_DBG4 SP2_ERR_CAPT_DBG4 SP3_ERR_CAPT_DBG4 2058h 2098h 20D8h 2118h Port 0 Port 1 Port 2 Port 3 Figure 151 Port n Error Capture CSR 4 SPn_ERR_CAPT_DBG4 31 CAPTURE3 LEGEND R Read only n Value after reset R 00000000h Table 171 Port n Error Capture CSR 4 SPn_ERR_CAPT_DBG4 Field Descriptions Bit Field Value Description 31 0 CAPTURE3 00000000h Bytes 12 to 15 of the packet header that corresponds to the error to FFFFFFFFh SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 227 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 89 Port Error Rate CSR n SPn_ERR_RATE Each of the four ports is supported by a register of this type see Table 172 SPn_ERR_RATE is shown in Figure 152 and described in Table 173 Table 172 SPn_ERR_RATE Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_RATE 2068h Port 0 SP1_ERR_RATE 20A8h Port 1 SP2_ERR_RATE 20E8h Port 2 SP3_ERR_RATE 2128h Port 3 Figure 152 Port Error Rate CSR n SPn_ERR_RATE
149. I Control Register DX CPP ONT 173 Transmit CPPI Weighted Round Robin Control Registers TX_QUEUE_CNTL O 3 174 Mailbox to Queue Mapping Registers RXU_MAP_Ln and RX MAP Hm 177 Flow Control Table Entry Register n FL OW CNTLo eee eee eee ee ee eee eee eeeeeeeeeeeeeeeeeee 181 Device Identity CAR DEN ID p sisene aa EEN 182 Device Information CAR DEV_INFO an 183 Assembly Identity CAR ASBEY ID eege Be a ee EE 184 Assembly Information CAR ASBLY_INFO uuuesssnnsannnnnennnnnnnnnannnannunnnnnnunnunnnnnnnnnnnn nen 185 Processing Element Features CAR PE F EATI nun nnnnnennn 186 Source Operations CAR PC OP 188 Destination Operations CAR DEST_OP uzaussenennnannnnnnnnnannnannun nun nun nun nun nun nann nun nenn 189 Processing Element Logical Layer Control CSR DE UL CU 190 Local Configuration Space Base Address 0 CSR LC CEOG HBAD 191 Local Configuration Space Base Address 1 CSR LCL_CFG_BAR seeeeeeeeeeeeeeeeeeees 192 Base Device ID CSR BASE ID u 2 0a nn ae anne ciate See 193 Host Base Device ID Lock CGp HOGT BASSE ID LOCKR nn Rn nn nn nennen nn nn nn nn 194 Component Tag CSR COMP_TAG nuzauusnnennnannunnnnnnannunnnnnnnnnunnnnnnnnn nun nann nun nun nun nun nenn 195 1x 4x LP Serial Port Maintenance Block Header Register GP MD HEAID 196 Port Link Time Out Control CSR GP UTC 197 Port Response Time Out Control CSR GP HI CILLIEN 198 Port General Control CSR GP GEN CTIE EEN 199 SPRUE13A Sep
150. ION_ERROR_EN Rate counting enable for delineation errors Disable error rate counting of delineation errors Enable error rate counting of delineation errors UNSOLICITED_ACK_CNTL_SYM_EN Rate counting enable for unsolicited acknowledge control symbols Disable error rate counting of unsolicited acknowledge control symbols Enable error rate counting of unsolicited acknowledge control symbols LINK_TIMEOUT_EN Rate counting enable for link time out errors Disable error rate counting of link timeout errors Enable error rate counting of link timeout errors 222 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 84 Port n Attributes Error Capture CSR 0 SPn_ERR_ATTR_CAPT_DBGO Each of the four ports is supported by a register of this type see The port n attributes error capture CSR 0 SPn_ERR_ATTR_CAPT_DBGO is shown in Figure 147 and described in Table 163 Table 162 SPn_ERR_ATTR_CAPT_DBGO Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_ATTR_CAPT_DBGO 2048h Port 0 SP1_ERR_ATTR_CAPT_DBGO 2088h Port 1 SP2_ERR_ATTR_CAPT_DBGO 20C8h Port 2 SP3_ERR_ATTR_CAPT_DBGO 2108h Port 3 Figure 147 Port n Attributes Error Capture CSR 0 SPn_ERR_ATTR_CAPT_DBGO 31 30 29 28 24 23 INFO_TYPE Reserved ERROR_TYPE IMP_SPECIFIC R 00 R 0 R
151. IORXO RIOCLK RIOCLK 2 Output Output Output Output Input Input Input Input Input Transmit Data Differential point to point unidirectional bus Transmits packet data to a receiving device s RX pins Most significant bits in 1 port 4X device Used in 4 port 1X device Transmit Data Differential point to point unidirectional bus Transmits packet data to a receiving device s RX pins Bit used in 4 port 1x device and 1 port 4X device Transmit Data Differential point to point unidirectional bus Transmits packet data to a receiving device s RX pins Bit used in 4 port 1x device and 1 port 4X device Transmit Data Differential point to point unidirectional bus Transmits packet data to a receiving device s RX pins Bit used in 1 port 1X device 4 port 1x device and 1 port 4X device Receive Data Differential point to point unidirectional bus Receives packet data for a transmitting device s TX pins Most significant bits in 1 port 4X device Used in 4 port 1X device Receive Data Differential point to point unidirectional bus Receives packet data for a transmitting device s TX pins Bit used in 4 port 1x device and 1 port 4X device Receive Data Differential point to point unidirectional bus Receives packet data for a transmitting device s TX pins Bit used in 4 port 1x device and 1 port 4X device Receive Data Differential point to point unidirectional bus Rece
152. L2 11 8 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map10 TX_Queue_Map10 TX_QUEUE_CNTL2 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map11 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 57 da TEXAS INSTRUMENTS www ti com SRIO Functional Description 58 Table 22 Weighted Round Robin Programming Registers Address Offset 7EOh 7ECh continued Field Pair Register Bits Field Value Description TX_Queue_Map11 TX_QUEUE_CNTL2 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map12 TX_Queue_Map12 TX_QUEUE_CNTL3 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 7 4 N
153. LP_Serial Port Maintenance Block Header Section 5 65 1120h SP_LT_CTL Port Link Time Out Control CSR Section 5 66 1124h SP_RT_CTL Port Response Time Out Control CSR Section 5 67 113Ch SP_GEN_CTL Port General Control CSR Section 5 68 1140h SPO_LM_REQ Port 0 Link Maintenance Request CSR Section 5 69 1144h SPO_LM RESP Port 0 Link Maintenance Response CSR Section 5 70 1148h SPO_ACKID_STAT Port 0 Local AckID Status CSR Section 5 71 1158h SPO_ERR_STAT Port 0 Error and Status CSR Section 5 72 115Ch SPO_CTL Port 0 Control CSR Section 5 73 1160h SP1_LM_REQ Port 1 Link Maintenance Request CSR Section 5 69 1164h SP1_LM_RESP Port 1 Link Maintenance Response CSR Section 5 70 1168h SP1_ACKID_STAT Port 1 Local AckID Status CSR Section 5 71 1178h SP1_ERR_STAT Port 1 Error and Status CSR Section 5 72 108 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section 117Ch SP1_CTL Port 1 Control CSR Section 5 73 1180h SP2_LM_REQ Port 2 Link Maintenance Request CSR Section 5 69 1184h SP2_LM_RESP Port 2 Link Maintenance Response CSR Section 5 70 1188h SP2_ACKID_STAT Port 2 Local AckID Status CSR Section
154. MAU modules response timer and controllers together known as the User Application UDI could also be known as the logical physical interface No action is required to define this interface 40 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Functional Description Data leaves the shared TX buffer sequentially in order of receipt not based on the packet priority However if fabric congestion occurs priority can affect the order in which the data leaves the TX FIFOs A reordering mechanism exists here which transmits the highest priority packets first if RETRY acknowledges For posted WRITE operations which do not require a RapidlO response packet a core may submit multiple outstanding requests For instance a single core may have many streaming write packets buffered at any given time given outgoing resources In this application the control command registers can be released BSY 0 to the CPU as soon as the header info is written into the shared TX buffer If the request has been flow controlled the peripheral will set the completion code status register and appropriate interrupt bit of the ICSR The control command registers can be released after the interrupt service routine completes For non posted WRITE operations which do require a RapidlO response packet there can be only one outstanding request per core at any given time The payload data and header i
155. Mapper 17 SPRUE13A September 2006 Serial RapidlO SRIO 177 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers Table 118 Mailbox to Queue Mapping Registers and the Associated RX Mappers continued Register Address Offset Associated RX Mapper RXU_MAP_L18 0890h Mapper 18 RXU_MAP_H18 0894h Mapper 18 RXU_MAP_L19 0898h Mapper 19 RXU_MAP_H19 089Ch Mapper 19 RXU_MAP_L20 08A0h Mapper 20 RXU_MAP_H20 08A4h Mapper 20 RXU_MAP_L21 08A8h Mapper 21 RXU_MAP_H21 08ACh Mapper 21 RXU_MAP_L22 08B0h Mapper 22 RXU_MAP_H22 08B4h Mapper 22 RXU_MAP_L23 08B8h Mapper 23 RXU_MAP_H23 08BCh Mapper 23 RXU_MAP_L24 08C0h Mapper 24 RXU_MAP_H24 08C4h Mapper 24 RXU_MAP_L25 08C8h Mapper 25 RXU_MAP_H25 08CCh Mapper 25 RXU_MAP_L26 08DOh Mapper 26 RXU_MAP_H26 08D4h Mapper 26 RXU_MAP_L27 08D8h Mapper 27 RXU_MAP_H27 08DCh Mapper 27 RXU_MAP_L28 O8E0h Mapper 28 RXU_MAP_H28 08E4h Mapper 28 RXU_MAP_L29 08E8h Mapper 29 RXU_MAP_H29 08ECh Mapper 29 RXU_MAP_L30 08F0h Mapper 30 RXU_MAP_H30 08F4h Mapper 30 RXU_MAP_L31 O8F8h Mapper 31 RXU_MAP_H31 08FCh Mapper 31 178 Serial RapidIO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Figure 113 Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n RXU_MAP_L n 31 30 29 24 23 22 21 16 LETTER_MASK MAILBOX_MASK LETTER MAILBOX R W 11 R W 111111 R
156. NCRMNT PE can support an atomic increment operation 6 ATOMIC_DCRMNT PE can support an atomic decrement operation 5 ATOMIC_SET PE can support an atomic set operation 4 ATOMIC_CLEAR PE can support an atomic clear operation 3 Reserved 0 This read only bit returns 0 when read 2 PORT_WRITE PE can support a port write generation 1 0 IMPLMNT_DEFINED_1 Defined by the device implementation 188 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 58 Destination Operations CAR DEST_OP The destination operations CAR DEST_OP is shown in Figure 121 and described in Table 129 Figure 121 Destination Operations CAR DEST_OP Address Offset 101Ch 31 24 Reserved R 0 23 18 17 16 Reserved IMPLMNT_DEFINED_ 2 R 0 R 00 15 14 13 12 11 10 9 8 READ WRITE STREAM_WRITE eet eee DATA MESS DOORBELL Reserved ee R 0 R 0 R 0 HO HO HO HO R 0 7 6 5 4 3 2 1 0 INCRMNT DCRMNT ser CLEAR Reseved WANE IMPLMINT_DEFINED_1 R 0 HO R 0 R 0 R 0 R 1 R 00 LEGEND R Read only n Value after reset Table 129 Destination Operations CAR DEST_OP Field Descriptions Bit Field Value Description 31 18 Reserved 0 These read only bits return Os when read 17 16 IMPLMNT_DEFINED_2 Defined by the device implementation 15 READ PE can
157. NENNEN ENNEN NEE SNE NEEN 30 9 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL Field Descriptions 31 10 EQ Bits eebe e Bee idan idea ee See ge 33 11 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL Field Descriptions 33 12 DE Bits 0f SERDES CFGIXA MONTE ace ae EEE E EEEE E E E 34 13 SWING Bits of SERDES CFGTXN ONT Le essei susino ro Ran EENS ENEE ENEE Ne EEN a aa En a m 35 14 LSU Control Command Register Fields siriu Ei 36 15 LSU Status Register FieldS 4 4 4420 400m a a ESEN een 37 16 RX DMA State Head Descriptor Pointer HDP Address Offset GOOh G3Ch eee ee eee eens eeeeeeeee 46 17 RX DMA State Completion Pointer CP Address Offset 680h 6BCh ccs eeeeeeeee eee eeeeeeeeeeeeeeeeeee 46 18 RX Buffer Descriptor Field Description 47 19 TX DMA State Head Descriptor Pointer HDP Address Offset 500h 53Ch 24 u 4 n nennen nn an mann nn 51 20 TX DMA State Completion Pointer CP Address Offset 58h 5BCh zurusssunnennannnunnnnnannnnn nun nun nen 52 21 TX Buffer Descriptor Field Definitions e 52 22 Weighted Round Robin Programming Registers Address Offset ZEOh ECH 56 23 Examples of DOORBELL_INFO Designations See Figure 26 urauusunnennannnnnnannannnnnnannannnnn nun nun nen 64 24 Flow Control Table Entry Register n FLOW_CNTLn Field Description 67 25 Fields Within Each Flow Maek ve VegektekeeugNNNEAN NENNEN NENNEN KEN RNEN NNN AEN aa a aaa 68 26 R
158. O SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section 0504h QUEUE1_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 1 Section 5 41 0508h QUEUE2_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 2 Section 5 41 050Ch QUEUE3_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 3 Section 5 41 0510h QUEUE4 TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 4 Section 5 41 0514h QUEUE5 TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 5 Section 5 41 0518h QUEUE6_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 6 Section 5 41 051Ch QUEUE7_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 7 Section 5 41 0520h QUEUE8 TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 8 Section 5 41 0524h QUEUE9 TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 9 Section 5 41 0528h QUEUE10_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 10 Section 5 41 052Ch QUEUE11_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 11 Section 5 41 0530h QUEUE12_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 12 Section 5 41 0534h QUEUE13_TXDMA
159. ORBELL packet 11 Boot Code is executed and normal operation follows Boot Program ONO Figure 41 Bootload Operation 1x RapidlO DSP vk Optional 12C EEPROM 2 3 14 2 Bootload Data Movement The system host is responsible for writing the bootload data into the DSP s L2 memory As such bootload is only supported using the direct I O model and not the message passing model Bootload data must be sent in packets with explicit L2 memory addresses indicating proper destination within the DSP As part of the peripheral s configuration it should be set up to transfer the desired bootload program to the DSP s memory through normal DMA bus commands 2 3 14 3 Device Wakeup 2 3 15 Upon completion of the bootload data transfer the system host issues a DOORBELL interrupt to the DSP The RapidlO peripheral processes this interrupt in a manner similar to that described in Section 4 monitoring the DMA bus write with response commands to ensure that the data has been completely transferred through the DMA This interrupt wakes up the CPUs by pulling them out of their reset state The 16 bit data field of the DOORBELL packet should be configured to interrupt Core 0 by setting a corresponding ICSR bit as described in Figure 46 RX Multicast Support Daisy Chain Operation and Packet Forwarding 2 3 15 1 RX Multicast Support 80 Multicast transactions are I O packets that specify a destination address within the hea
160. Oh 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 RX CPPI Interrupt Condition Routing Register 2 RX_CPPI_ICRR2 Address Offset 02C4h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset Table 79 RX CPPI Interrupt Condition Routing Register Field Descriptions Field Value Description ICRx Interrupt condition routing Routes the interrupt request from RX buffer descriptor queue x to one of x 0 to 15 eight interrupt destinations INTDSTO INTDST7 0000b INTDSTO 0001b INTDST1 0010b INTDST2 0011b INTDST3 0100b INTDST4 0101b INTDST5 0110b INTDST6 0111b INTDST7 1xxxb Reserved SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 145 SRIO Registers da TEXAS INSTRUMENTS www ti com 5 28 TX CPPI Interrupt Condition Routing Registers TX_CPPI_ICRR and TX_CPPI_ICRR2 Figure 89 and Table 80 summarize the ICRRs for the TXU These registers route queue interrupts to interrupt destinations For example if ICS6 1 in TX_CPPI_ICSR and ICR6 0011b in TX_CPPI_ICRR the interrupt request from TX buffer descriptor queue 6 is sent to interrupt destination 3 For additional
161. One data sample taken every two PLL output clock cycles 11b Reserved Table 8 shows the frequency range versus the multiplication factor MPY Table 8 Frequency Range versus MPY Value RIOCLK and RIOCLK Line Rate Range Gbps MPY Range MHz Full Half Quarter 4x 250 425 2 3 4 1 1 7 0 5 0 85 5x 200 425 2 4 25 1 2 125 0 5 1 0625 6x 167 354 167 2 4 25 1 2 125 0 5 1 0625 8x 125 265 625 2 4 25 1 2 125 0 5 1 0625 10x 100 212 5 2 4 25 1 2 125 0 5 1 0625 12x 83 33 177 08 2 4 25 1 2 125 0 5 1 0625 12 5x 80 170 2 4 25 1 2 125 0 5 1 0625 15x 66 67 141 67 2 4 25 1 2 125 0 5 1 0625 20x 50 106 25 2 4 25 1 2 125 0 5 1 0625 25x 40 85 2 4 25 1 2 125 0 5 1 0625 2 3 2 2 Enabling the Receiver 30 To enable a receiver for deserialization the ENRX bit of the associated SERDES_CFGRXn_CNTL registers 100h 10Ch must be set high The fields of SERDES_CFGRXn_CNTL are shown in Figure 10 and described in Table 9 When ENRX is low all digital circuitry within the receiver will be disabled and clocks will be gated off All current sources within the receiver will be fully powered down with the exception of those associated with the loss of signal detector and IEEE1149 6 boundary scan comparators Loss of signal power down is independently controlled via the LOS bits of SERDES_CFGRXn_CNTL When enabled the differential signal amplitude of the received signal is monitored Whenever loss
162. R W 0 23 22 21 eee GE Reserved R W 0 R W 0 R 0 8 Reserved R 0 7 6 5 0 Sesunmv ACCESS Reserved R W 0 R W 0 R 0 LEGEND R Read W Write n Value after reset Table 151 Logical Transport Layer Error Detect CSR ERR_DET Field Descriptions Bit Field Value Description 31 IO_ERR_RSPNS I O error response endpoint device only 0 An LSU did not receive an ERROR response to an UO logical layer request 1 An LSU received an ERROR response to an I O logical layer request To clear this bit write O to it 30 MSG_ERR_RSPNS Message error response endpoint device only 0 The TXU did not receive an ERROR response to a message logical layer request 1 The TXU received an ERROR response to a message logical layer request To clear this bit write 0 to it 29 Reserved 0 This read only bit returns 0 when read 28 ERR_MSG_FORMAT Error in message format endpoint device only 0 The RXU did not receive a message data payload with an invalid size or segment 1 The RXU received a message data payload with an invalid size or segment To clear this bit write 0 to it 27 ILL_TRANS_DECODE Illegal transaction decode switch or endpoint device For an LSU or the TXU 0 The LSU TXU did not receive illegal fields in the response packet for an IO message transaction 1 The LSU TXU received illegal fields in the response packet for an IO message transaction To clear this bit write 0 to it For the MAU or the RXU 0 The MAU RXU did not receive illegal fields in
163. RDER IN_ORDER IN_ORDER IN_ORDER IN_ORDER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 116 Receive CPPI Control Register RX_CPPI_CNTL Field Descriptions Bit Field Value Description 31 16 Reserved 0000h Reserved 15 0 QUEUEn_IN_ORDER Queuen in order n 15 to 0 0 Allows out of order message reception Requires in order message reception Used for applications with dedicated source destination flows SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 173 SRIO Registers da TEXAS INSTRUMENTS www ti com 5 49 Transmit CPPI Weighted Round Robin Control Registers TX_QUEUE_CNTL 0 3 The transmission order among TX buffer descriptor queues is based on the programmable weighted round robin scheme explained in Section 2 3 4 2 As part of this scheme software must program the 16 mappers to determine the order in which the queues are serviced and how many messages are handled in each queue during each time around the round robin cycle The mappers are programmed with the registers shown in Figure 112 The register fields are described in Table 117 For additional programming information see Section 2 3 4 2 Figure 112 Transmit CPPI Weighted Round Robin Control Registers TX_QUEUE_CNTLO Address Offset 07E0h
164. RIO 35 Submit Documentation Feedback SRIO Functional Description da TEXAS INSTRUMENTS www ti com Figure 12 Load Store Registers for RapidlO Address Offset LSU1 400h 418h LSU2 420h 438h LSU3 440h 458h LSU4 460h 478h LSUn_REGO RapidlO Address MSB Control 31 0 LSUn_REG1 RapidlO Address LSB Config_offset Control 31 0 LSUn_REG2 DSP Address Control 31 0 LSUn_REG3 RSV Byte_count Control 31 12 11 0 LSUn_REG4 OutPortID Priority xambs ID Size DestID RSV Interrupt Req Control 31 30 29 28 27 26 25 24 23 8 7 1 0 LSUn_REG5 Drbll Info Hop Count Packet Type Command 31 16 15 8 7 0 LSUn_REG6 RSV Completion Code Bsy Status 31 5 4 1 0 The mapping of LSU register fields to RapidlO packet header fields is explained in Table 14 and Table 15 Table 14 has the fields of the control and command registers LSUn_REGO through LSUn_REGS5 and Table 15 has the fields of the status register _SUn_REG6 Table 14 LSU Control Command Register Fields LSU Register Field RapidlO Packet Header Field RapidlO Address MSB 32 bit Extended Address Fields Packet Types 2 5 and 6 RapidlO Address LSB Config_offset 1 32 bit Address Packet Types 2 5 and 6 Will be used in conjunction with BYTE_COUNT to create 64 bit aligned RapidlO packet header address 2 24 bit Config_offset Field Maintenance Packets Type 8 Will be used in conjunction w
165. RIO_REGS gt PER_SET_CNTL mdata bootcmp1 0 SRIO_REGS gt DEV_ID OxBEEF0030 id BEEF ti 0x0030 SRIO_REGS gt DEV_INFO 0x00000000 0 SRIO_REGS gt ASBLY_ID 0x00000030 ti 0x0030 SRIO_REGS gt ASBLY_INFO 0x00000000 0x0000 next ext 0x0100 SRIO_REGS gt PE_FEAT 0x20000019 proc bu ext 16 bit ID 34 bit addr SRIO_REGS gt SRC_OP 0x0000FDFA4 all SRIO_REGS gt DEST_OP 0x0000FC04 all except atomic SRIO_REGS gt PE_LL_CTL 0x00000001 34 bit addr SRIO_REGS gt LCL_CFG_HBAR 0x00000000 0 SRIO_REGS gt LCL_CFG_BAR 0x00000000 0 SRIO_REGS gt BASE_ID 0x00ABBEEF 16b id BEEF 08b id AB SRIO_REGS gt HOST_BASE_ID_LOCK Ox0000BEEF id BEEF lock SRIO_REGS gt COMP_TAG 0x00000000 not touched SRIO_REGS gt SP_IP_DISCOVERY_TIMER 0x90000000 0 short cycles for sim SRIO_REGS gt IP_PRESCAL 0x00000021 srv_clk prescalar 0x21 333MHz SRIO_REGS gt SPO_SILENCE_TIMER 0x20000000 SRIO_REGS gt SP1_SILENCE_TIMER 0x20000000 SRIO_REGS gt SP2_SILENCE_TIMER 0x20000000 SRIO_REGS gt SP3_SILENCE_TIMER 0x20000000 rdata SRIO_REGS gt PER_SET_CNTL wdata 0x01000000 mask 0x01000000 mdata wdata amp mask rdata amp mask SRIO_REGS gt PER_SET_CNTL mdata bootcmpl 1 RIO_REGS gt SP_LT_CTL OxFFFFFF00 long 78 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Fu
166. RUMENTS www ti com SRIO Functional Description Figure 24 RX Buffer Descriptors RX queue head descriptor Port RX DMA pointer state TX Buffer Descriptor TX_DESCP0_0 gt TXDESCO CSL_FMK SRIO_TXDESCO_N_POINTER int TX_DESCPO_1 link to TX_DESCPO_1 TX_DESCP0_0 gt TXDESC1 CSL_FMK SRIO_TXDESC1_B_POINTER int amp xmtBuff1 0 Buffer Pointer TX_DESCP0_0 gt TXDESC2 CSL_FMK SRIO_TXDESC2_DESTID OxBEEF CSL_FMK SRIO_TXDESC2_PRI 1 CSL_FMK SRIO_TXDESC2_TT 1 CSL_FMK SRIO_TXDESC2_PORTID 3 CSL_FMK SRIO_TXDESC2_SSIZE SSIZE_256B CSL_FMK SRIO_TXDESC2_MAILBOX 0 TX_DESCP0_0 gt TXDESC3 CSL_FMK SRIO_TXDESC3_SOP 1 CSL_FMK SRIO_TXDESC3_EOP 1 CSL_FMK SRIO_TXDESC3_OWNERSHIP 1 CSL_FMK SRIO_TXDESC3_EOQ 1 CSL_FMK SRIO_TXDESC3_TEARDOWN 0 CSL_FMK SRIO_TXDESC3_RETRY_COUNT 0 CSL_FMK SRIO_TXDESC3_MESSAGE_LENGTH MLEN_512DW TX_DESCPO_1 gt TXDESCO CSL_FMK SRIO_TXDESCO_N_POINTER 0 end of message TX_DESCPO_1 gt TXDESCI CSL_FMK SRIO_TXDESC1_B_POINTER int amp xmtBuff2 0 TX_DESCPO_1 gt TXDESC2 CSL_FMK SRIO_TXDESC2_DESTID OxBEEF CSL_FMK SRIO_TXDESC2_PRI 1 CSL_FMK SRIO_TXDESC2_TT 1 CSL_FMK SRIO_TXDESC2_PORTID 3 CSL_FMK SRIO_TXDESC2_SSIZE SSIZE_256B CSL_FMK SRIO_TXDESC2_MAILBOX 1 TX_DESCPO_1 gt TXDESC3 CSL_FMK SRIO_TXDESC3_SOP 1 CSL_FMK SRIO_TXDESC3_EOP 1 CSL_FMK SRIO_TXDESC3_OWNERSHIP 1 CSL_FMK SRIO_TXDESC3_EOQ 1 CSL
167. R_STAT 203 OUTPUT_PORT_ENABLE field of SPn_CTL 206 OUTPUT_RETRIED field of SPn_ERR_STAT 203 OUTPUT_RETRY_ENC field of SPn_ERR_STAT 203 OUTPUT_RETRY_STP field of SPn_ERR_STAT 203 output amplitude field 128 output degraded status bit for ports 203 output enable field for portn 207 output error stopped status bit for ports 204 output failed status bit for ports 203 output packet drop status bit for ports 203 output port number field for LSUn 159 output retry control symbol status bit for ports 204 output retry status bit for ports 204 output retry stopped status bit for ports 204 output swing field 128 output transmission error status bit for ports 204 OUTSTANDING_ACKID field of SPn_ACKID_STAT 202 override memory sleep bit 113 oversize packet at port n rate counting enable field 222 status field 220 ownership field of RX buffer descriptor 47 ownership field of TX buffer descriptor 52 P PACKET_TYPE field of LSUn_REG5 160 packet drop status bit for ports 203 packet forwarding registers 8 bit device IDs 124 16 bit device IDs 123 packet header capture fields for port n error capture bytes 0 to 3 224 bytes A to 7 225 bytes 8 to 11 226 bytes 12 to 15 227 packet header fields direct I O operation 38 doorbell operation 64 message request packet 44 packet not accepted control symbol at port n rate counting enable field 221 status field 220 packet priority field for LSUn 159 packet reordering during transmission 75 SPRUE13A September 2006 S
168. Register NTD To DECOD I ussssssssssssnnnnnrrrrrrrnrrnnnnnnnnnnennnne 150 INTDSTn Interrupt Rate Control Register INTDSTn_RATE_CNTL 0 seeceeeeeeeeeeeee eee eeeeee 154 LSUn Control Register 0 LSUN_REGO uuzausunnennnannannnnnnannunnnunnnnnnnnnnnnnnnnnn nun nun nun 155 LSUn Control Register 1 LSUN_REG1 ccecceeee eee teeter eee eee ann nun nnnnnn nn nn nun nun nun nnan nun 156 LSUn Control Register 2 LSUn REG2 u ana en 157 LSUR GonNtr l Register 3 ESUn REGS eessen EE 158 LSUn Control Register 4 LSUn_REG4 ENEE EEN 159 LSUn Control Register 5 LSUn_REG5 u22suusnannnannan mann nannannnunnnnnannnannnunnnnn ann nun nun 160 LSUn Control Register 6 LSUN_REG6 Auen 161 LSUn Congestion Control Flow Mask Register LSUn_FLOW_MASKS eceeeeeeeeeeeeeeeees 162 Queue n Transmit DMA Head Descriptor Pointer Register QUEUEn_TXDMA_HDP 164 Queue n Transmit DMA Completion Pointer Register QUEUEn_TXDMA_CP sseeeeeeeeeeee 165 Queue n Receive DMA Head Descriptor Pointer Register QUEUEn_RXDMA_HDP 166 Queue n Receive DMA Completion Pointer Register QUEUEn_RXDMA_CP eeeeeeeeeees 167 Transmit Queue Teardown Register TX_QUEUE_TEAR_DOWN zuunennsnnnannnnnennnannnunnnn nen 168 Transmit CPPI Supported Flow Mask Registers T X_CPPI_FLOW_MASKSI O 7 uz r 2042 169 Receive Queue Teardown Register RX_QUEUE_TEAR_ DOWN eeeeeeeee cece eeeeeeee 172 Receive CPP
169. Register 2 Section 5 94 1201Ch SP_IP_PW_IN_CAPT3 Port Write In Capture CSR Register 3 Section 5 94 14000h SPO_RST_OPT Port 0 Reset Option CSR Section 5 95 14004h SPO_CTL_INDEP Port 0 Control Independent Register Section 5 96 14008h SPO_SILENCE_TIMER Port 0 Silence Timer Register Section 5 97 1400Ch SPO_MULT_EVNT_CS Port 0 Multicast Event Control Symbol Request Register Section 5 98 14014h SPO_CS_TX Port 0 Control Symbol Transmit Register Section 5 99 14100h SP1_RST_OPT Port 1 Reset Option CSR Section 5 95 14104h SP1_CTL_INDEP Port 1 Control Independent Register Section 5 96 14108h SP1_SILENCE_TIMER Port 1 Silence Timer Register Section 5 97 1410Ch SP1_MULT_EVNT_CS Port 1 Multicast Event Control Symbol Request Register Section 5 98 14114h SP1_CS TX Port 1 Control Symbol Transmit Register Section 5 99 14200h SP2_RST_OPT Port 2 Reset Option CSR Section 5 95 14204h SP2_CTL_INDEP Port 2 Control Independent Register Section 5 96 14208h SP2_SILENCE_TIMER Port 2 Silence Timer Register Section 5 97 1420Ch SP2_MULT_EVNT_CS Port 2 Multicast Event Control Symbol Request Register Section 5 98 14214h SP2_CS_TX Port 2 Control Symbol Transmit Register Section 5 99 14300h SP3_RST_OPT Port 3 Reset Option CSR Section 5 95 14304h SP3_CTL_INDEP Port 3 Control Independent Register Section 5 96 14308h SP3_SILENCE_TIMER Port 3 Silence Timer Register Section 5 97 1430Ch SP3_MULT_EVNT_CS Port 3 Multicast Event Control Symbol Request Register Se
170. Reserved 0 These read only bits return Os when read 5 MLTC_EN Multicast Event Interrupt Enable If enabled the interrupt signal is High when the Multicast Event control symbol is received by any port 0 Multicast interrupt disable Multicast interrupt enable 4 MLTC_IRQ Multicast event interrupt status Once set the MLTC_IRQ bit remains set until software writes a 1 to it The mitc_irq output signal is driven by this bit 0 The multicast event control symbol has not been received by any of the ports The multicast event control symbol has been received by one of the ports SPRUE13A September 2006 Serial RapidlO SRIO 231 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers Table 177 Port IP Mode CSR SP_IP_MODE Field Descriptions continued Bit Field Value Description 3 RST_EN Reset Interrupt Enable If enabled the interrupt signal is High when the 4 reset control symbols are received in a sequence 0 Reset interrupt disable 1 Reset interrupt enable 2 RST_CS Reset received status bit It is set when Once set the RST_CS bit remains set until software writes a 1 to it The rst_irq output signal is driven by this bit 0 Four reset control symbols have not been received in a sequence 1 Four reset control symbols have been received in a sequence 1 PW_EN Port Write In Interrupt Enable If enabled the interrupt signal is High when the Port Write In requ
171. SERDES_CFGRXn_CNTL 125 CLASS field of PID 111 clearing interrupt conditions 86 clear registers for CPPI interrupt conditions 135 137 for doorbell interrupt conditions 133 for error reset and special event port interrupt conditions 143 for LSU interrupt conditions 141 clock data recovery field 125 clock domains 21 clock prescaler field 233 clock recovery 21 CMD field of SPn_CS_TX 240 CM field of SERDES_CFGTXn_CNTL 128 CNTL_SYM_UNEXPECTED_ACKID_EN field of SPn_RATE_EN 221 CNTL_SYM_UNEXPECTED_ACKID field of SPn_ERR_DET 219 command control symbol field for portn 240 COMMAND field of SPn_LM_REQ 200 command status completion code field for LSUn 161 common mode field 128 common transport large system support field 186 Communications Port Programming Interface See CPPI 43 COMP_TAG 195 COMPLETION_CODE field of LSUn_REG6 161 completion pointer for RX queuen 167 completion pointer for TX queuen 165 COMPONENT_TAG field of COMP_TAG 195 configuration offset field for LSUn 156 configuring SERDES macros 28 congestion control 65 basicscheme 66 congestion control packet CCP Ftype and Ttype 25 congestion control packet CCP purpose 65 count of Xoff congestion control packets 66 flow control destination IDs 66 flow masks 67 time out timer 66 control capture CSR for logical transport errors 217 control information field for port n error capture 224 control symbols acknowledge or link response control symbol overdue SPRUE13A Septem
172. SK Field Descriptions Bit Field Value Description 15 FL15 0 Queue n does not support Flow 15 from table entry 1 Queue n supports Flow 15 from table entry 14 FL14 0 Queue n does not support Flow 14 from table entry 1 Queue n supports Flow 14 from table entry 13 FL13 0 Queue n does not support Flow 13 from table entry 1 Queue n supports Flow 13 from table entry 170 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 114 TX Queue n FLOW_MASK Field Descriptions continued Bit Field Value Description 12 FL12 0 Queue n does not support Flow 12 from table entry 1 Queue n supports Flow 12 from table entry 11 FL11 0 Queue n does not support Flow 11 from table entry 1 Queue n supports Flow 11 from table entry 10 FL10 0 Queue n does not support Flow 10 from table entry 1 Queue n supports Flow 10 from table entry 9 FL9 0 Queue n does not support Flow 9 from table entry 1 Queue n supports Flow 9 from table entry 8 FL8 0 Queue n does not support Flow 8 from table entry 1 Queue n supports Flow 8 from table entry 7 FL7 0 Queue n does not support Flow 7 from table entry 1 Queue n supports Flow 7 from table entry 6 FL6 0 Queue n does not support Flow 6 from table entry 1 Queue n supports Flow 6 from table entry 5 FL5 0 Queue n does not support Flow 5 from table entry 1 Queue
173. ST Interrupt Status Decode Register 3 Section 5 31 0310h INTDST4_DECODE INTDST Interrupt Status Decode Register 4 Section 5 31 0314h INTDST5 DECODE INTDST Interrupt Status Decode Register 5 Section 5 31 0318h INTDST6_DECODE INTDST Interrupt Status Decode Register 6 Section 5 31 031Ch INTDST7_DECODE INTDST Interrupt Status Decode Register 7 Section 5 31 0320h INTDSTO_RATE_CNTL INTDST Interrupt Rate Control Register 0 Section 5 32 0324h INTDSTI_RATE_CNTL INTDST Interrupt Rate Control Register 1 Section 5 32 0328h INTDST2_RATE_CNTL INTDST Interrupt Rate Control Register 2 Section 5 32 032Ch INTDST3_RATE_CNTL INTDST Interrupt Rate Control Register 3 Section 5 32 0330h INTDST4_RATE_CNTL INTDST Interrupt Rate Control Register 4 Section 5 32 0334h INTDST5_RATE_CNTL INTDST Interrupt Rate Control Register 5 Section 5 32 0338h INTDST6_RATE_CNTL INTDST Interrupt Rate Control Register 6 Section 5 32 033Ch INTDST7_RATE_CNTL INTDST Interrupt Rate Control Register 7 Section 5 32 0400h LSU1_REGO LSU1 Control Register 0 Section 5 33 0404h LSU1_REG1 LSU1 Control Register 1 Section 5 34 0408h LSU1_REG2 LSU1 Control Register 2 Section 5 35 040Ch LSU1_REG3 LSU1 Control Register 3 Section 5 36 0410h LSU1_REG4 LSU1 Control Register 4 Section 5 37 0414h LSU1_REGS5 LSU1 Control Register 5 Section 5 38 0418h LSU1_REG6 LSU1 Control Register 6 Section 5 39 041Ch LSU1_FLOW_MASKS LSU1 Congestion Control Flow Mask Register Section 5 40 0420h LSU2_ REGO LSU2 C
174. STRUMENTS www ti com SRIO Registers 5 64 Component Tag CSR COMP_TAG The component Tag CSR COMP_TAG is shown in Figure 127 and described in Table 135 Figure 127 Component Tag CSR COMP_TAG Address Offset 106Ch 31 0 COMPONENT_TAG R W 00000000h LEGEND R W Read Write n Value after reset Table 135 Component Tag CSR COMP_TAG Field Descriptions Bit Field Value Description 31 0 COMPONENT_TAG 00000000h Software defined component tag for the PE Useful for devices without to device IDs FFFFFFFFh SPRUE13A September 2006 Serial RapidlO SRIO 195 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 65 1x 4x LP Serial Port Maintenance Block Header Register SP_MB_HEAD The 1x 4x LP_Serial port maintenance block header register SP_MB_HEAD is shown in Figure 128 and described in Table 136 Figure 128 1x 4x LP_Serial Port Maintenance Block Header Register SP_MB_HEAD Address Offset 1100h 31 16 15 0 EF_PTR EF_ID R 1000h R 0001h LEGEND R Read only n Value after reset Table 136 1x 4x LP_Serial Port Maintenance Block Header Register SP_MB_HEAD Field Descriptions Bit Field Value Description 31 16 EF_PTR Hard wired pointer to the next block in the data structure 15 0 EF_ID Hard wired extended features ID 0001h General endpoint device 0002h General endpoint device with software assisted error recovery option
175. STRUMENTS www ti com SRIO Registers 5 42 Queue n Transmit DMA Completion Pointer Register QUEUEn_TXDMA_CP There are sixteen of these registers see Table 106 QUEUEn_TXDMA_CP is shown in Figure 104 and described in Table 107 For additional programming information see Section 2 3 4 2 Table 106 QUEUEn_TXDMA_CP Registers Register Address Offset QUEUEO_TXDMA_CP QUEUE1_TXDMA_CP QUEUE2_TXDMA_CP QUEUE3_TXDMA_CP QUEUE4_TXDMA_CP QUEUE5_TXDMA_CP QUEUE6_TXDMA_CP QUEUE7_TXDMA_CP QUEUE8_TXDMA_CP QUEUE9_TXDMA_CP QUEUE10_TXDMA_CP QUEUE11_TXDMA_CP QUEUE12_TXDMA_CP QUEUE13_TXDMA_CP QUEUE14_TXDMA_CP QUEUE15_TXDMA_CP 0580h 0584h 0588h 058Ch 0590h 0594h 0598h 059Ch 05A0h 05A4h 05A8h 05ACh 05B0h 05B4h 05B8h 05BCh Figure 104 Queue n Transmit DMA Completion Pointer Register QUEUEn_TXDMA_CP 31 TX_CP LEGEND R W Read Write n Value after reset R W 00000000h Table 107 Queue Transmit DMA Completion Pointer Registers QUEUEn_TXDMA_CP Field Descriptions Bit Field Value Description 31 0 TX_CP 00000000h This field is the memory address for the transmit queue completion pointer This to register is written by the DSP core with the buffer descriptor address for the last FFFFFFFFh buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted SPRUE13A September 2006 Submit Documentati
176. ST_EVNT_ICSR 7 3 Reserved 0 These read only bits return Os when read 2 0 ICCy 0 No effect y 2 to 0 1 Clear bit y of ERR_RST_EVNT_ICSR SPRUE13A September 2006 Serial RapidlO SRIO 143 Submit Documentation Feedback SRIO Registers 5 26 DOORBELLn Interrupt Condition Routing Registers DOORBELLn_ICRR and DOORBELLn_ICRR2 da TEXAS INSTRUMENTS www ti com When doorbell packets are received by the SRIO peripheral these ICRRs route doorbell interrupt requests from the associated doorbell ICSR to user selected interrupt destinations Each of the four doorbells can be mapped to these registers see Table 77 The general field description in Table 78 applies to an ICRx field of either register For additional programming information see Section 4 4 1 and Section 2 3 6 Table 77 DOORBELLn_ICRR Registers Register Address Offset DOORBELLO_ICRR DOORBELLO_ICRR2 DOORBELL1_ICRR DOORBELL1_ICRR2 DOORBELL2_ICRR DOORBELL2_ICRR2 DOORBELL3_ICRR DOORBELL3_ICRR3 0280h 0284h 0290h 0294h 02A0h 02A4h 02BOh 02B4h Figure 87 Doorbell n Interrupt Condition Routing Registers Doorbell n Interrupt Condition Routing Register DOORBELLn_ICRR 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W Oh R W Oh R W Oh R W Oh 15 12 11 87 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 Doorbell n Interrupt Condition Routing Register 2 DOORBELLn_ICRR2 31 28 27 24 23 20 1
177. Serial RapidlO SRIO 43 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Functional Description e Out of order responses are allowed e A RETRY response is issued to the first received segment of a multi segment message when the RX queue is busy servicing another request Subsequent RETRY responses may have to be sent for received pipeline segments or additional pipelined messages to the same queue e n order message reception for dedicated flows is mode programmable e A queue is needed for each supported simultaneous multi segment RX message e A minimum of 1 25K bytes of SRAM 64 buffer descriptors is supported e The transmit source must be able to retry any given segment of a message e DestlD is equal to port for TX operations and the same Deet is not accessible from multiple ports 2 3 4 1 RX Operation 44 Q15 As message packets are received by the RapidlO ports the data is written into memory while maintaining accurate state information that is needed for future processing For instance if amessage spans multiple packets information is saved that allows re assembly of those packets by the CPU The CPPI module provides a scheme for tracking single and multi packet messages linking messages in queues and generating interrupts Figure 16 illustrates the scheme Figure 16 CPPI RX Scheme for RapidlO Buffer descriptor Mailbox 1 64 queues from RapidlO packet Descriptor per message Head
178. Signal Processor DSP Included are descriptions of the available boot modes and any interfacing requirements associated with them instructions on generating the boot table and information on the different versions of the Bootloader Preface SPRUE13A September 2006 Submit Documentation Feedback i3 TEXAS INSTRUMENTS www ti com Related Documentation From Texas Instruments Trademarks TMS320TCI648x C6000 TMS320C62x TMS320C67x TMS320C6000 Code Composer Studio are trademarks of Texas Instruments RapidlO is a registered trademark of RapidlO Trade Association InfiniBand is a trademark of the InfiniBand Trade Association SPRUE13A September 2006 Read This First 15 Submit Documentation Feedback d TEXAS User s Guide INSTRUMENTS SPRUE13A September 2006 1 1 16 Serial RapidlO SRIO Overview The RapidlO peripheral used in the TMS320TCI648x is called a serial RapidlO SRIO This chapter describes the general operation of a RapidlO system how this module is connected to the outside world the definitions of terms used within this document and the features supported and not supported for SRIO General RapidlO System RapidlO is a non proprietary high bandwidth system level interconnect It is a packet switched interconnect intended primarily as an intra system interface for chip to chip and board to board communications at Gigabyte per second performance levels Uses for the architecture can be found in connected
179. Status Register IX CPP IG 136 5 21 TX CPPI Interrupt Clear Register TN CPP ICH 137 5 22 LSU Interrupt Condition Status Register GU WC 138 SPRUE13A September 2006 Table of Contents 3 Submit Documentation Feedback Contents 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 30 5 31 5 32 5 33 5 34 5 35 5 36 5 37 5 38 5 39 5 40 5 41 5 42 5 43 5 44 5 45 5 46 5 47 5 48 5 49 5 50 5 51 5 52 5 53 5 54 5 55 5 56 5 57 5 58 5 59 5 60 5 61 5 62 5 63 5 64 5 65 5 66 5 67 5 68 LSU Interrupt Condition Clear Register LSU_ICCR 0cseeeeee sees eee eee ee sees nun ann nen nun nenn 141 Error Reset and Special Event Interrupt Condition Status Register ERR RS ENT CSR asien aa nn aan Da an anna hai 142 Error Reset and Special Event Interrupt Condition Clear Register ERR RST EVNT ICER unnrssssus anne an nn a anna aa aan nn namen en 143 DOORBELLn Interrupt Condition Routing Registers DOORBELLn_ICRR and DOORBELLAICRR2 irendi a aan sc aaa anna 144 RX CPPI Interrupt Condition Routing Registers RX_CPPI_ICRR and RX_CPPI_ICRR2 145 TX CPPI Interrupt Condition Routing Registers TX_CPPI_ICRR and TX_CPPI_ICRR2 146 LSU Interrupt Condition Routing Registers LSU_ICRRO LSU_ICRR3 2eeeeeeeeeee eee 147 Error Reset and Special Event Interrupt Condition Routing Registers ERR_RST_EVNT_ICRR ERR_RST_EVNT_ICRR2 and ERR_RST_EVNT_ICRR3 149 Interrupt Status Decode
180. TED Reserved RESP_ENABLE TRANS_ENABLE R W 0 R W 0 R 0 8 Reserved R 0 7 6 5 0 RX_CPPI_ HX IO Reserved SECURITY_ SECURITY_ ENABLE ENABLE R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n Value after reset Table 152 Logical Transport Layer Error Enable CSR ERR_EN Field Descriptions Bit Field Value Description 31 IO_ERR_RESP_ENABLE IO error response reporting enable Disable reporting of an IO error response Enable reporting of an IO error response endpoint device only Save and lock original request transaction capture information in all Logical Transport Layer Capture CSRs 30 MSG_ERR_RESP_ENABLE Message error response reporting enable Disable reporting of a message error response Enable reporting of a message error response endpoint device only Save and lock transaction capture information in all Logical Transport Layer Capture CSRs 29 Reserved 0 Always write 0 to this reserved bit 28 ERR_MSG_FORMAT_ENABLE Message format error reporting enable Disable reporting of a message format error Enable reporting of a message format error endpoint device only Save and lock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs 27 ILL_TRANS_DECODE_ENABLE Illegal transaction decode error reporting enable Disable reporting of an illegal transaction decode error Enable reporting of an illegal transaction decode error switch or
181. TGT_ID Field Descriptions ceceeeeeeeeee non nn nn nun nun nn nn 218 158 SPn_ERR_DET Registers and the Associated Portes 219 159 Port Error Detect CSR n SPn_ERR_DET Field Descriptions uuzusuunnennnannnn nun nun nnnnnnn nun ann nn 219 160 SPn_RATE_EN Registers and the Associated Porte 221 161 Port Error Rate Enable CSR n SPn_RATE_EN Field Descriptions us4 u40n nun nenn ann nun nun ann nn 221 162 SPn_ERR_ATTR_CAPT_DBGO Registers and the Associated Portes 223 163 Port n Attributes Error Capture CSR 0 SPn_ERR_ATTR_CAPT_DBGO Field Descriptions 223 164 SPn_ERR_CAPT_DBG1 Registers and the Associated Portes 224 165 Port n Error Capture CSR 1 SPn_ERR_CAPT_DBG1 Field Descriptions eeeeeeeee eee eens eens 224 166 SPn_ERR_CAPT_DBG2 Registers and the Associated Portes 225 167 Port n Error Capture CSR 2 SPn_ERR_CAPT_DBG2 Field Descriptions 4 RH HH nen nn nennen 225 168 SPn_ERR_CAPT_DBG3 Registers and the Associated Portes 226 169 Port n Error Capture CSR 3 SPn_ERR_CAPT_DBGS Field Descriptions 4 HH HH nen Rn nennen 226 170 SPn_ERR_CAPT_DBG4 Registers and the Associated Portes 227 171 Port n Error Capture CSR 4 SPn_ERR_CAPT_DBG4 Field Descriptions uu4 44 44 HRnn Rn n nn ann nn nn 227 172 SPn_ERR_RATE Registers and the Associated Porte 228 173 Port Error Rate CSR n SPn_ERR_RATE Field Description 228 174 SPn_ERR_THRESH Regis
182. TMS320TCI648x Serial RapidlO SRIO User s Guide Literature Number SPRUE13A September 2006 d TEXAS INSTRUMENTS SPRUE13A September 2006 Submit Documentation Feedback Contents PROTA e 14 1 OVGIVIOW enee deeg adda ded deed dee 16 1 1 General RapidlO System NEE 16 1 2 RapidlO Feature Support in SIE eegene Sege rn 19 1 3 ee Ei E 20 1 4 External Devices Requirements NEEN NENNEN REENEN NEEN nennen ann nenn nenn nennen anne en KEEN 20 1 5 TI Devices Supported By This Document 20 2 SRIO Functional Description u00 02000000 ann aan ee 21 2 1 OV GIVIGW ee a EE 21 2 2 elle 25 2 3 fleece Eer le 26 3 Logical Transport Error Handling and Logging sees eens anne ee nn nnnn ann en nn 83 4 Interrupt Condttiong eseu neninn anna aan ea 85 4 1 ER N zus EE 85 4 2 General DeScriptioni sc le SE Ee ee sateen 85 4 3 Interrupt Condition Status and Clear Heglsters nun nun ann nenn 86 4 4 Interrupt Condition Routing Heoieters nun nun nannunn nun nun une nenn 93 4 5 Interrupt Status Decode Registers ceeceeeee eee ee eee eee eee neat eee e enna nun nun nun mann nun nun une nenn 97 4 6 IntSrrupt GOMeraAtiON bade sea Salk oes een 99 4 7 Interrupt PACING sus wend sae te a a a a 99 4 8 Interrupt Handling aus aan 100 5 SRIO Registers 0 0 02 2 enee ae nn an nn na ara nie A en ran 102 5 1 Juge ele Le EN 102 5 2 Peripheral Identification Register PID ae 111 5 3 Peripheral Control Register DCH un 112
183. TRUMENTS www ti com 4 1 4 2 SPRUE13A September 2006 Interrupt Conditions Interrupt Conditions This section defines the CPU interrupt capabilities and requirements of the peripheral CPU Interrupts The following interrupts are supported by the RIO peripheral e Error status Event indicating that a run time error was reached The CPU should reset resynchronize the peripheral e Critical error Event indicating that a critical error state was reached The CPU should reset the system e CPU servicing Event indicating that the CPU should service the peripheral General Description The RIO peripheral is capable of generating various types of CPU interrupts The interrupts serve two general purposes error indication and servicing requests Since RapidlO is a packet oriented interface the peripheral must recognize and respond to inbound signals from the serial interface There are no GPIO or external pins used to indicate an interrupt request Thus the interrupt requests are signaled either by an external RapidlO device through the packet protocols discussed as follows or are generated internally by the RIO peripheral CPU servicing interrupts lag behind the corresponding data which was generally transferred from an external processing element into local L2 memory This transfer can use a messaging or direct I O protocol When the single or multi packet data transfer is complete the external PE or the peripheral itself must
184. UE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 90 Port Error Rate Threshold CSR n SPn_ERR_THRESH Each of the four ports is supported by a register of this type see The port error rate threshold CSR n SPn_ERR_THRESH is shown in Figure 153 and described in Table 175 Table 174 SPn_ERR_THRESH Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_THRESH 206Ch Port 0 SP1_ERR_THRESH 20ACh Port 1 SP2_ERR_THRESH 20ECh Port 2 SP3_ERR_THRESH 212Ch Port 3 Figure 153 Port Error Rate Threshold CSR n SPn_ERR_THRESH 31 24 23 16 ERROR_RATE_FAILED_THRESH ERROR_RATE_DEGRADED_THRESH R W FFh R W FFh 15 0 Reserved R 0000h LEGEND R W Read Write R Read only n Value after reset Table 175 Port Error Rate Threshold CSR n SPn_ERR_THRESH Field Descriptions Bit Field Value Description 31 24 ERROR_RATE_FAILED_THRESH These bits provide the threshold value for reporting an error condition due to a possibly broken link 00h Disable the error rate register Oth Set the error reporting threshold to 1 02h Set the error reporting threshold to 2 FFh Set the error reporting threshold to 255 23 16 ERROR_RATE_DEGRADED_THRESH These bits provide the threshold value for reporting an error condition due to a degrading link 00h Disable the error rate Register Oih Set the error reporting threshold to 1 02h Set t
185. UE14_TXDMA_CP Queue Transmit DMA Completion Pointer Register 14 Section 5 42 05BCh QUEUE15_TXDMA_CP Queue Transmit DMA Completion Pointer Register 15 Section 5 42 0600h QUEUEO_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 0 Section 5 43 0604h QUEUE1_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 1 Section 5 43 0608h QUEUE2 RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 2 Section 5 43 060Ch QUEUE3_ RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 3 Section 5 43 0610h QUEUE4 RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 4 Section 5 43 0614h QUEUE5 RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 5 Section 5 43 0618h QUEUE6_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 6 Section 5 43 061Ch QUEUE7_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 7 Section 5 43 0620h QUEUE8_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 8 Section 5 43 0624h QUEUE9_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 9 Section 5 43 0628h QUEUE10_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 10 Section 5 43 062Ch QUEUE11_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 11 Section 5 43 0630h QUEUE12_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 12 Section 5 43 0634h QUEUE13_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 13 Section 5 43 0638h QUEUE14_RXDMA_HDP Queue Receive
186. UE3_ QUEUE2_ QUEUE1_ QUEUEO_ TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN W 0 W 0 W 0 W 0 WO WO WO WO LEGEND R Read only W Write n Value after reset Table 115 Receive Queue Teardown Register RX_QUEUE_TEAR_DOWN Field Descriptions Bit Field Value Description 31 16 Reserved 0000h These read only bits return Os when read 15 0 QUEUEn_TEAR_DWN Queue n tear down i Te tet 0 No effect 1 Tear down Queue n 172 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 5 48 Receive CPPI Control Register RX_CPPI_CNTL Each bit in this register indicates whether the associated RX buffer descriptor queue must receive messages in the order the source device attempts to transmit them RX_CPPI_CNTL is shown in and described in Table 116 For additional programming information see Section 2 3 4 1 SRIO Registers Figure 111 Receive CPPI Control Register RX_CPPI_CNTL Address Offset 0744h 31 24 Reserved R 00h 23 16 Reserved R 00h 15 14 13 12 11 10 9 8 QUEUE15_ QUEUE14_ QUEUE13_ QUEUE12_ QUEUE11_ QUEUE10_ QUEUE9_ QUEUE8_ IN_ORDER IN_ORDER IN_ORDER IN_ORDER IN_ORDER IN_ORDER IN_ORDER IN_ORDER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 QUEUE7_ QUEUE6_ QUEUE5_ QUEUE4 QUEUE3_ QUEUE2_ QUEUE1_ QUEUEO_ IN_ORDER IN_ORDER IN_ORDER IN_O
187. UT_RETRY_STP Output retry stopped state OUTPUT_RETRY_STP is a read only bit The output port has not received a packet retry control symbol and or is not in the output retry stopped state The output port has received a packet retry control symbol and is in the output retry stopped state 17 OUTPUT_ERROR_ENC Output transmission error encountered Once set the OUTPUT_ERROR_ENC bit remains set until software writes a 1 to it The output port has not encountered a transmission error The output port has encountered and possibly recovered from a transmission error This bit is set when bit 16 is set 16 OUTPUT_ERROR_STP Output error stopped OUTPUT_ERROR_STP is a read only bit The output port is not in the output error stopped state The output port is in the output error stopped state 15 11 Reserved These read only bits return Os when read 10 INPUT_RETRY_STP Input retry stopped state INPUT_RETRY_STP is a read only bit The input port is not in the input retry stopped state The input port is in the input retry stopped state INPUT_ERROR_ENC Input port transmission error encountered Once set the INPUT_ERROR_ENC bit remains set until software writes a 1 to it The input port has not encountered a transmission error The input port has encountered and possibly recovered from a transmission error This bit is set when bit 8 is set INPUT_ERROR_STP Input error stop
188. Use PHY TRA LOG TRA LOG 1007 2 7 4 47 16 V 32 b 16 srcTID info msb info Isb D 8 8 7010 destiD sourcelD 5 3 2 2 4 8 8 8 Doorbell bit Reserved Doorbell Reg rsv Serial RapidlO SRIO 85 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com Interrupt Conditions 4 3 86 The DOORBELL packet s 16 bit INFO field indicates which DOORBELL register interrupt bit to set There are four DOORBELL registers each currently with 16 bits allowing 64 interrupt sources or circular buffers see Table 23 for assignment of the 16 bits of DOORBELL_INFO field Each bit can be assigned to any core as described by the Interrupt Condition Routing Registers Additionally each status bit is user defined for the application For instance it may be desirable to support multiple priorities with multiple TID circular buffers per core if control data uses a high priority for example priority 2 while data packets are sent on priority 0 or 1 This allows the control packets to have preference in the switch fabric and arrive as quickly as possible Since it may be required to interrupt the CPU for both data and control packet processing separately separate circular buffers are used and DOORBELL packets must distinguish between them for interrupt servicing If any reserved bit in the DOORBELL info field is set an error response is
189. VICEID_MSB 00h FFh Most significant byte of the port write target device ID large transport systems only 23 16 DEVICEID 00h FFh Port write target devicelD 15 0 Reserved 0000h These read only bits return Os when read 218 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 82 Port Error Detect CSR n SPn_ERR_DET Each of the four ports is supported by a register of this type see Table 158 The port error detect CSR n SPn_ERR_DET is shown in Figure 145 and described in Table 159 Table 158 SPn_ERR_DET Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_DET 2040h Port 0 SP1_ERR_DET 2080h Port 1 SP2_ERR_DET 20C0h Port 2 SP3_ERR_DET 2100h Port 3 Figure 145 Port Error Detect CSR n SPn_ERR_DET 31 30 24 ERR_IMP_ SPECIFIC R seed R W 0 R 0 23 22 21 20 19 18 17 16 CNTL_SYM_ PKT_ RCVD_PKT_ Reserved an UNEXPECTED NOT RC OEE UNEXPEGTED_ WITH BAD ee Reserved ACKID ACKID _CRC R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 15 8 Reserved R 0 7 6 5 4 3 2 1 0 4 Stay anne PROTOCOL_ ee DELINEATION_ UNSOLICITED_ LINK_ eseive ag E ERROR FEIER ERROR ACK_CNTL_SYM TIMEOUT R 0 R W 0 R W 0 R 0 R 00h R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 159 Port Error Detect CSR n SPn_ERR
190. W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 71 TX CPPI Interrupt Condition Status Register TX_CPPI_ICSR Field Descriptions Bit Field Value Description 31 16 Reserved 0 These read only bits return 0 when read 15 0 ICSx TX CPPI interrupt status 15 to 0 0 TX buffer descriptor queue x has not generated an interrupt request TX buffer descriptor queue x has generated an interrupt request 136 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Registers 5 21 TX CPPI Interrupt Clear Register TX_CPPI_ICCR This register is used to clear bits in TX_CPPI_ICSR to acknowledge interrupts from the TX buffer descriptor queues TX_CPPI_ICCR is shown in Figure 82 and described in Table 72 Figure 82 TX CPPI Interrupt Condition Clear Register TX_CPPI_ICCR Address Offset 0258h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO WO WO WO WO WO WO WO WO W 0 W 0 WO WO W 0 WO WO WO LEGEND R Read only W Write only n Value after reset Table 72 TX CPPI Interrupt Condition Clear Register TX_CPPI_ICCR Field Descriptions Bit Field Value Description 31 16
191. X Buffer Descriptor Field Definitions continued Field Description ssize RIO standard message payload size Indicates how the hardware should segment the 54 outgoing message by specifying the maximum number of double words per packet If the message is a multi segment message this field remains the same for all outgoing segments All segments of the message except for the last segment have payloads equal to this size The last message segment may be equal or less than this size Maximum message size for a 16 segment message is shown below Message_length 16 must be less than or equal to Ssize if not the message is not sent and CC 101b is set Written by the DSP core 0000b 1000b Reserved 1001b 1 Double word payload Supports up to a 128 byte message 1010b 2 Double word payload Supports up to a 256 byte message 1011b 4 Double word payload Supports up to a 512 byte message 1100b 8 Double word payload Supports up to a 1024 byte message 1101b 16 Double word payload Supports up to a 2048 byte message 1110b 32 Double word payload Supports up to a 4096 byte message 1111b Reserved mailbox Destination Mailbox Specifies the mailbox to which the message will be sent Written by the DSP core 000000b Mailbox 0 000001b Mailbox 1 000100b Mailbox 4 111111b Mailbox 63 For multi segment messages only the 2 LSBs of this mailbox field are valid Hardware will ignore the 4 MSBs of this field if the outgoing m
192. X CPPI Interrupt Condition Status Register Section 5 18 0248h RX_CPPI_ICCR RX CPPI Interrupt Condition Clear Register Section 5 19 0250h TX_CPPI_ICSR TX CPPI Interrupt Condition Status Register Section 5 20 0258h TX_CPPI_ICCR TX CPPI Interrupt Condition Clear Register Section 5 21 0260h LSU_ICSR LSU Interrupt Condition Status Register Section 5 22 0268h LSU_ICCR LSU Interrupt Condition Clear Register Section 5 23 0270h ERR_RST_EVNT_ICSR Error Reset and Special Event Interrupt Condition Status Section 5 24 Register 0278h ERR_RST_EVNT_ICCR Error Reset and Special Event Interrupt Condition Clear Section 5 25 Register 0280h DOORBELLO_ICRR DOORBELLO Interrupt Condition Routing Register Section 5 26 0284h DOORBELLO_ICRR2 DOORBELL 0 Interrupt Condition Routing Register 2 Section 5 26 0290h DOORBELL1_ICRR DOORBELL1 Interrupt Condition Routing Register Section 5 26 0294h DOORBELL1_ICRR2 DOORBELL 1 Interrupt Condition Routing Register 2 Section 5 26 02A0h DOORBELL2_ICRR DOORBELL2 Interrupt Condition Routing Register Section 5 26 02A4h DOORBELL2_ICRR2 DOORBELL 2 Interrupt Condition Routing Register 2 Section 5 26 02B0h DOORBELL3_ICRR DOORBELL3 Interrupt Condition Routing Register Section 5 26 02B4h DOORBELL3_ICRR2 DOORBELL 3 Interrupt Condition Routing Register 2 Section 5 26 02C0h RX_CPPI_ICRR Receive CPPI Interrupt Condition Routing Register Section 5 27 02C4h_ RX_CPPI_ICRR2 Receive CPPI Interrupt Condition Routing Register 2 Sectio
193. _DET Field Descriptions Bit Field Value Description 31 ERR_IMP_SPECIFIC Implementation specific error This bit covers errors that are a result of an illegal field in a maintenance packet an illegal destination ID and an unsupported transaction An implementation specific error has not been detected An implementation specific error has been detected 30 23 Reserved These read only bits return Os when read 22 CORRUPT_CNTL_SYM Bad CRC in control symbol The port did not receive a control symbol with a bad CRC value The port received a control symbol with a bad CRC value 21 CNTL_SYM_UNEXPECTED_ACKID Unexpected ackID in control symbol The port did not receive an acknowledge control symbol with an unexpected ackID packet accepted or packet retry The port received an acknowledge control symbol with an unexpected ackID packet accepted or packet retry The capture registers do not have valid information during this error detection SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 219 SRIO Registers da TEXAS INSTRUMENTS www ti com Table 159 Port Error Detect CSR n SPn_ERR_DET Field Descriptions continued Bit Field Value Description 20 RCVD_PKT_NOT_ACCPT Packet not accepted control symbol The port did not receive a packet not accepted acknowledge control symbol The port received a packet not accepted acknowl
194. _FMK SRIO_TXDESC3_TEARDOWN 0 CSL_FMK SRIO_TXDESC3_RETRY_COUNT 0 CSL_FMK SRIO_TXDESC3_MESSAGE_LENGTH MLEN_512DW 62 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 3 5 2 3 6 SPRUE13A September 2006 SRIO Functional Description Figure 25 TX Buffer Descriptors zem zen TX queue head descriptor Port TX DMA state pointer Start Message Passing SRIO_REGS gt Queue0_RXDMA_HDP int RX_DESCPO_O SRIO_REGS gt Queue0_TXDMA_HDP int TX_DESCPO_O Maintenance The type 8 MAINTENANCE packet format accesses the RapidlO capability registers CARs command and status registers CSRs and data structures Unlike other request formats the type 8 packet format serves as both the request and the response format for maintenance operations Type 8 packets contain no addresses and only contain data payloads for write requests and read responses All configuration register read accesses are word 4 byte accesses All configuration register write accesses are also word 4 byte accesses The wrsize field specifies the maximum size of the data payload for multiple double word transactions The data payload may not exceed that size but may be smaller if desired Both the maintenance read and the maintenance write request generate the appropriate maintenance response The maintenance port write operation is a write operation that do
195. _FMK SRIO_LSU1_REG4_XAMSB 0 CSL_FMK SRIO_LSU1_REG4_ID_SIZE 1 CSL_FMK SRIO_LSU1_REG4_DESTID OxBEEF CSL_FMK SRIO_LSU1_REG4_INTERRUPT_REQ 0 SRIO_REGS gt LSU1_REG5 CSL_FMK SRIO_LSU1_REG5_DRBLL_INFO 0x0000 CSL_FMK SRIO_LSU1_REG5_HOP_COUNT 0x03 CSL_FMK SRIO_LSU1_REG5_PACKET_TYPE type type DOORBELL Atomic Operations The Atomic operation is a combination read and write operation The destination reads the data at the specified address returns the read data to the requestor performs the required operation to the data and then writes the modified data back to the specified address without allowing any intervening activity to that address Defined operations are increment decrement test and swap set and clear see Table 3 Packet Type Of these only test and swap requires the requesting processing element to supply data Incoming Atomic operations which target the device are not supported for internal L2 memory or registers Atomic request operations to external devices are supported and have a response packet Request Atomic operations Ftype 2 never contain a data payload These operations are like NREAD 24h transactions The data payload size for the response to an Atomic transaction is 8 bytes The addressing scheme defined for the read portion of the Atomic transaction also controls the size of the atomic operation in memory so that the bytes are contiguous and of size byte half word 2 bytes or wo
196. _FORMAT_ENABLE field of ERR_EN 212 ERR_MSG_FORMAT field of ERR_DET 210 ERR_RPT_BH 209 ERR_RST_EVNT_ICCR 143 ERR_RST_EVNT_ICRR 149 ERR_RST_EVNT_ICRR2 149 ERR_RST_EVNT_ICRR3 149 ERR_RST_EVNT_ICSR 142 ERROR_CHECK_DISABLE field of SPn_CTL 206 ERROR_RATE_BIAS field of SPn_ERR_RATE 228 ERROR_RATE_COUNTER field of SPn_ERR_RATE 228 ERROR_RATE_DEGRADED_THRESH field of SPn_ERR_THRESH 229 ERROR DATE FAILED _THRESH field of SPn_ERR_THRESH 229 ERROR_RATE_RECOVERY field of SPn_ERR_RATE 228 ERROR_TYPE field of SPn_ERR_ATTR_CAPT_DBGO 223 error checking for ports general error checking disable field 207 idle error checking disable field 231 error handling and logging for logical transport errors 83 error rate counter for port n count value 228 decrement rate 228 peak count value 228 threshold 228 error rate counting enable register for portn 221 error rate thresholds for port n broken link case 229 degraded link case 229 error recovery software option for portn 236 error reporting block header register 209 error reporting thresholds for port n broken link case 229 degraded link case 229 error reset and special event interrupt condition clear register 143 error reset and special event interrupt condition routing registers 149 error reset and special event interrupt condition status SPRUE13A September 2006 Submit Documentation Feedback SRIO Registers register 142 ERROR response during direct I O reception 42 during mes
197. _HDP Queue Transmit DMA Head Descriptor Pointer Register 13 Section 5 41 0538h QUEUE14_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 14 Section 5 41 053Ch QUEUE15_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 15 Section 5 41 0580h QUEUEO_TXDMA_CP Queue Transmit DMA Completion Pointer Register 0 Section 5 42 0584h QUEUE1_TXDMA_CP Queue Transmit DMA Completion Pointer Register 1 Section 5 42 0588h QUEUE2_TXDMA_CP Queue Transmit DMA Completion Pointer Register 2 Section 5 42 058Ch QUEUE3_TXDMA_CP Queue Transmit DMA Completion Pointer Register 3 Section 5 42 0590h QUEUE4_ TXDMA_CP Queue Transmit DMA Completion Pointer Register 4 Section 5 42 0594h QUEUE5_TXDMA_CP Queue Transmit DMA Completion Pointer Register 5 Section 5 42 0598h QUEUE6_TXDMA_CP Queue Transmit DMA Completion Pointer Register 6 Section 5 42 059Ch QUEUE7_TXDMA_CP Queue Transmit DMA Completion Pointer Register 7 Section 5 42 05A0h QUEUE8_TXDMA_CP Queue Transmit DMA Completion Pointer Register 8 Section 5 42 05A4h QUEUE9_ TXDMA_CP Queue Transmit DMA Completion Pointer Register 9 Section 5 42 05A8h QUEUE10_TXDMA_CP Queue Transmit DMA Completion Pointer Register 10 Section 5 42 05ACh QUEUE11_TXDMA_CP Queue Transmit DMA Completion Pointer Register 11 Section 5 42 05B0h QUEUE12_TXDMA_CP Queue Transmit DMA Completion Pointer Register 12 Section 5 42 05B4h QUEUE13_TXDMA_CP Queue Transmit DMA Completion Pointer Register 13 Section 5 42 05B8h QUE
198. _PROMISCUOUS 1 CSL_FMK SRIO_RXU_MAPO H_SEGMENT_MAPPING 1 RX Buffer Descriptor RX_DESCPO_O gt RXDESCO CSL_FMK SRIO_RXDESCO_N_POINTER int RX_DESCPO_1 link to RX_DESCPO_1 RX_DESCP0_0 gt RXDESC1 CSL_FMK SRIO_RXDESC1_B_ POINTER int amp rcvBuff1 0 RX_DESCPO_O gt RXDESC2 CSL_FMK SRIO_RXDESC2_SRC_ID OxBEEF CSL_FMK SRIO_RXDESC2_PRI 1 CSL_FMK SRIO_RXDESC2_TT CSL_FMK SRIO_RXDESC2_MAILBOX 0 RX_DESCP0_0 gt RXDESC3 CSL_FMK SRIO_RXDESC3_SOP CSL_FMK SRIO_RXDESC3_EOP CSL_FMK SRIO_RXDESC3_OWNERSHIP 1 CSL_FMK SRIO_RXDESC3_EOOQ CSL_FMK SRIO_RXDESC3_TEARDOWN O CSL_FMK SRIO_RXDESC3_CC 0 CSL_FMK SRIO_RXDESC3_MESSAGE_LENGTH MLEN_512DW RX_DESCPO_1 gt RXDESCO CSL_FMK SRIO_RXDESCO_N_POINTER 0 end of message RX_DESCP0_1 gt RXDESC1 CSL_FMK SRIO_RXDESC1_B_POINTER int amp rcvBuff2 0 RX_DESCPO_1 gt RXDESC2 CSL_FMK SRIO_RXDESC2_SRC_ID OxBEEF CSL_FMK SRIO_RXDESC2_PRI 1 CSL_FMK SRIO_RXDESC2_TT CSL_FMK SRIO_RXDESC2_MAILBOX 1 RX_DESCPO_1 gt RXDESC3 CSL_FMK SRIO_RXDESC3_SOP CSL_FMK SRIO_RXDESC3_EOP CSL_FMK SRIO_RXDESC3_OWNERSHIP 1 CSL_FMK SRIO_RXDESC3_EOO CSL_FMK SRIO_RXDESC3_TEARDOWN O CSL_FMK SRIO_RXDESC3_CC 0 CSL_FMK SRIO_RXDESC3_MESSAGE_LENGTH MLEN_512DW SPRUE13A September 2006 Serial RapidlO SRIO 61 Submit Documentation Feedback Wi TEXAS INST
199. _REGO Field Descriptions cceeeeeee sete eee eee esses tees nenn nn nun nun nn 185 89 LSUn_REG1 Registers and the Associated LSUS EEN EEN 156 90 LSUn Control Register 1 LSUn_REG1 Field Descriptions cceeeeeee eee e eee eee eens nun eee nun nun nun nn 156 91 LSUn_REG2 Registers and the Associated LSUS ceceeeeeee seen eens ence nese eee eeeeae nun nnnnun nun nannenn 157 92 LSUn Control Register 2 LSUn_REG2 Field Descriptions cceeeeeee seen ee eee nese eee eeeeeeeeeeeeeeeeeee 157 93 LSUn_REG3 Registers and the Associated LSUS ceceeeeeeeeeeeee eee e ence eens eeeeeeeeeeeeeeeeeeeeeeneneee 158 94 LSUn Control Register 3 LSUn_REG3 Field Descriptions c eeeeeee sees eee eee eens nun nn nn nun nun nennen 158 95 LSUn_REG4 Registers and the Associated LSUS ceceeeeeee eee eee eee eeeeeeeeeeeeeeeee tees eeeeeeeeaeeneneee 159 96 LSUn Control Register 4 LSUn_REG4 Field Descriptions cceeeeeee seen eee e cence eee mann nun nun nun nun nn 159 97 LSUn_REGS5 Registers and the Associated LSUS nun nnnnnn 160 98 LSUn Control Register 5 LSUn_REGS5 Field Descriptions cceeeeeee seen eee eee estes nun nannnn nun nennen 160 SPRUE13A September 2006 List of Tables 11 Submit Documentation Feedback 12 99 LSUn_REG6 Registers and the Associated LSUS seceeeeeee seen eee eeeeeeee ee eeeeeeeee nun nnnnun nun nennen 161 100 LSUn Control Register 6 LSUn_REG6 Field Descriptions
200. a TX programming error has occurred where duplicate segments or segments outside the MSGLEN were sent Upon successful reception of any message segment the RX CPPI is responsible for sending a DONE response to the sender Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description If a RX message s length is greater than that of the targeted buffer descriptor an ERROR response is sent back to the source device In addition the DSP is notified with the use of the CC field of the RX CPPI buffer descriptor described as follows This situation can result from a DSP software error misallocating a buffer for the queue or as a result of sender error sending to a wrong mailbox An RX transaction timeout is used by all multi segment queues in order to not hang receive mailbox resources in the event that a message segment is lost in the fabric This response to request timer controls the time out period for sending a response packet and receiving the next request packet of a given multi segment message It has the same value and is analogous to the request to response timer discussed in the TX CPPI and LSU sections which is defined by the 24 bit value in the port response time out CSR See Section 2 3 3 3 The RapidlO Interconnect Specification states that the maximum time interval all 1s is between 3 and 6 seconds Each multi segment receive timer requires a 4
201. a multi segment message xxxx00b xxxx11b 3 bit mailbox number 0 to 3 15 0 SOURCEID 0000h FFFFh Source identification number The SOURCEID field is used to indicate which external device has access to mapper n and its corresponding queue A comparison is performed between the sourcelD of the incoming message packet and the SOURCEID field If the values do not match an ERROR response is sent to the sender and the transaction is logged in the logical layer error management capture registers Table 120 Mailbox to Queue Mapping Register Hn RXU_MAP_Hn Field Descriptions Bit Field Value Description 31 10 Reserved 0 These read only bits return Os when read 9 8 TT Transport type 0 During the sourcelD comparison the incoming sourcelD is compared with the 8 LSBs of the SOURCEID field of RXU_MAP_Ln 1 During the sourcelD comparison the incoming sourcelD is compared with all 16 bits of the SOURCEID field of RXU_MAP_Ln SPRUE13A September 2006 Serial RapidlO SRIO 179 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com Table 120 Mailbox to Queue Mapping Register Hn RXU_MAP_Hn Field Descriptions continued Bit Field Value Description 7 6 Reserved 0 These read only bits return Os when read 5 2 QUEUE_ID 0 15 Queue identification number This field selects which of the 16 RX buffer queues is associated with mapper n
202. able 84 Interrupt sources are mapped to an interrupt decode register only if the ICRRs routes the interrupt source to the corresponding physical interrupt Each status decode bit is a logical OR of multiple interrupt sources that are mapped to the same bit For additional programming see Section 4 5 Table 83 INTDSTn_DECODE Registers and the Associated Interrupt Destinations Register Address Offset Associated Interrupt Destination INTDSTO_DECODE 0300h INTDSTO INTDST1_DECODE 0304h INTDST1 INTDST2_DECODE 0308h INTDST2 INTDST3_DECODE 030Ch INTDST3 INTDST4_DECODE 0310h INTDST4 INTDST5_DECODE 0314h INTDST5 INTDST6_DECODE 0318h INTDST6 INTDST7_DECODE 031Ch INTDST7 Figure 92 Interrupt Status Decode Register INTDSTn_DECODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ISD31 ISD30 ISD29 ISD28 ISD27 ISD26 ISD25 ISD24 ISD23 ISD22 ISD21 ISD20 ISD19 ISD18 ISD17 ISD16 HO R 0 R 0 HO HO R 0 R 0 HO HO R 0 R 0 HO HO R 0 R 0 HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISD15 ISD14 ISD13 ISD12 ISD11 ISD10 ISD9 ISD8 ISD7 ISD6 ISD5 ISD4 ISD3 ISD2 ISD1 ISDO HO R 0 R 0 HO HO R 0 R 0 HO HO R 0 R 0 HO HO R 0 R 0 HO LEGEND R Read W Write n Value after reset Table 84 Interrupt Status Decode Register INTDSTn_DECODE Field Descriptions Bit Fie
203. ailed port error threshold has been reached in the Port n Error Rate Threshold Register 24 OUTPUT_DEGRD_ENC Output degraded condition encountered Once set the OUTPUT_DEGRD_ENC bit remains set until software writes a 1 to it 0 The output port has not encountered a degraded condition The output port has encountered a degraded condition The degraded port error threshold has been reached in the Port n Error Rate Threshold Register SPRUE13A September 2006 Serial RapidlO SRIO 203 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com Table 147 Port Error and Status CSR n SPn_ERR_STAT Field Descriptions continued Bit Field Value Description 23 21 Reserved 0 These read only bits return Os when read 20 OUTPUT_RETRY_ENC Output retry condition encountered Once set the OUTPUT_RETRY_ENC bit remains set until software writes a 1 to it The output port has not encountered a retry condition The output port has encountered a retry condition This bit is set when bit 18 is set 19 OUTPUT_RETRIED Output retried OUTPUT_RETRIED is a read only bit The output port has not received a packet retry control symbol The output port has received a packet retry control symbol and cannot make forward progress This bit is set when bit 18 is set and is cleared when a packet accepted or packet not accepted control symbol is received 18 OUTP
204. al Control CSR SP_GEN_CTL Address Offset 113Ch 31 30 29 28 0 MASTER HOST ENABLE DISCOVERED Reserved R W 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n Value after reset Table 139 Port General Control CSR SP_GEN_CTL Field Descriptions Bit Field Value Description 31 HOST A host device is a device that is responsible for system exploration initialization and maintenance Agent or slave devices are typically initialized by Host devices 0 Agent or Slave device Host device 30 MASTER_ENABLE The Master Enable bit controls whether or not a device is allowed to issue requests into the system If the Master Enable is not set the device may only respond to requests 0 Processing element cannot issue requests Processing element can issue requests 29 DISCOVERED This device has been located by the processing element responsible for system configuration 0 The device has not been previously discovered The device has been discovered by another processing element 28 0 Reserved 0 These read only bits return Os when read SPRUE13A September 2006 Serial RapidlO SRIO 199 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 69 Port Link Maintenance Request CSR n SPn_LM_REQ Each of the four ports is supported by a register of this type see Table 140 SPn_LM_REQ is shown in Figure 132 and described in Table 141 Table 140
205. ally routed to all cores and provide notification of a change in the one ICSR while INTDST5 may be globally routed to all cores and provide notification of a change in a different ICSR The routing defaults for an interrupt condition routing bit ICRx are given in Table 39 Table 39 Interrupt Condition Routing Options Field Access Reset Value Value Function ICRx R 0000b 0000b Routed to INTDSTO 0001b Routed to INTDST1 0010b Routed to INTDST2 0011b Routed to INTDST3 0100b Routed to INTDST4 0101b Routed to INTDST5 0110b Routed to INTDST6 0111b Routed to INTDST7 1111b No interrupt destination interrupt source disabled other Reserved Doorbell Interrupt Condition Routing Registers Figure 54 shows the interrupt condition routing registers for Doorbell 0 The other doorbell ICRRs have the same bit field map with the following addresses e DOORBELL1_ICRR and DOORBELL1_ICCR2 Address offsets 0290h and 0294h e DOORBELL2_ICRR and DOORBELL2_ICRR2 Address offset O2A0h and 02A4h e DOORBELL3_ICRR and DOORBELL3_ICRR2 Address offset 02BOh and 02B4h Serial RapidiO SRIO 983 Submit Documentation Feedback Interrupt Conditions da TEXAS INSTRUMENTS www ti com When doorbell packets are received by the SRIO peripheral these ICRRs route doorbell interrupt requests to interrupt destinations For example if ICS6 1 in DOORBELL2_ICSR and ICR6 0010b in DOORBELL2_ICRR the interrupt request fro
206. an be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map2 TX_Queue_Map2 TX_QUEUE_CNTLO 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map3 TX_Queue_Map3 TX_QUEUE_CNTLO 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map4 TX_Queue_Map4 TX_QUEUE_CNTL1 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 7 4 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map5 TX_Queue_Map5 TX_QUEUE_CNTL1 11 8 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 15 12 Number of Msgs Oh to Fh Number of
207. ance thereby impairing system performance Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock via the LB field 00b Frequency dependent bandwidth The PLL bandwidth is set to a twelfth of the frequency of RIOCLK RIOCLK This setting is suitable for most systems that input the reference clock via a low jitter input cell and is required for standards compliance 01b Reserved 10b Low bandwidth The PLL bandwidth is set to a twentieth of the frequency of RIOCLK RIOCLK or 3MHz whichever is larger In systems where the reference clock is directly input via a low jitter input cell but is of lower quality this setting may offer better performance It will reduce the amount of reference clock jitter transferred through the PLL However it also increases the susceptibility to loop noise generated within the PLL itself It is difficult to predict whether the improvement in the former will more than offset the degradation in the latter 11b High bandwidth The PLL bandwidth is set to a eighth of the frequency of RIOCLK RIOCLK This is the setting appropriate for systems where the reference clock is cleaned through an ultra low jitter LC based PLL Standards compliance will be achieved even if the reference clock input to the cleaner PLL is outside the specification for the standard 7 6 Reserved 00h Reserved 5 1 MPY PLL multiply Select PLL multiply factors between 4 and 60 00000b 4x 00001b 5x 00
208. apidlO Physical Layer 1x 4x LP Serial Specification This includes ASIC microprocessor DSP and switch fabric devices from multiple vendors Compliance to the specification can be verified with bus functional models available through the RapidlO Trade Association as well as test suites currently available for licensing 1 5 TI Devices Supported By This Document Table 1 TI Devices Supported By This Document Number of Number of Number of SRIO Module Device DSP Cores CPUs Ports Lanes Configurations Frequency TMS320TCI6482 1 4 4 1x 4x 1x 1x DSP frequency 4 20 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com SRIO Functional Description SRIO Functional Description Overview Peripheral Data Flow This peripheral is designed to be an externally driven slave module that is capable of acting as a master in the DSP system This means that an external device can push burst write data to the DSP as needed without having to generate an interrupt to the CPU or without relying on the DSP EDMA This has several benefits It cuts down on the total number of interrupts it reduces handshaking latency associated with read only peripherals and it frees up the EDMA for other tasks SRIO specifies data packets with payloads up to 256 bytes Many times transactions will span across multiple packets RapidlO specifies a maximum of 16 transactions per message
209. ar Register LSU_ICCR Address Offset 0268h lt Bits for LSU4 gt gem Bits for LSU3 gt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Icc25 cc24 Gan cc22 cc21 cc2o cc19 ccts GC Gg ICC31 ICC30 ICC29 ICC28 ICC27 ICC26 W 0 WO WO W 0 W 0 WO WO WO W 0 WO WO W 0 W 0 WO W 0 W 0 lt Bits for LSU2 gt gem Bits for LSU1 gt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO ICC15 ICC14 ICC13 ICC12 WO W 0 W 0 WO WO W 0 W 0 WO WO LEGEND W Write only n Value after reset W 0 W 0 WO WO W 0 W 0 WO Table 74 LSU Interrupt Condition Clear Register LSU_ICCR Field Descriptions Bit Field Value Description 31 0 ICCx 0 No effect x 31 to 0 1 Clear bit x of the LSU interrupt condition status register LSU_ICSR SPRUE13A September 2006 Serial RapidlO SRIO Submit Documentation Feedback 141 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 24 Error Reset and Special Event Interrupt Condition Status Register ERR_RST_EVNT_ICSR Each of the nonreserved bits in this register indicate the status of a parti
210. be negative data and RIORXn positive 6 5 RATE Operating rate Selects full half or quarter rate operation 00b Full rate Two data samples taken per PLL output clock cycle 01b Half rate One data sample taken per PLL output clock cycle 10b Quarter rate One data sample taken every two PLL output clock cycles 11b Reserved 4 2 BUSWIDTH 000b Bus width Always write 000b to this field to indicate a 10 bit wide parallel bus to the clock All other values are reserved See Section 2 3 2 1 for an explanation of the bus 1 Reserved 0 Always write 0 to this reserved bit 0 ENRX Enable receiver 0 Disable this receiver 1 Enable this receiver Table 58 EQ Bits CFGRX 22 19 Low Freq Gain Zero Freq at ee min 0000b Maximum 0001b Adaptive Adaptive 001xb Reserved 01xxb Reserved Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 58 EQ Bits continued CFGRX 22 19 Low Freq Gain Zero Freq at ea min 1000b Adaptive 1084MHz 1001b 805MHz 1010b 573MHz 1011b 402MHz 1100b 304MHz 1101b 216MHz 1110b 156MHz 1111b 135MHz SPRUE13A September 2006 Serial RapidlO SRIO 127 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com 5 14 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL There are four of these registers to support four por
211. ber 2006 Submit Documentation Feedback at port n rate counting enable field 222 Status field 220 bad CRC in control symbol at port n rate counting enable field 221 Status field 219 detect 4 reset control symbols at port 232 detect multicast event control symbol at port 231 enable interrupt if 4 reset control symbols received at port 232 enable interrupt if multicast event control symbol received at port 231 force insertion of control symbol in outbound packet 240 initiate self reset interrupt if 4 link request control symbols accepted 231 introduction 24 link maintenance command field for portn 240 link maintenance request control symbol generation register 200 packet not accepted control symbol at port n rate counting enable field 221 Status field 220 parameterO field for portn 240 parameter1 field for portn 240 port multicast event control symbol request field 239 stype0 field for portn 240 stype1 field for portn 240 transmit request field for portn 240 unexpected ackID in control symbol at port n rate counting enable field 221 Status field 219 unexpected acknowledge control symbol at port n rate counting enable field 222 Status field 220 unexpected control symbol at port n rate counting enable field 222 status field 220 CORRUPT_CNTL_SYM_EN field of SPn_RATE_EN 221 CORRUPT_CNTL_SYM field of SPn_ERR_DET 219 corrupt control symbol at port n rate counting enable field 221 status field 219 corrupt packet at port n rate counti
212. bit register The register is loaded with the current timecode when the response is sent Each time the timecode changes a 4 bit compare is done to the register If the register becomes equal to the timecode again without the next message segment being seen then the transaction has timed out If this happens the RX buffer resources can be released The buffer descriptor points to the corresponding data buffer in memory and also points to the next buffer descriptor in the queue As segments of a received message arrive the msgseg field of each segment is monitored to detect the completion of the received message Once a full message is received the OWNERSHIP bit is cleared in the packet s buffer descriptor to give control to the host At this point a host interrupt is issued This interface works with programmable interrupt rate control There is an ICSR bit for each supported queue On interrupt the CPU processes the RX buffer queue detecting received packets by the status of the OWNERSHIP bit in each buffer descriptor The host processes the RX queue until it reaches a buffer descriptor with a set OWNERSHIP bit or set EOQ bit Once processing is complete the host updates the RX DMA State Completion Pointer allowing the peripheral to reuse the buffer Figure 19 shows the RX buffer descriptor fields and Table 18 describes them A RX buffer descriptor is a contiguous block of four 32 bit data words aligned on a 32 bit boundary Accesses to these r
213. ble 67 The general form of a doorbell interrupt condition clear register is shown in Figure 78 and described in Table 68 For additional programming information see Section 4 4 1 and Section 2 3 6 Table 67 DOORBELLn_ICCR Registers Register Address Offset DOORBELLO_ICCR 0208h DOORBELL1_ICCR 0218h DOORBELL2_ICCR 0228h DOORBELL3_ICCR 0238h Figure 78 Doorbell n Interrupt Condition Clear Register DOORBELLn_ICCR 31 in Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICCO W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 WO WO WO WO WO WO WO WO LEGEND W Write only R Read only n Value after reset Table 68 DOORBELL Interrupt Condition Clear Register DOORBELLn_ICCR Field Descriptions Bit Field Value Description 31 16 Reserved 0 These read only bits return Os when read 15 0 ICCx Doorbell n interrupt condition clear bit Ks 0 No effect 1 a xX of the corresponding doorbell interrupt condition status register SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 133 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 18 RX CPPI Interrupt Status Register RX_CPPI_ICSR The bits in this register indicate any active interrupt requests from RX buffer descriptor queues The RX CPPI interrupt status re
214. ce type field 182 device wakeup after bootloading 80 differential signals pins 25 direct I O data path description 39 introduction 35 RX operation 42 TX operation 40 disable error checking for portn 207 disable portn 207 DISCOVERED field of SP_LGEN_CTL 199 DISCOVERY_TIMER field of SP_IP_DISCOVERY_TIMER 230 DMA bus considerations regarding CPU interrupts 85 in data path description for LSUs 39 in direct I O RX operation 42 in Load Store module data flow diagram 39 in message passing 43 in SRIO component block diagram 26 DMA clock frequency as variable in clock prescaling 233 DMA error status bit for MAU 211 doorbell information field for LSUn 160 doorbell interrupt condition clear registers 133 doorbell interrupt condition routing registers 144 244 Index doorbell interrupt condition status registers 132 DOORBELLn_ICCR 133 DOORBELLn_ICRR 144 DOORBELLn_ICRR2 144 DOORBELLn_ICSR_ 132 doorbell operation 63 doorbell packets Ftype and Ttype 25 packet header 64 priority 64 used to cause CPU interrupts 85 doorbell retry response during direct I O reception 42 doorbell support for destination device 189 doorbell support for source device 188 DRBLL_INFO field of LSUn_REG5 160 drop packet enable for portn 207 DSP address field for LSUn 157 E EF_ID field of ERR_RPT_BH 209 EF_ID field of SP_MB_HEAD 196 EF_PTR field of ERR_RPT_BH 209 EF_PTR field of SP_MB_HEAD 196 emulation 74 EN_STAT field of BLKn_EN_STAT 120 enable and enable
215. cessed buffer descriptor ownership 1 e Writes CP value of last buffer descriptor processed e Port hardware clears ICSR bit only if the CP value written by CPU equals port written value in the RX DMA State CP register e Resets interrupt pacing value TX Operation Sets up associated buffer descriptor memory CPPI RAM or L2 RAM e Link lists the buffer descriptors next_descriptor_pointer e Assigns buffer descriptor to data buffer buffer_pointer e CPU writes buffer descriptors and sets ownership 1 for each used e Specifies RIO fields Dest_id Pri tt Mailbox e Sets parameters PortID Message_length e Port starts queue transmit on CPU write to HDP for up to 16 queues TX DMA State HDP e Port processes corresponding queues until ownership 0 or next_descriptor_pointer all Os Port sets eoq 1 and writes all Os to the HDP e When each packet transmission is complete the port sets ownership 0 and issues an interrupt to the CPU by writing the last processed buffer descriptor address to the CP TX DMA State CP Processes interrupt e The CPU processes the buffer queue to reclaim buffers If ownership 0 the packet has been transmitted and the buffer is reclaimed e CPU processes the queue until eoq 1 or ownership 1 e CPU determines all packets have been transmitted if ownership 0 eoq 1 and next_descriptor_pointer all Os in last processed buffer descriptor e CPU acknowledges the interrupt after re claiming al
216. ciptions 190 131 Local Configuration Space Base Address 0 CSR LCL_CFG_HBAR Field Descriptions 0655 191 132 Local Configuration Space Base Address 1 CSR LCL_CFG_BAR Field Descriptions 0000 192 133 Base Device ID CSR BASE_ID Field Descriptions ceceeee eee cece ee ee ee eee e eee e ee nun nun nnun nun nun nun nenn 193 134 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK Field Descriptions A 194 135 Component Tag CSR COMP_TAG Field Descriptions ccceee eee eee ee eee eect eee e eee ee nun nn un nun une nnn 195 136 1x 4x LP_Serial Port Maintenance Block Header Register SP_MB_HEAD Field Descriptions 196 137 Port Link Timeout Control CSR SP_LT_CTL Field Descriptions ceceeeeeeeee eens na nun nn nn nun en nun 197 138 Port Response Time Out Control CSR SP_RT_CTL Field Descriptions uuusssunnennennnannnnnan ann 198 139 Port General Control CSR SP_GEN_CTL Field Descriptions cccceee cece cece ences eee eee eeeeeeeeeeneee 199 140 SPn_LM_REQ Registers and the Associated Ports ccceeeeeeeee eee nennen nenn eee ee nun nennen nun nn en nenn 200 141 Port Link Maintenance Request CSR n SPn_LM_REQ Field Descriptions 0 eeeeeeeeeeeeeeeeeeees 200 142 SPn_LM_RESP Registers and the Associated Porte 201 143 Port Link Maintenance Response CSR n SPn_LM_RESP Field Descriptions cceeeeeeeeeeeeeeeeeeee 201 144 SPn_ACKID_STAT Registe
217. ck ze SIE arola El S d RX recovery Son decode dE DMA Cc an 567706 sb g 3 XOX Tex P2sf_cik_____ 8 rz R S 10b _ ei S OD D DXX jrx Pz ck bosing a8 2 10b 3 ki 5 a X_X_ XS TX P28 OK coding FIFOR2 I Command DOCKS IX Past ei ong EAFF registers Clock domain 1 Clock domain 2 Clock domain 3 Within the physical layer the data next goes to the 8 bit 10 bit 8b 10b decode block 8b 10b encoding is used by RapidlO to ensure adequate data transitions for the clock recovery circuits Here the 20 encoding overhead is removed as the 10 bit data is decoded to the raw 8 bit data At this point the recovered byte clock is still being used The next step is clock synchronization and data alignment These functions are handled by the FIFO and lane de skewing blocks In the Handi Interconnect Specification a lane is one serial differential pair The FIFO provides an elastic store mechanism used to hand off between the recovered clock domains and a common system clock After the FIFO the four lanes are synchronized in frequency and phase whether 1X or 4X mode is being used The FIFO is 8 words deep The lane de skew is only meaningful in the 4X mode where it aligns each channel s word boundaries such that the resulting 32 bit word is correctly aligned The CRC error detection block keeps a running tally of the incoming data and computes the expected CRC value for the 1X or 4X mode The expected value is
218. cket Forwarding Register n for 16 Bit Device IDs PF_16B_CNTLn There are four of these registers see Table 52 The general form of a packet forwarding register for 16 bit DevicelDs is shown in Figure 72 and described in Table 53 For additional programming information see Section 2 3 15 and Section 2 3 15 3 Table 52 PF_16B_CNTL Registers Register Address Offset PF_16B_CNTLO 0090h PF_16B_CNTL1 0098h PF_16B_CNTL2 00A0h PF_16B_CNTL3 00A8h Figure 72 Packet Forwarding Register n for 16 Bit Device IDs PF_16B_CNTLn 31 16 15 0 16BIT_DEVID_UP_BOUND 16BIT_DEVID_LOW_BOUND R W FFFFh R W FFFFh LEGEND R W Read Write n Value after reset Table 53 Packet Forwarding Register n for 16 Bit DevicelDs PF_16B_CNTLn Field Descriptions Bit Field Value Description 31 16 16BIT_DEVID_UP_BOUND 0000h FFFFh Upper 16 bit DevicelD boundary DestID above this range cannot use the table entry 15 0 16BIT_DEVID_LOW_BOUND 0000h FFFFh Lower 16 bit DevicelD boundary DestID lower than this number cannot use the table entry SPRUE13A September 2006 Serial RapidlO SRIO 123 Submit Documentation Feedback SRIO Registers 5 12 Packet Forwarding Register n for 8 Bit Device IDs PF_8B_CNTLn There are four of these registers see Table 54 The general form of a packet forwarding register for 16 bit DevicelDs is shown in Figure 73 and described in Table 55 For additiona programming information see Section 2
219. cket response timeout endpoint device only A timeout has not been detected by an LSU or the TXU A timeout has been detected by an LSU or the TXU A required response has not been received by the LSU TXU within the specified timeout interval To clear this bit write 0 to it 23 UNSOLICITED_RSPNS Unsolicited response switch or endpoint device An unsolicited response packet has not been received by an LSU or the TXU An unsolicited response packet has been received by an LSU or the TXU To clear this bit write 0 to it 22 UNSUPPORTED_TRANS Unsupported transaction switch or endpoint device The MAU has not received an unsupported transaction The MAU has received an unsupported transaction That is the MAU received a transaction that is not supported in the destination operations CAR To clear this bit write O to it Reserved These read only bits return O when read RX_CPPI_SECURITY RX CPPI security error The RXU has not detected an access block The RXU has detected an access block That is access to one of the RX queues was blocked To clear this bit write O to it RX_IO_DMA_ACCESS RX IO DMA access error A DMA access to the MAU has not been blocked A DMA access to the MAU was blocked To clear this bit write 0 to it Reserved These read only bits return O when read 84 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INS
220. contiguous messages descriptors to process before moving to TX_Queue_Map6 TX_Queue_Map6 TX_QUEUE_CNTL1 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map7 TX_Queue_Map7 TX_QUEUE_CNTL1 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map8 TX_Queue_Map8 TX_QUEUE_CNTL2 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 7 4 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map9 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 175 SRIO Registers 176 da TEXAS INSTRUMENTS www ti com Table 117 Transmit CPPI Weighted Round Robin Control Register Field Descriptions continued Field Pair Register Bits Field Value Description TX_Queue_Map9 TX_QUEUE_CNTL2 11 8 Queue Pointer Oh to
221. cribed in Table 138 For additional programming information see Section 2 3 3 3 and Section 2 3 3 Figure 130 Port Response Time Out Control CSR SP_RT_CTL Address Offset 1124h 31 TIMEOUT_VALUE RW FFFFFFh 8 7 0 TIMEOUT_VALUE Reserved RW FFFFFFh R 00h LEGEND R W Read Write R Read only n Value after reset Table 138 Port Response Time Out Control CSR SP_RT_CTL Field Descriptions Bit Field Value Description 31 8 TIMEOUT_VALUE 000000h Timeout value for all ports on the device This timeout is for sending a packet to to receiving the corresponding response packet Max value represents 3 to 6 FFFFFFh seconds The timeout duration can be expressed as Timeout 15 x Prescale Value 1 x DMA Clock Period x Timeout Value where Prescale value is set in PER_SET_CNTL offset 0020h and the Timeout value is the decimal representation of this register value For example given a 400 MHz DMA a Prescale Value of 4 and a Timeout Value of FFFFFFh the Timeout duration would be Timeout 15 x 4 1 x 2 5 ns x 16777216 3 15 s 7 0 Reserved 00h These read only bits return Os when read 198 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 68 Port General Control CSR SP_GEN_CTL The port general control CSR SP_GEN_CTL is shown in Figure 131 and described in Table 139 Figure 131 Port Gener
222. ct I O packets With direct I O the RapidlO packet contains the specific address where the data should be stored or read in the destination device Direct I O requires that a RapidlIO source device keep a local table of addresses for memory within the destination device Once these tables are established the RapidlO source controller uses this data to compute the destination address and insert it into the packet header The RapidlO destination peripheral extracts the destination address from the received packet header and transfers the payload to memory via the DMA When a CPU wants to send data from memory to an external processing element PE or read data from an external PE it provides the RIO peripheral vital information about the transfer such as DSP memory address target device ID target destination address packet priority etc Essentially a means must exist to fill all the header fields of the RapidlO packet The Load Store module provides a mechanism to handle this information exchange via a set of MMRs acting as transfer descriptors These registers shown in Figure 12 are addressable by the CPU through the configuration bus Upon completion of a write to LSUn_REGS5 a data transfer is initiated for either an NREAD NWRITE NWRITE_R SWRITE ATOMIC or MAINTENANCE RapidIO transaction Some fields such as the RapidlO srcT D targetTID field are assigned by hardware and do not have a corresponding command register field Serial RapidiO S
223. ction 5 98 14314h SP3_CS_TX Port 3 Control Symbol Transmit Register Section 5 99 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 2 Peripheral Identification Register PID The peripheral identification register PID is a read only register that contains the ID and ID revision number for that peripheral The PID stores version information used to identify the peripheral Writes have no effect to this register The values are hard coded and will not change from their reset state The peripheral ID register PID is shown in Figure 63 and described in Table 41 Figure 63 Peripheral ID Register PID Address Offset 0000h 31 24 23 16 Reserved TYPE R 00h R 01h 15 8 7 0 CLASS REV R OAh R 01h LEGEND R W Read Write R Read only n Value after reset Table 41 Peripheral ID Register PID Field Descriptions Bit Field Value Description 31 24 Reserved Reserved 23 16 TYPE Peripheral type Identifies the type of the peripheral RIO 15 8 CLASS Peripheral class Identifies the class Switch Fabric 7 0 REV Peripheral revision Identifies the revision of the peripheral This value should begin at O1h and be incremented each time the design is revised SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 111 da TEXAS INSTRUMENTS www ti co
224. ction with 2 selectable thresholds 00b Disabled Loss of signal detection disabled O1b High threshold Loss of signal detection threshold in the range 85 to 195MV ipp This setting is suitable for Infiniband 10b Low threshold Loss of signal detection threshold in the range 65 to 175MVtpp This setting is suitable for PCI E and S ATA 11b Reserved 13 12 ALIGN Symbol alignment Enables internal or external symbol alignment 00b Alignment disabled No symbol alignment will be performed while this setting is selected or when switching to this selection from another O1b Comma alignment enabled Symbol alignment will be performed whenever a misaligned comma symbol is received 10b Alignment jog The symbol alignment will be adjusted by one bit position when this mode is selected that is the ALIGN value changes from Oxb to 1xb 11b Reserved 11 Reserved 0 This read only bit returns 0 when read 10 8 TERM 001b Input termination The only valid value for this field is 001b This value sets the common point to 0 8 VDDT and supports AC coupled systems using CML transmitters The transmitter has no effect on the receiver common mode which is set to optimize the input sensitivity of the receiver Common mode termination is via a 50 pF capacitor to VSSA 7 INVPAIR Invert polarity Inverts polarity of RIORXn and RIORXn 0 Normal polarity RIORXn is considered to be positive data and RIORXn negative 1 Inverted polarity RIORXn is considered to
225. cular interrupt condition in one or more of the SRIO ports ERR_RST_EVNT_ICSR is shown in Figure 85 and described in Table 75 For additional programming information see Section 4 3 4 Figure 85 Error Reset and Special Event Interrupt Condition Status Register ERR_RST_EVNT_ICSR Address Offset 0270h 31 17 16 Reserved ICS16 HO HO 15 12 11 10 9 8 7 3 2 1 0 Reserved ICS11 ICS10 ICS9 ICS8 Reserved ICS2 ICS1 ICSO R 0 RO RO RO RO R 0 RO RO RO LEGEND R Read only W Write only n Value after reset Table 75 Error Reset and Special Event Interrupt Condition Status Register ERR_RST_EVNT_ICSR Field Descriptions Bit Field Value Description 31 17 Reserved 0 These reserved bits return Os when read 16 ICS16 0 Device reset interrupt not received from any port 1 Device reset interrupt received from any port 15 12 Reserved 0 These reserved bits return Os when read 11 ICS11 0 Error not detected on port 3 1 Error detected on port 3 10 ICS10 0 Error not detected on port 2 1 Error detected on port 2 9 ICS9 0 Error not detected on port 1 1 Error detected on port 1 8 ICS8 0 Error not detected on port 0 1 Error detected on port 0 7 3 Reserved 0 These reserved bits return Os when read 2 ICS2 0 Logical layer error management event capture not detected 1 Logical layer error management event capture detected 1 ICS1 0 Port write in request no
226. d is now defined as P 2 x 16 F This means the countdown timer frequency needs to be 44 7 89 5 MHz for a 6 3 second response timeout Since the needed timer frequency is derived from the DMA bus clock which is device dependent the hardware supports a programmable configuration register field to properly scale the clock frequency This configuration register field is described in the Peripheral Setting Control register Address offset 0020h The CPU initiates a TX queue teardown by writing to the TX Queue Teardown command register Teardown of a TX queue will cause the following actions e No new messages will be sent e All messages single and multi segment already started will be completed Failing to complete the message TX would leave an active receiver blocked waiting for the final segments until the transaction eventually times out Note that normal TX State Machine operation is to not send any more segments once an error response has been received on any segment So if the receiver has also been torn down and is receiving error responses multi segment transmit will complete as soon as all in transit segments have been responded to e When all in transit messages segments have been responded to teardown will be completed as follows If the queue is active the teardown bit will be set in the next buffer descriptor in the queue The peripheral completes the teardown procedure by clearing the HDP register setting t
227. der This address is used directly for the internal DSP transfers and is not modified in any way For this reason multi cast support is limited to groups containing devices with the same memory map or other devices that can perform address translation It is the responsibility of the system designer to pre determine valid multi cast address ranges When a packet is received the packet s tt field and DestID are checked against the main DevicelD offset 0x0080 and the MulticastID see Table 31 If there is no match the packet is destroyed and not forwarded to the logical layer If there is a match it is forwarded to the logical layer Since multicast operations are defined to be operations that do not require responses they are limited to NWRITE and SWRITE operations and forwarded to the MAU As an endpoint device the peripheral accepts packets based on the destination ID Two options exist for packet acceptance and are mode selectable The first option is to only accept packets whose DestIDs match the local devicelD in 0x0080 This provides a level of security The second option is is system multicast operation Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com SRIO Functional Description Table 31 Multicast DevicelD Operation Local DevicelD Multicast DevicelD Device Register Offset Register Offset Endpoint Device Requirements TMS320TC16482 0080h 0084h Accepts discrete multip
228. during TX operation 59 TX buffer descriptor fields 52 TX buffer descriptor link list figure 62 TX descriptor pointers 51 TX operation 51 weighted round robin transmission scheme 54 message request packet header fields 44 message request timeout at RXU reporting enable field 212 status field 211 message segment associated with logical transport error 217 message support for destination device 189 message support for source device 188 MLTC_EN field of SP_IP_MODE 231 MLTC_IRQ field of SP_IP_MODE 231 248 Index MMRs enable bit 119 MMRs enable status bits 118 120 mode selection field for ports 231 MPY field of SERDES_CFGn_CNTL 130 MPY value versus frequency range 30 MSB_DESTID field of ID_CAPT 216 MSB_SOURCEID field of ID_CAPT 216 MSBs of address associated with logical transport error 214 MSBs of destination ID associated with logical transport error 216 MSBs of source ID associated with logical transport error 216 MSG_ERR_RESP_ENABLE field of ERR_EN 212 MSG_ERR_RSPNS field of ERR_DET 210 MSG_REQ_TIMEOUT_ENABLE field of ERR_EN 212 MSG_REQ_TIMEOUT field of ERR_DET 210 MSGINFO field of CTRL_CAPT 217 MULT_EVNT_CS field of SPn_MULT_EVNT_CS 239 MULTICAST_PARTICIPANT field of SPn_CTL 206 multicast event control symbol request field for port n 239 multicast event interrupt enable field for ports 231 multicast event interrupt status field for ports 231 multicast event participant enable field for portn 207 multiple ports
229. e SPRUE13A September 2006 Serial RapidlO SRIO 75 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device in which case a re ordering algorithm is used The algorithm searches backward through the buffer group for the first packet with the highest priority If there are no higher priority packets in the queue the current packet is sent again As an example of the re ordering algorithm suppose a physical layer buffer group contains packets with the following priorities 00123310 where the leftmost 0 represents the packet that was the first in or the head of the queue If this packet is retried the next packet to be sent is the earliest packet with priority 3 the lefthand 3 If that packet is sent successfully the physical layer attempts to send the original retried packet again otherwise the physical layer repeats the re ordering algorithm 2 3 12 2 Single Port With 1x or 4x Operation In the case when only one portis used logical layer buffers are grouped per priority Each priority is 8 buffers deep A counter is maintained for each priority to track available buffer credit across the UDI The count is initialized to 8 credits per port The count is decremented each time a packet is sent across the UDI for a port Each port buffer group has a buffer release signal which indicates the relea
230. e 148 and described in Table 165 da TEXAS INSTRUMENTS www ti com Table 164 SPn_ERR_CAPT_DBG1 Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_CAPT_DBG1 204Ch Port 0 SP1_ERR_CAPT_DBG1 208Ch Port 1 SP2_ERR_CAPT_DBG1 20CCh Port 2 SP3_ERR_CAPT_DBG1 210Ch Port 3 Figure 148 Port n Error Capture CSR 1 SPn_ERR_CAPT_DBG1 31 CAPTUREO LEGEND R Read only n Value after reset R 00000000h Table 165 Port n Error Capture CSR 1 SPn_ERR_CAPT_DBG1 Field Descriptions Bit Field Value Description 31 0 CAPTUREO 00000000h In the case of a control symbol error to Control character and control symbol that correspond to the error FFFFFFFFh In the case of a packet error Bytes 0 to 3 of the packet header that corresponds to the error 224 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com SRIO Registers 5 86 Port n Error Capture CSR 2 SPn_ERR_CAPT_DBG2 Each of the four ports is supported by a register of this type see Table 166 SPn_ERR_CAPT_DBG2 is shown in Figure 149 and described in Table 167 Table 166 SPn_ERR_CAPT_DBG2 Registers and the Associated Ports Register Address Offset Associated Port SPO_ERR_CAPT_DBG2 2050h Port 0 SP1_ERR_CAPT_DBG2 2090h Port 1 SP2_ERR_CAPT_DBG2 20D0h Port 2 SP3_ERR_CAPT_DBG2 2110h Port 3 Figure 149 Port n Error Capture CSR 2 SPn_ERR_CAPT_
231. e 188 READ transactions during direct I O transmission 41 receive CPPI control register 173 receive CPPI interrupt condition clear register 135 receive CPPI interrupt condition routing registers 145 receive CPPI interrupt condition status register 134 receive queue teardown register 172 receiver enabling for SERDES macro introduction 30 receiver enable bit 126 receive transmit lockout field for portn 207 register configuration offset field for LSUn 156 register introduction 102 reinitialization process field for portn 236 related documentation 14 reordering of outbound packets 75 reporting thresholds for port n errors broken link case 229 degraded link case 229 request packets Ftypes and Ttypes 25 in SRIO operation sequence 22 requirements for external devices 20 reset and power down 70 CPPI module 59 enable and enable status registers 71 Load Store module 43 software shutdown details 74 reset interrupt enable field for ports 232 reset interrupt status field for ports 232 reset option CSR for portn 235 RESPONSE _VALID field of SPn_LM_RESP 201 response packets Ftypes and Ttypes 25 in SRIO operation sequence 22 responses to CPPI message transmissions 58 response time out error at LSU or TXU reporting enable field 213 status field 211 response timer in direct I O reception 42 in Load Store module data flow diagram 39 in message reception 47 in message transmission 59 RETRANSMIT_SUPPRESS field of PE_FEAT 186 retry_count field of TX b
232. e DMA bus interface For example if the GBL_EN is asserted in the middle of a DMA transfer from the peripheral this could hang the bus The procedure to follow is 1 Stop all RapidlO source transactions including LSU and TXU operations The four LSU blocks should indiciate a BSY status of Ob offsets 0418h 0438h 0458h 0478h If an EDMA channel is used for driving the LSU it must be stopped to prevent new additional transfers This procedure is outside the scope of this specification Teardown of the TXU queues is accomplished by writing OOOOFFFFh to RIO_TX_QUEUE_TEAR_DOWN offset 0700h Hardware will then tear down the queues and clear these bits automatically when the teardown is complete 2 Stop all RapidlO message receive RXU operations Teardown of the RXU queues is accomplished by writing OOOOFFFFh to RIO_RX_QUEUE_TEAR_DOWN offset 0740h Hardware will then tear down the queues and clear these bits automatically when complete 3 Once teardown is complete clear the PEREN bit of the RIO_PCR offset 0004h to stop all new logical layer transactions 4 Wait 1 second to finish any current DMA transfer 5 Deassert GBL_EN offset 0030h 2 3 11 Emulation Expected behavior during emulation halt is controlled within the peripheral by the SOFT and FREE bits of the peripheral control register PCR These bits are shown in Figure 40 and described in Table 29 Figure 40 Peripheral Control Register PCR Address Offset 0004h
233. e that when the PROMISCUOUS bit is set the mailbox letter and corresponding mask bits are still in effect When the PROMISCUOUS bit is cleared it equals a mask value of FFFFh and only a request with the matching sourcelD is allowed access to the mailbox Each table entry also indicates if it used for single or multi segment message mapping Single segment message mapping entries utilize all six bits of the mailbox and corresponding mask fields Multi segment entries uses only the 2 LSBs The number of simultaneous supported multi segment messages is determined by the number of dedicated RX queues as discussed further below It is recommended to dedicate a multi segment mapping entry for each supported simultaneous letter Essentially letter masks should be avoided for multi segment mapping to reduce excessive retries Note that it is possible to configure the table entries such that incoming single segment and multi segment messages are directed to the same queue To avoid this condition properly program the mapping table entries SPRUE13A September 2006 Serial RapidlO SRIO 45 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Functional Description Figure 18 Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n RXU_MAP_L n 31 30 29 24 23 22 21 16 LETTER_MASK MAILBOX_MASK LETTER MAILBOX R W 11 R W 111111 R W 00 R W 000000 15 E SOURCEID
234. edge control symbol 19 PKT_UNEXPECTED_ACKID Unexpected ackID in packet The port did not receive a packet with unexpected out of sequence ackID The port received a packet with unexpected out of sequence acklD 18 RCVD_PKT_WITH_BAD_CRC Bad CRC in packet The port did not receive a packet with a bad CRC value The port received a packet with a bad CRC value 17 RCVD_PKT_OVER_276B Oversize packet The port did not receive packet that exceeds the maximum allowed size The port received packet that exceeds the maximum allowed size 16 6 Reserved These read only bits return Os when read NON_OUTSTANDING_ACKID Non outstanding ackID The port did not receive a link response with a non outstanding ackID The port received a link response with an ackID that is not outstanding The capture registers do not have valid information during this error detection PROTOCOL_ERROR Protocol error The port did not receive an unexpected packet or control symbol The port received an unexpected packet or control symbol Reserved This read only bit returns 0 when read DELINEATION_ERROR Delineation error The port did not detect a delineation error The port detected a delineation error The port received an unaligned SC or PD or undefined code group The capture registers do not have valid information during this error detection UNSOLICITED_ACK_CNTL_SYM Unsolicited acknowledge
235. eeeneee 193 126 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK Address Offset 10G9h 194 127 Component Tag CSR COMP_TAG Address Offset 106Ch ursussennnunennnannnunnnnnannnun nun nun nun nenn 195 128 1x 4x LP_Serial Port Maintenance Block Header Register SP_MB_HEAD Address Offset 1100h 196 129 Port Link Time Out Control CSR SP_LT_CTL Address Offset 1120 197 130 Port Response Time Out Control CSR SP_RT_CTL Address Offset 1124 198 131 Port General Control CSR SP_GEN_CTL Address Offset 112Ch eens eee nun nun nennen 199 132 Port Link Maintenance Request CSR n SPn_LM_REQ eee eee eee eee nun nun nun unnnnnnnnn nun nun nun 200 133 Port Link Maintenance Response CSR n SPn_LM_RESP ceeceeee eee e eee eee eee eee e eee ee seen nun nun nun nun 201 134 Port Local AckID Status CSR oi Gbn ACKID GIATI eee ee eee eee eee eee eee e eee ee eee eee eeee eae anne 202 135 Port Error and Status CSR n SPN ERR STAT eee eee iensen iani esirinda aneneen Ene asama 203 136 Porm ControlGSRin SPI Ee 206 137 Error Reporting Block Header Register ERR_RPT_BH Address Offset 2000 209 138 Logical Transport Layer Error Detect CSR ERR_DET Address Offset 2008h 0 ceeeeeeeeeeeeeeees 210 139 Logical Transport Layer Error Enable CSR ERR EN Address Offset 200Ch 212 140 Logical Transport Layer High Address Capture CSR H_ADDR_CAPT Address Offset 2010h 214 141 Logical Transport Layer Address Cap
236. egister If the register becomes equal to the timecode again without a response being seen then the transaction has timed out Essentially instead of the 24 bit value representing the period of the response timer the period is now defined as P 224 x 16 F This means the countdown timer frequency needs to be 44 7 89 5Mhz for a 6 3 second response timeout Because the needed timer frequency is derived from the DMA bus clock which is device dependent the hardware supports a programmable configuration register field to properly scale the clock frequency This configuration register field is described in the Peripheral Setting Control register Address offset 0020h If a response packet indicates ERROR status the Load Store module notifies the CPU by generating an error interrupt for the pending non posted transaction If the response has completed successfully and the Interrupt Req bit is set in the control register the module generates a CPU servicing interrupt to notify the CPU that the response is available The control command registers can be released as soon as the response packet is received by the logical layer The hardware is not responsible for attempting a retransmission of the non posted transaction If a Doorbell response packet indicates Retry status the Load Store module notifies the CPU by generating an interrupt The control command registers can be released as soon as the response packet is received by the logical lay
237. egisters These registers route LSU interrupt requests from LSU_ICSR to interrupt destinations For example if ICS4 1 in LSU_ICSR and ICR4 0000b in LSU_ICRRO LSU1 has generated a transaction timeout interrupt request and that request is routed to interrupt destination 0 For additional programming see Section 4 4 1 2 LSU Interrupt Condition Routing Register 0 LSU_ICRRO Address Offset 02E0h Figure 90 LSU Interrupt Condition Routing Registers 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 LSU Interrupt Condition Routing Register 1 LSU_ICRR1 Address Offset 02E4h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LSU Interrupt Condition Routing Register 2 LSU_ICRR2 Address Offset 02E8h 31 28 27 24 23 20 19 16 ICR23 ICR22 ICR21 ICR20 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR19 ICR18 ICR17 ICR16 R W 0000 R W 0000 R W 0000 R W 0000 LSU Interrupt Condition Routing Register 3 LSU_ICRR3 Address Offset 02ECh 31 28 27 24 23 20 19 16 ICR31 ICR30 ICR29 ICR28 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 43 0 ICR27 ICR26 ICR25 ICR24 R W 0000 R
238. egisters are restricted to 32 bit boundaries Figure 19 RX Buffer Descriptor Fields Bit Fields t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 J10 a 8 7 16 5 Ja 3 2 next_descriptor_pointer 1 buffer ES reserved mailbox reserved message_length D THA ODEO BSBeoanooe Word Offse 0 RS Field Description Table 18 RX Buffer Descriptor Field Descriptions next_descriptor_pointer Next Descriptor Pointer The 32 bit word aligned memory address of the next buffer descriptor in the RX queue This references the next buffer descriptor from the current buffer descriptor If the value of this pointer is zero then the current buffer is the last buffer in the queue The DSP core sets the next_descriptor_pointer buffer_pointer Buffer Pointer The byte aligned memory address of the buffer associated with the buffer descriptor The DSP core sets the buffer_pointer sop 1 Start of Message Indicates that the descriptor buffer is the first buffer in the message e This bit will always be set as this device only supports one buffer per message eop 1 End of Message Indicates that the descriptor buffer is the last buffer in the message e This bit will always be set as this device only supports one buffer per message SPRUE13A September 2006 Serial RapidlO SRIO 47 Submit Documentation Feedback SRIO Functional Description da TEXAS INSTRUMENTS
239. eld 232 port write maintenance operation 63 port write pending status field 204 port write repeat period field 230 port write request port ID 235 port write target device IDCSR 218 posted WRITE operations during direct I O transmission 41 power down state CPPI module 59 Load Store module 43 PRESCALE field of IP_PRESCAL 233 PRESCALER_SELECT field of PER_SET_CNTL 113 pri field of RX buffer descriptor 47 pri field of TX buffer descriptor 52 priority arbiter for single port transmission 76 PRIORITY field of LSUn_REG4 159 priority of doorbell packets 64 priority transmit credit thresholds 113 processing element features CAR 186 processing element logical layer control CSR 190 PROCESSOR field of PE_FEAT 186 processor present field 186 PROMISCUOUS field of RXU_MAP_Hn description 178 introduction 45 PROTOCOL_ERROR_EN field of SPn_RATE_EN 221 PROTOCOL_ERROR field of SPn_ERR_DET 219 PW_CAPTO field of SP_IP_PW_IN_CAPTO 234 PW_CAPT1 field of SP_IP_PW_IN_CAPT1 234 PW_CAPT2 field of SP_IP_PW_IN_CAPT2 234 PW_CAPTS field of SP_IP_PW_IN_CAPT3 234 SPRUE13A September 2006 Submit Documentation Feedback PW_DIS field of SP_IP_MODE 231 PW_EN field of SP_IP_MODE 231 PW_IRQ field of Sp Ip MODE 231 PW_TGT_ID 218 PW_TIMER field of SP_IP_DISCOVERY_TIMER 230 Q QUEUE ID field of RXU_MAP_Hn 178 QUEUEn_FLOW_MASK fields of TX_CPPI_FLOW_MASKSI O 7 169 QUEUEn_IN_ORDER fields of RX_CPPI_CNTL 173 QUEUEn RXDMA CP 167 QUEUEn_RXDMA_HDP 166 QUEUEn_TE
240. eld Descriptions Bit Field Value Description 31 3 Reserved 0 2 0 EXTENDED_ADDRESSING_CONTROL These read only bits return Os when read Controls the number of address bits generated by the PE as a source and processed by the PE as the target of an operation All other encodings reserved 001b PE supports 34 bit addresses 010b PE supports 50 bit addresses 100b PE supports 66 bit addresses Other Reserved 190 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 60 Local Configuration Space Base Address 0 CSR LCL_CFG_HBAR The local configuration space base address 0 CSR LCL_CFG_HBAR is shown in Figure 123 and described in Table 131 Figure 123 Local Configuration Space Base Address 0 CSR LCL_CFG_HBAR Address Offset 1 058h 31 30 0 Reserved LCSBA R 0 R 00000000h LEGEND R Read only n Value after reset Table 131 Local Configuration Space Base Address 0 CSR LCL_CFG_HBAR Field Descriptions Bit Field Value Description 31 Reserved 0 These read only bits return Os when read 30 0 LCSBA 00000000h Bits 30 to 15 are reserved for 34 bit addresses reserved for 50 bit addresses and to bits 66 to 51 of a 66 bit address FFFFFFFFh e Bits 14 to 0 are reserved for 34 bit addresses bits 50 to 36 of a 50 bit address and bits 50 to 36 of a 66 bit address SPRUE13A Se
241. eld encoding ICS2 LSU1 interrupt condition not detected LSU1 interrupt condition detected Transaction was not sent due to Xoff condition SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 139 SRIO Registers da TEXAS INSTRUMENTS www ti com Table 73 LSU Interrupt Condition Status Register LSU_ICSR Field Descriptions continued Bit Field Value Description 1 ICS1 0 LSU1 interrupt condition not detected 1 LSU1 interrupt condition detected Non posted transaction received ERROR response or error in response payload 0 ICSO 0 LSU1 interrupt condition not detected 1 LSU1 interrupt condition detected Transaction complete No errors posted non posted Enable for this interrupt is ultimately controlled by the Interrupt Req bit of LSU1_REG4 This allows enabling disabling on a per request basis For optimum LSU performance interrupt pacing should not be used on the LSU interrupts 140 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 23 LSU Interrupt Condition Clear Register LSU_ICCR Setting a bit in this register clears the corresponding bit in LSU_ICSR to acknowledge the interrupt LSU_ICCR is shown in Figure 84 and described in Table 74 For additional programming information see Section 4 3 3 Figure 84 LSU Interrupt Condition Cle
242. en the Byte_Count of Read Write requests exceeds 256 bytes up to 4K bytes The second type is when Read Write request RapidlO address is non 64 bit aligned In both cases the outgoing request is broken up into multiple RapidlO request packets For example assume that the CPU wants to perform a 1K byte store operation to an external RapidlO device After setting up the LSU registers the CPU performs one write to the LSUn_REGS register The peripheral hardware then segments the store operation into four RapidlO write packets of 256 bytes each and calculates the 64 bit aligned RapidlO address WRSIZE and WDPTR as required for each packet This example requires four outbound handles to be assigned and four DMA transmit requests The LSU registers cannot be released until all posted request packets are passed to the TX FIFOs Alternatively for non posted operations such as CPU loads all packet responses must be received before the LSU registers are released 2 3 3 3 Direct I O RX Operation 42 Response packets are always type 13 RapidlO packets All response packets with transaction types not equal to 0001b are routed to the LSU block sequentially in order of reception These packets may have a payload depending on the type of corresponding request packet that was originally sent Due to the nature of RapidlO switch fabric systems response packets can arrive in any order The data payload if any and header data is moved from the RX FIFO to the s
243. eptember 2006 List of Tables 13 Submit Documentation Feedback d TEXAS Preface INSTRUMENTS SPRUE13A September 2006 Read This First About This Manual This document describes the Serial RapidIO SRIO peripheral on the TMS320TCI648x devices Notational Conventions This document uses the following conventions e Hexadecimal numbers are shown with the suffix h For example the following number represents 40 hexadecimal decimal 64 40h e Registers in this document are shown in figures and described in tables Each register figure shows a rectangle divided into fields that represent the fields of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties below A legend explains the notation used for the properties Reserved bits in a register figure designate a bit that is used for future device expansion Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com Implementing Serial RapidlO SRIO PCB Layout on a TMS320TCI6482 Hardware Design literature number SPRAABO specifies a complete printed circuit board PCB solution for the TCI6482 as well as a list of compatible SRIO devices showing two DSPs connected via a 4x SRIO link TI
244. er Received on any All priorities input port Dedicated single segment Il message descriptor queue L2 memory A data buffer up to 256B Mailbox mapper m Rp Cc n data packet 3 data packet L y n Q2 Q1 Qo D n 4 data packet Packet EN manager E n 6 data packet Queue assignable to any core null 256B free buffer L2 memory data buffer up to 4K n 1 data packet n 2 data packet n 5 data packet Multi segment message descriptor queue B Multi segment message descriptor queue N null 4KB free buffer Messages addressed to any of the 64 mailbox locations can be received on any of the RapidlO ports simultaneously Packets are handled sequentially in order of receipt The function of the mailbox mapper block is to direct the inbound messages to the appropriate queue and finally to the correct core The queue mapping is programmable and must be configured after device reset RapidlO originally supported only 4 mailboxes with 4 letters mailbox Letters allow concurrent message traffic between sender and receiver However for messages that consist of only single packets the unused 4 bit packet field normally indicating the message segment extends the available number of mailboxes Figure 17 shows the packet header fields for message requests Packet sequence Serial RapidlO SRIO SPRUE13A September 2006
245. er The hardware is not responsible for attempting retransmission of the Doorbell transaction Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com SRIO Functional Description So the general flow is as follows e Previously the control command registers were written and the request packet was sent e Response Packet Type13 Trans 0001b arrives at module interface and is handled sequentially not based on priority e The argetTID is examined to determine routing of a response to the appropriate core e The status field of the response packet is checked for ERROR RETRY or DONE e Ifthe field is DONE it submits DMA bus request and transmits the payload if any to DSP address If the field is ERROR RETRY it sets an interrupt e Command registers are released BSY 0 e Optional Interrupt to CPU notifying packet reception 2 3 3 4 Reset and Power Down State 2 3 4 Upon reset the Load Store module clears the command register fields and wait for a write by the CPU The Load Store module can be powered down if the direct I O protocol is not being supported in the application For example if the messaging protocol is being used for data transfers powering down the Load Store module will save power In this situation the command registers should be powered down and inaccessible Clocks should be gated to these blocks while in the power down state Message Passing The Commun
246. er H16 Section 5 50 0888h RXU_MAP_L17 MailBox to Queue Mapping Register L17 Section 5 50 088Ch RXU_MAP_H17 MailBox to Queue Mapping Register H17 Section 5 50 0890h RXU_MAP_L18 MailBox to Queue Mapping Register L18 Section 5 50 0894h RXU_MAP_H18 MailBox to Queue Mapping Register H18 Section 5 50 0898h RXU_MAP_L19 MailBox to Queue Mapping Register L19 Section 5 50 089Ch RXU_MAP_H19 MailBox to Queue Mapping Register H19 Section 5 50 O8A0h_ RXU_MAP_L20 MailBox to Queue Mapping Register L20 Section 5 50 08A4h RXU_MAP_H20 MailBox to Queue Mapping Register H20 Section 5 50 08A8h RXU_MAP_L21 MailBox to Queue Mapping Register L21 Section 5 50 08ACh RXU_MAP_H21 MailBox to Queue Mapping Register H21 Section 5 50 08B0h RXU_MAP_L22 MailBox to Queue Mapping Register L22 Section 5 50 08B4h RXU_MAP_H22 MailBox to Queue Mapping Register H22 Section 5 50 08B8h RXU_MAP_L23 MailBox to Queue Mapping Register L23 Section 5 50 08BCh RXU_MAP_H23 MailBox to Queue Mapping Register H23 Section 5 50 08C0h RXU_MAP_L24 MailBox to Queue Mapping Register L24 Section 5 50 08C4h_ RXU_MAP_H24 MailBox to Queue Mapping Register H24 Section 5 50 08C8h RXU_MAP_L25 MailBox to Queue Mapping Register L25 Section 5 50 08CCh RXU_MAP_H25 MailBox to Queue Mapping Register H25 Section 5 50 08DOh RXU_MAP_L26 MailBox to Queue Mapping Register L26 Section 5 50 08D4h RXU_MAP_H26 MailBox to Queue Mapping Register H26 Section 5 50 O8D8h RXU_MAP_L27 MailBox to Queue Ma
247. er field to specify the appropriate output port FIFO The data is burst internally to the Load Store module at the DMA clock rate 2 3 3 1 Detailed Data Path Description The Load Store module is for generating all outgoing RapidlO direct I O packets Any read or write transaction other than the messaging protocol uses this interface In addition outgoing DOORBELL packets are generated through this interface The data path for this module uses DMA bus as the DMA interface The configuration bus is used by the CPU to access the control command registers The registers contain transfer descriptors that are needed to initiate READ and WRITE packet generation After the transfer descriptors are written flow control status is queried The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that flow has been Xoffd Additionally the free buffer status of the TX FIFO is checked based on the OutPortlD register field Only after the flow control access is granted and a TX FIFO buffer has been allocated can a DMA bus read command be issued for payload data to be moved into the shared TX buffer Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential order based on completion of the DMA bus transaction However if fabric congestion occurs priority can affect the order in which the data lea
248. er value is decremented for each corresponding Xon CCP that is received but it is not decrement below zero Additionally a hardware timer exists for each table entry to turn on flows that may have been abandoned by lost Xon CCPs The timer value is of an order of magnitude larger than the 32 bit Port Response Time out CSR value For this reason each transmission source adds 2 bits to its 4 bit response time out counter Descriptions of this type of time out counter are in Section 2 3 3 3 and Section 2 3 4 2 The additional 2 bits count three timecode revolutions and provide an implicit Xon timer equal to 3x the Response time out counter value Figure 27 Flow Control Table Entry Registers Address Offset 0900h 093Ch 31 18 17 16 15 0 FLOW_CNTLO Reserved TT FLOW_CNTL_ID R 0x00000 R W 01 R W 0x0000 31 18 17 16 15 0 FLOW_CNTL1 Reserved TT FLOW_CNTL_ID R 0x00000 R W 01 R W 0x0000 31 18 17 16 15 0 FLOW_CNTL2 Reserved TT FLOW_CNTL_ID R 0x00000 R W 01 R W 0x0000 eee 31 18 17 16 15 0 FLOW_CNTL15 Reserved TT FLOW_CNTL_ID R 0x00000 R W 01 R W 0x0000 LEGEND R W Read Write R Read only n Value after reset 66 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 24 Flow Control Table Entry Register n FLOW_CNTLn Field Descriptions Bit Field Value Description 31 18 Rese
249. erial RapidlO SRIO Registers continued Offset Acronym Register Description Section 0838h RXU_MAP_L7 MailBox to Queue Mapping Register L7 Section 5 50 083Ch RXU_MAP_H7 MailBox to Queue Mapping Register H7 Section 5 50 0840h RXU_MAP_L8 MailBox to Queue Mapping Register L8 Section 5 50 0844h RXU_MAP_H8 MailBox to Queue Mapping Register H8 Section 5 50 0848h RXU_MAP_L9 MailBox to Queue Mapping Register L9 Section 5 50 084Ch RXU_MAP_H9 MailBox to Queue Mapping Register H9 Section 5 50 0850h RXU_MAP_L10 MailBox to Queue Mapping Register L10 Section 5 50 0854h RXU_MAP_H10 MailBox to Queue Mapping Register H10 Section 5 50 0858h RXU_MAP_L11 MailBox to Queue Mapping Register L11 Section 5 50 085Ch RXU_MAP_H11 MailBox to Queue Mapping Register H11 Section 5 50 0860h RXU_MAP_L12 MailBox to Queue Mapping Register L12 Section 5 50 0864h RXU_MAP_H12 MailBox to Queue Mapping Register H12 Section 5 50 0868h RXU_MAP_L13 MailBox to Queue Mapping Register L13 Section 5 50 086Ch RXU_MAP_H13 MailBox to Queue Mapping Register H13 Section 5 50 0870h RXU_MAP_L14 MailBox to Queue Mapping Register L14 Section 5 50 0874h RXU_MAP_H14 MailBox to Queue Mapping Register H14 Section 5 50 0878h RXU_MAP_L15 MailBox to Queue Mapping Register L15 Section 5 50 087Ch RXU_MAP_H15 MailBox to Queue Mapping Register H15 Section 5 50 0880h RXU_MAP_L16 MailBox to Queue Mapping Register L16 Section 5 50 0884h RXU_MAP_H16 MailBox to Queue Mapping Regist
250. ernal device RapidlO allows 4 bytes 8 bytes or any multiple of a double word access up to 64 bytes for type 8 maintenance packets The peripheral only supports 4 byte accesses as the target but can generate all sizes of request packets RapidlO is defined as Big Endian only and has double word aligned Big Endian packet payloads 2 3 9 2 Endian Conversion TMS320TCI6482 The DMA however supports byte wide accesses The peripheral performs Endian conversion on the payload if Little Endian is used on the device This conversion is not only applicable for type 8 packets but is also relevant for all outgoing payloads of NWRITE NWRITE_R SWRITE NREAD and message packets This means that the memory image is different between Little Endian and Big Endian configurations as shown in Figure 31 Figure 31 DMA Example The desired operation is to send a Type 8 maintenance request to an external device The goal is to read 16B of RapidlO MMR from an external device starting offset 0x0000 This operation involves the LSU block and utilizes the DMA for transferring the response packet payload RapidlO defined bit positions 0 31 MMR offset 0x0000 AO A1 A2 A3 RapidlO defined MMR offset 0x0004 BO B1 B2 B3 Ann MMR offset 0x0008 C0 c1 c2 c3 offsets MMR offset 0x000C DO D1 D2 D3 Type 8 Response Header fields A0A1A2A3
251. error free control symbols with the attached device 0 PORT_UNINITIALIZED Port uninitialized PORT_UNINITIALIZED is a read only bit This bit and the PORT_OK bit are mutually exclusive 0 Input and output ports are initialized Input and output ports are not initialized SPRUE13A September 2006 Serial RapidlO SRIO 205 Submit Documentation Feedback SRIO Registers 5 73 Port Control CSR n SPn_CTL Each of the four ports is supported by a register of this type see Table 148 The port control CSR n SPn_CTL is shown in Figure 136 and described in Table 149 To change from 1 lane to 4 lanes there are 2 registers that need to be programmed The SP_IP_MODE offset 0x12004 bits 31 30 are set to be 1x 4p or 4 ports 1x mode each The PER_SET_CNTL offset 0x0020 bit 8 is set up for port 1x 4p or priority based 1x mode each da TEXAS INSTRUMENTS www ti com Table 148 SPn_CTL Registers and the Associated Ports Register Address Offset Associated Port SPO_CTL 115Ch Port 0 SP1_CTL 117Ch Port 1 SP2_CTL 119Ch Port 2 SP3_CTL 11BCh Port 3 Figure 136 Port Control CSR n SPn_CTL 31 30 29 27 26 24 PORT_WIDTH INITIALIZED_PORT_WIDTH PORT_WIDTH_OVERRIDE R 01 R 000 R W 000 23 22 21 20 19 18 16 PORT_ OUTPUT _ INPUT_ ERROR MULTICAST_ DISABLE PORT_ PORT_ CHECK_ PARTICIPANT Reserved ENABLE ENABLE DISABLE R W 0 R W 0 R W 0 R W 0 HO HO 15 8
252. errupt condition status register is shown in Figure 77 and described in Table 66 For additional programming information see Section 4 3 1 and Section 2 3 6 Table 65 DOORBELLn_ICSR Registers Register Address Offset DOORBELLO_ICSR 0200h DOORBELL1_ICSR 0210h DOORBELL2_ICSR 0220h DOORBELL3_ICSR 0230h Figure 77 Doorbell n Interrupt Condition Status Register DOORBELLn_ICSR 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 66 DOORBELLn Interrupt Condition Status Register DOORBELLn_ICSR Field Descriptions Bit Field Value Description 31 16 Reserved 0 These read only bits return Os when read 15 0 ICSx Doorbell n interrupt condition status bit 0 Bit x of the doorbell information value is 0 Bit x of the doorbell information value is 1 generating an interrupt request 132 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 17 DOORBELLn Interrupt Condition Clear Register DOORBELLn_ICCR The four doorbells interrupts that are mapped are cleared by this register see Ta
253. errupt sources one for each buffer descriptor queue can be mapped to bits 31 16 as shown in Figure 60 The doorbell interrupt sources can be mapped to bits 15 0 An interrupt source is mapped to ISDR bits only if the ICRR for that interrupt source routes it to the corresponding interrupt destination When multiple interrupt sources are mapped to the same bit the bit status is a logical OR of those interrupt sources The mapping of interrupt source bits to decode bits is fixed and is not programmable Figure 59 Interrupt Status Decode Register INTDSTn_DECODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ISD31 ISD30 ISD29 ISD28 ISD27 ISD26 ISD25 ISD24 ISD23 ISD22 ISD21 ISD20 ISD19 ISD18 ISD17 ISD16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISD15 ISD14 ISD13 ISD12 ISD11 ISD10 ISD9 ISD8 ISD7 ISD6 ISD5 ISD4 ISD3 ISD2 ISD1 ISDO R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n Value after reset Figure 60 Interrupt Sources Assigned to ISDR Bits ISDR bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ti m LSU Error reset and special event lt TX CPPI ICSR 0 15 gt WM RX CPPI ICSR GR gt ISDR bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
254. es have a payload So READ commands simply require a non payload shared TX buffer In addition they require a shared RX buffer This buffer is not pre allocated before transmitting the READ request packet since doing so could cause traffic congestion of other in bound packets destined to other functional blocks Again the control command registers cannot be released BSY 1 until the response packet is routed back to the module and appropriate completion code is set in the status register So the general flow would be e LSU registers are written using the configuration bus e Flow control is determined e TX FIFO free buffer availability is determined e Header data in the LSU registers is written to the shared TX buffer e Payload and header are transferred to the TX FIFO e The LSU registers are released if no RapidlO response is needed e Transfer from the TX FIFO to external device based on priority For all transactions the shared TX buffers are released as soon as the packet is forwarded to the TX FIFOs If an ERROR or RETRY response is received for a non posted transaction the CPU must either reinitiate the process by writing to the LSU register or initiate a new transaction altogether SPRUE13A September 2006 Serial RapidlO SRIO 41 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Segmeniation The LSU handles two types of segmentation of outbound requests The first type is wh
255. es not have guaranteed delivery and does not have an associated response This maintenance operation is useful for sending messages such as error indicators or status information from a device that does not contain an endpoint such as a switch The data payload is typically placed in a queue in the targeted endpoint and an interrupt is typically generated to a local processor A port write request to a queue that is full or busy servicing another request may be discarded SRIO_REGS gt LSU1_REGO CSL_FMK SRIO_LSU1_REGO_RAPIDIO_ADDRESS_MSB 0 SRIO_REGS gt LSU1_REG1 CSL_FMK SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET int car_csr SRIO_REGS gt LSU1_REG2 CSL_FMK SRIO_LSU1_REG2_DSP_ADDRESS int amp xmtBuff 0 SRIO_REGS gt LSU1_REG3 CSL_FMK SRIO_LSU1_REG3_BYTE_COUNT byte_count SRIO_REGS gt LSU1_REG4 CSL_FMK SRIO_LSU1_REG4_OUTPORTID 0 CSL_FMK SRIO_LSU1_REG4_PRIORITY 0 CSL_FMK SRIO_LSU1_REG4_XAMSB 0 no extended address CSL_FMK SRIO_LSU1_REG4_ID_SIZE 1 CSL_FMK SRIO_LSU1_REG4_DESTID OxBEEF CSL_FMK SRIO_LSU1_REG4_INTERRUPT_REQ 0 SRIO_REGS gt LSU1_REG5 CSL_FMK SRIO_LSU1_REG5_DRBLL_INFO 0x0000 CSL_FMK SRIO_LSU1_REG5_HOP_COUNT 0x03 CSL_FMK SRIO_LSU1_REG5_PACKET_TYPE type type REQ_MAINT_RD Doorbell Operation The doorbell operation is shown in Figure 26 It consists of the DOORBELL and RESPONSE transactions typically a DONE response a
256. ese packets is to turn off Xoff or turn on Xon specific flows defined by DESTID and PRIORITY of outgoing packets CCPs are sent at the highest priority in an attempt to address fabric congestion as quickly as possible CCPs do not have a response packet and they do not have guaranteed delivery When the peripheral receives an Xoff CCP the peripheral must block outgoing LSU and CPPI packets that are destined for that flow When the peripheral receives an Xon the flow may be enabled Since CCPs may arrive from different switches within the fabric it is possible to receive multiple Xoff CCPs for the same flow For this reason the peripheral must maintain a table and count of Xoff CCPs for each flow For example if two Xoff CCPs are received for a given flow two Xon CCPs must be received before the flow is enabled SPRUE13A September 2006 Serial RapidlO SRIO 65 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Functional Description Since CCPs do not have guaranteed delivery and can be dropped by the fabric an implicit method of enabling an Xoff d flow must exist A simple timeout method is used Additionally flow control checks can be enabled or disabled through the Transmit Source Flow Control Masks Received CCPs are not passed through the DMA bus interface 2 3 8 1 Detailed Description To avoid large and complex table management a basic scheme is implemented for congestion management The primary goal is
257. eset Hier rfchy zu ia a a REN EE ENNEN EK AN e 70 27 Global Enable and Global Enable Status Field Descriptions ccceeeeeee eee eee e ee eee eee nun nun nun nun ann nenn 72 28 Block Enable and Block Enable Status Field Descriptions ceceeeeeee cece eee eee nun eens nun nun nun nun nenn nun 73 29 Peripheral Control Register PCR Field Descriptions eee e eee eens tees ann nun nun enn nun nun nun nen 74 30 Port Mode Register Ssettings au aa ei 77 31 Multicast DevicelD Operations s e a 0 seen ee 81 32 Packet Forwarding Register n for 16 Bit DevicelDs PF_16B_CNTLn Field Descriptions 2 0005 81 33 Packet Forwarding Register n for 8 Bit DevicelDs PF_8B_CNTLn Field Descriptions 200 2eeeees 82 34 Logical Transport Layer Error Detect CSR ERR_DET Field Descriptions r4 uu44HHR nenn nenn nennen 83 35 Interrupt Condition Status and Clear Bis 87 36 Interrupt Conditions Shown in LSU_ICSR and Cleared With L GU ICH 2 ce eeeee nnnn nun nennen nn nennen 90 37 Interrupt Conditions Shown in ERR_RST_EVNT_ICSR and Cleared With ERR_RST_EVNT_ICCR 91 38 Interrupt Clearing Sequence for Special Event Interrupts 20ceeeee Run nenn nenn nennen nun nun nenn nennen nen 92 39 Interrupt Condition Routing Options NEEN ENEE EE 93 40 serial RapidlO SRIO Registers u c ce san Eschen 102 41 Peripheral ID Register PID Field Descriptions EN uk 42 Peripheral Control Register PCR Field Descript
258. ess offsets 0800h 08FCh Each entry stores the queue number associated with the message s intended mailbox letter If a mailbox letter is not supported or does not have a mapping table entry the message is discarded and an ERROR response sent The mapping entries can explicitly call out a mailbox and letter combination or alternatively the mask fields can be used to grant multiple mailbox letter combinations access to a queue using the same table entry A masking value of 0 in the mailbox or letter mask fields indicates that the corresponding bit in the mailbox or letter field will not be used to match for this queue mapping entry For example a mailbox mask of all zeros would allow a mapping entry to be used for all incoming mailboxes The mapping table entry also provides a security feature to enable or disable access from specific external devices to local mailboxes The sourcelD field indicates which external device has access to the mapping entry and corresponding queue A compare is performed between the sourcelD of the incoming message packet and each relevant mailbox letter table mapping entry SOURCEID field If they do not match an ERROR response is sent back to the sender and the transaction is logged in the logical layer error management capture registers which sets an interrupt A PROMISCUOUS bit allows this security feature to be disabled When the PROMISCUOUS bit is set full access to the mapping entry from any sourcelD is allowed Not
259. essage is multi segment Once the port controls the buffer descriptor the DEST_ID field can be queried to determine flow control If the transaction has been flow controlled the DMA bus READ request is postponed so that the TX buffer space is not wasted Because buffer descriptors cannot be reordered in the link list if the transaction at the head of the buffer descriptor queue is flow controlled head of line HOL blocking will occur on that queue When this occurs all transactions located in that queue are stalled To counter the effects and reduce back up of more TX packets multiple queues are available The peripheral supports a total of 16 assignable TX queues and their associated TX DMA state registers The transmission order between queues is based on a programmable weighted round robin scheme at the message level The programmable control registers are shown in Figure 23 This scheme allows configurability of the queue transmission order as well as the weight of each queue within the round robin The TX state machine begins by processing the current TX_Queue_Map n It will attempt to process the queue and number of buffer descriptors from that queue programmed in this mapping entry Then it will move to TX_Queue_Map n 1 followed by TX_Queue_Map n 2 and so forth It is important to note that this mapping order is fixed in a circular pattern Each mapper can point to any queue and multiple mappers can point to a single queue If a mapper
260. est is received 0 Port Write In interrupt disable 1 Port Write In interrupt enable 0 PW_IRQ Port Write In request interrupt Once set the PW_IRQ bit remains set until software writes a 1 to it The pw_irq output signal is driven by this bit 0 The Port Write In request has not been received 1 The Port Write In request has been received The payload is captured 232 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Registers 5 93 Port IP Prescaler Register IP_PRESCAL The port IP prescaler register IP_PRESCAL is shown in Figure 156 and described in Table 178 This register defines a prescaler for different frequencies of the DMA clock The purpose of this register is to keep the timers of SP_LT_CTL offset 01120h SPO_ERR_RATE through SP3_ERR_RATE offsets 02068h 020A8h 020E8 and 02128h SP_IP_DISCOVERY_TIMER offset 12000h and SPO_SILENCE_TIMER through SP3_SILENCE_TIMER offsets 14008h 14108h 14208h and 14308h within the same range for different frequencies of the DMA clock Figure 156 Port IP Prescaler Register IP_PRESCAL Address Offset 12008h 31 18 Reserved R 0000h 15 8 7 0 Reserved PRESCALE R 00h RW OFh LEGEND R W Read Write R Read only n Value after reset Table 178 Port IP Prescaler Register IP_PRESCAL Field Descriptions Bit Field Value Description 31 8 Reserved 000000h These read onl
261. f message packets 49 in order requirement bits for RX queues 173 INPUT_ERROR_ENC field of SPn_ERR_STAT 203 INPUT_ERROR_STP field of SPn_ERR_STAT 203 INPUT_PORT_ENABLE field of SPnCTL 206 INPUT_RETRY_STP field of SPn_ERR_STAT 203 input enable field for portn 207 input error stopped status bit for ports 204 input retry stopped status bit for ports 204 input termination field for SERDES receiver 126 input transmission error status bit for ports 204 INTDSTn_DECODE 150 INTDSTn_RATE_CNTL 154 interconnect architecture for RapidlO 18 interfacing two 1x or 4x devices 18 INTERRUPT_REQ field of LSUn_REG4 159 interrupt approach to messaging protocol 86 246 Index interrupt condition clearing 86 interrupt condition clear registers for CPPI interrupt conditions 135 137 for doorbell interrupt conditions 133 for error reset and special event port interrupt conditions 143 for LSU interrupt conditions 141 interrupt condition routing 93 interrupt conditions 85 interrupt condition status checking 86 interrupt condition status registers for CPPI interrupt conditions 134 136 for doorbell interrupt conditions 132 for error reset and special event port interrupt conditions 142 interrupt destinations controlling interrupt pacing with interrupt rate control registers 99 narrowing down interrupt sources with help from interrupt status decode registers 97 selecting with interrupt condition routing registers 93 interrupt error at port n report
262. g on the whether the hardware packet forwarding is enabled Additionally it is beneficial to be able to only forward a packet if the destination ID is one of the devices in the chain ring Otherwise a rogue packet may be forwarded endlessly using up valuable bandwidth The hardware packet forwarding uses a 4 entry mapping table shown in Table 32 and Table 33 These mapping entries allow programmable selection of output port based on the in coming packets DestID range Since the packet forwarding is done at the logical layer and not the physical layer CRCs will be regenerated for each forwarded packet 2 3 15 3 Enabling Multicast and Packet Forwarding In order to enable multicast support bit 5 of the SP_IP_MODE offset 0x12004 must be set to 1 The multicast mode is disabled by simply writing the same devicelD into the registers listed in Table 31 Hardware packet forwarding can be disabled by assigning all the table entry Upper and Lower devicelD boundaries equal to the local DevicelD value Figure 42 Packet Forwarding Register n for 16 Bit Device IDs PF_16B_CNTLn Offsets 0x0090 0x0098 0x00A0 0x00A8 16 15 0 16BIT_DEVID_UP_BOUND 16BIT_DEVID_LOW_BOUND R W FFFFh R W FFFFh LEGEND R W Read Write n Value after reset Table 32 Packet Forwarding Register n for 16 Bit DevicelDs PF_16B_CNTLn Field Descriptions Field Value Description 31 16 16BIT_DEVID_UP_BOUND 0000h FFFFh Upper 16 bit DevicelD boundary
263. gister RX_CPPI_ICSR is shown in Figure 79 and described in Table 69 For additional programming information see Section 4 3 2 Figure 79 RX CPPI Interrupt Condition Status Register RX_CPPI_ICSR Address Offset 0240h 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 69 RX CPPI Interrupt Condition Status Register RX_CPPI_ICSR Field Descriptions Bit Field Value Description 31 16 Reserved 0 These read only bits return O when read 15 0 ICSx RX CPPI interrupt status c 15 to 0 0 RX buffer descriptor queue x has not generated an interrupt request RX buffer descriptor queue x has generated an interrupt request 134 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Registers 5 19 RX CPPI Interrupt Clear Register RX_CPPI_ICCR This register is used to clear bits in RX_CPPI_ICSR to acknowledge interrupts from the RX buffer descriptor queues The RX CPPI interrupt clear register RX_CPPI_ICCR is shown in Figure 80 and described in Table 70 For additional programming information see Section 4 3 2
264. guration Register 2 Section 5 14 102 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section 011Ch SERDES_CFGTX3_CNTL SERDES Transmit Channel Configuration Register 3 Section 5 14 0120h SERDES_CFGO_CNTL SERDES Macro Configuration Register 0 Section 5 15 0124h SERDES_CFG1_CNTL SERDES Macro Configuration Register 1 Section 5 15 0128h SERDES_CFG2_CNTL SERDES Macro Configuration Register 2 Section 5 15 012Ch SERDES_CFG3_CNTL SERDES Macro Configuration Register 3 Section 5 15 0200h DOORBELLO_ICSR DOORBELL Interrupt Condition Status Register 0 Section 5 16 0208h DOORBELLO_ICCR DOORBELL Interrupt Condition Clear Register 0 Section 5 17 0210h DOORBELL1_ICSR DOORBELL Interrupt Condition Status Register 1 Section 5 16 0218h DOORBELL1_ICCR DOORBELL Interrupt Condition Clear Register 1 Section 5 17 0220h DOORBELL2_ICSR DOORBELL Interrupt Condition Status Register 2 Section 5 16 0228h DOORBELL2_ICCR DOORBELL Interrupt Condition Clear Register 2 Section 5 17 0230h DOORBELL3_ICSR DOORBELL Interrupt Condition Status Register 3 Section 5 16 0238h DOORBELL3_ICCR DOORBELL Interrupt Condition Clear Register 3 Section 5 17 0240h RX_CPPI_ICSR R
265. hared RX buffer The targetTID field of the packet is examined to determine which core and corresponding set of registers are waiting for the response Remember there can be only one outstanding request per core Any payload data is moved from the shared RX buffer into memory through normal DMA bus operations Registers for all non posted operations should only be held for a finite amount of time to avoid blocking resources when a request or response packet is somehow lost in the switch fabric This time correlates to the 24 bit Port Response Time out Control CSR value discussed in sections 5 10 1 and 6 1 2 4 of the RapidlO Physical Layer 1x 4x LP Serial Specification If the time expires control command register resources should be released and an error is logged in the error management RapidlO registers The RapidlO Interconnect Specification states that the maximum time interval all 1s is between 3 and 6 seconds A logical layer timeout occurs if the response packet is not received before a countdown timer initialized to this CSR value reaches zero Each outstanding packet response timer requires a 4 bit register The register is loaded with the current timecode when the transaction is sent The timecode comes from a 4 bit counter associated with the 24 bit down counter that continually counts down and is re loaded with the value of SP_RT_CTL Address offset 1124h when it reaches 0 Each time the timecode changes a 4 bit compare is done to the r
266. he CP register to FFFFFFFCh and issuing an interrupt for the given queue The teardown command register bit is automatically cleared by the peripheral Ifthe queue is in active no additional buffer descriptors available or becomes inactive after a message in transmission is completed no buffer descriptor fields are written The HDP register and the CP register remain unchanged An interrupt is not issued The teardown command register bit is automatically cleared by the peripheral Because of topology differences between flow s response packets may arrive in a different order to the order of requests After the teardown process is complete and the interrupt is serviced by the CPU software must re initialize the TX queue to restart normal operation 2 3 4 3 Reset and Power Down State Upon reset the CPPI module must be configured by the CPU The CPU sets up the receive and transmit queues in memory Then the CPU updates the CPPI module with the appropriate RX TX DMA state head descriptor pointer so the peripheral knows with which buffer descriptor address to start Additionally the CPU must provide the CPPI module with initial buffer descriptor values for each data buffer The CPPI module can be powered down if the message passing protocol is not being supported in the application For example if the direct I O protocol is being used for data transfers powering down the CPPI module will save power In this situation the buffer de
267. he error reporting threshold to 2 FFh Set the error reporting threshold to 255 15 0 Reserved 0000h These read only bits return Os when read SPRUE13A September 2006 Serial RapidlO SRIO 229 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 91 Port IP Discovery Timer for 4x Mode Register SP_IP_DISCOVERY_TIMER The port IP discovery timer for 4x mode register SP_IP_DISCOVERY_TIMER is shown in Figure 154 and described in Table 176 Figure 154 Port IP Discovery Timer for 4x Mode Register SP_IP_DISCOVERY_TIMER Address Offset 12000h 31 28 27 24 23 20 19 16 DISCOVERY_TIMER Reserved PW_TIMER Reserved R W 9h R Oh R W 8h R Oh 15 0 Reserved R 0000h LEGEND R W Read Write R Read only n Value after reset Table 176 Port IP Discovery Timer for 4x Mode Register SP_IP_DISCOVERY_TIMER Field Descriptions Bit Field Value Description 31 28 DISCOVERY_TIMER Discovery timer for 4x mode The discovery timer allows time for the link partner to enter its DISCOVERY state and if the link partner is supporting 4x mode for all 4 lanes to be aligned 0000b Reserved 0001b 0 84 ms 0010b 0 84 ms x 2 1 68 ms 1001b 0 84 ms x 9 7 56 ms default 1111b 0 84 ms x 15 12 6 ms 27 24 Reserved 0000b These read only bits return Os when read 23 20 PW_TIMER Port write timer The timer defines a period to repeat sending an error reporting port
268. he in order bit in the RX CPPI Control register must be disabled by software for that queue after which it may be enabled again if desired The in order mode of operation is only valid on multi segment queues because single segment messages will never generate RETRY responses Figure 20 RX CPPI Mode Explanation Data flow destined for the same RX queue RX queue status when packet arrives Scenario A Default Open Open Open Open Open Full Endpoint Retry Retry Retry Retry Accept Retry Action RX queue status when packet arrives Scenario B In order mode Open Open Open Open Full Full Switch co B2 B1 BO A1 AO Endpoint Retry Retry Retry Retry Retry Retry Action Records SourcelD letter of first retry packet Serial RapidlO SRIO 49 d TEXAS INSTRUMENTS www ti com SRIO Functional Description In addition multiple messages can be interleaved at the receive port due to ordering within a connected switch s output queue This can occur when using a single or multiple priorities The RX CPPI block can handle simultaneous interleaved multi segment messages This implies that state information write pointers and sourcelD is maintained on each simultaneous message to properly store the segments in memory The number of simultaneous transactions supported directly impacts the number of
269. hy cceecceee eee eee eee eee nun eee enna eee nun nannun nun nun nunnnnnnnnnnnn nun Saaja 17 2 RapidlO Interconnect Architecture 2 2 0 cece eee eee eee eee eee eee ene eee ene ene nun nun nunnunnnnn nun nen nnnnnn nn eee 18 3 Serial RapidlO Device to Device Interface Diagrams c eeceeee eee e eee eeeeee eee e eee eee eee nun nnunnun nun nn nenn 19 4 SRIO Peripheral Block DiaGra Mic sisiran eier a e g et deeg Yard geesde 22 5 Operation sequence ee nee ee 23 6 1x 4x RapidlO Packet Data Stream Streaming Write Class 24 7 Serial RapidlO Control Symbol Format 24 8 SRIO Gomponent Block Diagram 4 00 5400 Bann ai 27 9 SERDES Macro Configuration Register 0 SERDES_CFGO_CNTL uuzauuennennnannannnnnnnnnun nun nun ann nenn 28 10 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL uusursunnennnnnannnen nn 31 11 SERDES Transmit Channel Configuration Register n GERDESG CFGtTxn CNTU nun 33 12 Load Store Registers for RapidlO Address Offset LSU1 400h 418h LSU2 420h 438h LSU3 440h 458h LSU4 460h 478h ENEE EEN EEN EEN EEN 36 13 LSU Registers Timing se 5 445 4 00a a en ceeded 38 14 Example Burst NWRITE_R nessaenenennenennnennnnnnnennnnnnnnnnennnnnnnnnnnnn nenn nenn nenne nenne nenn nennen nennen nenne 39 15 Load Store Module Data Flow Diagram ENEE EEN 40 16 GPRPIRX SCheme for RapidlO E 44 17 Message Request Packet zeuuussuunnannnnunnnnnnnnannnnnan nun nennen nn anne nun nenn nenn nennen nenn
270. ications Port Programming Interface CPPI module is the incoming and outgoing message passing protocol engine of the RapidlO peripheral Messages contain application specific data that is pushed to the receiving device comparable to a streaming write Messages do not contain read operations but do have response packets With message passing a destination address is not specified Instead a mailbox identifier is used within the RapidlO packet The mailbox is controlled and mapped to memory by the local destination device For RapidlO message passing four mailbox locations are specified Each mailbox can contain 4 separate transactions or letters effectively providing 16 messages Single packet messages provide 64 mailboxes with 4 letters effectively providing 256 messages Mailboxes can be defined for different data types or priorities The advantage of message passing is that the source device does not require any knowledge of the destination device s memory map The DSP contains buffer description tables for each mailbox These tables define a memory map and pointers for each mailbox Messages are transferred to the appropriate memory locations via the DMA The data path for this module uses the DMA bus as the DMA interface The ftype header field of the received RapidlO message packets are decoded by the logical layer of the peripheral Only Type 11 and Type 13 transaction type 1 packets are routed to this module Data is routed from the pr
271. ing 34 bit addresses e Support for generating 34 bit 50 bit and 66 bit addresses e Support for the following data sizes byte half word word double word e Big endian data transfers e Direct I O transfers e Message passing transfers e Data payloads of up to 256 bytes e Single messages consisting of up to 16 packets e Elastic storage FIFOs for clock domain handoff e Short run and long run compliance e Support for Error Management Extensions e Support for Congestion Control Extensions e Support for one multi cast ID SPRUE13A September 2006 Serial RapidlO SRIO 19 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Overview Features Not Supported e Compliance with the Global Shared Memory specification GSM e 8 16 LP LVDS compatible e Destination support of RapidlO Atomic Operations e Simultaneous mixing of frequencies between 1x ports all ports must be the same frequency e Target atomic operations including increment decrement test and swap set and clear for internal L2 memory and registers 1 3 Standards The SRIO peripheral is compliant to V1 2 of the Rapid O Interconnect Specification and V1 2 of the RapidlO Physical Layer 1x 4x LP Serial Specification These and the various associated documents listed herein can be found at the official RapidlO website www RapidlO org 1 4 External Devices Requirements SRIO provides a seamless interface to all devices which are compliant to V1 2 of the R
272. ing enable field 237 status field 237 interrupt generation 99 interrupt handling 100 interrupt pacing rate control 99 interrupt rate control registers 154 interrupt request field for LSUn 159 interrupt status decode registers description 150 introduction 97 mapping example 98 invert polarity bit for SERDES receiver 126 invert polarity bit for SERDES transmitter 128 INVPAIR field of SERDES_CFGRXn_CNTL 125 INVPAIR field of SERDES_CFGTXn_CNTL 128 I O error response at LSU reporting enable field 212 status field 210 IP_PRESCAL 233 IRQ_EN field of SPn_CTL_INDEP 236 IRQ_ERR field of SPn_CTL_INDEP 236 L L2 memory in Load Store module data flow diagram 39 lane select field for portn 206 large common transport system base device ID 193 large common transport system support field 186 LB field of SERDES_CFGn_CNTL 130 LCL_CFG_BAR 192 LCL_CFG_HBAR 191 LETTER_MASK field of RXU_MAP_Ln 178 LETTER field of RXU_MAP_Ln 178 letter number associated with logical transport error 217 letter number masking 45 letters and mailboxes 43 SPRUE13A September 2006 Submit Documentation Feedback limiting which devices can access a mailbox 45 line rate versus PLL output clock frequency 29 LINK_STATUS field of SPn_LM_RESP 201 LINK_TIMEOUT_EN field of SPn_RATE_EN 221 LINK_TIMEOUT field of SPn_ERR_DET 219 link maintenance command field for portn 240 link request control symbol generation register 200 link responses acknowledge or link response control
273. interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 5 bit 5 of TX_CPPI_ICSR e RX buffer descriptor queue 5 bit 5 of RX_CPPI_ICSR 25 ISD25 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 6 bit 6 of TX_CPPI_ICSR e RX buffer descriptor queue 6 bit 6 of RX_CPPI_ICSR 24 ISD24 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 7 bit 7 of TX_CPPI_ICSR e RX buffer descriptor queue 7 bit 7 of RX_CPPI_ICSR 23 ISD23 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 8 bit 8 of TX_CPPI_ICSR e RX buffer descriptor queue 8 bit 8 of RX_CPPI_ICSR 22 ISD22 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 9 bit 9 of TX_CPPI_ICSR e RX buffer descriptor queue 9 bit 9 of RX_CPPI_ICSR 21 ISD21 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 10 bit 10 of TX_CPPI_ICSR e RX buffer descriptor queue 10 bit 10 of RX_CPPI_ICSR 20 ISD20 0 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 11 bit 11 of
274. inued Bit Field Value Description 0 ENTX Enable transmitter 0 Disable this transmitter 1 Enable this transmitter Table 61 DE Bits of SERDES_CFGTXn_CNTL Amplitude Reduction DE Bits dB 0000b 0 0 0001b 4 76 0 42 0010b 9 52 0 87 0011b 14 28 1 34 0100b 19 04 1 83 0101b 23 8 2 36 0110b 28 56 2 92 0111b 33 32 3 52 1000b 38 08 4 16 1001b 42 85 4 86 1010b 47 61 5 61 1011b 52 38 6 44 1100b 57 14 7 35 1101b 61 9 8 38 1110b 66 66 9 54 1111b 71 42 10 87 Table 62 SWING Bits of SERDES_CFGTXn_CNTL SWING Bits Amplitude mVatpp 000b 125 001b 250 010b 500 011b 625 100b 750 101b 1000 110b 1125 111b 1250 SPRUE13A September 2006 Serial RapidlO SRIO 129 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 15 SERDES Macro Configuration Register n SERDES_CFGn_CNTL There are four of these registers to support four ports see Table 63 The general form for a SERDES transmit channel configuration register is summarized by Figure 76 and Table 64 See Section 2 3 2 1 for a complete explanation of the programming of this register Table 63 SERDES_CFGn_CNTL Registers and the Associated Ports Register Address Offset Associated Port SERDES CFGO_CNTL 0120h Port 0 Port 1 Port 2 and Port 3 SERDES CFG1_CNTL 0124h Not Used Program as 0x00000000 SERDES CFG2_CNTL 0128h Not Used Program as 0x00000000 SERDES_CFG3_CNTL
275. ion Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com Table 161 Port Error Rate Enable CSR n SPn_RATE_EN Field Descriptions continued Bit Field Value Description 19 PKT_UNEXPECTED_ACKID_EN Rate counting enable for packets with unexpected ackIDs Disable error rate counting of packets with unexpected out of sequence ackIDs Enable error rate counting of packets with unexpected out of sequence acklDs 18 RCVED_PKT_WITH_BAD_CRC_EN Rate counting enable for packets with bad CRC Disable error rate counting of packets with abad CRC values Enable error rate counting of packets with a bad CRC values 17 RCVED_PKT_OVER_276B_EN Rate counting enable for oversize packets Disable error rate counting of packets that exceed the maximum allowed size Enable error rate counting of packets that exceed the maximum allowed size 16 6 Reserved These read only bits return Os when read NON_OUTSTANDING_ACKID_EN Rate counting enable for non outstanding ackIDs Disable error rate counting of link responses received with an ackID that is not outstanding Enable error rate counting of link responses received with an ackID that is not outstanding PROTOCOL_ERROR_EN Rate counting enable for protocol errors Disable error rate counting of protocol errors Enable error rate counting of protocol errors Reserved This read only bit returns 0 when read DELINEAT
276. ion Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 57 Source Operations CAR SRC_OP The source operations CAR SRC_OP is shown in Figure 120 and described in Table 128 Figure 120 Source Operations CAR SRC_OP Address Offset 1018h 31 24 Reserved R 0 23 18 17 16 Reserved IMPLMNT_DEFINED_2 R 0 R 00 15 14 13 12 11 10 9 8 STREAM WRITE wm ATOMIC_TEST_ READ WRITE WE Bee DATA MESS DOORBELL Reserved AND SWAP R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 ATOMIC ATOMIC ATOMIC ATOMIC PORT_ INCRMNT DCRMNT SET CLEAR Reserved WRITE RER E R 0 R 0 R 0 R 0 R 0 R 1 R 00 LEGEND R Read only n Value after reset Table 128 Source Operations CAR SRC_OP Field Descriptions Bit Field Value Description 31 18 Reserved 0 These read only bits return Os when read 17 16 IMPLMNT_DEFINED_2 Defined by the device implementation 15 READ PE can support a read operation 14 WRITE PE can support a write operation 13 STREAM_WRITE PE can support a streaming write operation 12 WRITE_WITH_RESP PE can support a write with response operation 11 DATA_MESS PE can support a data message operation 10 DOORBELL PE can support a doorbell operation 9 Reserved 0 This read only bit returns 0 when read 8 ATOMIC_TEST_ PE can support an atomic test and swap operation AND_SWAP 7 ATOMIC_I
277. ions ceeceeeeeee eee nun eee e eee nun sees nun nun nun nnnnan nun 112 43 Peripheral Settings Control Register PER_SET_CNTL Field Descriptions cseeeeeeeeeeeeeeeeeee eens 113 44 Peripheral Global Enable Register GBL_EN Field Description 116 45 Peripheral Global Enable Status Register GBL_EN_STAT Field Descriptions 200 eeeeeeeeeeeeees 117 46 Block n Enable Registers and the Associated Blocks 200cceeeeeee cece cence eee nun cece nun nenn nun nenn nn nenn 119 47 Block n Enable Register BLKn_EN Field Descrtotions cece eee eee eee eee eeeeeeeeeeeeeeeaeeeeeeee 119 48 Block n Enable Status Registers and the Associated Blocks nn nen ann nun nun nn nenn nenn nennen 120 49 Block n Enable Status Register BLKn_EN_STAT Field Descrpttons nennen nn an nun nn 120 List of Tables SPRUE13A September 2006 Submit Documentation Feedback 50 RapidlO DEVICEID1 Register DEVICEID_REG1 Field Descriptions 0cceeeeeeeeee eee nn nun nun nennen 121 51 RapidlO DEVICEID2 Register DEVICEID_REG2 Field Descriptions 0cceeeeeeeee non ee en nun nun nennen 122 52 PF 16B ENTIL Registers sssaaeneenaeieniain anna na an ee ea 123 53 Packet Forwarding Register n for 16 Bit DevicelDs PF_16B_CNTLn Field Descriptions 123 54 PF 8B ENTL Registers a u a nee na aid cig an a Tee E ala aan NEEN RN malen 124 55 Packet Forwarding Register n for 8 Bit DevicelDs PF_8B_CNTLn Field Descriptions
278. iority based RX FIFOs to the CPPI module s data buffer within the shared buffer pool The mbox mailbox header fields are examined by the mailbox mapper block of the CPPI module Based on the mailbox and message length the data is assigned memory addresses within memory Data is transferred via DMA bus commands to memory from the buffer space of the peripheral The maximum buffer space should accommodate 256 bytes of data as that is the maximum payload size of a RapidlO packet Each message in memory will be represented by a buffer descriptor in the queue The following rules exist for all CPPI traffic e One buffer descriptor is provided per message each buffer descriptor consists of 4 words or 16 bytes e Contiguous memory space is required for multi segment read and write operations There are fixed buffer sizes configured to handle the application s maximum message size e An ERROR response is sent if the RX message is too big for the allotted buffer space ERROR responses are sent for all subsequent segments of that message e An ERROR response is sent if the mailbox is not mapped or if it is mapped to a non existent queue e An ERROR response is sent if the mailbox is mapped but the queue is not initialized the head descriptor pointer is not written or if the queue is disabled due to a teardown e An ERROR response is sent if the RX buffer descriptor queue has no empty buffers there is an overflow SPRUE13A September 2006
279. ists the names and address offsets of the memory mapped registers for the Serial RapidlO SRIO peripheral See the device specific data manual for the exact memory addresses of these registers Table 40 Serial RapidlO SRIO Registers Offset Acronym Register Description Section 0000h PID Peripheral Identification Register Section 5 2 0004h PCR Peripheral Control Register Section 5 3 0020h PER_SET_CNTL Peripheral Settings Control Register Section 5 4 0030h GPL EN Peripheral Global Enable Register Section 5 5 0034h GBL_EN_STAT Peripheral Global Enable Status Section 5 6 0038h BLKO_EN Block Enable 0 Section 5 7 003Ch BLKO_EN_STAT Block Enable Status 0 Section 5 8 0040h BLK1_EN Block Enable 1 Section 5 7 0044h BLK1_EN STAT Block Enable Status 1 Section 5 8 0048h BLK2_EN Block Enable 2 Section 5 7 004Ch BLK2_EN_ STAT Block Enable Status 2 Section 5 8 0050h BLK3_EN Block Enable 3 Section 5 7 0054h BLK3_EN STAT Block Enable Status 3 Section 5 8 0058h BLK4_EN Block Enable 4 Section 5 7 005Ch BLK4_EN_STAT Block Enable Status 4 Section 5 8 0060h BLK5 EN Block Enable 5 Section 5 7 0064h BLK5 EN STAT Block Enable Status 5 Section 5 8 0068h BLK6_EN Block Enable 6 Section 5 7 006Ch BLK6_EN_STAT Block Enable Status 6 Section 5 8 0070h BLK7_EN Block Enable 7 Section 5 7 0074h BLK7_EN_STAT Block Enable S
280. it request the TXU moves to the next queue in the round robin loop of TX buffer descriptor queues The TXU tries to send the unsent message again the next time the round robin scheduler returns to the given queue Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description For multi segment messages if the transfer is unsuccessful after 256 times of credit request for the first segment the TXU moves to the next queue in the round robin loop The TXU tries to send the unsent message again the next time around the loop After the first segment is granted outbound credit and is sent to the physical layer for transmission all subsequent segments are given 64K attempts to gain outbound credit If the TXU is unsuccessful after the 64K attempts a completion code of 111b is written to the buffer descriptor and the message is cancelled with no attempt to resend 2 3 13 Initialization Example 2 3 13 1 Enabling the SRIO Peripheral When the device is powered on the SRIO peripheral is in a disabled state Before any SRIO specific initialization can take place the peripheral needs to be enabled otherwise its registers cannot be written and the reads will all return a value of zero Glb enable srio SRIO_REGS gt GBL_EN 0x00000001 SRIO_REGS gt BLKO_EN 0x00000001 MMR_EN SRIO_REGS gt BLK5_EN 0x00000001 PORTO_EN SRIO_REGS gt BLKI_EN 0
281. ith BYTE_COUNT to create 64 bit aligned RapidlO packet header Config_offset The 2 LSBs of this field must be zero since the smallest configuration access is 4 bytes DSP Address 32 bit DSP byte address Not available in RapidlO Header Byte_Count Number of data bytes to Read Write up to 4K bytes Used in conjunction with RapidlO address to create WRSIZE RDSIZE and WDPTR in RapidlO packet header 000000000000b 4K bytes 000000000001b 1 byte 000000000010b 2 bytes 111111111111b 4095 bytes Maintenance requests are limited to 4 bytes ID Size RapidlO tt field specifying 8 or 16 bit DevicelDs 00b 8 bit devicelDs 01b 16 bit devicelDs 10b reserved 11b reserved Priority RapidlO prio field specifying packet priority 0 lowest 3 highest Request packets should not be sent at a priority level of 3 to avoid system deadlock It is the responsibility of the software to assign the appropriate outgoing priority Xamsbs RapidlO xamsb field specifying the extended address MSBs 36 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 14 LSU Control Command Register Fields continued LSU Register Field RapidlO Packet Header Field DestID RapidlO destinationID field specifying the target device Packet Type 4 MSBs 4 bit ftype field for all packets
282. its ICS15 ICS8 and ICSO of DOORBELLO_ICSR correspond to Doorbell 0 information bits 15 8 and 0 The 16 ICC bits of each interrupt condition clear register ICCR are used to clear the corresponding bits in the ICSR For example the ICC7 bit of DOORBELL2_ICCR is used to clear the ICS7 bit of DOORBELL2_ICSR Figure 46 Doorbell 0 Interrupt Condition Status and Clear Registers Doorbell 0 Interrupt Condition Status Register DOORBELLO_ICSR Address Offset 0200h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICSO HO R 0 R 0 R 0 R 0 HO R 0 R 0 HO R 0 R 0 R 0 HO R 0 R 0 R 0 Doorbell 0 Interrupt Condition Clear Register DOORBELLO_ICCR Address Offset 0208h 31 1e Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cc15 cc14 16013 cc12 cc11 ccto icco ccs cc7 icce 1ccs5 cca cc3 cc2 icc1 icco W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n Value after reset Figure 47 Doorbell 1 Interrupt Condition Status and Clear Registers Doorbell 1 Interrupt Condition Status Register DOORBELL1_ICSR Address Offset 0210h 31 16 Reserved HO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13
283. ived n anyport Offset 0x0278 Offset 0x12004 ERR_RST_EVNT_ICCR 0 SP_IP_MODE 4 Port Write In Request received Write 1 to clear Write 1 to clear an any por Offset 0x0278 Offset 0x12004 ERR_RST_EVNT_ICCRI1 SP_IP_MODE 0 Port 0 Error Write 1 to clear Offset 0x0278 ERR_RST_EVNT_ICCR 8 Write 1 to clear any of the Write 1 to clear following possible bits Offset 0x2040 SPO_ERR_STATI2 Fatal error SPO_ERR_STAT 25 Failed Threshold SPO_ERR_STAT 24 Degraded Threshold Offset 0x14004 SPO_CTL_INDEP 20 Illegal Transaction SPO_CTL_INDEP 16 Max Retry Error Offset 0x14004 SPO_CTL_INDEPI6 Port 1 Error Write 1 to clear Offset 0x0278 ERR_RST_EVNT_ICCRI9 Write 1 to clear any of the Write 1 to clear following possible bits Offset 0x2080 SP1_ERR_STATI2 Fatal error SP1_ERR_STAT 25 Failed Threshold SP1_ERR_STAT 24 Degraded Threshold Offset 0x14104 SP1_CTL_INDEP 20 Illegal Transaction SP1_CTL_INDEP 16 Max Retry Error Offset 0x14104 SP1_CTL_INDEP 6 Port 2 Error TMS320TCI6482 Only Write 1 to clear Offset 0x0278 ERR_RST_EVNT_ICCR 10 Write 1 to clear any of the Write 1 to clear following possible bits Offset 0x20C0 SP2_ERR_STATI2 Fatal error SP2_ERR_STAT 25 Failed Threshold SP2_ERR_STAT 24 Degraded Threshold Offset 0x14204 SP2_CTL_INDEP 20 Illegal Transaction SP2_CTL_INDEP 16 Ma
284. ives packet data for a transmitting device s TX pins Bit used in 1 port 1X device 4 port 1x device and 1 port 4X device Reference Clock Input Buffer for peripheral clock recovery circuitry Functional Operation Component Block Diagram Figure 8 shows a component block diagram of the SRIO peripheral The load store unit LSU controls the transmission of direct I O packets and the memory access unit MAU controls the reception of direct I O packets The LSU also controls the transmission of maintenance packets Message packets are transmitted by the TXU and received by the RXU These four units use the internal DMA to communicate with internal memory and they use buffers and receive transmit ports to communicate with external devices Serializer deserializer SERDES macros support the ports by performing the parallel to serial coding for transmission and serial to parallel decoding for reception Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Figure 8 SRIO Component Block Diagram Load Store Memory units LSUs TXU access unit RXU TX direct UO Messaging MAU Messaging RX direct I O Maintenance 4 5 KB TX 4 5 KB RX shared shared buffer buffer Queue handle TX buffering 32 x 276B Transaction Logical 8 buffers per 1X port all priorities mapping layer 32 buffers per 4X
285. k o Enable Register BLKN_EN secceeeeeeeee cece cece eee nee nun nun nnunnunnannnannun mann nannannnunnannann nenn 119 69 Block n Enable Status Register BLKn_EN 0 ceceeeeeee settee eee eee eens eee eens eee nun nunnen nun nun une nenn 120 70 RapidlO DEVICEID1 Register DEVICEID_REG1 Offset 0080h ceeeeeeee eee eeeeeee mann nn nn nn 121 71 RapidlO DEVICEID2 Register DEVICEID_REG2 Offset OvOO8A cette nun nnnan nun nnn nun 122 72 Packet Forwarding Register n for 16 Bit Device IDs PF_16B_CNTLn u 2uss usun nenn nen nn nun nun nn nn 123 73 Packet Forwarding Register n for 8 Bit Device IDs PF_8B_CNTLn ccceeeeeeeee eens eens ee nun nun en nun 124 74 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL 222 usun nennen nn nennen 125 75 SERDES Transmit Channel Configuration Register n SERDES CFGTXn_CNTL cceeeeeeeeeeee eee eee 128 76 SERDES Macro Configuration Register n SERDES_CFGn_CNTL zuussaunsunennnannnnnnnnnannnnn nun nun nen 130 77 Doorbell n Interrupt Condition Status Register DOORBELLnN_ICSR zuuusunnnnnunnnnnnnnnannnun nun nenn nn 132 78 Doorbell n Interrupt Condition Clear Register DOORBELLnN ICH 133 79 RX CPPI Interrupt Condition Status Register RX_CPPI_ICSR Address Offset 0240h 134 80 RX CPPI Interrupt Condition Clear Register RX_CPPI_ICCR Address Offset 0248h seeeeeeeeeeeee 135 81 TX CPPI Interrupt Condition Status Register TX_CPPI_ICSR
286. ket is sent Writes when the bit is set are ignored Debug mode only 21 ILL_TRANS_EN Illegal transfer error reporting enable If enabled the Port Write and interrupt are reported errors Disable illegal transfer error reporting Enable illegal transfer error reporting 20 ILL_TRANS_ERR Illegal Transfer Error After being set the ILL_TRANS_ERR bit remains set until written with a 1 or until a value of all Os is written to the register SPO_ERR_DET No error condition detected One of the following error conditions has been detected e The received transaction has a reserved value in the tt field e A reserved field of Maintenance transaction type is detected e The destination ID is not defined in look up table This error is also reported in registers SPO_ERR_DET and ERR_DET 19 18 Reserved These read only bits return Os when read 17 MAX_RETRY_EN Ob 1b Maximum retry error reporting enable If enabled the Port Write and interrupt are reported as errors Max retry error report disable Max retry error report enable 16 MAX_RETRY_ERR Maximum retry error This bit is ignored if max_retry_threshold is 0 Once set the MAX_RETRY_ERR bit remains set until written with a 1 or until a value of all Os is written to the register SPO_ERR_DET No error condition detected max_retry_cnt is equal to max_retry_threshold The Port Write request and interrupt are generated if enabled This error
287. l RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Functional Description Figure 14 Example Burst NWRITE_R LSUn_REG2 DSP Address DMA Read LSUn_REG4 eg Source Address OutPortID Priority xambs ID Size DestID RSV Interrupt Req Destination Address 31 8 7 1 D Count LSUn_REG3 LSUn_REG5 Byte Count Drbll Hop Count Packet 31 16 15 87 Count translator rdsize rdptr wsize wptr LSUn_REGO LSUn_REG1 RapiolO Address Config_offset NodelD Count 8 ackID rsv prio tt ftype destID sourcelD trans wrsize srcTID ext addr address wrptr xamsbs payload CRC 5 3 2 2 4 8 8 4 4 8 32 29 7 2 16 TX Shared Buffer Pool For WRITE commands the payload is combined with the header information from the control command registers and buffered in the shared TX buffer resource pool Finally it is forwarded to the TX FIFO for transmission READ commands have no payload In this case only the control command register fields are buffered and used to create a RapidlIO NREAD packet which is forwarded to the TX FIFO Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer resource pool when forwarded from the receive ports Both posted and non posted operations rely on the OutPortID command regist
288. l Register 1 Section 5 49 07E8h TX_QUEUE_CNTL2 Transmit CPPI Weighted Round Robin Control Register 2 Section 5 49 07ECh TX_QUEUE_CNTL3 Transmit CPPI Weighted Round Robin Control Register 3 Section 5 49 0800h RXU_MAP_LO MailBox to Queue Mapping Register LO Section 5 50 0804h RXU_MAP_HO MailBox to Queue Mapping Register HO Section 5 50 0808h RXU_MAP_L1 MailBox to Queue Mapping Register L1 Section 5 50 080Ch RXU_MAP_H1 MailBox to Queue Mapping Register H1 Section 5 50 0810h RXU_MAP_L2 MailBox to Queue Mapping Register L2 Section 5 50 0814h RXU_MAP_H2 MailBox to Queue Mapping Register H2 Section 5 50 0818h RXU_MAP_L3 MailBox to Queue Mapping Register L3 Section 5 50 081Ch RXU_MAP_H3 MailBox to Queue Mapping Register H3 Section 5 50 0820h RXU_MAP_L4 MailBox to Queue Mapping Register L4 Section 5 50 0824h RXU_MAP_H4 MailBox to Queue Mapping Register H4 Section 5 50 0828h RXU_MAP_L5 MailBox to Queue Mapping Register L5 Section 5 50 082Ch RXU_MAP_H5 MailBox to Queue Mapping Register H5 Section 5 50 0830h RXU_MAP_L6 MailBox to Queue Mapping Register L6 Section 5 50 0834h RXU_MAP_H6 MailBox to Queue Mapping Register H6 Section 5 50 106 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 S
289. l available buffer descriptors e CPU acknowledges the interrupt by writing the CP value e This value is compared against the port written value in the TX DMA State CP register if equal the interrupt is deasserted Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Initialization Example SRIO_REGS gt Queue0_RXDMA_HDP 0 SRIO_REGS gt Queuel_RXDMA_HDP 0 SRIO_REGS gt Queue2_RXDMA_HDP 0 SRIO_REGS gt Queue3_RXDMA_HDP 0 SRIO_REGS gt Queue4_RXDMA_HDP 0 SRIO_REGS gt Queue5_RXDMA_HDP 0 SRIO_REGS gt Queue6_RXDMA_HDP 0 SRIO_REGS gt Queue7_RXDMA_HDP 0 SRIO_REGS gt Queue8_RXDMA_HDP 0 SRIO_REGS gt Queue9_RXDMA_HDP 0 SRIO_REGS gt Queuel0_RXDMA_HDP 0 SRIO_REGS gt Queuell_RXDMA_HDP 0 SRIO_REGS gt Queuel2_RXDMA_HDP 0 SRIO_REGS gt Queuel3_RXDMA_HDP 0 SRIO_REGS gt Queuel4_RXDMA_HDP D SRIO_REGS gt Queuel5_RXDMA_HDP 0 Queue Mapping SRIO_REGS gt RXU_MAPOl_L CSL_FMK SRIO_RXU_MAPO L_LETTER_MASK 3 CSL_FMK SRIO_RXU_MAPO L_MAILBOX_MASK 0x3F CSL_FMK SRIO_RXU_MAPOI1_L_LETTER 0 CSL_FMK SRIO_RXU_MAPO1_L_MAILBOX 1 CSL_FMK SRIO_RXU_MAPO1_L_SOURCEID OxBEEF SRIO_REGS gt RXU_MAPOl_H CSL_FMK SRIO_RXU_MAPO1_H_TT 1 CSL_FMK SRIO_RXU_MAPO H_QUEUE_ID 0 CSL_FMK SRIO_RXU_MAPO1_H
290. l block 0 is in reset with its clock off 1 Logical block 0 is enabled with its clock running 0 GBL_EN_STAT Global enable status 0 The peripheral is in reset with all its clocks off 1 The peripheral is enabled with all its clocks running 118 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 7 Block n Enable Register BLKn_EN There are nine of these registers one for each of nine logical blocks in the peripheral The registers and the blocks they support are listed in Table 46 The general form for a block n enable register BLKn_EN is shown in Figure 68 and described in Table 47 For additional programming information see Section 2 3 10 Table 46 Block n Enable Registers and the Associated Blocks Register Address Offset Associated Block BLKO_EN 0038h Logical block 0 the set of memory mapped control registers for the SRIO peripheral BLK1_EN 0040h Logical block 1 the Load Store module the four LSUs and supporting logic BLK2_EN 0048h Logical block 2 the memory access unit MAU BLK3_EN 0050h Logical block 3 the message transmit unit TXU BLK4_EN 0058h Logical block 4 the message receive unit RXU BLK5_EN 0060h Logical block 5 SRIO port 0 BLK6_EN 0068h Logical block 6 SRIO port 1 BLK7_EN 0070h Logical block 7 SRIO port 2 BLK8_EN 0078h Logical block 8 SRIO port 3 Figure 68 Block n Enable Register BLKn_EN
291. l block 6 is enabled with its clock running 6 BLK5_EN_STAT Block 5 enable status Logical block 5 is SRIO port 0 0 Logical block 5 is in reset with its clock off 1 Logical block 5 is enabled with its clock running 5 BLK4_EN_STAT Block 4 enable status Logical block 4 is the message receive unit RXU 0 Logical block 4 is in reset with its clock off 1 Logical block 4 is enabled with its clock running 4 BLK3_EN_STAT Block 3 enable status Logical block 3 is the message transmit unit TXU 0 Logical block 3 is in reset with its clock off 1 Logical block 3 is enabled with clock running 3 BLK2_EN_STAT Block 2 enable status Logical block 2 is the memory access unit MAU 0 Logical block 2 is in reset with its clock off 1 Logical block 2 is enabled with its clock running 2 BLK1_EN_STAT Block 1 enable status Logical block 1 is the Load Store module which is comprised of the four Load Store units LSU1 LSU2 LSU3 and LSU4 0 Logical block 1 is in reset with its clock off 1 Logical block 1 is enabled with its clock running SPRUE13A September 2006 Serial RapidlO SRIO 117 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com Table 45 Peripheral Global Enable Status Register GBL_EN_STAT Field Descriptions continued Bit Field Value Description 1 BLKO_EN_STAT Block 0 enable status Logical block 0 is the set of memory mapped registers MMRs for the SRIO peripheral 0 Logica
292. ld Value Description 31 ISD31 0 No interrupt request routed to this bit 1 Interrupt request detected Possible interrupt sources e An LSU check LSU_ICSR e TX buffer descriptor queue 0 bit O of TX_CPPI_ICSR e RX buffer descriptor queue 0 bit 0 of RX_CPPI_ICSR 30 ISD30 0 No interrupt request routed to this bit 1 Interrupt request detected Possible interrupt sources e A port check ERR_RST_EVNT_ICSR e TX buffer descriptor queue 1 bit 1 of TX_CPPI_ICSR e RX buffer descriptor queue 1 bit 1 of RX_CPPI_ICSR 29 ISD29 0 No interrupt request routed to this bit 1 Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 2 bit 2 of TX_CPPI_ICSR e RX buffer descriptor queue 2 bit 2 of RX_CPPI_ICSR 28 ISD28 0 No interrupt request routed to this bit 1 Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 3 bit 3 of TX_CPPI_ICSR e RX buffer descriptor queue 3 bit 3 of RX_CPPI_ICSR 150 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 84 Interrupt Status Decode Register INTDSTn_DECODE Field Descriptions continued Bit Field Value Description 27 ISD27 0 No interrupt request routed to this bit 1 Interrupt request detected Possible interrupt sources e TX buffer descriptor queue 4 bit 4 of TX_CPPI_ICSR e RX buffer descriptor queue 4 bit 4 of RX_CPPI_ICSR 26 ISD26 0 No
293. le DestIDs from incoming packet 2 3 15 2 Daisy Chain Operation and Packet Forwarding Some applications may require daisy chaining of devices together versus using a switch fabric Typically these applications are low cost implementations Daisy chains have variable system latency depending on device position within the chain Daisy chain implementations also have reduced bandwidth capabilities since the link bandwidth doesn t change the bandwidth allocated to each device in the chain is limited sum of devices individual bandwidth needs can t exceed link bandwidth To support daisy chain or ring topologies the peripheral features a hardware packet forwarding function This feature eliminates the need for software to be involved in routing a packet to the next device in the chain The basic idea behind the hardware packet forwarding logic is to provide an input port to output port path such that the packets never leave the peripheral no DMA transfer A simple check of an in coming packet s DestID versus the device s DevicelD and MulticastID is done to determine if the packet should be forwarded If the packet s DestID matches DevicelD the packet is accepted and processed by the device If the packet s DestID matches the MulticastID the packet is accepted by the device and forwarded based on the rules outlined in Section 2 3 15 1 If the packet s DestID doesn t match either the packet is simply destroyed or forwarded dependin
294. le words 111111111b 511 double words src_id Source Node ID Unique node identifier of the source of the message Written by the DSP core tt RapidlO tt field specifying 8 or 16 bit DevicelDs Written by the DSP core 00b 8 bit devicelDs 01b 16 bit devicelDs 10 reserved 11 reserved pri Message Priority Specifies the SRIO priority at which the message was sent Written by the DSP core cc Completion Code Written by the port 000 Good completion Message received 001 Error RX message length greater than supported buffer descriptor message_length 010 Error TimeOut on receiving one of the segments 011 DMA transfer error on one or more segments 100 Queue teardown completed data invalid 101 111 Reserved mailbox Destination Mailbox Specifies the mailbox to which the message was sent Written by the DSP core 000000b Mailbox 0 000001b Mailbox 1 000100b Mailbox 4 111111b Mailbox 63 For multi segment messages only the two LSBs of this mailbox are valid Hardware ignores the four MSBs if the incoming message has multiple segments 48 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SPRUE13A September 2006 Submit Documentation Feedback co B2 B1 BO A1 AO SRIO Functional Description Although the switch fabric delivers the segments of multi packet messages in the order they were sent buffer resources at the receiving endpoint
295. lts immediately This mode is not supported in the peripheral TX Buffers Credit and Packet Reordering Packets to be transmitted by the SRIO peripheral travel to logical layer buffers The packets are then moved from the logical layer buffers to physical layer buffers From the physical layer buffers the packets are transmitted through a port to a connected device 2 3 12 1 Multiple Ports With 1x Operation With multiple ports in 1x mode logical layer buffers are grouped per port and contain all priorities Each group is 8 buffers deep A counter is maintained for each port to track available buffer credit across the UDI The count is initialized to 8 credits per port The count is decremented each time a packet is sent across the UDI for a port Each port buffer group has a buffer release signal which indicates the release of a packet from the logical layer buffer to the port s physical buffer thus indicating the freeing up of space in the port s logical buffer Thresholds are used to govern outbound credit when requested by the protocol units MAU RXU TXU and the LSUs These thresholds are programmable in the peripheral settings control register PER_SET_CNTL at address offset 0020h The physical layer buffer tries to process all packets in the order they were sent across the UDI However it is also governed by a re ordering algorithm to decide which packets may be sent to the physical layer buffer depending on credit availability ther
296. m SRIO Registers 5 3 Peripheral Control Register PCR The peripheral control register PCR contains a bit that enables or disables data flow in the logical layer of the entire peripheral In addition the PCR has emulation control bits that control the peripheral behavior during emulation halts PCR is shown in Figure 64 and described in Table 42 For additional programming information see Section 2 3 11 Figure 64 Peripheral Control Register PCR Address Offset 0004h 31 16 Reserved HO 15 3 2 1 0 Reserved PEREN SOFT FREE R 0 R W 0 R W 0 R W 1 LEGEND R W Read Write R Read only n Value after reset Table 42 Peripheral Control Register PCR Field Descriptions Bit Field Value Description 31 3 Reserved 0 These read only bits return Os when read 2 PEREN Peripheral flow control enable Controls the flow of data in the logical layer of the peripheral As an initiator it will prevent TX transaction generation as a target it will disable incoming requests This should be the last enable bit to toggle when bringing the device out of reset to begin normal operation 0 Data flow control is disabled Data flow control is enabled 1 SOFT Ger stop This bit and the FREE bit determine how the SRIO peripheral behaves during emulation alts 0 Hard stop All status registers are frozen in default state This mode is not supported on the SRIO peripheral 1 Soft stop 0 FREE Free
297. m Doorbell 2 bit 6 is sent to interrupt destination 2 Doorbell 0 Interrupt Condition Routing Register DOORBELLO_ICRR Address Offset 0280h Figure 54 Doorbell 0 Interrupt Condition Routing Registers 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR3 ICR2 ICR1 ICRO R W 0000 R W 0000 R W 0000 R W 0000 Doorbell 0 Interrupt Condition Routing Register 2 DOORBELLO_ICRR2 Address Offset 0284h 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 87 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R W Read Write n Value after reset 4 4 1 1 CPPI Interrupt Condition Routing Registers Figure 55 shows the ICRRs for the RXU and Figure 56 shows the ICRRs for the TXU These registers route queue interrupts to interrupt destinations For example if ICS6 1 in RX_CPPI_ICSR and ICR6 0010b in RX_CPPI_ICRR the interrupt request from RX buffer descriptor queue 6 is sent to interrupt destination 2 Similarly if ICS6 1 in TX_CPPI_ICSR and ICR6 0011b in TX_CPPI_ICRR the interrupt request from TX buffer descriptor queue 6 is sent to interrupt destination 3 RX CPPI Interrupt Condition Routing Register RX_CPPI_ICRR Address Offset 02COh Figure 55 RX CPPI Interrupt Condition Routing Registers 31 28 27 24 23
298. mation field for port n error capture 223 U UDI definition 40 in Load Store module data flow diagram 39 in SRIO component block diagram 26 UDI buffering setup field 114 unacknowledged acklD status field 202 unavailable outbound credit 76 undefined Ftypes 25 unexpected acklD in control symbol at port n rate counting enable field 221 254 Index status field 219 unexpected acklD in packet at port n rate counting enable field 222 status field 220 unexpected acknowledge control symbol at port n rate counting enable field 222 status field 220 unexpected control symbol at port n rate counting enable field 222 status field 220 unexpected packet at port n rate counting enable field 222 status field 220 uninitialized status bit for ports 205 unrecoverable error status bit for ports 204 UNSOLICITED_ACK_CNTL_SYM_EN field of SPn_RATE_EN 221 UNSOLICITED_ACK_CNTL_SYM field of SPn_ERR_DET 219 UNSOLICITED_RESP_ENABLE field of ERR EN 212 UNSOLICITED_RSPNS field of ERR_DET 210 unsolicited response at LSU or TXU reporting enable field 213 status field 211 UNSUPPORTED_TRANS_ENABLE field of ERR_EN ala UNSUPPORTED_TRANS field of ERR_DET 210 unsupported transaction at MAU reporting enable field 213 status field 211 User Defined Interface See UDI 40 V valid information field for port n error capture 223 W weighted round robin access to TX buffer descriptor queues 54 weighted round robin control registers 174 width field f
299. may create HOL blocking issues on that queue Figure 28 Transmit Source Flow Control Masks 31 16 15 0 RIO_LSUn_FLOW_MASKS Address Offsets 0x041C Reserved LSU n Flow Mask 0x043C 0x045C 0x047C R 0x0000 R W OxFFFF 31 16 15 0 31 16 15 0 RIO_TX_CPPI_FLOW_MASKSO TX Queue TX QueueOd RIO_TX_CPPI_FLOW_MASKS4 TX Queue9 TX Queue8 Address Offsets 0x0704 Flow Mask Flow Mask Address Offsets 0x0714 Flow Mask Flow Mask R W OxFFFF R W OxFFFF R W OxFFFF RM OxFFFF 31 16 15 0 31 16 15 0 RIO_TX_CPPI_FLOW_MASKS1 TX Queue3 TX Queue2 RIO_TX_CPPI_FLOW_MASKS5 TX Queue11 TX Queue10 Address Offsets 0x0708 Flow Mask Flow Mask Address Offsets 0x0718 Flow Mask Flow Mask R W OxFFFF RM OxFFFF R W OxFFFF RM OxFFFF 31 16 15 0 31 16 15 0 RIO_TX_CPPI_FLOW_MASKS2 TX Queue5 TX Queue4 RIO_TX_CPPI_FLOW_MASKS6 TX Queue13 TX Queue12 Address Offsets 0x070C Flow Mask Flow Mask Address Offsets 0x071C Flow Mask Flow Mask R W OxFFFF RM OxFFFF RIW OxFFFF RM OxFFFF 31 16 15 0 31 16 15 0 RIO_TX_CPPI_FLOW_MASKS3 TX Queue7 TX Queue6 RIO_TX_CPPI_FLOW_MASKS7 TX Queue15 TX Queue14 Address Offsets 0x0710 Flow Mask Flow Mask Address Offsets 0x0720 Flow Mask Flow Mask R W OxFFFF R W OxFFFF R W OxFFFF R W OxFFFF LEGEND R W Read Write R Read only n Value after reset Figure 29 Fields Within Each Flow Mask 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FL15 FL14 FL13 FL12 FL11 FL10
300. mers These 4 bits are the prescaler reload value allowing division of the DMA clock by a range from 1 up to 16 Setting should reflect the device DMA frequency in MHz Sets the internal clock frequency Min 44 7 and Max 89 5 Sets the internal clock frequency Min 89 5 and Max 179 0 Sets the internal clock frequency Min 134 2 and Max 268 4 Sets the internal clock frequency Min 180 0 and Max 360 0 Sets the internal clock frequency Min 223 7 and Max 447 4 Sets the internal clock frequency Min 268 4 and Max 536 8 Sets the internal clock frequency Min 313 2 and Max 626 4 Sets the internal clock frequency Min 357 9 and Max 715 8 sets the internal clock frequency Min 402 7 and Max 805 4 Sets the internal clock frequency Min 447 4 and Max 894 8 Sets the internal clock frequency Min 492 1 and Max 984 2 Sets the internal clock frequency Min 536 9 and Max 1073 8 Sets the internal clock frequency Min 581 6 and Max 1163 2 Sets the internal clock frequency Min 626 3 and Max 1252 6 Sets the internal clock frequency Min 671 1 and Max 1342 2 Sets the internal clock frequency Min 715 8 and Max 1431 6 114 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUME NTS www ti com Table 43 Peripheral Settings Control Register PER_SET_CNTL Field Descriptions continued SRIO Registers Bit Field Value Description 3 ENPLL4 0 Not used Should always be programmed as 0 See Section 2 3 2 1 t
301. mode Transmit data to receive on the same port Packet data is looped back in the digital domain before the SERDES macros 24 BOOT_COMPLETE Controls ability to write any register during initialization It also includes read only registers during normal mode of operation that have application defined reset value 0 Write to read only registers enabled Write to read only registers disabled Usually the boot_complete is asserted once after reset to define power on configuration 23 21 Reserved 000b These read only bits return Os when read 20 18 TX_PRI2_WM 000b 111b Transmit credit threshold Sets the required number of logical layer TX buffers needed to send priority 2 packets across the UDI This is valid for all ports in 1x mode only Required buffer count for transmit credit threshold 2 value TX_PRI2_WM e 000 8 7 6 5 4 3 2 1 effectively lets all of this priority pass e 001 8 7 6 5 4 3 2 e 010 8 7 6 5 4 3 e 011 8 7 6 5 4 e 100 8 7 6 5 e 101 8 7 6 e 110 8 7 e 111 8 SPRUE13A September 2006 Serial RapidlO SRIO 113 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com Table 43 Peripheral Settings Control Register PER_SET_CNTL Field Descriptions continued Bit Field Value Description 17 15 TX_PRH_WM 000b 111b Transmit credit threshold Sets the required number of logical layer TX buffers needed to send prio
302. n 5 27 02D0h TX_CPPI_ICRR Transmit CPPI Interrupt Condition Routing Register Section 5 28 02D4h TX_CPPI_ICRR2 Transmit CPPI Interrupt Condition Routing Register 2 Section 5 28 02E0h LSU_ICRRO LSU Interrupt Condition Routing Register 0 Section 5 29 02E4h LSU_ICRR1 LSU Interrupt Condition Routing Register 1 Section 5 29 02E8h LSU_ICRR2 LSU Interrupt Condition Routing Register 2 Section 5 29 02ECh LSU_ICRR3 LSU Interrupt Condition Routing Register 3 Section 5 29 02FOh ERR_RST_EVNT_ICRR Error Reset and Special Event Interrupt Condition Routing Section 5 30 Register 02F4h ERR_RST_EVNT_ICRR2 Error Reset and Special Event Interrupt Condition Routing Section 5 30 Register 2 02F8h ERR_RST_EVNT_ICRR3 Error Reset and Special Event Interrupt Condition Routing Section 5 30 Register 3 0300h INTDSTO_DECODE INTDST Interrupt Status Decode Register 0 Section 5 31 0304h INTDST1_DECODE INTDST Interrupt Status Decode Register 1 Section 5 31 0308h INTDST2_DECODE INTDST Interrupt Status Decode Register 2 Section 5 31 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 103 da TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section 030Ch INTDST3_DECODE INTD
303. n Table 28 Figure 34 BLKO_EN Address 0038h 31 1 0 Reserved EN R 0 RW 1 LEGEND R Read W Write n Value after reset 72 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Figure 35 BLKO_EN_STAT Address 003Ch 31 1 0 Reserved EN_STAT R 0 R 1 LEGEND R Read W Write n Value after reset Figure 36 BLK1_EN Address 0040h 31 1 0 Reserved EN R 0 R W 1 LEGEND R Read W Write n Value after reset Figure 37 BLK1_EN_STAT Address 0044h 31 1 0 Reserved EN_STAT R 0 R 1 LEGEND R Read W Write n Value after reset Figure 38 BLK8_EN Address 0078h 31 1 0 Reserved EN HO R W 1 LEGEND R Read W Write n Value after reset Figure 39 BLK8_EN_STAT Address 007Ch 31 1 0 Reserved EN_STAT HO R 1 LEGEND R Read W Write n Value after reset Table 28 Block Enable and Block Enable Status Field Descriptions Register Bit Field Valu Description e BLKn_EN 31 1 Reserved 0 These read only bits return Os when read BLKn_EN 0 EN Block n enable 0 Logical block nis to be reset with its clock off Logical block nis to be enabled with its clock running BLKn_EN_STAT 31 1 Reserved 0 These read only bits return Os when read BLKn_EN_STAT 0 EN_STAT Block n enable status 0 Logical block nis
304. n supports Flow 5 from table entry 4 FL4 0 Queue n does not support Flow 4 from table entry 1 Queue n supports Flow 4 from table entry 3 FL3 0 Queue n does not support Flow 3 from table entry 1 Queue n supports Flow 3 from table entry 2 FL2 0 Queue n does not support Flow 2 from table entry 1 Queue n supports Flow 2 from table entry 1 FL1 0 Queue n does not support Flow 1 from table entry 1 Queue n supports Flow 1 from table entry 0 FLO 0 Queue n does not support Flow 0 from table entry 1 Queue n supports Flow 0 from table entry SPRUE13A September 2006 Serial RapidlO SRIO 171 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com 5 47 Receive Queue Teardown Register RX_QUEUE_TEAR_DOWN Each of this register s bits corresponds to one of the 16 RX buffer descriptor queues If a 1 is written to a bit the teardown process is started for the associated queue RX_QUEUE_TEAR_DOWN is shown in Figure 110 and described in Table 115 For additional programming information see Section 2 3 4 1 Figure 110 Receive Queue Teardown Register RX_QUEUE_TEAR_DOWN Address Offset 0740h 31 16 Reserved R 0000h 15 14 13 12 11 10 9 8 QUEUE15_ QUEUE14_ QUEUE13_ QUEUE12_ QUEUE11_ QUEUE10_ QUEUE9_ QUEUE8_ TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN W 0 W 0 W 0 W 0 WO WO WO WO 7 6 5 4 3 2 1 0 QUEUE7_ QUEUE6_ QUEUE5_ QUEUE4_ QUE
305. n the LSUs When the DMA bus read request is transmitted the appropriate TX buffer address is specified within it The data payload is written to that buffer through the DMA bus response transaction Depending on the architecture of the device interleaving of multi segmented DMA bus responses from the DMA is possible Upon receipt of a DMA bus read response segment the unit checks the completion status of the payload Note that only one payload can be completed in any single DMA bus cycle The Load Store module can only forward the packet to the TX FIFO after the final payload byte from the DMA bus response has been written into the shared TX buffer Once the packet is forwarded to the TX FIFO the shared TX buffer can be released and made available for a new transaction The TX buffer space is dynamically shared among all outgoing sources including the Load Store module and the TX CPPI as well as the response packets from RX CPPI and the memory access unit MAU Thus the buffer space memory is partitioned to handle packets with and without payloads A 4 5K byte buffer space is configured to support 16 packets with payloads up to 256 bytes in addition to 16 packets without payloads The SRAM is configured as a 128 bit wide two port which matches the UDI width of the TX FIFOs Note The UDI User Defined Interface is a reference to the interface between a the SERDES and the FIFO queues and b the logical buffers shared buffers LSU and
306. nables alignment to the K28 comma symbols included in the 8b 10b data encoding scheme defined by the IEEE and employed by numerous transmission standards For systems which cannot use comma based symbol alignment the single bit alignment jog capability provides a means to control the symbol realignment features of the receiver directly from logic implemented in the ASIC core This logic can be designed to support whatever alignment detection protocol is required The EQ bits allow for enabling and configuring the adaptive equalizer incorporated in all of the receive channels which can compensate for channel insertion loss by attenuating the low frequency components with respect to the high frequency components of the signal thereby reducing inter symbol interference Above the zero frequency the gain increases at 6dB octave until it reaches the high frequency gain When enabled the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain of the equalizer should be increased or decreased For the fully adaptive setting EQ 0001 if the low frequency gain reaches the minimum value the zero frequency is then reduced Likewise if it reaches the maximum value the zero frequency is then increased This decision logic is implemented as a voting algorithm with a relatively long analysis interval The slow time constant that results reduces the probability of incorrect decisions but allows the equali
307. nctional Description SRIO_REGS gt SP_RT_CTL OxFFFFFFO0 long SRIO_REGS gt SP_GEN_CTL 0x40000000 agent master undiscovered SRIO_REGS gt SPO_CTL 0x00600000 enable i o SRIO_REGS gt SP1_CTL 0x00600000 enable i o SRIO_REGS gt SP2_CTL 0x00600000 enable i o SRIO_REGS gt SP3_CTL 0x00600000 enable i o SRIO_REGS gt ERR_DET 0x00000000 clear SRIO_REGS gt ERR_EN 0x00000000 disable SRIO_REGS gt H_ADDR_CAPT 0x00000000 clear SRIO_REGS gt ADDR_CAPT 0x00000000 clear SRIO_REGS gt ID_CAPT 0x00000000 clear SRIO_REGS gt CTRL_CAPT 0x00000000 clear SRIO_REGS gt SP_IP_PW_IN_CAPTO 0x00000000 clear SRIO_REGS gt SP_IP_PW_IN_CAPT1 0x00000000 clear SRIO_REGS gt SP_IP_PW_IN_CAPT2 0x00000000 clear SRIO_REGS gt SP_IP_PW_IN_CAPT3 0x00000000 clear INIT_WAIT wait for lane initialization Read register to check portx 1 4 OK bit polling SRIO_MAC s port_ok bit rdata SRIO_REGS gt PO_ERR_STAT while rdata amp 0x00000002 0x00000002 rdata SRIO_REGS gt PO_ERR_STAT if srio4plx_mode rdata SRIO_REGS gt P1_ERR_STAT while rdata amp 0x00000002 0x00000002 rdata SRIO_REGS gt P1_ERR_STAT rdata SRIO_REGS gt P2_ERR_STAT while rdata amp 0x00000002 0x00000002 rdata SRIO_REGS gt P2_ERR_STAT rdata SRIO_REGS gt P3_ERR_STAT while rdata amp 0x00000002 0x00000002 rdata SRIO_REGS gt P3_ERR_STAT
308. nd it is used by a processing element to send a very short message to another processing element through the interconnect fabric The DOORBELL transaction contains the info field to hold information and does not have a data payload This field is software defined and can be used Serial RapidiO SRIO 63 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description for any desired purpose see the Rapid O Interconnect Specification Section 3 1 4 Type 10 Packet Formats Doorbell Class for information about the info field A processing element that receives a doorbell transaction takes the packet and puts it in a doorbell message queue within the processing element This queue may be implemented in hardware or in local memory This behavior is similar to that of typical message passing mailbox hardware The local processor is expected to read the queue to determine the sending processing element and the info field and determine what action to take The DOORBELL functionality is user defined but this packet type is commonly used to initiate DSP core CPU interrupts A DOORBELL packet is not associated with a particular data packet that was previously transferred so the info field of the packet must be configured to reflect the DOORBELL bit to be serviced for the correct TID Transfer Information Descriptor information to be processed Figure 26 Doorbell Operation
309. ne circular buffer for each core The correct circular buffer to read from and increment depends on the bit set in the ICSR register The CPU then clears the status bit For Error Status interrupts the peripheral must indicate to all the CPUs that one of the link ports has reached the error threshold In this case the peripheral sets the status bit indicating degraded or failed limits have been reached and an interrupt is generated to each core through the ICRR mapping The cores can then scan the ICSR registers to determine the port with the error problems Further action can then be taken as determined by the application 100 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Interrupt Handler templ SRIO_REGS gt TX_CPPI_ICSR if templ amp 0x00000001 0x00000001 SRIO_REGS gt Queue0_TXDMA_CP int TX_DESCP0_0 temp2 SRIO_REGS gt RX_CPPI_ICSR if temp2 amp 0x00000001 0x00000001 SRIO_REGS gt Queue0_RXDMA_CP int RX_DESCP0_0 SRIO_REGS gt DOORBELLO_ICCR OxFFFFFFFF SRIO_REGS gt DOORBELLI1_ICCR OxFFFFFFFF SRIO_REGS gt DOORBELL2_ICCR 0OxFFFFFFFF SRIO_REGS gt DOORBELL3_ICCR OxFFFFFFFF SRIO_REGS gt INTDSTO_Rate_CNTL 1 SPRUE13A September 2006 Submit Documentation Feedback Interrupt Conditions Serial RapidlO SRIO 101 SRIO Registers 5 SRIO Registers 5 1 Introduction da TEXAS INSTRUMENTS www ti com Table 40 l
310. nformation is written to the shared TX buffer as described above however the command registers cannot be released BSY 1 until the response packet is routed back to the module and the appropriate completion code is set in the status register One special case exists for outgoing test and swap packets Ftype 5 Transaction 1110b This is the only WRITE class packet that expects a response with payload This response payload is routed to the LSU where it is examined to verify whether the semaphore was accepted and then the appropriate completion code is set The payload is not transferred out of the peripheral via the DMA bus So the general flow is as follows e LSU registers are written using the configuration bus e Flow control is determined e TX FIFO free buffer availability is determined e DMA bus read request for data payload e DMA bus response writes data to specified module buffer in the shared TX buffer space e DMA bus read response is monitored for last byte of payload e Header data in the LSU registers is written to the shared TX buffer space e Payload and header are transferred to the TX FIFO e The LSU registers are released if no RapidlO response is needed e Transfer from the TX FIFO to external device based on priority READ Transactions The flow for generating READ transactions is similar to non posted WRITE with response transactions There are two main differences READ packets contain no data payload and READ respons
311. ng enable field 222 status field 220 count down value for interrupt rate control 154 CPPI 43 boundary diagram 50 rules for data traffic 43 RX operation 44 TX operation 51 CPU in Load Store module data flow diagram 39 interrupts 85 SPRUE13A September 2006 Submit Documentation Feedback SRIO Registers requesting interrupt with INTERRUPT_REQ field 159 CRC errors bad CRC in control symbol at port n rate counting enable field 221 Status field 219 bad CRC in packet at port n rate counting enable field 222 Status field 220 recovery suppression support field 186 CRC in control symbol 24 CRC in packet 23 credit for outbound packets 75 CRF_SUPPORT field of PE_FEAT 186 critical error interrupt to the CPU 85 critical request flow support field 186 CS_EMB field of SPn_CS_TX 240 CTRL_CAPT 217 cut through mode option for portn 236 D DATA_MESS field of DEST_OP 189 DATA_MESS field of SRC_OP 188 data flow diagram for Load Store module 39 data flow overview for SRIO peripheral 21 data message support for destination device 189 data message support for source device 188 data rate select field for SERDES receiver 126 DEBUG field of SPn_CTL_INDEP 236 debug mode selection for portn 237 debug packet field for portn 237 decode registers for interrupt conditions 150 decoding interrupt condition source 97 decrement rate for port error rate counter 228 de emphasis field 128 DE field of SERDES_CFGTXn_CNTL 128 delimiting of control symbols 24 delinea
312. nse is sent Table 23 Examples of DOORBELL_INFO Designations See Figure 26 info Field Segments Value Written To DOORBELL_INFO Associated Mapped To This Doorbell Doorbell Field Of Doorbell Interrupt Doorbell Interrupt Reserved Reg rsv Bit LSUn_REG5 Routing Bits Status Bit 000000000b 00b Ob 0000b 0000h DOORBELLO_ICRR 3 0 DOORBELLO_ICSRI 0 000000000b 00b 0b 1001b 0009h DOORBELLO_ICRR2 7 4 DOORBELLO_ICSRI 9 000000000b 01b 0b 0111b 0027h DOORBELL1_ICRR 31 28 DOORBELL1_ICSR 7 000000000b 01b 0b 1100b 002Ch DOORBELL1_ICRR2 19 16 DOORBELL1_ICSR 12 000000000b 10b 0b 0101b 0045h DOORBELL2_ICRR 23 20 DOORBELL2_ICSR 5 000000000b 10b 0b 1111b 004Fh DOORBELL2_ICRR2 31 28 DOORBELL2_ICSR 15 000000000b 11b 0b 0110b 0066h DOORBELL3_ICRR 27 24 DOORBELL3_ICSR 6 000000000b 11b 0b 1011b 006Bh DOORBELL3_ICRR2 15 12 DOORBELL3_ICSR 11 SPRUE13A September 2006 64 Serial RapidlO SRIO Submit Documentation Feedback i INSTRUMENTS www ti com 2 3 7 2 3 8 SRIO Functional Description SRIO_REGS gt LSU1_REGO CSL_FMK SRIO_LSU1_REGO_RAPIDIO_ADDRESS_MSB 0 SRIO_REGS gt LSU1_REG1 CSL_FMK SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET 0 SRIO_REGS gt LSU1_REG2 CSL_FMK SRIO_LSU1_REG2_DSP_ADDRESS 0 SRIO_REGS gt LSU1_REG3 CSL_FMK SRIO_LSU1_REG3_BYTE_COUNT 0 SRIO_REGS gt LSU1_REG4 CSL_FMK SRIO_LSU1_REG4_OUTPORTID 1 CSL_FMK SRIO_LSU1_REG4_PRIORITY 0 CSL
313. o enable SERDES PLL 2 ENPLL3 0 Not used Should always be programmed as 0 See Section 2 3 2 1 to enable SERDES PLL 1 ENPLL2 0 Not used Should always be programmed as 0 See Section 2 3 2 1 to enable SERDES PLL 0 ENPLL1 0 Not used Should always be programmed as 0 See Section 2 3 2 1 to enable SERDES PLL SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 115 SRIO Registers d TEXAS INSTRUMENTS www ti com 5 5 Peripheral Global Enable Register GBL_EN GBL_EN is implemented with a single enable bit for the entire SRIO peripheral This bit is logically ORed with the reset input to the module and is fanned out to all logical blocks within the peripheral GBL_EN is shown in Figure 66 and described in Table 44 For additional programming information see Section 2 3 10 Figure 66 Peripheral Global Enable Register GBL_EN Address Offset 0030h 31 1 0 Reserved EN HO R W 0 LEGEND R W Read Write R Read only n Value after reset Table 44 Peripheral Global Enable Register GBL_EN Field Descriptions Bit Field Value Description 31 1 Reserved 00000000h These read only bits return Os when read 0 EN Global enable This bit controls reset to all clock domains within the peripheral 0 The peripheral is to be disabled held in reset with clocks disabled The peripheral is to be enabled 116 Serial RapidlO SRIO SPRUE13A Sep
314. ock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs 22 UNSUPPORTED_TRANS_ENABLE Unsupported transaction error reporting enable 0 Disable reporting of an unsupported transaction error 1 Enable reporting of an unsupported transaction error switch or endpoint device Save and lock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs 21 8 Reserved 0 These read only bits return Os when read 7 RX_CPPI_SECURITY_ENABLE RX CPPI security error reporting enable 0 Disable reporting of an attempt at unauthorized access to aRX queue 1 Enable reporting of attempt at unauthorized access to a RX queue Save and Lock capture information in appropriate Logical Transport Layer Capture CSRs 6 RX_IO_SECURITY_ENABLE RX UO secuirty error reporting enable 0 Disable reporting of attempt at unauthorized access to a memory location 1 Enable reporting of attempt at unauthorized access to a memory location Save and Lock capture information in appropriate Logical Transport Layer Capture CSRs 5 0 Reserved 0 These read only bits return Os when read SPRUE13A September 2006 Serial RapidlO SRIO 213 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 77 Logical Transport Layer High Address Capture CSR H_ADDR_CAPT The logical transport layer high address capture CSR H_ADDR_CAPT is shown in Figure 14
315. of RX buffer descriptor queues 50 teardown of TX buffer descriptor queues 59 TERM field of SERDES_CFGRXn_CNTL 125 test and swap See Atomic operations 25 TGT_ID_DIS field of SP_IP_MODE 231 thresholds for loss of signal detection LOS field 126 for port error rate counter 228 for priority 0 1 and 2 transmit credit 113 for reporting errors broken link 229 degraded link 229 maximum retry error at portn 237 TIMEOUT_VALUE field of SP_LT_CTL 197 TIMEOUT_VALUE field of SP_RT_CTL 198 time out condition during direct I O reception 42 during message passing RX operation 47 during message passing TX operation 59 time out values for ports link time out 197 response time out 198 trademarks 14 TRANS_MODE field of SPn_CTL_INDEP 236 transaction priority field 114 transaction type associated with logical transport error 217 transfer mode field for portn 236 transfer type field for flow control destination IDs 181 transmission error count for portn 228 transmission error recovery software option for port n 236 transmission flow control 65 transmit CPPI interrupt condition clear register 137 transmit CPPI interrupt condition routing registers 146 transmit CPPI interrupt condition status register 136 transmit CPPI supported flow mask registers 169 transmit CPPI weighted round robin control registers 174 transmit credit threshold for priorities 0 through 2 113 transmit data rate select field 128 transmit FIFO bypass field for ports 231
316. of signal is detected the clock recovery algorithm is frozen to prevent the phase and frequency of the recovered clock from being modified by low level signal noise Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample the received message so that the data samples are taken midway between data transitions The second order algorithm can be optionally disabled and both can be configured to optimize their dynamics Both algorithms use the same basic technique for determining whether the sampling clock is ideally placed and if not whether it needs to be moved earlier or later When two contiguous data samples are different the phase sample between the two is examined Eight data samples and nine phase samples are taken with each result counted as a vote to move the sample point either earlier or later These eight data bits constitute the voting window The eight votes are then counted and an action to adjust the position of the sampling clock occurs if there is a majority of early or late votes The first order algorithm makes a single phase adjustment per majority vote The second order algorithm acts repeatedly according to the net difference between early and late majority votes thereby adjusting for the rate of change of phase Setting the ALIGN field to 01 e
317. omplete No errors posted non posted Enable for this interrupt is ultimately controlled by the Interrupt Req bit of LSU4_REG4 This allows enabling disabling on a per request basis For optimum LSU performance interrupt pacing should not be used on the LSU interrupts 23 ICS23 0 LSU3 interrupt condition not detected LSU3 interrupt condition detected Packet not sent due to unavailable outbound credit at given priority 22 ICS22 0 LSU3 interrupt condition not detected LSU3 interrupt condition detected Retry Doorbell response received or Atomic test and swap was not allowed semaphore in use 21 ICS21 LSU3 interrupt condition not detected LSU3 interrupt condition detected Transaction was not sent due to DMA data transfer error 20 ICS20 LSU3 interrupt condition not detected Oj O LSU3 interrupt condition detected Transaction timeout occurred 138 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 73 LSU Interrupt Condition Status Register LSU_ICSR Field Descriptions continued Bit Field Value Description 19 ICS19 0 1 LSU3 interrupt condition not detected LSU3 interrupt condition detected Transaction was not sent due to unsupported transaction type or invalid field encoding 18 ICS18 LSU3 interrupt condition not detected LSU3 interrup
318. on The SRAM is accessible by the CPU through the configuration bus Alternatively the buffer descriptors could use L2 memory as well 50 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com CPPI block CPPI control registers Buffer SRIO Functional Description Figure 21 CPPI Boundary Diagram Peripheral boundary Config bus access 3 descriptor dual port SRAM Nx20B Data buffer 2 3 4 2 TX Operation Outgoing messages are handled similarly with buffer descriptor queues that are assigned by the CPUs The queues are configured and initialized upon reset When a CPU wants to send a message to an external RapidlO device it writes the buffer descriptor information via the configuration bus into the SRAM Again there is a single buffer descriptor per RapidlO message Upon completion of writing the buffer descriptor the OWNERSHIP bit is set to give control to the peripheral The CPU then writes the TX DMA State HDP register to initiate the queue transmit For TX operation PortID is specified to direct the outgoing packet to the appropriate port Table 19 and Table 20 describe the TX DMA state registers Figure 22 shows the TX buffer descriptor fields and Table 21 describes them A TX buffer descriptor is a contiguous block of four 32 bit data words aligned on a 32 bit boundary L2 memory Table 19 TX DMA State Head Descriptor Pointer HDP Address Offset 500h 5
319. on Feedback SRIO Functional Description Figure 23 Weighted Round Robin Programming Registers Address Offset 7EOh 7ECh TX_QUEUE_CNTLO Address Offset 7EOh da TEXAS INSTRUMENTS www ti com lt TX_Queue_Map3 gt lt TX_Queue_Map2 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W 0h R W 3h R W 0 R W 2h lt TX_Queue_Map1 gt lt TX_Queue_Map0 gt 15 12 11 8 7 4 3 0 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 1h R W Oh R W Oh TX_QUEUE_CNTL1 Address Offset 7E4h Be TX_Queue_Map7 gt sr TX_Queue_Map6 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W 0 R W 7h R W Oh R W 6h Be TX_Queue_Map5 gt rn TX_Queue_Map4 gt 15 12 11 8 7 4 3 uy Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 5h R W Oh R W 4h TX_QUEUE_CNTL2 Address Offset 7E8h eege TX_Queue_Map11 Gees TX_Queue_Ma
320. on Feedback Serial RapidiO SRIO 165 SRIO Registers da TEXAS INSTRUMENTS www ti com 5 43 Queue n Receive DMA Head Descriptor Pointer Register QUEUEn_RXDMA_HDP There are sixteen of these registers see Table 108 QUEUEn RXDMA_HDP is shown in Figure 105 and described in Table 109 For additional programming information see Section 2 3 4 1 31 Table 108 QUEUEn_RXDMA_HDP Registers Register Address Offset QUEUEO_RXDMA_HDP QUEUE1_RXDMA_HDP QUEUE2_RXDMA_HDP QUEUE3_RXDMA_HDP QUEUE4 RXDMA_HDP QUEUE5 RXDMA_HDP QUEUE6_RXDMA_HDP QUEUE7_RXDMA_HDP QUEUE8_RXDMA_HDP QUEUE9_RXDMA_HDP QUEUE10_RXDMA_HDP QUEUE11_RXDMA_HDP QUEUE12_RXDMA_HDP QUEUE13_RXDMA_HDP QUEUE14_RXDMA_HDP QUEUE15_RXDMA_HDP 0600h 0604h 0608h 060Ch 0610h 0614h 0618h 061Ch 0620h 0624h 0628h 062Ch 0630h 0634h 0638h 063Ch Figure 105 Queue n Receive DMA Head Descriptor Pointer Register QUEUEn_RXDMA_HDP RX_HDP LEGEND R W Read Write n Value after reset R W 00000000h Table 109 Queue n Receive DMA Head Descriptor Pointer Register QUEUEn_RXDMA_HDP Field Descriptions Bit Field Value Description 31 0 RX_HDP 00000000h RX Queue Head Descriptor Pointer This field is the memory address for the first to buffer descriptor in the channel receive queue This field is written by the DSP FFFFFFFCh core to initiate queue receive operations and is zeroed by the port when all free buffers have been u
321. on to this statement is the use of the RapidlO error management extended features This specification monitors and tabulates the errors that occur on a per port basis If the number of errors exceeds a pre determined configurable amount the peripheral should interrupt the CPU software and notify that an error condition exits Alternatively if a system host is used the peripheral may issue a port write operation to notify the system software of a bad link A system reset or Critical Error interrupt can be initialized through the RapidlO link This procedure allows an external device to reset the local device causing all state machine and configuration registers to reset to their original values This is executed with the Reset Device command described in Part VI Section 3 4 5 of the RapidlO Physical Layer 1x 4x LP Serial Specification Four sequential Reset Device control symbols are needed to avoid inadvertent resetting of a device Interrupt Condition Status and Clear Registers Interrupt condition status and clear registers configure which CPU interrupts are to be generated and how based on the peripheral activity All peripheral conditions that result in a CPU interrupt are grouped so that the interrupt can be accessed in the minimum number of register reads possible For each of the three types of interrupts CPU servicing error status and critical error there are two sets of registers e Interrupt Condition Status Register ICSR Sta
322. ontrol Register 2 LSU A REG ee 157 97 LSUn Control Register 3 LSUn_REG3 us2sunannennnennannnunnannannnunnnnnannnannnunnnnnannnannun mann nun nenn 158 98 LSUn Control Register 4 LSUn_REG4 uuusnsunannannnannannnunnannannnunnnnnannnannnunnnnnannnannunnann nun nenn 159 99 LSUn Control Register 5 LSUN REGS urn nad 160 100 LSUn Control Register 6 LSUn_REG 6 uusussunnennnnnnunnnnnnnnnannnunnunnnnnnunnnnnnnnnunnnunnun nun nennen 161 101 LSUn Congestion Control Flow Mask Register LSUn_FLOW_MASKS uuususnannannnnnnannunnnunnnnnan ann 162 SPRUE13A September 2006 List of Figures 7 Submit Documentation Feedback 102 SEELEN MASK Fields sata E E T nn a E kauen 162 103 Queue n Transmit DMA Head Descriptor Pointer Register QUEUEn_TXDMA_HDP ssssssssssssssssssssenee 164 104 Queue n Transmit DMA Completion Pointer Register QUEUEN_TXDMA_CP ccseeeeeeeeeeeeeeeeeeeeeee 165 105 Queue n Receive DMA Head Descriptor Pointer Register QUEUEn_RXDMA_HDP 0cseeeeeeeeeeeee 166 106 Queue n Receive DMA Completion Pointer Register QUEUEn_RXDMA_CP 0ceeeeeeeeeeeeeeeeeeeeeeee 167 107 Transmit Queue Teardown Register TX_QUEUE_TEAR_DOWN Address Offset 0700h 168 108 Transmit CPPI Supported Flow Mask Registers A 170 109 TX Quetie A FLOW_MASK Fields sicer a a nn E Rn weenie 170 110 Receive Queue Teardown Register RX_QUEUE_TEAR_DOWN Address Offset 0740h 20055 172 111 Recei
323. ontrol Register 0 Section 5 33 0424h LSU2_REG1 LSU2 Control Register 1 Section 5 34 0428h LSU2_REG2 LSU2 Control Register 2 Section 5 35 042Ch LSU2_REG3 LSU2 Control Register 3 Section 5 36 0430h LSU2 REG4 LSU2 Control Register 4 Section 5 37 0434h LSU2_REG5 LSU2 Control Register 5 Section 5 38 0438h LSU2_REG6 LSU2 Control Register 6 Section 5 39 043Ch LSU2 FLOW_MASKS1 LSU2 Congestion Control Flow Mask Register Section 5 40 0440h LSU3_ REGO LSU3 Control Register 0 Section 5 33 0444h LSU3_REG1 LSU3 Control Register 1 Section 5 34 0448h LSU3 REG2 LSU3 Control Register 2 Section 5 35 DACH LSU3_REG3 LSU3 Control Register 3 Section 5 36 0450h LSU3 REG4 LSU3 Control Register 4 Section 5 37 0454h LSU3_REGS5 LSU3 Control Register 5 Section 5 38 0458h LSU3_REG6 LSU3 Control Register 6 Section 5 39 045Ch LSU3_FLOW_MASKS2 LSU3 Congestion Control Flow Mask Register Section 5 40 0460h LSU4_REGO LSU4 Control Register 0 Section 5 33 0464h LSU4 REG1 LSU4 Control Register 1 Section 5 34 0468h LSU4 REG2 LSU4 Control Register 2 Section 5 35 046Ch LSU4 REG3 LSU4 Control Register 3 Section 5 36 0470h LSU4 REG4 LSU4 Control Register 4 Section 5 37 0474h LSU4 REGS5 LSU4 Control Register 5 Section 5 38 0478h LSU4 REG6 LSU4 Control Register 6 Section 5 39 047Ch LSU4_FLOW_MASKS3 LSU4 Congestion Control Flow Mask Register Section 5 40 0500h QUEUEO_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 0 Section 5 41 104 Serial RapidlO SRI
324. op count field specified for type 8 maintenance packets 7 0 PACKET_TYPE 00h FFh The 4 MSBs specify the ftype field for all packet types and the 4 LSBs specify the trans field for packet types 2 5 and 8 See Section 2 1 2 4 160 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 39 LSUn Control Register 6 LSUn_REG6 There are four of these registers one for each LSU see Table 99 LSUn_REG6 is shown in Figure 100 and described in Table 100 For additional programming see Section 2 3 3 Table 99 LSUn_REG6 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG6 0418h LSU1 LSU2_REG6 0438h LSU2 LSU3_REG6 0458h LSU3 LSU4_REG6 0478h LSU4 Figure 100 LSUn Control Register 6 LSUn_REG6 31 gt Reserved R 0000h 15 54 1 0 Reserved COMPLETION_CODE BSY R 000h R 0000 HO LEGEND R Read only n Value after reset Table 100 LSUn Control Register 6 LSUn_REG6 Field Descriptions Bit Field Value Description 31 5 Reserved 0000h These read only bits return Os when read 4 1 COMPLETION_CODE Indicates the status of the pending command 0000b Transaction complete no errors posted non posted 0001b Transaction timeout occurred on non posted transaction 0010 b Transaction complete packet not sent due to flow control blockade Xoff 0011b Transaction complete non posted re
325. or Capture CSR 2 SPn_ERR_CAPT_DBG2 ccceeeee cece ee nn nenn nn nun nun nme nn 225 5 87 Port n Error Capture CSR 3 SPn_ERR_CAPT_DBG9 ccceeece cece ee nn nenn nn nun nun nn nen 226 5 88 Port n Error Capture CSR 4 SPn_ERR_CAPT_DBG4 nennen en nennen nun nenn nennen 227 5 89 Port Error Rate CSR n SPn_ERR_RATE erserssunsannnnnannnannnnnunnnannunnnunnnnnannnunnnnnnnn nen 228 5 90 Port Error Rate Threshold CSR n SPn_ERR_THRESH cece sence nun an nun nun nun nen 229 5 91 Port IP Discovery Timer for 4x Mode Register SP_IP_DISCOVERY_TIMER An 230 5 92 Port IP Mode CSR SP IP MODE z u 0 0 10 and a anne 231 5 93 Port IP Prescaler Register IP_PRESCAL nun nun nannun nun nun ennnnn nun nun nen 233 5 94 Port Write In Capture CSRs SP_IP_PW_IN_CAPTI O 3 uruussun nennen sees nnnnennnan nun nn 234 5 95 Port Reset Option CSR n SPn_RST_OPT uzzuu4Hu4 cece nn an nn nun nun ann anne nun nn nennen nennen 235 5 96 Port Control Independent Register n SPn_CTL_INDEP ccccceeee sees ences eee seen eee eeeeaeeee 236 5 97 Port Silence Timer n Register SPn_SILENCE_TIMER uuu2s444HR He RR nenn nen nun nenn nenn nennen 238 5 98 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS 239 5 99 Port Control Symbol Transmit n Register bn CS Ti 240 NAEK EE 241 SPRUE13A September 2006 Contents 5 Submit Documentation Feedback List of Figures 1 RapidlO Architectural Hierarc
326. or management registers allow detection and logging of logical transport layer errors The detectable errors are captured in the logical layer error detect CSR see Figure 44 Table 34 names the functional block s involved for each detectable error condition and includes brief descriptions of the errors captured Figure 44 Logical Transport Layer Error Detect CSR ERR_DET 31 30 29 28 27 26 25 24 eg RSPNS Reseved FFORMAT DECODE Reseved Toea TIMEOUT R W 0 R W 0 R 0 R W 0 R W 0 HO R W 0 R W 0 23 22 21 a re Reserved R W 0 R W 0 R 0 8 Reserved R 0 7 6 5 0 Sesunmv ACCESS Reserved R W 0 R W 0 R 0 LEGEND R Read W Write n Value after reset Table 34 Logical Transport Layer Error Detect CSR ERR_DET Field Descriptions Bit Field Value Description 31 IO_ERR_RSPNS IO error response endpoint device only 0 An LSU did not receive an ERROR response to an IO logical layer request 1 An LSU received an ERROR response to an IO logical layer request To clear this bit write 0 to it 30 MSG_ERR_RSPNS Message error response endpoint device only 0 The TXU did not receive an ERROR response to a message logical layer request 1 The TXU received an ERROR response to a message logical layer request To clear this bit write 0 to it 29 Reserved 0 This read only bit returns 0 when read 28 ERR_MSG_FORMAT Error in message fo
327. or portn 206 width override field for portn 207 WRITE_WITH_RESP field of DEST OP 189 WRITE_WITH_RESP field of SRC_OP 188 WRITE field of DEST_OP 189 WRITE field of SRC_OP 188 write support for destination device 189 write support for source device 188 WRITE transactions during direct I O transmission description 40 non posted 41 posted 41 write with response support for destination device 189 write with response support for source device 188 X XAMSB field of LSUn_REG4 159 XAMSBS field of ADDR_CAPT 215 SPRUE13A September 2006 Submit Documentation Feedback SRIO Registers Xoff 65 Xon 65 SPRUE13A September 2006 Index 255 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except
328. p10 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W Bh R W Oh R W Ah a ee TX_Queue_Map9 gt rn TX_Queue_Map8 gt 15 12 11 817 4 3 2 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W 9h R W Oh R W 8h TX_QUEUE_CNTL3 Address Offset 7ECh lt TX_Queue_Map15 gt lt TX_Queue_Map14 gt 31 28 27 24 23 20 19 16 Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W Oh R W Fh R W Oh R W Eh lt TX_Queue_Map13 gt lt TX_Queue_Map12 gt 15 12 11 lk 4 3 y Number of Msgs Queue Pointer Number of Msgs Queue Pointer R W 0h R W Dh R W 0h R W Ch Table 22 Weighted Round Robin Programming Registers Address Offset 7EOh 7ECh Field Pair Register Bits Field Value Description TX_Queue_Map0 TX_QUEUE_CNTLO 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 7 4 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map1 TX_Queue_Map1 TX_QUEUE_CNTLO 11 8 Queue Pointer Oh to Fh Pointer to a q
329. packet header to specifying target device 7 1 Reserved 00h These read only bits return Os when read 0 INTERRUPT_REQ Indicates whether the CPU requests an interrupt upon completion of the LSU command This is a CPU controlled request bit and is typically used in conjunction with non posted commands to alert the CPU when the requested data status is present 0 Interrupt not requested upon completion of command Interrupt requested upon completion of command SPRUE13A September 2006 Serial RapidlO SRIO 159 Submit Documentation Feedback SRIO Registers 5 38 LSUn Control Register 5 LSUn_REGS5 There are four of these registers one for each LSU see Table 97 LSUn_REGS is shown in Figure 99 and described in Table 98 For additional programming see Section 2 3 3 da TEXAS INSTRUMENTS www ti com Table 97 LSUn_REG5 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG5 0414h LSU1 LSU2_REG5 0434h LSU2 LSU3_REG5 0454h LSU3 LSU4_REG5 0474h LSU4 Figure 99 LSUn Control Register 5 LSUn_REG5 31 gt DRBLL_INFO R W 0000h 15 87 0 HOP_COUNT PACKET_TYPE R W 00h R W 00h LEGEND R W Read Write n Value after reset Table 98 LSUn Control Register 5 LSUn_REG5 Field Descriptions Bit Field Value Description 31 16 DRBLL_INFO 0000h FFFFh RapidlO doorbell info field for type 10 packets see Table 23 15 8 HOP_COUNT 00h FFh RapidlO h
330. ped state INPUT_ERROR_STP is a read only bit The input port is not in the input error stopped state The input port is in the input error stopped state 7 5 Reserved These read only bits return Os when read PORT_WRITE_PND Port write pending This bit is only valid if the device is capable of issuing a maintenance port write transaction Once set the PORT_WRITE_PND bit remains set until software writes a 1 to it The port has not encountered a condition which required it to initiate a Maintenance Port write operation The port has encountered a condition which required it to initiate a Maintenance Port write operation Reserved This read only bit returns 0 when read PORT_ERROR Port unrecoverable error Once set the PORT_ERROR bit remains set until software writes a 1 to it The input or output port has not encountered an error from which hardware was unable to recover The input or output port has encountered an error from which hardware was unable to recover 204 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 147 Port Error and Status CSR n SPn_ERR_STAT Field Descriptions continued Bit Field Value Description 1 PORT_OK Port OK This bit is a read only bit 0 Port not OK condition Port OK condition The input and output ports are initialized and the port is exchanging
331. pping Register L27 Section 5 50 08DCh RXU_MAP_H27 MailBox to Queue Mapping Register H27 Section 5 50 08E0h RXU_MAP_L28 MailBox to Queue Mapping Register L28 Section 5 50 08E4h RXU_MAP_H28 MailBox to Queue Mapping Register H28 Section 5 50 08E8h RXU_MAP_L29 MailBox to Queue Mapping Register L29 Section 5 50 O8ECh RXU_MAP_H29 MailBox to Queue Mapping Register H29 Section 5 50 SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 107 da TEXAS INSTRUMENTS www ti com SRIO Registers Table 40 Serial RapidlO SRIO Registers continued Offset Acronym Register Description Section O8FOh RXU_MAP_L30 MailBox to Queue Mapping Register L30 Section 5 50 08F4h RXU_MAP_H30 MailBox to Queue Mapping Register H30 Section 5 50 08F8h RXU_MAP_L31 MailBox to Queue Mapping Register L31 Section 5 50 O8FCh RXU_MAP_H31 MailBox to Queue Mapping Register H31 Section 5 50 0900h FLOW_CNTLO Flow Control Table Entry Register 0 Section 5 51 0904h FLOW_CNTL1 Flow Control Table Entry Register 1 Section 5 51 0908h FLOW_CNTL2 Flow Control Table Entry Register 2 Section 5 51 090Ch FLOW_CNTL3 Flow Control Table Entry Register 3 Section 5 51 0910h FLOW_CNTL4 Flow Control Table Entry Register 4 Section 5 51 0914h FLOW_CNTL5 Flow Control Table Entry Register 5 Section 5 51 09
332. pt request detected Possible interrupt sources e Doorbell 0 bit 10 bit 10 of DOORBELLO_ICSR e Doorbell 1 bit 10 bit 10 of DOORBELL1_ICSR e Doorbell 2 bit 10 bit 10 of DOORBELL2_ICSR e Doorbell 3 bit 10 bit 10 of DOORBELL3_ICSR ISD9 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 9 bit 9 of DOORBELLO_ICSR e Doorbell 1 bit 9 bit 9 of DOORBELL1_ICSR e Doorbell 2 bit 9 bit 9 of DOORBELL2_ICSR e Doorbell 3 bit 9 bit 9 of DOORBELL3_ICSR ISD8 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 8 bit 8 of DOORBELLO_ICSR e Doorbell 1 bit 8 bit 8 of DOORBELL1_ICSR e Doorbell 2 bit 8 bit 8 of DOORBELL2_ICSR e Doorbell 3 bit 8 bit 8 of DOORBELL3_ICSR 152 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Table 84 Interrupt Status Decode Register INTDSTn_DECODE Field Descriptions continued SRIO Registers Bit Field Value Description 7 ISD7 0 1 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 7 bit 7 of DOORBELLO_ICSR e Doorbell 1 bit 7 bit 7 of DOORBELL1_ICSR e Doorbell 2 bit 7 bit 7 of DOORBELL2_ICSR e Doorbell 3 bit 7 bit 7 of DOORBELL3_ICSR ISD6 No interr
333. ptember 2006 Serial RapidlO SRIO 191 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com SRIO Registers 5 61 Local Configuration Space Base Address 1 CSR LCL_CFG_BAR The local configuration space base address 1 CSR LCL_CFG_BAR is shown in Figure 124 and described in Table 132 Figure 124 Local Configuration Space Base cen 1 CSR LCL_CFG_BAR Address Offset 105Ch 31 0 LCSBA R 00000000h LEGEND R Read only n Value after reset Table 132 Local Configuration Space Base Address 1 CSR LCL_CFG_BAR Field Descriptions Bit Field Value Description 31 0 LCSBA 00000000h Bit 31 is reserved for 34 bit addresses bit 35 of a 50 bit address and bit 35 of a to 66 bit address FFFFFFFFh Bits 30 to 0 are bits 34 to 3 of a 34 bit address bits 35 to 3 of a 50 bit address and bits 35 to 3 of a 66 bit address 192 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 62 Base Device ID CSR BASE_ID The base device ID CSR BASE_ID is shown in Figure 125 and described in Table 133 Figure 125 Base Device ID CSR BASE_ID Address Offset 1060h 31 24 23 16 Reserved BASE_DEVICEID R 00h R W FFh 15 0 LARGE_BASE_DEVICEID R W FFFFh LEGEND R W Read Write R Read only n Value after reset Table 133 Base Device ID CSR BASE_ID Field Descriptions Bit Field Value Descrip
334. ption 177 introduction 45 S security error reporting enable bit for MAU 213 security error reporting enable bit for RXU 213 security error status bit for MAU 211 security error status bit for RXU 211 SEGMENT_MAPPING field of RXU_MAP_Hn 178 segmentation of outbound direct I O requests 42 SELF_RST field of SP_IP_MODE 231 self reset interrupt enable field for ports 231 SEND_DBG_PKT field of SPn_CTL_INDEP 236 send debug packet field for portn 237 SERDES CFGn_CNTL 130 SERDES_CFGRXn_CNTL 125 SERDES_CFGTXn_CNTL 128 SERDES macro configuration register 130 252 Index SERDES macros configuration example 35 description 28 enable bits 115 in SRIO component block diagram 26 in SRIO peripheral block diagram 21 PLL enabling 28 receiver enabling 30 transmitter enabling 33 SERDES receive channel configuration registers 125 SERDES transmit channel configuration registers 128 serialization deserialization SERDES 21 serial port IP prescaler register 233 Serial RapidlO peripheral See SRIO peripheral 19 shared buffers in direct I O RX operation 42 in direct O TX READ transaction 41 in direct O TX WRITE transaction 40 in Load Store module data flow diagram 39 in message passing 43 in SRIO component block diagram 26 SILENCE_TIMER field of SPn_SILENCE_TIMER 238 silent state period for portn 238 single multi segment selection field for message reception 180 single port with 1x or 4x operation 76 small common transport system base device ID 1
335. r 2006 Submit Documentation Feedback S INSTRUMENTS www ti com SRIO Registers 5 74 Error Reporting Block Header Register ERR_RPT_BH The Error Reporting Block Header Register ERR_RPT_BH is shown in Figure 137 and described in Table 150 Figure 137 Error Reporting Block Header Register ERR_RPT_BH Address Offset 2000h 31 16 15 0 EF_PTR EF_ID R 0000h R 0007h LEGEND R Read only n Value after reset Table 150 Error Reporting Block Header Register ERR_RPT_BH Field Descriptions Bit Field Value Description 31 16 EF_PTR 0000h Hard wired pointer to the next block in the data structure NONE EXISTS 15 0 EF_ID 0007h Hard wired Extended Features ID SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 209 da TEXAS INSTRUMENTS www ti com SRIO Registers 5 75 Logical Transport Layer Error Detect CSR ERR_DET This register allows for the detection of logical transport layer errors The detectable errors are captured in the fields shown in Figure 138 and described in Table 151 For additional programming information see Section 3 Figure 138 Logical Transport Layer Error Detect CSR ERR_DET Address Offset 2008h 31 30 29 28 27 26 25 24 eg RSPNS Reseved FFORMAT Decope Reseved PMEOUT TIMEOUT R W 0 R W 0 R 0 R W 0 R W 0 HO R W 0
336. r 2006 Submit Documentation Feedback 155 Port IP Mode CSR SP_IP_MODE Address Offset 12004 231 156 Port IP Prescaler Register IP_PRESCAL Address Offset 12008h cceeeeeee nn nennen nn nennen 233 157 iPort Write In Capture CSRS ass ea a aa aa ae Eee 234 158 Port Reset Option CSR n SPrRL_RSTLOPT ums ae na nenn ann 235 159 Port Control Independent Register n GP CT IND DI nenn na nun nun nun ann nun nun nun nun nn 236 160 Port Silence Timer n Register SPn_SILENCE_TIMER uuusussunnannnnnnnnnannnunnunnnnnnannunnnunnnnnnn nun 238 161 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS eeeeeeeeee eee eee eeee 239 162 Port Control Symbol Transmit n Register SPn_CS_TX uuzaunsunsnnnannnnnnnnnannnunnun nun nunnunnnunnnnnennnnn 240 SPRUE13A September 2006 List of Figures 9 Submit Documentation Feedback 10 List of Tables 1 TI Devic s Supported By The geen ee AHA EENS ENNEN NSA SE E 20 2 Registers Checked for Multicast Devicelf nenn 21 3 Packet TY PGS usa a a a a a aaa a a Da SEN 25 4 PinDescription seet egie in a a a ar 26 5 SERDES Macro Configuration Register 0 SERDES_CFGO_CNTL Field Descriptions 4 u4 44er 29 6 Line Rate versus PLL Output Clock Frequency uuuusnensnannunnannnannunnnnnnannannnunnannannnannnunnnnnannnan nun 30 7 Effect ofthe RATE Bits ua na ee ee nee RER TEE ae 30 8 Frequency Range versus MPY Value NEEN SRENEN ENEE NN ENEE NNEERERE NEEN EE
337. r Register LSU_ICCR Field Descipttons sssssssssrssssnnnnnnnnnnnnnnnnnnnn 141 75 Error Reset and Special Event Interrupt Condition Status Register ERR_RST_EVNT_ICSR Field Descriptions sin de ea rn 142 76 Error Reset and Special Event Interrupt Condition Clear Register ERR_RST_EVNT_ICCR Field Descriptions E 143 77 DOORBELLR IERR EC 144 78 DOORBELLn Interrupt Condition Routing Register Field Descriptions nun nennen 144 79 RX CPPI Interrupt Condition Routing Register Field Descriptions cceeeeeee eee eeeeee na nn ann nn nun nennen 145 80 TX CPPI Interrupt Condition Routing Register Field Descriptions eceeeeeeeeeeeee eee eeeeeeeeeeeeeeneees 146 81 LSU Interrupt Condition Routing Register Field Descriptions eee eee eee sees nun nun nun nun nnn 148 82 Error Reset and Special Event Interrupt Condition Routing Register Field Descriptions seeeeeeee 149 83 INTDSTn_DECODE Registers and the Associated Interrupt Destinations seeeeeeeeeeeeeeeeeeeeeeeees 150 84 Interrupt Status Decode Register INTDSTn_DECODE Field Description 150 85 INTDSTn_RATE_CNTL Registers and the Associated Interrupt Destinations seeeeeeeeeeeeeeeeeee 154 86 INTDSTn Interrupt Rate Control Register INTDSTn_RATE_CNTL Field Descriptions 0 eee0es 154 87 LSUn_REGO Registers and the Associated LSUS ceceeeeeee ences eee reece enna ee eeeee nun nun nun nun nennen 155 88 LSUn Control Register 0 LSUn
338. r of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map5 TX_Queue_Map5 TX_QUEUE_CNTL1 11 8 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map6 TX_Queue_Map6 TX_QUEUE_CNTL1 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map7 TX_Queue_Map7 TX_QUEUE_CNTL1 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map8 TX_Queue_Map8 TX_QUEUE_CNTL2 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL2 7 4 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map9 TX_Queue_Map9 TX_QUEUE_CNT
339. ransmitted and the TX queue is empty End of queue is determined by the port when the next_descriptor_pointer is zero on an eop buffer This bit is valid only on eop 0 The TX queue has more messages to transfer 1 The Descriptor buffer is the last buffer in the last message in the queue teardown_complete Teardown Complete Set by the port to indicate that the DSP core commanded teardown process is complete and the channel buffers may be reclaimed by the DSP core 0 The port has not completed the teardown process 1 The port has completed the commanded teardown process 52 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 21 TX Buffer Descriptor Field Definitions continued Field Description retry_count Message Retry Count Set by the DSP core to indicate the total number of retries allowed for this message including all segments Decremented by the port each time a message is retried 000000b Infinite Retries 000001b Retry Message 1 time 000002b Retry Message 2 times 111111b Retry Message 63 times cc Completion Code Set by the port 000 Good Completion Message received a done response 001 Transaction error Message received an error response 010 Excessive Retries Message received more than retry_count retry responses 011 Transaction timeout Transaction timer elapsed wi
340. rd 4 bytes and are aligned to that boundary and byte lane as with a regular read transaction Double word 8 byte 3 byte 5 byte 6 byte and 7 byte Atomic transactions are not allowed Atomic test and swap operations Ftype 5 to external devices are limited to a payload of one double word 8 bytes These operations are like NWRITE with response 55h transactions The addressing scheme defined for the write transactions also controls the size of the Atomic operation in memory so that the bytes are contiguous and of size byte half word 2 bytes or word 4 bytes and are aligned to that boundary and byte lane as with a regular write transaction Double word 8 byte 3 byte 5 byte 6 byte and 7 byte Atomic test and swap transactions are not allowed Upon receipt of the request the targeted device swaps the contents of the specified memory location and the payload if the contents of the memory location are all Os The contents of the memory location are returned and the appropriate completion code is set in the LSU status register LSUn_REG6 The completion codes are listed in Table 15 Congestion Control The RapidlO Logical Layer Flow Control Extensions Specification This section describes the requirements and implementation of congestion control within the peripheral The peripheral is notified of switch fabric congestion through type 7 RapidlO packets The packets are referred to as Congestion Control Packets CCPs The purpose of th
341. register to FFFFFFFCh and issuing an interrupt for the given queue The teardown command register bit is automatically cleared by the peripheral If the queue is not in message and active next descriptor available then the next descriptor will be fetched and updated to report teardown teardown bit set ownership bit cleared CC 100b All other fields of the buffer descriptor are invalid The peripheral completes the teardown procedure by clearing the HDP register setting the CP register to FFFFFFFCh and issuing an interrupt for the given queue The teardown command register bit is automatically cleared by the peripheral If the queue is not in message but inactive next descriptor unavailable then no additional buffer descriptor will be written The HDP register and the CP register remain unchanged An interrupt is not issued The teardown command register bit is automatically cleared by the peripheral e f teardown is issued by software during the time when the RXU state machine is busy the teardown procedure will be postponed until the state machine is idle After the teardown process is complete and the interrupt is serviced by the CPU the software must re initialize the RX queue to restart normal operation The buffer descriptor queues are maintained in local SRAM just outside of the peripheral as shown in Figure 21 This allows the quickest access time while maintaining a level of configurability for device implementati
342. reset with its clock off Logical block nis enabled with its clock running SPRUE13A September 2006 Serial RapidlO SRIO 73 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com SRIO Functional Description 2 3 10 3 Software Shutdown Details Power consumption is minimized for all logical blocks that are in shutdown In addition to simply asserting the appropriate reset signal to each logical block within the peripheral clocks are gated off to the corresponding logical block as well Clocks are allowed to run for 32 clock cycles which is necessary to fully reset each logical block When the appropriate logical block is fully reset the clock input to that subblock is gated off When software asserts GBL_EN BLKn_EN to release the logical block from reset the clocks are un gated and the GBL_EN_STAT BLKn_EN_STAT bit s indicate a value of 1b Note The BLK_EN bits allow you to shut down and gate clocks to unused portions of the logic while other parts of the peripheral continue to operate When shutting down an individual block if TXU and RXU queues are not torn down correctly the DMA bus could hang For example setting BLK3_EN 0 disabling the TXU before a teardown of the queue could cause any outstanding DMA request returned to the peripheral for the TXU to hang the bus When using the GBL_EN to shutdown reset the entire peripheral it is important to first stop all master initiated commands on th
343. rity 1 packets across the UDI This is valid for all ports in 1x mode only Required buffer count for transmit credit threshold 1 value TX_PRI1_WM e 000 8 7 6 5 4 3 2 1 effectively lets all of this priority pass e 001 8 7 6 5 4 3 2 e 010 8 7 6 5 4 3 e 011 8 7 6 5 4 e 100 8 7 6 5 e 101 8 7 6 e 110 8 7 e 111 8 14 12 TX_PRIO_WM 000b 111b Transmit credit threshold Sets the required number of logical layer TX buffers needed to send priority 0 packets across the UDI This is valid for all ports in 1x mode only Required buffer count for transmit credit threshold 0 value TX_PRIO_WM e 000 8 7 6 5 4 3 2 1 effectively lets all of this priority pass e 001 8 7 6 5 4 3 2 e 010 8 7 6 5 4 3 e 011 8 7 6 5 4 e 100 8 7 6 5 e 101 8 7 6 e 110 8 7 e 111 8 11 9 CBA_TRANS_PRI 000b 111b DSP system transaction priority 000b Highest Priority 111b Lowest Priority 1X_MODE This register bit determines the UDI buffering setup priority versus port For additional programming information see Section 2 3 13 2 UDI buffers are priority based UDI buffers are port based This mode must be selected when using more than one 1x port PRESCALER_SELECT 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Internal frequency prescaler used to drive the request to response ti
344. rmat endpoint device only 0 The RXU did not receive a message data payload with an invalid size or segment 1 The RXU received a message data payload with an invalid size or segment To clear this bit write O to it 27 ILL_TRANS_DECODE Illegal transaction decode switch or endpoint device For an LSU or the TXU 0 The LSU TXU did not receive illegal fields in the response packet for an IO message transaction 1 The LSU TXU received illegal fields in the response packet for an IO message transaction To clear this bit write 0 to it For the MAU or the RXU 0 The MAU RXU did not receive illegal fields in the request packet for an IO message transaction 1 The MAU RXU received illegal fields in the request packet for an IO message transaction To clear this bit write 0 to it 26 Reserved 0 This read only bit returns 0 when read SPRUE13A September 2006 Serial RapidlO SRIO 83 Submit Documentation Feedback Logical Transport Error Handling and Logging da TEXAS INSTRUMENTS www ti com Table 34 Logical Transport Layer Error Detect CSR ERR_DET Field Descriptions continued Bit Field Value Description 25 MSG_REQ_TIMEOUT Message request timeout endpoint device only A timeout has not been detected by RXU A timeout has been detected by the RXU A required message request has not been received by the RXU within the specified time out interval To clear this bit write O to it 24 PKT_RSPNS_TIMEOUT Pa
345. rror Reset and Special Event Interrupt Condition Routing Registers The ICRRs shown in Figure 58 route port interrupt requests to interrupt destinations For example if ICS8 1 in ERR_RST_EVNT_ICSR and ICR8 0001b in ERR_RST_EVNT_ICRR2 port 0 has generated an error interrupt request and that request is routed to interrupt destination 1 96 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback ii INSTRUMENTS www ti com Interrupt Conditions Figure 58 Error Reset and Special Event Interrupt Condition Routing Registers Error Reset and Special Event ICRR ERR_RST_EVNT_ICRR Address Offset 02F0h 31 Reserved HO 12 11 8 7 4 3 0 Reserved ICR2 ICR1 ICRO R 0 R W 0000 R W 0000 R W 0000 Error Reset amp Special Event ICRR 2 ERR_RST_EVNT_ICRR2 Address Offset 02F4h 31 1e Reserved R 0 15 12 11 87 4 3 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 Error Reset and Special Event ICRR 3 ERR_RST_EVNT_ICRR3 Address Offset 02F8h 31 Reserved HO 43 0 Reserved ICR16 R 0 R W 0000 LEGEND R W Read Write R Read only n Value after reset 4 5 Interrupt Status Decode Registers There are 8 blocks of the ICSRs to indicate the source of a pending interrupt 0x0200 0x0210 0x0220 0x0230 0x0240 0x0250 0x0260 0x0270 Doorbell0O interrupts Doorbelll interrupts Doorbell2 interrupts
346. rs and the Associated Portes 202 145 Port Local AckID Status CSR n SPn_ACKID_STAT Field Descrtotons 202 146 SPn_ERR_STAT Registers and the Associated Ports cseeeeeeeeeeeeee cece eee nun nn nun nnnnnn nun nennen nen 203 147 Port Error and Status CSR n SPn_ERR_STAT Field Descriptions ceeeeeeeeee eee nenn eee nun nun ann nn 203 148 SPn_ CTL Registers and the Associated Ports cceeeeeee eee eee eee eee eect renee enna nun nun nun nun nun nun une eee 206 149 Port Control CSR n SPn_CTL Field Descriptions cc ceee eee ee eee eee eee eee eee eee eee nannunnnunnnnnann nn 206 List of Tables SPRUE13A September 2006 Submit Documentation Feedback 150 Error Reporting Block Header Register ERR_RPT_BH Field Descriptions e 209 151 Logical Transport Layer Error Detect CSR ERR_DET Field Descriptions 20eeeeeeeeeeeeeeeeeeeees 210 152 Logical Transport Layer Error Enable CSR ERR EN Field Descriptions seeeee sees nn nn nn nn 212 153 Logical Transport Layer High Address Capture CSR H_ADDR_CAPT Field Descriptions 214 154 Logical Transport Layer Address Capture CSR ADDR_CAPT Field Description 215 155 Logical Transport Layer Device ID Capture CSR ID_CAPT Field Descriptions eeeeeeeeeeeeeees 216 156 Logical Transport Layer Control Capture CSR CTRL_CAPT Field Descriptions ssssssscecccssnrnnnn 217 157 Port Write Target Device ID CSR PW_
347. rt 0 Packet Control Symbol Error Capture CSR 4 Section 5 88 2068h SPO_ERR_RATE Port 0 Error Rate CSR 0 Section 5 89 206Ch SPO_ERR_THRESH Port 0 Error Rate Threshold CSR Section 5 90 2080h SP1_ERR_DET Port 1 Error Detect CSR Section 5 82 2084h SP1_RATE_EN Port 1 Error Enable CSR Section 5 83 2088h SP1_ERR_ATTR_CAPT_DBGO Port 1 Attributes Error Capture CSR 0 Section 5 84 208Ch SP1_ERR_CAPT_DBG1 Port 1 Packet Control Symbol Error Capture CSR 1 Section 5 85 2090h SP1_ERR_CAPT_DBG2 Port 1 Packet Control Symbol Error Capture CSR 2 Section 5 86 2094h SP1_ERR_CAPT_DBG3 Port 1 Packet Control Symbol Error Capture CSR 3 Section 5 87 2098h SP1_ERR_CAPT_DBG4 Port 1 Packet Control Symbol Error Capture CSR 4 Section 5 88 20A8h SP1_ERR_RATE Port 1 Error Rate CSR Section 5 89 20ACh SP1_ERR_THRESH Port 1 Error Rate Threshold CSR Section 5 90 20C0Oh SP2_ERR_DET Port 2 Error Detect CSR Section 5 82 20C4h_ SP2_RATE_EN Port 2 Error Enable CSR Section 5 83 20C8h SP2_ERR_ATTR_CAPT_DBGO Port 2 Attributes Error Capture CSR 0 Section 5 84 20CCh SP2_ERR_CAPT_DBG1 Port 2 Packet Control Symbol Error Capture CSR 1 Section 5 85 20D0h_ SP2_ERR_CAPT_DBG2 Port 2 Packet Control Symbol Error Capture CSR 2 Section 5 86 20D4h SP2_ERR_CAPT_DBG3 Port 2 Packet Control Symbol Error Capture CSR 3 Section 5 87 20D8h SP2_ERR_CAPT_DBG4 Port 2 Packet Control Symbol Error Capture CSR 4 Section 5 88 20E8h SP2_ERR_RATE Port 2 Error Rate CSR Section 5 89 20ECh SP2_ERR_THR
348. rved 0 These read only bits return Os when read 17 16 TT Transfer type for flow n 00b 8 bit destination IDs 01b 16 bit destination IDs 1xb Reserved 15 0 FLOW_CNTL_ID 0000h FFFFh Destination ID for flow n When 8 bit destination IDs are used TT 00b the 8 MSBs of this field are don t care bits Each transmit source including any LSU and any TX CPPI queue indicates which of the 16 flows it uses with a 16 bit flow mask Figure 28 illustrates the registers that contain the flow masks and Figure 29 illustrates the general form of an individual flow mask As can be seen from Table 25 bits 0 through 15 of the flow mask correspond to flows 0 through 15 respectively The CPU must configure the flow masks upon reset The default setting is all 1s indicating that the transmit source supports all flows If the register is set to all Os the transmit source does not support any flow and consequently that source is never flow controlled If any of the table entry counters that a transmit Source supports have a corresponding non zero Xoff count the transmit source is flow controlled A simple 16 bit bus indicates the Xoff state of all 16 flows and is compared to the transmit source mask register Each source interprets this result and performs flow control accordingly For example an LSU module that is flow controlled can reload its registers and attempt to send a packet to another flow while a TX CPPI queue that is flow controlled
349. rvices with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Low Power Wireless www ti com lpw Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2006 Texas Instruments Incorporated
350. s 117 120 handling of unavailable outbound credit 76 in SRIO component block diagram 26 MAX_RETRY_EN field of SPn_CTL_INDEP 236 Index 247 SRIO Registers MAX_RETRY_ERR field of SPn_CTL_INDEP 236 MAX_RETRY_THR field of SPn_CTL_INDEP 236 maximum packet size exceeded at port n rate counting enable field 222 status field 220 maximum retry error at port n reporting enable field 237 reporting threshold field 237 status field 237 memory access unit See MAU 26 MEMORY field of PE_FEAT 186 memory mapped registers enable bit 119 memory mapped registers enable status bits 118 120 memory present field 186 message_length field of RX buffer descriptor 47 message_length field of TX buffer descriptor 52 message error response at TXU reporting enable field 212 status field 210 message format error at RXU reporting enable field 212 status field 210 message packet Ftype and Ttype 25 message passing 43 CPPI reset and power down state 59 ERROR response 43 initialization example 61 interrupting the CPU after reception 86 order of received packets 49 order of response packets during TX operation 58 order of transmitted packets 54 responses to CPPI transmissions 58 RETRY response 43 RX buffer descriptor fields 47 RX buffer descriptor link list figure 61 RX descriptor pointers 46 RX operation 44 software requirements 60 teardown of RX buffer descriptor queues 50 time out condition during RX operation 47 time out condition
351. sage passing 43 error status interrupt to the CPU 85 error type field for port n error capture 223 EXTENDED_ADDRESSING_CONTROL field of PE LL CTL 190 EXTENDED_ADDRESSING_SUPPORT field of PE_FEAT 186 EXTENDED_FEATURES field of PE_FEAT 186 extended address 2 MSBs field for LSUn 159 extended address LSB field for LSUn 156 extended address MSB field for LSUn 155 extended features ID field 196 EXTENDEDFEATURESPTR field of ASBLY_INFO 185 extended feature support field 186 external device requirements 20 F features not supported in SRIO peripheral 20 features supported in SRIO peripheral 19 FIFOs in data path description for LSUs 39 in direct I O RX operation 42 in direct UO TX operation 40 in Load Store module data flow diagram 39 in message passing 43 in SRIO peripheral block diagram 21 TX FIFO bypass field for ports 231 finding interrupt source with help from interrupt status decode registers 97 fixed transmit clock phase enable bit 128 FLOW_CNTL_ID field of FLOW_CNTLn 181 FLOW_CNTLn 181 FLOW_CONTROL_SUPPORT field of PE_FEAT 186 FLOW_MASK field of LSUn_FLOW_MASKS 162 flow control 65 flow control enable bit for data flow in logical layer of peripheral 112 for port n transmit flow control 236 flow control table entry register 181 flow masks for CPPI message transmission 169 for LSU transmission 162 introduction 67 force insertion of control symbol in outbound packet 240 force reinitialization process for portn 23
352. scriptor queue SRAMs and mailbox mapper logic should be powered down Clocks should be gated to these blocks while in the power down state Section 2 3 10 describes this in detail SPRUE13A September 2006 Serial RapidlO SRIO 59 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description 2 3 4 4 Message Passing Software Requirements 60 Software performs the following functions for messaging RX Operation e Assigns Mailbox to queue mapping and allowable SourcelDs mailbox Queue Mapping e Sets up associated buffer descriptor memory CPPI RAM or L2 RAM e Link lists the buffer descriptors next_descriptor_pointer e Assigns single segment 256 byte payload and multi segment 4K byte payload buffers to queues buffer_length e Assigns buffer descriptor to data buffer buffer_pointer e Gives control of the buffer to the peripheral ownership 1 Configures and initiates RX queues e Assigns Head Descriptor Pointer HDP for up to 16 queues RX DMA State HDP e Port begins to consume buffers beginning with HDP descriptor and sets ownership 0 for each buffer descriptor used Writes Completion Pointer CP RX DMA State CP and moves to next buffer e Port hardware generates pending interrupt when CP is written Physical interrupt generated when Interrupt Pacing Count down timer 0 Processes interrupt e Determines ICSR bit and process corresponding queue until ownership 1 or eoq 1 e Sets pro
353. se of a packet from the logical layer buffer to the port s physical buffer thus indicating the freeing up of space in the port s logical buffer A priority arbiter empties the logical layer buffer with the highest priority available first For example it empties all available priority 3 buffers before priority 2 1 or 0 The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device in which case a re ordering algorithm is used The algorithm searches backward through the buffer group for the first packet with the highest priority If there are no higher priority packets in the queue the current packet is sent again As an example of the re ordering algorithm suppose a physical layer buffer group contains packets with the following priorities 00123310 where the leftmost 0 represents the packet that was the first in or head of the queue If this packet is retried the next packet to be sent is the earliest packet with priority 3 the lefthand 3 If that packet is sent successfully the physical layer attempts to send the original retried packet again otherwise the physical layer repeats the re ordering algorithm 2 3 12 3 Unavailable Outbound Credit 76 At any time if one of the credit counters reaches 0 no more buffer credit is available The following describes how the protocol units deal with this case MAU or RXU In the case of the MAU or the RXU all outbound packets are response packe
354. sed An error condition results if the DSP core writes this field when the current field value is nonzero The address must be 32 bit word aligned the 2 LSBs must be 0s 166 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 44 Queue n Receive DMA Completion Pointer Register QUEUEn_RXDMA_CP There are sixteen of these registers see Table 110 QUEUEn_RXDMA _CP is shown in Figure 106 and described in Table 111 For additional programming information see Section 2 3 4 1 31 Table 110 QUEUEn_RXDMA_CP Registers Register Address Offset QUEUEO_RXDMA_CP QUEUE1_RXDMA_CP QUEUE2_RXDMA_CP QUEUE3_RXDMA_CP QUEUE4_RXDMA_CP QUEUE5_RXDMA_CP QUEUE6_RXDMA_CP QUEUE7_RXDMA_CP QUEUE8_RXDMA_CP QUEUE9_RXDMA_CP QUEUE10_RXDMA_CP QUEUE11_RXDMA_CP QUEUE12_RXDMA_CP QUEUE13_RXDMA_CP QUEUE14_RXDMA_CP QUEUE15_RXDMA_CP 0680h 0684h 0688h 068Ch 0690h 0694h 0698h 069Ch O6A0h 06AAh 06A8h 06ACh O6BOh 06B4h O6B8h 06BCh Figure 106 Queue n Receive DMA Completion Pointer Register QUEUEn_RXDMA_CP RX_CP LEGEND R W Read Write n Value after reset R W 00000000h Table 111 Queue n Receive DMA Completion Pointer Register QUEUEn_RXDMA_CP Field Descriptions Bit Field Value Description 31 0 RX_CP 00000000h This field is the memory address for the receive queue completion pointer This to register
355. ses the output amplitude to be smaller for bits which are not preceded by a transition than for bits which are See Table 61 11 9 SWING 000b 111b Output swing Selects one of 8 output amplitude settings between 125 and 1250mV app See Table 62 8 CM Common mode Adjusts the common mode to suit the termination at the attached receiver 0 Normal common mode Common mode not adjusted 1 Raised common mode Common mode raised by 5 of amp 54 7 INVPAIR Invert polarity Inverts the polarity of RIOTXn and RIOTXn 0 Normal polarity RIOTXn is considered to be positive data and RIOTXn negative 1 Inverted polarity RIOTXn is considered to be negative data and RIOTXn positive 6 5 RATE Operating rate Selects full half or quarter rate operation 00b Full rate Two data samples taken per PLL output clock cycle 01b Half rate One data sample taken per PLL output clock cycle 10b Quarter rate One data sample taken every two PLL output clock cycles 11b Reserved 4 2 BUSWIDTH 000b Bus width Always write 000b to this field to indicate a 10 bit wide parallel bus to the clock All other values are reserved See Section 2 3 2 1 for an explanation of the bus 1 Reserved 0 Always write 0 to this reserved bit 128 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 60 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL Field Descriptions cont
356. sing Element Features CAR PE_FEAT Address Offset 1010h 31 30 29 28 27 24 BRIDGE MEMORY PROCESSOR SWITCH Reserved R 0 R 0 R 1 R 0 R Oh 23 16 Reserved R 00h 15 a Reserved R 00h 7 6 5 4 3 2 0 SCH RE CRF LARGE EATENDEDZ EXTENDED_ADDRESSING_SUPPORT Ee SUPPRESS SUPPORT SUPPORT FEATURES z R 0 R 0 R 0 R 0 R 1 R 001 LEGEND R Read only n Value after reset Table 127 Processing Element Features CAR PE_FEAT Field Descriptions Bit Field Value Description 31 BRIDGE PE can bridge to another interface Examples are PCI proprietary processor buses DRAM etc 30 MEMORY PE has physically addressable local address space and can be accessed as an endpoint through non maintenance i e non coherent read and write operations This local address space may be limited to local configuration Registers or could be on chip SRAM etc 29 PROCESSOR PE physically contains a local processor or similar device that executes code A device that bridges to an interface that connects to a processor does not count see bit 31 28 SWITCH PE can bridge to another external RapidlO interface An internal port to a local endpoint does not count as a switch port For example a device with two RapidlO ports and a local endpoint is a two port switch not a three port switch regardless of the internal architecture 27 8 Reserved
357. sponse packet type 8 and 13 contained ERROR status or response payload length was in error 0100b Transaction complete packet not sent due to unsupported transaction type or invalid programming encoding for one or more LSU register fields 0101b DMA data transfer error 0110b Retry DOORBELL response received or Atomic test and swap was not allowed semaphore in use 0111b Transaction complete packet not sent due to unavailable outbound credit at given priority 1xxxb Reserved 0 BSY Indicates status of the writeable LSU registers 0 LSU registers available writable for next set of transfer descriptors LSU registers busy with current transfer SPRUE13A September 2006 Serial RapidlO SRIO 161 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 40 LSUn Congestion Control Flow Mask Register LSUn_FLOW_MASKS There are four of these registers one for each LSU see Table 101 The fields of an LSUn_FLOW_MASKS register are summarized by Figure 101 and described in Table 102 The 16 bits within each FLOW_MASK field are summarized by Figure 102 and Table 103 For additional programming see Section 2 3 8 Table 101 LSUn_FLOW_MASKS Registers and the Associated LSUs Register Address Offset LSU LSU1_FLOW_MASKS 041Ch LSU1 LSU2_FLOW_MASKS 043Ch LSU2 LSU3_FLOW_MASKS 045Ch LSU3 LSU4_FLOW_MASKS 047Ch LSU4 Figure 101 LSUn Congestion Control Flow Mask Register LSUn_FLOW_MASKS
358. states to be stored and the size of the buffer descriptor memory outside the peripheral With this in mind the peripheral s supported buffer descriptor SRAM is parameterizable A minimum size of 1 25K bytes is recommended which will allow up to 64 buffer descriptors to be stored at any given time for one core These buffer descriptors can be configured to support any combination of single and multi segment messages For example if the application only handles single segment messages all 64 buffers can be allotted to that queue Note that a given RX queue can contain packets of all priorities which have been directed from any of the receive ports A CPU may wish to stop receiving messages and reclaim buffers belonging to a specific queue This is called queue teardown The CPU initiates a RX queue teardown by writing to the RX Queue Teardown command register Address Offset 0740h Teardown of an RX queue causes the following actions e f teardown is issued by software during the time when the RX state machine is idle then the state machine will immediately start the teardown procedure Ifthe queue to be torn down is in message waiting for one or more segments then the queue will be torn down and reported with the current buffer descriptor teardown bit set ownership bit cleared CC 100b All other fields of the buffer descriptor are invalid The peripheral completes the teardown procedure by clearing the HDP register setting the CP
359. support a read operation 14 WRITE PE can support a write operation 13 STREAM_WRITE PE can support a streaming write operation 12 WRITE_WITH_RESP PE can support a write with response operation 11 DATA_MESS PE can support a data message operation 10 DOORBELL PE can support a doorbell operation 9 Reserved 0 This read only bit returns 0 when read 8 ATOMIC_TEST_AND_SWAP PE can support an atomic test and swap operation 7 ATOMIC_INCRMNT PE can support an atomic increment operation 6 ATOMIC_DCRMNT PE can support an atomic decrement operation 5 ATOMIC_SET PE can support an atomic set operation 4 ATOMIC_CLEAR PE can support an atomic clear operation 3 Reserved 0 This read only bit returns 0 when read 2 PORT_WRITE PE can support a port write generation 1 0 IMPLMNT_DEFINED_1 Defined by the device implementation SPRUE13A September 2006 Serial RapidlO SRIO 189 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 59 Processing Element Logical Layer Control CSR PE_LL_CTL The processing element logical layer control CSR PE_LL_CTL is shown in Figure 122 and described in Table 130 Figure 122 Processing Element Logical Layer Control CSR PE_LL_CTL Address Offset 104Ch 31 16 Reserved R 0 15 3 2 0 EXTENDED Reserved ADDRESSING __ CONTROL R 0 R W 001 LEGEND R W Read Write R Read only n Value after reset Table 130 Processing Element Logical Layer Control CSR PE_LL_CTL Fi
360. symbol overdue at port n rate counting enable field 222 Status field 220 link response valid field 201 link status received 201 non outstanding ackID at port n rate counting enable field 222 status field 220 link timeout at port n rate counting enable field 222 status field 220 Little Endian versus Big Endian 68 Load Store module data flow diagram 39 data path description 39 enable bit 119 enable status bits 117 120 power down state 43 Load Store units SeeLSUs 40 local configuration space base address CSRs_ 191 192 lockout field for portn 207 logical blocks of the SRIO peripheral 71 logical layer content in SRIO data stream 22 definition 16 logical layer buffers in packet transmission discussion 75 in SRIO component block diagram 26 logical transport error handling and logging 83 logical transport layer address capture CSR 215 logical transport layer control capture CSR 217 logical transport layer device ID capture CSR 216 logical transport layer error detect CSR 210 logical transport layer error enable CSR 212 logical transport layer high address capture CSR 214 LOG See logical layer 23 loopback mode 113 loop bandwidth field for SERDES PLL 130 LOS field of SERDES_CFGRXn_CNTL 125 loss of signal detection in SERDES receiver 126 LSBs of address associated with logical transport error 215 LSBs of destination ID associated with logical transport error 216 LSBs of source ID associated with logical transport error 216 LSU_I
361. symbols 22 OUTPUT_PORT_ENABLE Output port enable The port is stopped and not enabled to issue any packets except to route or respond to I O logical maintenance packets depending upon the functionality of the processing element Control symbols are not affected and are sent normally The port is enabled to issue any packets 21 INPUT_PORT_ENABLE Input port receive enable The port is stopped and only enabled to route or respond UO logical maintenance packets depending upon the functionality of the processing element Other packets generate packet not accepted control symbols to force an error condition to be signaled by the sending device Control symbols are not affected and are received and handled normally Port is enabled to respond to any packet 20 ERROR_CHECK_DISABLE Error check disable RapidlO transmission error checking and recovery are enabled RapilO transmission error checking and recovery are disabled If an error condition occurs device behavior is undefined 19 MULTICAST_PARTICIPANT Multicast event participant enable This read only bit is 0 to indicate that multicast event control symbols cannot be accepted by this port 18 4 Reserved These read only bits return Os when read 3 STOP_PORT_FLD_ENC_ENABLE Stop on fail enable Even when the Output Failed encountered bit is set the port continues to attempt to transmit packets to the connected device When the Output Failed
362. t and Special Event Interrupt Condition Routing Registers Error Reset and Special Event ICRR ERR_RST_EVNT_ICRR Address Offset 02F0h 31 Reserved HO 12 11 8 7 0 Reserved ICR2 ICR1 ICRO R 0 R W 0000 R W 0000 R W 0000 Error Reset amp Special Event ICRR 2 ERR_RST_EVNT_ICRR2 Address Offset 02F4h 31 d Reserved HO 15 12 11 8 7 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 Error Reset and Special Event ICRR 3 ERR_RST_EVNT_ICRR3 Address Offset 02F8h 31 Reserved HO 0 Reserved ICR16 R 0 R W 0000 LEGEND R W Read Write R Read only n Value after reset Table 82 Error Reset and Special Event Interrupt Condition Routing Register Field Descriptions Field Value Description ICRx Interrupt condition routing Routes the associated port interrupt request to one of eight x 0 to 2 8 to 11 and 16 interrupt destinations INTDSTO INTDST7 0000b INTDSTO 0001b INTDST1 0010b INTDST2 0011b INTDST3 0100b INTDST4 0101b INTDST5 0110b INTDST6 0111b INTDST7 1xxxb Reserved SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 149 SRIO Registers 5 31 Interrupt Status Decode Register INTDSTn_DECODE da TEXAS INSTRUMENTS www ti com There are eight of these registers one for each interrupt destination see Table 83 This type of register is shown in Figure 92 and described in T
363. t and swap Ttype others Ftype 6 Ttype don t care SWRITE Ftype 7 Ttype don t care Congestion control Ftype 8 Ttype 0000b Maintenance read Ttype 0001b Maintenance write Ttype 0010b Maintenance read response Ttype 0011b Maintenance write response Ttype 0100b Maintenance port write Ttype others Ftype 10 Ttype don t care Doorbell Ftype 11 Ttype don t care Message Ftype 13 Ttype 0000b Response Doorbell Resp Ttype 0001b Ttype 1000b Ttype other Message Response Response w payload Undefined Ftypes 1 3 4 9 12 14 15 2 2 SRIO Pins The SRIO device pins are high speed differential signals based on Current Mode Logic CML switching levels The transmit and receive buffers are self contained within the clock recovery blocks The reference clock input is not incorporated into the SERDES macro It uses a differential input buffer that is compatible with the LVDS and LVPECL interfaces available from crystal oscillator manufacturers Table 4 describes the device pins for the SRIO peripheral SPRUE13A September 2006 Submit Documentation Feedback Serial RapidlO SRIO 25 SRIO Functional Description 2 3 2 3 1 26 da TEXAS INSTRUMENTS www ti com Table 4 Pin Description Pin Name Pin Count Signal Direction Description RIOTX3 RIOTX3 RIOTX2 RIOTX2 RIOTX1 RIOTX1 RIOTX0 RIOTXO RIORX3 RIORX3 RIORX2 RIORX2 RIORX1 RIORX1 RIORX0 R
364. t condition detected Transaction was not sent due to Xoff condition 17 ICS17 ch Oj O LSU3 interrupt condition not detected LSU3 interrupt condition detected Non posted transaction received ERROR response or error in response payload 16 ICS16 LSU3 interrupt condition not detected LSU3 interrupt condition detected Transaction complete No errors posted non posted Enable for this interrupt is ultimately controlled by the Interrupt Req bit of LSU3_REG4 This allows enabling disabling on a per request basis For optimum LSU performance interrupt pacing should not be used on the LSU interrupts 15 ICS15 LSU2 interrupt condition not detected LSU2 interrupt condition detected Packet not sent due to unavailable outbound credit at given priority 14 ICS14 k LSU2 interrupt condition not detected LSU2 interrupt condition detected Retry Doorbell response received or Atomic test and swap was not allowed semaphore in use 13 ICS13 LSU2 interrupt condition not detected LSU2 interrupt condition detected Transaction was not sent due to DMA data transfer error 12 ICS12 LSU2 interrupt condition not detected LSU2 interrupt condition detected Transaction timeout occurred 11 ICS11 Oj ol O LSU2 interrupt condition not detected LSU2 interrupt condition detected Transaction was not sent due to unsupported transaction type or invalid field encoding
365. t received on any port 1 Port write in request received on any port 0 ICSO 0 Multi cast event control symbol interrupt not received on any port 1 Multi cast event control symbol interrupt received on any port 142 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 25 Error Reset and Special Event Interrupt Condition Clear Register ERR_RST_EVNT_ICCR Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR The field of ERR_RST_EVNT_ICCR are shown in Figure 86 and described in Table 76 For additional programming information see Section 4 3 4 Figure 86 Error Reset and Special Event Interrupt Condition Clear Register ERR_RST_EVNT_ICCR Address Offset 0278h 31 17 16 Reserved ICC16 R 0 W 0 15 12 11 10 9 8 7 3 2 1 0 Reserved ICC11 ICC10 ICC9 ICC8 Reserved ICC2 ICC1 ICCO R 0 WO WO WO WO HO WO WO WO LEGEND R Read only W Write only n Value after reset Table 76 Error Reset and Special Event Interrupt Condition Clear Register ERR_RST_EVNT_ICCR Field Descriptions Bit Field Value Description 31 17 Reserved 0 These read only bits return Os when read 16 ICC16 0 No effect 1 Clear bit 16 of ERR_RST_EVNT_ICSR 15 12 Reserved 0 These read only bits return Os when read 11 8 ICCx 0 No effect xe HB 1 Clear bit x of ERR_R
366. t service routine is completed the BSY signal is deasserted and the completion code becomes valid and the registers are accessible again SPRUE13A September 2006 Serial RapidlO SRIO 37 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Functional Description Figure 13 LSU Registers Timing After Transaction Completes TO T1 T2 T3 T4 T5 Tn LSUn_REG3 L LSUn_REG5 X vaa X OSE Oe FOX or Rdy BSY Completion Valid Valid The following code illustrates an LSU registers programming example SRIO_REGS gt LSU1_REGO CSL_FMK SRIO_LSU1_REGO_RAPIDIO_ADDRESS_MSB 0 SRIO_REGS gt LSU1_REG1 CSL_FMK SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET int amp rcvBuff1 0 SRIO_REGS gt LSU1_REG2 CSL_FMK SRIO_LSU1_REG2_DSP_ADDRESS int amp xmtBuff1 0 SRIO_REGS gt LSU1_REG3 CSL_FMK SRIO_LSU1_REG3_BYTE_COUNT byte_count SRIO_REGS gt LSU1_REG4 CSL_FMK SRIO_LSU1_REG4_OUTPORTID 0 CSL_FMK SRIO_LSU1_REG4_PRIORITY 0O CSL_FMK SRIO_LSU1_REG4_XAMSB 0 CSL_FMK SRIO_LSU1_REG4_ID_SIZE 1 CSL_FMK SRIO_LSU1_REG4_DESTID OxBEEF CSL_FMK SRIO_LSU1_REG4_INTERRUPT_REQ 1 SRIO_REGS gt LSU1_REG5 CSL_FMK SRIO_LSU1_REG5_DRBLL_INFO 0x0000 CSL_FMK SRIO_LSU1_REG5_HOP_COUNT 0x00 CSL_FMK SRIO_LSUlL_REGS_PACKET_TYPE type ir Figure 14 gives an example of the data flow and field mappings for a burst NWRITE_R transaction 38 Seria
367. ta stream To do this a low frequency reference clock is required Typically this clock comes from an off chip stable crystal oscillator and is a LVDS device input separate to the SERDES This clock is distributed to the SERDES PLL block which multiplies that frequency up to that of the data rate Multiple high speed clock phases are created and routed to the clock recovery blocks The clock recovery blocks further interpolate between these clocks to provide maximum Unit Interval UI resolution on the recovered clock The clock recovery block samples the incoming data and monitors the relative positions of the data edges With this information it can provide the data and a center aligned clock to the S2P block The S2P block uses the newly recovered clock to de multiplex the data into 10 bit words At this point the data leaves the SERDES macro at 1 10th the pin data rate accompanied by an aligned byte clock SPRUE13A September 2006 Serial RapidlO SRIO 21 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Figure 4 SRIO Peripheral Block Diagram 1 25 to 3 125 Gbps differential data SERDES oc D 8 0 XXX RX recovery S2 FIFO 5 Capability a EE SE registers OC 8b T0b 8b lg SO EEE FIFO 5 10b b 5 g oc z 8D T0D 8b l e COO El recovery S2 FIFO S O yy EH Clo
368. tatus 7 Section 5 8 0078h BLK8_EN Block Enable 8 Section 5 7 007Ch BLK8_EN_STAT Block Enable Status 8 Section 5 8 0080h DEVICEID_REG1 RapidlO DEVICEID1 Register Section 5 9 0084h DEVICEID_REG2 RapidlO DEVICEID2 Register Section 5 10 0090h PF_16B_CNTLO Packet Forwarding Register 0 for 16 bit DevicelDs Section 5 11 0094h PF_8B_CNTLO Packet Forwarding Register 0 for 8 bit DevicelDs Section 5 12 0098h PF_16B_CNTL1 Packet Forwarding Register 1 for 16 bit DevicelDs Section 5 11 009Ch PF_8B_CNTLI Packet Forwarding Register 1 for 8 bit DevicelDs Section 5 12 OOAOh_ PF_16B_CNTL2 Packet Forwarding Register 2 for 16 bit DevicelDs Section 5 11 00A4h PF_8B_CNTL2 Packet Forwarding Register 2 for 8 bit DevicelDs Section 5 12 00A8h PF_16B_CNTL3 Packet Forwarding Register 3 for 16 bit DevicelDs Section 5 11 00ACh PF_8B_CNTL3 Packet Forwarding Register 3 for 8 bit DevicelDs Section 5 12 0100h SERDES_CFGRXO_CNTL SERDES Receive Channel Configuration Register 0 Section 5 13 0104h SERDES CFGRX1_CNTL SERDES Receive Channel Configuration Register 1 Section 5 13 0108h SERDES_CFGRX2_CNTL SERDES Receive Channel Configuration Register 2 Section 5 13 010Ch SERDES_CFGRX3_CNTL SERDES Receive Channel Configuration Register 3 Section 5 13 0110h SERDES CFGTX0_CNTL SERDES Transmit Channel Configuration Register 0 Section 5 14 0114h SERDES CFGTX1_CNTL SERDES Transmit Channel Configuration Register 1 Section 5 14 0118h SERDES CFGTX2_CNTL SERDES Transmit Channel Confi
369. tember 2006 Submit Documentation Feedback 5 69 Port Link Maintenance Request CSR ntGbn LM BEOI eee e eee cess eeeeeeeeeeeeaeeee 200 5 70 Port Link Maintenance Response CSR n SPn_LM_RESP ceceeee sees ee eee eens eeeeeeeeeeeeeeee 201 5 71 Port Local AckID Status CSR ntGbo ACKID GIAT nun nun nen 202 5 72 Port Error and Status CGboiGbn ERR GIATI nun nnnn nen 203 5 73 _ Port Control CSR A SPM OTL una de ee nie 206 5 74 Error Reporting Block Header Register ED DPI BH 209 5 75 Logical Transport Layer Error Detect CSR ERR_DET a 210 5 76 Logical Transport Layer Error Enable CSR ERR_EN uuussu nennen nn nennen nun nennen nn nn en nn 212 5 77 Logical Transport Layer High Address Capture CSR H ADDR CAPTI HR Rn n nennen 214 5 78 Logical Transport Layer Address Capture CSR ADDR CAPT nen 215 5 79 Logical Transport Layer Device ID Capture CSR UD CART 216 5 80 Logical Transport Layer Control Capture CSR CTRL CAPTI 217 5 81 Port Write Target Device ID CSR PW_TGT_ID 0 ce cece cece eee eee nennen nun nenn nenn nennen 218 5 82 Port Error Detect CSR oiGbo ERR D I 219 5 83 Port Error Rate Enable CSR n SPn_RATE_EN cece eee e ee eee eee teen eee ee eee nannnan mann nun nen 221 5 84 Port n Attributes Error Capture CSR 0 SPn_ERR_ATTR_CAPT_DBGO eceeeeeeeeeeeeeeee 223 5 85 Port n Error Capture CSR 1 SPn_ERR_CAPT_DBG1 cs eeeeee ence ee eee eee cree eee nn nun nun nen 224 5 86 Port n Err
370. tember 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 6 Peripheral Global Enable Status Register GBL_EN_STAT The peripheral global enable status register GBL_EN_STAT is shown in Figure 67 and described in Table 45 For additional programming information see Section 2 3 10 Figure 67 Peripheral Global Enable Status Register GPL EN STAT Address 0034h 31 24 Reserved R 0 23 16 Reserved R 0 15 10 9 8 Reserved Zaemer en R 0 R 1 R 1 7 6 5 4 3 2 1 0 BLK6_EN_ BLK5_EN_ BLK4_EN_ BLK3_EN_ BLK2_EN_ BLK1_EN_ BLKO_EN_ GBL_EN_ STAT STAT STAT STAT STAT STAT STAT STAT R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 LEGEND R Read only n Value after reset Table 45 Peripheral Global Enable Status Register GBL_EN_STAT Field Descriptions Bit Field Value Description 31 10 Reserved 0 These read only bits return Os when read 9 BLK8_EN_STAT Block 8 enable status Logical block 8 is SRIO port 3 0 Logical block 8 is in reset with its clock off 1 Logical block 8 is enabled with its clock running 8 BLK7_EN_STAT Block 7 enable status Logical block 7 is SRIO port 2 0 Logical block 7 is in reset with its clock off 1 Logical block 7 is enabled with its clock running 7 BLK6_EN_STAT Block 6 enable status Logical block 6 is SRIO port 1 0 Logical block 6 is in reset with its clock off 1 Logica
371. ten contiguously into memory beginning at the specified address Any unaligned payloads will be padded and properly aligned within the 8 byte boundary In this case WDPTR RDSIZE and WRSIZE RapidlO header fields indicate the byte position of the data within the double word boundary An example of an unaligned transfer is shown in Section 2 4 of the Rapid O Interconnect Specification Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description 2 3 9 1 Translation for MMR space There are no Endian translation requirements for accessing the local MMR space Regardless of the device memory Endian configuration all configuration bus accesses are performed on 32 bit values at a fixed address position The bit positions in the 32 bit word are defined by this specification This means that a memory image which will be copied to a MMR is identical between Little Endian and Big Endian configurations Configuration bus reads are performed in the same manner Figure 30 illustrates the concept The desired operation is to locally update a serial RapidIO MMR offset 1000h with a value of AOA1A2ASh using the configuration bus Figure 30 Configuration Bus Example Byte Byte lane 0 lane 3 31 0 L2 offset 0x0 AO A1 A2 A3 DSP defined MMR AO A1 A2 A3 offset 0x1000 DMA 32b When accessing RapidlO defined MMR within an ext
372. ters and the Associated Porte 229 175 Port Error Rate Threshold CSR n SPn_ERR_THRESH Field Descriotons nn nn an nn 229 176 Port IP Discovery Timer for 4x Mode Register SP_IP_DISCOVERY_TIMER Field Descriptions 230 177 Port IP Mode CSR SP_IP_MODE Field Descriptions eee e ence ee ee eens eee nannnnn nun nun nun nenn 231 178 Port IP Prescaler Register IP_PRESCAL Field Descriptions 0 eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 233 179 Port Write In Capture CSR Field Descriptions ur uuuunnaunnannannnunnannannnunnannann nun nun nun nann una nenn 234 180 SPn_RST_OPT Registers and the Associated Porte 235 181 Port Reset Option CSR n SPn_RST_OPT Field Descriptions 2ce cece ee eee ence eee eee nun nennen nen 235 182 SPn_CTL_INDEP Registers and the Associated Porte 236 183 Port Control Independent Register n SPn_CTL_INDEP Field Descriptions sceeeeeeeeeeeeeeeeees 236 184 SPn_SILENCE_TIMER Registers and the Associated Porte 238 185 Port Silence Timer n Register SPn_SILENCE_TIMER Field Descriptions eceeeeeeeeeeeeeeeeeeeeeeee 238 186 SPn_MULT_EVNT_CS Registers and the Associated Portes 239 187 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS Field Descriptions 239 188 SPn_CS_TX Registers and the Associated Portes 240 189 Port Control Symbol Transmit n Register SPn_CS_TX Field Descriptions eeeeeeeeeeeee eee ees 240 SPRUE13A S
373. the request packet for an IO message transaction 1 The MAU RXU received illegal fields in the request packet for an IO message transaction To clear this bit write 0 to it 26 Reserved 0 This read only bit returns 0 when read 210 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 151 Logical Transport Layer Error Detect CSR ERR_DET Field Descriptions continued Bit Field Value Description 25 MSG_REQ_TIMEOUT Message request timeout endpoint device only 0 A timeout has not been detected by RXU 1 A timeout has been detected by the RXU A required message request has not been received by the RXU within the specified time out interval To clear this bit write O to it 24 PKT_RSPNS_TIMEOUT Packet response timeout endpoint device only 0 A timeout has not been detected by an LSU or the TXU 1 A timeout has been detected by an LSU or the TXU A required response has not been received by the LSU TXU within the specified timeout interval To clear this bit write 0 to it 23 UNSOLICITED_RSPNS Unsolicited response switch or endpoint device 0 An unsolicited response packet has not been received by an LSU or the TXU 1 An unsolicited response packet has been received by an LSU or the TXU To clear this bit write 0 to it 22 UNSUPPORTED_TRANS Unsupported transaction switch or endpoint device 0 The MAU has not received an unsupported
374. thout any message response being received 100 DMA data transfer error 101 Descriptor Programming error 110 TX Queue Teardown Complete 111 Outbound Credit not available An ERROR transfer completion code indicates an error in one or more segments of a transmitted multi segment message message_length Message Length Message Length Written by the DSP core to specify the number of double words to transmit Message payloads are limited to a maximum size of 512 double words 4096 bytes 000000000b 512 double words 000000001b 1 double word 00000001 0b 2 double words 111111111b 511 double words dest_id Destination Node Id Unique Node identifier for the Destination of the message Written by the DSP core pri Message Priority Specifies the SRIO priority at which the message will be sent Messages should not be sent at a priority level of 3 because the message response is required to promote the priority to avoid system deadlock It is the responsibility of the software to assign the appropriate outgoing priority tt RapidlO tt field specifying 8 or 16 bit DevicelDs Written by the host 00 8 bit devicelDs 01 16 bit devicelDs 10 reserved 11 reserved port_id Port number for routing outgoing packet Written by the DSP core SPRUE13A September 2006 Submit Documentation Feedback Serial RapidiO SRIO 53 da TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 21 T
375. tiguous block of buffer descriptors starting at the oldest outstanding descriptor has been processed by the hardware and is ready for the CPU to reclaim the buffers Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com SRIO Functional Description A transaction timeout is used by all outgoing message and direct I O packets It has the same value and is analogous to the request to response timer discussed in the RX CPPI and LSU sections which is defined by the 24 bit value in the port response time out CSR See Section 2 3 3 3 The Rapid O Interconnect Specification states that the maximum time interval all 1s is between 3 and 6 seconds A logical layer timeout occurs if the response packet is not received before a countdown timer initialized to this CSR value reaches zero Since transaction responses can be acknowledged out of order a timer is needed for each supported outstanding packet in the TX queue Each outstanding packet response timer requires a 4 bit register The register is loaded with the current timecode when the transaction is sent Each time the timecode changes a 4 bit compare is done to the 16 outstanding packet registers If the register becomes equal to the timecode again without a response being seen then the transaction has timed out and the buffer descriptor is written Essentially instead of the 24 bit value representing the period of the response timer the perio
376. tion 31 24 Reserved 00h These read only bits return Os when read 23 16 BASE_DEVICEID 00h FFh This is the base ID of the device in small common transport system endpoints only 15 0 LARGE_BASE_DEVICEID 0000h FFFFh This is the base ID of the device in a large common transport system Only valid for endpoints and if bit 4 of the PE_FEAT Register is set SPRUE13A September 2006 Serial RapidlO SRIO 193 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 63 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK See Section 2 4 2 of the RapidlO Common Transport Specification for a description of this register It provides a lock function that is write once reset able The host base device ID lock CSR HOST_BASE_ID_LOCK is shown in Figure 126 and described in Table 134 Figure 126 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK Address Offset 1068h 31 16 15 Reserved HOST_BASE_DEVICEID R 0000h R W FFFFh LEGEND R W Read Write R Read only n Value after reset Table 134 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK Field Descriptions 194 Bit Field Value Description 31 16 Reserved 0000h These read only bits return Os when read 15 0 HOST_BASE_DEVICEID 0000h FFFFh This is the base ID for the Host PE that is initializing this PE Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback i3 TEXAS IN
377. tion The peripheral functions normally irrespective of the CPU emulation state Soft Stop Mode The peripheral gracefully halts operations The peripheral halts operation at a point that makes sense both to the internal DMA data access operation and to the pin interface as described below after finishing packet reception or transmission in progress e DMA bus DMA master DMA bus requests in progress are allowed to complete DMA bus has no means to throttle command in progress from the master DMA bus requests that correspond to the same network packet are allowed to complete No new DMA bus requests will be generated on the next new packet e Configuration bus MMR interface All memory mapped register MMR configuration bus requests are serviced as normal e Events interrupts New events interrupts are not generated to the CPU for newly arriving packets Current transactions are allowed to finish and may cause an interrupt upon completion e Slave pin interface The pin interface functions as normal If buffering is available in the peripheral the peripheral services externally generated requests as long as possible When the internal buffers are consumed the peripheral will retry incoming network packets in the physical layer e Master pin interface No new master requests are generated Master requests in progress are allowed to complete including all packets located in the physical layer transmit buffers Hard Stop Mode The peripheral ha
378. tion error at port n rate counting enable field 222 status field 220 dest_id field of TX buffer descriptor 52 DEST_OP 189 DESTID field for LSUn 159 DESTID field of ID CAPT 216 DESTID field of LSUn_REG4 159 destination IDs destination ID associated with logical transport error 216 device ID for port write target 218 disable base ID match requirement field for ports 231 for control flows description 181 introduction 66 for LSU transmission 159 size select field for flow control 181 destination operations CAR 189 DEV_ID 182 Index 243 SRIO Registers DEV_INFO 183 DEVICE_VENDORIDENTITY field of DEV_ID 182 DEVICEID_MSB field of PW_TGT_ID 218 DEVICEID_REG1 121 DEVICEID_REG2 122 device ID capture CSR for logical transport errors 216 device identity CAR 182 DEVICEIDENTITY field of DEV_ID 182 DEVICEID field of PW_TGT_ID 218 device IDs base device ID for host PE 194 base device ID for large common transport system 193 base device ID for small common transport system 193 device ID for port write target 218 disable base ID match requirement field for ports 231 flow control destination ID size field 181 lower boundary for packet forwarding 8 bit IDs 124 16 bit IDs 123 node ID field to compare to incoming destination ID 122 node ID field to supply outgoing source ID 121 size selection field for LSUn 159 upper boundary for packet forwarding 8 bit IDs 124 16 bit IDs 123 device information CAR 183 device revision field 183 devi
379. transaction 1 The MAU has received an unsupported transaction That is the MAU received a transaction that is not supported in the destination operations CAR To clear this bit write O to it 21 8 Reserved 0 These read only bits return O when read 7 RX_CPPI_SECURITY RX CPPI security error 0 The RXU has not detected an access block 1 The RXU has detected an access block That is access to one of the RX queues was blocked To clear this bit write O to it 6 RX_lIO_DMA_ACCESS RX I O DMA access error 0 A DMA access to the MAU has not been blocked 1 A DMA access to the MAU was blocked To clear this bit write O to it 5 0 Reserved 0 These read only bits return 0 when read SPRUE13A September 2006 Serial RapidlO SRIO 211 Submit Documentation Feedback SRIO Registers da TEXAS INSTRUMENTS www ti com 5 76 Logical Transport Layer Error Enable CSR ERR_EN The logical transport layer error enable CSR ERR_EN is shown in Figure 139 and described in Table 152 Figure 139 Logical Transport Layer Error Enable CSR ERR_EN Address Offset 200Ch 31 30 29 28 27 26 25 24 IO_ERR_ MSG_ERR_ Reserved ERR_MSG ILL_TRANS Reserved MSG_REQ PKT_RESP RESP_ RESP_ write 0 FORMAT DECODE_ write 0 TIMEOUT_ TIMEOUT_ ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 23 22 21 UNSOLICITED UNSUPPOR
380. ts As a result the MAU or RXU is free to promote a packet s priority level until priority 3 is reached If priority 3 cannot warrant a credit the MAU or RXU keeps retrying on priority 3 until credit is available The assumption is that if all priority levels become backed up the physical layer re ordering mechanism will be implemented to send out the highest priority packets first LSUs For single packet transfers if the transfer is unsuccessful after 256 times of credit request a completion code of 111b is indicated in the LSU status register LSUn_REG6 After reading this status software must determine whether to try again increase the priority or try a different control flow For transfers with up to 4K byte payloads requiring multiple packets if the transfer is unsuccessful after 256 times of credit request for the first packet a completion code of 111b is indicated in LSUn_REG6 After the first packet is successfully completed subsequent packets are given more retry attempts The LSU makes up to 64K attempts to gain outbound credit for the subsequent packets If the LSU is unsuccessful after the 64K attempts a completion code of 111b is indicated in LSUn_REG6 TXU The TXU cannot change state to handle inbound responses while it is requesting outbound credit To avoid deadlock situations the TXU tries for outbound credit in the following manner For single segment messages if the transfer is unsuccessful after 256 times of cred
381. ts see Table 59 The general form for a SERDES transmit channel configuration register is summarized by Figure 75 and Table 60 See Section 2 3 2 3 for a complete explanation of the programming for these registers Table 59 SERDES_CFGTXn_CNTL Registers and the Associated Ports Register Address Offset Associated Port SERDES_CFGTX0_CNTL 0110h Port 0 SERDES_CFGTX1_CNTL 0114h Port 1 SERDES_CFGTX2_CNTL 0118h Port 2 TMS320TC16482 Only SERDES_CFGTX3_CNTL 011Ch Port 3 TMS320TC16482 Only Figure 75 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL 31 17 16 Reserved ENFTP R 0 R W 0 15 12 11 9 8 7 6 5 4 2 1 0 DE SWING CM INVPAIR RATE BUSWIDTH write 0 ENTX R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n Value after reset Table 60 SERDES Transmit Channel Configuration Register n SERDES_CFGTXn_CNTL Field Descriptions Bit Field Value Description 31 17 Reserved 0 These read only bits return Os when read 16 ENFTP 1 Enables fixed phase relationship of transmit input clock with respect to transmit output clock The only valid value for this field is 1b all other values are reserved 15 12 DE 0000b 1111b De emphasis Selects one of 15 output de emphasis settings from 4 76 to 71 42 De emphasis provides a means to compensate for high frequency attenuation in the attached media It cau
382. ts partner are fully initialized and ready for normal operation the peripheral will not send any data packets or non status control symbols e GBL_EN Resets all MMRs excluding Reset Ctl Values 0000h 01FCh Resets all logical blocks except MMR configuration bus i f While asserted the slave configuration bus is operational e BLK_ENO Resets all MMRs excluding Reset Ctl Values 0000h 01FCh Other logical blocks are unaffected including MMR configuration bus i f e BLK_EN n 1 Single enable reset per logical block See Table 26 2 3 10 2 Enable and Enable Status Registers The enable and enable status registers are comprised of two global registers and nine pairs of block specific registers The global registers are summarized by Figure 32 Figure 33 Table 26 and Table 27 The GBL_EN register is implemented with a single enable bit This bit is logically ORed with the reset input to the module and is fanned out to all logical blocks within the peripheral Figure 32 GBL_EN Address 0030h 31 1 0 Reserved EN HO R W 1 LEGEND R W Read Write R Read only n Value after reset Figure 33 GBL_EN_STAT Address 0034h 31 24 Reserved R 0 23 16 Reserved R 0 15 10 9 8 Reserved BLK8_EN_ BLK7_EN_ STAT STAT R 0 R 1 R 1 7 6 5 4 3 2 1 0 BLK6_EN_ BLK5_EN_ BLK4_EN_ BLK3_EN_ BLK2_EN_ BLK1_EN_ BLKO_EN_ GBL_EN_ STAT STAT STAT STAT STAT STAT STAT STAT R 1 R 1 R
383. ture CSR ADDR_CAPT Address Offset 201 An 215 142 Logical Transport Layer Device ID Capture CSR ID_CAPT Address Offset 2018h uruussunnen nn 216 143 Logical Transport Layer Control Capture CSR CTRL_CAPT Address Offset 201Ch HH Rn 217 144 Port Write Target Device ID CSR PW_TGT_ID Address Offset 2028h zuuu4uu4n HH nenn nenn nennen 218 145 Port Error Detect CSR n SPn_ERR_DET uuzsssensennunnnannnnnunnnnnnnnnnnnnannnnn nun nun nun nun nun nunnannnenn 219 146 Port Error Rate Enable CSR n SPn_RATE_EN a 221 147 Port n Attributes Error Capture CSR O Gbo ERR ATTRH CAPT D BG0 223 148 Port n Error Capture CSR 1 SPn_ERR_CAPT_DBGI uzusuennennnunnannnnnnannunnnnn nun nun nun nun une nn 224 149 Port n Error Capture CSR 2 SPn_ERR_CAPT_DBQ2 uuusunnennannnnnnannannnunnunnnnnnnnnnn nun nun ann nn 225 150 Port n Error Capture CSR 3 SPn_ERR_CAPT_DBG cceeee cece ee eee eee eee eee eee ee ee ee seen nun nun ann nn 226 151 Port n Error Capture CSR 4 SPn_ERR_CAPT_DBGA4 0 cceeee eee eee eee ener eee eee eee e eee eee eee eee ann eee 227 152 Port Error Rate CSR n SPn_ERR_RATE uusussnsnennnannannannnannannnunnunnannnannnunnnnnunnnannunnann nun nenn 228 153 Port Error Rate Threshold CSR o Gbn ERR THREGHN sees ee eee eee eee nun nun nun nun nun nun en nun 229 154 Port IP Discovery Timer for 4x Mode Register SP_IP_DISCOVERY_TIMER Address Offset 12000h 230 List of Figures SPRUE13A Septembe
384. tus register that reflects the state of each condition that can trigger the interrupt The general description of each interrupt condition status bit ICSx is given in Table 35 e Interrupt Condition Clear Register ICCR Command register that allows each condition to be cleared This is typically required prior to enabling a condition so that spurious interrupts are not generated Table 35 shows the general description of an interrupt condition clear bit ICCx These registers are accessible in the memory map of the CPU The CPU controls the clear register The status register is readable by the CPU to determine the peripheral condition Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Interrupt Conditions Table 35 Interrupt Condition Status and Clear Bits Field Access Reset Value Value Function ICSx R 0 0 Condition not present 1 Condition present ICCx Ww 0 0 No effect 1 Clear the condition status bit ICSx 4 3 1 Doorbell Interrupt Condition Status and Clear Registers The interrupt condition status registers ICSRs and the interrupt condition clear registers ICCRs for the four doorbells are shown in Figure 46 through Figure 49 These registers are used when the SRIO peripheral receives doorbell packets The 16 ICS bits of each interrupt condition status register ICSR indicate the incoming doorbell information packet For example the b
385. ubmit Documentation Feedback SRIO Registers packet response timeout at LSU or TXU reporting enable field 213 status field 211 packets bad CRC in packet at port n rate counting enable field 222 status field 220 force insertion of control symbol in outbound packet 240 Ftype and Ttype 25 maintenance packets 63 operation sequence 22 oversize packet at port n rate counting enable field 222 status field 220 send debug packet field for portn 237 streaming write example 23 unexpected ackID in packet at port n rate counting enable field 222 status field 220 unexpected packet at port n rate counting enable field 222 status field 220 PAR_O0 field of SPn_CS_TX 240 PAR_1 field of SPn_CS_TX 240 parameterO control symbol field for portn 240 parameter control symbol field for portn 240 payload capture fields for port write in 234 PCR 112 PE FEAT 186 PE LL CTL 190 peak value of error rate counter for portn 228 PER_SET_CNTL 113 PEREN field of PCR 112 peripheral class field 111 peripheral control register 112 peripheral data flow 21 peripheral flow control enable bit 112 peripheral global enable register 116 peripheral global enable status register 117 peripheral identification register 111 peripheral revision field 111 peripheral settings control register 113 peripheral type field 111 PF_8B_CNTL 124 PF_16B_CNTLn 123 PHY See physical layer 23 physical layer content in SRIO data stream 22 control symbols
386. ueue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map2 56 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Table 22 Weighted Round Robin Programming Registers Address Offset 7EOh 7ECh continued Field Pair Register Bits Field Value Description TX_Queue_Map2 TX_QUEUE_CNTLO 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map3 TX_Queue_Map3 TX_QUEUE_CNTLO 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTLO 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map4 TX_Queue_Map4 TX_QUEUE_CNTL1 3 0 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL1 7 4 Numbe
387. uffer descriptor 52 RETRY response in message passing 43 REV field of PID 111 RIOCLK and RIOCLK signals 25 RIORXn and RIORXn signals 25 RIOTXn and RIOTXn signals 25 round robin access to TX buffer descriptor queues 54 routing interrupt conditions to interrupt destinations 93 routing registers for CPPI interrupt conditions 145 146 Index 251 SRIO Registers for doorbell interrupt conditions 144 for error reset and special event port interrupt conditions 149 for LSU interrupt conditions 147 RST_CS field of SP_IP_MODE 231 RST_EN field of SP_IP_MODE 231 rules for CPPI data traffic 43 RX_CP field of QUEUEn_RXDMA_CP 167 RX_CPPI_CNTL 173 RX_CPPI_ICCR 135 RX_CPPI_ICRR 145 RX_CPPI_ICRR2 145 RX_CPPI_ICSR 134 RX_CPPI_SECURITY_ENABLE field of ERR_EN 212 RX_CPPI_SECURITY field of ERR_DET 210 RX_HDP field of QUEUEn_RXDMA_HDP 166 RX_IO_DMA_ACCESS field of ERR_DET 210 RX_IO_SECURITY_ENABLE field of ERR_EN 212 RX_QUEUE_TEAR_DOWN 172 RX buffer descriptor fields 47 RX buffer descriptor link list figure 61 RX buffer descriptor queue teardown 50 RX CPPI security error reporting enable field 213 status bit 211 RX I O DMA access error reporting enable field 213 status field 211 RX shared buffer in direct I O RX operation 42 in direct O TX READ transaction 41 in SRIO component block diagram 26 RXU enable bit 119 enable status bits 117 120 handling of unavailable outbound credit 76 in SRIO component block diagram 26 RXU_MAP registers descri
388. umber of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map13 TX_Queue_Map13 TX_QUEUE_CNTL3 11 8 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 15 12 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map14 TX_Queue_Map14 TX_QUEUE_CNTL3 19 16 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 23 20 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map15 TX_Queue_Map15 TX_QUEUE_CNTL3 27 24 Queue Pointer Oh to Fh Pointer to a queue This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues TX_QUEUE_CNTL3 31 28 Number of Msgs Oh to Fh Number of contiguous messages descriptors to process before moving to TX_Queue_Map0 The TX queues are treated differently than the RX queues A TX queue can mix single and multi segment message buffer descriptors The software manages the queue usage All outgoing message segments have responses that indicate the status of the transaction Responses may indicate DONE ERROR or RETRY A buffer descriptor may be released back to CPU control OWNERSHIP
389. uniquely managed to meet individual customer applications For example control registers within the SERDES allow you to adjust the TX differential output voltage Vod on a per driver basis This allows power savings on short trace links on the same board by reducing the TX swing Similarly data edge rates can be adjusted through the control registers to help reduce any EMI affects Unused links can be individually powered down without affecting the working links The SERDES macro is a self contained macro which includes transmitter TX receiver RX phase locked loop PLL clock recovery serial to parallel S2P and parallel to serial P2S blocks The internal PLL multiplies a user supplied reference clock All loop filter components of the PLL are onchip Likewise the differential TX and RX buffers contain on chip termination resistors The only off chip component requirement is for DC blocking capacitors 2 3 2 1 Enabling the PLL The Physical layer SERDES has a built in PLL which is used for the clock recovery circuitry The PLL is responsible for clock multiplication of a slow speed reference clock This reference clock has no timing relationship to the serial data and is asynchronous to any CPU system clock The multiplied high speed clock is only routed within the SERDES block it is not distributed to the remaining blocks of the peripheral nor is it a boundary signal to the core of the device It is extremely important to have a good
390. upt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 6 bit 6 of DOORBELLO_ICSR e Doorbell 1 bit 6 bit 6 of DOORBELL1_ICSR e Doorbell 2 bit 6 bit 6 of DOORBELL2_ICSR e Doorbell 3 bit 6 bit 6 of DOORBELL3_ICSR ISD5 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 5 bit 5 of DOORBELLO_ICSR e Doorbell 1 bit 5 bit 5 of DOORBELL1_ICSR e Doorbell 2 bit 5 bit 5 of DOORBELL2_ICSR e Doorbell 3 bit 5 bit 5 of DOORBELL3_ICSR ISD4 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 4 bit 4 of DOORBELLO_ICSR e Doorbell 1 bit 4 bit 4 of DOORBELL1_ICSR e Doorbell 2 bit 4 bit 4 of DOORBELL2_ICSR e Doorbell 3 bit 4 bit 4 of DOORBELL3_ICSR ISD3 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 3 bit 3 of DOORBELLO_ICSR e Doorbell 1 bit 3 bit 3 of DOORBELL1_ICSR e Doorbell 2 bit 3 bit 3 of DOORBELL2_ICSR e Doorbell 3 bit 3 bit 3 of DOORBELL3_ICSR ISD2 No interrupt request routed to this bit Interrupt request detected Possible interrupt sources e Doorbell 0 bit 2 bit 2 of DOORBELLO_ICSR e Doorbell 1 bit 2 bit 2 of DOORBELL1_ICSR e Doorbell 2 bit 2 bit 2 of DOORBELL2_ICSR e Doorbell 3 bit 2 bit 2 of DOORBELL3_ICSR
391. used in conjunction with BYTE_COUNT to create a 64 bit aligned RapidlO packet header address For packet type 8 maintenance packet 00000000h The right aligned 24 bit register configuration offset This value is to used in conjunction with BYTE_COUNT to create a 64 bit aligned OOFFFFFFh RapidlO packet header Config_offset value The 2 LSBs of this field must be Os because the smallest configuration access is 4 bytes 156 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 35 LSUn Control Register 2 LSUn_REG2 There are four of these registers one for each LSU see Table 91 LSUn_REG2 is shown in Figure 96 and described in Table 92 For additional programming see Section 2 3 3 Table 91 LSUn_REG2 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG2 0408h LSU1 LSU2_REG2 0428h LSU2 LSU3_REG2 0448h LSU3 LSU4_REG2 0468h LSU4 Figure 96 LSUn Control Register 2 LSUn_REG2 31 DSP_ADDRESS R W 00000000h LEGEND R W Read Write n Value after reset Table 92 LSUn Control Register 2 LSUn_REG2 Field Descriptions Bit Field Value Description 31 0 DSP_ADDRESS 00000000h 32 bit DSP byte address for the source of the LSU transaction to FFFFFFFFh SPRUE13A September 2006 Serial RapidlO SRIO 157 Submit Documentation Feedback da TEXAS INSTRUMENTS w
392. ve CPPI Control Register RX_CPPI_CNTL Address Offset 0744h uuusussansunnannnannannnnnnennnn 173 112 Transmit CPPI Weighted Round Robin Control Registers A 174 113 Mailbox to Queue Mapping Register Par 179 114 Flow Control Table Entry Register n FL OW CNTLo nun nunnannnunnunnunnnnn 181 115 Device Identity CAR DEV_ID Address Offset 1000h uuuusussennennnunnnnnannnannnunnunnannnnnnun nun nun 182 116 Device Information CAR DEV_INFO Address Offset 1004h zersensannnnnennnannnnnnnnnannnannun nun nun nn 183 117 Assembly Identity CAR ASBLY_ID Address Offset 1008h 222us4 s san nennen nun nun nun mann nun nun une nn 184 118 Assembly Information CAR ASBLY_INFO Address Offset 1000h ann 185 119 Processing Element Features CAR PE_FEAT Address Offset 1010h uuss ssun nenne ann an nun nun 186 120 Source Operations CAR SRC_OP Address Offset 1018h uzursussuunennnannnnnnnnnannnunnun nun nannnn 188 121 Destination Operations CAR DEST_OP Address Offset 1010h nen nn nn an nun nun nun anne 189 122 Processing Element Logical Layer Control CSR PE_LL_CTL Address Offset 1O4Ch nenn 190 123 Local Configuration Space Base Address 0 CSR LCL_CFG_HBAR Address Offset 1058h 191 124 Local Configuration Space Base Address 1 CSR LCL_CFG_BAR Address Offset 1050h sssccccccssses 192 125 Base Device ID CSR BASE_ID Address Offset 1060h ccceeee cece eee ee eee e neces eens eeeeeeeeee
393. ve transmit data line TDx on one device is connected to a positive receive data line RDx on the other device Likewise each negative transmit data line TDx is connected to a negative receive data line RDx Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback INSTRUMENTS www ti com Overview Figure 3 Serial RapidlO Device to Device Interface Diagrams 1x Device RD 0 RD 0 1x Device TD 0 TD 0 RD 0 RDO TDIO TD O Serial RapidlO 1x Device to 1x Device Interface Diagram 4x Device RD 0 3 RD 0 3 4x Device TD 0 3 TD 0 3 Serial RapidlO 4x Device to 4x Device Interface Diagram 1 2 RapidlO Feature Support in SRIO Features Supported in SRIO Peripheral e RapidlO Interconnect Specification V1 2 compliance Errata 1 2 e Physical Layer 1x 4x LP Serial Specification V1 2 compliance e 4x Serial RapidlO with auto negotiation to 1x port optional operation for four 1x ports e Integrated clock recovery with TI SERDES e Hardware error handling including Cyclic Redundancy Code CRC e Differential CML signaling supporting AC coupling e Support for 1 25 2 5 and 3 125 Gbps rates e Power down option for unused ports e Read write write with response streaming write outgoing Atomic and maintenance operations e Generates interrupts to the CPU Doorbell packets and internal scheduling e Support for 8 bit and 16 bit device ID e Support for receiv
394. ves the TX FIFOs Here a reordering mechanism exists which transmits the highest priority packets first if RETRY acknowledges Once in the FIFO the data is guaranteed to be transmitted through the pins Alternatively if an intended flow has been shut down the peripheral signals the CPU with an interrupt to notify that the packet was not sent and sets the completion code to 010b in the status register The registers are held until the interrupt service routine is complete before the BSY signal is released BSY 0 in LSUn_REG6 and the CPU can then rewrite or overwrite the transfer descriptors with new data Figure 15 illustrates the data path and buffering that is required to support the Load Store module SPRUE13A September 2006 Serial RapidlO SRIO 39 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Functional Description Figure 15 Load Store Module Data Flow Diagram UDI Peripheral boundary RapidlO transport and physical layers Load Store module Write transfer descriptors MMR command Config bus access Port x transmission zu FIFO queues arbitrator DMA request Shared RX buffer L2 memory lt q DMA response _ Shared resource for CPPI and MAU 2 3 3 2 Direct I O TX Operation WRITE Transactions The TX buffers are implemented in a single SRAM and shared between multiple cores A state machine arbitrates and assigns available buffers betwee
395. where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or se
396. will come from Queue 1 Within a given queue the hardware will always try to send the head buffer descriptor and can not move to the next buffer descriptor in the queue until a completion code is written The weighted round robin control advocates that statistically over many transmissions the messages will be transmitted in accordance with the percentages programmed into the registers Network traffic can also affect the packet delivery order The physical layer of the RapidlO peripheral can re order packets of different priorities when fabric congestion occurs If message ordering is needed the following must be obeyed e Multi Segmented Messages If there are only two devices A sending to B where ordering has to be guaranteed e Use one TX queue e Use the same priority e Map all messages to the same RX queue _ ee are multiple devices A and B both sending to C and ordering has to be guaranteed for e Use one TX queue in each sending device e Use the same priority within each TX queue e Map all A messages to the same RX queue and all B messages to another queue by disabling the promiscuous mode and programming allowable sourcelDs e Single Segmented Messages There will never be a retry so even if there are multiple senders e Use one TX queue in each sending device e Use the same priority within each TX queue e Map all messages to the same RX queue SPRUE13A September 2006 Serial RapidlO SRIO 55 Submit Documentati
397. within the PLL itself It is difficult to predict whether the improvement in the former will more than offset the degradation in the latter 11b High bandwidth The PLL bandwidth is set to a eighth of the frequency of RIOCLK RIOCLK This is the setting appropriate for systems where the reference clock is cleaned through an ultra low jitter LC based PLL Standards compliance will be achieved even if the reference clock input to the cleaner PLL is outside the specification for the standard 7 6 Reserved 0 Reserved 130 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers Table 64 SERDES Macro Configuration Register n SERDES_CFGn_CNTL Field Descriptions continued Bit Field Value Description 5 1 MPY PLL multiply Select PLL multiply factors between 4 and 60 00000b 4x 00001b 5x 00010b 6x 00011b Reserved 00100b 8x 00101b 10x 00110b 12x 00111b 12 5x 01000b 15x 01001b 20x 01010b 25x 01011b Reserved 01100b Reserved 01111b Reserved 1xxxxb Reserved 0 ENPLL Enable PLL 0 PLL disabled 1 PLL enabled SPRUE13A September 2006 Serial RapidlO SRIO 131 Submit Documentation Feedback da TEXAS INSTRUMENTS www ti com SRIO Registers 5 16 DOORBELLn Interrupt Condition Status Register DOORBELLn_ICSR The four doorbell interrupts are mapped to these registers see Table 65 The general form of a doorbell int
398. wn 70 ssize field of TX buffer descriptor 52 status bits for recording interrupt conditions 86 status registers for CPPI interrupt conditions 134 136 for doorbell interrupt conditions 132 for error reset and special event port interrupt conditions 142 for LSU interrupt conditions 138 STOP_PORT_FLD_ENC_ENABLE field of SPn_CTL 206 stop on output failure at portn 207 stop receiving messages and reclaim buffers RX teardown 50 stop transmitting messages and clear buffers TX teardown 59 store and forward mode option for portn 236 STREAM_WRITE field of DEST_OP 189 STREAM_WRITE field of SRC_OP 188 streaming write packet example 23 streaming write support for destination device 189 streaming write support for source device 188 stypeO and stype1 control symbols 24 stypeO control symbol field for portn 240 stype1 control symbol field for portn 240 STYPE_0 field of SPn_CS_TX 240 STYPE_1 field of SPn_CS_TX 240 suppression support field 186 SW_MEM_SLEEP_OVERRIDE field of PER_SET_CNTL 113 SPRUE13A September 2006 Submit Documentation Feedback SRIO Registers SWING field of SERDES_CFGTXn_CNTL 128 switch capability field 186 SWITCH field of PE_FEAT 186 SWRITE packet Ftype and Ttype 25 symbol alignment field 126 T target IDs See destination IDs 218 teardown_complete field of RX buffer descriptor 47 teardown_complete field of TX buffer descriptor 52 teardown bits for RX queues 172 teardown bits for TX queues 168 teardown
399. write request for software assistance The timer is stopped by software writing to the error detect registers 0000b Disabled Port write is sent once only 0001b 107 ms 214 ms 0010b 214 ms 321 ms 0100b 428 ms 535 ms 1000b 856 ms 963 ms default Other Reserved 19 0 Reserved 0000h These read only bits return Os when read 230 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 92 Port IP Mode CSR SP_IP_MODE The port IP mode CSR SP_IP_MODE is shown in Figure 155 and described in Table 177 For additional programming information see Section 2 3 13 2 Figure 155 Port IP Mode CSR SP_IP_MODE Address Offset 12004h 31 30 29 28 27 25 24 16 IDLE TX SP_MODE ERR_ FIFO_ ee e eee Reserved DIS BYPASS R W 0 RW 0 R W 0 RW 0 RO RW R 0 15 6 5 4 3 2 1 0 MLTC_ MLTC_ RST RST PW_ PW Reserved EN IRQ EN cs EN IRQ R 0 RW 0 R W 0 Bun RW 0 Dun R W 0 LEGEND R W Read Write R Read only n Value after reset Table 177 Port IP Mode CSR SP_IP_MODE Field Descriptions Bit Field Value Description 31 30 SP_MODE SRIO port IP mode of operation 00b RapidlO Physical Layer 1x 4x LP Serial Specification 01b 4 ports 1x mode each 10b Reserved 11b Reserved 29 IDLE_ERR_DIS Idle error checking disable 0 Error checking enabled
400. ww ti com SRIO Registers 5 36 LSUn Control Register 3 LSUn_REG3 There are four of these registers one for each LSU see Table 93 LSUn_REG3 is shown in Figure 97 and described in Table 94 For additional programming see Section 2 3 3 Table 93 LSUn_REG3 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG3 040Ch LSU1 LSU2_REG3 042Ch LSU2 LSU3_REG3 044Ch LSU3 LSU4_REG3 046Ch LSU4 Figure 97 LSUn Control Register 3 LSUn_REG3 31 16 Reserved R 0000h 15 12 11 Reserved BYTE_COUNT R Oh R W 000h LEGEND R W Read Write R Read only n Value after reset Table 94 LSUn Control Register 3 LSUn_REG3 Field Descriptions Bit Field Value Description 31 12 Reserved 00000h These read only bits return Os when read 11 0 BYTE_COUNT 000h FFFh Number of data bytes to read or write up to 4K bytes This value is used in conjunction with the specified RapidlO address to create the data size and word pointer fields in the RapidlO packet header 158 Serial RapidlO SRIO SPRUE13A September 2006 Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SRIO Registers 5 37 LSUn Control Register 4 LSUn_REG4 There are four of these registers one for each LSU see Table 95 LSUn_REG4 is shown in Figure 98 and described in Table 96 For additional programming see Section 2 3 3 Table 95 LSUn_REG4 Registers and the Associated LSUs
401. x dest VW i mailbox reserved retry_count message_length Table 21 TX Buffer Descriptor Field Definitions Field Description next_descriptor_pointer Next Descriptor Pointer The 32 bit word aligned memory address of the next buffer descriptor in the TX queue This is the mechanism used to reference the next buffer descriptor from the current buffer descriptor If the value of this pointer is zero then the current buffer is the last buffer in the queue The DSP core sets the next_descriptor_pointer buffer_pointer Buffer Pointer The byte aligned memory address of the buffer associated with the buffer descriptor The DSP core sets the buffer_pointer sop 1 Start of Message Indicates that the descriptor buffer is the first buffer in the message e This bit will always be set as this device only supports one buffer per message eop 1 End of Message Indicates that the descriptor buffer is the last buffer in the message e This bit will always be set as this device only supports one buffer per message ownership Ownership Indicates ownership of the message and is valid only on sop This bit is set by the DSP core and cleared by the port when the message has been transmitted The DSP core uses this bit to reclaim buffers 0 The message is owned by the DSP core 1 The message is owned by the port eoq End Of Queue Set by the port to indicate that all messages in the queue have been t
402. x Retry Error Offset 0x14204 SP2_CTL_INDEP 6 92 Serial RapidiO SRIO SPRUE13A September 2006 Submit Documentation Feedback i INSTRUMENTS www ti com 4 4 4 4 1 SPRUE13A September 2006 Interrupt Conditions Table 38 Interrupt Clearing Sequence for Special Event Interrupts continued Interrupt Function 1st Step 2 nd Step 3rd Step Port 3 Error TMS320TCI6482 Only Write 1 to clear Offset 0x0278 ERR_RST_EVNT_ICCR 11 Write 1 to clear any of the Write 1 to clear following possible bits Offset 0x2100 SP3_ERR_STATI2 Fatal error SP3_ERR_STAT 25 Failed Threshold SP3_ERR_STAT 24 Degraded Threshold Offset 0x14304 SP3_CTL_INDEP 20 Illegal Transaction SP3_CTL_INDEP 16 Max Retry Error Offset 0x14304 SP_CTL_INDEPI 6 Write 1 to clear Offset 0x0278 ERR_RST_EVNT_ICCR 16 Device Reset Write 1 to clear Offset 0x12004 SP_IP_MODE 2 Interrupt Condition Routing Registers The interrupt conditions are programmable to select the interrupt output that will be driven Using the interrupt condition routing registers ICRRs software can independently route each interrupt request to any of the interrupt destinations supported by the device For example a quad core device may support four CPU servicing interrupt destinations one per core INTDSTO for CoreO INTDST1 for Coret INTDST2 for Core2 and INTDSTS3 for Core3 In addition INTDST4 may be glob
403. x00000001 LSU_EN SRIO_REGS gt BLK2_EN 0x00000001 MAU_EN SRIO_REGS gt BLK3_EN 0x00000001 TXU_EN SRIO_REGS gt BLK4_EN 0x00000001 RXU_EN SRIO_REGS gt BLK6_EN 0x00000001 PORTI_EN SRIO_REGS gt BLK7_EN 0x00000001 PORT2_EN SRIO_REGS gt BLK8_EN 0x00000001 PORT3_EN 2 3 13 2 PLL Ports Device ID and Data Rate Initializations To change from 1 lane to 4 lanes there are 2 registers that need to be programmed See Table 30 Table 30 Port Mode Register Settings Device SP_IP_MODE offset 0x12004 PER_SET_CNTL offset 0x0020 Port Mode Bits 31 30 Bit 8 TMS320TC16482 0x00 0x00 1x 4p TMS320TC16482 0x01 0x01 1x 1x For example Enable PLL 333MHz 1x 4p srio4p1x_mode 1 x20 125MHz ref clock 2 5 Gbps half rate if srio4plx_mode rdata SRIO_REGS gt PER_SET_CNTL wdata 0x0000014F aplx mask 0x000001FF mdata wdata amp mask rdata amp mask SRIO_REGS gt PER_SET_CNTL mdata enable PLL else wdata 0x0000004F enable PLL 1p4x rdata SRIO_REGS gt PER_SET_CNTL mask 0x000001FF mdata wdata amp mask rdata amp mask SRIO_REGS gt PER_SET_CNTL mdata enable PLL 1p1x 4x INIT_MACO if srio4plx_mode SRIO_REGS gt SP_IP_MODE 0x4400003F Jadis mltc rst pw enable clear else SRIO_REGS gt SP_IP_MODE 0x0400003F Jadis mltc rst pw enable clear SPRUE13A September 2006 Serial RapidlO SRIO 77 Submit
404. y bits return Os when read 7 0 PRESCALE For different frequencies of the DMA clock use the following formula to get the prescaler value in decimal where the DMA clock frequency is in MHz DMA clock frequency x 16 156 25 1 06h 66 67 MHz 09h 100 MHz OFh 156 25 MHz 10h 166 67 MHz 18h 250 MHz 2th 333 MHz SPRUE13A September 2006 Serial RapidlO SRIO 233 Submit Documentation Feedback SRIO Registers 5 94 Port Write In Capture CSRs SP_IP_PW_IN_CAPT 0 3 da TEXAS INSTRUMENTS www ti com Four registers are used to capture the incoming 128 bit payload of a Port Write These four registers are shown in Figure 157 As can be seen in Table 179 each of the registers captures one of the four 32 bit words of the payload Figure 157 Port Write In Capture CSRs Port Write In Capture CSR 0 SP_IP_PW_IN_CAPTO Address Offset 12010h 31 0 PW_CAPTO R 00000000h Port Write In Capture CSR 1 SP_IP_PW_IN_CAPT1 Address Offset 12014h 31 0 PW_CAPT1 R 00000000h Port Write In Capture CSR 0 SP_IP_PW_IN_CAPTO Address Offset 12018h 31 0 PW_CAPT2 R 00000000h Port Write In Capture CSR 0 SP_IP_PW_IN_CAPTO Address Offset 1201Ch 31 0 PW_CAPT3 R 00000000h LEGEND R Read only n Value after reset Table 179 Port Write In Capture CSR Field Descriptions Field Value Description PW_CAPTO 00000000h Word 0 bits 0 to 31 of the Port Write payload to FFFFFFFFh
405. y for packet forwarding 123 node ID field to compare to incoming destination ID 122 node ID field to supply outgoing source ID 121 upper boundary for packet forwarding 123 16 bit node ID field to compare to incoming destination ID 122 to supply outgoing source ID 121 16BNODEID field of DEVICEID_REG1 121 16BNODEID field of DEVICEID_REG2 122 A ACKID_STATUS field of SPn_LM_RESP 201 acknowledge control symbol overdue at port n rate counting enable field 222 status field 220 acknowledge control symbols in SRIO operation sequence 22 acknowledge IDs ackID status field for link response 201 SPRUE13A September 2006 Submit Documentation Feedback Index SPRUE13A September 2006 Index next expected acklD field 202 output port next transmitted ackID field 202 output port unacknowledged acklD status field 202 unexpected ackID in control symbol at port n rate counting enable field 221 Status field 219 unexpected ackID in packet at port n rate counting enable field 222 Status field 220 adaptive equalizer control field 125 ADDR_CAPT 215 ADDRESS_ 31_3 field of ADDR_CAPT 215 ADDRESS_63_32 field of H_ADDR_CAPT 214 ADDRESS_LSB CONFIG_OFFSET field of LSUn_REG1 156 ADDRESS_MSSB field of LSUn_REGO 155 address associated with logical transport error LSBs 215 MSBs 214 address capture CSRs for logical transport errors 214 215 address LSBs for LSUn destination 156 address MSBs for LSUn destination 155 ALIGN field of SERDES_CFGRXn_CNTL
406. zer to compensate for the relatively stable response of the channel e No adaptive equalization The equalizer provides a flat response at the maximum gain This setting may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than frequency dependent loss e Fully adaptive equalization Both the low frequency gain and zero position of the equalizer are determined algorithmically by analysing the data patterns and transition positions in the received data This setting should be used for most applications e Partially adaptive equalisation The low frequency gain of the equalizer is determined algorithmically by analysing the data patterns and transition positions in the received data The zero position is fixed in one of eight zero positions For any given application the optimal setting is a function of the loss characteristics of the channel and the spectral density of the signal as well as the data rate which means it is not possible to identify the best setting by data rate alone although generally speaking the lower the line rate the lower the zero frequency that will be required Figure 10 SERDES Receive Channel Configuration Register n SERDES_CFGRXn_CNTL 26 25 24 23 22 19 18 16 Reserved Reserved write Os EQ CDR R 0 R W 0 R 0 R W 0 R W 0 15 14 13 12 11 10 8 7 6 54 1 0 LOS ALIGN TERM INVPAIR RATE BUSWIDTH ENRX write 001b

Texas Instruments TMS320TCI648x User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents