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Texas Instruments TLV1562 User's Manual

1. 12 Ae Writing tothe ADC 12 7 2 Mono Interrupt Driven Mode Using RD 12 7 3 Mono Interrupt Driven Mode Using CSTART 14 7 4 Dual Interrupt Driven Mode 1 4 2 2 2 2 15 7 5 Mono Continuous Mode 2 16 7 6 Dual Continuous Mode 17 8 Software Overview 22225 2 els ek Re 18 8 1 Software Development tools 18 8 2 DSP Memory Map tasa u fare DD GERE Sendo 18 8 3 Programming Strategies for the C54x Explanations 20 8 3 1 Optimizing CPU Resources for Maximum Data Rates 20 8 3 2 Address and Data Bus for I O Tasks 20 9 39 39 Timer OUIDUEr 1o im Pd rs Ele heal 20 8 3 4 Data Page Polnter i tree E PIE RR A ON RAI Raw pen sia 21 8 3 5 Generating the Chip Select Signal and the CSTART 21 8 3 6 Interfacing the Serial DAC 5618 to the DSP
2. SAVE_INTO_MEMORY 0 S Reset Actual Memory Pointer AR6 7 First Memory Store Location AR7 Data Loc A AR6 Data LOc B Wait 5 6 ADC Clock Cycles __ Started at Time Stamp 1 tc Rp 800 ns With 8 MHz ADC Clock Figure 11 Flow Chart Dual Continuous Mode Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 39 Software Overview 8 5 6 C Callable with Mono Interrupt Driven Mode Using CSTART to Start Conversion 40 The following descriptions explain the software for the data acquisition with a user friendly C program interface in monomode using the CSTART signal The required interface connections are shown in Figure 2 Program Files C1562 ASM Includes the complete software in the C layer asm1562 ASM Includes the complete software algorithm to control the monomode CONSTANT ASM file of all modes constants definition VECTORS ASM Common file of all modes IRQ vector table Other Files linker cmd Organization of the DSP memory data and program memory auto bat Batch file to start the compiler for the monomode software 1500 Compiler c code into assembler mnem2alg exe Mnemonic algebraic instruction converter asm500 exe C54x Code compiler 1nk500 exe C54x linker res Las Library to organize boot loader The timing requirements for interfacing the 54 to the ADC are provided in Table 13 The STEP numbers given there can be found agai
3. 2 2 3 2 Recyclic Architecture 4 3 2 3 8 Note the Interface Using an External ADC Clock 4 2 4 Onboard Components meee askna dhol anes 4 2 4 1 5618 DAC 2 2 4 2 42 TLNV5651 Parallel DAG ertet Ree oe eer eee ec PEE 5 3 Operational Overview 6 3 1 Reference Voltage Inputs u u uy u a ioi pre feed Rhodes haus 6 3 2 Input Data BIS y acre one rp AE eee tied dee aches IE a ete Deore a deem Done Bei e RES 6 3 3 Connections Between the DSP and the 7 3 3 1 Jumpers Used on the TLV1562bEVM 8 The Serial DAC DSP System 9 The DSP SerialPort 2 5 siepe Geta se lie tine eee eda e a BOG E 10 Other DSP TLV1562 11 6 1 DSP Internal Serial Port Operation 11 Conversation Between the TLV1562 and the DSP
4. lt OIT BABATTELZS 1 SEND OUT PARALLEL 1j Store Sample Into Memory Save Sample to AR7 Pointed Location Copy Last Sample to Parallel DAC SEND OUT PARALLEL 1 Table End Reached AR amp ARO Yes Reset Actual Memory Pointer AR amp First Memory Store Location SEND OUT SERIAL 21 Copy Last Sample to Serial DAC SEND OUT SERIAL 0 1 if Send Register is Empty SAVE_INTO_MEMORY 0 aa em L 4 Figure 6 Software Flow of the Mono Interrupt Driven Solution Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 29 Software Overview 8 5 2 Mono Interrupt Driven Mode Using CSTART to Start Conversion 30 The following descriptions explain the software for the data acquisition in monomode using the CSTART signal The required interface connections are shown in Figure 1 Program Files MONOCST1 ASM Includes the complete software algorithm to control the monomode CALIBRAT ASM Calibration procedure of the DAC CONSTANT ASM file of all modes constants definition VECTORS ASM Common file of all modes IRQ vector table Other Files linker cmd Organization of the DSP memory data and program memory auto bat Batch file to start the compiler for the monomode software asm500 exe C54x Code compiler 1nk500 exe C54x linker The timing requirements to interface the C54x to the ADC are provided in Table 8 The
5. if POLLING DRV wait until INT goes low in polling the INTO pin M1 TC bit AR5 15 0 test is the INTO Bit in IFR 1 if NTC goto 1 wait until INT signal went high IFR 1 reset any old interrupt on pin INTO elseif INTO DRIVEN user main program area this could execute additional code go into idle state until the INTO wakes the processor up USER MAIN IDLE 2 the user software could do something else her goto USER MAIN elseif NO INTO SIG instead of using the INT signal the processor waits for 6ADCSYSCLK 49ns and reads then the sampl repeat 32 nop wait for 34 processor cycles endif Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 71 Software Overview read sample STEP2 XE 0 clear CSTART STEP10 CH1_ADSAMPLE port ADC read the new sample into the DSP STEP14 CH2_ADSAMPLE port ADC read the new sample into the DSP STEP3 wait for TW CSTARTL if AUTO PWDN ENABLE wait 800ns before finishing the sampling requirment in Auto power down mode repeat 38 nop wait for 40 clock cycles t APDR 1000ns endif STEP4 XF 1 wait for TW CSTARTL and set CSTART call STORE store the last sample into the table if INTO DRIVEN return return from routine back to IRQ INTO else goto STEPS go back to receive next sample endif lt ck Ck ck ck k k ck kk kk ck k k lt kk
6. 21 8 3 7 Interrupt Eatenocy r Lea he nk Meee ew DESI EN E NGA RUE as 22 8 3 8 Branch Optimization goto dgoto 22 8 3 9 Enabling Software Modules if elseif endif 23 8 4 Software Code Explanation 23 8 4 1 Software Principals of the 23 8 5 Flow Charts and Comments for All Software Modes 27 8 5 1 The Mono Interrupt Driven Mode Using RD to Start Conversion 27 8 5 2 Mono Interrupt Driven Mode Using CSTART to Start Conversion 30 8 5 3 Dual Interrupt Driven 2 2 33 8 5 4 Mono Continuous Mode 36 Interfacing the TLV1562 Parallel AD Converter to the TMS320C54x DSP iii Contents 8 5 5 Dual Continuous Mode 38 8 5 6 C Callable With Mono Interrupt Driven Mode Using CSTART to Start Conversion 40 8 6 SOUrCE COTE eet cede hee M eras nw PR ae A Data n 41 8 6 1 Common Software for all Modes except C Callable 41
7. m tion variabl variabl Address Decoder constants RD CALIBRATION ADC D D EACTIVE set timing mode POLLING DRV INTO DRIVEN NO INTO SIG SAVE INTO MEMORY SEND OUT SERIAL SEND OUT PARALLEL R1OBIT_RESOLU R8BIT RESOLU RABIT RESOLU INTERNAL CLOCK EXTERNAL CLOCK AUTO PWDN ENABLE DIFF INPUT MODE IME CALIBRATIO SME CALIBRATIO sect text SeUt SeUt SS L Set Set BOE BEG set use 00001h 00002h 00003h 00000 od IRQ 00001 00000 00000 variabl variabl variabl variabl variabl variabl n n 00000n 00000 00001h 00001 00000 00000 00001 00000 00000 00000 00000 00000 n n n n n 5 5 1 variabl 1 i 1 1 Software Overview counter for one channel points to act memory save location sent value to register CRO of the ADC sent value to register CR1 of the ADC problem with initialization of this mode when repeated reset the value zero to send a Zero Dummy last read sample from the ADC serial output send word
8. is only for an EVM test in practice the calibration procedure should 9 xecuted when the inputs shorted to the correct voltage and after calibration the analog signal is to apply before doing any further signal conversion the calibration implementation is more or less inserted as an example KKKKKKKKKKKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK x K x x lt x KKK KKK KKK KK KKK if IME CALIBRATION call CALIBRAT INTERNAL MID SCAL endif if SME CALIBRATION Gl call CALIBRAT_SYSTEM_MID_SCALI endif Ck Ck ck ck ck ck ck ck ck k k k KK KKK KKK KKK ck ck KKK ADC_INI set ADC register CRO CR1 ck k k Sk lt k k k k K ck kk k x lt lt lt x ko ko ADC INI write CRI port ADC CR1_SEND Address decoder sets CS low WR low and send CR1 value to the ADC NOP wait for tW CSH 50ns write CRO port ADC 8CRO SEND send CRO value to the ADC 1 port DEACTIVE ZERO deselect ADC CS high STEP2 NOP NOP NOP wait for t SAMPLE1 100ns initialize longer waitstates DP 00000h point to page zero SWWSR 07000h one I O wait states Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 77 Software Overview DP AD_DP j k k ck k k k k k lt k x k Ck ck K ck k k ck lt K k k k lt ck lt lt k k x lt lt lt x ko ADC mono con Start read samp
9. 00 num_da num_da num_da num_da if SEND OUT SERIAL Ck ck ck k ck ck kk k Ck k ck k x Ck x k k k lt lt x k kk K kk k x k Ck KKK ck kk ck k lt k x k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ko KKK ERIAL DAC INI ta loc A ta loc B ta loc C ta loc D 000h ta A 1 ta B 1 1 ta_D 1 Ceo locations of E point to page zero one I O wait which are not critical for the states EVM to the IRQ table location kit but has to be changed on other platforms point to page 1 IRQ vector table copy the NMI vector COPY INTO INT Ly the sampling tabl P fill memory P fill memory P fill memory P fill memory table where th table 1 table 2 table 3 table 4 samples will be stored initialize the serial interface to send out the samples for the serial DAC set up the serial interface for a DSP DAC 561 initialize the SPI interface and the DAC 8A conversation the serial interface will be updated with the last sample if the serial buffer is empty after the last bit has been send KKK k k x KKK k Ck k ck lt x Ck x k k K KKK ck kk KK KKK k k k ck lt x ck kk ck kk Ck x x k k ck kk ck kk KKK Ck ck k x x lt kk K x x ko lt KKK KKK KK BSPI INI 48 DP QBSPC QBSPCI QBSPC endif
10. Generate External Clock v INTO External Interrupt Save Modified Register of The IRQ Routine if Not Automatically Saved by The DSP Data Memory Serial Port Initialize DSP Memory For Sample Store AR7 Points to The First Store Location ARO Points to The Table End ADCOUNT Table Size Number of Samples Not Required r 5 ___ IME CALABRATI ME CAESPRATIONSS pa e eee IME CALABRATION LR IME CALABRATION IMESISEABHATION ES Initialize Id The Two ADC Registers CRO CRO SEND CR1 CR1 SEND Start Sampling Pull Down CSTART Wait 100 ns Stop Sampling and Start Conversion Reset CSTART Set Back High ru 4 INTO DRINEN 1 ri i POLLING_DRIVEN 1 Wait Until End of Conversion Poll INTO Pin Until 0 Transition Occurs muss NO INTO SIGNAL Wait Until End of Conversion Wait For a Certain Time r 7 Start New Sampling Pull Down CSTART Read Both Samples Stop Sampling and Start Conversion Reset CSTART Set Back High SEND_OUT_SERIAL 0 3 Copy Last Sample to Serial DAC if Send Register is Empty LIII zu q SAVE_INTO_MEMORY 1 L 2202 4 Store Sample Into Memory Save Sample to AR7 Pointed Location Table End Reached AR7 ARO SAVE_INTO_MEMORY 0 5 Reset Actual Memory Pointer AR7 7 First Memory Store Location AR7 Data_Loc_A AR6 Data_L
11. interface Program RRR KKK e e KKK k k k k k k K k KKK KKK K k k k k K K K K KOK 7 stack 0x0080 asm1562 MAP asm1562 0UT 0 mb Et su N h asm1562 obj c1562 0bj MEMORY PAGE 0 VECT origin 0200h length 0080h 0400h length 0300h 1900h length 1500h 1800h length 0100h PROG origin PAGE 1 RAMBO origin STAC origin n ECTIONS 92 SLAA040 test Vegctors t data variabl Stack gt PROG PAGE 0 gt VECT PAGE 0 gt RAMBO PAGE 1 gt RAMBO PAGE 1 gt STAC PAGE 1 9 Summary This application report provides several software application examples and recommendations for simplifying the software through modifications to the DSP hardware interface circuit The user can customize any of the number of software routines provided in this document to fit his specific applicaltion 10 References TLV1562 Data Sheet TMS320C54x Fixed Point Digital Signal Processor Data Sheet Literature number SPRSO039B TMS320C54x DSP Algebraic Instruction Set Literature number SPRU179 5320 54 DSP Mnemonic Instruction Set Literature number SPRU172 TMS320C54x DSP CPU and Peripherals Literature number SPRU131D TMS320C54x Optimizing C Compiler Literature number SPRU103B TMS320C54x Assembly Language Tools Literature number SPRU102B TMS320C54x DSKplus DSP Starter Kit Literature number SPRU191 TLV1544 Data Sheet Literatur
12. 01 allow INTO endif enable global interrupt this is even required if no IRQ routine is used by this program because the GoDSP debugger needs to do its backgroud interrupts INTM 0 enable global IRQ initialize storage table for the ADC samples 7 data_loc_A point to first date location of the storage table ARO num data A data loc A ARO points to table end DP AD_DP ADCOUNT num_data_A initialize ADCOUNT with the number of required samples if POLLING DRV AR5 IFR AR5 points to the register only for polling mode endif DP AD DP ZERO 00000 set the dummy send value initialize the send values to set up the two programmable register of the ADC QGCRO SEND 4 CH1 MONO INT SINGLE END CLK INTERNAL NO CALIB OP QCR1 SEND NO SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT CST CONV START change some of the possible modes by variation of the bit setting in the file header this next steps can be erased if the user is running in only one special configuration if R8BIT RESOLUT GCR1 SEND 4 RES 10 clear bit for 10 Bit Resolution GCR1 SEND RES 8 BIT set 8 Bit conversion mode elseif R4BIT_RESOLUT GCR1 SEND 4RES 10 clear bit for 10 Bit Resolution GCR1 SEND RES 4 BIT set 8 Bit conversion mode endif Interfacing the TLV1
13. main TLV1562 Channel Save Memory Start address NUMBER OF SAMPLES 1 1562 1 0x2000 0x0080 P 80h samples of channel 1 will be stored beginning on 2000h TLV1562 2 0x2100 0 0080 80h samples of channel 2 will be stored beginning on 2100h TLV1562 3 0x2200 0 0080 80h samples of channel 3 will be stored beginning on 2200h Assembler Routine to Control the Interface to the ADC ASM1562 asm KKK K k k k k KK KKK k k k KKK KKK KK KKK KKK KKK ck x x x lt KKK x k k KKK k x x KKK KEK KKK KK KKK KKK KKK KK KKK TITHE TLV1562 ADC Interface routine FILE DUALIRQ1 ASM FUNCTION MAIN PROTOTYPE void MAIN CALLS N A PRECONDITION N A POSTCONDITION N A DESCRIPTION main routine to use the mono interrupt driven mode oi and the CSTART signal to CPU power for the conversion time AUTHOR AAP Application Group ICKE Dallas CREATED 1998 BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 Data Aquisation Circuits TI 1998 Kk ck K k k k k ck k ck Ck x k k k ck lt lt ck kk ck ck ck Ck x x k x KKK KKK x kk Ck ck x k x ck kk ck x x K lt lt lt lt x x x x kk x x x Sk lt KKK KKK KK title DUALIRQI mmregs width 80 length 55 version 542 86 SLAA040 Software Overview Setsect vectors 0x0018
14. Advantage e Fastest solution with a fine tune the maximum performance can be extracted from the converter e Saves CPU power of the DSP no time wasted for polling e Program can not hang up in an endless loop Less hardware required input pin on the DSP and INT connection are left out Disadvantage e Every software variation changes timing and therefore requires fine tuning again This can be avoided by using the DSP timer module but since the TLV1562 is an extremely fast device 2 MSPS at 10 bit a timer module solution becomes too slow Ifthe conversion time of the ADC varies for some reasons this algorithm is not able to respond instead the maximum conversion time is used SLAA040 Software Overview 8 4 1 3 Interrupt Driven Solution Usually the most elegant solution is to use an interrupt procedure to control external signals The problem for this application is the high speed First if more than a few words of code have to be executed between two samples the software hasto ensure that the first interrupts will be completed before the second interrupt is enabled This can be done by globally disabling IRQs while executing one IRQ The second problem is the interrupt latency According to the pipeline architecture of the C54x an interrupt routine is started at the earliest after three clock cycles the last instruction in the pipeline will be executed before branching to the IRQ vector Another processing over
15. BSPCE 00521 set Auto buffer mode AXR BSPC_BUFFER_START set the starting address of the auto buffer BKX BSPC_BUFFER_SIZE buffer size BSPC 0C07Ch start serial port FSX in Burst every word Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 21 Software Overview 8 3 7 Interrupt Latency The time required to execute an interrupt depends on the handling of the IRQ at the four word vector address or jumping further with a GOTO instruction Using the fast return from IRQ instruction and branching from the IRQ vector to a separate routine memory location produces an IRQ overhead of 3 sysclk goto IRQ vector 4sysclk goto dgoto 1 sysclk fast return 8 instruction cycles The time between when the IRQ occurs and the routine executes its first instruction depends on the instruction in the CPU pipeline when the interrupt occurs Running a repeat command delays the IRQ until the full number of repetitions is finished NOTE Using a delayed branch instruction dgoto and putting two useful words of instruction behind this instruction saves the CPU calculation power See the explanations about delayed branches Section 8 3 8 8 3 8 Branch Optimization goto dgoto call dcall 22 The easiest solution for a branch is to use the goto instruction Since the C54x has a pipeline to allow execution of one instruction in one clock cycle a simple branch instruction will take four cycles for executio
16. Table 9 DSP Algorithm for Dual Interrupt Driven Mode Wait cycles for the DSP internally 40 2 DSPCLK STEPS TIMING NOTES Set CS Deselect ADC 1 2 3 Wait for tw csrARTL tw csrARTL 100ns APD 0 tw csTaRTL 600ns APD 1 4 5 Wait until INT goes low Alternative ignore the INT signal wait 210ns 10 ADCSYSCLK and go to step number 7 I MN reset RD signal 1 1 Read sample out from the data port reset RD signal 0 2 3 Wait the time teN pATAOUT tEN DATAOUT 41 ns 4 5 1 Set CS Deselect ADC 16 Goto step 2 for the next samples 5 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 15 Conversation Between the TLV1562 and the DSP 7 5 Mono Continuous Mode This mode simplifies data acquisition since there is no need to generate a signal to sample or convert data Instead initializing this mode once the ADC sends out the data continuously and will be read by the DSP with the RD signal CAUTION In this mode the sampling result sent out by the ADC is the value of the sample from the last cycle Therefore the first sample after initialization is trash Table 10 DSP Algorithm for Mono Continuous Mode Wait cycles for the DSP internally 40 2 DSPCLK STEPS TIMING NOTES APD 0 APD 0 APD 1 APD 1 ADCSYCLK ADCSYCLK ADCSYCLK ADCSYCLK 7 5 MHz 10 MHz 10 MHz 10 MHz Initialization N A N A Write all configuration data to the Activate the mono continuous mode in N
17. Use as single input channel 2 or differential input negative channel An external clock source drives the SCLK pin instead of the DSP An external clock source drives the CLK pin instead of the DSP XF signal connects to CSTART pin RD pin driven by IOSTRB ORed with R W JUMPER Table 3 2 Position Jumpers GENERAL DESCRIPTION PINS SHORTED PINS OPEN W16 Connects Mode input TLV 5651 to GND Connects REFIO TLV5651 to VREF1 or leaves the REFIO pin decoupled to GND via a 0 1 uF capacitor MODE 0 is chosen binary data input Use as external reference voltage input MODE 1 is chosen 2s complement data input Use as internal reference voltage output with this pin terminated into GND in series with 0 1 pF Connects DIR U19 to GND or leaves the DIR pin connected to WR Connects OE U19 to GND or leaves the OE pin connected to CS ADC can only write but not read to the data bus Output driver is isolated and disabled no signal can bus trough the data bus Normal operation mode Normal operation mode Connects BDX to BDR or leaves BDR open Connects BSFX to BSFR or leaves BCLKR open DSP BDR pin gets a shortcuted feedback from the BDX transmit pin normal mode DSP BSFR pin gets a shortcuted feedback BDR remains open BSFR remains open from the BSFX transmit pin normal mode W28 Connects BCLKX backwards with BCLKR or leaves it open Connect Sleep input TL
18. if INTO DRIVEN POLLING DRV SERIAL DAC INI 0 00 00 0C SLAA040 038h 101 078h reset SPI set clock speed start serial port no Autobuffer Mode Software Overview reset pending IRQs IFR 1 reset any old interrupt pin INTO endif if INTO DRIVEN enable Interrupt INTO IMR 01 allow INTO endif enable global interrupt this is required even if no IRQ routine is used by this program because the GoDSP debugger needs to do its backgroud interrupts INTM 0 enable global IRQ initialize storage table for the ADC samples AR7 data_loc_A point to first date location of the storage table ARO num_data_Atdata_loc_A ARO points to table end DP AD_DP ADCOUNT num data A initialize ADCOUNT with the number of required samples if POLLING DRV AR5 IFR AR5 points to the IFR register only for polling mode endif DP DP ZERO 00000 set the dummy send value initialize the send values to set up the two programmable register of the ADC CRO_SEND CH1 MONO_INT SINGLE_END CLK_INTERNAL NO_CALIB_OP CR1_SEND NO_SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START change some of the possible modes by variation of the bit setting in the file header this next steps can be erased if the user is running in only one special configuration if
19. AR7 AR7 ARO table end reached if NTC goto STORE_END set pointer back to table start AR7 data_loc_A point to first date location of the storage table AR6 d data loc B point to first date location of the storage table endif STORE END RETURN jump back into data aquisition routine Ck Ck ck ck Ck lt KKK k k KKK k k k KKK KKK k k x ck lt x x k x kk ck kk x kk ck kk x x x lt x K x x KKK KKK KK x lt lt IRQ_INTO Interrupt routine of the external interrupt input pin INTO KKK KKK KKK k k x KK k k k x x K K x x k k lt KKK x x x KEK KKK KKK KKK KKK KK KKK KKK KKK KK x lt lt IRQ INTO call STEP2 initialize the next conversion and store results return_enable return from IRQ wake up from the IDLE mode Ck Ck ck ck KKK KKK KK KK k k k KKK KKK k k x KK KKK KKK KKK k k x KK K k k x x x ck x x KKK KKK KKK KKK KK KKK KKK KKK BXINTO Interrupt routine of the serial transmit interrupt of the buffered SPI KKK KKK KKK KKK k x K KKK k k k KKK KK KKK KKK KKK KKK KKK KKK KKK x lt x k k x lt lt lt k x x KKK x x x KKK KK KKK BXINTO return_enable interrupt is not in use Sect text calibrat asm end Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 73 Software Overview Constants definition see 8 6 1 1 Constants asm Interrupt Routine handler see 8 6 1 2 Interrupt Vectors 8 6 6 Mono Continuous Mode Mai
20. AUTO PWDN deselect select the ADC with cs requirment in Auto power down mode TEMP port DEACTIVE deselect ADC TEMP port ADC activate ADC CS again repeat 18 nop wait for 20 clock cycles t APDR 500ns endif XF 0 clear RD step 4 call STORE handle storing of the samples into memory and serail DAC if INTO DRIVEN return return from routine back to IRQ INTO else goto STEPS go back to receive next sample endif Ck Ck ck ck lt K k kk k kk lt kk Ck k x kk Sk x x k ko ko KK lt k x KKK STORE Gl saving the samples into memory ck k Ck ck k k KKK KKK KKK lt k k x ck lt lt ck x k KKK KKK KK STORE if SAVE INTO MEMORY store new sample into DSP data memory AR7 data QADSAMPLE write last sample into memory table endif if SEND OUT SERIAL store sample into the serial buffer location Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 51 Software Overview DP 00000h point to page zero TC bitf SPC 01000h test is the XRDY Bit in SPC 1 if TC goto SEND SERIAL END don t send something until XDR is empty this has been included because the serial DAC TLC5618A is not able to understand endless data streem the CS should not become high before end of sending the 16th bit DP AD_DP reset Data page pointer to variables A ADSAMPLE l
21. BSPI INI DP BSPC BSPCI C3 BSPC endif ERIAL DAC INI 0 00038h 00101 0C078h if INTO DRIVEN POLLING DRV reset pen IFR endif ding IRQs 1 if INTO DRIVEN enable In terrupt INTO Software Overview reset SPI set clock speed no Autobuffer Mode start serial port reset any old interrupt on pin INTO if no IRQ routine is used this program because the GoDSP debugger needs to do its backgroud interrupts enable global IRQ point to first date location of the storage table ARO points to table end DP 0 IMR 01 allow INTO endif enable global interrupt this is even required by INTM 0 initialize storage table for the ADC samples AR7 data loc A ARO num_data_At data_loc_A DP AD_DP ADCOUNT num A E if POLLING DRV AR5 endif DP ZE RO IFR AD_DP 00000 initialize ADCOUNT with th number of required samples AR5 points to the IFR register only for polling mode set the dummy send value initialize the send values to set up the two programmable register of the ADC Dy CRO_SI CR1_SEND change so this next ND CH1 MONO_INT SINGL me of the possible modes steps can be erased if if R8BIT RESOLUT QCR1 SEND 10 BIT QCR1 SEND RES 8 BIT Interfacing the TLV1562 Parallel ADC to the TMS320C54x D
22. R8BIT RESOLUT QCR1 SEND RES 10 clear bit for 10 Bit Resolution GCR1 SEND RES_8 BIT set 8 Bit conversion mode elseif 4 RESOLUT QGCR1 SEND 10 BIT clear bit for 10 Bit Resolution 8 1 SEND RES_4 BIT set 8 Bit conversion mode endif if EXTERNAL CLOCK GCRO SEND CLK_INTERNAL clear CLK INTERNAL bit if one QCRO SEND CLK_EXTERNAL set CLK EXTERNAL mode endif Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 49 Software Overview if AUTO PWDN ENABLE 1 SEND 4NO AUTO PWDN clear NO AUTO PWDN bit if one GCR1 SEND AUTO_PWDN set AUTO PWDN mode endif if DIFF INPUT MODE QGCRO SEND SINGLE END clear single ended input bit if one GCRO SEND DIFFERENTIAL set differential input mode endif kk ck ck ck ck kk ck lt ck ck k K x ck KK KKK ck lt lt KKK ADC INI set ADC register CRO CR1 KKK k k k KKK KKK KK KKK KKK KKK ck ck ck KK ADC INI write CRI port ADC CR1_SEND Address decoder sets CS low WR low and send CR1 value to the ADC port DEACTIVE ZERO deselect ADC CShigh NOP wait for tW CSH 50ns write CRO port ADC QCRO SEND send CRO value to the ADC port DEACTIVE ZERO deselect ADC CShigh NOP wait for tW CSH 50ns kk ck Ck ck k k k k lt k Ck Sk k k
23. set the dummy send value initialize the send values to set up the two programmable register of the ADC QGCRO SEND CH1 MONO_CONTINUOUS SINGLE_END CLK_INTERNAL NO_CALIB_OP CR1_SEND NO_SW_PWDN NO_AUTO_PWDN 2 NO_DEBUG RES_10_BIT RD_CONV_START change some of the possible modes by variation of the bit setting in the file header this next step can be erased if the user is running in only one special configuration 1 R8BIT_RESOLUT QCR1 SEND RES_10_BIT clear bit for 10 Bit Resolution 1 SEND RES 8 BIT set 8 Bit conversion mode elseif RESOLUT 1 SEND 4RES 10 BIT clear bit for 10 Bit Resolution 76 SLAA040 Software Overview GCR1 SEND RES_4 BIT set 8 Bit conversion mode endif if EXTERNAL CLOCK QCRO SEND 4CLK INTERNAL clear CLK INTERNAL bit if one GCRO SEND CLK_EXTERNAL set CLK EXTERNAL mode endif if DIFF INPUT MODE GCRO SEND SINGLE END clear single ended input bit if one GCRO SEND DIFFERENTIAL set differential input mode endif Ck Ck ck ck ck K ck k x k k x lt Sk k k k ck Ck ck Ck k k lt KK x x x KKK KKK k x x ck kk k k x KK KKK ck kk lt kk x x x ko lt lt x x x x ko KKK ko ko KKK Calibration do a calibration of the input if chosen the location of this instruction
24. variabl 1 Address Decoder constants ADC set 00002h CSTART set 00001 DAC1 set 00003h DEACTIVE 00000h 7 Software Overview the last value sent to register CRO the last value sent to register 1 problem with initialization of this mode when repeated reset the value zero to send temporary variable memory location to save AR7 during interrupts last read sample of channel 1 last read sample of channel 2 activate AO when TLV1562 is choosen activate Al when CSTART is choosen activate A2 when 1 is choosen deactivate the address lines AO Al and A2 set timing mode use od IRQ or timer POLLING_DRV set 00001h INTO_DRIVEN set 00000h NO_INT0_SIG set 00000h SAVE INTO MEMORY set 00001h SEND OUT SERIAL set 00000n SEND OUT PARALLEL set 00001h 10 RESOLUT set 00001 R8BIT_RESOLU set 00000 R4BIT_RESOLU set 00000 INTERNAL CLOCK set 00001 EXTERNAL CLOCK set 00000 pez AUTO_PWDN_ENABLE set 00000 DIFF_INPUT_MODE set 00000 IME CALIBRATION set 00000h SME CALIBRATION set 00000 sect text IAIN START INITIALIZATION disable IRQ sign extension mode software polls the INTO pin to wait until conversion is done software uses Interrupt INTO to wait for
25. 6 ADC SYSCLk Go to step 4 for more samples TIMING NOTES Activate the dual continuous mode in CRO 2 3 deselect ADC tisaupLE 100 ns Select ADC Start conversion tEN DATAOUT 41 ns Caution the first result after initialization is trash 5 6 ADCSysclk since step 7 and 8 take at least 4 DSPSYSCLK the calculation are 5 6 ADCSYSCLK minus 100 ns Start conversion tEN DATAOUT 41 ns Caution the first result after initialization is trash t conv1 5 6 ADCSysclk since step 7 and 8 take at least 4 DSPSYSCLK the calculation are 5 6 ADCSYSCLK minus 100ns APD 0 APD 0 APD 1 APD 1 ADCSYCLK ADCSYCLK ADCSYCLK ADCSYCLK 7 5 MHz 10 MHz 10 MHz 10 MHz N A N A N A N A N A N A 24 24 N A N A N A N A 22 22 N A N A N A N A 223 216 N A N A 22 22 N A N A N A N A 223 216 N A N A N A N A 17 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP Software Overview 8 Software Overview 8 1 The software in this report shows how to use all modes of the TLV1562 and useful variations for each mode It also includes a C program to start data acquisition from a C level To limit the number of programs the report supplies five files for running the ADC in five modes a sixth program shows the C callable function Each program can enable different software blocks to give the user a large choice for generating the data acquisition For more details see paragraph 8 3 9 Instead of using
26. 8 6 2 Mono Mode Interrupt Driven Software Using RD to Start Conversion 46 8 6 3 Calibration of the 53 8 6 4 Mono Mode Interrupt Driven Software Using CSTART to Start Conversion 58 8 6 5 Dual Interrupt Driven 66 8 6 6 Mono Continuous Mode 1 7 74 8 6 7 Dual Continuous Mode 80 8 86 8 G Gallable uu ree ea edes EAUX Sand ata eT pet d Wh eee 86 9 S mmafy uta s Po UI X DOCU MILITE 93 Heferences 5 oro ex Ie kiasa ee ere ee 93 iv SLAA040 Figures List of Figures 1 TLV1562 DSP Interface of the EVM Using RD or the CSTART Signal to Start Conversion 2 2 TLV1562 DSP Interface of the EVM Using RD or the CSTART Signal to Start Conversion 3 3 TEC5618 DSP Interface ee root et Dese d tee waned Dodo done 5 4 TLC5651 DSP Interface 21 2 2 5 5 Memory Map u regia dno Ae pereo Oe 19 6 Software Flow of the Mono Interrupt Driven Solution 29 7 Flow Chart Mono Interrupt
27. A N A ADC CRO 2 3 ET sc w CSI s s a ee 6 Read sample out from the data port Umm fe first result after initialization reset RD signal is trash 7 for the time t conv1 minus t CONV1 6 ADCSYSCLK since step 223 step 7 and 8 to ensure 5 6 ADC 7 and 8 least 4 DSPSYSCLK the SYSCLk calculation are 5 6 ADCSYSCLK minus 100 ns 16 SLAA040 7 6 Dual Continuous Mode Slap Py o si gt 10 11 12 The dual continuous mode provides a data stream of two input signals The Conversation Between the TLV1562 and the DSP characteristic of the data protocol is similar to the mono continuous mode but with the use of two RD cycles for one sample hold cycle In this mode the sampling result sent out by the ADC is the value of the sample from the last cycle Therefore the first CAUTION sample after initialization is trash Table 11 DSP Algorithm for Dual Continuous Mode Wait cycles for the DSP internally 40 2 DSPCLK STEPS Initialization Write all configuration data to the ADC Set CS Wait for t samPLet Clear CS Clear RD Wait the time tEN DATAOUT Read first sample out from the data port reset RD signal Wait for the time t conv1 minus step 7 and 8 to ensure 5 6 ADC SYSCLk Clear RD Wait the time tEN pATAOUT Read second sample out from the data port reset RD signal Wait for the time t conv1 minus step 7 and 8 to ensure 5
28. ICKE Dallas Freising CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED x REFERENCE TMS320C54x Assembly Language Tools TI 1997 i TMS320C54x DSKPlus User s Guide TI 1997 Data Aquisation Circuits TI 1998 Ck Ck ck ck K K ck Ck ck k k ck lt Sk KKK k x K ck Ck x k k KKK KKK k x lt ck x x k k x ck kk Ck x x kk ck x x k k x ko kk x x x KK KK KKK KKK x x x x lt x lt ck Ck ck k k lt lt kk k k x x x K x x k k lt lt x x x lt lt SEND WORDS FOR THE ADC TLV1562 ee k k k k k k k K k K k K k K K INDEX MODE 0 CH1 set 00000h Channel selection is Channel 1 CH2 set 00001h Channel selection is Channel 2 CH3 set 00002h Channel selection is Channel 3 CHA set 00003h Channel selection is Channel 4 PAIR A set 00000h Channel selection is Pair A PAIR B set 00003h Channel selection is Pair B MONO INT set 00000h Conversion mode selection is Mono Interrupt DUAL INT set 00004h Conversion mode selection is Dual Interrupt MONO CONTINUOUS set 00008h Conversion mode selection is Mono Continuous DUAL CONTINUOUS set 0000Ch Conversion mode selection is Dual Continuous SINGLE END set 00000h Input type is Single Ended DIFFERENTIAL set 00010h Input type is Differential CLK INTERNAL set 00000h Conversion clock selection is Internal CLK EXTERNAL set 00020h Conversion clock selection i
29. STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code IMPORTANT NOTE The code has been optimized during the software development to maximize the data throughput It was found that CSTART can be pulled down earlier than the data read instruction is performed by the DSP The advantage is to save the 100 ns wait time in STEP 6 because the data read requires at least 100 ns Therefore CSTART gets pulled back high directly after data read and the interface becomes faster and gains throughput This variation will be found in the code the data acquisition software contains a small number of steps and everything is explained in the code Code verification To verify the software the user must change the code in the MONCST1 ASM file and save those changes The next step is to recompile the four ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages the new output file is ready to load in the DSP program memory e g with the GoDSP development tools and to execute The flowchart in Figure 8 gives a general overview of the software structure MONOCST1 ASM SLAA040 Software Overview was Initialize DSP No Er Wait States AR Pointer IRQ Table Data Memory Serial Port L lt Transition on INTO gt gt T T eT Initialize SP Yes Active Transmitter Use Frame Sync Generate Externa
30. SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used 5 publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated Contents 1 Introd ctiom 2 52 Il iw 1 2 eee 1 2 1 TMS320C54x Starter 1 2 2 TEVA562EVM ua Am Qa pega u an p EGRE ORE e PRICE ale CE EU Ra 2 253 ADC ATEVAS62 OVERVIEW ea dd a aan ods RD earn Rut Rd 2 2 31 Suggestions for the C54x to TLV1562 Interface
31. chip DARAM 10k words OVLY 1 from 0080h to 27FFh SLAA040 Software Overview 0000h OVLY 1 007Fh 0080h Original Interrupts DSKplus OOFFh Starter Kit 017Fh Starter Kit 180h 0800h OFFFh BSP RAM Block or Program RAM 1000h 1009h 100Ah 17FFh 1800h 27FFh 2800h EFFFh F000h F7FFh F800h FF7Fh FF80h FFFFh Reserved Memory by DSKplus Board 0000h Memory Mapped Register 005Fh 0060h Scratch Pad RAM 007Fh ei DRAN Soe Program emery DRAM See Program Memory K data_log_A 27FFh gt Table 1 1800h Software Data Memory E loc A num data A 4FFFh All Variables Que data loc B 2 2000h data loc B num data STER Tables to Store Data Samples data loc C Table 3 Hn omm s i aa m dataloc D FFFFh Table 4 A data loc D num data D Figure 5 Memory Map Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 19 Software Overview 8 3 Programming Strategies for the C54x Explanations Before listing the program code this chapter introduces some basic instructions strategies to provide the C54x user with some ideas for dealing with the DSP architecture 8 3 1 Optimizing CPU Resources for Maximum Data Rates The C54x processor on the DSKplus starter kit runs at an internal clock frequency of 40 MHz Since the pipeline architecture allows most instructions to be executed in one cycle the DSP provides up to 40 MIPS However
32. end of conversion INTO signal not in use timing solution store the samples into DSP memory store the last sample allways into serial buffer memory store the last sample allways into DACI use maximum resolution of 10 bit use 8 Bit resolution use fastest mode 4 Bit resolution use the internal clock of the ADC use the external clock of the ADC ADC goes into power reduced state after conversion use differential mode instead of single ended inputs do an Internal Midscale Error Calibration do a System Midscale Error Calibration ini Stack Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 67 Software Overview clear all memory locations INTM 1 SXM zu SP 0 280h initialize waitstates DP 00 SWWSR 000h 01000h copy interrupt routine this is required for the DSKplus kit but has to be c DP 1 AR7 0 repeat 3h data 0084h AR7 0 repeat 35 data 00COh DP TEMP repeat num_data_A 1 GTI 0200h ART 0240h ART AD_DP 00000h data data loc A repeat fnum data B 1 data data loc B repeat num_data_C 1 data data loc C repeat data D 1 data data loc D if SEND OUT SERIAL Ck ck ck kk ck kk k Ck k ck k lt Ck x k k k KKK KKK KK KKK k Ck ck kk ck x x K x lt k x K k k ck kk k k k k k k k k k k k k k k k k k k k k k k k k k K
33. kk x K x ck ck x x x x ck ck kk STORE saving the samples into memory Dk k ck Ck Ck Ck k k K ck k k k k lt lt kk k k x lt kx x x k x ko x x STORE 1 SEND OUT PARALLEL store sample into the parallel buffer location if chosen port DAC1 CH1_ADSAMPLE update DAC output with sample one endif if SAVE INTO MEMORY store new sample into DSP data memory AR7 data QCH1 ADSAMPLE write last sample of channel 1 into memory table AR6 endif if SEND OUT SERIAL data QCH2 ADSAMPLE write last sample of channel 2 into memory table store sample into the serial buffer location DP 00000h point to page zero TC bitf SPC 01000h test is the XRDY Bit in SPC 1 if TC goto SEND SERIAL END don t send something until XDR is empty this has been included because the serial DAC TLC5618A isn t able to understand endless data stream the CS should not become high before end of sending the 16th bit DP AD_DP reset Data page pointer to variables A ADSAMPLE lt lt 2 leftshift of the sample for 12 bit format ADSAMPLE A z 72 SLAA040 Software Overview ADSAMPLE TLC5618_LATCH_A TLC5618_FAST_MODE TLC5618_POWER_UP set the mode of th DAC data BDXR ADSAMPLE send out the sample to the serial DAC SEND SERIAL END endif test for table end set pointer back if true if SAVE INTO MEMORY TC ARO
34. l O wait state is required for write operations to the ADC The read sequence from the ADC does not require any wait states because the RD signal is generated with XF TLV1562 TMS320C54x 10 Decoder 4 11 A1 XF IOSTRB a f R W 1 x CLOCKOUT D 0 9 Figure 1 TLV1562 to C54x DSP Interface of the EVM Using RD or the CSTART Signal to Start Conversion SLAA040 2 3 1 2 Simplification of Software Requirements Through Modified Interface Of all the TLV1562 modes of operation only the mono interrupt driven mode uses the RD signal to start the conversion This requires a very flexible handling of the read signal and therefore has to be performed by a general purpose output signal If the application excludes using the RD signal to start the conversion using CSTART instead The TLV1562 RD input signal can be generated with an OR gate whose inputs are driven by IOSTRB and R W signals from the DSP see Figure 2 Using these connections saves the programming steps of setting resetting RD with the XF signal Another advantage is having XF available to control the CSTART signal This saves busy times on the address bus in Figure 1 CSTART was generated through 0 1 and simplifies the software code CAUTION The time ten DATAOUT between the RD high to low transition generated by the DSP and the arrival of valid ADC output data on the data bus is related to the capacitive load of the bus In mos
35. repeat 35 data 00COh AR7 copy INTO clear all memory locations of the sampling tabl table where the samples will be stored DP AD_DP TEMP 00000h 2 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 81 Software Overview repeat num_data_A 1 data data_loc_A TEMP fill memory table 1 repeat num_data_B 1 data data_loc_B TEMP fill memory table 2 repeat num data C 1 data data loc C TEMP fill memory table 3 repeat data D 1 data data loc D TEMP fill memory table 4 if SEND OUT SERIAL kk ck Ck k k k k ck lt k Ck x k k k KKK k k x KK KKK x k x KKK k x x KK KKK k k x KKK ck x k x kk K x x k lt lt lt lt k kk ck lt lt Sk x x x KKK KKK initial set up initial the ser ize the ize ial ERIAL DAC INI the serial interface to send out the samples for the serial DAC serial interface for a DSP DAC 5618A conversation the SPI interface and the DAC interface will be updated with the last sample if the serial buffer is empty after the last bit has been sent KKK k k x KKK k k x ck lt lt Ck Sk k k k KKK ck kk ck kk Ck x k k k ck kk ck kk ck kk Ck x k kk ck kk ck kk KKK K x k kk x lt lt k x x k k k k k k k k KK BSPI_INI DP BSPC BSPCE E BSPC endif SERIAL DAC INI 0 00038h reset SPI 00101h set clock speed no A
36. serial port operation section discusses the registers The six signals are BCLKX The serial transmit clock This signal clocks the transmitted data from the BDX terminal to the DIN terminal of the TLC5618A e BCLKR The serial receive clock This signal clocks data into the DSP BDR terminal Since the DAC does not send any information back to the DSP this signal is not important BDX Data transmit From this terminal the DSP transmits 16 bit data to the DIN terminal of the TLC5618A BDR Data receive not in use BFSX Frame sync transmit This signal frames the transmit data The DSP begins to transmit data from BDX on the falling edge of BFSX and continues to transmit data for the next 16 clock cycles from the BCLKX terminal The BFSX signal is applied to the TLC5618A CS terminal BFSR Frame sync receive This signal frames the receive data The DSP begins to receive data on the falling edge of BFSR and continues to recognize valid data for the following 16 clocks from BCLKR This signal is not important for this application Table 5 lists the serial port pins and registers Table 5 DSP Serial Port Signals and Registers mms DESCRIPTION REGISTERS DESCRIPTION For this application the DSP buffered serial port is programmed as the master so the BCLKX output is fed to the BCLKR terminal and the BFSX output is fed to the BFSR terminal SLAA040 Other DSP TLV1562 Signals 6 Other DSP TLV1562 Signals
37. wait for tW CSH 50ns write CRO port ADC CRO_SEND send CRO value to the ADC STEP1 port DEACTIVE ZERO deselect ADC CS high STEP2 NOP NOP f NOP wait for t SAMPLE1 100ns initialize longer waitstates DP 00000h point to page zero Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 83 Software Overview SWWSR 07000h one I O wait states DP AD_DP KKK k k ck KKK x k k KKK KKK KKK KKK KKK KKK KKK x x lt KKK KK ADC_dual_con_Start read samples and store them into memory KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK ck ck ck ck ck ck ck ck KKK ADC dual con Start repeat 12 NOP wait for t SAMPLES 450ns n E EP6 CH1_ADSAMPLE port ADC read the new sample into the DSP n EP7 repeat 20 NOP wait for t CONV1 about 800ns EP10 CH2_ADSAMPLE port ADC read the new sample into the DSP 0 E E PORTANT fine tune the counter number of the next repeat loop order t to achive maximum throughput related to the delay of the store instructions 6 11 repeat 7 wait for t CONV1 about 800ns EP12 call STOR 6 store the last sample into the table goto STEP6 go back to receive next sample KKK KKK k k k k KKK k k k KKK KKK KKK KKK KKK kk ck STORE saving the samples into memory KKK KK k k k KK KKK k
38. x ck kk Ck k x kk K x x k lt ko kc KK KK x lt lt STORE FS saving the samples into memory x lt k ck Ck x k k K K kk k k x lt x lt x x k lt x KK x x x KKK STORE store new sample into DSP data memory AR7 data QADSAMPLE write last sample into memory table test for table end set pointer back if true TC ARO AR7 is ARO AR7 table end reached if NTC goto STORE_END finish conversion CPL 1 do stack pointer addressing 7 restore AR7 AR6 pop z restore AR6 A 0 clear ACCU RETURN jump back to C layer STORE END goto STEPS go back to receive next sample Ck Ck ck ck x k ck Ck x k k x lt Sk k k k x x K ck Ck x k kk ck kk Ck k x lt kk Ck x x kk ck kk x k x kk Sk lt x x x lt k lt KKK x lt lt IRQ INTO Interrupt routine of the external interrupt input pin INTO Ck Ck ck ck K K ck Ck x k k x KKK k k x KKK x x k k lt lt lt x x x KKK KKK x x x KKK k x x lt lt lt x x k x lt k ko x x x KKK IRO INTO return enable return from IRQ wake up from the IDLE mode Ck Ck ck ck k k x lt ck K k k KKK KKK k k KKK KKK KKK KKK k k x ck kk x x x kk ck x x k kk lt kk x x x kk x x x x KK KKK KKK BXINTO Interrupt routine of the serial transmit interrupt of the buffered SPI KKK KKK KKK k k x KK k k k KKK KKK k k KKK KKK KKK KKK x k lt KKK x k x KKK x x KKK KKK KKK K
39. 0 0 sections of code i Setsect text 0x00200 0 these assembler directives specify i Setsect data 0x01800 1 the absolute addresses of different Setsect variabl 0x01800 1 sections of code m sect vectors copy vectors asm sect data copy constant asm AD DP usect variabl 0 ACT CHANNEL usect variabl 1 jump address to init new channel ADWORD usect variabl 1 send bytes to the ADC ADCOUNT usect variabl 1 counter for one channel ADMEM usect variabl 1 points to act memory save location CH NO usect variabl 1 channel number 1 to 4 CRO SEND usect variabl 1 the last value sent to register CRO CR1 SEND usect variabl 1 the last value sent to register CR PROBLEM usect variabl 1 problem with initialization of this mode when repeated reset ZERO usect variabl 1 the value zero to send TEMP usect variabl 1 temporary variable isr save usect variabl 1 memory location to save AR7 during interrupts ADSAMPLE usect variabl 1 last read sample Address Decoder constants ADC set 00002 activate A0 when TLV1562 is choosen CSTART set 00001 activate A1 when CSTART is choosen DAC1 set 00003 activate A2 when DAC1 is choosen DEACTIVE set 00000h deactivate the address lines AO Al and 2 def TLV1562 sect texts START INITIALIZATION _TLV1562
40. 10 28 D5 D6 JP3 14 10 25 D6 D7 JP3 18 1 10 27 D7 D8 JP3 17 J10 29 D8 D9 JP3 21 J10 31 D9 Serial Interface to the DAC TLC5618A BCLKR JP1 14 J11 25 SCLK BCLKX JP1 17 J11 23 SCLK BFSR JP1 20 J11 21 cs BFSX JP1 23 cs BDR JP1 26 DIN BDX JP1 29 J11 15 DIN Signals D 9 0 of the TLV1562 and D 9 0 of the DSP are tied together in this application to simplify hardware debugging during the development phase However if the 2s complement feature of the DAC is to be used it is easier to connect D 15 6 of the DSP with D 9 0 of the ADC A simple right shift of the result then evaluates the result when sign extension mode SXM is enabled Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 7 Operational Overview 3 3 1 Jumpers Used on the TLV1562EVM JUMPER Table 2 3 Position Jumpers GENERAL DESCRIPTION PIN 2 3 W1 Connects BP CH3 ADC to R45 or GND Connects BM CH4 ADC to R44 or GND Input not in use grounded to reduce noise Use as single input channel3 or differential input positive channel B Input not in use grounded to reduce noise Use as single input channel4 or differential input negative channel Connects RD to XF or RD1 WR WRT is connected with DSP_WR or U12 J9 3 Logic generator is connected to the ADC DSP is connected to the ADC Logic generator is connected to the ADC DSP is connected to th
41. 562 Parallel ADC to the TMS320C54x DSP 69 Software Overview if EXTERNAL CLOCK QGCRO SEND CLK INTERNAL clear INTERNAL bit if GCRO SEND CLK_EXTERNAL set EXTERNAL mode endif if AUTO PWDN ENABLE QGCR1 SEND NO AUTO PWDN clear NO AUTO PWDN bit if CR1_SEND AUTO_PWDN set AUTO PWDN mode endif if DIFF INPUT MODE QGCRO SEND SINGLE END clear single ended input bit if one I SEND DIFFER endif NTIAL set differential input mode Ck ck ck Ck ck kk ck ck Se se qe Sk Ck ck kk Sk ck ck S Sak ck ck se qe Sk kk ke ase sk ck kk ck ck ck kk Sk e KKK kk KKK ko Sk ko ko ko ko ko ko ko ko ko kck kok ok Calibration do a calibration of the input if choosen the location of this instruction is only for an EVM test in practice the calibration procedure should xecuted when the inputs shorted to the correct voltage and after calibration the analog signal is to apply before doing any further signal conversion the calibration implementation is more or less inserted as an example KKK KKK k k KK KKK k k x KKK KKK KK KKK KKK KKK k x x KKK KKK k x lt KKK x KKK KKK x x x KKK KKK KKK KKK ko ko kc KKK 1 IME_CALIBRATION call CALIBRAT_INTERNAL_MID_SCAL endif if SME CALIBRATION call CALIBRAT SYSTEM MID SCALE endif KKK KK KKK KK
42. ADC Clock Cycles L Started at Time Stamp 1 tc RD 800 ns With 8 MHz ADC Clock Figure 10 Flow Chart Mono Continuous Mode Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 37 Software Overview 8 5 5 Dual Continuous Mode The following descriptions explain the software for data acquisition in dual continuous mode The required interface connections are shown in Figure 2 38 Program DUALCON1 CALIBRAT CONSTANT VECTORS Files 5 5 5 5 Other Files linker cmd auto bat asm500 e lnk500 e xe xe Includes the complete software algorithm to control the Dual Continuous Mode Calibration procedure of the DAC Common file of all modes constants definition Common file of all modes IRQ vector table Organization of the DSP memory data and program memory Batch file to start the compiler for the dual continuous software C54x Code compiler C54x linker The timing requirements to interface the C54x to the ADC are provided in Table 12 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Code verification To verify the software the user must change the code in the DUALCON1 ASM file and save those changes The next step is to recompile the four ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages the new output file is ready to load in the DSP pro
43. CLOCK set 00000h use the external clock of the ADC DIFF INPUT MODE set 00000 use differential mode instead of single ended inputs IME CALIBRATIO set 00000 do an Internal Midscale Error Calibration SME CALIBRATIO set 00000 do a System Midscale Error Calibration text JM MAIN START INITIALIZATION disable IRQ INTM 1 SXM O SP 0280h initialize waitstates 00000h 01000h DP SWWSR copy interrupt routine sign extension mode ini Stack disable IRQ no sign extension mode initialize Stack pointer point to page zero one I O wait states EVM to the IRQ table location which are not critical for the this is required for the DSKplus kit but has to be changed on other platforms DP 1 AR7 00200h repeat 3h data 0084h AR7 AR7 00240h repeat 35 data 00COh 7 clear all memory locations of the sampling tabl DP AD_DP TEMP 00000h repeat num_data_A 1 point to page 1 IRQ vector table copy the NMI vector copy INTO 1 tabl where th y samples will be stored f Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 75 Software Overview data data_loc_A TEMP fill memory table 1 repeat num_data_B 1 data data_loc_B TEMP fill memory table 2 repeat num_data_C 1 data data_loc_C TEMP fill memory table 3 repeat num
44. DC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns kk ck Ck ck k k k ck Ck ck ck kk Ck k lt Ck x k k k ck kk ck kk ko x x Sk lt x k lt KKK KK KKK do one sample to perform the calibration Dk Ck ck ck K ck k k k k ck Ck ck k k k lt ck ck k k x lt Ck ck lt k x K lt ck x x x x x lt ko ko x ko XF 0 clear CSTART repeat 10 nop wait for some sampling time 1 reset CSTART repeat 34 54 SLAA040 Software Overview nop wait for 34 cycles until conversion has been finished TEMP port ADC read the sample but don t care about the content IFR 1 reset any old interrupt on pin INTO KKK KKK KKK k k lt KK KKK KKK KKK KKK KK KKK KK set back ADC register CRO CR1 KKK KKK KKK k k lt KK KKK KKK KKK k x x KK lt x x KK write CR1 to reset old CSTART mode initialization because otherwise the ADC never resets the INT pin to show a sample is available QCR PROBLEM 511 PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START port QCR PROBLEM Address decoder sets CS low WR low and send CR PROBLEM value to the ADC NOP wait for tW CSH 50ns write CRI port ADC CR1_SEND Address decoder sets CS low WR low and send CR1 value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns write CRO port ADC CRO_
45. DEBUGGER external interrupt external interrupt into intl vectors for software interrupts 18 30 Eri Software Overview nop nop nop int2 return enable 48 external interrupt int2 nop nop nop tint return enable 4C internal timer interrupt nop nop nop brint return enable 50 BSP receive interrupt nop nop nop bxint goto BXINTO 754 BSP transmit interrupt nop nop trint goto trint 758 TDM receive interrupt nop nop txint return enable 5 TDM transmit interrupt nop nop nop int3 return enable 60 external interrupt int3 nop nop nop hpiint goto hpiint 64 HPIint DO NOT MODIFY IF USING DEBUGGER nop nop Space 24 16 68 7 reserved area Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 91 Software Overview Constants definition see 8 6 1 1 Constants asm and for Interrupt Routine handler see 8 6 1 2 Interrupt Vectors Auto bat ECHO del map del obj del out del list del cnv cl500 exe k n c1562 c pause mnem2alg exe c1562 asm pause asm500 asmi562 asm 1 mg q s pause asm500 1562 1 mg q s pause lnk500 linker cmd Linker cmd RK IK IK kk kk kk K K K K K K K OK K K KOK K K KOK KOK KOK KOK K KOK KOK K K KOK KOK KOK K KOK K K K K KOK K K OK O K ke File Linker lnk COMMAND FILE title COMMAND FILE FOR TLV1562 ASM This CMD file allocates the memory area for the TLV1562
46. DMEM usect variabl 1 points to act memory save location CRO SEND usect variabl 1 the last value sent to register CRO CR1 SEND usect variabl 1 z the last value sent to register CRI CR PROBLEM usect variabl 1 problem with initialization of this mode when repeated reset ZERO usect variabl 1 the value zero to send TEMP usect variabl 1 temporary variable 74 SLAA040 Software Overview isr_save usect variabl 1 memory location to save AR7 during interrupts ADSAMPLE usect variabl 1 last read sample from the ADC Address Decoder constants ADC set 00002h activate A0 when TLV1562 is choosen RD CALIBRATION set 00001h activate A1 when CSTART is choosen DAC1 set 00003 activate A2 when DAC1 is choosen DEACTIVE set 00000 deactivate the address lines 0 Al and A2 SAVE INTO MEMORY set 00000 store the samples into DSP memory SEND OUT SERIAL set 00000 store the last sample allways into serial buffer memory SEND OUT PARALLEL set 00001 store the last sample allways into DACI R1LOBIT_RESOLU set 00001h use maximum resolution of 10 bit R8BIT_RESOLU set 00000h use 8 Bit resolution R4BIT_RESOLU set 00000h use fastest mode 4 Bit resolution INTERNAL CLOCK set 00001 use the internal clock of the ADC EXTERNAL
47. Driven Mode Using CSTART to Start Conversion 31 8 Time Optimization monocst1 Maximum Performance at 12 MSPS with Internal 33 9 Flow Chart Dual Interrupt Driven Mode Using CSTART to Start Conversion 35 10 Flow Chart Mono Continuous Mode 37 11 Flow Chart Dual Continuous Mode 1 39 List of Tables 1 Signal Connections 2 2 acere tages aig ue VER 7 2 3 Positlon Jumpets zeit tu Ree ek ice ERE Ru EEIT RR ERE a MEHR RIEN RUE 8 37 2 POSITION Jumpets vore eee eee ress ertt gre de eee er aede dr eer SY 8 4 DSP DAC 9 5 DSP Serial Port Signals and Registers 10 6 DSP Algorithm for Writing to the 12 7 DSP Algorithm for Mono Interrupt Driven Mode Using RD 13 8 DSP Algorithm for Mono Interrupt Driven Mode Using CSTART 14 9 DSP Algorithm for Dual Interrupt Driven Mode 15 10 DSP Algorithm for Mono Continuo
48. END CALIB_OP set calibration for further use clear mode related bits in CR CALIBRA and set MONO INT CR_CALIBRA amp INT OFFFFh clear bit for no calibration use CR_CALIBRA amp 00 INT OFFFFh clear bit for no calibration use CR_CALIBRA amp MONO CONTINUOUS OFFFFh clear bit for no calibration use GCR CALIBRA amp DUAL CONTINUOUS OFFFFh clear bit for no calibration use GCR CALIBRA INT set calibration for further use clear clock related bits in CR CALIBRA and set internal clock mode QCR CALIBRA amp CLK INTERNAL OFFFFh CR_CALIBRA amp CLK EXTERNAL OFFFFh CALIBRA 4CLK INTERNAL set mode for intermal offset calibration CR_CALIBRA 5 5 OFF CALIB kk ck k k k kk ck kk kk ck k lt x K lt lt x k x lt lt KKK x kk verify ADC register CRO CR1 KKK KK k k k KKK KKK KK x ko lt k k k KKK KKK KKK clear bit for no calibration use clear bit for no calibration use set calibration for further use set internal calibration mode write to reset old CSTART mode initialization because otherwise the ADC never sets back its INT pin to show a sample is available QCR PROBLEM SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START port ADC GCR PROBLEM NOP write CR1 Address decod
49. FILE title COMMAND FILE FOR TLV1562 ASM This CMD file allocates the memory area for the TLV1562 interface Program F k k e ke he hehehe hee e k e k k k k k k k k k k k k k k hee e ke k K k he he ke ee e He e KOK 7 stack 0x0080 M monocon1 MAP monocon1 OUT e START monoconl obj MEMORY PAGE 0 VECT origin 0200h length 0080h PROG origin 0300h length 0400h PAGE 1 RAMBO origin 1800h length 1600h SECTIONS text gt PROG 0 vectors gt VECT PAGE 0 gt RAMBO PAGE 1 variabl gt RAMBO PAGE 1 8 6 1 4 Auto bat The batch file to compile changes is specified for each mode but in general looks like the following made for the mono continuous mode del map del obj del out del 1st asm500 monoconl asm 1 mg q s pause lnk500 linker cmd Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 45 Software Overview 8 6 2 Mono Mode Interrupt Driven Software Using RD to Start Conversion Mainprogram Monomode asm KKK KKK k k KK KKK k k K KKK KKK KK KKK x k x KKK K x x KK KKK KKK KKK KKK KKK KEK KKK KKK KKK KK KKK KKK KK TITLE TLV1562 ADC Interface routine FILE MONOIDM1 ASM FUNCTION MAIN PROTOTYPE void MAIN CALLS SERIAL DAC initialzation of the BSPI ser
50. GoDSP development tools and to execute The flow chart in Figure 11 gives a general overview of the software structure MONOCON 1 ASM SLAA040 Software Overview Initialize DSP Wait States AR Pointer IRQ Table Data Memory Serial Port Initialize SPI Active Transmitter Use Frame Sync Generate External Clock SAVE_INTO_MEMORY 0 Initialize DSP Memory For Sample Store AR7 Points to The First Store Location ARO Points to The Table End ADCOUNT Table Size Number of Samples IME CALABRATION LIII E IME CALABRATION 9 Calibrate Internal Midscale Error A ETE r Calibrate System Midscale Error L SME CALABRATION 0 Initialize Id The Two ADC Registers CRO CRO_SEND CR1 CR1_SEND Increase States to 7 Start Sampling This Has Been Initialized by The WR 1 0 Transmit Wait 450 ns Read Sample Into DSP AD_SAMPLE Port ADC X pO u s r ine q 1 SAVE INTO MEMORY 1 e xD Sel SEND OUT PARALLEL 1 1 7 onda 4 Store Sample Into Memory SEND OUT PARALLEL o Save Sample to AR7 Pointed Location l ota 0 1 Table End Reached AR7 ARO Copy Last Sample to Serial DAC EA eurn T SERIAL 0 if Send Register is Empty L SE ND OU SER Reset Actual Memory Pointer TUE Ee achiev AR7 First Memory Store LSAVE INTO MEMO uM o 4 Location Data_Loc_A Wait 5 6
51. IRQ or timer set 00001 software polls the INTO pin to wait until conversion set 00000 software uses Interrupt INTO to organize conversion set 00000 INTO signal not in use interface is controlled with set 00001 store the samples into DSP memory defined in 000008 send the samples always to the serial DAC set 00001h update always the parallel DAC with the last sample DAC1 set 00001 use maximum resolution of 10 bit set 00000 use 8 bit resolution set 00000h use fastest mode 4 bit resolution set 00001 use the internal clock of the ADC set 00000hn use the external clock of the ADC set 00000h ADC goes into power reduced state after conversion set 00001 use differential mode instead of single ended inputs disable IRQ sign extension INIM SXM i SP 1 0 0280h mode ini Stack disable IRQ no sign extension mode initialize Stack pointer Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 47 Software Overview initialize waitstates copy interrupt routine this is required for the DSKplus clear all memory DP SWWSR 00000h 0100 Oh DP 1 ART 00200h repeat 3h data 0084h AR7 AR7 00240h repeat 35 data 00COh AR7 DP TEMP repeat data da repeat data da repea data da repea data da AD_DP
52. K QCRO SEND 4CLK INTERNAL clear CLK INTERNAL bit if one QCRO SEND CLK_EXTERNAL set CLK EXTERNAL mode endif if DIFF INPUT MODE GCRO SEND SINGLE END clear single ended input bit if one GCRO SEND DIFFERENTIAL set differential input mode endif Ck Ck ck ck K K ck k ck k k x lt Sk K k k KKK KKK k k lt KK x k k KKK KKK k x lt ck kk x kk KKK x x k kk ck kk x kk lt x lt x x KKK KKK x lt KKK Calibration do a calibration of the input if chosen the location of this instruction is only for an EVM test in practice the calibration procedure should xecuted when the inputs are shorted to the correct voltage and after calibration the analog signal is to apply before doing any further signal conversion the calibration implementation is more or less inserted as an example KKK KKK ck Ck ck k k x KK k k k KKK KKK k k lt KK KKK KKK KKK k x x KKK k x x KKK x x KKK KKK x k x KK K x x KKK KK k x lt x lt lt if IME CALIBRATION Lu call CALIBRAT INTERNAL MID SCAL endif if SME CALIBRATION call CALIBRAT SYSTEM MID SCALI endif Ck Ck ck ck ck ck ck ck ck k k x lt kk kk k x x KK KKK KKK Ug ADC INI set ADC register CRO CR1 KKKKKKKKKKKKKKKKK KKK KKK KKK KK ADC INI write CRI port ADC CR1_SEND Address decoder sets cs low Z WR low and send CR1 value to the ADC NOP
53. K 5 ERIAL DAC I initialize set up the initialize the serial buffer is e NI which are uncritical by the y disable IRQ no sign extension mode initialize Stack pointer point to page zero one I O wait states copy the NMI vector copy INTO fill El fill fill of the sampling memory memory memory memory INEL a tabl EVM to the IRQ table location hanged on other platforms point to page 1 IRQ vector table table table table table table where the samples will be stored the serial interface to send out the samples for the serial DAC serial interface for a DSP to DAC the SPI interface and the DAC 5618A conversation interface will be updated with the last sample if the serial mpty after the last bit has been send KKK k k k KKK KKK KK KKK k k K KKK KKK KK KKK KKK KKK x x x KKK KKK KKK KK KKK KKK KEK KKK KKK KK KKK KKK KKK KK SERIAL DAC INI BSPI INI DP 0 BSPC 00038h 68 SLAA040 reset SPI Software Overview BSPCE 00101h set clock speed no Autobuffer Mode BSPC 0C078h start serial port endif if INTO DRIVEN POLLING DRV reset pending IRQs IFR 1 reset any old interrupt on pin INTO endif if INTO DRIVEN enable Interrupt INTO DP 0 IMR
54. KK x x x KKK KK KKK Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 89 Software Overview BXINTO return_enable end Vectors asm interrupt is not in use kk ck k k k k ck Ck Ck k x k k k KKK k kk KK KKK x k k ck kk ck x x x lt lt Ck x x k x ck kk KKK ko x lt K x x kk x lt lt ck x x lt lt KKK KKK KK TI iE FILE FUNCTION ROTOTYPI ALLS OSTCONDITION PRECONDITION P SPECIAL COND D ESCRIPTION REFERENCE title Vector Table mmregs width 80 length 55 ref int00 reset goto c int00 00 nop nop nmi goto START 04 nop nop trap2 goto trap2 08 Space 52 16 0C 3F into s return fast nop nop goto IRQ INTO nop nop intl 90 TLV1562 ADC Interface routine VECTORS ASM Vector Table for the AAP Application Group EATED 1998 C CR N A N A A N A N A N A BY TEXAS I STRUM TMS320C54x DSKPlus User s Guide KKK KKK k k k KK KK k k k KKK KKK KK KKK x k x KK KKK x x x KKK k k k KKK KKK KKK KEK KKK KK KKK KKK KKK KKK KK return_enable SLAA040 come out of the IDLE 740 744 RESET DO NOT MODIFY IF USING DEBUGGER definition of of all interrupt vectors 54 DSKplus E Dallas Freising ENTS INCORPORATI TI 1997 non maskable external interrupt trap2 DO NOT MODIFY IF USING
55. KKK KKK KKK KKK KKK KKK ADC_INI set ADC register CRO CR1 KKK KK k k k KKK KKK KK KKK KKK KKK KKK ADC INI write to reset old CSTART mode initialization because otherwise the ADC never sets back its INT pin to show a sample is available QCR PROBLEM SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START port ADC PROBLEM Address decoder sets CS low WR low and send CR PROBLEM value to the ADC NOP wait for tW CSH 50ns write CRI port ADC CR1_SEND Address decoder sets CS low WR low and send CR1 value to the ADC 70 SLAA040 Software Overview port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns write CRO port ADC 8CRO SEND send CRO value to the ADC STEP1 port DEACTIVE ZERO deselect ADC CS high NOP KKK KKK KKK k k x KKK x x k k x KKK k k x KKK x x KKK KKK KKK KKK ADC dual IRQ Start read samples and store them into memory KEK KKK KKK KKK KKK KKK KKK lt ck x k k x lt ko ck k k lt lt KKK KKK KK ADC dual IRQ Start ISTEP2 XF 0 clear CSTART ISTEP3 NOP NOP NOP wait for TW CSTARIL if AUTO PWDN ENABLE wait 800ns before finishing the sampling requirment in Auto power down mode repeat 38 nop wait for 40 clock cycles t APDR 1000ns endif ISTEP4 XF 1 set CSTART STEP5
56. LC56 18 POWI 18 POWI 42 LATCH A LATCH B 18 FAST 18 SLOW 8 DOUBLE LATCH ODE OD ER_UP ER_DOWN SLAA040 Se se Se Se t 08000 t 00000 t 01000 t 04000 t 00000 t 00000 t 02000 n n n update output A update B update both outputs fast settling time 2 5us slower settling time power save remain active go sleep 8 6 1 2 Interrupt Vectors KKK KKK KKK k k KKK k k k KKK KKK k k x KK lt x k KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK TT ZEE P C P P S D TAR reset nmi trap2 ITLE ILE UNCTION ROTOTYPE ALLS CONDITION PECIAL COND ESCRIPTION UTHOR EFERENCE title Vector mmregs width CONDITION TLV1562 ADC Interface routine V A A A A A A ECTORS ASM definition of of all interrupt vectors Vector Table for the 54 DS AA P Application Group ICKE CREAT ED 1998 BY TEXAS INST 80 length 55 nop nop goto MAIN goto START nop nop nop nop Space 52 16 int 0 goto trap2 return fast nop nop nop goto IRQ INTO nop nop int 1 return_enable nop nop nop int2 return_enable Table 700 RESET DO NOT MODIFY IF USING DEBUGGER Kplus Dallas Freising
57. Midscale Error Calibration SME CALIBRATION System midscale error calibration Note the 2 switches are independent from each other however performing more than one calibration does not make sense see data sheet Features not listed in Table 12 must be changed directly in the two data words CR0 1 that are sent to the ADC In general correct bit setting is described in the data sheet However the file CONSTANT ASM includes a look up table to simplify the task of setting the right bits in CRO and CR1 Thus all it requires is to place the synonym for each feature into the correct bracket as shown in the next example EXAMPLE Task 1 1 Sample channel 1 in mono interrupt driven mode with single ended inputs Use the internal 8 MHz clock of the ADC and do not run in any power save mode The result should have a binary format with 10 bit resolution The conversion start is controlled by the RD signal Table 13 Instruction in the Program Header Step 1 R1OBIT_RESOLUT set 00001h enable 10 bit resolution R8BIT RESOLUT set 00000h RABIT RESOLUT set 00000h INTERNAL CLOCK set 00001h use internal clock EXTERNAL CLOCK set 00000h AUTO PWDN ENABLE set 00000h disable auto power down DIFF INPUT MODE set 00000h single input mode IME CALIBRATION 00000h no internal calibration SME CALIBRATION 00000h no system calibration 26 SLAA040 CRO_SEND 1 SEND Task 1 2 Software Overv
58. RUMENTS INCORPORAT 5320 54 DSKPlus User s Guide 1997 KKK KKK KKK k k x KK k k k KKK KKK k k x KK KKK x lt lt ck x x k k x KK KKK x x x K x x k lt x KKK KKK KKK x x x KKK KK KKK 704 non maskable external interrupt 708 trap2 DO NOT MODIFY IF USING DEBUGGER 0 vectors for software interrupts 18 30 come out of the IDLE 40 external interrupt 44 external interrupt 7 48 external interrupt into intl int2 Software Overview Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 43 Software Overview tint brint bxint trint txint int3 hpiint nop nop nop return_enable 4C internal timer interrupt nop nop nop return enable 50 BSP receive interrupt nop nop nop goto BXINTO 54 BSP transmit interrupt nop nop goto trint 7 58 TDM receive interrupt nop nop return enable 5C TDM transmit interrupt nop nop nop return enable 60 external interrupt int3 nop nop nop goto hpiint 764 HPIint DO NOT MODIFY IF USING DEBUGGER nop nop Space 24 16 68 7 reserved area 44 SLAA040 Software Overview 8 6 1 3 linker cmd The linker file for each mode is specified with called file names but in general looks like the following made for the Mono Continuous Mode KK KK KR RR RR RR KCKCKCKCKCKCKCKCKCKCKCKCKCKCKCKCKCKCKCKCkCK k Ck k ck k ck ck ck ck ck I x ke I I f File Linker 1nk COMMAND
59. SEND send CRO value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns return return from call endif if SME CALIBRATION Ck CK ck ck x x ck x k k x Ck Sk KKK KKK ck Ck x k k KKK K x x x x lt ck kk k kk lt kk x x x x x ck lt x k x x lt kk x x ck lt lt ck KK x x KKK KKK KKK KKK x x KKK CALIBRAT_SYSTEM_MID_SCAL performs internal calibration of the ADC to offset for the device midscale error and input offset basic idea do a error calibration in mono interrupt driven mode using CSTART for conversion but use the channel amp single differential input information already set up in the CRO_send register from KKK KKK ck k k k k KKK KKK k x K KKK k k x KK KKK x x lt KKK k x KKK KKK ck x lt KKK k k KKK KKK KKK KKK k lt x KK KKK KKK KK x x x x ko CALIBRAT_SYSTEM_MID_SCALE DP AD_DP initialize data pointer clear calibration related bits in CRO CRO_SEND amp CALIB OP OFFFFh clear bit for no calibration use SEND amp OP OFFFFh clear bit for no calibration use initialize the send values to setup the two programmable registers of the ADC to calibrate data CR CALIBRA QCRO SEND load help register with CRO content Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 55 Software Overview use calibrated mode in the following for conversion CRO_S
60. SP END CLK INTERNA NO SW PWDN NO AUTO PWDN NO 2COMPL NO CALIB OP EMENT NO D EBUG R ES 10 BIT CST CONV START by variation of the bit setting in the file header the user is running in only one special configuration clear bit for 10 Bit Resolution set 8 Bit conversion mode 61 Software Overview elseif R4BIT_RESOLUT CR1_SEND RES_10_BIT CR1_SEND RES 4 BIT endif if EXTERNAL CLOCK CRO_SEND CLK_INTERNAL CRO_SEND CLK_EXTERNAL endif if AUTO PWDN ENABLE QCR1 SEND NO AUTO PWDN QGCR1 SEND AUTO_PWDN endif if DIFF INPUT MODE SEND SINGLE_END GCRO SEND DIFFERENTIAL endif if IME CALIBRATION call CALIBRAT INTERNAL MID SCAL endif if SME CALIBRATION call CALIBRAT SYSTEM MID SCALE endif kk ck ck ck ck k k k ck ck ck ck ck x x lt lt K x x k lt kk KKK ADC INI set ADC register CRO CR1 KKK KK k k k KKK KKK KKK KKK KKK KK KKK ADC INI clear bit for 10 Bit Resolution set 8 Bit conversion mode clear CLK INTERNAL bit if one set CLK EXTERNAL mode clear NO AUTO PWDN bit if one set AUTO PWDN mode clear single ended input bit if one set differential input mode write to reset old CSTART mode initialization because otherwise the ADC never sets back its i
61. These paragraphs describe other DSP and TLV1562 signals 6 1 DSP Internal Serial Port Operation Three signals are necessary to connect the transmit pins of the transmitting device with the receive pins of the receiving device for data transmission The transmitted serial data signal BDX sends the actual data BFSX initiates the transfer at the beginning of the packet and BCLKX clocks the bit transfer The corresponding pins on the receive device are BDR BFSR and BCLKR respectively The transmit is executed by the autobuffer mode This means there is no need to write to the serial port output buffer Instead the DSP continuously sends the data located in the memory beginning on AXR When all data are sent defined by the buffer length in BXR the first word pointed to by AXR is sent again Therefore the program has only to store the samples into this memory location The rest of the task is handled in the background using no CPU power Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 11 Conversation Between the TLV1562 and the DSP 7 Conversation Between the TLV1562 and the DSP The complexity of the TLV1562 ADC may be confusing because of the number of possible modes to drive the protocol between DSP and ADC The following paragraphs explain more about the data sheet descriptions for interfacing the C54x to the ADC 7 1 Writing to the ADC Registers CRO and CR1 must be set to choose any of the modes the TLV1562 of
62. UT SERIAL store sample into the serial buffer location DP 00000h point to page zero lf this TC has been includ bitf s goto S PC 0 1000h END_S ERIAL_ END d becaus th test is the XRDY Bit in SPC 1 don t send something until XDR is empty serial DAC TLC5618A is not able to understand endless data stream the 16th bit DP AD_DP A ADSAMPLE lt lt 2 ADSAMPLI A ADSAMP LE DAC da END_S endif BDXR ERIAL END if SAVE INTO MEMORY ADSAMPLE test for table end se TC ARO AR7 if NTC goto STORE_END set pointer back to table start 64 SLAA040 the cs should TLC5618_LATCH_A TLC5618_FAST_MODE TLC5618_POWER_UP not become high before end of sending reset Data page pointer to variables leftshift of the sample for a 12 bit format set the mode of th send out th to the serial DAC sampl t pointer back if true is ARO AR7 table end reached Software Overview AR7 data_loc_A point to first date location of the storage table endif STORE END RETURN jump back into data aquisition routine Ck Ck ck ck Ck K KKK k k x lt Sk k k k ck x K KKK k kk ck kk x k x kk ck x x k kk ck kk ck k x kk lt x x KKK KK KKK x lt lt IRQ_INTO Interrupt routine of the external int
63. V5651 5 GND DSP BCLKR pin gets a shortcuted feedback BCLKR remains open from the BCLKX transmit pin normal mode Normal mode of operation Sleep mode seleted SLAA040 The Serial DAC DSP System 4 The Serial DAC DSP System The software configures the buffered DSP serial port to the 16 bit master mode so that the DSP generates the frame sync signal at BFSX and the data clock at BCLKX serial port terminals Table 4 shows the connections between the DSP and the DAC TLC5618A Table 4 DSP DAC Interconnection The following statements describe the generation and application of the configuration and control signals The DSP BCLKX output provides a 20 MHz data clock which is a divide by 2 of the DSP master clock e The DSP BDX output supplies the 16 bit control and data move to the TLC5618A at DATA IN e The DSP BFSX frame synchronization signal connected to CS triggers the start of a new frame of data After the falling edge of FSX the next 16 data clocks transfer data into the DSP DR terminal and out of the DX terminal Since this DSP DAC interface is synchronous the FSX signal is sent to the FSR terminal and the CLKX is sent to the CLKR terminal Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 9 The DSP Serial Port 5 The DSP Serial Port The buffered serial port provides direct communication with serial I O devices and consists of six basic signals and five registers The DSP internal
64. _data_D 1 data data_loc_D TEMP fill memory table 4 if SEND OUT SERIAL kk ck Ck ck k k k ck lt ck k Sk Ck Ck KKK k kk ck kk Ck x k KKK KKK kk ck kk Ck x x k k lt kk ck kk ck kk Ck x k k x lt kk lt kk Sk x K lt lt lt k k KKK KKK SERIAL DAC INI initialize the serial interface to send out the samples for the serial DAC set up the serial interface for a DSP DAC 5618A conversation initialize the SPI interface and the DAC the serial interface will be updated with the last sample if the serial buffer is empty after the last bit has been send kk ck Ck ck k k k ck kk k x k k k ck K x k k k ck kk Ck x x k K KKK ck k x KK KKK x k x KKK ck x x x kk ko x x kk lt kk Sk x x x x lt Sk x x x x lt lt x lt x ok SERIAL DAC INI BSPI INI DP 0 BSPC 00038h reset SPI BSPCE 00101h set clock speed no Autobuffer Mode BSPC 0C078h start serial port endif enable global interrupt this is even required if no IRQ routine is used by this program because the GoDSP debugger needs to do its backgroud interrupts INTM 0 enable global IRQ initialize storage table for the ADC samples ART d data loc A point to first date location of the storage table ARO num data A data loc A ARO points to table end DP AD_DP 7 ADCOUNT num_data_A initialize ADCOUNT with the number of required samples DP DP ZERO 00000
65. are given later in this report CommsDAC is a trademark of Texas Instruments 2 2 TLV1562EVM The TLV1562EVM gives customers an easy start with employing many of the features of this converter A serial DAC TLC5618A a parallel DAC THS5651 and the ADC TLV1562 make this EVM flexible enough to test the features of the TLV1562 It also helps show how this ADC can be implemented 23 ADC TLV1562 Overview The TLV1562 is a CMOS 10 bit high speed programmable resolution analog to digital converter using a low power recyclic architecture The converter provides two differential or four single ended inputs to interface the analog input signals On the digital side the device has a chip select CS input clock CLKIN sample conversion start signal CSTART read signal input RD write signal input WR and 10 parallel data I O lines 09 0 The converter integrates the CSTART signal to coordinate sampling and conversion timing without using the parallel bus Since the TMS320C542 DSP has no second general purpose output this signal is generated with the signal CSTART from the address decoder 2 3 1 Suggestions for the C54x to TLV1562 Interface The following paragraphs describe two suggested interfaces between the C54x and the TLV1562 The Universal Interface The schematic in Figure 1 shows the pin to pin connections between the TLV1562 and C54x realized on the EVM This routing can test the converter in each mode One
66. data ADMEM SP 1 read saving location data ADCOUNT SP 2 read number of samples push AR6 save AR6 push AR7 save AR7 CPL 0 do DP pointer addressing sign extension mode ini Stack SXM 0 no sign extension mode reset pending IRQs IFR 1 reset any old interrupt on pin INTO Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 87 Software Overview initialize storage table for the DP 1 CH_NO A A ADMEM AR7 A ADCOUNT B ADMEM ARO A AR5 IFR DP AD_DP ZERO 00000 initialize the send values to MONO_INT SINGL ADC samples 7 decrement A read number of sampling channel point to first date location of the storage table ARO points to table end ARO is loaded with last save location AR5 points to the register only for polling mode set the dummy send value set up the two programmable register of the ADC A QCRO SEND INTERNAL NO CALIB OP NO SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT CST CONV START KKK k k x KKK k k k KK KKK KKK KKK KKK KK ADC_INI set ADC register CRO CR1 KKK KK k k k KK KKK KKK KKK KKK KKK KKK ADC INI write CR1 to back its int PROBLEM port ADC NOP write CRI reset old CSTART mode initialization otherwise the ADC never se
67. ded in Table 9 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 33 Software Overview 34 IMPORTANT NOTE The code has been optimized to maximize the data throughput It was found that CSTART can be pulled low earlier than the data read instruction is performed by the DSP This saves the 100 ns wait time in STEP 3 because the data read requires at least 100 ns Therefore CSTART gets pulled high directly after data read and the interface becomes faster and gains throughput This variation will be found in the code The data acquisition is done in a small number of steps that explains everything inside the code Code verification To verify the software the user must change the code in the DUALIRQ1 ASM file and save those changes The next step is to recompile the four ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages the new output file is ready to load into the DSP program memory e g with the GoDSP development tools and to execute The flow chart in Figure 10 gives a general overview of the software structure DUALIRQ1 ASM SLAA040 Software Overview wass Initialize DSP No Wait States AR Pointer IRQ Table L Transition on INTO 27 gt gt T T Initialize SP Yes Active Transmitter Use Frame Sync
68. e interrupt is not in use sect text copy TLC5618 asm end 52 SLAA040 Software Overview 8 6 3 Calibration of the ADC CALIBRAT ASM KKK KKK KKK k k KKK KKK KKK KKK k k KKK KKK KKK KKK KKK KK K k x KKK KKK k lt x KK KKK KKK KKK KKK KKK KKK TITLE TLV1562 ADC Interface routine FILE CALIBRAT ASM FUNCTION CALIBRAT INTERNAL MID SCALE X CALIBRAT_SYSTEM_MID_SCALE x CALLS N A PRECONDITION N A POSTCONDITION N A SPECIAL COND N A DESCRIPTION routine to perform a ADC calibration Ww AUTHOR AAP Application Group ICKE Dallas CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 5 KK KK KK KK KK KK K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K title CALIBRAT mmregs width 80 length 55 version 542 if IME CALIBRATION SME CALIBRATION sect data CR CALIBRA usect variabl 1 temporary variable can be changed anywhere during the program sect text if IME CALIBRATION Ck Ck ck ck K K ck Ck x k k x lt Sk K Ck x k Ck lt x x k k x KK K x x x x lt ck x x k x KKK KKK x x lt ck kk k kk lt kk Ck x ck x x ck kk k kk ck x x Ck x x x lt x KKK x lt ko ko CALIBRAT_INTERNAL_MID_SCALE performs an internal calibration of the ADC to offset for internal dev
69. e ADC The three Jumpers define the prescaling of the CLKOUT signal to the MCB_CLK Pin if W8 is set to Counter Mode MCB_CLK is connected to BUFCLK U14 or RDT U11 Counter Mode signal is divided by the counter set up with Jumper W 5 7 Counter Mode disabled MCB CLK is synchronize with the CLKOUT signal W10 W11 W12 CLK input of the Counter U2 is connected with CLKOUT or CLKOUT 2 ADC CLKIN is connected to CLK 2 or CLK 4 Connects AP CH1 ADC to R48 or GND Connects AM CH2 ADC to R47 or GND The counter is toggled by the DSP system clock signal The ADC clock runs at a quarter of the DSP clock frequency 10 MHz Input not in use grounded to reduce noise Input not in use grounded to reduce noise The counter s clock is prescaled by two toggled by half the DSP system clock CLKOUT2 The ADC clock runs at half the DSP Use as single input channel 1 or differential input positive channel A W13 Connects REFLO TLV5651 to Vcc or GND Disable internal reference Enable internal reference W14 W15 W23 W24 Connects SCLK TLC5618AA to BCLKX or J8 BNC Connects CLK TLV5651 to CLKOUT DSP or J7 BNC Connects CSTART to AO A1 or XF Connects DSP_RD to XF or IOSTRB ORed with R W from the DSP Normal DSP mode Normal DSP mode AO and A1 used to generate ADC CSTART signal XF signal connected to ADC RD pin clock frequency 20 MHz
70. e number SLAS139 5320 54 DSK plus Adapter Kit Literature number SLAU030 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP Summary 93
71. er for the monomode software C54x Code compiler C54x linker in the code This helps to debug and verify the code Code verification To verify the software the user must change the code in the MONIDM1 ASM file and save those changes The next step is to recompile the three ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages the new output file is ready to load in the DSP program memory e g with the GoDSP development tools and to execute The flow chart in Figure 7 gives a general overview of the software structure MONOIDM1 ASM SLAA040 Software Overview Initialize DSP Wait States AR Pointer IRQ Table Data Memory Serial Port rap rw Initialize SPI No Active Transmitter Use Frame Sync oru gt G te External Clock lt lt L Transition on INTO 2 gt gt ener R d T J Yes TEENE SAVE INTO MEMORY 0 eee 1 Initialize DSP Memory For Sample Store AR7 Points to The First Store Location ARO Points to The Table End ADCOUNT Table Size Number of Samples INTO External Interrupt Save Modified Register of 74 IRQ Routine if Not Automatically Saved by The DSP Not Required Initialize Id The Two ADC Registers CRO CRO_SEND CR1 CR1 SEND INTO_DRINEN 1 1 POLLING DRIVEN 11 INTO SIGNAL 1 fi LU 2 J
72. er sets CS low WR low and send CR PROBLEM value to the ADC wait for tW CSH 50ns initialize the send values to setup the two programmable registers of the ADC CR_PROBLEM NO SW PWDN NO AUTO PWDN NO 2COMPL port ADC PROBLEM port DEACTIVE ZERO NOP write CRO port ADC CR_CALIBRA port DEACTIVE ZERO NOP ENT NO_DEBUG RES_10_BIT CST_CONV_START send CRO value to the ADC deselect ADC CS high wait for tW CSH 50ns send CRO value to the ADC deselect ADC CS high wait for tW CSH 50ns KKK KK KKK KKK k k k KKK KKK k k KKK KKK KK KKK x k k KKK KKK KK do one sample to perform the calibration KKK KKK k k ck KKK KKK KKK x k k KKK KKK KKK KKK KKK KKK KKK KK 0 repeat 10 56 SLAA040 clear CSTART Software Overview nop wait for some sampling time 1 reset CSTART repeat 34 nop wait for 34 cycles until conversion has been finished TEMP port ADC read the sample but don t care about the content IFR 1 reset any old interrupt on pin INTO Ck Ck ck ck K K ck Ck ck k k x Ck kk kk k kk kk x k k x lt ko KKK KK set back ADC register CRO CR1 Ck Ck ck k kk ck Ck ck k k x Ck kk Ck k k x x lt kk k k x KK KKK KK write CR1 to reset old CSTART mode initialization because otherwise the ADC never sets back its i
73. errupt input pin INTO Ck ck ck ck K KKK k k x lt Sk Ck Ck k x K K ck Ck x k k x ck kk x k x kk ck x x k kk ck kk k kk kk K x x KKK KK lt x x x lt lt IRQ INTO call STEP2 initialize the next conversion and store results return enable return from IRQ wake up from the IDLE mode Ck Ck ck ck k k x lt Sk k Ck k KKK KKK k k x KK KKK KKK KKK k k x ck kk lt k x kk k x x k k lt ck kk x k x lt lt lt x x x lt ko KKK KKK BXINTO Interrupt routine of the serial transmit interrupt of the buffered SPI KKK KKK KKK k k x KK k k k x x x KKK k k KKK KKK KKK KKK k k x KK x x k x x lt K x x k lt lt KK KKK KKK KKK KKK KKK KKK BXINTO return_enable interrupt is not in use sect text copy calibrat asm end Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 65 Software Overview Constants definition see 8 6 1 1 Constants asm Interrupt Routine handler see 8 6 1 2 Interrupt Vectors 8 6 5 Dual Interrupt Driven Mode Mainprogram DUALIRQ1 asm KKK KK k k k KK KKK k k k KKK KKK KK KKK k k k KKK x x x KKK lt x k k k x KK KKK KKK KEK k k k KK KKK k k k k k k k k k KK xaT E P C SP P D T ILI U RO AL RE OS ES UT CTION TOTYPI LS CONDITION TCONDITION CRIPTION HOR ERENCE TLV1562 ADC Interface routine G DUALIRQ1 ASM MAIN void MAIN N A N A N A main routine to use the mon
74. fers Therefore a write sequence must be performed from the DSP to the ADC After selecting the ADC CS low a high low transition of the WR line tells the converter that something is to be written to the data port Table 6 DSP Algorithm for Writing to the ADC STEPS TIMING NOTES 1 Set DSP I O waitstate Make timing between 40 MHz C54x CPU compatible with the TLV1562 2 Clear CS Select ADC 3 Send out data on the bus The signal WR is automatically handled by the DSP 4 SetCS Deselect ADC 7 2 Mono Interrupt Driven Mode Using RD This mode is used when the application needs to sample one channel at a time and performs the sampling conversion and serial transmission steps only once Although this mode produces continuous sampling data the use of other modes is recommended One reason is the CS signal has to stay low during the whole sampling conversion time An interesting advantage of this mode is its ability to control the start sample time The RD signal controls the sampling and converting Every falling edge of RD stops the sampling process disconnects the capacitor from the input signal and starts the signal conversion After two ADCSYSSCLKs the sampling capacitor gets connected back to the input signal to do the next sampling The conversion time needs five ADCSYSCLKs to finish the conversion before it gets written to the data port During configuration the rising edge of WR starts the sampling Also when con
75. ght Switches As the software offers the choice of three conversion end recognition strategies it allows selection of other ADC related features such as the clock source power save mode or the resolution Depending on the custom requirements of data throughput the program header also defines whether the samples will be stored into memory sent serially out to the TLC5618A DAC or sent in parallel to the TLV5651 CommsDAC Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 25 Software Overview Table 12 Switch Settings SWITCH SAVE_INTO_MEMORY SEND_OUT_SERIAL SEND_OUT_PARALLEL DESCRIBTION Store the samples into DSP memory location defined in constants asm Send the samples always to the serial DAC TLC5618A Update always the parallel DAC with the last sample DAC1 THS5651 Note the 3 switches are independent from each other R10BIT RESOLUT R8BIT RESOLUT RABIT RESOLUT Use maximum resolution of 10 bit Use 8 Bit resolution Use fastest mode 4 Bit resolution Note enable only one of the 3 switches Use the internal clock of the ADC Use the external clock of the ADC Note enable only one of the 2 switches INTERNAL CLOCK EXTERNAL CLOCK AUTO PWDN ENABLE ADC reduces power consumption after conversion 1 enable power down mode 0 no PWDN mode Use differential mode instead of single ended inputs 1 differential ADC input 0 single ADC input DIFF INPUT MODE IME CALIBRATION Internal
76. gram memory e g with the GoDSP development tools and to execute The flow chart in Figure 12 gives a general overview of the software structure DUALCON1 ASM SLAA040 Initialize DSP Wait States AR Pointer IRQ Table Initialize SP Active Transmitter Use Frame Sync Clock Generate External Data Memory Serial Port Software Overview SAVETINTOTIIEMCO RAS SS q ILI Initialize DSP Memory For Storing Samples AR7 Points to The First Store Location ARO Points to The Table End ADCOUNT Table Size Number of Samples F IME CALABRATION 1 CALABRATION 01 r r L e SSE ARROAN AN A Calibrate System Midscale Error CALABRATION 0 Initialize Id The Two ADC Registers CRO CRO_SEND CR1 CR1 SEND Increase l O Wait States to 7 Start Sampling This Has Been Initialized by The WR 1 0 Transmit Wait 450 ns Read Sample A A Port ADC Wait 5 6 ADC Clock Cycles 800 ns With 8 MHz ADC Clock Read Sample B B Port ADC m ra e Z s gt 1 LJ B F SEND OUT PARALLE 01 r b Store Sample Into Memory Save Sample to AR7 Pointed Location Table End Reached AR7 ARO ll Copy Last Sample to Serial DAC END T SERIAL if Send Register is Empty SET ID OUT 5 zo J r
77. head is the branch instruction from the original IRQ vector to the IRQ handler memory location In summary the large number of instructions used to organize the interrupt and to branch from the actual code execution into the interrupt service routine will significantly use up resources Advantages e Data acquisition runs fully automated in the background the main program filtering other controlling etc does not need to control any data acquisition software flow Easy software debugging and implementing of new features not critical for any software changes e The software compensates for variations in timing given in data sheets for conversion and the real time until the flag goes high Disadvantages e Program overhead uses a lot of resources which is critical for maximum throughput performance e Watchdog algorithms needed to avoid a hang up of the ADC 8 4 1 4 Enabling One Software Mode Every main file given later in this document offers the following three switches in the program header SWITCH DESCRIPTION POLLING DRV software polls the INTO pin until conversion is finished INTO DRIVEN software uses Interrupt INTO to organize conversion NO INTO SIG INTO signal not in use interface is controlled with timing solution NOTE Only one of the three switches is to be enabled Example Run in interrupt driven mode POLLING DRV set 00000h INTO DRIVEN set 00001h NO INTO SIG set 00000h 8 4 1 5 Setting the Ri
78. ial DAC PRECONDITION N A POSTCONDITION N A SPECIAL COND ARO protected in use for the data storage procedure 5 AR5 protected in use for polling IFR only for software polling solution D X AR7 protected in use for the data storage procedure DESCRIPTION main routine to use the mono interrupt driven mode AUTHOR AAP Application Group ICKE Dallas CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED E REFERENCE TMS320C54x User s Guide TI 1997 TMS320C54x DSKPlus User s Guide TI 1997 Data Aquisation Circuits TI 1998 KKK KKK k k k KKK x k k KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KEK KKK KK KKK KKK KKK KKK KK title mmregs width length Version the next 4 lines instead of Setsec Sect copy vec sect da copy con MONOIDM1 80 55 542 set sect hav to b nabled if the DSKplus code generator the asm500 exe tools are in use t vectors 0x00180 0 sections of code t text 0x00200 0 these assembler directives specify t data 0x01800 1 the absolute addresses of different t variabl 0x01800 1 sections of code ctors tors asm ta stant asm ADC conversation AD DP usect ACT CHANNEL usect ADCOUNT usect ADMEM usect 46 SLAA040 variabl variabl variabl variabl pointer address jump addres
79. ic rrors basic idea do a error calibration in mono interrupt driven mode using CSTART for conversion but use the channel amp single differential input information already set up in the CRO_send register from k K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K ck K K K K K K K K K K K K K K K K K CALIBRAT_INTERNAL_MID_SCALE DP AD_DP initialize data pointer clear calibration related bits in CRO GQGCRO SEND amp CALIB OP OFFFFh clear bit for no calibration use QGCRO SEND amp CALIB OP OFFFFh clear bit for no calibration use initialize the send values to setup the two programmable registers of the ADC to calibrate data CR CALIBRA QCRO SEND load help register with CRO content use calibrated mode in the following for conversion GCRO SEND CALIB_OP set calibration for further use Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 53 Software Overview clear mode related bits in CRO and set MONO_INT CRO_SEND amp MONO_INT OFFFFh clear bit for no calibration use GCRO SEND amp DUAL INT OFFFFh clear bit for no calibration use QGCRO SEND amp 4 CONTINUOUS OFFFFh clear bit for no calibration use QGCRO SEND amp DUAL CONTINUOUS OFFFFh clear bit for no calibration use GCRO SEND INT set calibration for further use c
80. ical for any software changes e g adding new features e Even when the program reaches the polling loop later than the transition occurred it steps ahead properly Disadvantage e Time inside the polling loop is not usable for other software features wasted CPU power Ahangup ADC does not respond will not be recognized without a watchdog algorithm e The polling algorithm requires five instruction cycles Depending on when the conversion finishes during these five instructions when the INT signal goes low the time response after the falling edge can vary upto the five instruction cycles As experiments confirmed this can result in a variation in the length of the sampling window So a filter algorithm eg FFT on the samples might result in slightly different results for a steady stable input function related to the sampling time variations The only way to prevent this is to control the conversion with the on chip timer of the DSP Unfortunately the maximum throughput falls off with increased requirements for CPU power 8 4 1 2 Timed Solution 24 How long the ADC requires for conversion must be factored into the software flow In other words the DSP has to wait a certain time between initializing the conversion and reading the conversion result on the data bus from the ADC This timing is critical to the sampling device If the conversion time of a data converter changes data sheet the timing must be verified again
81. iew Use channel B in differential input mode and an external clock source Following changes have to be done with the set up of Task 1 1 Table 14 Instruction in the Program Header Step 1 R10BIT RESOLUT R8BIT RESOLUT RABIT RESOLUT INTERNAL CLOCK EXTERNAL CLOCK AUTO PWDN ENABLE DIFF INPUT MODE H E CALIBRATION E_CALIBRATION set 00001h enable 10 bit resolution set 00000h set 00000h set 00000h set 00001h use external clock set 00000h disable auto power down set 00001h differential input mode set 00000h no internal calibration set 00000h no system calibration Additional correction in the middle of the main program files step 2 PAIR INT SINGLE END CLK INTERNAL NO CALIB OP NO SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START CAUTION Changing statements in step 2 is not required if they are already defined in the header For example the statement CLK INTI ERNAL does not change to CLK EXTERNAL in step 2 because the clock source is defined in the program header and therefore will be justified behind the step 2 instructions later in the program That is why in step 2 only the CH1 value is replaced with PAIR B but nothing else has been specified 8 4 1 6 Common Software for all Modes The files CONSTANT ASM and VECTORS ASM include constant definitions and the interrupt vector table Those pa
82. into idle state until the INTO wakes the processor up USER MAIN IDLE 2 the user software could do something else her goto USER MAIN elseif NO INTO SIG instead of using the INT signal the processor waits for 6ADCSYSCLK 49ns and reads then the sampl repeat 32 nop wait for 34 processor cycles endif read sample STEP2 XF 0 clear CSTART STEP10 ADSAMPLE port ADC read the new sample into the DSP if AUTO PWDN wait 800ns before finishing the sampling requirment in Auto power down mode repeat 424 nop wait for 20 clock cycles t APDR 500ns endif Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 63 Software Overview wait for TW CSTARTL and set CSTART STEP4 call XF 1 STORE store the last sample into the table if INTO DRIVEN return return from routine back to IRQ INTO else goto STEPS go back to receive next sample endif kk ck ck ck k k k k kk kk ck k k lt kk k k k KKK lt x K x x lt kk ck STORE saving the samples into memory KKK KKK k k KKK KKK k k KKK KKK KKK KKK KKK kk ck STORE if SEND OUT PARALLEL store sample into the parallel buffer location if choosen port DAC1 endif ADSAMPLE Z update DAC output if SAVE INTO MEMORY store new sample into DSP data memory data ADSAMPLE ART endif write last sample into memory table if SEND O
83. k ck kk ck kk k x lt ko kk x k lt lt KKK KKK KKK KK ADC mono IRQ Start read samples and store them into memory ck ck k k ck k K lt lt k k k k Ck ck lt k k ck lt lt ck kk k lt ck lt lt k x x x lt lt x x lt ADC_mono_IRQ_Start STEP3 repeat 4 NOP wait for tD CSL SAMPLE 41SYSCLK 6 STEP4 XE 0 clear RD STEP5 if POLLING DRV wait until INT goes low in polling the INTO pin M1 TC bit AR5 15 0 test is the INTO Bit in IFR 1 if NTC goto M1 wait until INT signal goes high IFR 1 reset any old interrupt on pin INTO elseif INTO DRIVEN user main program area this could execute additional code go into idle state until the INTO wakes the processor up STEP2 TEMP port ADC select ADC CS low change address bus signal USER MAIN IDLE 2 the user software could do something els goto USER_MAIN gt 50 SLAA040 Software Overview elseif NO INTO SIG instead of using the INT signal the processor waits for 6ADCSYSCLK 49ns and reads then the sampl repeat 32 nop wait for 34 processor cycles endif read sample STEP7 ADSAMPLE port ADC read the new sample into the DSP XF 1 set RD if SEND OUT PARALLEL store sample into the parallel buffer location if choosen port DAC1 ADSAMPLE update DAC output Q TEMP port ADC activate ADC CS again endif if
84. k k lt kk KKK KKK KKK KKK kk ck STORE 1 SEND_OUT_PARALLEL store sample into the parallel buffer location if choosen port DAC1 CH1_ADSAMPLE update DAC output with sample one endif if SAVE INTO MEMORY store new sample into DSP data memory AR7 data QCH1 ADSAMPLE write last sample of channel 1 into memory table AR6 endif if SEND OUT SERIAL data QCH2 ADSAMPLE write last sample of channel 2 into memory table store sample into the serial buffer location DP 00000h point to page zero TC bitf SPC 01000h test is the XRDY Bit in SPC 1 if TC goto SEND_SERIAL_END don t send something until XDR is empty this has been included because the serial DAC TLC5618A is not able to understand endless data streem the cs should not become high before end of sending the 16th bit DP AD_DP reset Data page pointer to variables A ADSAMPLE lt lt 2 leftshift of the sample for a 12 bit format 84 SLAA040 Software Overview ADSAMPLE A Z ADSAMPLE TLC5618_LATCH_A TLC5618_FAST_MODE TLC5618_POWER UP set the mode of the DAC data BDXR ADSAMPLE send out the sample to the serial DAC SEND_SERIAL_END endif test for table end set pointer back if true if SAVE INTO MEMORY TO ARO ART is AR7 ARO table end reached if NTC goto STORE_END set pointer back to table sta
85. ki TEXAS INSTRUMENTS Interfacing the TLV1562 Parallel AD Converter to the TMS320C54x DSP Application Report July 1999 Advanced Analog Products SLAA040 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN
86. l Clock INTO External Interrupt x Initialize DSP Memory For Sample Store Save Modified Register of AR7 Points to The First Store Location The IRQ Routine if Not ARO Points to The Table End Automatically Saved by The ADCOUNT Table Size Number of Samples o _ IME CALABRATI E ME CAESPRATIONSS IIS IME CALABRATION 1 0 5 r 7 IME CALABRATION IMESISEABHATION Oy Initialize Id The Two ADC Registers CRO CRO_SEND CR1 CR1 SEND Start Sampling Pull Down CSTART Wait 100 ns Stop Sampling and Start Conversion Reset CSTART Set Back High zo INTO_DRINEN 1 POLLING_DRIVEN NO_INTO_SIGNAL 4 4 Start New Sampling Pull Down CSTART Read Sample Stop Sampling and Start Conversion Reset Set Back High SAVE INTO MEMORY 0 4 L Copy Last Sample to Parallel DAC Store Sample Into Memory Save Sample to AR7 Pointed Location rs END_OUT_PARALLEL Table End Reached AR7 ARO Start New Conversion r Copy Last Sample to Serial DAC rupe if Send Register is Empty SEND OUT SEHIAEEO Reset Actual Memory Pointer AR amp First Memory Store Location SAVE INTO MEMORY 0 l Figure 7 Flow Chart Mono Interrupt Driven Mode Using CSTART to Start Conversion Interfacing the TLV1562 Pa
87. lear clock related bits in CRO and set internal clock mode GCRO SEND amp CLK INTERNAL OFFFFh clear bit for no calibration use GCRO SEND amp CLK EXTERNAL OFFFFh clear bit for no calibration use QGCRO SEND CLK_INTERNAL set calibration for further use set mode for intermal offset calibration CR_CALIBRA OFF CALIB set internal calibration mode ck k k k ck kk k kk k k x kk k k k x x lt x x x KKK verify ADC register CR0 CR1 KKK K k k k k x x x ko lt x k k lt kk lt x x lt x lt x x x x write CR1 to reset old CSTART mode initialization because otherwise the ADC never sets back its INT pin to show a sample is available CR_PROBLEM SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START port ADC CR_PROBLEM Address decoder sets CS low WR low and send CR PROBLEM value to the ADC NOP wait for tW CSH 50ns write initialize the send values to setup the two programmable registers of the ADC QGCR PROBLEM NO SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT CST CONV START port ADC PROBLEM send CRO value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns write CRO port ADC CR_CALIBRA send CRO value to the A
88. les and store them into memory k k ck K ck k k k k ck lt k k k k k lt x k k k kk ck k k k lt ck kk k lt lt lt k ko X ko ADC_mono_con_Start repeat 12 NOP wait for t SAMPLES 450ns STI Gl P6 ADSAMPLE port ADC read the new sample into the DSP IMPORTANT fine tune the counter number of the next repeat loop in order to achive maximum throughput related to the delay of the store instructions n 7 repeat 7 NOP wait for t CONV1 about 800ns n E EP8 call STOR Fl store the last sample into the table goto STEP6 go back to receive next sample KKK KK k k k KK KKK k k k KKK KKK KKK KKK KKK KKK STORE saving the samples into memory ck ck ck ck ck ck KKK KKK KKK ck x k K lt lt lt lt lt KKK KK x x lt STORE if SEND OUT PARALLEL store sample into the parallel buffer location if chosen port DAC1 ADSAMPLE update DAC output endif if SAVE INTO MEMORY store new sample into DSP data memory AR7 data QADSAMPLE write last sample into memory table endif if SEND OUT SERIAL store sample into the serial buffer location DP 00000h point to page zero TC bitf SPC 01000h test is the XRDY Bit SPC 1 if TC goto SEND_SERIAL_END don t send something until XDR is empty this has been included because the serial DAC TLC5618A is not able to understand endless data s
89. n this is required for the DSKplus kit but has to be changed on other platforms DP 1 point to page 1 IRQ vector table AR7 00200h repeat 3h data 0084h AR7 copy the NMI vector 00240h repeat 35 data 00COh AR7 copy INTO clear all memory locations of the sampling tabl table where the samples will be stored DP AD_DP TEMP 00000h repeat num_data_A 1 data data_loc_A TEMP fill memory table 1 repeat num_data_B 1 data data_loc_B TEMP fill memory table 2 repeat num_data_C 1 data data_loc_C TEMP fill memory table 3 repeat num_data_D 1 data data_loc_D TEMP fill memory table 4 if SEND OUT SERIAL kk ck k k k k k ck ck ck k x k k Sk K K K k k k ck kk Ck x k k ck ck lt lt ck kk KK KKK x k x KKK ck x x K kk Ck x x k x lt kk Sk kk Sk x lt Sk lt x k k lt lt lt KKK SERIAL_DAC_INI initialize the serial interface to send out the samples for the serial DAC set up the serial interface for a DSP DAC 5618A conversation jinitialize the SPI interface and the DAC the serial interface will be updated with the last sample if the serial buffer is empty after the last bit has been sent KKK k k k KKK k k k KKK KK k k k KKK KKK KK KKK k k K KK KKK KKK KKK K k k KKK KKK KKK KEK k k k KK k k k k k k k k k k k k KK 60 SLAA040 S
90. n Example GOTO MARK MARK DP 1 ARP 5 The program counter PC points after the last instruction ARP 5 past 6 sysclk cycles However this can be optimized using a delayed branch DGOTO MARK DP 1 ARP 5 MARK The time to execute the same number of instructions is now only four CPU clock cycles After four instructions the PC points to the address MARK The reason for this is the processor s pipeline finishes the instructions after dgoto and does not just trash the already processed fetch when the branch is in the pipeline s decoding state Conclusion The goto and dgoto instructions both execute the branch in less than four SYSCLCKs but the dgoto instruction can execute the next two instructions following dgoto in the same amount of time CAUTION Use the delayed branches carefully since it looks confusing when aninstruction has been executed after a call instruction A solution is to first use the normal branches when writing the code and when all tasks have been finished optimize the code with the delayed algorithms SLAA040 Software Overview 8 3 9 Enabling Software Modules if elseif endif To test different software solutions while keeping the number of files small requires integrating all the modules in the same file Furthermore a switch is needed to enable any of the software modules Setting the constant SWITCH in the program header to either one or zero enables disables the instructio
91. n as Marker in the code This helps to debug and verify the code Code verification The user only needs to edit the C1562 C software file and to run the AUTO BAT to adapt the acquisition This software samples one of the four channels with a specified number of samples and stores each sample into a defined memory location To verify the software the user must change the code in the C1562 ASM file and save those changes The next step is to recompile the four ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages the new output file is ready to load in the DSP program memory e g with the GoDSP development tools and to execute SLAA040 Software Overview 8 6 Source Code The following paragraphs contain the source code 8 6 1 Common Software for all Modes except C Callable The files shown below contained the actual C54x program listings and program examples 8 6 1 1 Constants asm KKK KKK ck x k k KKK KKK KKK ck x x k k x KK KKK x x lt ck x x k k KKK K K x x x x KKK KKK KKK KKK KK KKK k x k KK x x x KK TITLE TLV1562 ADC Interface routine FILE CONSTANT ASM FUNCTION N A PROTOTYPE N A CALLS N A PRECONDITION N A POSTCONDITION N A SPECIAL COND N A DESCRIPTION definition of constant values for interface software AUTHOR AAP Application Group
92. ng conversion purposes without having to use CS which always blocks the address bus Since the C542 DSP does not have enough general purpose outputs this application still uses the address bus to activate CSTART 6 3 6 Interfacing the Serial DAC 5618A to the DSP A buffered serial port on the C542 board interfaces the TLC5618A DAC The advantage of using a buffered serial port compared to the standard port is the auto buffer mode This allows the programmer to save CPU power A background process takes the data from a defined memory location table and moves it out to the serial port An interrupt can be generated after sending out half or the full table content However disabling this interrupt and writing the new ADC samples into the same memory location where the SPI takes the send value from allows continuous transmission of the data stream to the DAC When debugging the EVM it is preferable to compare the analog output signal of the DAC with the analog input signal applied to the ADC The TLC5618A is very easy to use The sample size is limited to 10 bits and the first six MSBs are set so that the converter outputs the value on the right pin in the right mode The next lines of code show the initialization The only requirement is to initialize the buffered serial port since the DAC does not need an initialization procedure BSPC 00000h reset SPI 00020h clear any pending SPI IRQ IMR 00020 allow BXINTO
93. nprogram MONOCON 1 asm ck k k k ck kk Ck x k k k KKK ck kk KK KKK KKK KK KKK x x x KKK x k x ck kk x x x KKK K x x kk x kk ck x x ko lt KKK KKK KK TITLE TLV1562 ADC Interface routine FILE MONOCON1 ASM FUNCTION MAIN PROTOTYPE void MAIN CALLS N A PRECONDITION POSTCONDITION N A DESCRIPTION main routine to use the mono continuous driven mode X AUTHOR AAP Application Group ICKE Dallas E CREATED 1998 BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 Data Aquisation Circuits TI 1998 ck k k k ck lt x k x k k k KKK KKK KK KKK KKK ck kk ck kk x kk Ck ck k k k ck kk x kk K ck ck K x x ko x x kk ck x x ko lt KKK KKK KK title 1 mmregs width 80 length 55 version 542 Setsect vectors 0x00180 0 sections of code Setsect text 0x00200 0 these assembler directives specify Setsect data 0x01800 1 the absolute addresses of different 3 Setsect variabl 0 01800 1 sections of code vectors copy vectors asm sect data copy constant asm AD DP usect variabl 0 Z ACT_CHANNEL usect variabl 1 jump address to init new channel ADWORD usect variabl 1 send bytes to the ADC ADCOUNT usect variabl 1 counter for one channel A
94. nput is equal to or greater than the voltage on VREFP and is zero scale when the input signal is equal to or lower than VREFM Input Data Bits The ADC contains the two user accessible registers CRO and CR1 All user defined features such as conversion mode data output format or sample size are programmed in CRO and 1 The data acquisition process must be started by writing to these two registers After this initialization the converter processes data in the same configuration until these registers are overwritten SLAA040 Operational Overview 3 3 Connections Between the DSP and the EVM The following connections provide the interface between the DSP and the EVM Table 1 Signal Connections DSP Signal Connector Pin on the DSKplus cir Connector Pin on ADC Signal cuit board the TLV1562EVM General GND Connector JP4 Pin 1 10 11 12 14 J10 2 J10 4 J10 34 GND 15 19 20 21 27 34 35 J11 4 J11 6 J11 26 Connector JP5 Pin 6 10 11 12 VCC JP1 32 NMA VCC Parallel Interface CLKOUT JP3 2 CLKIN INTO JP5 1 J115 INT XF JP4 8 J11 3 RD R W JP4 30 J11 9 decoded to the WR line lOSTRB JP4 36 e Mr decoded to the WR line AO JP5 34 J11 2 addr decoder for CS and CSTART A1 JP5 35 J11 addr decoder for CS and CSTART D0 JP3 35 OAS D0 D1 JP3 34 J10 15 D1 D2 JP3 8 QT D2 D3 JP3 12 0 19 D3 D4 JP3 11 J10 21 D4 D5 JP3 15
95. ns inside an IF ENDIF loop Example SWITCHI1 set 00001 SWITCH2 set 00000h if SWITCH1 instruction_X the instructions on this line will be assembled elseif SWITCH2 instruction Y the instructions on this line will be ignored endif In this example instruction X is executed linked into object code while instruction Y is ignored Setting SWITCH 2 instead of SWITCH7 to 1 enables instruction Y and makes the compiler link it to object code If both switches are one only instruction X is compiled 8 4 Software Code Explanation The next capture describes the software solution to interface the TLV1562 and the two DACs on the EVM board Although the code looks very large and complicated at first it is a simple solution with only a little knowledge of the code required to verify customize the settings The TLV1562 ADC offers a wide choice of settings First choose the conversation mode This application report provides one file for each mode Many settings 2s complement channels etc must be selected This software allows a variation of those parameters in the program header A simple switch enables or disables each component After recompiling the code with a special setting of all switches the code becomes much smaller and easier to understand The f elsif endif instruction allows the program to use or ignore blocks of instruction between the statements If for example one does not want to use the serial DAC and disable
96. nt pin to show a sample is available QCR PROBLEM SW PWDN NO AUTO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START port ADC 8 PROBLEM NOP write CRI port ADC CR1_SEND port DEACTIV ZERO ll NOP 62 SLAA040 Address decoder sets CS low WR low and send CR PROBLEM value to the ADC wait for tW CSH 50ns Address decoder sets CS low WR low and send CR1 value to the ADC deselect ADC CS high wait for tW CSH 50ns Software Overview write CRO port ADC CRO_SEND send CRO value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns KKK KKK KKK k k x KKK Ck x k k x KKK k k x KK KKK KKK KKK x x x KKK ADC mono IRQ Start read samples and store them into memory ck k k x lt ck ck Ck k x lt ck lt k k k ck x ck ck x ck k x ck x ck k k ck lt ko lt k x x ko oko ADC_mono_IRQ_Start 5 2 0 clear CSTART ISTEP3 NOP NOP NOP wait for TW CSTARTL ISTEP4 XF 1 set CSTART STEP5 1 POLLING_DRV wait until INT goes low in polling the INTO pin 1 TC bit AR5 15 0 test is the INTO Bit in IFR 1 if NTC goto 1 wait until INT signal goes high IFR 1 reset any old interrupt on pin INTO elseif INTO DRIVEN user main program area this could execute additional code go
97. nt pin to show a sample is available QCR PROBLEM 511 PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START port ADC PROBLEM Address decoder sets cs low WR low and send CR_PROBLEM value to the ADC NOP wait for tW CSH 50nS write CR1 port ADC CR1_SEND Address decoder sets CS low 2 WR low and send CR1 value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns write CRO port ADC CRO_SEND send CRO value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns return return from call endif endif Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 57 Software Overview 8 6 4 Mono Mode Interrupt Driven Software Using CSTART to Start Conversion Mainprogram Monomode asm KKK KK k k k KK KKK k k k KKK KKK KK KKK k k x KK KKK x x x KKK x k k KKK KKK KKK KEK KKK KK KKK KKK k ko kc KKK KK TITHE TLV1562 ADC Interface routine FILE MONOCST1 ASM FUNCTION MAIN PROTOTYPE void MAIN CALLS N A d PRECONDITION N A POSTCONDITION N A SPECIAL COND ARO protected in use for the data storage procedure 5 AR5 protected in use for polling IFR only for software polling solution Bs AR7 protected in use for the data s
98. nt a significant design problem because hardware and software must work together across the interface to produce a usable complete design This application report provides a design solution for the interface between the TLV1562 10 bit parallel output analog to digital converter ADC and the TMS320C54x digital signal processor DSP The report describes the hardware and software needed to interface the C54x DSP to the TLV1562 ADC which is intended for applications such as industrial control and signal intelligence in which large amounts of data must be processed quickly The first sections describe the basic operation of the TLV1562 For additional information see the References section at the end of this report 2 The Board TLV1562 evaluation module EVM is a four layer printed circuit board PCB constructed from FR4 material The PCB dimensions are 180 mm x 112 mm x 12 mm Ribbon cables are used to interface the TLV1562EVM to the TMS320C54x DSK plus starter kit 2 1 TMS320C54x Starter Kit The starter kit simplifies the task of interfacing to the 54 processor It comes with an ADC for voice bandwidth and GoDSP code explorer as the software tool A 10 2 oscillator provides the clock signal to allow 40 MHz internal DSP clock cycles generated by the internal DSP PLL Therefore the board provides 40 MIPS of processing power Ribbon cables are used to connect the DSP with the EVM Detailed descriptions of all connections
99. numbers for memory addresses or constants very often symbols replace the numbers For that the symbol name is assigned with the real value number in the file header The advantage of doing this is the higher flexibility Instead of changing a variable memory location in every related instruction the value forthis location is changed only once in the program header This prevents software bugs from appearing through a forgotten correction of a related instruction BSPC BUFFER START set 00800h memory location 800h for the start address of the SPC buffer GAXR BSPC BUFFER START assign the starting address of auto buffer Software Development tools The DSKplus Starter Kit of the TMS320C54x comes with a free compiler to generate an absolute object file from assembler code DSKPLASM EXE the TMS320C54x DSKplus development tools The object code is then loaded into the GoDSP software to run it on the kit An advanced version of this kit is the TMS320C54x Optimizing C Compiler Assembler Linker for example TMDS324L855 02 These tools allow generation of object code from C and assembler files Furthermore they also link the code to an executable COFF file The software in this report was created with these tools For more information visit Tl s Internet page at http www ti com sc docs dsps tools c5000 c54x index htm 8 2 DSP Memory Map Figure 6 shows the memory map assigned to the application PROGRAM MEMORY on
100. o interrupt driven mode and the CSTART signal to CPU power for the conversion time AAP Application Group Dallas CREATED 1998 BY TEXAS INSTRUMENTS INCORPORATED 5320 54 User s Guide TI 1997 Data Aquisation Circuits TI 1998 x KKK KKK k k k KKK x k k KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KEK KKK KK KKK KKK k k k KKK KK title DUALIRO1 mmregs width 8 length 5 version 542 setsect lt Setssct sSetsect setsect 0 5 m sect vectors Copy AD_ DP ct data u Sect vectors asm constant asm m variabl 0 ACT CHANNEL usect variabl ADWORD ADCOUNT ADM 66 EM usect m variabl usect variabl variabl SLAA040 1 1 1 1 vectors 0x00180 0 text 0 00200 0 data 0 01800 1 variabl 0x01800 1 sections of code these assembler directives specify the absolute addresses of different sections of code jump address to init new channel send bytes to the ADC counter for one channel points to act memory save location CRO_SEND usect variabl 1 CR1 SEND usect variabl 1 CR PROBLEM usect variabl 1 ZERO usect variabl 1 TEMP usect variabl 1 isr save usect variabl 1 CH1 ADSAMPLE usect variabl 1 CH2 ADSAMPLE usect
101. oc_B Figure 9 Flow Chart Dual Interrupt Driven Mode Using CSTART to Start Conversion Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 35 Software Overview 8 5 4 Mono Continuous Mode 36 The following descriptions explain the software for the data acquisition in Mono Continuous Mode The required interface connections are shown in Figure 2 Program 1 CALIBRAT CONSTANT VECTORS Files 5 5 5 5 Other Files linker cmd auto bat asm500 e lnk500 e xe xe Includes the complete software algorithm to control the Mono Continuous Mode Calibration procedure of the DAC Common file of all modes constants definition Common file of all modes IRQ vector table Organization of the DSP memory data and program memory Batch file to start the compiler for the mono continuous software C54x Code compiler C54x linker The timing requirements to interface the C54x to the ADC are provided in Table 11 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Code verification To verify the software the user must change the code in the MONOCON 1 ASM file and save those changes The next step is to recompile the four ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages the new output file is ready to load in the DSP program memory e g with the
102. ode Using CSTART Use the CSTART signal when two or more ADCs must sample convert signals at the same time Instead of the RD signal the timing for sampling and converting is started with the edges of the CSTART signal The RD signal is still required to get the data out of the ADC and onto the bus Table 8 DSP Algorithm for Mono Interrupt Driven Mode Using CSTART Wait cycles for the DSP internally 40 2 DSPCLK STEPS TIMING NOTES APD 0 APD 0 APD 1 APD 1 ADCSYCLK ADCSYCLK ADCSYCLK ADCSYCLK 7 5 MHz 10 MHz 10 MHz 1 SetCS Deselect ADC Wait for tw csTARTL tw CSTARTL 100 ns APD 0 gt 24 iw CSTARTL 600 ns APD 1 TD i 5 Wait until INT goes low Alternative ignore the INT signal 233 221 wait 14ns 5 ADCSYSCLK and goto step number 7 6 Wait the time 51 10 ns Ea 7 Clear CS Select the ADC gl 8 Clear RD Start communication 9 Wait the time tEN DATAOUT tEN DATAOUT 41 ns gt 10 Read sample out from the data port Reset RD signal 12 Goto step 2 for the next samples 14 SLAA040 Conversation Between the TLV1562 and the DSP 7 4 Dual Interrupt Driven Mode Using techniques similar to those described in the first two modes for sampling converting sending tasks the dual mode samples two channels at the same time and sends out the results in series to the data port The CSTART pin is used to start sampling and converting
103. of the clock signal The user must adhere to this timing otherwise the conversion result may be wrong The user may not recognize the erroneous result since the ADC will signal that the conversion has finished during the logic low transition of the INT signal The following timing diagram shows the interface behavior of the ADC whether the timing is correct or not The following figure shows what happens when the RD falling edge is timed wrong Although RD falls nearly 1 2 of one cycle too late the conversion result is valid on the 5th clock cycle 1 2 3 4 5 6 7 8 9 10 m NX do NN Conversion Starts Next Sampling Starts Conversion Finished 2 4 Onboard Components These sections describe the EVM onboard components 2 4 1 TLC5618A Serial DAC This 12 bit DAC has a serial interface that can run at 20 MHz clock therefore it can update the output at 1 21 MSPS Two outputs are available on the 8 pin package The buffered SPI of the DSP provides the DSP interface Using the auto buffer mode updating the data on the DAC requires only four CPU instructions samples 4 SLAA040 Serial DAC cs TLC5618A The Board DSP BCLKX BCLKR BFSX TMS320C542 BFSR BDX BDR TLV1562 EVM Pin Connector Figure 3 TLC5618A to C542 DSP Interface 2 4 2 THS5651 Parallel Output CommsDAC This 10 bit data converter has a parallel interface and is able to update its output with 100 MSPS The two out
104. ort OFFFFh set address bus to FFFFh and write 1234h for one cycle on the DATA bus 8 3 2 2 Reading Smem PORT Reading from the I O bus PA sets the ADDRESS bus Smem is a memory cell PA the address on the bus 8 3 3 Timer Output TCR 00010h deactivate timer PRD 00000h E TCR 00 01 set timer output toggling frequency to CLKOUT frequency and start toggling 20 SLAA040 Software Overview The timer output pin TOUT can be used to generate an output function with a prescale from half the CLK frequency down to 1FFFF The problem the high time is always one clock cycle and only the low time of the TOUT signal changes with the timer 8 3 4 Data Page Pointer DP 0 load DP with 0 DP variable point with DP to the page where variable is stored DP register error this won t work the DP gets not loaded with register page instead load DP with zero If a register has to be written example IFR the DP has to be loaded with zero since DP register will not work 8 3 5 Generating the Chip Select Signal and the CSTART Signal port CSTART ZERO clear CSTART CSTARTlow port ADC QCRO SEND Clear 5 CSlow port DEACTIVE ZERO set CS or CSTART back CS high or CSTARThigh The chip select signal and the CSTART signal can be accessed using the address bus decoder on 0 1 The basic idea of having CSTART was to allow ADC triggering for sampli
105. puts on the 28 pin package can each drive a current between 2 mA and 20 mA with an output resistance gt 100 kQ ideal current source output impedance e The data bus and the address decoder provide the interface to the DSP Parallel DAC CLK THS5651 DSP CLKOUT TMS320C542 A 0 1 11b D 0 9 Figure 4 THS5651 to C542 DSP Interface Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 5 Operational Overview 3 Operational Overview 3 1 3 2 This chapter discusses the software and hardware interface for the TLV1562 Plus the overall operational sequence of the A D interface is described Reference Voltage Inputs The voltage difference between the VREFP and VREFM terminals determines the analog input range i e the upper and lower limits of the analog inputs that produce the full scale output data all 1s and zero scale output data all Os readings respectively For design reasons this high speed sampling ADC does not have a ground referenced input voltage range Hence level shifting is required unless the application allows the signal to be ac coupled Level shifting could be done with single supply op amps The absolute voltage values applied to VREFP VREFM and the analog input should not be greater than the AVpp supply minus 1 V or lower than 0 8 V Other input restrictions apply so consult the TLV1562 data sheet for further information The digital output is full scale when the analog i
106. rallel ADC to the TMS320C54x DSP 31 Software Overview 8 5 2 1 Throughput Optimizationt According to the data sheet the mono interrupt driven mode with CSTART starting the conversion can be described as follows After the conversion is done INT set low the DSP e selects the converter brings down the RD signal e waits until the data are valid e reads the data from the ADC and e resets RD to a high signal level e Now CSTART can be pulled low for at least 100 ns and set high to start a new conversion As tests showed it does not matter at what time the CSTART signal gets pulled low to start the sampling Changing the signal flow slightly by pulling CSTART low before the ADC output data are read on the data bus will save at least of 100 ns of CSTART low time after read instruction additional advantage the longer the analog input is sampled the more precisely the sampling capacitor will be charged assuming that the noise located by RD is negligible In this algorithm CSTART can be taken high right after the data has been read by the DSP without any wait instruction Therefore the maximum throughput is gained because the 100 ns sampling time is saved Test results showed a maximum throughput of more than 1 2 MSPS approximately 20 of gain in throughput with the internal ADC clock when using this strategy see Figure 8 A concern is that possible small spikes during conversion at the same time as the data get
107. rameters are identical for all ADC modes Therefore the two files will be used for each mode and are described next CONSTANT ASM __ Definition of constant values as it is the bit code for different VECTORS ASM CALIBRAT ASM ADC modes 0 1 the serial DAC send words and the DSP memory saving locations Interrupt vector table of the TMS320C542 ADC calibration procedure except for mono interrupt driven mode using RD this mode has not implemented any calibration so far 8 5 Flow Charts and Comments for All Software Modes The following paragraphs show the flow charts and include comments for all software modes 8 5 1 The Mono Interrupt Driven Mode Using RD to Start Conversion The following descriptions explain the software for the data acquisition in monomode The required interface connections are shown in Figure 1 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 27 Software Overview 28 Program Files MONOIDM1 ASM_ includes the complete software algorithm to control the monomode CONSTANT ASM common file of all modes constants definition VECTORS ASM Other Files linker cmd auto bat asm500 exe lnk500 exe The timing requirements to interface the C54x to the ADC are provided in Tables 6 and 7 The STEP numbers given there can be found again as Marker common file of all modes IRQ vector table organization of the DSP memory data and program memory batch file to start the compil
108. rt AR7 data_loc_A point to first date location of the storage table AR6 data_loc_B point to first date location of the storage table endif STORE END RETURN jump back into data aquisition routine ck k k ck Ck ck ck Ck k KKK Ck k k x lt Ck ck ck k k k K ck x k k ck lt ck ck k ck x ck ck lt k k x ck x ck ck k x lt x lt x x x lt x INTO Interrupt routine of the external interrupt input pin INTO ck ck Ck KKK KKK KKK KKK KKK KKK KKK KKK KKK k k x KK ck k k KKK KK k x lt lt lt ck x x KKK x x x lt lt KK IRQ_INTO return_enable interrupt is not in use KEK KKK KKK KKK k x lt KKK k k k KKK KK KKK KKK k x lt KKK KKK KKK x k k KKK K k k k lt lt lt k k x lt x k k k k k k k KKK KK BXINTO Interrupt routine of the serial transmit interrupt of the buffered SPI KKK k x lt KKK k x K KKK k k k KKK x k KKK KKK KKK KKK KKK KKK ck k k KKK lt k k x lt lt lt k k x lt x lt KKK KKK KK KKK BXINTO return_enable interrupt is not in use sect text calibrat asm end Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 85 Software Overview Constants definition see 8 6 1 1 Constants asm Interrupt Routine handler see 8 6 1 2 Interrupt Vectors 8 6 8 C Callable Mainprogram 1562 File 1562 x This file will select the parameters to allow a C call of the ADC sampling extern void TLV1562 int int int
109. s External CALIB OP set 00000h Operate with the calibrated inputs SYS OFF CALIB set 00040h do a system offset calibration INT OFF CALIB set 00080h do a internal offset calibration Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 41 Software Overview NO_CALIB_OP set 000 0 INDEX MOD NO_SW_PWDN SW_PWDN NO_AUTO_PWDN AUTO_PWD Set Se Se TWO COMPLEM EN NO 2COMPLEM EN NO DEBUG DEBUG MOD P ES 10 RES 8 BI RES 4 BI CST CONV START Example to use Set the sending calibrated inpu send 3 port xxxxh Dk k ck K ck KKK k k ck KKK k k k KKK k k k KKK lt k k lt lt KKK x K lt lt ck x ck K x lt lt x x x x ko memory organiza RD_CONV_START Se Se Se Se Se CH4 tion Se value send k k KKK lt k k k KKK KKK KK KKK num_data_A num_data_B num_data_C num_data_D data_loc_A data_loc_B data_loc_C data_loc_D TRASH Set t 00100 00101 t 00100 t 00102 t 00100 t 00104 t 00000 t 00108 t 00100 t 00120 t 00110 t 00100 t 00140 Operate without calibrated inputs no offset n n the constants F Software power down mode disabled instruction for sof
110. s read onto the data bus might worsen the analog input signal accuracy Some measurements could help here to verify the applicability of the throughput optimization A concern is that during conversion if any small spikes occurs on the CSTART signal while the ADC data is being read out onto the data bus then the accuracy of the ADC quantized output data could be affected This only works for one TLV1562 not multiple because CS is not used 32 SLAA040 Software Overview CSTART cs la g nene Figure 8 Time Optimization monocst1 Performance at 1 2 MSPS with Internal Clock INT 8 5 3 Dual Interrupt Driven Mode The following descriptions explain the software for the data acquisition in Dual Interrupt Driven Mode using the CSTART signal The required interface connections are shown in Figure 2 Program Files DUALIRQ1 ASM Includes the complete software algorithm to control the Dual IRQ Driven Mode CALIBRAT ASM Calibration procedure of the DAC CONSTANT ASM file of all modes constants definition VECTORS ASM Common file of all modes IRQ vector table Other Files linker cmd Organization of the DSP memory data and program memory auto bat Batch file to start the compiler for the dual interrupt driven software asm500 exe 54x Code compiler 1nk500 exe C54x linker The timing requirements to interface the C54x to the ADC are provi
111. s the switch SEND OUT SERIAL all the source code for the serial conversation between DSP and DAC is ignored The compiler will not implement any code related to the serial DAC 8 4 1 Software Principals of the Interface Controlling the status of signals can be done in different ways One of the challenges in this interface is controlling signal status when the ADC conversion is finished and the digital result is ready to be transferred from the ADC to DSP A high low transition on the INT line of the TLV1562 informs the DSP that the ADC has completed the conversion Optionally the DSP can ignore the INT signal initialize the conversion instead wait for a defined time and directly read the result out of the ADC This solution requires knowing the precise time for conversion data ready on the bus for each converter mode Three options are given for each mode to match different custom needs they are listed in the next three sections Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 23 Software Overview 8 4 1 1 Software Polling The status of the input pin is tested in a loop until the valid transition occurs After this transition the program branches to the next instruction reads data sample Advantage Relatively fast program response after high to low transition of INT e The software compensates for variations of timing given in data sheets for conversion and the real time until the flag goes high e Not crit
112. s to counter for one points to act when using any of the following variables init new channel channel memory save location ADSAMPLE 5618 convers ERIAL SEND other usect usect sect ation usect usect Software Overview variabl 1 sent value to register CRO of the ADC r variabl 1 sent value to register CR1 of the ADC variabl 1 the value zero to send a Zero Dummy variabl 1 last read sample from the ADC variabl 1 serial output send word variabl 1 temporary variable can be changed anywhere during Address Decoder constants CSTART ADC DAC1 DEACTIV set timing mode POLLING_DRV is done INTO_DRIVEN NO_INTO_SIG timing solution SAVE_INTO_MEMORY constants asm SEND_OUT_SERIAL SEND_OUT_PARAL H E R1OBIT_RESOLU R8BIT RESOLU RABIT RESOLU INTERNAL CLOCK EXTERNAL CLOCK AUTO PWDN ENABLE DIFF INPUT MODE sect text JM MAIN START INITIALIZATION Set the program 00001h activate A1 when CSTART is choosen 00002 activate 2 when TLV1562 is choosen 00003h activate when DAC1 is choosen 00000h deactivate the address lines A0 A1 and A2 use od
113. sen DEACTIVE set 00000 deactivate the address lines A0 A1 and 2 SAVE INTO MEMORY set 00001h store the samples into DSP memory SEND OUT SERIAL set 00000h store the last sample allways into serial buffer memory SEND OUT PARALLEL set 00001h store the last sample allways into DACI R1LOBIT_RESOLU set 00001 use maximum resolution of 10 bit R8BIT_RESOLU set 00000 use 8 Bit resolution R4BIT_RESOLU set 00000 use fastest mode 4 Bit resolution INTERNAL CLOCK set 00001 use the internal clock of the ADC EXTERNAL CLOCK set 00000h use the external clock of the ADC DIFF INPUT MODE set 00000h use differential mode instead of single ended inputs IME CALIBRATIO set 000008 do an Internal Midscale Error Calibration SME CALIBRATIO set 00000 do a System Midscale Error Calibration sect text JM MAIN START INITIALIZATION disable IRQ sign extension mode ini Stack INTM 1 disable IRQ SXM 0 no sign extension mode z SP 0280h initialize Stack pointer initialize waitstates DP 00000h point to page zero SWWSR 01000h one I O wait states copy interrupt routine which are uncritical by the EVM to the IRQ table location this is required for the DSKplus kit but has to be changed on other platforms DP 1 point to page 1 vector table AR7 00200h repeat 3h data 0084h AR7 copy the NMI vector AR7 00240h
114. some instructions especially branch instructions are not single cycle instructions therefore they lower the available CPU power Because of the high transfer rate of the TLV1562 ADC the software code must be optimized to test the full ADC performance Since correct signal timing between DSP and ADC requires some instructions per sample the CPU power required between two samples is very small The optimum case is to read a new sample store it into memory execute a customized task as it could be data filtering FFT FIR IIR and send a digital result to one of the DACs Unfortunately this task is impossible at the ADC s maximum throughput of 40 MIPS Therefore this software only stores the samples and optionally moves them out to the DACs Enabling all options at the same time prevents the application from running at maximum throughput The following switches enable disable these actions SAVE INTO MEMORY set 00001h set 1 to store the samples into memory SEND OUT SERIAL set 00001h set 1 to send last sample to the serial DAC SEND OUT PARALLEL set 00001h set 1 to send last sample out to the parallel DAC 8 3 2 Address and Data Bus for I O Tasks 8 3 2 1 Writing PORT PA Smem Writing something to the I O bus uses the portinstruction PA sets the ADDRESS bus permanently to that value Smemis a value from memory transferred for one clock cycle to the DATA bus send 01234h set the content of memory address send to 1234h p
115. t variabl ADCOUNT usect variabl ADMEM usect variabl CRO SEND usect variabl CR1 SEND usect variabl PROBLEM usect variabl ZERO usect variabl TEMP usect variabl 80 SLAA040 sections EXAS INSTRUMENTS INCORPORATI tinuous driven mode las Eri 8 KKK k K k k k ck KK KKK k x lt KEK k k k KKK KKK k x lt KEK KKK KKK KKK KKK lt x kc x x lt f code thes the absolu Sections o jump addre send bytes counter fo points to the last v the last v problem wi assembler directives specify te addresses of different f code ss to init to the ADC r one channel act alue alue th initialization of this mode when repea the value 7 temporary ted reset zero to send variable new channel memory save location sent to register CRO sent to register Software Overview isr_save usect variabl 1 memory location to save AR7 during interrupts CH1_ADSAMPLE usect variabl 1 last readed sample of channel 1 CH2_ADSAMPLE usect variabl 1 last readed sample of channel 2 Address Decoder constants ADC set 00002h activate AO when TLV1562 is choosen RD_CALIBRATION set 00001 activate Al when CSTART is choosen DAC1 set 00003h activate 2 when DAC1 is choo
116. t lt 2 leftshift of the sample for a 12 bit format ADSAMPLE A z ADSAMPLE TLC5618_LATCH_A TLC5618_FAST_MODE TLC5618_POWER_UP set the mode of the DAC data BDXR ADSAMPLE send out the sample to the serial DAC SEND SERIAL END endif if SAVE INTO MEMORY test for table end set pointer back if true TC ARO AR7 is ARO AR7 table end reached if NTC goto STORE_END Z set pointer back to table start AR7 data_loc_A point to first date location of the storage table endif STORE_END RETURN jump back into data aquisition routine KKK KK k k k KK KKK k k k KKK k k k K lt KKK x k K KKK KK k x lt KKK x k x KKK KKK KKK KKK KKK KKK IRO INTO Interrupt routine of the external interrupt input pin INTO kk ck Ck k k k k k K KKK k k k KKK k k k K x KKK k k x KKK ck kk x kk Ck kk k k K kk Sk kk Sk lt k k k k k k ko KKK IRQ_INTO call STEP7 initialize the next conversion and store results return_enable return from IRQ wake up from the IDLE mode KKK K k k k k lt x k x k k k KKK ck x k x lt KKK x k k KKK K x x K x lt KKK k k lt lt lt k x x x lt lt lt lt k x k x lt lt Sk x x K lt k lt kc lt x BXINTO Interrupt routine of the serial transmit interrupt of the buffered SPI KKK k k K KKK k k k KKK KK x k x KKK k k k KKK KKK KKK KKK KKK KKK KKK x x KK KKK KKK KKK KKK KKK KK KKK BXINTO return_enabl
117. t cases the ADC come out of the 3 state mode and supplies the correct voltage levels onto the bus lines in less than 50 ns Thus the minimum number of I O wait states becomes two for tEN DATAOUT 90 ns TLV1562 TMS320C54x XF 01 Address AO 10 Decoder M 11 IOSTRB R W 1 x Nd D 0 9 Figure 2 TLV1562 to C54x DSP Interface of the EVM Using RD or the CSTART Signal to Start Conversion 2 3 2 Recyclic Architecture One specialty of this ADC is its recyclic architecture Instead of limiting the device power by the highest possible resolution at the fastest speed this converter is able to work at three maximum speeds for three resolutions The highest resolution runs at 2MSPS maximum throughput rate 8 bit resolution corresponds to 3MSPS and 4 bit resolution to 7MSPS Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP The Board The Board This feature fits well into monitoring application For example the ADC may have to trigger on one event out of some channels inside an extremely small time window and then sample the correct channel with a higher resolution but lower throughput to analyze this process This feature also fits well into home security applications or applications that must monitor several inputs simultaneously 2 3 3 Note on the Interface Using an External ADC Clock Drive The TLV1562data sheet Figure 9 shows that RD has to fall as close as possible to the falling edge
118. temporary variable can be changed anywhere during the program activate A1 when RD CALIBRATION is choosen activate A2 when TLV1562 is choosen activate when DAC1 is choosen deactivate the address lines A0 A1 and A2 or timer software polls the INTO pin to wait until conversion is done software uses Interrupt INTO to organize conversion INTO signal not in use interface is controlled with timing solution store the samples into DSP memory defined in constants asm send the samples always to the serial DAC update always the parallel DAC with the last sample DACI use maximum resolution of 10 bit use 8 Bit resolution use fastest mode 4 Bit resolution use the internal clock of the ADC use the external clock of the ADC ADC goes into power reduced state after conversion use differential mode instead of single ended inputs do an Internal Midscale Error Calibration do a System Midscale Error Calibration Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 59 Software Overview _MAIN START INITIALIZATION disable IRQ sign extension mode ini Stack 1 disable IRQ SXM 0 no sign extension mode s SP 0280h initialize Stack pointer initialize waitstates DP 00000h point to page zero SWWSR 01000h one I O wait states copy interrupt routine which are not critical for the EVM to the IRQ table locatio
119. torage procedure DESCRIPTION main routine to use the mono interrupt driven mode X and the CSTART signal to CPU power for the conversion time AUTHOR AAP Application Group ICKE Dallas i CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 5320 54 DSKPlus User s Guide TI 1997 5 Data Aquisation Circuits TI 1998 KKK k k k KKK x k k KKK KKK KKK KKK k k x KKK KKK KK KKK k k k KKK KKK KKK KEK KKK KKK KK x k k KKK KKK KK title 5 1 mmregs width 80 length 55 version 542 the next 4 lines setsect have to b nabled if the DSKplus code generator instead of the asm500 exe tools are in use Setsect vectors 0x00180 0 Sections of code Setsect text 0x00200 0 these assembler directives specify f Setsect data 0x01800 1 the absolute addresses of different Setsect variabl 0x01800 1 Sections of code sect vectors copy vectors asm sect data constant asm ADC conversation AD DP usect variabl 0 pointer address when using any of the following variables ACT CHANNEL usect variabl 1 jump address to init new channel 58 SLAA040 ADCOUNT usect ADMEM usect CR0_SEND usect CR1 SEND usect CR PROBLEM usect ZERO usect ADSAMPLE usect TLC5618 conversa SERIAL_SEND usect other TEMP usect
120. tream the cs should not become high before end of sending the 16th bit DP AD_DP reset Data page pointer to variables A ADSAMPLE lt lt 2 leftshift of the sample for a 12 bit format ADSAMPLE A ADSAMPLE TLC5618_LATCH_A TLC5618_FAST_MODE TLC5618_POWER_UP set the mode of the DAC data BDXR ADSAMPLE send out the sample to the serial DAC SEND SERIAL END 78 SLAA040 Software Overview endif if SAVE INTO MEMORY test for table end set pointer back if true TG ARO AR7 is ARO AR7 table end reached if NTC goto STORE_END set pointer back to table start AR7 data_loc_A point to first date location of the storage table endif STORE END RETURN jump back into data aquisition routine KKK KKK ck Ck ck k k KKK k k k KKK KKK k kk ck kk x x x lt ck ck x x k kk ck x x x x x lt lt lt x x x x ko KKK x x x lt lt IRQ INTO Interrupt routine of the external interrupt input pin INTO ck k k ck Ck ck ck Ck k x K k k K lt ck ck k k x ck ck ck k x x lt lt k k x lt ck lt k k x ck ko ck kk x kk lt x x x lt x IRQ_INTO return_enable interrupt is not in use KKK KKK ck k k k x lt KKK k k k KKK x k KKK KKK KKK KKK KKK KKK KKK x lt x lt k k x K lt lt k k x K lt k k k X KK KKK KKK BXINTO Interrupt routine of the serial transmit interrupt of the b
121. ts becaus pin to show a sample is available 511 PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START PROBLEM port ADC QCR1 SEND port DEACTIVE ZERO NOP write CRO port ADC CRO_SEND STEP1 port DEACTIVE 42 ERO NOP Address decoder sets Cs low WR low and send CR_PROBLEM value to the ADC wait for tW CSH 50ns Address decoder sets CS low WR low and send CR1 value to the ADC deselect ADC CS high wait for tW CSH 50ns send CRO value to the ADC deselect ADC CS high KKK KKK k k k lt KKK k k k KKK KKK KKK KKK KKK KKK KKK KKK KKK ADC_mono_IRQ_ Start read samples and store them into memory KKK k k k KKK KKK KKK K x k k k KKK KKK KKK KKK KKK KK KKK KKK 88 SLAA040 Software Overview ADC mono IRQ Start ISTEP2 XF 0 clear CSTART ISTEP3 NOP NOP NOP wait for TW CSTARTL ISTEP4 XF 1 set CSTART STEP5 wait until INT goes low in polling the INTO pin M1 TC bit AR5 15 0 test is the INTO Bit in IFR 1 if NTC goto 1 wait until INT signal went high IFR 1 reset any old interrupt on pin INTO read sample STEP2 XE 0 clear CSTART STEP10 ADSAMPLE port ADC read the new sample into the DSP STEP4 XF 1 wait for TW CSTARTL and set CSTART KKK KKK ck Ck x k k
122. tware power down Automatic internal power down Disabled Automatic internal power down Enabled ADC output in 2s complement format ADC output is binary not in 2s complement Debug mode disabled Debug mode enabled 10 bit resolution of the ADC 8 bit resolution of the ADC 4 bit resolution of the ADC start Conversion by RD Signal start Conversion by CSTART Signal decribed on the top ts into Mono Continuous MONO_CONTINUOUS SINGLE send to sampling Channel 4 with external clock source ode END CLK EXTERNAL CALIB OP Send the value over the Data lines to the TLCV1562 KKEKKKKK table write of samples for the C54x KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKE t 00200 Number of data from channel t 00200 Number of data from channel t 00200h Number of data from channel t 00200h Number of data from channel D t 02000 Start data location for channel A t 02200 Start data location for channel B t 02400h Start data location for channel C t 02600h Start data location for channel D 02000h address to waste the first input sample f after initialization KKK KKK KKK ck k k KKK KKK k k lt KKK KK KK KKK k k x KKK KKK KKK KKK KKK KKK KKK bit se tting of the serial DAC to match the right mode KKK KKK KKK k k k KK KKK k k x KKK k k k KKK x x x KK KKK KKK KKK KKK KKK KKK KKK 561 TLC561 TLC561 8 8 TLC56 TLC56 TLC56 T
123. uffered SPI KKK KKK lt lt k KKK KKK ck k k KKK x k KKK KKK KKK KKK k k k KKK lt k k KKK lt k k k k amp k k k X k k k k Sk k KK KKK KKK BXINTO return_enable interrupt is not in use sect text calibrat asm end Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 79 Software Overview Constants definition see 8 6 1 1 Constants asm Interrupt Routine handler see 8 6 1 2 Interrupt Vectors 8 6 7 Dual Continuous Mode Mainprogram DUALCON1 asm KKK KK k k k KK KKK k k lt KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK x x KKK KKK KKK KKK KKK KKK KKK KKK PEGE FILE UNCTION ROTOTYPE ALLS RECONDITION OSTCONDITION ESCRIPTION Pr oO UV UTHOR TLV1562 ADC Interface routine DUALCON1 ASM MA void MAIN IN N A N A N A main routine to use the mono con AAP Application Group ICKE Dal CREATED 1998 C BY TI TMS320C54x User s Guide TI 1997 Data Aquisation Circuits TI 199 lt lt K k k k KKK KKK KKK ck kk title DUALCON1 mmregs width 80 length 55 version 542 Setsect vectors 0x00180 0 Setsect text 0x00200 0 setsect data 0 01800 1 3 Setsect variabl 0x01800 1 Sect vectors copy vectors asm Sect data copy constant asm AD DP usect variabl 0 ACT CHANNEL usect variabl ADWORD usec
124. us 16 11 DSP Algorithm for Dual Continuous Mode 17 12 Switch Settings ence Radi ned ia ait Pail ae bial oa Pa al Aad a Paes 26 13 Instruction in the Program Header Step 1 26 14 Instruction in the Program Header Step 1 27 Interfacing the TLV1562 Parallel AD Converter to the TMS320C54x DSP M vi SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP Falk Alicke and Perry Miller ABSTRACT In this application report we discuss the hardware and software interface of the TLV1562 10 bit parallel output analog to digital converter ADC to the TMS320C54x digital signal processor DSP The hardware interface board or evaluation module EVM consists of the TLV1562 10 bit ADC a THS5651 10 bit parallel output communication digital to analog converter CommsDAC and a TLC5618A serial output digital to analog converter DAC Following the discussion of the ADC we explain the need for both the THS5651 CommsDAC and the TLC5618A serial DAC The application report concludes with several software application examples and recommendations for simplifying the software through modifications of the DSP hardware interface circuit 1 Introduction The analog to digital A D interface can prese
125. utobuffer Mode 0CO78h start serial port enable global interrupt this is even required if no IRQ routine is used by this program because the GoDSP debugger needs to do its backgroud interrupts INTM initialize s AR7 ARO DP DP ZERO ADCOUNT 0 enable global IRQ torage table for the ADC samples data_loc_A point to first date location of the storage table num data A data loc A ARO points to table end AD DP num data A initialize ADCOUNT with the number of required samples AD DP 00000 set the dummy send value initialize the send values to set up the two programmable register of the ADC QGCRO SEND GQCR1 SEND CONTINUOUS SINGLE END CLK INTERNAL NO CALIB OP SW PWDN NO AUTO PWDN NO 2COMPLEMENT NO DEBUG RES 10 BIT RD CONV START change some of the possible modes by variation of the bit setting in the file header this nex if R8B GCR1 S END END t step can be erased if the user is running in only one special configuration IT RESOLUT CR1_SI RES_10_BIT clear bit for 10 Bit Resolution RES_8 BIT set 8 Bit conversion mode elseif R4BIT_RESOLUT 82 SLAA040 Software Overview CRI_SEND RES_10_BIT clear bit for 10 Bit Resolution GCR1 SEND RES_4 BIT set 8 Bit conversion mode endif if EXTERNAL CLOC
126. version is finished the ADC clears the INT signal purposes Next the ADC writes the conversion result to the data port The rising edge of RD resets this status in other words the INT signal goes back to logic high and the conversion result on the data port becomes invalid the ADC data port gets 3 stated The configuration data needs to be written only once to the ADC After this toggling the RD signal runs the ADC in a sampling conversion sending mode and the RD signal releases every new cycle 12 SLAA040 Conversation Between the TLV1562 and the DSP Table 7 DSP Algorithm for Mono Interrupt Driven Mode Using RD Wait cycles for the DSP internally 40 MHz DSPCLK TIMING NOTES 0 Initialization Write all configuration data to the activate the mono interrupt driven mode ADC in CRO 2 3 2 clear CS Select ADC Note if Hardware Auto power down is enabled Chip select has to be used otherwise CS can be left high E edd tp CsL sample 515 APD 0 tp CSL sample 500ns APD 1 tp cSL sample 1 ADCSYSCLK 5 Wait until INT goes low alternative ignore the INT signal wait 49 ns 5 6 ADCSYSCLK and goto step number 7 6 Wait the time tEN DATAOUT teN DATAOUT 41 ns 7 Read sample out from the data port Reset RD signal 8 Goto step 1 or step 3 if APD 0 for more samples Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 13 Conversation Between the TLV1562 and the DSP 7 3 Mono Interrupt Driven M

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