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Texas Instruments DM648 DSP User's Manual

1. 45 A 1 Document Revision History netur anie meer waa sa 46 SPRUEK5A October 2007 List of Tables 5 Submit Documentation Feedback 35 TEXAS Preface INSTRUMENTS SPRUEK5A October 2007 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320DM647 DM648 Digital Signal Processor DSP Notational Conventions This document uses the following conventions e Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h Registers in this document are shown in figures and described in tables Each register figure shows a rectangle divided into fields that represent the fields of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties below A legend explains the notation used for the properties Reserved bits in a register figure designate a bit that is used for future device expansion Note Acronyms 3PSW CPSW CPSW and 3pGSw are interchangeable and all refer to the 3 port gigabit switch Related Documentation From Texas Instruments The following documents describe the TMS320DM647 DM648 Digital Signal Processor DSP Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the
2. Y Y Y Y Y Y Y y A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual SPRUEK5A October 2007 DSP DDR2 Memory Controller 31 Submit Documentation Feedback Using the DDR2 Memory Controller Figure 19 Connecting to Two 8 Bit DDR2 SDRAM Devices DDR CLK DDR CLK ppR2 DDR memory DDR CS controller DDR WE DDR RAS DDR CAS DDR DQMO DDR 0050 DDR 0080 DDR BA 2 0 DDR A 13 0 DDR DI 7 0 DDR DDR 0081 DDR 6951 DDR D 15 8 DDR ODTO DDR 1 DDR VREF DDR DQGATEO DDR_DQGATE1 A DDR DQGATE2 DDR DQGATE3 VREF gt e e e Y YY Y Y Y YV Wy TEXAS INSTRUMENTS www ti com DDR2 memory DDR2 memory A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual 32 DSP DDR2 Memory Controller SPRUEK5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Using the DDR2 Memory Controller 3 2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 ac
3. Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony Low Power www ti com lpw Video amp Imaging www ti com video Wireless Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated
4. 2 20 13 Logical Address to DDR2 SDRAM Address 2 2 4 1 2 40112 4 21 14 DDR2 SDRAM Column Row and Bank ACCESS 4 22 15 DDR2 Memory Controller FIFO Block 23 16 DDR2 Memory Controller Reset Block Diagram 26 17 Connecting to Two 16 Bit DDR2 SDRAM Devices 4 21 6 30 18 Connecting to a Single 16 Bit DDR2 SDRAM 4 2 2 nnne 31 19 Connecting to Two 8 Bit DDR2 SDRAM 32 20 Module ID and Revision Register 44 2 4 1 1 37 21 DDR2 Memory Controller Status Register 37 22 SDRAM Configuration Register SDCFG 1 38 23 SDRAM Refresh Control Register 6 40 24 SDRAM Timing 1 Register SDTIM1 2 42 4 2 4 714 2 244 4 444 44
5. DDR CLK frequency PLL2 input clock frequencyx20 2 PLL2 input clock frequencyx 10 The second output clock of the DDR2 memory controller DDR is the inverse of DDR CLK For more information on the PLL2 see the device specific data manual 2 2 Memory Map Please see the device specific data manual for information describing the device memory map 2 3 Signal Descriptions The DDR2 memory controller signals are shown in Figure 2 and described in Table 1 The following features are included The maximum width for the data bus DDR 0 31 0 is 32 bits e The address bus DDR A 13 0 is 14 bits wide with an additional 3 bank address pins DDR BA 2 0 Two differential output clocks DDR and DDR CLK driven by internal clock sources Command signals Row and column address strobe RAS and DDR CAS write enable strobe DDR WE data strobe DDR DQS 3 0 and DQS 3 0 and data mask DDR DQM 3 0 e chip select signal DDR CS and one clock enable signal DDR CKE Two on die termination output signals DDR ODTT 0 SPRUEK5A October 2007 DSP DDR2 Memory Controller 11 Submit Documentation Feedback Peripheral Architecture Texas INSTRUMENTS www ti com Figure 2 DDR2 Memory Controller Signals DDR CLK DDR CLK DDR CKE DDR CS DDR WE DDR RAS DDR CAS DDR DQN 3 0 DDR DQS 3 0 DDR DQS 3 0 DDR BA 2 0 DDR A 13 0 DDR D 31 0 DDR ODT 0 DDR DQGATE 3 0
6. Submit Documentation Feedback DSP DDR2 Memory Controller 41 Wy TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers Table 22 SDRAM Timing 1 Register SDTIM1 Field Descriptions continued Bit Field Value Description 1 0 These bits specify the minimum number of DDR CLK cycles from the last write to a read command minus 1 The value for these bits can be derived from the twr AC timing parameter in the DDR2 memory data sheet Calculate using this formula T t4 DDR CLK 1 42 DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback WB TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 4 6 SDRAM Timing 2 Register SDTIM2 Like the SDRAM timing 1 register SDTIM1 the SDRAM timing 2 register SDTIM2 also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory See the DDR2 memory data sheet for information on the appropriate values to program each field The bit fields in the SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register SDCFG is unlocked SDTIM2 is shown in Figure 25 and described in Table 23 Figure 25 SDRAM Timing 2 Register SDTIM2 31 25 24 23 22 16 Reserved T_ODT T_SXNR R 0x0 R W 0x3 R W 0x7F 15 8 7 5 4 0 T_SXRD T_RTP T_CKE R W OxFF R W 0x7 R W 0x1F LEGEND R W Read Write R Read only n
7. DDR VREF DDR2 memory controller Table 1 DDR2 Memory Controller Signal Descriptions Pin Description DDR D 31 0 Bidirectional data bus Input for data reads and output for data writes DDR A 13 0 External address output DDR CS Active low chip enable for memory space CEO DDR CS is used to enable the DDR2 SDRAM memory device during external memory accesses DDR CS pin stays low throughout the operation of the DDR2 memory controller it never goes high Note that this behavior does not affect the ability of the DDR2 memory controller to access DDR2 SDRAM memory devices DDR DQN 3 0 Active low output data mask DDR CLK Differential clock outputs DDR CLK DDR CKE Clock enable used for self refresh mode DDR CAS Active low column address strobe DDR RAS Active low row address strobe WE Active low write enable DDR DQS S 0 Differential data strobe bidirectional signals DDR 00513 0 DDR ODTT1 0 On die termination signals to external DDR2 SDRAM These pins are reserved for future use and should not be connected to the DDR2 SDRAM Note there are no on die termination resistors implemented on the die of this device DDR BA 2 0 Bank address control outputs DDR DQGATE 3 0 DDR VREF Data strobe gate pins These pins are used as a timing reference during memory reads The DDR DQGATEO and DDR DQGATE2 pins should be routed out and connected to the DQGATE 1 and DDR DQGATES pins respectively For m
8. www ti com Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller The external memory is always right aligned on the data bus Figure 10 Byte Alignment DDR2 memory controller data bus DDR_D 31 24 DDR_D 23 16 DDR D 15 8 DDR D 7 0 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0 32 bit memory device 16 bit memory device Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory This statement is true regardless of the number of memory devices located on the chip select space The DDR2 memory controller receives DDR2 memory access requests along with a 32 bit logical address from the rest of the system In turn DDR2 memory controller uses the logical address to generate a row page column and bank address for the DDR2 SDRAM The number of column and bank address bits used is determined by the IBANK and PAGESIZE fields see Table 5 The DDR2 memory controller uses up to 14 bits for the row page address Table 5 Bank Configuration Register Fields for Address Mapping Bit Field Bit Value Bit Description IBANK Defines the number of internal banks on the external DDR2 memory 0 1 bank 1h 2 banks 2h 4 banks 3h 8 banks PAGESIZE Defines the page size of each page of the external DDR2 memory 0 256 words requires 8 column address bits 1h 512 words requires 9 column address bits 2h 1024 words requires 10 column address bits 3h 2048 word
9. 2 14 28 Table 10 DDR2 SDRAM Extended Mode Register 1 Configuration continued Mode Mode Register Register Bit Field Init Value Description 2 ODT Value Rtt 1 On die termination effective resistance Rtt bits Together with bit 2 this bit selects the value for as 750 1 Output Driver SDCFG DDR DRIVE Output driver impedance control bits Initialized using the Impedance DDR DRIVE bit of the SDRAM configuration register SDCFG 0 DLL Enable 0 DLL enable disable bits DLL is always enabled DDR2 SDRAM Initialization After Reset After a hard or a soft reset the DDR2 memory controller will automatically start the initialization sequence The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device s Note that since a soft reset does not reset the DDR2 memory controller registers an initialization sequence started by a soft reset would use the register values from a previous configuration DDR2 SDRAM Initialization After Register Configuration The initialization sequence can also be initiated by performing a write to the two least significant bytes in the SDRAM configuration register SDCFG Using this approach data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the
10. Texas INSTRUMENTS www ti com Using the DDR2 Memory Controller Figure 17 Connecting to Two 16 Bit DDR2 SDRAM Devices DDR CLK e DDR CLK e DDRLEKE memory DDR_CS controller DDR WE DDR RAS e DDR CAS e DDR DQMO DDR DOM1 DDR DQSO DDR DQSO DDR 0081 DDR DGS1 DDR BA 2 0 DDR A 13 0 e DDR D 15 0 DDR DQM2 A DDR_DQM3 e DDR DQS2 DDR 0092 DDR 0053 DDR DQS3 DDR D 31 16 DDR ODTO DDR ODT DDR DQGATEO DDR DQGATE1 DDR DQGATE2 DDR DQGATE3 DDR2 memory x16 bit WY YV V Y Y Y Y DDR2 memory x16 bit Y V Y Y A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual 30 DSP DDR2 Memory Controller SPRUEKSA October 2007 Submit Documentation Feedback Texas INSTRUMENTS www ti com Using the DDR2 Memory Controller Figure 18 Connecting to a Single 16 Bit DDR2 SDRAM Device DDR_CLK DDR_CLK DDR_CKE DDRCS controller DDR_WE DDR_RAS DDR_CAS DDR DQMO DDR 1 DDR DQSO DDR DQSO DDR DQS1 DDR 0051 DDR 2 01 DDR A 13 0 DDR D 15 0 DDR ODTO VREF DDR ODT1 DDR VREF DDR DQGATEO DDR DQGATE 1 DDR DQGATE2 9 DDR DQGATE3 DDR2 memory x16 bit
11. 13 SDRFC Configuration Field Value Function Selection SR REFRESH RATE 0 DDR2 memory controller is not in self refresh mode 81Eh Set to 81Eh DDR2 clock cycles to meet the DDR2 memory refresh rate requirement 3 2 3 Configuring SDRAM Timing Registers SDTIM1 and SDTIM2 The SDRAM timing 1 register SDTIM1 and SDRAM timing 2 register SDTIM2 configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device Each field in SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification Table 14 and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along with the data sheet value These tables also provide a formula to calculate the register field value and displays the resulting calculation Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1 See Section 4 5 and Section 4 6 for more information Table 14 SDTIM1 Configuration DDR2 SDRAM Data Sheet Register Parameter Data Sheet Formula Register Field Field Field Name Name Description Value nS Must Be 2 Value T RFC Refresh cycle time 127 5 ppRe 1 33 T_RP Precharge command to refresh or 15 x 1 3 activate command T RCD Activate command to read write 15 trep 1 3 command T WR twn Write recovery time 15 tw
12. 66 nen nenne 41 25 SDRAM Timing 2 Register SDTIM2 43 26 Burst Priority Register aan ana aa anna 44 27 DDR2 Memory Controller Control Register DMCCTL 45 List of Figures SPRUEKS5A October 2007 Submit Documentation Feedback List of Tables 1 DDR2 Memory Controller Signal Descriptions U 12 2 DDR2 SDRAMiCOMMANAS c 13 3 Truth Table for DDR2 SDRAM u en 13 4 Addressable Memory 18 5 Bank Configuration Register Fields for Address Mapping 19 6 DDR2 Memory Controller FIFO Description U 22 7 Refresh Urgency Levels 25 8 Reset le 26 9 DDR2 SDRAM Mode Register Configuration 27 10 DDR2 SDRAM Extended Mode Register 1 Configuration 27 11 SDEFG Config
13. com Peripheral Architecture 2 7 3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller For example if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that the write completes when master B attempts to read the software message it may read stale data and therefore receive an incorrect message In order to confirm that a write from master A has landed before a read from master B is performed master A must wait for the write completion status from the DDR2 memory controller before indicating to master B that the data is ready to be read If master A does not wait for indication that a write is complete it must perform the following workaround 1 Perform the required write 2 Perform a dummy write to the DDR2 memory controller module ID and revision register 3 Perform a dummy read to the DDR2 memory controller module ID and revision register 4 Indicate to master B that the data is ready to be read after completion of the read in step 3 The completion of the read in step 3 ensures that the previous write was done For a list of the master peripherals that need this workaround see the device specific data sheet 2 8 Refresh Scheduling The DDR2 memory controller issues autorefresh REFR commands to DDR2 SDRAM devices at a rate defined in the refresh rate REFRESH RATE bit field in the SDRAM refresh control register SDRFC A r
14. controller Power control The DDR2 memory controller is compliant with the JESD79D 2A DDR2 SDRAM standard with the exception of the On Die Termination ODT feature The DSP does not include any on die terminating resistors Furthermore the on die terminating resistors of the DDR2 SDRAM device must be disabled by tying the ODT input pin of the DDR2 SDRAM memory to ground DSP DDR2 Memory Controller SPRUEK5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self refresh mode and prioritized refresh In addition it provides flexibility through programmable parameters such as the refresh rate CAS latency and many SDRAM timing parameters The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform read and write operations to DDR2 SDRAM devices Also Section 3 provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM device 2 1 Clock Control The DDR2 memory controller is clocked directly from the output of the second phase locked loop PLL2 of the device The PLL2 multiplies its input clock by 20 This clock is divided by 2 to generate DDR The frequency of CLK can be determined by using the following formula
15. cycles between transitions on the DDR pin minus 1 The value for these bits can be derived from the teke AC timing parameter in the DDR2 data sheet Calculate using this formula T 1 SPRUEK5A October 2007 DSP DDR2 Memory Controller 43 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 47 Burst Priority Register BPRIO The Burst Priority Register BPRIO helps prevent command starvation within the DDR2 memory controller To avoid command starvation the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made The PRIO RAISE bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command The BPRIO is shown in Figure 26 and described in Table 24 See Section 2 7 2 for more details on command starvation Figure 26 Burst Priority Register BPRIO Reserved R 0 15 8 7 0 Reserved PRIO RAISE R 0 R W OxFF LEGEND R W Read Write R Read only n value after reset Table 24 Burst Priority Register BPRIO Field Descriptions Bit Field Value Description 31 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 0 PRIO RAISE Number of memory transfers after which the DDR2 memory controller will e
16. memory space The host device functions as a master to the interface which increases ease of access The host and CPU can exchange information via internal or external memory The host also has direct access to memory mapped peripherals Connectivity to the CPU memory space is provided through the enhanced direct memory access controller SPRUEL8 TMS320DM647 DM648 DSP Universal Asynchronous Receiver Transmitter UART User s Guide describes the universal asynchronous receiver transmitter UART peripheral in the TMS320DM647 DM648 Digital Signal Processor DSP The UART peripheral performs serial to parallel conversion on data received from a peripheral device and parallel to serial conversion on data received from the CPU SPRUEL9 TMS320DM647 DM648 DSP VLYNQ Port User s Guide describes the VLYNQ port in the TMS320DM647 DM648 Digital Signal Processor DSP The VLYNQ port is a high speed point to point serial interface for connecting to host processors and other VLYNQ compatible devices It is a full duplex serial bus where transmit and receive operations occur separately and simultaneously without interference SPRUEM 1 TMS320DM647 DM648 DSP Video Port VCXO Interpolated Control VIC Port User s Guide discusses the video port and VCXO interpolated control VIC port in the TMS320DM647 DM648 Digital Signal Processor DSP The video port can operate as a video capture port video display port or transport channel interface T
17. no effect 2 0 PAGESIZE Page size bits Defines the internal page size of the external DDR2 memory A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence Values 0 1 6 and 7 are reserved for this field Values 4 7 are reserved for this field 0 256 word page requiring 8 column address bits 1 512 word page requiring 9 column address bits 2 1024 word page requiring 10 column address bits 3 2048 word page requiring 11 column address bits SPRUEK5A October 2007 DSP DDR2 Memory Controller 39 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 44 SDRAM Refresh Control Register SDRFC The SDRAM refresh control register SDRFC is used to configure the DDR2 memory controller to Enter and Exit the self refresh state Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands The SDRFC is shown in Figure 23 and described in Table 21 Figure 23 SDRAM Refresh Control Register SDRFC 31 30 29 16 SR Rsvd Reserved R W R W R 0x0 0x0 0x0 15 0 REFRESH RATE R W 0x753 LEGEND R W Read Write R Read only n value after reset Table 21 SDRAM Refresh Control Register SDRFC Field Descriptions Bit Field Value Description 31 SR Self refresh bit Writing a 1 to this bit will cause connected SDRAM devices to be plac
18. the ty AC timing parameter in the DDR2 memory data sheet Calculate using the formula T WR ty DDR 1 The SDRAM initialization sequence will be started when the value of this field is changed from the previous value and the DDR2 ENABLE in SDCFG is equal to 1 15 11 T RAS These bits specify the minimum number of DDR CLK cycles from an activate command to precharge command minus 1 The value for these bits can be derived from the tras AC timing parameter in the DDR2 memory data sheet Calculate using this formula T RAS t4 DDR 1 RAS must be greater than or equal to 10 6 T RC These bits specify the minimum number of DDR CLK cycles from an activate command to an activate command minus 1 The value for these bits can be derived from the AC timing parameter in the DDR2 memory data sheet Calculate using this formula T RC t DDR_CLKk 1 5 3 T RRD These bits specify the minimum number of DDR CLK cycles from an activate command to an activate command in a different bank minus 1 The value for these bits can be derived from the AC timing parameter in the DDR2 memory data sheet Calculate using this formula T RRD t y DDR 1 When connecting to an 8 bank DDR2 SDRAM this field must be equal to T_RRD 4 tyg 2 4 1 2 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect SPRUEK5SA October 2007
19. when the DDR2 memory is in self refresh mode Table 7 Refresh Urgency Levels Urgency Level Description Refresh May Backlog count is greater than O Indicates there is a backlog of REFR commands when the DDR2 memory controller is not busy it will issue the REFR command Refresh Release Backlog count is greater than 3 Indicates the level at which enough REFR commands have been performed and the DDR2 memory controller may service new memory access requests Refresh Need Backlog count is greater than 7 Indicates the DDR2 memory controller should raise the priority level of a REFR command above servicing a new memory access Refresh Must Backlog count is greater than 11 Indicates the level at which the DDR2 memory controller should perform a REFR command before servicing new memory access requests SPRUEK5A October 2007 DSP DDR2 Memory Controller 25 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 9 2 10 26 Self Refresh Mode Setting the self refresh SR bit in the SDRAM refresh control register SDRFC to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low power mode self refresh in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power When the SR bit is asserted the DDR2 memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cl
20. 0 Reserved IBANK Reserved PAGESIZE R 0x0 R W 0x2 R 0x0 R W 0x0 LEGEND R W Read Write R Read only n value after reset Table 20 SDRAM Configuration Register SDCFG Field Descriptions Bit Field Value Description 31 24 Reserved Reserved Writes to this register must keep these bits at their default values 23 BOOT UNLOCK Boot unlock bit Controls write access to bits 16 through 22 of this register 0 Writes to bits 22 16 of this register are not permitted Writes to bits 22 16 of this register are allowed 22 19 Reserved Reserved Writes to this register must keep these bits at their default value 18 DDR DRIVE DDR2 SDRAM drive strength This bit is used to select the drive strength used by the DDR2 SDRAM This bit is writeable only when BOOT UNLOCK is unlocked set to 1 0 Normal drive strength Weak 60 drive strength 17 16 Reserved Reserved Writes to this register must keep these bits at their default value 15 TIMUNLOCK Timing unlock bit Controls write access for the SDRAM Timing Register SDTIM1 and SDRAM Timing Register 2 SDTIM2 A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence 0 Register fields in the SDTIM1 and SDTIM2 registers may be changed Register fields in the SDTIM1 and SDTIM2 registers may be changed 14 NM DDR2 data bus width A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization seque
21. 0 29 16 Reserved MOD ID R 0x0 R 0x0031 15 8 7 0 MJ_REV MN_REV R 0x03 R 0x0F LEGEND R W Read Write R Read only n value after reset Table 18 Module ID and Revision Register MIDR Field Descriptions Bit Field Value Description 31 30 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 29 16 MOD ID Module ID bits 15 8 MJ REV Major revision 7 0 MN REV Minor revision 42 DDR2 Memory Controller Status Register DMCSTAT The DDR2 memory controller status register DMCSTAT is shown in Figure 21 and described in Table 19 Figure 21 DDR2 Memory Controller Status Register DMCSTAT 31 30 29 16 Rsvd Rsvd Reserved R 0x0 R Ox1 R 0x0 15 3 2 1 0 Reserved IFRDY Reserved R 0x0 R 0x0 R 0x0 LEGEND R W Read Write R Read only n value after reset Table 19 DDR2 Memory Controller Status Register DMCSTAT Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved The value always should be written as 0 write of 1 results an error in functionality 30 Reserved 1 Reserved The reserved bit location is always read as 1 A value written to this field has no effect 29 3 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 IFRDY DDR2 memory controller interface logic ready bit The interface logic control
22. AM Timing 1 Register SDTIM1 31 25 24 22 21 19 18 16 T RFC T RP T RCD T WR R W 0x3F R W 0x7 R W 0x7 R W 0x7 15 10 6 5 3 2 1 0 T RAS T RC T RRD Rsvd T WTR R W 0x1F R W Ox1F R W 0x7 R 0 R W 0x3 LEGEND R W Read Write R Read only n value after reset Table 22 SDRAM Timing 1 Register SDTIM1 Field Descriptions Bit Field Value Description 31 25 T RFC These bits specify the minimum number of DDR CLK cycles from a refresh or load mode command to a refresh or activate command minus The value for these bits can be derived from the ty AC timing parameter in the DDR2 memory data sheet Calculate using this formula T RFC tr DDR_CLK 1 24 22 T RP These bits specify the minimum number of DDR CLK cycles from a precharge command to a refresh or activate command minus 1 The value for these bits can be derived from the AC timing parameter in the DDR2 memory data sheet Calculate using the formula T RP ty DDR CLK 1 21 19 T These bits specify the minimum number of DDR CLK cycles from an activate command to a read or write command minus 1 The value for these bits can be derived from the AC timing parameter in the DDR2 memory data sheet Calculate using the formula trcg DDR_CLKk 1 18 16 T WR These bits specify the minimum number of DDR CLK cycles from the last write transfer to a precharge command minus 1 The value for these bits can be derived from
23. CI capture port The VIC port provides single bit interpolated VCXO control with resolution from 9 bits to up to 16 bits When the video port is used in TCI mode the VIC port is used to control the system clock VCXO for MPEG transport channel SPRUEK5SA October 2007 Read This First 7 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Related Documentation From Texas Instruments SPRUEM2 TMS320DM647 DM648 DSP Serial Port Interface SPI User s Guide discusses the Serial Port Interface SPI in the TMS320DM647 DM648 Digital Signal Processor DSP This reference guide provides the specifications for a 16 bit configurable synchronous serial peripheral interface The SPI is a programmable length shift register used for high speed communication between external peripherals or other DSPs SPRUEU6 TMS320DM647 DM648 DSP Subsystem User s Guide describes the subsystem in the TMS320DM647 DM648 Digital Signal Processor DSP The subsystem is responsible for performing digital signal processing for digital media applications The subsystem acts as the overall system controller responsible for handling many system functions such as system level initialization configuration user interface user command execution connectivity functions and overall system control SPRUF57 TMS320DM647 DM648 DSP 3 Port Switch 3PSW Ethernet Subsystem User s Guide describes the operation of the port switch 3PSW ethernet subsystem in the TM
24. Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices The steps required to configure the DDR2 memory controller for external memory access are also described 3 1 Connecting the DDR2 Memory Controller to DDR2 SDRAM Figure 17 Figure 18 and Figure 19 show a high level view of the three memory topologies A 32 bit wide configuration interfacing to two 16 bit wide DDR2 SDRAM devices A 16 bit wide configuration interfacing to a single 16 bit wide DDR2 SDRAM device A 16 bit wide configuration interfacing to two 8 bit wide DDR2 SDRAM devices All DDR2 SDRAM devices must be complaint to the JESD79D 2A standard Not all of the memory topologies shown may be supported by your device See the device specific data manual for more information Printed circuit board PCB layout rules and connection requirements between the DSP and the memory device exist and are described in a separate document See the device specific data manual for more information The ODT output pins of the DDR2 memory controller must not be connected to the ODT input pins of DDR2 memory devices Instead the ODT input pins of the DDR2 memory devices should be connected to ground and the ODT output pins of the DDR2 memory controller must be left unconnected The ODT output pins of the DDR2 memory controller are reserved for future use SPRUEK5A October 2007 DSP DDR2 Memory Controller 29 Submit Documentation Feedback
25. Digital Signal Processor DSP The McASP functions as a general purpose audio serial port optimized for the needs of multichannel audio applications The McASP is useful for time division multiplexed TDM stream Inter Integrated Sound I2S protocols and intercomponent digital audio interface transmission DIT SPRUEL2 TMS320DM647 DM648 DSP Enhanced DMA EDMA Controller User s Guide describes the operation of the enhanced direct memory access controller in the TMS320DM647 DM648 Digital Signal Processor DSP The EDMAS controller s primary purpose is to service user programmed data transfers between two memory mapped slave endpoints on the DSP SPRUEL4 TMS320DM647 DM648 DSP Peripheral Component Interconnect PCI User s Guide describes the peripheral component interconnect PCI port in the TMS320DM647 DM648 Digital Signal Processor DSP The PCI port supports connection of the C642x DSP to a PCI host via the integrated PCI master slave bus interface The PCI port interfaces to the DSP via the enhanced controller This architecture allows for both PCI master and slave transactions while keeping the EDMA channel resources available for other applications SPRUEL5 TMS320DM647 DM648 DSP Host Port Interface UHPI User s Guide describes the host port interface HPI in the TMS320DM647 DM648 Digital Signal Processor DSP The HPI is a parallel port through which a host processor can directly access the CPU
26. S320DM647 DM648 Digital Signal Processor DSP The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch DM648 only It provides the serial gigabit media independent interface SGMII the management data input output MDIO for physical layer device PHY management Trademarks 8 Read This First SPRUEK5A October 2007 Submit Documentation Feedback X User s Guide TEXAS SPRUEK5A October 2007 INSTRUMENTS 1 1 1 2 1 3 DSP DDR2 Memory Controller Introduction This document describes the DDR2 memory controller in the device Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D 2A standard compliant DDR2 SDRAM devices Memory types such as DDR1 SDRAM SDR SDRAM SBSRAM and asynchronous memories are not supported The DDR2 memory controller SDRAM can be used for program and data storage Features The DDR2 memory controller supports the following features JESD79D 2A standard compliant DDR2 SDRAM 256 Mbyte memory space e Data bus width of 32 or 16 bits CAS latencies 2 3 4 and 5 e Internal banks 1 2 4 and 8 Burst length 8 Burst type sequential e 1 signal e Page sizes 256 512 1024 and 2048 SDRAM auto initialization Self refresh mode Prioritized refresh e Programmable refresh rate and backlog counter e Programmable timing parameters Functional Block Diagram T
27. SDRAM devices This bit resets the interface logic The status of this interface logic is shown on the DDR2 memory controller status register 0 Release reset 1 Assert reset 4 Reserved Reserved Writes to this register must keep this field at its default value 3 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 0 RL Read latency bits These bits must be set equal to the CAS latency plus 1 SPRUEK5SA October 2007 Submit Documentation Feedback DSP DDR2 Memory Controller 45 3 TEXAS INSTRUMENTS www ti com Appendix A Appendix A Revision History Table A 1 lists the changes made since the previous version of this document Table A 1 Document Revision History Reference Additions Modifications Deletions Global Revised all signal names to match the data manual Section 2 3 Changed fourth bullet Figure 2 Changed Figure 2 Figure 3 Changed Figure 3 Figure 4 Changed Figure 4 Figure 5 Changed Figure 5 Figure 6 Changed Figure 6 Figure 7 Changed Figure 7 Section 2 4 5 Changed third sentence first paragraph Figure 8 Changed Figure 8 Figure 9 Changed Figure 9 Figure 17 Changed Figure 17 Figure 18 Changed Figure 18 Figure 19 Changed Figure 19 46 Revision History SPRUEKS5A October 2007 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections mo
28. TMS320DM647 DM648 DSP DDR2 Memory Controller User s Guide Literature Number SPRUEK5A October 2007 TEXAS INSTRUMENTS SPRUEK5A October 2007 Submit Documentation Feedback Contents rur 6 1 uuu L 9 14 Purpose of the Peripheral uu uu naga sa a 9 1 2 9 1 3 Functional Block n hme enne hm enn nhe e ne nme nnn nnn 9 1 4 Industry Standard s Compliance Statement 10 2 Peripheral Architecture EEE 11 2 1 uec device 11 2 2 Memory Da Ka CUN ram 11 2 3 Signal eee 11 2 4 Protocol Description s 13 2 5 Memory Width and Byte Alignment 18 2 6 Address Mapping csecee eee e cece eee e ee n nnn nnn nnn enne nme enne hne hh hne nn nne nnne 19 2 7 DDR2 Memory Controller Interface eene enne nn nnn nnne 22 2 8 Refresh uuu IDE IE MEIN 25 2 9 E creatinine Eee EEE scien aa 26 2107 Reset COnSIderalioriS aq ae asusta u 26 2 11 DDR2 SDRAM Memory Initializati
29. b 11 1 3 x nrb 14 nbb 1 ncb 11 2 3 x nrb 12 nbb 2 ncb 11 3 3 x nrb 11 nbb 3 ncb 11 4 Legend number of row address bits ncb number of column address bits nbb number of bank address bits BE byte enable bits Figure 12 Logical Address to DDR2 SDRAM Address Map for 16 bit SDRAM 20 SDCFG Bit Logical Address IBANK PAGESIZE 31 28 27 26 25 24 23 22 21 16 15 14 13 12 11 10 9 8 1 0 0 x x x x x x 14 ncb 8 1 0 x x x x nrb 14 nbb 1 ncb 8 2 0 x x x nrb 14 nbb 2 ncb 8 3 0 x x x nrb 14 nbb 3 ncb 8 0 1 x x x x nrb 14 ncb 9 1 1 x x x nrb 14 nbb 1 ncb 9 2 1 x x x nrb 14 nbb 2 ncb 9 3 1 x x nrb 14 nbb 3 ncb 9 0 2 x x x nrb 14 ncb 10 1 2 x x nrb 14 nbb 1 ncb 10 2 2 x x nrb 14 nbb 2 ncb 10 3 2 x nrb 14 nbb 3 ncb 10 0 3 x x nrb 14 ncb 11 1 3 x nrb 14 nbb 1 ncb 11 2 3 x nrb 13 nbb 2 ncb 11 3 3 x nrb 12 nbb 3 ncb 11 1 Legend nrb number of row address bits ncb number of column address bits nbb number of bank address bits BE byte enable bit DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Peripheral Architecture Figure 11 shows how the DSP memory map is partitioned into col
30. ble disable single ended strobe etc The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands When the MRS or EMRS command is executed the value on DDR BA 1 0 selects the mode register to be written and the data on DDR A 12 0 is loaded into the register Figure 3 shows the timing for an MRS and EMRS command The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller initialization sequence See Section 2 11 for more information Figure 3 DDR2 MRS and EMRS Command L MRS EMRS DDR CLK DDR CLK DDR CKE DDR CS DDR RAS DDR CAS DDR WE DDR COL DDR BAR O BANK EEE Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device Figure 4 REFR is automatically preceded by a DCAB command ensuring the deactivation of all CE spaces and banks selected Following the DCAB command the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate REFRESH RATE bit in the SDRAM refresh control register SDRFC Page information is always invalid before and after a REFR command thus a refresh cycle always forces a page miss This type of refresh cycle is often called autorefresh Autorefresh commands may not be disabled within the DDR2 memory controller See Section 2 8 for more details on REFR command scheduling DSP DDR2 Memory Controller SPRUEKS5A O
31. cesses This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices By programming the SDRAM Configuration Register SDCFG SDRAM Refresh Control Register SDRFC SDRAM Timing 1 Register SDTIM1 and SDRAM Timing 2 Register SDTIM2 the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D 2A compliant DDR2 SDRAM devices As an example the following sections describe how to configure each of these registers for access to two 1Gb 16 bit wide DDR2 SDRAM devices connected as shown on Figure 17 where each device has the following configuration Maximum data rate 533MHz Number of banks 8 e Page size 1024 words CAS latency 4 is assumed that the frequency of the DDR2 memory controller clock DDR is set to 266 5MHz 3 2 1 Programming the SDRAM Configuration Register SDCFG The SDRAM configuration register SDCFG contains register fields that configure the DDR2 memory controller to match the data bus width CAS latency number of banks and page size of the attached DDR2 memory Table 11 shows the resulting SDCFG configuration Note that the value of the TIMUNLOCK field is dependent on whether or not it is desirable to unlock SDTIM1 and SDTIM2 The TIMUNLOCK bit should only be set to 1 when the SDTIM1 and SDTIM2 needs to be updated Table 11 SDCFG Configuration Field Value Function Selection TIMUNLOCK x Set to 1 to unlock
32. ch master the DDR2 memory controller reorders the commands based on the following rules e Selects the oldest command Aread command is advanced before an older write command if the read is to a different block address 2048 bytes and the read priority is equal to or greater than the write priority Note Most masters issue commands on a single priority level Also the EDMA transfer controller read and write ports are considered different masters and thus the above rule does not apply The second bullet above may be viewed as an exception to the first bullet This means that for an individual master all of its commands will complete from oldest to newest with the exception that a read may be advanced ahead of an older lower or equal priority write Following this scheduling each master may have one command ready for execution SPRUEK5A October 2007 DSP DDR2 Memory Controller 23 Submit Documentation Feedback D TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 7 2 24 Next the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering Among all pending reads selects reads to rows already open Among all pending writes selects writes to rows already open e Selects the highest priority command from pending reads and writes to open rows If multiple commands have the highest priority then the DDR2 memory controller selects the oldest
33. command The DDR2 memory controller may now have a final read and write command If the Read FIFO is not full then the read command will be performed before the write command otherwise the write command will be performed first Besides commands received from on chip resources the DDR2 memory controller also issues refresh commands The DDR2 memory controller attempts to delay refresh commands as long as possible to maximize performance while meeting the SDRAM refresh requirements As the DDR2 memory controller issues read write and refresh commands to DDR2 SDRAM device it follows the following priority scheme 1 Highest Refresh request resulting from the Refresh Must level of urgency see Section 2 8 being reached Read request without a higher priority write selected from above reordering algorithm Refresh request resulting from the Refresh Need level of urgency see Section 2 8 being reached Write request selected from above reordering algorithm Refresh request resulting from Refresh May level of urgency see Section 2 8 being reached Lowest Request to enter self refresh mode m The following results from the above scheduling algorithm Allwrites from a single master will complete in order e All reads from a single master will complete in order e From the same master any read to the same location or within 2048 bytes as a previous write will complete in order Command Starvation The reordering and sc
34. ctober 2007 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Peripheral Architecture Figure 4 Refresh Command L REFR DDR_CLK DDR CLK DDR_CKE DDR CS DDR RAS 7 DDR_CAS DDR WE 1 0 j BA 2 4 3 Activation ACTV The DDR2 memory controller automatically issues the activate ACTV command before a read or write to a closed row of memory The ACTV command opens a row of memory allowing future accesses reads or writes with minimum latency The value of DDR BA 2 0 selects the bank and the value of A 12 0 selects the row When the DDR2 memory controller issues ACTV command a delay of is incurred before a read or write command is issued Figure 5 shows an example of an ACTV command Reads or writes to the currently active row and bank of memory can achieve much higher throughput than reads or writes to random areas because every time a new row is accessed the ACTV command must be issued and a delay of tacp incurred Figure 5 ACTV Command L ACTV DDR CLK DDR CLK DDR CKE DDR CS DDR RAS DDR CAS DDR WE DDR 2 ROW DDR BA2 0 BANK DDR DOM 3 0 SPRUEK5A October 2007 DSP DDR2 Memory Controller 15 Submit Documentation Feedback 9 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 4 4 Deactivation DCAB and DEAC The precharge all banks command DCAB is performed after a reset to the DDR2 memo
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36. e into Self Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state 0 Exit self refresh mode Enter self refresh mode 30 Reserved Reserved Writes to this register must keep this field at its default value 29 16 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 REFRESH RATE Refresh rate bits The value in this field is used to define the rate at which connected SDRAM devices will be refreshed as follows effect SDRAM refresh rate DDR CLK clock rate REFRESH RATE Writing a value less than 0x0100 to this field will cause it to be loaded with 2 T RFC value from the SDRAM Timing 1 Register 40 DSP DDR2 Memory Controller SPRUEKSA October 2007 Submit Documentation Feedback Wi TEXAS INSTRUMENTS www ti com 4 5 DDR2 Memory Controller Registers SDRAM Timing 1 Register SDTIM1 The SDRAM timing 1 register SDTIM1 configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory Note that DDR CLK is equal to the period of the DDR_CLK signal See the DDR2 memory data sheet for information on the appropriate values to program each field The bit fields in the SDTIM1 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register SDCFG is unlocked The SDTIM1 is shown in Figure 24 and described in Table 22 Figure 24 SDR
37. e nn 43 4 7 Burst Priority Register nnne nnne nnne 44 4 8 DDR2 Memory Controller Control Register DMCCTL 45 Appendix A Revision History uuu uuu nna EAEE E EEEE 46 SPRUEK5A October 2007 Table of Contents 3 Submit Documentation Feedback 4 List of Figures 1 DDR2 Memory Controller Block Diagram 10 2 DDR2 Memory Controller Signals 1 12 3 DDR2 MBS and EMRS nein ai ERE E DEDERE 14 4 Refresh Command u LR 15 5 ACM COMMANG E OE 15 6 L 16 7 DEAC COMMANG 16 8 DDR2 READ e 17 9 DBR2 WRT GOmmalidisss sicco ne E n ER awa a Q ERN EE 18 10 Byte AligritTignE casas ava a rat a aa aa NM ENIM M MN EE M MAE 19 11 Logical Address to DDR2 SDRAM Address for 32 Bit SDRAM 19 12 Logical Address to DDR2 SDRAM Address Map for 16 bit
38. eared At this point all open pages of DDR2 SDRAM are closed and a self refresh SLFRFR command an autorefresh command with DDR CKE low is issued The DDR2 memory controller exits the self refresh state when a memory access is received or when the SR bit in SDRFC is cleared While in the self refresh state if a request for a memory access is received the DDR2 memory controller services the memory access request returning to the self refresh state upon completion The DDR2 memory controller will not exit the self refresh state whether from a memory access request or from clearing the SR bit until T CKE 1 cycles have expired since the self refresh command was issued The value of T CKE is defined in the SDRAM timing 2 register SDTIM2 After exiting from the self refresh state the DDR2 memory controller will not immediately start using commands Instead it will wait T SXNR 1 clock cycles before issuing non read commands and T SXRD 1 clock cycles before issuing read commands The SDRAM timing 2 register SDTIM2 programs the values of T SXNR and T SXRD Reset Considerations The DDR2 memory controller has two reset signals VRST RST VRST is a module level reset that resets both the state machine and the DDR2 memory controller memory mapped registers RST resets the state machine only If the DDR2 memory controller is reset independently of other peripherals your software should not perform memory or registe
39. ed for Fast exit 11 9 Write Recovery SDTIM1 T WR Write recovery bits for auto precharge Initialized using the WR bits of the SDRAM timing 1 register SDTIM1 DLL Reset 0 DLL reset bits DLL is not in reset 7 Mode 0 Operating mode bit Normal operating mode is always selected 6 4 CAS Latency SDCFG CL CAS latency bits Initialized using the CL bits of the SDRAM configuration register SDCFG Burst Type 0 Burst type bits Sequential burst mode is always used 2 0 Burst Length 3h Bust length bits A burst length of 8 is always used Table 10 DDR2 SDRAM Extended Mode Register 1 Configuration Mode Mode Register Register Bit Field Init Value Description 12 Output Buffer Enable 0 Output buffer enable bits Output buffer is always enabled 11 RDQS Enable 0 RDQS enable bits Always initialized to 0 RDQS signals disabled 10 DQS enable 0 DQS enable bit Always initialized to 0 DQS signals enabled 9 7 OCD Operation Oh Off chip driver impedance calibration bits This bit is always initialized to Oh 6 ODT Value Rtt 0 On die termination effective resistance Rtt bit Together with bit 2 this bit selects the value for Rtt as 75Q 5 3 Additive Latency Oh Additive latency bits Always initialized to Oh no additive latency SPRUEK5A October 2007 DSP DDR2 Memory Controller 27 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 11 2 2 11 3 2 12 2 13
40. efresh interval counter is loaded with the value of the REFRESH RATE bit field and decrements by 1 each cycle until it reaches zero Once the interval counter reaches zero it reloads with the value of the REFRESH RATE bit Each time the interval counter expires a refresh backlog counter increments by 1 Conversely each time the DDR2 memory controller performs a REFR command the backlog counter decrements by 1 This means the refresh backlog counter records the number of REFR commands the DDR2 memory controller currently has outstanding The DDR2 memory controller issues REFR commands based on the level of urgency The level of urgency is defined in Table 7 Whenever the refresh level of urgency is reached the DDR2 memory controller issues a REFR command before servicing any new memory access requests Following a REFR command the DDR2 memory controller waits T RFC cycles defined in the SDRAM timing 1 register SDTIM1 before rechecking the refresh urgency level In addition to the refresh counter previously mentioned a separate backlog counter ensures the interval between two REFR commands does not exceed 8x the refresh rate This backlog counter increments by 1 each time the interval counter expires and resets to zero when the DDR2 memory controller issues a REFR command When this backlog counter is greater than 7 the DDR2 memory controller issues four REFR commands before servicing any new memory requests The refresh counters do not operate
41. er of banks as determined by IBANK minus 1 and N is number of rows as determined by both PAGESIZE and IBANK minus 1 SPRUEK5A October 2007 DSP DDR2 Memory Controller 21 Submit Documentation Feedback Peripheral Architecture 3 TEXAS Figure 14 DDR2 SDRAM Column Row and Bank Access CCC C o BankO 0 1 2 3 3 Row Row 2 Row N C o ccc C 1 0 1 2 3 M 000 POWA EOE SE SE SEE TENE Row 1 Bank2 0 1 2 M Row0 Row 1 2 Row INSTRUMENTS www ti com ccc T 4 Ban kP 0 1 2 3 M RowO Row 1 Row 2 Row N A Mis number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and N is number of rows as determined by both PAGESIZE and IBANK minus 1 2 7 DDR2 Memory Controller Interface To move data efficiently from on chip resources to external DDR2 SDRAM device the DDR2 memory controller makes use of a command FIFO a write FIFO a read FIFO and command and data schedulers Table 6 describes the purpose of each FIFO Figure 15 shows the block diagram of the DDR2 memory controller FIFOs Commands write data and read data arrive at the DDR2 memo
42. he DDR2 memory controller is the main interface to external DDR2 memory see Figure 1 Master peripherals such as the EDMA controller and the CPU can access the DDR2 memory controller through the switched central resource SCR The DDR2 memory controller performs all memory related background tasks such as opening and closing banks refreshes and command arbitration SPRUEK5A October 2007 DSP DDR2 Memory Controller 9 Submit Documentation Feedback Introduction 1 4 10 Figure 1 DDR2 Memory Controller Block Diagram DDR2 memory controller Switched central resource Other peripherals EDMA controller Boot Industry Standard s Compliance Statement o umm L2 memory controller Cache control Bandwidth management Memory protection External memory controller L1P cache SRAM L1 program memory controller Cache control Bandwidth management Memory protection Configuration registers Master DMA Slave DMA Wy TEXAS INSTRUMENTS www ti com Advanced event triggering AET C64x CPU Instruction fetch SPLOOP buffer 16 32 bit instruction dispatch Instruction decode Data path A Register file A Register file B Data path B L1 data memory controller Cache control Memory protection Bandwidth management cache SRAM Interrupt and exception
43. heduling rules listed above may lead to command starvation which is the prevention of certain commands from being processed by the DDR2 memory controller Command starvation results from the following conditions Acontinuous stream of high priority read commands can block a low priority write command e Acontinuous stream of DDR2 SDRAM commands to a row in an open bank can block commands to the closed row in the same bank To avoid these conditions the DDR2 memory controller can momentarily raise the priority of the oldest command in the command FIFO after a set number of transfers have been made The PRIO RAISE field in the Burst Priority Register BPRIO sets the number of the transfers that must be made before the DDR2 memory controller will raise the priority of the oldest command Note Leaving the PRIO RAISE bits at their default value FFh disables this feature of the DDR2 memory controller This means commands can stay in the command FIFO indefinitely Therefore these bits should be set to FEh immediately following reset to enable this feature with the highest level of allowable memory transfers It is suggested that system level prioritization be set to avoid placing high bandwidth masters on the highest priority levels These bits can be left as unless advanced bandwidth prioritization control is required DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti
44. initialization sequence Perform the following steps to start the initialization sequence 1 Set the BOOT_UNLOCK bit in the SDRAM configuration register SDCFG 2 Write a 0 to the BOOT_UNLOCK bit along with the desired value for the DDR_DRIVE bit 3 Program the rest of the SDCFG to the desired value with the TIMUNLOCK bit set unlocked 4 Program the SDRAM timing 1 register SDTIM1 and SDRAM timing register 2 SDTIM2 with the value needed to meet the DDR2 SDRAM device timings Program the REFRESH_RATE bits in the SDRAM refresh control register SDRFC to a value that meets the refresh requirements of the DDR2 SDRAM device 6 Program SDCFG with the desired value and the TIMUNLOCK bit cleared locked 7 Program the read latency RL bit in the DDR2 memory controller control register DMCCTL to the desired value e Interrupt Support The DDR2 memory controller does not generate any interrupts EDMA Event Support The DDR2 memory controller is a DMA slave peripheral and therefore does not generate EDMA events Data read and write requests may be made directly by masters including the EDMA controller Emulation Considerations The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Using the DDR2 Memory Controller 3 Using the DDR2 Memory
45. levate the priority of the oldest command in the command FIFO Setting this field to FFh disables this feature thereby allowing old commands to stay in the FIFO indefinitely 0 1 memory transfer 1 2 memory transfers 2 3 memory transfers 3 FEh 4 FFh memory transfers FFh Feature disabled commands can stay in command FIFO indefinitely 44 DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS WWW ti com DDR2 Memory Controller Registers 48 DDR2 Memory Controller Control Register DMCCTL The DDR2 memory controller control register DMCCTL resets the interface logic of the DDR2 memory controller The DMCCTL is shown in Figure 27 and described in Table 25 Figure 27 DDR2 Memory Controller Control Register DMCCTL 31 16 Reserved R 0x5000 15 6 5 4 3 2 0 IF Reserved icu Rsvd Rsvd RL R W 0x0190 R W R W R 0x0 R W 0x7 0x1 0x0 LEGEND R W Read Write R Read only n value after reset Table 25 DDR2 Memory Controller Control Register DMCCTL Field Descriptions Bit Field Value Description 31 6 Reserved Reserved Writes to this register must keep this field at its default value 15 6 Reserved Reserved Writes to this register must keep this field at its default value 5 IFRESET DDR2 memory controller interface logic reset The interface logic controls the signals used to communicate with DDR2
46. mpliant with the JESDEC79 2A specification The DDR2 memory controller performs the initialization sequence under the following conditions e Automatically following a hard or soft reset see Section 2 11 2 e Following a write to the two least significant bytes in the SDRAM configuration register SDCFG see Section 2 11 3 At the end of the initialization sequence the DDR2 memory controller performs an auto refresh cycle leaving the DDR2 memory controller in an idle state with all banks deactivated When the initialization section is started automatically after a hard or soft reset commands and data stored in the DDR2 memory controller FIFOs are lost However when the initialization sequence is initiated by a write to the two least significant bytes in SDCFG data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence 2 11 1 DDR2 SDRAM Device Mode Register Configuration Values The DDR2 memory controller initializes the mode register and extended mode register 1 of the memory device with the values shown on Table 9 and Table 10 The DDR2 SDRAM extended mode registers 2 and 3 are configured with a value of Oh Table 9 DDR2 SDRAM Mode Register Configuration Mode Mode Register Register Bit Field Init Value Description 12 Power down Mode 0 Active power down exit time bit Configur
47. n X fppR2 1 3 T RAS tRAS Active to precharge command 40 trac X fppne 1 10 T RC Activate to Activate command in the 55 tac fppR2 1 14 same bank T RRD Activate to Activate command 10 tarp X fppge 1 3 different bank T WTR twrR Write to read command delay 7 5 twtr X 1 1 34 DSP DDR2 Memory Controller SPRUEK5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Using the DDR2 Memory Controller Table 15 SDTIM2 Configuration DDR2 SDRAM Data Register Field Sheet Parameter Data Sheet Formula Register Field Name Name Description Value Field Must Be gt Value T ODT tAOND Specifies the ODT 2 cycles CAS latency taonp 1 1 turn on delay T SXNR 5 Exit self refresh to non read 137 5 nS tsxNR X 1 36 command T SXRD lsxRD Exit self refresh to a read 200 cycles texnp 1 199 command T RTP Read to precharge command 7 5 nS tate X fppRe 1 1 delay T CKE tcKE CKE minimum pulse width 3 cycles teke 1 2 3 2 4 Configuring the DDR2 Memory Controller Control Register DMCCTL The DDR2 memory controller control register DMCCTL contains a read latency RL field that helps the DDR2 memory controller determine when to sample read data The RL field should be programmed to a value equal to CAS latency plus 1 For example if a CAS latency of 4 is u
48. nce 0 32 bit bus width 16 bit bus width 13 12 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 38 DSP DDR2 Memory Controller SPRUEKSA October 2007 Submit Documentation Feedback WB TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers Table 20 SDRAM Configuration Register SDCFG Field Descriptions continued Bit Field Value Description 11 9 CL CAS latency The value of this field defines the CAS latency to be used when accessing connected SDRAM devices A write to this field will cause the DDR2 Memory Controller to start the SDRAM initialization sequence This field is writeable only when the TIMUNLOCK bit is unlocked Values 0 1 6 and 7 are reserved for this field 2 CAS latency of 2 3 CAS latency of 3 4 CAS latency of 4 5 CAS latency of 5 8 7 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 6 4 IBANK Internal SDRAM bank setup bits Defines number of banks inside connected SDRAM devices A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence Values 4 7 are reserved for this field 0 One bank SDRAM devices 1 Two banks SDRAM devices 2 Four banks SDRAM devices 3 Eight banks SDRAM devices 3 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has
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50. on 27 2 12 Interrupt SUPPO aa a E PAPE M aw 28 2 13 Event SUDDOLTL na een rae rex dex a dre Duae 28 2 14 JEmulation GonslideralloriS s ukum eios aaa Siam 28 3 Using the DDR2 Memory Controller 29 3 1 Connecting the DDR2 Memory Controller to DDR2 SDRAM 29 3 2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications 33 4 DDR2 Memory Controller Registers 36 4 1 Module ID and Revision Register MIDR er 4 2 DDR2 Memory Controller Status Register DMCSTAT 37 4 3 SDRAM Configuration Register 5 2 1 38 4 4 SDRAM Refresh Control Register 40 4 5 SDRAM Timing 1 Register SDTIM1 41 4 6 SDRAM Timing 2 Register 2 nna nm
51. ore routing requirements on these pins see the device specific data manual DDR2 Memory Controller reference voltage This voltage must be supplied externally See the device specific data manual for more details 12 DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 4 Protocol Description s The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 Table 3 shows the signal truth table for the DDR2 SDRAM commands Table 2 DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row DCAB Precharge all command Deactivates precharges all banks DEAC Precharge single command Deactivates precharges a single bank DESEL Device Deselect EMRS Extended Mode Register set Allows altering the contents of the mode register MRS Mode register set Allows altering the contents of the mode register NOP No operation Power Down Power down mode READ Inputs the starting column address and begins the read operation READ with Inputs the starting column address and begins the read operation The read operation is followed by a autoprecharge precharge REFR Autorefresh cycle SLFREFR Self refresh mode WRT Inputs the starting column address and begins the write operation WRT with Inp
52. r accesses while VRST or are asserted If memory or register accesses are performed while the DDR2 memory controller is in the reset state other masters may hang Following the rising edge of VRST or RST the DDR2 memory controller FIFOs are lost Table 8 describes the different methods for asserting each reset signal The Power and Sleep Controller PSC acts as a master controller for power management for all of the peripherals on the device Table 8 Reset Sources Reset Signal Reset Source VRST Hardware device reset VCTL RST Power and sleep controller Figure 16 DDR2 Memory Controller Reset Block Diagram DDR2 memory controller registers Hard VRST reset from PLLCTL1 State VCTL RST machine DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 11 DDR2 SDRAM Memory Initialization DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device These registers control parameters such as burst type burst length and CAS latency The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence described in Section 2 11 2 and Section 2 11 3 The initialization sequence performed by the DDR2 memory controller is co
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54. ry controller or following the initialization sequence DDR2 SDRAMs also require this cycle prior to a refresh REFR and mode set register commands MRS and EMRS During a DCAB command DDR A 10 is driven high to ensure the deactivation of all banks Figure 6 shows the timing diagram for a DCAB command Figure 6 DCAB Command L DCAB i c A 35 5 Cee DDR CLK rr r rr n 995 DDR_CKE DDR_CS DDR RAS N DDR CAS ww CNN DDR 13 11 9 0 j Alto 7 1 N 1 DDR Bapo 1 2 1 DEAC command closes a single bank of memory specified by the bank select signals Figure 7 shows the timings diagram for a DEAC command Figure 7 DEAC Command L DEAC X X oo DDR_CLK DDR CKE DDR CS DDR RAS N DDR CAS DDR WE N DDR 00 400 DOR Bg r h zc 16 DSP DDR2 Memory Controller SPRUEKSA October 2007 Submit Documentation Feedback Ww TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 4 5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM The READ command initiates a burst read operation to an active row During the READ command DDR_CAS drives low DDR WE and DDR RAS remain high the column address is driven on DDR A 12 0 and the bank address is driven on BA 2 0 The DDR2 memory controller uses a b
55. ry controller parallel to each other The same peripheral bus is used to write and read data from external memory as well as internal memory mapped registers Table 6 DDR2 Memory Controller FIFO Description FIFO Description Depth 64 Bit Doublewords Command Write Read Stores all commands coming from on chip requesters Stores write data coming from on chip requesters to memory Stores read data coming from memory to on chi requesters 7 11 17 22 DSP DDR2 Memory Controller SPRUEKS5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 2 7 1 Peripheral Architecture Figure 15 DDR2 Memory Controller FIFO Block Diagram Command FIFO Command Data Command Scheduler to Memory Write FIFO 5 m Write Data lt to Memory a Read FIFO Read Data from Memory Registers Command Data Command Ordering and Scheduling Advanced Concept The DDR2 memory controller performs command re ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput The goal is to maximize the utilization of the data address and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows Command re ordering takes place within the command FIFO The DDR2 memory controller examines all the commands stored in the command FIFO to schedule commands to the external memory For ea
56. s requires 11 column address bits Figure 11 and Figure 12 show how the logical address bits map to the row column and bank bits all combinations of IBANK and PAGESIZE values Note that the upper four bits of the logical address cannot be used for memory addressing as the DDR2 memory controller has a maximum addressable memory range of 256 Mbytes The DDR2 memory controller address pins provide the row and column address to the DDR2 SDRAM thus the DDR2 memory controller appropriately shifts the logical address during row and column address selection The bank address is driven to the DDR2 SDRAM using the bank address pins The two lower bits of the logical address decode the value of the byte enable pins only used for accesses less than the width of the DDR2 memory controller data bus Figure 11 Logical Address to DDR2 SDRAM Address Map for 32 Bit SDRAM SPRUEK5A October 2007 DSP DDR2 Memory Controller 19 Submit Documentation Feedback TEXAS INSTRUMENTS www ti com Peripheral Architecture SDCFG Bit Logical Address IBANK PAGESIZE 31 28 27 26 25 24 23 22 17 16 15 14 13 12 11 10 9 2 0 0 x x x x x 14 ncb 8 1 0 x x X X nrb 14 nbb 1 ncb 8 2 0 x x x nrb 14 nbb 2 ncb 8 3 0 x x nrb 14 nbb 3 ncb 8 0 1 x x X X nrb 14 ncb 9 1 1 x x x nrb 14 nbb 1 ncb 9 2 1 x x nrb 14 nbb 2 ncb 9 3 1 x nrb 14 nbb 3 ncb 9 0 2 x x nrb 14 ncb 10 1 2 X nrb 14 nbb 1 ncb 10 2 2 x nrb 14 nbb 2 ncb 10 3 2 x nrb 13 nbb 3 ncb 10 0 3 x x nrb 14 nc
57. s the signals used to communicate with DDR2 SDRAM devices This bit displays the status of the interface logic 0 Interface logic is not ready either powered down not ready or not locked Interface logic is powered up locked and ready for operation 1 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect SPRUEK5A October 2007 DSP DDR2 Memory Controller 37 Submit Documentation Feedback 35 TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 43 SDRAM Configuration Register SDCFG The SDRAM configuration register SDCFG contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory These fields configure the DDR2 memory controller to match the data bus width CAS latency number of internal banks and page size of the external DDR2 memory Bits 0 14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 unlocked See Section 2 11 1 for more information on initializing the configuration registers of the DDR2 memory controller The SDCFG is shown in Figure 22 and described in Table 20 Figure 22 SDRAM Configuration Register SDCFG 31 24 Reserved R 0x0 23 22 19 18 17 16 BOOT_ UNLOCK Reserved DDR_DRIVE Reserved R W 0 R W 0xA R 0 R 0x3 15 14 13 12 11 9 8 TIMUNLOCK NM Reserved CL Reserved R W 0 R W 0 R 0x0 R W 0x5 R 0x0 7 6 4 3 2
58. search box provided at www ti com SPRS372 TMS320DM647 DM648 Digital Media Processor Data Manual describes the signals specifications and electrical characteristics of the device SPRU732 TMS320C64x C64x DSP CPU and Instruction Set Reference Guide describes the CPU architecture pipeline instruction set and interrupts for the TMS320C64x and TMS320C64x digital signal processors DSPs of the TMS320C6000 DSP family The C64x C64x4 DSP generation comprises fixed point devices in the C6000 DSP platform The C64x DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set SPRUEK5 TMS320DM647 DM648 DSP DDR2 Memory Controller User s Guide describes the DDR2 memory controller in the TMS320DM647 DM648 Digital Signal Processor DSP The DDR2 mDDR memory controller is used to interface with JESD79D 2A standard compliant DDR2 SDRAM devices and standard Mobile DDR SDRAM devices SPRUEK6 TMS320DM647 DM648 DSP External Memory Interface EMIF User s Guide describes the operation of the asynchronous external memory interface EMIF in the TMS320DM647 DM648 Digital Signal Processor DSP The EMIF supports a glueless interface to a variety of external devices SPRUEK7 TMS320DM647 DM648 DSP General Purpose Input Output GPIO User s Guide describes the general purpose input output GPIO peripheral in the TMS320DM647 DM648 Digital Signal Processor DSP The GPIO peripheral provides dedicated general p
59. sed then RL should be programmed to 5 Table 16 DMCCTL Configuration Register Register Field Name Description Value IFRESET Programmed to be out of reset 0 RL Read latency is equal to CAS latency plus 1 5 SPRUEK5A October 2007 DSP DDR2 Memory Controller 35 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 4 DDR2 Memory Controller Registers Table 17 lists the memory mapped registers for the DDR2 memory controller See the device specific data manual for the memory address of these registers Table 17 DDR2 Memory Controller Registers Offset Acronym Register Description Section 00h MIDR Module ID and Revision Register Section 4 1 04h DMCSTAT DDR2 Memory Controller Status Register Section 4 2 08h SDCFG SDRAM Configuration Register Section 4 3 OCh SDRFC SDRAM Refresh Control Register Section 4 4 10h SDTIM1 SDRAM Timing 1 Register Section 4 5 14h SDTIM2 SDRAM Timing 2 Register Section 4 6 20h BPRIO Burst Priority Register Section 4 7 E4h DMCCTL DDR2 Memory Controller Control Register Section 4 8 36 DSP DDR2 Memory Controller SPRUEKSA October 2007 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 4 1 Module ID and Revision Register The Module ID and Revision register MIDR is shown in Figure 20 and described in Table 18 Figure 20 Module ID and Revision Register MIDR 31 3
60. te latency is equal to CAS latency minus 1 All writes have a burst length of 8 The use of the DDR_DQM outputs allows byte and halfword writes to be executed Figure 9 shows the timing for a write on the DDR2 memory controller If the transfer request is for less than 8 words depending on the scheduling result and the pending commands the DDR2 memory controller can e Mask out the additional data using DDR_DQM outputs e Terminate the write burst and start a new write burst The DDR2 memory controller does not perform the DEAC command until page information becomes invalid Figure 9 DDR2 WRT Command DDR CLK DDR CLK Sample Latency 5 DDR CKE DDR CS DDR RAS DDR CAS DDR WE oor anso EXE DoR eno DDR A 10 DDR Doc DDR D 31 0 po X D X o2 X D4 X D5 X pe X 7 DDR DOS 3 0 N N N Memory Width and Byte Alignment The DDR2 memory controller supports memory widths of 16 bits and 32 bits Table 4 summarizes the addressable memory ranges on the DDR2 memory controller Table 4 Addressable Memory Ranges Memory Width Maximum Addressable Bytes Address Type Generated by DDR2 Memory Controller x16 128 Mbytes Halfword address x32 256 Mbytes Word address DSP DDR2 Memory Controller SPRUEK5A October 2007 Submit Documentation Feedback Wi TEXAS INSTRUMENTS 2 6
61. the SDRAM timing and timing 2 registers Cleared to 0 to lock the SDRAM timing and timing 2 registers NM Oh To configure the DDR2 memory controller for a 32 bit data bus width CL 4h To select a CAS latency of 4 IBANK 3h To select 8 internal DDR2 banks PAGESIZE 2h To select 1024 word page size 3 2 2 Programming the SDRAM Refresh Control Register SDRFC The SDRAM refresh control register SDRFC configures the DDR2 memory controller to meet the refresh requirements of the attached DDR2 device SDRFC also allows the DDR2 memory controller to enter and exit self refresh In this example we assume that the DDR2 memory controller is not is in self refresh mode The REFRESH RATE field in SDRFC is defined as the rate at which the attached DDR2 device is refreshed in DDR2 cycles The value of this field may be calculated using the following equation REFRESH_RATE DDR_CLK frequency x memory refresh period SPRUEK5A October 2007 DSP DDR2 Memory Controller 33 Submit Documentation Feedback Using the DDR2 Memory Controller Table 12 displays the DDR2 533 refresh rate specification 5 INSTRUMENTS www ti com Table 12 DDR2 Memory Refresh Specification Symbol Description Value tREF Average Periodic Refresh Interval 7 8 us Therefore the value for the REFRESH RATE can be calculated as follows REFRESH RATE 266 5 MHz x 7 8 us 2078 7 81Eh Table 13 shows the resulting SDRFC configuration Table
62. umns rows and banks Note that during a linear access the DDR2 memory controller increments the column address as the logical address increments When the DDR2 memory controller reaches a page row boundary it moves onto the same page row in the next bank This movement continues until the same page has been accessed in all banks To the DDR2 SDRAM this process looks as shown on Figure 14 By traversing across banks while remaining on the same row page the DDR2 memory controller maximizes the number of activated banks for a linear access This results in the maximum number of open pages when performing a linear access being equal to the number of banks Note that the DDR2 memory controller never opens more than one page per bank Ending the current access is not a condition that forces the active DDR2 SDRAM row page to be closed The DDR2 memory controller leaves the active row open until it becomes necessary to close it This decreases the deactivate reactivate overhead Figure 13 Logical Address to DDR2 SDRAM Address Map Col 0 Col 1 Col 2 Col 3 Col 4 eee Col 1 Col M Row 0 bank 0 Row 0 bank 1 Row 0 bank 2 Row 0 bank P Row 1 bank 0 Row 1 bank 1 Row 1 bank 2 Row 1 bank P Row N bank 0 Row N bank 1 Row N bank 2 Row N bank P A Mis number of columns as determined by PAGESIZE minus 1 P is numb
63. uration 33 12 DDR2 Memory Refresh Specification uses eoe te eee ehe UU 34 13 SDRFE Configuration 34 14 COmlGuratlO Mis m 34 15 SDTIM2 Configuration 35 16 ete eiusm eoe ERI RR e REDDE i He na En yaaa DLE DU ES CERE 35 17 DDR2 Memory Controller Regislers oae denne Du a a Beck wav um 36 18 Module ID and Revision Register MIDR Field Descriptions 37 19 DDR2 Memory Controller Status Register DMCSTAT Field Descriptions 37 20 SDRAM Configuration Register SDCFG Field Descriptions 38 21 SDRAM Refresh Control Register SDRFC Field Descriptions 40 22 SDRAM Timing 1 Register SDTIM1 Field Descriptions 4 4 2 1 224 4 4 4 2 41 23 SDRAM Timing 2 Register SDTIM2 Field Descriptions 43 24 Burst Priority Register BPRIO Field Descriptions 44 25 DDR2 Memory Controller Control Register DMCCTL Field Descriptions
64. urpose pins that can be configured as either inputs or outputs When configured as an input you can detect the state of the input by reading the state of an internal register When configured as an output you can write to an internal register to control the state driven on the output pin 6 Preface SPRUEK5A October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Related Documentation From Texas Instruments SPRUEK8 TMS320DM647 DM648 DSP Inter Integrated Circuit I2C Module User s Guide describes the inter integrated circuit I2C peripheral in the TMS320DM647 DM648 Digital Signal Processor DSP The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C bus specification and connected way of an I2C bus External components attached to this 2 wire serial bus can transmit and receive up to 8 bit wide data to and from the DSP through the 2 peripheral This document assumes the reader is familiar with the I2C bus specification SPRUELO TMS320DM647 DM648 DSP 64 Bit Timer User s Guide describes the operation of the 64 bit timer in the TMS320DM647 DM648 Digital Signal Processor DSP The timer can be configured as a general purpose 64 bit timer dual general purpose 32 bit timers or a watchdog timer SPRUEL1 TMS320DM647 DM648 DSP Multichannel Audio Serial Port User s Guide describes the multichannel audio serial port McASP in the TMS320DM647 DM648
65. urst length of 8 and has a programmable CAS latency of 2 3 4 or 5 The CAS latency is three cycles in Figure 8 Read latency is equal to CAS latency plus additive latency The DDR2 memory controller always configures the memory to have an additive latency of 0 so read latency equals CAS latency Since the default burst size is 8 the DDR2 memory controller returns 8 pieces of data for every read command If additional accesses are not pending to the DDR2 memory controller the read burst completes and the unneeded data is disregarded If additional accesses are pending depending on the scheduling result the DDR2 memory controller can terminate the read burst and start a new read burst Furthermore the DDR2 memory controller does not issue a DCAB DEAC command until page information becomes invalid Figure 8 DDR2 READ Command DDR CLK DDR CLK DDR CKE DDR CS DDR RAS DDR CAS DDR WE DDR A 13 0 Gau DDR A 10 DDR DOM 3 0 amp CAS Latency DDR_D 31 0 po X2 X o2 X 03 X 24X25 X ds X 57 DDR Das fF J SPRUEK5A 2007 DSP DDR2 Memory Controller 17 Submit Documentation Feedback 5 INSTRUMENTS www ti com Peripheral Architecture 2 4 6 2 5 18 Write WRT Command Prior to a WRT command the desired bank and row are activated by the ACTV command Following the WRT command a write latency is incurred Wri
66. uts the starting column address and begins the write operation The write operation is followed by a autoprecharge precharge Table 3 Truth Table for DDR2 SDRAM Commands DDR2 SDRAM Signals CKE cs RAS CAS WE BA 2 0 A 13 11 9 0 A10 DDR CKE DDR2 Memory Previous DDR BA 2 0 Controller Signals Cycles Current Cycle DDR CS DDR RAS DDR CAS DDR WE 1 DDR A 13 11 9 0 A 10 ACTV H L H H Bank Row Address DCAB H H H L x x H H L L H L Bank X L MRS H H L L L L BAO OP Code EMRS H H L L L L BA OP Code READ H H L H L H BA Column Address L READ with H H L H L H BA Column Address H precharge WRT H H H L L BA Column Address L WRT with precharge H H L H L L BA Column Address REFR H H L L L H x X X SLFREFR H L L L H x x x entry SLFREFR L H H x x x x x x exit L H H H x x x NOP li H H H x X X DESEL H X X X x x x Power Down entry H X X X x x x L H H H x X X Power Down exit L H H X X x x x x H H H x X X 1 Legend H means logic high L means logic low X means don t care either H or L 2 refers to the bank address pins 2 0 SPRUEK5SA October 2007 Submit Documentation Feedback DSP DDR2 Memory Controller 13 D TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 4 1 2 4 2 14 Mode Register Set MRS and EMRS DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation These registers control burst type burst length CAS latency DLL ena
67. value after reset x value is indeterminate after reset Table 23 SDRAM Timing 2 Register SDTIM2 Field Descriptions Bit Field Value Description 31 25 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 24 23 ODT These bits specify the number of DDR CLK cycles from ODT enable to write data driven for DDR2 SDRAM ODT must be less than the CAS latency minus one Calculate using this formula ODT CAS latency taond 1 22 16 SXNR 0 7Fh These bits specify the minimum number of DDR CLK cycles from a self refresh exit to any other command except a read command minus 1 The value for these bits can be derived from the tsxNR AC timing parameter in the DDR2 data sheet Calculate using this formula T SXNR tsxur DDR_CLK 1 15 8 T SXRD O FFh These bits specify the minimum number of DDR CLK cycles from a self refresh exit to a read command minus 1 The value for these bits can be derived from the tsxgp AC timing parameter the DDR2 data sheet Calculate using this formula T SXRD tgxgp 1 7 5 0 71 These bits specify the minimum number of DDR CLK cycles from a last read command to a precharge command minus 1 The value for these bits can be derived from the ty AC timing parameter in the DDR2 data sheet Calculate using this formula T RTP 1 4 0 T CKE 0 1Fh These bits specify the minimum number of DDR CLK

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