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Motorola TMS320C6711D User's Manual

1. OOOOOOOOOO OOOOOOOOOO O ooo 0 635 9 11 13 15 17 19 10 12 14 16 18 20 Bottom View 4204396 A 04 02 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 151 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 MECHANICAL DATA MPBG276 MAY 2002 ZDP S PBGA N272 A1 Corner gt lt lt PLASTIC BALL GRID ARRAY oooo OOOOOOOOOO OOOOOOOOOO 13 15 17 19 0 635 9 1l 10 12 14 16 18 20 Bottom View NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 151 D This package is lead free 4204398 A
2. nese O j Table 14 McBSP0 and McBSP1 Registers HEX ADDRESS RANGE McBSP0 MeBsPi 0180 0009 0130 0000 DRRX The CPU and EDMA controller can only read this register they cannot write to it pee ACRONYM REGISTER DESCRIPTION McBSPx data receive register via Configuration Bus 3 TEXAS INSTRUMENTS 16 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 signal groups description CLKIN RESET CLKOUT3 4 NMI Reset and lt EXT INT7t CLKOUT2 Clock PLL Interrupts 4 EXT _INT6 lt INT5t CLKMODEO lt EXT INT4t PLLHV 4 e TDI gt gt RSV TCK gt gt RSV TRST IEEE Standard EMUO lt 1149 1 Reserved 4 gt JTAG Emulation EMI gt RSV s 42 EMU5 gt RSV Control Status 16 HPI HD 15 0 Host Port Interface HAS HCNTLO HR W HCNTL1 Hcs Control HDS1 HDS2 HHWIL gt gt HINT T For this device the CLKOUT2 pin is multiplexed with the GP 2 pin Default function is CLKOUT2 To use this as GPIO the GP2EN bit in the GPEN register and the GP2DIR bit in the GPDIR register must be properly configured t For this device the external interrupts EXT INT 7 4 go through the gener
3. development 22 3 asynchronous memory timing sss echt device support 3 synchronous burst memory timing CPU CSR register description synchronous DRAM cache configuration CCFG register description interrupt sources and interrupt selector BUSREQ bod ttd module and EDMA selector roset T Mns AA PLL and PLL controller rrr mere nin ids general purpose input output GPIO a ds MEE MEA multichannel buffered serial port timing power down mode logic 54 timer timing nic eee general purpose input output GPIO port timing JTAG test poit timing mechanical data power supply sequencing power supply decoupling IEEE 1149 1 JTAG compatibility statement device Speed cs beeen DERE RE Ra 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 REVISION HISTORY
4. Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respectively To ensure a proper logic level during reset when these pins are both routed out and 3 stated or not driven it is recommended an external 10 kQ pullup pulldown resistor be included to sustain the IPU IPD respectively To maintain signal integrity for the EMIF signals serial termination resistors should be inserted into all EMIF output signal lines HINT HCNTL1 HCNTLO W os Cra La La CN LN co La Me zz eg Pye 435 TEXAS INSTRUMENTS 26 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME DESCRIPTION Memory space enables e Enabled by bits 28 through 31 of the word address e Only one asserted during any external data access Byte enable control e Decoded from the two lowest bits of the internal address Byte write enables for most types of memory f f e Can be directly connected to SDRAM read and write mask signal SDQM EMIF BUS ARBITRATION EMIF ASYNCHRONOUS SYNCHRONOUS MEMORY CONTROL ECLKIN po External input clock source EMIF output clock depends on the EKSRC bit DEVCFG 4 and on bit GBLCTL 5
5. qr s 7 HSTROBE N x gt 18 eR C 12 2 lt 15 lad 5 u ee 7 9 16 9 HD 15 0 output _ gt 5 l lt 1st half word k 8 2nd half word HRDY case 1 5 8 174 45 HRDY case 2 n T For correct operation strobe the HAS signal only once per HSTROBE active cycle t HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 43 HPI Read Timing HAS Used 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 89 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 HOST PORT INTERFACE TIMING CONTINUED HAS 1 9 1 Se 2 lt 2 HCNTL 1 0 1 1 _ j HR W _ P 1 gt gt 2 porem 5 HHWIL SE 7 4 3 3 gt 5 mmm I ur HE ST 4 7 ___ _ 12 12 e 13 3 HD 15 0 input dese E al le 1st halfword 4 2nd halfwor 17 BY ___ JN T HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS Figure 44 HPI Write Timing HAS Not Used Tied High BS fF i 19 19 4 11
6. 11 lt 1094 lt HCNTL 1 0 141 4 11 103 1094 HRW 110 E 11 11 10 lt 10 gt lt O Fr X N 4 32 gt 4 gt HSTROBEt eee le 18 gt hk 18 HCS Em gt N p ee 13 12 13 HD 15 0 input V mel den ELT 4 le 1st half word 2nd half wor 17 gt le le 5 HRDY y y T For correct operation strobe the HAS signal only once per HSTROBE active cycle HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 45 HPI Write Timing HAS Used 35 TEXAS INSTRUMENTS 90 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSPT see Figure 46 GDPA 167 ZDPA 167 200 250 tsu FRH CKRL Setup time external FSR high before CLKR low ns NE th CKRL FRH Hold time external FSR high after CLKR low ns Lo 8 tsu DRV CKRL Setup time DR valid before CLKR low ns NM th CKRL DRV Hold time DR valid after CLKR low ns 10 tsu FXH CKXL Setup time external FSX high before CLKX low ns NENNEN NN 11 th CKXL FXH Hold time external FSX high after CLKX low ns T CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the t
7. 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 91 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED switching characteristics over recommended operating conditions for McBSPT see Figure 46 GDPA 167 ZDPA 167 PARAMETER 200 250 Delay time CLKS high to CLKR X high for internal CLKR X generated from 1 td CKSH CKRXH input 1 8 10 ns te CKRX Cycle time CLKR X CLKR X int 2281 twiCKRX Pulse duration CLKR X high or CLKR X low CLKR X int Cat C 1 ns 4 tg CKRH FRV Delay time CLKR high to internal FSR valid CLKR int 2 3 ns CKXH FXV Delay time CLKX high to internal FSX valid CLKX ext 2 9 Disable time DX high impedance following last data bit from CLKX int 4 Idis CKXH DXHZ CLKX high CLKX ext 15 10 DER CLKX int 3 2 Dill 4 D2l 13 CKXH DXV Delay time C igh to valid CLKX ext STD 10 Dal ns Delay time FSX high to DX valid FSX int 4 75 d FXH DXV ONLY applies when in data FSX ext delay 0 XDATDLY 00b mode T CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted Minimum delay times also represent minimum output hold times P 1 CPU clock frequency in ns For example when running parts at 200 MHz use P 5 ns The minimum CLKR X period is twice the CPU cycle time 2P and not faster than 75
8. be externally pulled down with a 10 resistor A PU Reserved leave unconnected do not connect to power or ground Reserved For proper device operation this pin must be externally pulled up with a 10 kQ resistor Reserved For proper device operation this pin must be externally pulled up with a 10 kQ resistor Reserved leave unconnected do not connect to power or ground Rv p D P Reserved leave unconnected do not connect to power or ground Reserved For new designs it is recommended that this be connected directly to CVpp RSV A12 power For old designs this be left unconnected Reserved For new designs it is recommended that this pin be connected directly to Vss RSV B11 in ground For old designs this pin can be left unconnected 1 Input O Output Z High impedance S Supply voltage GND Ground Analog signal PLL Filter t IPD Internal pulldown IPU Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respectively 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 31 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME DESCRIPTION SUPPLY VOLTAGE PINS gt 3 3 V supply voltage see the p
9. itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on chip as SYSCLK3 SYSCLK3 is derived from divider D3 off of PLLOUT see Figure 8 PLL and Clock Generator Logic The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time If either the input to the PLL changes due to 00 CLKMODEO or CLKIN or if the PLL multiplier is changed then software must enter bypass first and stay in bypass until the PLL has had enough time to lock see electrical specifications For the programming procedure see the TMS320C6000 DSP Software Programmable Phase Locked Loop PLL Controller Heference Guide literature number SPRU233 SYSCLK is the internal clock source for peripheral bus control SYSCLK2 Divider D2 must be programmed to be half of the SYSCLK1 rate For example if D1 is configured to divide by 2 mode 2 then D2 must be programmed to divide by 4 mode 4 SYSCLK is also tied directly to CLKOUT2 pin see Figure 8 During the programming transition of Divider D1 and Divider D2 resulting SYSCLK1 and SYSCLK2 output clocks see Figure 8 the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to ensure that SYSCLK always runs at half the SYSCLK1 rate or slower For example if the divider ratios of D1 and D2 are to be change
10. 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 75 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles see Figure 31 GDPA 167 ZDPA 167 200 250 MIN 6 tsu EDV EKOH Setup time read EDx valid before ECLKOUT high th EKOH EDV Hold time read EDx valid after ECLKOUT high ns t The SDRAM interface takes advantage of the internal burst counter in the SDRAM Accesses default to incrementing 4 word bursts but random bursts and decrementing bursts are done by interrupting bursts in progress All burst types can sustain continuous data flow switching characteristics over recommended operating conditions for synchronous DRAM cyclest see Figure 31 Figure 37 ZDPA 167 PARAMETER 200 250 MIN A td EKOH CEV Delay time ECLKOUT high to valid 1 5 7 tg EKOH BEV Delay time ECLKOUT high to BEx valid td EKOH BEIV Delay time ECLKOUT high to BEx invalid 5 ns ns 5 ns 57 5 12 td EKOH RAS Delay time ECLKOUT high to AOE SDRAS SSOE valid ns 7 3 4 5 e H 1 td EKOH EAIV Delay time ECLKOUT high to EAx invalid 1 td EKOH CASV Delay time ECLKOUT high to ARE SDCAS SSADS valid 1 H 1 1 2 3 4 5 1 11 12 T The SDRAM interface takes advantage of the internal burst counter in the SDRAM Accesses default to inc
11. EKSRC 0 ECLKOUT is based on the internal SYSCLK3 signal from the clock generator default EKSRC 1 ECLKOUT is based on the the external EMIF input clock 10 oz source pin ECLKIN EKEN 0 ECLKOUT held low 1 ECLKOUT enabled to clock default 388 Asynchronous memory read enable SDRAM column address strobe SBSRAM address strobe DRAS Asynchronous memory output enable SDRAM row address strobe SBSRAM output enable awe Asynchronous memory write enable SDRAM write enable SBSRAM write enable ARDY Asynchronous memory ready input 1 Input O Output Z High impedance S Supply voltage GND Ground Analog signal PLL Filter IPD Internal pulldown IPU Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respectively To maintain signal integrity for the EMIF signals serial termination resistors should be inserted into all EMIF output signal lines 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 27 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME DESCRIPTION N EMIF external address Y Y V V lt N ARIA N Y EMIF y 1 Input O Output Z Hi
12. Emulation boot mode is a variation of host boot In this mode it is not necessary for a host to load code or to set DSPINT to release the CPU from the stalled state Instead the emulator will set DSPINT if it has not been previously set so that the CPU can begin executing code from address 0 Prior to beginning execution the emulator sets a breakpoint at address 0 This prevents the execution of invalid code by halting the CPU prior to executing the first instruction Emulation boot is a good tool in the debug phase of development boot using default ROM timings Upon the release of internal reset the 1K Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings while the CPU is internally stalled The data should be stored in the endian format that the system is using The boot process also lets you choose the width of the ROM In this case the EMIF automatically assembles consecutive 8 bit bytes or 16 bit half words to form the 32 bit instruction words to be copied The transfer is automatically done by the EDMA as a single frame block transfer from the ROM to address 0 After completion of the block transfer the CPU is released from the stalled state and start running from address 0 reset A hardware reset RESET is required to place the DSP into a known good state out of power up The RESET signal can be asserted pulled low prior to ramping the core and
13. t The reference points for the rise and fall transitions are measured at VoL MAX and Vor MIN ECLKIN period in ns is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns ECLKIN 7 7N 7 K 1 4 ee cc ee ee 4 2 ECLKOUT in Figure 26 ECLKOUT Timings 435 TEXAS INSTRUMENTS 70 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cyclestt see Figure 27 Figure 28 GDPA 167 ZDPA 167 200 250 MN EN th EKOH ARDY Hold time ARDY valid after ECLKOUT high T To ensure data setup time simply program the strobe width wide enough ARDY is internally synchronized The ARDY signal is recognized in the cycle for which the setup and hold time is met To use ARDY as an asynchronous input the pulse width of the ARDY signal should be wide enough e g pulse width 2E to ensure setup and hold time is met tRS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold These parameters are programmed via the EMIF CE space control registers ECLKOUT period in ns switching characteristics over recommended operating conditions for asynchronous memory cyclesti see Figure 27 28
14. Texas Instruments recommends two of three possible prefix designators for support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully T s standard warranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices
15. n value after reset 1 Do not write non zero values to these bit locations Table 17 Device Configuration DEVCFG Register Selection Bit Descriptions Reserved Do not write non zero values to these bit locations EMIF input clock source bit Determines which clock signal is used as the EMIF input clock 0 SYSCLK3 from the clock generator is the input clock source default 1 ECLKIN external pin is the EMIF input clock source Reserved Reserved Do not write non zero values to these bit locations 35 TEXAS INSTRUMENTS 22 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names the associated pin ball numbers along with the mechanical package designator the pin type l O Z or 2 whether the pin has any internal pullup pulldown resistors and a functional pin description For more detailed information on device configuration see the Device Configurations section of this data sheet Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 23 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions SIGNAL NAME DESCRIPTION CLOCK PLL EM For this device the CLKOUT2 pin is multiplexed with the GP 2 pin Clock ou
16. AIA Ground pins The center thermal balls J9 J12 9 12 19 112 M9 M12 shaded are all tied to ground and act as both electrical grounds and thermal relief thermal dissipation m c A 4 H17 J4 J9 Jio Ji2 K2 K9 Kio Kn K12 K20 L9 L10 EI 112 M4 9 10 M12 N4 N17 P4 P17 P19 T4 7 11 Input O Output Z High impedance Supply voltage GND Ground A Analog signal PLL Filter Shaded pin numbers denote the center thermal balls for the GDP package 35 TEXAS INSTRUMENTS 34 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME GDP DESCRIPTION ZDP GROUND PINS CONTINUED U4 08 09 20 Ground Y1 Y2 Y20 T Input O Output Z High impedance S Supply voltage GND Ground A Analog signal PLL Filter 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 35 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 development support offers an extensive line of development tools for the TMS320C6000 DSP platform including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and
17. EE S320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Excellent Price Performance Floating Point e 32 Bit External Memory Interface EMIF Digital Signal Processor DSP Glueless Interface to Asynchronous TMS320C6711D Memories SRAM and EPROM Eight 32 Bit Instructions Cycle Glueless Interface to Synchronous 167 200 250 MHz Clock Rates Memories SDRAM and SBSRAM 6 5 4 ns Instruction Cycle Time 256M Byte Total Addressable External 1000 1200 1500 MFLOPS Memory Space Advanced Very Long Instruction Word e 16 Bit Host Port Interface VLIW C67x DSP Core Two Multichannel Buffered Serial Ports Eight Highly Independent Functional McBSPs Units Direct Interface to T1 E1 MVIP SCSA Four ALUS Floating and Fixed Point Framers Two ALUs Fixed Point ST Bus Switching Compatible Fixed Point AC97 Compatible Load Store Architecture With 32 32 Bit Serial Peripheral Interface SPI General Purpose Registers Compatible Motorola T 1 2 Size Two 32 Bit General Purpose Timers All Instructions Conditional e Instruction Set Features Flexible Software Configurable PLL Based Clock Generator Module Hardware Support for IEEE Single Precision and Double Precision A Dedicated General Purpose Input Output Byte Addressable 8 16 32 Bit Data 1149 1 JTAGT 8 Bit Overflow Protection Boundary Scan
18. OCTOBER 2005 TIMER TIMING timing requirements for timer inputst see Figure 52 GDPA 167 ZDPA 167 200 tw TINPH Pulse duration TINP high tw TINPL Pulse duration TINP low 2P ns P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns switching characteristics over recommended operating conditions for timer outputst see Figure 52 GDPA 167 ZDPA 167 PARAMETER 200 tw TOUTH Pulse duration TOUT high tw TOUTL Pulse duration TOUT low Hs TP 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns k 2 1 Ff X N 0 0 0 0 0 0 3 TOUTx N Figure 52 Timer Timing 35 TEXAS INSTRUMENTS 100 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 GENERAL PURPOSE INPUT OUTPUT GPIO PORT TIMING timing requirements for GPIO inputst see Figure 53 GDPA 167 ZDPA 167 200 250 tw GPIH Pulse duration high tw GPIL Pulse duration GPIx low 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns The pulse width given is sufficient to generate a CPU interrupt or an EDMA event However if a user wants to have the DSP recognize the changes through software polling of the GPIO register the GPIx duration must be exten
19. OCTOBER 2005 switching characteristics over recommended operating conditions for McBSP as SPI master or slave CLKSTP 10b CLKXP see Figure 50 GDPA 167 ZDPA 167 200 PARAMETER 250 MAX MAX 1 tnc Hold time FSX low h CKXH FXL after CLKX high 2 taFxL ckxL Delay time FSX low to CLKX low H 2 H 3 Delay time CLKX low to DX valid 6 2 10P 17 ns Disable time DX high impedance following last data bit from Disable time DX high impedance following last data bit from FSX 7 tdis FXH DXHZ high 1 E 9 2P 3 6 17 8 ta FXL DXV Delay time FSX low to DX valid 4 2 8 17 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 Sample rate generator input clock 2P if CLKSM 1 P 1 CPU clock frequency Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period CLKX period 1 CLKGDV S H CLKX high pulse width CLKGDV 2 1 8 if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero 1 FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FS
20. board route delays and how they are perceived by the DSP and the external device 66 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION CONTINUED Table 35 Board Level Timings Example see Figure 21 DESCRIPTION lt a ECLKOUT N Output from DSP ES 1 ECLKOUT Input to External Device 2 Control SignalsT Output from DSP his T 4 Control Signals 6 ee a 5 Input to External Device 7 oly Data Signalst _ 9 Output from External Device 10 11 4 Data Signalst Input to DSP n T Control signals include data for Writes Data signals are generated during Reads from an external device Figure 21 Board Level Input Output Timings 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 67 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS timing requirements for CLKINTt see Figure 22 GDPA 167 ZDPA 167 PLL MODE BYPASS MODE PLL MODE BYPASS MODE PLLEN 1 PLLEN 0 PLLEN 1 PLLEN 0 T The reference points for the rise and fall transitions are measured at Vi MAX and MIN tC CLKIN cycle time in nanoseconds
21. ns For example when CLKIN frequency is 40 MHz use C 25 ns See the PLL and PLL controller section of this data sheet timing requirements for CLKINT 8 see Figure 22 PLL MODE BYPASS MODE PLLEN 1 PLLEN 0 wm MAX tt CLKIN Transition time CLKIN T The reference points for the rise and fall transitions are measured at MAX and MIN tC CLKIN cycle time in nanoseconds ns For example when frequency is 40 MHz use C 25 ns See the PLL and PLL controller section of this data sheet 6 5 1 e Z Zx DJ ak 4 k 3 4 4 le Figure 22 CLKIN Timings 35 TEXAS INSTRUMENTS 68 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS CONTINUED switching characteristics over recommended operating conditions for CLKOUT2Tt see Figure 23 GDPA 167 ZDPA 167 PARAMETER 200 250 MN ns Transition time CLKOUT2 T The reference points for the rise and fall transitions are measured at MAX and Voy MIN t C2 CLKOUT2 period in ns CLKOUT2 period is determined by the PLL controller output SYSCLK2 period which must be set to CPU period divide by 2 72227 1 aie k 3 4 Figure 23 CLKOUT2 Timings switching
22. recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 2 All voltage values are with respect to Vss recommended operating conditions NOM x e t a v All signals except CLKS1 DR1 and RESET All signals except CLKS1 DR1 and RESET WIIWIQGCCCGCGH IxI QUWIA IL Low level ow level input voltage GiKS1 DR1 and RESET 0 3 DVDD All signals except ECLKOUT CLKOUT2 CLKS1 and IOH High level output current DR1 mA ECLKOUT and CLKOUT2 All signals except ECLKOUT CLKOUT2 CLKS1 and DR1 mA Operating case Maximum voltage during overshoot See Figure 19 4 Maximum voltage during undershoot Figure 20 V Operating case A version C6711DGDPA and C6711DZDPA 40 105 C temperature t The core supply should be powered up prior to and powered down after the I O supply Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage These values are compatible with existing 1 26 designs T Refers to DC or steady state currents only actual switching currents are higher For more details see the device specific IBIS models The absolute maximum ratings should not be exceeded for more than 30 of the cycle period 435 TEXAS INSTRUMENTS 62 POST OFFICE BOX 1443 HOUSTON TEX
23. voltages or after the core and voltages have reached their proper operating conditions As a best practice reset should be held low during power up Prior to deasserting RESET low to high transition the core and voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 61 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 absolute maximum ratings over operating case temperature range unless otherwise noted t Supply voltage range CVpp see 2 0 3 V to 1 8 V Supply voltage range DVpp see Note 2 0 3Vto4 V Inp t voltage range Tissa RE ws Sas ee 0 3 V to DVpp 0 5 V Output voltage range 2222224 ce 0 3 V to DVpp 0 5 V Operating case temperature ranges Tc default 0 C to 90 C A version C6711DGDPA and C6711DZDPA 40 C to105 C Storage temperature range Inn 65 C to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
24. 04 02 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual pro
25. 86 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 HOST PORT INTERFACE TIMING timing requirements for host port interface cyclestt see Figure 42 Figure 43 Figure 44 and Figure 45 GDPA 167 ZDPA 167 200 250 tsu SELV HSTBL Setup time select signals valid before HSTROBE low th HSTBL SELV Hold time select signals valid after HSTROBE low Pulse duration HSTROBE low host read access 3 tw HSTBL Pulse duration HSTROBE low host write access se duration HSTROBE high between consecutive accesses th HASL SELV Hold time select signals valid after HAS low tsu HDV HSTBH Setup time host data valid before HSTROBE high 13 tn HsTBH HDV Hold time host data valid after HSTROBE high Hold time HSTROBE low after HRDY low HSTROBE should not be inactivated until HRDY is active low otherwise HPI writes will not complete properly 4 th HRDYL HSTBL 18 tgsy HASL HSTBL Setup time HAS low before HSTROBE low 19 tn HSTBL HASL Hold time HAS low after HSTROBE low T HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns Select signals include HCNTL 1 0 HR W and HHWIL 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 87 TMS320C6711D FLOAT
26. Endian mode correctness EMIFBE HD12 The EMIF data will always be presented on the ED 7 0 side of the bus regardless of the endianess mode Little Big Endian In Little Endian mode HD8 1 the 8 bit or 16 bit EMIF data will be present on the ED 7 0 side of the bus In Big Endian mode HD8 0 the 8 bit or 16 bit EMIF data will be present on the ED 31 24 side of the bus default G20 on HD11 A16 HD10 B16 HD9 16 HD8 B17 VO Z This new functionality does not affect systems using the curent default value of HD12 1 For e 020 more detailed information on the big endian mode correctness see the EMIF Big Endian Mode Correctness portion of this data sheet HD7 HD6 Bootmode HD 4 3 00 HPlboot Emulation boot 01 CE1 width 8 bit Asynchronous external ROM boot with default timings default mode 10 CE1 width 16 bit Asynchronous external ROM boot with default timings 11 CE1 width 32 bit Asynchronous external ROM boot with default timings Other HD pins HD 15 13 11 9 7 5 2 0 have pullups pulldowns IPUs IPDs For proper de vice operation of the HD 14 13 11 9 7 1 0 do not oppose these pins with external IPUs IPDs at reset however the HD 15 6 5 2 pins can be opposed and driven during reset 11 Input O Output Z High impedance S Supply voltage GND Ground A Analog signal PLL Filter t IPD Internal pulldown
27. INSTRUMENTS 72 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING CONTINUED Setup 2 Strobe 3 Not Ready Hold 2 ecikour _ _ _ A _ _ ASA _ _ _ _ _ em qecscm o 8 BE 3 0 BE oe Ea 21 21 ___X Address X J T m Write Dat AOE SDRAS SSOET i U E E E ARE SDCAS SSADST gt 10 gt T AWE SDWE SSWET E EE EE gt N J Y gt 6 gt IT 6 7 m O umm 7 CT ED 31 0 respectively during asynchronous memory accesses Figure 28 Asynchronous Memory Write Timing Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 73 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS BURST MEMORY TIMING timing requirements for synchronous burst SRAM cyclest see Figure 29 tsu EDV EKOH Setup time read EDx valid before ECLKOUT high th EKOH EDV Hold time read EDx valid after ECLKOUT high T The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM Accesses default to incrementing 4 word bursts but random bursts and decrementing burs
28. Mbps 13 3 ns This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167 MHz and 200 MHz CPU clocks or 50 Mbps for 100 MHz CPU clock where the McBSP is either the master or the slave Care must be taken to ensure that the AC timings specified in this data sheet are met The maximum bit rate for McBSP to McBSP communications is 67 Mbps therefore the minimum CLKR X clock cycle is either twice the CPU cycle time 2P or 15 ns 67 MHz whichever value is larger For example when running parts at 167 MHz P 6 ns use 15 ns as the minimum CLKR X clock cycle by setting the appropriate CLKGDV ratio or external clock source When running parts at 60 MHz P 16 67 ns use 2P 33 ns 30 MHz as the minimum CLKR X clock cycle The maximum bit rate for McBSP to McBSP communications applies when the serial port is a master of the clock and frame syncs with CLKR connected to CLKX FSR connected to FSX CLKXM FSXM 1 and CLKRM FSRM 0 in data delay 1 or 2 mode R XDATDLY 01b or 10b and the other device the McBSP communicates to is a slave C Hor L S sample rate generator input clock 2P if CLKSM 1 P 1 CPU clock frequency sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S
29. S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero 1 FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX 35 TEXAS INSTRUMENTS 96 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED Figure 49 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 timing requirements for McBSP as SPI master or slave CLKSTP 10b CLKXP 11 see Figure 50 GDPA 167 ZDPA 167 200 250 MASTER SLAVE th CKXH DRV Hold time DR valid after CLKX high 5 12 1 CPU clock frequency ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 97 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292
30. TMS320C6711B devices GFN packages to the TMS320C6711C device GDP package 7MSS320C6711 TMS320C6711B TMS320C6711C TMS320C6711D Digital Signal Processors Silicon Errata C6711 Silicon Revisions 1 0 1 2 and 1 3 C6711B Silicon Revisions 2 0 and 2 1 C6711C Silicon Revision 1 1 and C6711D Silicon Revision 2 0 literature number SPRZ173K or later categorizes and describes the known exceptions to the functional specifications and usage notes for the TMS320C6711 TMS320C6711B TMS320C6711C and TMS320C6711D DSP devices The TMS320C6711D C6712D C6713B Power Consumption Summary application report literature number TMS320C6712D and TMS320C6711D DSP devices The Using IBIS Models for Timing Analysis application report literature number SPRA839 describes how to properly use IBIS models to attain accurate timing analysis for a given system The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment IDE For a complete listing of C60007 DSP latest documentation visit the Texas Instruments web site on the Worldwide Web at http www ti com uniform resource locator URL See the Worldwide Web URL for the application reports How To Begin Development Today with the TMS320C6211 DSP literature number SPRA474 and How To Begin Development with the TMS320C6711 DSP literature number SPRA522 which describe in more detail the similarities differences between the C62
31. The TMS320C6711D device specific documentation has been split from TMS320C6711 TMS320C6711B TMS320C6711C TMS320C6711D Floating Point Digital Signal Processors literature number SPRSO88N into separate Data Sheet literature number SPRS292 It also highlights technical changes made to SPRS292 to gen erate SPRS292A these changes are marked by Revision in the Revision History table below Scope Updated information on McBSP and JTAG for clarification Changed Pin Description for A12 and B11 Revisions SPRS292 and SPRS292A Updated Nomenclature figure by adding device specific information for the ZDP package Updated Characteristics of the Processor table with device specific information footnote for the ZDP package TI Recommends for new designs that the following pins be configured as such Pin A12 connected directly to CVpp core power Pin B11 connected directly to Vss ground o ADDITIONS CHANGES DELETIONS 21 Device Configurations Device Configurations Pins at Device Reset HD 4 3 HD8 HD12 and CLKMODEO section Removed CE1 width 32 bit from Functional Description for 00 in HD 4 3 BOOTMODE Configuration Pin 25 Terminal Functions Resets and Interrupts section Updated IPU IPD for RESET Signal Name from IPU to 26 Terminal Functions Host Port Interface section Removed CE1 width 32 bit from Description for 00 in Bootmode HD 4 3 31 Terminal Functions Reserved for Test
32. are to be used TI device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example GDP the temperature range for example blank is the default commercial temperature range and A is the extended temperature range and the device speed range in megahertz for example 167 is 167 MHz The ZDP package like the GDP package is a 272 ball plastic BGA only with Pb free balls For device part numbers and further ordering information for TMS320C6711D in the GDP and ZDP package types see the TI website http www ti com or contact your TI sales representative TMS320 is a trademark of Texas Instruments 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 37 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 device and development support tool nomenclature continued TMS 320 67110 GDP 250 PREFIX TMX x device Prototype device DEVICE SPEED RANGE TMS Qualified device SMJ MIL PRF 38535 QML 167 MHz SM High Rel non 38535 200 MHz 250 MHz DEVICE FAMILY 320r320 TMS320 DSP family TEMPERATURE RANGE DEFAULT 0 C TO 90 C Blank 0 C to 90 C commercial temperature A 40 C to 105 C extended temperature TECHNOLOGY C CMOS PACKAGE 8 GDP 272 pin plastic BGA ZDP 272 pin plastic BGA with Pb free soldered
33. as the McASP or McBSP This can be avoided by setting the P bit to 1 because the EDMA will assume a higher priority than the L1D memory system when accessing L2 memory For more detailed information on the P bit function and for silicon advisories concerning EDMA L2 memory accesses blocked see the TMS320C6711 TMS320C6711B TMS320C6711C TMS320C6711D Digital Signal Processors Silicon Errata literature number SPRZ1 73K or later 31 30 10 9 8 7 3 2 0 Reserved Reserved L2MODE R W 0 R x W 0 W 0 R 0 0000 R W 000 Legend R Readable R W Readable Writeable n value after reset x undefined value after reset Figure 7 Cache Configuration Register CCFG Table 19 CCFG Register Bit Field Description DESCRIPTION L1D requestor priority to L2 bit 0 L1D requests to L2 higher priority than TC requests 1 TC requests to L2 higher priority than L1D requests Reserved Read only writes have no effect Invalidate L1P bit Normal L1P operation All L1P lines are invalidated Invalidate L1D bit 0 Normal L1D operation 1 AIIL1D lines are invalidated Reserved Read only writes have no effect L2 operation mode bits L2MODE 000b L2 Cache disabled All SRAM mode 64K SRAM L2MODE 001b 1 way Cache 16K L2 Cache 48K SRAM 010b 2 way Cache 32K L2 Cache 32K SRAM 011b 3 way Cache 48K L2 Cache 16K SRAM 111b 4 way Cache 64K L2 Cache no SRAM All others Reserved 435 TEXAS INSTRUMENTS 42 POST O
34. balls DEVICE C6711D TBGA Ball Grid Array t The ZDP mechanical package designator represents the version of the GDP with Pb Free soldered balls The ZDP package devices are supported in the same speed grades as the GDP package devices available upon requesi For actual device part numbers P Ns and ordering information see the Mechanical Data section of this document or the TI website www ti com Figure 5 TMS320C6711D DSP Device Nomenclature MicroStar BGA and PowerPAD are trademarks of Texas Instruments 38 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development The types of documentation available include data sheets such as this document with design specifications complete user s reference guides for all devices and tools technical briefs development support tools on line help and hardware and software applications The following is a brief descriptive list of support documentation specific to the C6000 DSP devices The TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 describes the C6000 CPU DSP core architecture instruction set pipeline and associated interrupts The TMS320C6000
35. com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated
36. or to hold the condition for conditional instructions if the condition is not automatically true The two M functional units are dedicated for multiplies The two S and L functional units perform a general set of arithmetic logical and branch functions with results available every clock cycle The processing flow begins when a 256 bit wide instruction fetch packet is fetched from a program memory The 32 bit instructions destined for the individual functional units are linked together by 1 bits in the least significant bit LSB position of the instructions The instructions that are chained together for simultaneous execution up to eight in total compose an execute packet A 0 in the LSB of an instruction breaks the chain effectively placing the instructions that follow it in the next execute packet If an execute packet crosses the fetch packet boundary 256 bits wide the assembler places it in the next fetch packet while the remainder of the current fetch packet is padded with NOP instructions The number of execute packets within a fetch packet can vary from one to eight Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256 bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched After decoding the instructions simultaneously drive all active functional units for a maximum execution rate of eight i
37. section Updated Description for RSV Signal Name A12 GDP ZDP Updated Description for RSV Signal Name B11 GDP ZDP 31 Terminal Functions Reserved for Test section Updated changed Description for RSV Signal Name A12 GDP to recommended Revision A Updated changed Description for RSV Signal Name B11 GDP to recommended Revision A 38 Device Support device and development support tool nomenclature Updated figure for clarity 39 Device Support documentation support section Updated paragraphs for clarity 58 IEEE 1149 1 JTAG Compatibility Statement section Updated added paragraphs for clarity 62 Recommended Operating Conditions Added Vos Maximum voltage during overshoot row and associated footnote Added Vys Maximum voltage during undershoot row and associated footnote 65 Parameter Measurement Information AC transient rise fall time specifications section Added AC Transient Specification Rise Time figure Added AC Transient Specification Fall Time figure 93 MULTICHANNEL BUFFERED SERIAL PORT TIMING switching characteristics over recommended operating conditions for McBSP section Updated McBSP Timings figure for clarification 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 3 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 GDP and ZDP BGA packages bottom view GDP and ZDP 272 PIN BALL GRID ARRAY BGA PACKAGEST BOTTOM V
38. the C6711D device also offers cost effective solutions to high performance DSP programming challenges The C6711D DSP possesses the operational flexibility of high speed controllers and the numerical capability of array processors This processor has 32 general purpose registers of 32 bit word length and eight highly independent functional units The eight functional units provide four floating fixed point ALUs two fixed point ALUs and two floating fixed point multipliers The C6711D can produce two MACs per cycle for a total of 400 MMACS The C6711D DSP also has application specific hardware logic on chip memory and additional on chip peripherals The C6711D device uses a two level cache based architecture and has a powerful and diverse set of peripherals The Level 1 program cache L1P is a 32 Kbit direct mapped cache and the Level 1 data cache L1D is a 32 Kbit 2 way set associative cache The Level 2 memory cache L2 consists of a 512 Kbit memory space that is shared between program and data space L2 memory can be configured as mapped memory cache or combinations of the two The peripheral set includes two multichannel buffered serial ports McBSPs two general purpose timers a host port interface HPI and a glueless external memory interface EMIF capable of interfacing to SDRAM SBSRAM and asynchronous peripherals The C6711D has a complete set of development tools which includes a new C compiler an assembly optimizer to simplif
39. the CSR to account for this delay If PD1 mode is terminated by a non enabled interrupt the program execution returns to the instruction where PD1 took effect If PD1 mode is terminated by an enabled interrupt the interrupt service routine will be executed first then the program execution returns to the instruction where PD1 took effect In the case with an enabled interrupt the GIE bit in the CSR and the NMIE bit in the interrupt enable register IER must also be set in order for the interrupt service routine to execute otherwise execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt PD2 and modes can only be aborted by device reset Table 33 summarizes all the power down modes 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 55 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Table 33 Characteristics of the Power Down Modes PRWD FIELD POWER DOWN BITS 15 10 MODE WAKE UP METHOD EFFECT ON CHIP S OPERATION CPU halted except for the interrupt logic Power down mode blocks the internal clock inputs at the boundary of the CPU preventing most of the CPU s logic from 010001 PD1 Wake by an enabled or switching During PD1 EDMA transactions can proceed non enabled interrupt between peripherals and internal memory Output clock from PLL is halted stopping the internal clock structur
40. values for the PLLDIVO PLLDIV1 PLLDIV2 and PLLDIVS bits are 1 1 2 and 2 respectively 00000 10000 17 00001 2 10001 18 00010 8 10010 19 00011 4 10011 20 00100 5 10100 21 00101 6 10101 22 00110 7 10110 23 PLLDIVX 00111 8 10111 24 01000 9 11000 25 01001 10 11001 26 01010 1 11010 27 01011 12 11011 28 01100 11100 29 01101 14 11101 30 01110 15 11110 31 01111 16 11111 32 t Note that SYSCLK2 must run at half the rate of SYSCLK1 Therefore the divider ratio of D2 must be two times slower than D1 For example if D1 is set to 2 then D2 mustbe set to 4 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 51 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller continued OSCDIV1 Register 0x01B7 C124 31 28 27 24 23 20 19 16 Reserved R 0 15 14 12 11 e 7 5 4 3 2 1 0 OD1EN Reserved OSCDIV1 R W 1 R 0 R W 0 0111 Legend R Read only R W Read Write n value after reset The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3 The CLKOUTS signal does not go through the PLL path Table 32 Oscillator Divider 1 Register OSCDIV1 DESCRIPTION 31 16 Reserved Read only writes have no effect Oscillator Divider 1 Enable OD1EN 0 Oscilator Divider 1 Disabled 1 Oscillator Divider 1 Ena
41. 0x00010801 for PLL Controller Reserved PLL control status register OIBTCT4 OPBTCHF 01B7 C110 PLLM PLL multiplier control register 0 pu Table 11 GPIO Registers REGISTER NAME 01B0 0000 GPEN GPIO enable register 01B0 0004 GPDIR GPIO direction register 01B0 0008 GPVAL GPIO value register Reserved GPIO delta high register Table 12 HPI Registers HPID HPI data register Host read write access only HPIA HPI address register Host read write access only 0188 0000 HPIC HPI control register Both Host CPU read write access 00880001 O18BFFFF Reserved 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 15 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 peripheral register descriptions continued Table 13 Timer 0 and Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS TIMER 0 TIMER 1 input clock cycles to count C Contains the current value of 0194 0008 0198 0008 Timer x counter register the incrementing counter Determines the operating mode of the timer monitors the 0194 0000 0198 0000 TLx Timer x control register timer status and controls the function of the TOUT pin Contains the number of timer 0194 0004 0198 0004 PRDx Timer x period register This number controls the TSTAT signal frequency 0194000C 0197
42. 1 CPU clock frequency Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX Figure 48 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 95 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for McBSP as SPI master or slave CLKSTP 11b CLKXP 01 see Figure 49 GDPA 167 ZDPA 167 200 250 5 SLAVE th CKXH DRV Hold time DR valid after CLKX high 5 12P TP 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes CLKG is programmed as 1 2 of t
43. 10110 x22 00111 x7 10111 x23 01000 x8 11000 x24 01001 x9 11001 x25 01010 x10 11010 Reserved 01011 x11 11011 Reserved 01100 x12 11100 Reserved 01101 x13 11101 Reserved 01110 x14 11110 Reserved 01111 x15 11111 Reserved PLLM select values 00000 through 00011 and 11010 through 11111 are not supported 4 6 INSTRUMENTS 50 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller continued PLLDIVO PLLDIV1 PLLDIV2 and PLLDIV3 Registers 0x01B7 C114 0x01B7 C118 0x01B7 C11C and 0x01B7 C120 respectively Reserved PLLDIVx R W 1 R 0 RAV x Legend R Read only R W Read Write n value after reset T Default values for the PLLDIVO PLLDIV1 PLLDIV2 and PLLDIV bits are 1 0 0000 1 0 0000 2 0 0001 and 2 0 0001 respectively CAUTION D1 and D2 should never be disabled D3 should only be disabled if ECLKIN is used Table 31 PLL Wrapper Divider x Registers Prescaler Divider DO and Post Scaler Dividers D1 D2 and D3 t DESCRIPTION 31 16 Reserved Read only writes have no effect Divider Dx Enable where x denotes 0 through 3 0 Divider x Disabled No clock output DxEN 1 Divider x Enabled default These divider enable bits are device specific and must be set to 1 to enable Reserved Read only writes have no effect PLL Divider Ratio Default
44. 11 and C6711 C6000 DSP devices TMS320C62x is a trademark of Texas Instruments 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 39 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 CPU CSR register description The CPU control status register CSR contains the CPU ID and CPU Revision ID bits 16 31 as well as the status of the device power down modes PWRD field bits 15 10 program and data cache control modes the endian bit EN bit 8 and the global interrupt enable GIE bit 0 and previous GIE PGIE bit 1 Figure 6 and Table 18 identify the bit fields in the CPU CSR register For more detailed information on the bit fields in the CPU CSR register see the TMS320C6000 DSP Peripherals Overview Reference Guide literature number SPRU190 and the TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 31 24 23 16 CPU ID REVISION ID R 0x02 R 0x03 15 10 9 8 7 6 5 4 2 1 0 PWRD SAT EN PCC DCC PGIE GIE R W 0 R C 0 1 R W 0 R W 0 R W 0 R W 0 Legend R Readable by the MVC instruction R W Readable Writeable by the MVC instruction W Read write n value after reset x undefined value after reset C Clearable by the MVC instruction Figure 6 CPU Control Status Register CPU CSR 35 TEXAS INSTRUMENTS 40 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SI
45. 7 Disable time DX high impedance following last data bit from td EXL DXV Delay time FSX low to DX valid L 2 L 65 4P 2 8P 17 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 Sample rate generator input clock 2P if CLKSM 1 P 1 CPU clock frequency Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX 4 5 DR _ Bito n2 X n3 X n4 X Figure 51 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 99 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292
46. A sync event number see Table 23 users can map any EDMA event to the EDMA channel For example if EVTSEL15 is programmed to 00 0001b the EDMA selector code for TINTO then channel 15 is triggered by TimerO TINTO events 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 45 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller The device includes a PLL and a flexible PLL controller peripheral consisting of a prescaler DO and four dividers OSCDIV1 D1 D2 and D3 The PLL controller is able to generate different clocks for different parts of the system i e DSP core Peripheral Data Bus External Memory Interface McASP and other peripherals Figure 8 illustrates the PLL the PLL controller and the clock generator logic RRE 53 3 PLLHV C1 1 C2 mme one on V E CLKMODEO PLLOUT CLKIN X PLLREF DIVIDER DO PLLEN PLL_CSR 0 PLL ea 4910225 to x25 DIVIDER D1 Reserved DSP Core D1EN PLLDIV1 15 DOEN PLLDIVO 15 SYSCLK2 Peripherals CLKOUT3 osco D2EN PLLDIV2 15 For Use lt 4 System OD1EN OSCDIV1 15 SYScLK3 D3EN PLLDIV3 15 ECLKIN gt EMIF Clock Input 1 Of EKSRC Bit DEVCFG 4 C6711D DSP ECLKOUT t Divider
47. AS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 electrical characteristics over recommended ranges of supply voltage and operating case temperature unless otherwise noted PARAMETER High level output All signals except CLKS1 and Vi DVpp MIN 1 MAX 2 4 V OF voltage TT All signals except CLKS1 and 04 ow level outpu DR1 DVpp MIN IoL MAX V voltage CLKS1 and 1 All signals except CLKS1 and 170 uA Input current VI Vss to DVpp CLKS1 and DR1 All signals except CLKS1 and ff Off state output Vo DVpD or 0 V E gt current CLKS1 and DR1 uA GDP CVpp 1 4 V CPU clock 250 MHz GDP ZDP CVpp 1 26 V CPU clock 200 MHz GDPA ZDPA CVpp 1 26 V CPU clock 167 MHz IDD3V IO supply current d 75 T For test conditions shown as MIN use the appropriate value specified the recommended operating conditions table For this device these currents were measured with average activity 50 high 50 low power at 25 C case temperature and 100 MHz EMIF This model represents a device performing high DSP activity operations 50 of the time and the remainder performing low DSP activity operations The high low DSP activity models are defined as follows High DSP Activity Model CPU 8 instructions cycle with 2 LDDW instructions L1 Data Memory 128 bits cycle via LDDW instruction
48. Compatible Saturation 272 Ball Grid Array BGA Package Bit Field Extract Set Clear and ZDP Suffixes 7 2 CMOS Technology oe N 0 13 um 6 Level Copper Metal Process e emory Architecture f 32K Bit 4K Byte L1P Program Cache SSN po Ley Internal m Direct Mapped 3 3 V I O 1 20 V Internal 32K Bit 4K Byte L1D Data Cache 2 Way Set Associative 512K Bit 64K Byte L2 Unified Mapped RAM Cache Flexible Data Program Allocation Device Configuration Boot Mode HPI 8 16 32 Bit ROM Boot Endianness Little Endian Big Endian Enhanced Direct Memory Access EDMA Controller 16 Independent Channels Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet TMS320C67x and C67x are trademarks of Texas Instruments Motorola is a trademark of Motorola Inc All trademarks are the property of their respective owners IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture ai These values are compatible with existing 1 26V designs a M These values are compatible with existing 1 26V designs X5 I 3 EXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 1 PRODUCTION DATA information is current as of publication date Copyright 2005 Texas Instruments Incorporat
49. D 000 010 Cache Enabled 2 Way Cache All other DCC values reserved 1 m GIE Previous GIE global interrupt enable saves the Global Interrupt Enable GIE when an interrupt is taken Allows for proper nesting of interrupts PGIE 0 Previous GIE value is 0 default 1 Previous GIE value is 1 Global interrupt enable bit Enables 1 or disables 0 all interrupts except the reset interrupt and NMI nonmaskable interrupt 0 Disables all interrupts except the reset interrupt and NMI default Enables all interrupts except the reset interrupt and NMI 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 41 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 cache configuration CCFG register description The device includes an enhancement to the cache configuration CCFG register A P bit CCFG 31 allows the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar TC over accesses originating from the L1D memory system An important class of TC accesses is EDMA transfers which move data to or from the L2 memory While the EDMA normally has no issue accessing L2 memory due to the high hit rates on the L1D memory system there are pathological cases where certain CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline when transferring data to a peripheral such
50. DSP Peripherals Overview Reference Guide hereafter referred to as the C6000 PRG Overview literature number SPRUT90 provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents These C6711D peripherals except the PLL are similar to the peripherals on the TMS320C6711 and TMS320C64x devices therefore see the TMS320C6711 C6711 or C67x peripheral information and in some cases where indicated see the TMS320C6711 C6711 or TMS320C67x or C67x peripheral information and in some cases where indicated see the C64x information in the C6000 PRG Overview literature number SPRU190 TMS320C6000 DSP Software Programmable Phase Locked Loop PLL Controller Reference Guide literature number SPRU233 describes the functionality of the PLL peripheral available on the C6711C and C6711D devices The TMSS320C6000 Technical Brief literature number SPRU197 gives an introduction to the TMS320C62x TMS320C67x devices associated development tools and third party support The Migrating from TMS320C6211B 6711B to TMS320C6711C application report literature number SPRA837 describes the differences and issues of interest related to migration from the Texas Instruments TMS320C6211 TMS320C6211B TMS320C6711 and
51. FFICE BOX 1443 HOUSTON TEXAS 77251 1443 interrupt sources and interrupt selector TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 The C67x DSP core on the device supports 16 prioritized interrupts which are listed in Table 20 The highest priority interrupt is INT 00 dedicated to RESET while the lowest priority is INT 15 The first four interrupts are non maskable and fixed The remaining interrupts 4 15 are maskable and default to the interrupt source listed in Table 20 However their interrupt source may be reprogrammed to any one of the sources listed in Table 21 Interrupt Selector Table 21 lists the selector value corresponding to each of the alternate interrupt sources The selector choice for interrupts 4 15 is made by programming the corresponding fields listed in Table 20 in the MUXH address 0x019C0000 and MUXL address 0x019C0004 registers Table 20 DSP Interrupts INTERRUPT DSP DEFAULT SELECTOR SELECTOR IEEE CONTROL VALUE REGISTER BINARY INT 00 INT 01 INT 02 INT 03 INT 04 INT 05 INT 06 INT 07 INT 08 INT 09 INT 10 INT 11 INT 12 INT 13 INT 14 MUXLIA 0 MUXLI9 5 MUXL 14 10 MUXL 20 16 MUXL 25 21 MUXL 30 26 MUXH 4 0 MUXH 9 5 MUXH 14 10 MUXH 20 16 MUXH 25 21 MUXH 30 26 DEFAULT INTERRUPT SELECTOR INTERRUPT EVENT VALUE EVENT BINARY Reserved Reserved
52. GDPA 167 ZDPA 167 PARAMETER 200 250 EN 75 uaweRsELV tme high select EDxivald 17 td EKOH AWEV Delay time ECLKOUT high to AWE valid ns WS 1 tosu EDV AWEL Output setup time ED valid to AWE low 17 ns TRS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold These parameters are programmed via the EMIF CE space control registers ECLKOUT period in ns Select signals include CEx BE 3 0 EA 21 2 and AOE 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 71 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING CONTINUED Setup 2 Strobe 3 Not Ready Hold 2 ECLKOUT NN NT V 1 2 CEx 8 4 2 BE 3 0 BE 1 9 2 EA 21 2 actress X Address X i 3 mamas _ e ED 31 0 _ 1 gp e Read Data ae AOE SDRAS SSOET N 5 lt gt 5 ARE SDCAS SSADST 1 1 1 AWE SDWE SSWET p a gt 1 i gt lt 6 k6 respectively during asynchronous memory accesses Figure 27 Asynchronous Memory Read Timing 35 TEXAS
53. GNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 CPU CSR register description continued Table 18 CPU CSR Register Bit Field Description DESCRIPTION 31 24 CPU ID CPU ID REV ID Read only Identifies which CPU is used and defines the silicon revision of the CPU 310 REXISICMID CPU ID REVISION ID 31 16 are combined for a value of 0x0203 Control power down modes The values are always read as zero 000000 no power down default 15 10 PWRD 001001 PD1 wake up by an enabled interrupt 010001 PD1 wake up by enabled or not enabled interrupt 011010 PD2 wake up by a device reset 011100 PD3 wake up by a device reset Others Reserved Saturate bit Set when any unit performs a saturate This bit can be cleared only by the MVC instruction and can be set only by a functional unit The set by the a functional unit has priority over a clear by the MVC instruction if they occur on the same cycle The saturate bit is set one full cycle one delay slot after a saturate occurs This bit will not be modified by a conditional instruction whose condition is false Endian bit This bit is read only Depicts the device endian mode 0 BigEndian moqe 1 Little Endian mode default Program Cache control mode 7 L1D Level 1 Program Cache 000 010 Cache Enabled Cache accessed and updated on reads All other PCC values reserved SAT EN 5 PCC Data Cache control mode L1D Level 1 Data Cache s
54. GPINT4T GPINT5T GPINTet GPINT7T EDMAINT EMUDTDMA EMURTDXRX EMURTDXTX DSPINT Table 21 Interrupt Selector INTERRUPT RESET NMI SDINT TINTO TINT1 t Interrupt Events GPINT4 GPINT5 GPINT6 and GPINT7 are outputs from the GPIO module GP They originate from the device pins GP 4 EXT_INT4 GP 5 EXT_INT5 GP 6 EXT_INT6 and GP 7 EXT_INT7 These pins can be used as edge sensitive EXT INTx with polarity controlled by the External Interrupt Polarity Register EXTPOL 3 0 The corresponding pins must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register GPEN 7 4 and configuring them as inputs in the GP Direction Register GPDIR 7 4 These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL 3 0 bits For more information on interrupt control via the GPIO module see the 7MS320C6000 DSP General Purpose Input Output GPIO Reference Guide literature number SPRU584 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 43 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 EDMA module and EDMA selector The C67x EDMA for the device also supports up to 16 EDMA channels Four of the sixteen channels channels 8 11 are reserved for EDMA chaining leaving 12 EDMA channels available to service peripheral devices O
55. IEW O O O O O O O O O O O O QO Q Q O Q O O O O O O O P uUOoomTmOoOrcarazzum c z 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 T The ZDP mechanical package designator represents the version of the GDP package with lead free balls For more detailed information see the Mechanical Data section of this document 35 TEXAS INSTRUMENTS 4 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 description The TMS320C67x DSPs including the TMS320C6711 TMS320C6711B TMS320C6711C TMS320C6711D devicest compose the floating point DSP family in the TMS320C6000 DSP platform The C6711 C6711B C6711C and C6711D devices are based on the high performance advanced very long instruction word VLIW architecture developed by Texas Instruments TI making these DSPs an excellent choice for multichannel and multifunction applications With performance of up to 1200 million floating point operations per second MFLOPS at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz
56. ING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 HOST PORT INTERFACE TIMING CONTINUED switching characteristics over recommended operating conditions during host port interface cyclestt see Figure 42 Figure 43 Figure 44 and Figure 45 GDPA 167 ZDPA 167 PARAMETER 200 250 td HCS HRDY Delay time HCS to HRDYS 6 tqHSTBLHRDYH Delay time HSTROBE low to HRDY highfl td HSTBL HDLZ Delay time HSTROBE low to HD low impedance for an HPI read 8 ta HDV HRDYL Delay time HD valid to low 9 toh HSTBH HDV Output hold time HD valid after HSTROBE high ns HSTBH HDHZ Delay time HSTROBE high to HD high impedance ns td HSTBL HDV Delay time HSTROBE low to HD valid 3 125 ns WHSTBHHRDYH Delay time HSTROBE high to HRDY high ns T HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns HCS enables and is always low when HGS is high The case where goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement T This parameter is used during an HPID read At the beginning of the first half word transfer on the falling edge of HSTROBE the HPI sends the request to the EDMA internal address generation hardware and HRDY remains high until the EDMA internal address generation hardware loads th
57. LOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MECHANICAL DATA package thermal resistance characteristics The following tables show the thermal resistance characteristics for the GDP and ZDP mechanical packages thermal resistance characteristics S PBGA package for GDP Air Flow m s t EM T m s meters second thermal resistance characteristics S PBGA package for ZDP a T m s meters per second packaging information The following packaging information and addendum reflect the most current released data available for the designated device s This data is subject to change without notice and without revision of this document 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 1038 X3 TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 14 Nov 2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan 2 Lead Ball Finish MSL Peak Temp Type Drawing Qty TMS320C6711DGDP200 ACTIVE BGA GDP 272 40 TBD SNPB Level 3 220C 168HR TMS320C6711DGDP250 ACTIVE BGA GDP 272 1 TBD SNPB Level 3 220C 168HR TMS320C6711DZDP200 ACTIVE BGA ZDP 272 40 Pb Free SNAGCU Level 3 260C 168HR RoHS TMS32C6711DGDPA167 ACTIVE BGA GDP 272 40 TBD SNPB Level 3 220C 168HR The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the
58. MA Event Selector Registers ESELO ESEL1 and ESEL3 ESELO Register 0x01A0 00 31 30 29 28 27 24 23 22 21 20 19 16 Reserved Reserved 2 R 0 R W 00 00116 R 0 R W 00 00106 15 14 13 12 11 7 6 5 4 0 Reserved EVTSEL1 Reserved EVTSELO R 0 R W 00 0001b R 0 R W 00 0000b Legend R Read only R W Read Write n value after reset ESEL1 Register 0x01A0 FF04 31 30 29 28 27 24 23 22 21 20 19 16 Reserved EVTSEL7 Reserved EVTSEL6 R 0 R W 00 0111b R 0 R W 00 0110b 15 14 13 12 11 a 7 6 5 4 0 Reserved EVTSEL5 Reserved EVTSEL4 R 0 R W 00 01016 R 0 R W 00 0100b Legend R Read only R W Read Write n value after reset ESEL3 Register 0x01A0 FF0C 31 30 29 28 27 24 23 22 21 20 19 16 Reserved EVTSELI5 Reserved EVTSELI4 R 0 R W 00 1111b R 0 R W 00 11100 15 14 13 12111 8 7 6 5 4 3 0 R O R W 00 1101b R 0 R W 00 1100b Legend R Read only R W Read Write n value after reset Table 25 EDMA Event Selection Registers ESELO ESEL1 and ESEL3 Description DESCRIPTION Reserved Reserved Read only writes have no effect EDMA event selection bits for channel x Allows mapping of the EDMA events to the EDMA channels The EVTSELO through EVTSEL15 bits correspond to the channels 0 to 15 respectively These EVTSELx fields are user selectable By configuring the EVTSELx fields to the EDMA selector value EVTSELx of the desired EDM
59. PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Table 15 Device Configurations Pins at Device Reset HD 4 3 HD8 HD12 and CLKMODEO t CONFIGURATION PIN GDP ZDP FUNCTIONAL DESCRIPTION EMIF Big Endian mode correctness EMIFBE 0 The EMIF data will always be presented on the ED 7 0 side of the bus regardless of the endianess mode Little Big Endian 1 In Little Endian mode HD8 1 the 8 bit or 16 bit EMIF data will be present on the ED 7 0 side of the bus HD12t In Big Endian mode HD8 0 the 8 bit or 16 bit EMIF data will be present on the ED 31 24 side of the bus default EMIF Big Endian mode correctness is not supported on the C6711 11B 11C device This new functionality does not affect systems using the current default value of HD12 1 For more detailed information on the big endian mode correctness see the EMIF Big Endian Mode Correctness portion of this data sheet Device Endian mode LEND 0 System operates in Big Endian mode 1 System operates in Little Endian mode default Bootmode Configuration Pins BOOTMODE 00 HPI boot Emulation boot 01 CE1 width 8 bit Asynchronous external ROM boot with default timings default mode HD 4 3 C19 C 10 CE1 width 16 bit Asynchronous external ROM boot with default BOOTMODE t 19 C20 timings 11 width 32 bit Asynchronous external ROM boot with default timings For more detailed information on these bootmode configurations see the bootmod
60. PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 CPU DSP core description The CPU fetches advanced very long instruction words VLIW 256 bits wide to supply up to eight 32 bit instructions to the eight functional units during every clock cycle The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute The first bit of every 32 bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction or whether it should be executed in the following clock as a part of the next execute packet Fetch packets are always 256 bits wide however the execute packets can vary in size The variable length execute packets are a key memory saving feature distinguishing the C67x CPU from other VLIW architectures The CPU features two sets of functional units Each set contains four units and a register file One set contains functional units L1 S1 M1 and D1 the other set contains units D2 M2 S2 and L2 The two register files each contain 16 32 bit registers for a total of 32 general purpose registers The two sets of functional units along with two register files compose sides A and B of the CPU see the functional block and CPU diagram and Figure 1 The four functional units on each side of the CPU can freely share the 16 registers belonging to that side Additionally each side features a single data bus con
61. R 2005 REVISED NOVEMBER 2005 RESET TIMING CONTINUED k Phase 1 gt Phase2 lt Phase 3 CLKIN ECLKIN NV SS S MN N NINY N NI NL NINN LIONS c y Internal Reset Internal SYSCLK1 innn Internal SYSCLK2 2 N ZN ZN NS NI NS NI NS NS Internal SYSCLK3 us puce 72722727272 I 4 gt N A gt 5 M 6 CLKOUT2 N54 M N k 8 gt CLKOUT3 S EMIF Z Groupt ieee 1 gt 10 gt EMIF Low Groupt MENS zaout pe lt 12 Z Group 21 __ lt 14 Boot and Device 13 EE Configuration Pins Y I si n T t EMIF Z group consists of EA 21 2 ED 31 0 CE 3 0 BE 3 0 ARE SDCAS SSADS AWE SDWE SSWE AOE SDRAS SSOE and HOLDA EMIF low group consists of BUSREQ Z group 1 consists of CLKRO CLKR1 CLKX0 CLKX1 FSR0 FSR1 FSX0 FSX1 DX0 DX1 TOUTO and TOUT1 Z group 2 consists of All other HPI and GPIO signals Boot and device configurations consist of HD 8 4 3 Figure 40 Reset Timing Reset Phase 1 The RESET pin is asserted During this time all internal clocks are running at the CLKIN f
62. SDRASSSOEt T N L f ARE SDCAS SSADST 11 k 11 AWE SDWESSWET accesses Figure 35 SDRAM DEAC Command REFR _ __f H 1 1 CEx N BE 3 0 a s 12 ED 31 0 rr r rv 12 12 AOE SDRASSSOE N AS 8 3 8 ARE SDCAS SSADST AWE SDWE SSWET accesses Figure 36 SDRAM REFR Command 3 TEXAS INSTRUMENTS 80 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING CONTINUED MRS n ECLKOUT ULL XN 4 4 5 EN2 2 X 050 X 2 7 ED 31 0 E k 12 k 12 AOE SDRAS SSOET 8 8 ARESDCASSSADS NJ lt 11 4 5 11 AWE SDWE SSWET accesses Figure 37 SDRAM MRS Command 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 81 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 HOLD HOLDA TIMING timing requirements for the HOLD HOLDA cycles see Figure 38 GDPA 167 ZDPA 167 200 250 th HOLDAL HOLDL Hold time HOLD low after HOLDA low ECLKIN period in ns switching characteristics over re
63. T OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING CONTINUED ACTV A f OD fe 1 CEx BE 3 0 rsr lt 4 35 5 EA 231 33 1 1 A Bank Activate XK 4 35 5 11 2 _________________________ _ RowAddress 4 5 EAA2 i a NN U 12 _ 12 AOE SDRAS SSOET N ARE SDCAS SSADST AWE SDWE SSWET accesses Figure 33 SDRAM ACTV Command DCAB 0 4 34 22 27 5 vV O 1 1 BE 3 0 1 O ww r _ EA 21 13 11 2 pruina k 4 5 EA12 w rrrrr ED 31 0 s 12 S S 12 AOE SDRAS SSOET a ARE SDCAS SSADST K 3 11 7 11 AWE SDWE SSWET accesses Figure 34 SDRAM DCAB Command 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 79 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING CONTINUED DEAC ECLKOUT f A NN f A NAA R S VV s 1 CEx BE 3 0 oO 4 k 5 21 13 X Bak X 121 SS y y 4 5 12 ED 31 0 k 12 k 12 AOE
64. XM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX fC WX YS o NON 2 FSX 4 a 7 6 8 4 ke 3 DX _ BittO C Bit n 1 A 2 X n3 X n4 X 4 5 DR Figure 50 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 435 TEXAS INSTRUMENTS 98 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 timing requirements for McBSP as SPI master or slave CLKSTP 11b CLKXP 1T see Figure 51 GDPA 167 ZDPA 167 200 250 MASTER SLAVE tsuDRV CKXH Setup time DR valid before CLKX high th CKXH DRV Hold time DR valid after CLKX high 5 12 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics over recommended operating conditions for McBSP as SPI master or slave CLKSTP 11b CLKXP 11 see Figure 51 GDPA 167 ZDPA 167 200 PARAMETER 250 MASTERS SLAVE th CKXH EXL Hold time FSX low after CLKX high H 2 H 83 td EXL CKXL Delay time FSX low to CLKX low T 2 T 3 C td CKXH DXV Delay time CLKX high to DX valid 6P 2 10 1
65. age represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA MPBG274 MAY 2002 PLASTIC BALL GRID ARRAY GDP 272 A1 Corner gt lt lt 0000000000 0000000000 oooo
66. al purpose input output GPIO module When used as interrupt inputs the GP 7 4 pins must be configured as inputs via the GPDIR register and enabled via the register in addition to enabling the interrupts in the interrupt enable register IER Figure 3 CPU DSP Core and Peripheral Signals 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 17 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 signal groups description continued ED 31 0 CE3 CE2 CE0 TOUT1 TINP1 CLKX1 FSX1 DX1 CLKR1 FSR1 DR1T CLKS1T For proper device operation these pins must be externally pulled up with a 10 kQ resistor 32 20 Memory Map Memory Control Space Select Bus Arbitration Byte Enables EMIF External Memory Interface Timer 1 Timer 0 gt Timers McBSP0 Transmit Transmit McBSPs Multichannel Buffered Serial Ports Figure 4 Peripheral Signals ECLKIN ECLKOUT ARE SDCAS SSADS AOE SDRAS SSOE AWE SDWE SSWE ARDY HOLD HOLDA BUSREQ TOUTO TINPO CLKXO FSX0 DX0 CLKR0 FSR0 DR0 CLKS0 18 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 signal groups description
67. alue after reset Figure 9 GPIO Enable Register GPEN Hex Address 01B0 0000 Figure 10 shows the GPIO direction bits in the GPDIR register This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled set to 1 in the register By default all the GPIO pins are configured as input pins 31 24 23 16 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R W Readable Writeable n value after reset x undefined value after reset Figure 10 GPIO Direction Register GPDIR Hex Address 01B0 0004 For more detailed information on general purpose inputs outputs GPIOs see the TMS320C6000 DSP General Purpose Input Output GPIO Reference Guide literature number SPRU584 Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 53 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 power down mode logic Figure 11 shows the power down mode logic on the device CLKOUT2 Internal Clock Tree Clock Distribution and Dividers Internal Peripherals TMS320C6711D CLKIN RESET T External input clocks with the exception of CLKOUT3 and CLKIN are not gated by the power down mode logic Figure 11 Power Down Mode Log
68. bled default Oscillator Divider 1 Ratio default is 8 0 0111 00000 10000 17 00001 2 10001 18 00010 3 10010 19 00011 4 10011 20 00100 5 10100 21 00101 6 10101 22 00110 IT 10110 23 OSCDIV1 00111 8 10111 24 01000 9 11000 25 01001 11001 26 01010 11 11010 27 01011 A2 11011 28 01100 13 11100 29 01101 14 11101 30 01110 15 11110 31 01111 16 11111 32 435 TEXAS INSTRUMENTS 52 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 general purpose input output GPIO To use the GP 7 4 2 software configurable GPIO pins the GPxEN bits in the GP Enable GPEN Register and the GPxDIR bits in the GP Direction GPDIR Register must be properly configured GPxEN 1 GP x pin is enabled 0 GP x is an input 1 GP x is an output where x represents one of the 7 through 4 or 2 GPIO pins Figure 9 shows the GPIO enable bits in the GPEN register for the device To use any of the GPx pins as general purpose input output functions the corresponding GPxEN bit must be set to 1 enabled Default values are device specific so refer to Figure 9 for the C6711D default configuration 31 24 23 16 R 0 Reserved R W 0 R W 1 R W 1 R W 1 R W 1 R W 0 R W 0 R W 0 R W 0 Legend R W Readable Writeable n value after reset x undefined v
69. characteristics over recommended operating conditions for CLKOUT3TS see Figure 24 GDPA 167 ZDPA 167 PARAMETER 200 250 MN 52 032 09 3 32 09 C32 09 tt CKO3 Transition time CLKOUT3 T The reference points for the rise and fall transitions are measured at VoL MAX and MIN t CLKOUT3 period in ns CLKOUTS period is a divide down of the CPU clock configurable via the OSCDIV1 register For more details see PLL and PLL controller cnn A NS NSN SN SN INS OO 6 6 1 5 5 jew cik Z N NF NOTE A For this example the CLKOUT3 frequency is CLKIN divide by 2 Figure 24 CLKOUT3 Timings 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 69 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS CONTINUED timing requirements for see Figure 25 GDPA 167 ZDPA 167 200 250 MIN MAX Transition time ECLKIN 3 ns T The reference points for the rise and fall transitions are measured at MAX and MIN 1 7 pee 2 ECLKIN FF N k 3 4 gt le Figure 25 ECLKIN Timings switching characteristics over recommended operating conditions for ECLKOUT tS1 see Figure 26 GDPA 167 ZDPA 167 PARAMETER 200 250 6 ta EKIL EKOL Delay time ECLKIN low to ECLKOUT low
70. commended operating conditions for the HOLD HOLDA cyclestt see Figure 38 ZDPA 167 PARAMETER 200 250 td HOLDL EMHZ Delay time HOLD low to EMIF Bus high impedance td EMHZ HOLDAL Delay time EMIF Bus high impedance to HOLDA low td HOLDH EMLZ Delay time HOLD high to EMIF Bus low impedance 2E 7E ns td EMLZ HOLDAH Delay time EMIF Bus low impedance to HOLDA high 0 2E ns ECLKIN period in ns t EMIF Bus consists of CE 3 0 BE 3 0 ED 31 0 21 2 ARE SDCAS SSADS AOE SDRAS SSOE and AWE SDWE SSWE All pending EMIF transactions are allowed to complete before HOLDA is asserted If no bus transactions are occurring then the minimum delay time can be achieved Also bus hold can be indefinitely delayed by setting NOHOLD 1 External Requestor DSP Owns Bus Owns Bus DSP Owns Bus T EMIF Bus consists of CE 3 0 BE 3 0 ED 31 0 EA 21 2 ARE SDCAS SSADS AOE SDRAS SSOE and AWE SDWE SSWE Figure 38 HOLD HOLDA Timing TEXAS INSTRUMENTS 82 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles see Figure 39 ZDPA 167 PARAMETER 200 250 td EKOH BUSRV Delay time ECLKOUT high to BUSREQ valid 1 5 72 ECLKOUT NL 41 BUSREQ ___ 3 lt aum REN F
71. continued gt GP 7 EXT_INT7 GP 6 EXT_INT6 gt 51 5 p GP 4 EXT_INT4 CLKOUT2 GP 2 General Purpose Input Output GPIO Port Figure 4 Peripheral Signals Continued 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS On this device bootmode and certain device configurations peripheral selections are determined at device reset Also other device configurations e g EMIF input clock source are software configurable via the device configurations register DEVCFG address location 0x019C0200 after device reset device configurations at device reset Table 15 describes the C6711D device configuration pins which are set up via internal or external pullup pulldown resistors through the HPI data pins HD 4 3 HD8 HD12 and CLKMODEO pin These configuration pins must be in the desired state until reset is released For proper device operation do not oppose the internal pulldowns pullups in the HD 14 13 11 9 7 1 0 pins with the external pullups pulldowns or by driving them at reset For more details on these device configuration pins see the Terminal Functions table of this data sheet 35 TEXAS INSTRUMENTS 20 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL
72. d from 1 2 respectively to 5 10 respectively then the PLLDIV2 register must be programmed before the PLLDIV1 register The transition ratios become 1 2 1 10 and then 5 10 If the divider ratios of D1 and D2 are to be changed from 3 6 to 1 2 then the PLLDIV1 register must be programmed before the PLLDIV2 register The transition ratios for this case become 8 6 1 6 and then 1 2 The final SYSCLK rate must be exactly half of the SYSCLK1 rate Note that Divider D1 and Divider D2 must always be enabled i e DIEN and D2EN bits are set to 1 in the PLLDIV1 and PLLDIV2 registers The PLL Controller registers should be modified only by the CPU or via emulation The HPI should not be used to directly access the PLL Controller registers For detailed information on the clock generator PLL Controller registers and their associated software bit descriptions see Table 29 through Table 32 48 4 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller continued PLLCSR Register 0x01B7 C100 Reserved 15 12 11 8 7 6 5 4 3 2 1 0 Reserved R 0 R x R 0 RW 1 R W 0 R W 0b RW 0 Legend R Read only R W Read Write n value after reset Table 29 PLL Control Status Register PLLCSR Reserved Read only writes have no effect Oscillator In
73. ded to at least 24 to allow the DSP enough time to access the GPIO register through the CFGBUS switching characteristics over recommended operating conditions for GPIO outputst see Figure 53 GDPA 167 ZDPA 167 PARAMETER 200 250 tw GPOH Pulse duration GPOx high 12P 3 tw GPOL Pulse duration GPOx low 12P 3 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns The number of CFGBUS cycles between two back to back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles therefore the minimum GPOx pulse width is 12 I 2 GPIx GPOx _ Z J 0 N Figure 53 GPIO Port Timing 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 101 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 JTAG TEST PORT TIMING timing requirements for JTAG test port see Figure 54 GDPA 167 ZDPA 167 200 250 tsu TDIV TCKH Setup time TDI TMS TRST valid before high th TCKH TDIV Hold time TDI TMS TRST valid after TCK high switching characteristics over recommended operating conditions for JTAG test port see Figure 54 ZDPA 167 PARAMETER 200 250 K 4 3 5 TDWMSTRST C C X F Figure 54 JTAG Test Port Timing 35 TEXAS INSTRUMENTS 102 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D F
74. device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device Eco Plan The planned eco friendly classification Pb Free RoHS or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tis terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this p
75. driving the pin CLKX1 VO Z Transmit clock 1 Input O Output Z High impedance S Supply voltage GND Ground A Analog signal PLL Filter t IPD Internal pulldown IPU Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 kQ and 2 0 respectively To maintain signal integrity for the EMIF signals serial termination resistors should be inserted into all EMIF output signal lines 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 29 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 1 McBSP1 CONTINUED Receive data On this device this pin does not have an internal pullup IPU For proper device operation DR1 M2 IPU the DR1 pin should either be driven externally at all times or be pulled up with a 10 kQ resis tor to a valid logic level Because it is common for some ICs to 3 state their outputs at times a 10 kQ pullup resistor may be desirable even when an external device is driving the pin MULTICHANNEL BUFFERED SERIAL PORT 0 McBSPO Eu NN GENERAL PURPOSE INPUT OUTPUT GPIO MODULE For this device the CLKOUT2 pin is multiplexed with the GP 2 pin Clock output at half of device speed O Z default SYSCLK2 in
76. e Refer to reset timing for reset timing characteristics and states of device pins during reset The release of the internal reset signal see the Reset Phase 3 discussion in the Reset Timing section of this data sheet starts the processor running with the prescribed device configuration and boot mode The device has three types of boot modes Host boot If host boot is selected upon release of internal reset the CPU is internally stalled while the remainder of the device is released During this period an external host can initialize the CPU s memory space as necessary through the host interface including internal configuration registers such as those that control the EMIF or other peripherals Once the host is finished with all necessary initialization it must set the DSPINT bit in the HPIC register to complete the boot process This transition causes the boot configuration logic to bring the CPU out of the stalled state The CPU then begins execution from address 0 The DSPINT condition is not latched by the CPU because it occurs while the CPU is still internally stalled Also DSPINT brings the CPU out of the stalled state only if the host boot process is selected All memory may be written to and read by the host This allows for the host to verify what it sends to the DSP if required After the CPU is out of the stalled state the CPU needs to clear the DSPINT otherwise no more DSPINTs can be received Emulation boot
77. e configuration register L2 writeback base address register L2 writeback word count register L2 writeback invalidate base address register L2 writeback invalidate word count register L1P invalidate base address register L1P invalidate word count register L1D writeback invalidate base address register L1D writeback invalidate word count register L2 writeback all register L2 writeback invalidate all register Controls CEO range 8000 0000 80FF FFFF Controls CEO range 8100 0000 81FF FFFF Controls CEO range 8200 0000 82FF FFFF Controls CEO range 8300 0000 83FF FFFF Controls CE1 range 9000 0000 90FF FFFF Controls CE1 range 9100 0000 91FF FFFF Controls range 9200 0000 92FF FFFF Controls CE1 range 9300 0000 93FF FFFF Controls CE2 range A000 0000 EFFE Controls CE2 range A100 0000 A1FF FFFF Controls CE2 range A200 0000 A2FF FFFF Controls CE2 range A300 0000 A3FF FFFF Controls range 000 0000 BOFF FFFF Controls range B100 0000 B1FF FFFF Controls CE3 range B200 0000 B2FF FFFF Controls CE3 range B300 0000 B3FF FFFF resenes 4 TEXAS INSTRUMENTS 12 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 peripheral register descriptions continued Table 5 Interrupt Selector Registers ACRONYM COMMENTS C Selects which interrupts drive CPU in
78. e from switching and resulting in the entire chip being 011010 PD2t Wake by a device reset halted All register and internal RAM contents are preserved All functional I O freeze in the last state when the PLL clock is turned off Input clock to the PLL stops generating clocks All register and internal RAM contents are preserved All functional I O freeze in the last state when the PLL clock is turned off Following reset the 011100 Post PLL needs time to re lock just it does following power up Wake up from PD3 takes longer than wake up from PD2 because the PLL needs to be re locked just as it does following power up All others C S S s C C T When entering PD2 and all functional I O remains in the previous state However for peripherals which are asynchronous in nature or peripherals with an external clock source output signals may transition in response to stimulus on the inputs Under these conditions peripherals will not operate according to specifications The device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit in the PLLCSR register With this enhanced functionality come some additional considerations when entering power down modes The power down modes PD2 and PD3 function by disabling the PLL to stop clocks to the device However if the PLL is bypassed PLLEN 0 the device will still receive clocks from the external clock input CLKIN T
79. e requested data into HPID This parameter is used after the second half word of an HPID write or autoincrement read HRDY remains low if the access is not an HPID write or autoincrement read Reading or writing to HPIC or HPIA does not affect the HRDY signal 435 TEXAS INSTRUMENTS 88 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 HOST PORT INTERFACE TIMING CONTINUED HAS m 1 1 2 lt 2 X gt O 5 re od HRW mS w __ P A n V 4 2 1 2 HHWIL lt 3 4 3 HSTROBET 32224727 S CN one se UT HCS 15 4 gt 15 HH 9 gt e mz 9 7 16 9 HD 15 0 output P 5 isthalfword 8 2nd halfword OO p epe met TURBAT k ars HRDY case 1 gt lt 6 gt 8 gt 5 HRDY case 2 A o o o t HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 42 HPI Read Timing HAS Not Used Tied High HAST A Y gt 49 gt 819 10 gt 11 10 4 HCNTL 1 0 amc X X X 11 19 11 R n lt 10 HRW LE 11 r 10 gt k 10 HHWIL
80. e section of this data sheet Clock generator input clock source select 0 Reserved Do not use CLKMODEO 1 CLKIN square wave default For proper device operation this pin must be either left unconnected or externally pulled up with a 1 kQ resistor T All other HD pins or HD 15 13 11 9 7 5 2 0 have pullups pulldowns IPUs or IPDs For proper device operation of the HD 14 13 11 9 7 1 0 do not oppose these pins with external pullups pulldowns at reset however the HD 15 6 5 2 pins can be opposed and driven during reset To ensure a proper logic level during reset when these pins are both routed out and 3 stated or not driven it is recommended an external 10 kQ pullup pulldown resistor be included to sustain the IPU IPD respectively 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 21 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS CONTINUED DEVCFG register description The device configuration register DEVCFG allows the user control of the EMIF input clock source for the device For more detailed information on the DEVCFG register control bits see Table 16 and Table 17 Table 16 Device Configuration Register DEVCFG Address location 0x019C0200 0x019C02FF 31 16 Reservedt RW 0 Lp sels 15 Reservedt EKSRC Reservedt RW 0 R W 0 R W 0 Legend R W Read Write
81. ectively t This value is compatible with existing 1 26V designs 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 7 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 functional block and CPU DSP core diagram SDRAM Digital Signal Processor External SBSRAM 32 Memory L1P Cache SRAM Interface 4K Bytes Total ROM FLASH Devices Timer 0 C6000 CPU DSP Core Instruction Fetch Control 12 Instruction Dispatch Registers utere Memory Control Framing Chips Serial Port 1 4 Banks Instruction Decode Logic H 100 MVIP McBSP1 64K B Enhanced ytes Data Path A Data Path B T SCSA E1 DMA Total est ad Devices Controller A Register File B Register File In Circuit 42 16 channel gt Emulation Serial Port 0 Interrupt BGPA EE Host Port 16 Interface HPI L1D Cache 2 Way Set Associative 4K Bytes Total Interrupt Selector Power Down PLL Logic Boot Configuration T In addition to fixed point instructions these functional units execute floating point instructions t The device has a software configurable PLL with x4 through x25 multiplier and 1 through 32 divider kiz TEXAS INSTRUMENTS 8 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL
82. ed Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Table of Contents revision history eene mr e Rp EMIF big endian mode correctness 60 and ZDP BGA packages bottom view bootmode descriptio DIR ex Rm es OSOl wie tte Deine Qe Heure de E qupd D E maaa device characteristics absolute maximum ratings over operating case ee device compatibility 222 REI rmt Gaede es temperature range 62 functional block and CPU DSP core diagram recommended operating conditions CPU DSP core description electrical characteristics over recommended ranges of _ _ supply voltage and operating case temperature 63 memory map summary peripheral register descriptions parameter measurement information signal transition levels signal groups description M DAL device configurations timing parameters and board routing analysis terminal functions input and output
83. edance 6 ta RSTH CKO2V Delay time RESET high to CLKOUT2 valid td RSTL CKO3L Delay time RESET low to CLKOUTS low 8 td RSTH CKO3V Delay time RESET high to CLKOUTS valid 9 td RSTL EMIFZHZ Delay time RESET low to EMIF Z group high impedancell td RSTL EMIFLIV Delay time RESET low to EMIF low group BUSREQ invalidll td RSTL Z1HZ Delay time RESET low to Z group 1 high impedancell tg RSTL Z2HZ Delay time RESET low to Z group 2 high impedancell 1 CPU clock frequency in ns Note that while internal reset is asserted low the CPU clock SYSCLK1 period is equal to the input clock CLKIN period multiplied by 8 For example if the CLKIN period is 20 ns then the CPU clock SYSCLK1 period is 20 ns x 8 160 ns Therefore P SYSCLK1 160 ns while internal reset is asserted The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used CLKMODEO 1 If the input clock CLKIN is not stable when RESET is deasserted the actual delay time may vary _ EMIF Z group consists of EA 21 2 ED 31 0 CE 3 0 BE 3 0 ARE SDCAS SSADS AWE SDWE SSWE AOE SDRAS SSOE and HOLDA EMIF low group consists of BUSREQ Z group 1 consists of CLKRO CLKR1 CLKX0 CLKX1 FSRO FSR1 FSX0 FSX1 DX0 DX1 TOUTO and TOUT1 Z group 2 consists of All other HPI and GPIO signals 35 TEXAS INSTRUMENTS 84 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBE
84. er Trace impedance 78 Q 167 MHz 16 bit SDRAM 6A 100 MHz For short traces EMIF cannot 167 MHz 16 bit SDRAM 6 meet SDRAM input hold requirement see NOTE 1 143 MHz 32 bit SDRAM 7 83 MHz One bank of one 166 MHz 32 bit SDRAM 6 83 MHz 4 32 Bit SDRAM Loads One bank of one 4 to 7 inches from EMIF 183 MHz 32 bit SDRAM 55 83 MHz Long Traces Bit SBSRAM Trace impedance ada SDRAM data output hold time One bank of buffer 200 MHz 32 bit SDRAM 5 cannot meet EMIF input hold requirement see NOTE 1 NOTE 1 Results are based on IBIS simulations for the given example boards TYPE Timing analysis should be performed to determine if timing requirements can be met for the particular system 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 59 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 EMIF big endian mode correctness The HD8 pin device endian mode LENDIAN selects the endian mode of operation Little or Big Endian For the device Little Endian is the default setting The HD12 pin EMIF Big Endian Mode Correctness EMIFBE enhancement allows the flexibility to change the EMIF data placement on the EMIF bus When using the default setting of HD12 1 the EMIF will present 8 bit and 16 bit data on the ED 7 0 side of the bus if using Little Endian mode HD8 1 and to the ED 31 24 side of the bus if using Big End
85. er or slave CLKSTP 10b CLKXP 0T see Figure 48 GDPA 167 ZDPA 167 200 4 tsu DRV CKXL Setup time DR valid before CLKX low 5 th CKXL DRV Hold time DR valid after CLKX low 4 5 4 12P ns 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 435 TEXAS INSTRUMENTS 94 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED switching characteristics over recommended operating conditions for McBSP as SPI master or slave CLKSTP 10b CLKXP 01 see Figure 48 GDPA 167 ZDPA 167 200 PARAMETER 250 MASTERS SLAVE Hold time FSX low after CLKX low T _ x F td FXL CKXH Delay time FSX low to CLKX L 2 td CKXH DXV Delay time CLKX high to DX valid 6P 2 10 17 Disable time DX high impedance following last data bit from Disable time DX high impedance following last data bit from 3 8 td FXL DXV Delay time FSX low to DX valid 4 2 8 17 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 Sample rate generator input clock 2P if CLKSM 1 P
86. gh impedance Supply voltage GND Ground A Analog signal PLL Filter t IPD Internal pulldown Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respectively TTo maintain signal integrity for the EMIF signals serial termination resistors should be inserted into all EMIF output signal lines P P P R R VO Z IPU External data T T U U U 9 9 8 8 7 6 3 3 2 1 2 3 2 1 3 1 2 1 2 35 TEXAS INSTRUMENTS 28 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued DESCRIPTION DATA CONTINUED l ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 10 2 External data ED EDS ED4 EDS ED2 EDO TIMER 1 Timer 1 or general purpose output m MULTICHANNEL BUFFERED SERIAL PORT 1 McBSP1 External clock source as opposed to internal On the device this pin does not have an internal pulldown IPD For proper device opera CLKS1 E1 tion the CLKS1 pin should either be driven externally at all times or be pulled up with a 10 kO resistor to a valid logic level Because it is common for some ICs to 3 state their outputs at times a 10 kQ pullup resistor may be desirable even when an external device is
87. hardware modules The following products support development of C6000 DSP based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE including Editor C C Assembly Code Generation and Debug plus additional development tools Scalable Real Time Foundation Software DSP BIOS which provides the basic run time target software needed to support any DSP application Hardware Development Tools Extended Development System XDS Emulator supports C6000 DSP multiprocessor system debug EVM Evaluation Module For a complete listing of development support tools for the TMS320C6000 DSP platform visit the Texas Instruments web site on the Worldwide Web at http www ti com uniform resource locator URL For information on pricing and availability contact the nearest TI field sales office or authorized distributor Code Composer Studio DSP BIOS and XDS are trademarks of Texas Instruments 36 4 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 device support device and development support tool nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMS320C6711DGDP250
88. he CPU clock by setting CLKSM CLKGDV 1 FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX switching characteristics over recommended operating conditions for McBSP as SPI master or slave CLKSTP 11b CLKXP 013 see Figure 49 GDPA 167 ZDPA 167 200 PARAMETER 250 MASTERS SLAVE Hold time FSX low after CLKX td EXL CKXH Delay time FSX low to CLKX high T 2 td CKXL DXV Delay time CLKX low to DX valid 6P 2 10P 17 Disable time DX high 6 tdis CKXL DXHZ impedance following last data bit 2 4 6P 3 10P 17 ns from CLKX low 7 td FXL DXV Delay time FSX low to DX valid H 2 H 6 5 4P 2 8P 17 ns 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 S Sample rate generator input clock 2P if CLKSM 1 P 1 CPU clock frequency Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1
89. he low to high transition of TRST must be seen to latch the state of EMU1 and EMUO The EMU 1 0 pins configure the device for either Boundary Scan mode or Emulation mode For more detailed information see the terminal functions section of this data sheet Note The DESIGN WARNING section of the TMS320C6711D BSDL file contains information and constraints regarding proper device operation while in Boundary Scan Mode For more detailed information on the C6711D JTAG emulation see the TMS320C6000 DSP Designing for JTAG Emulation Reference Guide literature number SPRU641 58 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 EMIF device speed The maximum EMIF speed on the device is 100 MHz TI recommends utilizing buffer information specification IBIS to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given board layout To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 For ease of design evaluation Table 34 contains IBIS simulation results showing the maximum EMIF SDRAM interface speeds for the given example boards TYPE and SDRAM speed grades Timing analysis should be performed to verify that all AC timings are met for the specified board
90. herefore bypassing the PLL makes the power down modes PD2 and ineffective sure that the PLL is enabled by writing a 1 to PLLEN bit PLLCSR 0 before writing to either CSR 11 or PD2 CSR 10 to enter a power down mode power supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I O supply However systems should be designed to ensure that neither supply is powered up for extended periods of time gt 1 second if the other supply is below the proper operating voltage system level design considerations System level design considerations such as bus contention may require supply sequencing to be implemented The core supply should be powered up prior to and powered down after the I O buffers This is to ensure that the I O buffers receive valid inputs from the core before the output buffers are powered up thus preventing bus contention with other chips on the board 4 TEXAS INSTRUMENTS 56 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 power supply design considerations A dual power supply with simultaneous sequencing can be used to eliminate the delay between core and I O power up A Schottky diode can also be used to tie the core rail to the I O rail see Figure 13 Supply Schottky Diode Core Supply GND F
91. ian mode Figure 14 shows the mapping of 16 bit and 8 bit devices with EMIF endianness correction EMIF DATA LINES PINS WHERE DATA PRESENT ED 31 24 BE3 ED 23 16 BE2 ED 15 8 BE1 ED 7 0 BEO 32 Bit Device in Any Endianness Mode 16 Bit Device in Big Endianness Mode 16 Bit Device in Little Endianness Mode 8 Bit Device Little Endianness Mode Endianness Mode Figure 14 16 8 Bit EMIF Big Endian Mode Correctness Mapping HD12 1 When HD12 0 enabling EMIF endianness correction the EMIF will present 8 bit and 16 bit data on the ED 7 0 side of the bus regardless of the endianess mode see Figure 15 EMIF DATA LINES PINS WHERE DATA PRESENT ED 31 24 ED 23 16 BE2 ED 15 8 BE1 ED 7 0 BEO 32 Bit Device in Any Endianness Mode Figure 15 16 8 Bit EMIF Big Endian Mode Correctness Mapping HD12 0 This new endianness correction functionality does not affect systems using the default value of HD12 1 This new feature does not affect systems operating in Little Endian mode 35 TEXAS INSTRUMENTS 60 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 bootmode The C67x device resets using the active low signal RESET and the internal reset signal While RESET is low the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset stat
92. ict triggering wake up and effects The power down modes and their wake up methods are programmed by setting the PWRD field bits 15 10 of the control status register CSR The PWRD field of the CSR is shown in Figure 12 and described in Table 33 When writing to the CSR all bits of the PWRD field should be set at the same time Logic 0 should be used when writing to the reserved bit bit 15 of the PWRD field The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 35 TEXAS INSTRUMENTS 54 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 31 16 G lt i 15 14 13 12 11 10 9 8 Enable or Enabled Reserved Non Enabled Interrupt Wake m PD1 Interrupt Wake R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 0 iw F r r Legend R W x Read write reset value NOTE The shadowed bits are not part of the power down logic discussion and therefore are not covered here For information on these other bit fields in the CSR register see the TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 Figure 12 PWRD Field of the CSR Register A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect As best practice NOPs should be padded after the PWRD bits are set in
93. if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit see footnote above Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA 1 in SPCR If DXENA 0 then D1 D2 0 If DXENA 1 then D1 2P D2 4P 435 TEXAS INSTRUMENTS 92 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED 2 5 3 GO 4 7 7 JE 9 le FSX int _ 10 p FSX ext _ FSX XDATDLY 00b ee C lt de13 gt 14 Ft OC 13 K 1 2 e 13 Figure 46 McBSP Timings 3 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 93 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for FSR when GSYNC 1 see Figure 47 GDPA 167 ZDPA 167 200 250 tsu FRH CKSH Setup time FSR high before CLKS high th CKSH FRH Hold time FSR high after CLKS high ciks AX g A _ N N N N FSR external 2 no need to resyn 52 00 7 needs resyn Figure 47 FSR Timing When GSYNC 1 timing requirements for McBSP as SPI mast
94. igure 13 Schottky Diode Diagram Core and I O supply voltage regulators should be located close to the DSP or DSP array to minimize inductance and resistance in the power delivery path Additionally when designing for high performance applications utilizing the C6000 platform of DSPs the PC board should include separate power planes for core I O and ground all bypassed with high quality low ESL ESR capacitors power supply decoupling In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP Assuming 0603 caps the user should be able to fit a total of 60 caps 30 for the core supply and 30 for the I O supply These caps need to be close no more than 1 25 cm maximum distance to the DSP to be effective Physically smaller caps are better such as 0402 but the size needs to be evaluated from a yield manufacturing point of view Parasitic inductance limits the effectiveness of the decoupling capacitors therefore physically smaller capacitors should be used while maintaining the largest available capacitance value As with the selection of any component verification of capacitor availability over the product s production lifetime needs to be considered 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 57 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 IEEE 1149 1 JTAG compatib
95. igure 39 BUSREQ Timing Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 83 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 RESET TIMING timing requirements for resettt see Figure 40 GDPA 167 ZDPA 167 tw RST Pulse duration RESET tsu HD Setup time HD boot configuration bits valid before RESET highS th HD Hold time HD boot configuration bits valid after RESET high TP 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t The PLL is bypassed immediately after the device comes out of reset The PLL Controller can be programmed to change the PLL mode in software For more detailed information on the PLL Controller see the TMS320C6000 DSP Software Programmable Phase Lock Loop PLL Controller Reference Guide literature number SPRU233 The Boot and device configurations bits are latched asynchronously when RESET is transitioning high The Boot and device configurations bits consist of HD 8 4 3 switching characteristics over recommended operating conditions during reset l see Figure 40 GDPA 167 ZDPA 167 PARAMETER 200 Delay time external RESET high to internal reset C Ia RSTH ZV high and all signal groups valid l LKMODE0 1 tg RSTL ECKOL Delay time RESET low to ECLKOUT high impedance td RSTH ECKOV Delay time RESET high to ECLKOUT valid tg RSTL CKO2IV Delay time RESET low to CLKOUT2 high imp
96. ility statement TMS320C6711D DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized While RESET initializes the DSP core TRST initializes the DSP s emulation logic Both resets are required for proper operation Note TRST is synchronous and must be clocked by TCLK otherwise BSCAN may not respond as expected after TRST is asserted While both TRST and RESET need to be asserted upon power up only RESET needs to be released for the DSP to boot properly TRST may be asserted indefinitely for normal operation keeping the JTAG port interface and DSP s emulation logic in the reset state TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP s boundary scan functionality The TMS320C6711D DSP includes an internal pulldown IPD on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP s internal emulation logic will always be properly initialized when this pin is not routed out JTAG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST When using this type of JTAG controller assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations Following the release of RESET t
97. iming references of that signal are also inverted P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns The minimum CLKR X period is twice the CPU cycle time 2P and not faster than 75 Mbps 13 3 ns This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167 MHz and 200 MHz CPU clocks or 50 Mbps for 100 MHz CPU clock where the McBSP is either the master or the slave Care must be taken to ensure that the AC timings specified in this data sheet are met The maximum bit rate for McBSP to McBSP communications is 67 Mbps therefore the minimum CLKR X clock cycle is either twice the CPU cycle time 2P or 15 ns 67 MHz whichever value is larger For example when running parts at 167 MHz P 6 ns use 15 ns as the minimum CLKR X clock cycle by setting the appropriate CLKGDV ratio or external clock source When running parts at 60 MHz P 16 67 ns use 2P 33 ns 30 MHz as the minimum CLKR X clock cycle The maximum bit rate for McBSP to McBSP communications applies when the serial port is a master of the clock and frame syncs with CLKR connected to CLKX FSR connected to FSX CLKXM FSXM 1 and CLKRM FSRM 0 in data delay 1 or 2 mode R XDATDLY 01b or 10b and the other device the McBSP communicates to is a slave This parameter applies to the maximum McBSP frequency Operate serial clocks CLKR X in the reasonable range of 40 60 duty cycle
98. ively To ensure a proper logic level during reset when these pins are both routed out and 3 stated or not driven it is recommended an external 10 kQ pullup pulldown resistor be included to sustain the IPU IPD respectively TEXAS INSTRUMENTS 24 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME DESCRIPTION For Emulation and normal operation no external pullup pulldown resistors are necessary How ever for the Boundary Scan operation pull down the EMU1 and EMUO pins with a dedicated 1 kQ resistor Emulation 1 0 pins e Select the device functional mode of operation EMUf 1 0 Operation 00 Boundary Scan Functional Mode see Note 01 Reserved 10 Reserved IPU 11 Emulation Functional Mode default see the IEEE 1149 1 JTAG Compatibility Statement section of this data sheet The DSP can be placed in Functional mode when the EMU 1 0 pins are configured for either Boundary Scan or Emulation Note When the EMU 1 0 pins are configured for Boundary Scan mode the internal pulldown IPD on the TRST signal must not be opposed in order to operate in Functional mode For the Boundary Scan mode drive EMU 1 0 and RESET pins low RESETS AND INTERRUPTS Device reset When using Boundary Scan mode on the device drive the EMU 1 0 and RESET pins low This pin doe
99. layout Other configurations are also possible but again timing analysis must be done to verify proper AC timings To maintain signal integrity serial termination resistors should be inserted into all EMIF output signal lines see the Terminal Functions table for the EMIF output signals Table 34 Example Boards and Maximum EMIF Speed MAXIMUM ACHIEVABLE EMIF INTERFACE SDRAM SPEED GRADE EMIF SDRAM COMPONENTS INTERFACE SPEED 143 MHz 32 bit SDRAM 7 100 MHz 1 to 3 inch traces with proper 166 MHz 32 bit SDRAM 6 For short traces SDRAM data 1 Load One bank of one termination resistors output hold time these Short Traces 32 Bit SDRAM TIE 183 MHz 32 bit SDRAM 55 SDRAM speed grades cannot Trace impedance 50 Q meet EMIF input hold time 200 MHz 32 bit SDRAM 5 requirement see NOTE 1 125 MHz 16 bit SDRAM 8E 100 MHz 1 2 to 3 inches from EMIF to 133 MHz 16 bit SDRAM 75 100 MHz 7 6 Short Traces 16 Bit SDRAMs termination resistors 143 MHAIS BI SDRAM 7E 1000077 Trace impedance 78 Q 167 MHz 16 bit SDRAM 6A 100 MHz 167 MHz 16 bit SDRAM 6 100 MHz For short traces EMIF cannot 125 MHz 16 bit SDRAM 8E meet SDRAM input hold requirement see NOTE 1 One banker we 1 2 io to 133 MHz 16 bit SDRAM 75 100 MHz 32 Bit SDRAMs 1 0 143 MHz 16 bit SDRAM 7E 100 MHz Short Traces One bank or buff termination resistors od
100. m the data sheet timings Input requirements in this data sheet are tested with an input slew rate of 4 Volts per nanosecond 4 V ns at the device pin Figure 16 Test Load Circuit for AC Timing Measurements signal transition levels All input and output timing parameters are referenced to 1 5 V for both 0 and 1 logic levels Vref 1 5 V Figure 17 Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to MAX and MIN for input clocks and VoL MAX and Vox MIN for output clocks Vref MIN MIN Vref MAX or VoL MAX Figure 18 Rise and Fall Transition Time Voltage Reference Levels TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION CONTINUED AC transient rise fall time specifications Figure 19 and Figure 20 show the AC transient specifications for Rise and Fall Time For device specific information on these values refer to the Recommended Operating Conditions section of this Data Sheet t 0 3 te max t Vos Ke Risetime Vin min Waveform Valid Region Ground Figure 19 AC Transient Specification Rise Time Ttc the peripheral cycle time t 0 3 te max t ma
101. m bypass to the PLL path see Table 26 and Figure 8 Under some operating conditions the maximum PLL Lock Time may vary from the specified typical value For the PLL Lock Time values see Table 26 Table 26 PLL Lock and Reset Times PLL Lock Time 75 1875 PLL Reset Time 125 ns Table 27 shows the device s CLKOUT signals how they are derived and by what register control bits and the default settings For more details on the PLL see the PLL and Clock Generator Logic diagram Figure 8 Table 27 CLKOUT Signals Default Settings and Control CLOCK OUTPUT DEFAULT SETTING CONTROL SIGNAL NAME ENABLED or DISABLED BIT s Register D2EN 1 PLLDIV2 15 C CLKOUT2 ON ENABLED 2 1 EMIF GBLCTL 3 SYSCLK2 selected default CLKOUT3 ON ENABLED OD1EN 1 OSCDIV1 15 Derived from CLKIN SYSCLK3 selected default DESCRIPTION ON ENABLED EKSRC 0 DEVCFG 4 derived from SYSCLK3 1 EMIF GBLCTL 5 To select ECLKIN as source EKSRC 1 DEVCFG 4 and 1 EMIF GBLCTL 5 ECLKOUT This input clock is directly available as an internal high frequency clock source that may be divided down by a programmable divider OSCDIV1 1 2 8 32 and output on the CLKOUTS pin for other use in the system Figure 8 shows that the input clock source may be divided down by divider PLLDIVO 1 2 32 and then multiplied up by a factor of x4 x5 x6 and so on up to x25 Either
102. n the device the user through the EDMA selector registers can control the EDMA channels servicing peripheral devices The EDMA selector registers are located at addresses 0x01AO0FF00 ESELO 0x01AO0FF04 ESEL1 and 0x01A0FFOC ESEL3 These EDMA selector registers control the mapping of the events to the EDMA channels Each EDMA event has an assigned EDMA selector code see Table 23 By loading each EVTSELx register field with an EDMA selector code users can map any desired EDMA event to any specified EDMA channel Table 22 lists the default EDMA selector value for each EDMA channel See Table 24 and Table 25 for the EDMA Event Selector registers and their associated bit descriptions Table 22 EDMA Channels Table 23 EDMA Selector EDMA DEFAULT EDMA SELECTOR SELECTOR CHANNEL CONTROL VALUE EVENT c ODE MODULE REGISTER BINARY o ommo s DEFAULT EDMA 7 ESEL1 29 24 000111 NT7 000111 GPINT7T GPIO TCC8 Chaining 001000 Reserved 9 Chaining 001001 Reserved NES E pe t The GPINT 4 7 interrupt events are sourced from the GPIO module via the external interrupt capable GP 4 7 pins 435 TEXAS INSTRUMENTS 44 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 EDMA module and EDMA selector continued Table 24 ED
103. nected to all the registers on the other side by which the two sets of functional units can access data from the register files on the opposite side While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle register access using the register file across the CPU supports one read and one write per cycle The C67x CPU executes all C62x instructions In addition to C62x fixed point instructions the six out of eight functional units L1 S1 M1 M2 S2 and L2 also execute floating point instructions The remaining two functional units D1 and D2 also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle Another key feature of the C67x CPU is the load store architecture where all instructions operate on registers as opposed to data in memory Two sets of data addressing units D1 and D2 are responsible for all data transfers between the register files and the memory The data address driven by the D units allows data addresses generated from one register file to be used to load or store data to or from the other register file The C67x CPU supports a variety of indirect addressing modes using either linear or circular addressing modes with 5 or 15 bit offsets All instructions are conditional and most can access any one of the 32 registers Some registers however are singled out to support specific addressing
104. nstructions every clock cycle While most results are stored in 32 bit registers they can be subsequently moved to memory as bytes or half words as well All load and store instructions are byte half word or word addressable 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 9 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 CPU DSP core description continued LD1 32 MSB ST1 Register File Data Path A0 A15 LD1 32 LSB DA1 gt lt DA2 LD2 32 LSB Register File B Data Path B BO B15 LD2 32 MSB ST2 lt gt Control Register File addition to fixed point instructions these functional units execute floating point instructions Figure 1 TMS320C67x CPU DSP Core Data Paths 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 memory map summary Table 2 shows the memory map address ranges of the device Internal memory is always located at address 0 and can be used as both program and data memory The configuration registers for the common peripherals are located at the same hex address ranges The external memory address ranges in the device begin at the addre
105. ock speeds with a C6211BGFNA extended temperature device that also runs at 150 MHz while the C6711 C6711B device runs at 150 and 100 MHz with a C6711BGFNA extended temperature device that also runs at 100 MHz and the C6711C and C6711D devices run at 200 clock speed with a C6711CGDPA and C6711DGDPA extended temperature devices that also run at 167 MHz The C6211 C6211B C6711 100 and C6711B devices have a core voltage of 1 8 V the C6711 150 device core voltage is 1 9 V and the C6711C and C6711D devices operate with a core voltage of 1 201 V There are several enhancements and features that are only available on the C6711C and C6711D devices such as the CLKOUTS signal a software programmable PLL and PLL Controller and a GPIO peripheral module The C6711D device also has additional enhancements such as EMIF Big Endian mode correctness EMIFBE and the L1D requestor priority to L2 bit P bit in the cache configuration CCFG register For more detailed discussion on the migration of a C6211 C6211B C6711 C6711B device to a TMS320C6711C device see the Migrating from TMS320C6211B 6711B to TMS320C6711C application report literature number SPRA837 For a more detailed discussion on the similarities differences between the C6211 and C6711 devices see the How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the TMS320C6711 DSP application reports literature number SPRA474 and SPRA522 resp
106. ower supply decoupling portion of this data sheet T3 Us ws Wo W12 Yi 4 A9 1 4 V supply voltage 250 1 20 V supply voltage See Note see the power supply decoupling portion of this data sheet Note This value is compatible with existing 1 26 V designs 1 Input O Output Z High impedance Supply voltage GND Ground A Analog signal PLL Filter 435 TEXAS INSTRUMENTS 32 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME GDP ZDP D11 D14 D15 DESCRIPTION 1 4 V supply voltage 250 1 20 V supply voltage See Note CVpp see the power supply decoupling portion of this data sheet F17 K17 L17 R17 U10 U11 CIG oje S lt Note This value is compatible with existing 1 26 designs o GROUND PINS A11 A A19 A GND Ground pins B15 B 1 Input O Output Z High impedance Supply voltage GND Ground Analog signal PLL Filter 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 33 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME GROUND PINS CONTINUED DESCRIPTION j E A EC gt
107. perty right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti
108. put Stable This bit indicates if the OSCIN CLKIN input has stabilized STABLE 0 OSCIN CLKIN input not yet stable Oscillator counter is not finished counting default 1 OSCIN CLKIN input stable Reserved Reserved Read only writes have no effect Asserts RESET to PLL PLLRST 0 PLL Reset Released 1 PLL Reset Asserted default Reserved Reserved The user must write a 0 to this bit Select PLL Power Down PLLPWRDN 0 PLL Operational default 1 PLL Placed Power Down State PLL Mode Enable 0 Bypass Mode default PLL disabled Divider DO and PLL are bypassed SYSCLK1 SYSCLK2 SYSCLKG3 are divided down directly from input reference clock PLL Enabled Divider DO and PLL are not bypassed SYSCLK1 SYSCLK2 SYSCLK3 are divided down from PLL output Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 49 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller continued PLLM Register 0x01B7 C110 15 12 11 8 7 6 5 4 3 2 1 0 Reserved PLLM R 0 R W 0 0111 Legend R Read only R W Read Write n value after reset Table 30 PLL Multiplier Control Register PLLM PLL multiply mode default is x7 0 0111 00000 Reserved 1000 x16 00001 Reserved 10001 x17 00010 Reserved 10010 x18 00011 Reserved 10011 x19 00100 x4 10100 x20 00101 x5 10101 x21 00110 x6
109. r Sat Prescaler 1 2 13 132 Generator Options Multiplier x4 x5 x6 x25 Postscaler 1 2 132 272 Pin BGA BGA Package 27 x 27 mm GDP and ZDP Product Status Product Preview PP ppt Advance Information Al Production Data PD t These values are compatible with existing 1 26 designs t PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters The ZDP package devices are supported in the same speed grades as the GDP package devices available upon request On Chip Memory C6000 is a trademark of Texas Instruments TEXAS INSTRUMENTS 6 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 device compatibility The TMS320C6211 C6211B and C6711 C6711B devices are pin compatible and have the same peripheral set thus making new system designs easier and providing faster time to market The following list summarizes the device characteristic differences among the C6211 C6211B C6711 C6711B C6711C and C6711D devices The C6211 and C6211B devices have a fixed point C62x CPU while the C6711 C6711B C6711C and C6711D devices have a floating point C67x CPU The C6211 C6211B device runs at 167 and 150 MHz cl
110. rementing 4 word bursts but random bursts and decrementing bursts are done by interrupting bursts in progress All burst types can sustain continuous data flow accesses TEXAS INSTRUMENTS 76 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 READ O A A A A A A 1 1 2 k 3 0 X BE BE X BE4 4 gt 5 21 13 X Bank X 4 5 1 2 XX Column XT 4 kot 5 EA12 7 Awww amsa 6 7 ED 31 0 AOE SDRAS SSOET 8 L 8 ARE SDCAS SSADST N U U U UU 1 AWE SDWE SSWEt accesses Figure 31 SDRAM Read Command CAS Latency 3 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 77 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING CONTINUED WRITE ECLKoUT of f NA FN f Df U UA LU __ FERRI 1 0422 7 1 2 k 4 k 3 0 4 k 5 ZARE X Bak 0 4 5 EA 11 2 424 4 E 5 mo 10 ED 31 0 AOE SDRAS SSOET n L 8 9 0 8 ARE SDCAS SSADSt gt gt 11 11 accesses Figure 32 SDRAM Write Command 35 TEXAS INSTRUMENTS 78 POS
111. requency divide by 8 The CPU is also running at the CLKIN frequency divide by 8 Reset Phase 2 The RESET pin is deasserted but the internal reset is stretched During this time all internal clocks are running at the CLKIN frequency divide by 8 The CPU is also running at the CLKIN frequency divide by 8 Reset Phase 3 Both the RESET pin and internal reset are deasserted During this time all internal clocks are running at their default divide down frequency of CLKIN The CPU clock SYSCLK1 is running at CLKIN frequency The peripheral clock SYSCLK2 is running at CLKIN frequency divide by 2 The EMIF internal clock source SYSCLK3 is running at CLKIN frequency divide by 2 SYSCLK3 is reflected on the ECLKOUT pin when EKSRC bit 0 default CLKOUTS is running at CLKIN frequency divide by 8 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 85 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 EXTERNAL INTERRUPT TIMING timing requirements for external interruptst see Figure 41 GDPA 167 ZDPA 167 200 Width of the interrupt pulse low Width of the EXT_INT interrupt pulse low 2 Width of the EXT_INT interrupt pulse high ns TP 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns 2 r N x Figure 41 External NMI Interrupt Timing 435 TEXAS INSTRUMENTS
112. s L1 Program Memory 256 bits cycle L2 EMIF EDMA 50 writes 50 reads to from SDRAM 50 bit switching McBSP 2 channels at E1 rate Timers 2 timers at maximum rate IDD2V Core supply currentt Low DSP Activity Model CPU 2 instructions cycle with 1 LDH instruction L1 Data Memory 16 bits cycle L1 Program Memory 256 bits per 4 cycles L2 EMIF EDMA None McBSP 2 channels at E1 rate Timers 2 timers at maximum rate The actual current draw is highly application dependent For more details on core and I O activity refer to the TMS320C6711D 12D 13B Power Consumption Summary application report literature number SPRA889A 435 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 63 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION Tester Pin Electronics Data Sheet Timing Reference Point 420 3 5 nH Output MUN Under T 20 500 din see note Device Pin T 4 0 pF T 1 85 pF see note NOTE The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect The transmission line is intended as a load only It is not necessary to add or subtract the transmission line delay 2 ns or longer fro
113. s D1 and D2 must never be disabled Never write a 0 to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers NOTES A Place all PLL external components C1 C2 and the EMI Filter as close to the C67x DSP device as possible For the best performance TI recommends that all the PLL external components be on a single side of the board without jumpers switches or components other than the ones shown B For reduced PLL jitter maximize the spacing between switching signals and the PLL external components C1 C2 and the EMI Filter C The 3 3 V supply for the EMI filter must be from the same 3 3 V power plane supplying the I O voltage DVpp D EMI filter manufacturer TDK part number ACF451832 333 223 153 103 Panasonic part number EXCCET103U Figure 8 PLL and Clock Generator Logic 46 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller continued The PLL Reset Time is the amount of wait time needed when resetting the PLL writing PLLRST 1 in order for the PLL to properly reset before bringing the PLL out of reset writing PLLRST 0 For the PLL Reset Time value see Table 26 The PLL Lock Time is the amount of time from when PLLRST 0 with PLLEN 0 PLL out of reset but still bypassed to when the PLLEN bit can be safely changed to 1 switching fro
114. s for Event 0 15 Reload link parameters for Event 0 15 Scratch pad area 2 words 01A0 07E0 0180 07F7 01A0 07F8 01A0 07FF t The device has 85 EDMA parameters total 16 Event Reload parameters and 69 Reload only parameters Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 13 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 peripheral register descriptions continued For more details on the EDMA parameter RAM 6 word parameter entry structure see Figure 2 31 0 EDMA Parameter Word 0 EDMA Channel Options Parameter OPT OPT Word 1 SRC Word 2 Array Frame Count FRMCNT Element Count ELECNT CNT Word 3 EDMA Channel Destination Address DST DST Word 4 Word 5 Element Count Reload ELERLD Link Address LINK RLD Figure 2 EDMA Channel Parameter Entries 6 Words for Each EDMA Event Table 8 EDMA Registers REGISTER NAME DEA MM E Table 9 Quick DMA QDMA and Pseudo Registerst REGISTER NAME sd QDMA pseudo destination address register QDMA pseudo index register T All the QDMA and Pseudo registers are write accessible only 4 6 INSTRUMENTS 14 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 peripheral register descriptions continued Table 10 PLL Controller Registers
115. s not have an IPU on this device Nonmaskable interrupt e Edge driven rising edge Any noise on the NMI pin may trigger an NMI interrupt therefore if the NMI pin is not used it is recommended that the NMI pin be grounded versus relying on the IPD General purpose input output pins 1 2 which also function as external interrupts Edge driven e Polarity independently selected via the External Interrupt Polarity Register bits EXTPOL 3 0 in addition to the GPIO registers ti Input O Output Z High impedance S Supply voltage GND Ground A Analog signal PLL Filter t IPD Internal pulldown IPU Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respectively 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 25 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL Fd NAME GDP ZDP HHWIL H20 Host half word select first or second half word not necessarily high or low order HR W Host read or write select HD15 Host port data Used for transfer of data address and control Also controls initialization of DSP modes at reset via pullup pulldown resistors Device Endian mode HD8 0 Big Endian 1 Little Endian DESCRIPTION B14 0149 HD13 HD12 EMIF Big
116. ss location 0x8000 0000 Table 2 TMS320C6711D Memory Map Summary External Memory Interface EMIF Registers K K C000 0000 FFFF FFF t The number of EMIF address pins EA 21 2 limits the maximum addressable memory SDRAM to 128MB per CE space To get 256MB of addressable memory additional general purpose output pin or external logic is required QDMA Registers 0200 0000 0200 0033 EDMA RAM and EDMA Registers 256K 01A0 0000 01A3 FFFF 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 11 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 peripheral register descriptions Table 3 through Table 14 identify the peripheral registers for the device by their register names acronyms and hex address or hex address range For more detailed information on the register contents bit names and their descriptions see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide literature number SPRU190 Table 3 EMIF Registers REGISTER NAME 0180 0000 GBLCTL EMIF global control 0180 0004 CECTL1 EMIF CE1 space control 0180 0008 CECTLO EMIF CEO space control C Reseed EMIF CE2 space control EMIF space control EMIF SDRAM contol EMIF SDRAM refresh control EMIF SDRAM extension 01800024 0183FFFF Reserved Table 4 L2 Cache Registers REGISTER NAME Cach
117. ternal signal from the clock generator or this pin be programmed as GP 2 1 0 2 12 VO Z GP 2 When the CLKOUT2 pin is enabled the CLK2EN bit in the EMIF global control register GBLCTL controls the CLKOUT2 pin All devices CLK2EN 0 CLKOUT 2 is disabled CLK2EN 1 CLKOUT 2 enabled to clock default GP 7 EXT_INT7 General purpose input output pins 1 0 2 which also function as external GP 6 EXT_INT6 D2 interrupts ee VO Z IPU e Edge driven GRIBIEXT INT e Polarity independently selected via the External Interrupt Polarity Register GP 4 EXT_INT4 bits EXTPOL 3 0 in addition to the GPIO registers 1 Input O Output Z High impedance Supply voltage GND Ground A Analog signal PLL Filter t IPD Internal pulldown IPU Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respectively TEXAS INSTRUMENTS 30 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 Terminal Functions Continued SIGNAL NAME RESERVED FOR TEST RSV C12 IPU Reserved leave unconnected do not connect to power or ground DESCRIPTION On this device this pin does not have an IPU On this device this pin does not have an IPU For proper device operation the D12 pin must D12 IPU
118. terrupts 10 15 019C 0000 MUXH Interrupt multiplexer high INT10 INT15 019C 0004 MUXL Interrupt multiplexer low drive CPU interrupts 4 9 019C 0008 EXTPOL External interrupt polarity Table 6 Device Registers REGISTER DESCRIPTION This register allows the user control of the EMIF input ice clock source For detailed information the 019 0200 DEVCFG Device Configuration device configuration register see the Device Configurations section of this data sheet Identifies which defines the silicon revision of the CPU This register also offers the user control of device operation CSR CPU Control Status Register For more detailed information on the CPU Control Status Register see the CPU CSR Register Description section of this data sheet Table 7 EDMA Parameter RAMT REGISTER NAME Parameters for Event 9 6 words or Reload Link Parameters for other Event Parameters for Event 10 6 words Reload Link Parameters for other Event 01A0 0150 01A0 0167 Parameters for Event 14 6 words or Reload Link Parameters for other Event 01A0 0168 01A0 017F Parameters for Event 15 6 words or Reload Link Parameters for other Event 01A0 0180 01A0 0197 Reload link parameters for Event 0 15 01A0 0198 01A0 01AF a Reload link parameter
119. the input clock PLLEN 0 or the PLL output PLLEN 1 then serves as the high frequency reference clock for the rest of the DSP system The DSP core clock the peripheral bus clock and the EMIF clock may be divided down from this high frequency clock each with a unique divider For example with a 40 MHz input if the PLL output is configured for 400 MHz the DSP core may be operated at 200 MHz 2 while the EMIF may be configured to operate at a rate of 75 MHz 6 Note that there is a specific minimum and maximum reference clock PLLREF and output clock PLLOUT for the block labeled PLL in Figure 8 as well as for the DSP core peripheral bus and EMIF The clock generator must not be configured to exceed any of these constraints certain combinations of external clock input internal dividers and PLL multiply ratios might not be supported See Table 28 for the PLL clocks input and output frequency ranges 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 47 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PLL and PLL controller continued Table 28 PLL Clock Frequency Rangestt GDPA 167 ZDPA 167 CLOCK SIGNAL GDP 200 ZDP 200 T SYSCLK rate must be exactly half of SYSCLK1 t Also see the electrical specification timing requirements and switching characteristics parameters in the Input and Output Clocks section of this data sheet The
120. tput at half of device speed O Z default SYSCLK2 internal signal from the clock generator or this pin can be programmed as GP 2 1 2 Y12 O Z GPO 2 When the CLKOUT2 pin is enabled the CLK2EN bit in the EMIF global control register GBLCTL controls the CLKOUT2 pin All devices CLK2EN 0 CLKOUT 2 is disabled CLK2EN 1 2 enabled to clock default CLKOUT3 o Clock output programmable by OSCDIV1 register in the PLL controller Clock generator input clock source select 0 Reserved Do not use CLKMODEO C4 IPU 1 CLKIN square wave default For proper device operation this pin must be either left unconnected or externally pulled up with a 1 kQ resistor PLLHV _ Analog power 3 3 V for PLL JTAG EMULATION T 02 DI CK TRSTS E JTAG test port reset For IEEE 1149 1 JTAG compatibility see the EEE 1149 1 JTAG Compatibility Statement section of this data sheet EMU5 VO Z Emulation pin 5 Reserved for future use leave unconnected EMU4 VO Z Emulation pin 4 Reserved for future use leave unconnected EMU3 VO Z Emulation pin 3 Reserved for future use leave unconnected 11 Input O Output Z High impedance S Supply voltage GND Ground A Analog signal PLL Filter t IPD Internal pulldown Internal pullup To oppose the supply rail on these IPD IPU signal pins use external pullup or pulldown resistors no greater than 4 4 and 2 0 respect
121. ts are done by interrupting bursts in progress All burst types can sustain continuous data flow switching characteristics over recommended operating conditions for synchronous burst SRAM cyclest see Figure 29 and Figure 30 ZDPA 167 NO PARAMETER 200 UNIT 250 td EKOH CEV Delay time ECLKOUT high to CEx valid 12 1 7 ns td EKOH EAIV Delay time ECLKOUT high to EAx invalid T The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM Accesses default to incrementing 4 word bursts but random bursts and decrementing bursts are done by interrupting bursts in progress All burst types can sustain continuous data flow accesses TEXAS INSTRUMENTS 74 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 SYNCHRONOUS BURST MEMORY TIMING CONTINUED ECcLKOUT N A A A A A VL 1 1 5 r A EA 21 2 XE X ED 31 0 Q02 X G3 X Q 8 Kex 8 ARE SDCAS SSADST TUUM SS 9 9 AOE SDRAS SSOET O U Op _ AWE SDWE SSWET accesses Figure 29 SBSRAM Read Timing EcLKOUT XA A A AN NSS CEx BE 3 0 EA 21 2 ED 31 0 ARE SDCAS SSADST AOE SDRAS SSOET AWE SDWE SSWET accesses Figure 30 SBSRAM Write Timing
122. x Vus max Ground Figure 20 AC Transient Specification Fall Time Ttc the peripheral cycle time Wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 65 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION CONTINUED timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings As a good board design practice such delays must always be taken into account Timing values may be adjusted by increasing decreasing such delays TI recommends utilizing the available buffer information specification IBIS models to analyze the timing characteristics correctly To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 If needed external logic hardware such as buffers may be used to compensate any timing differences For inputs timing is most impacted by the round trip propagation delay from the DSP to the external device and from the external device to the DSP This round trip delay tends to negatively impact the input setup time margin but also tends to improve the input hold time margins see Table 35 and Figure 21 Figure 21 represents a general transfer between the DSP and an external device The figure also represents
123. y programming and scheduling and a Windows debugger interface for visibility into source code execution TMS320C6000 is a trademark of Texas Instruments Windows is a registered trademark of the Microsoft Corporation t Throughout the remainder of this document the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 5 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A OCTOBER 2005 REVISED NOVEMBER 2005 device characteristics Table 1 provides an overview of the C6711D DSP The table shows significant features of the device including the capacity of on chip RAM the peripherals the execution time and the package type with pin count For more details on the C6000 DSP device part numbers and part numbering see Figure 5 Table 1 Characteristics of the C6711D Processor INTERNAL CLOCK C6711D SOURCE FLOATING POINT DSP EWIE ECLKIN SYSCLK3 or ECLKIN HARDWARE FEATURES E GPIO Module SYSCLK2 Sie yes 4K Byte 4KB L1 Program L1P Cache Organization 4KB L1 Data L1D Cache 64KB Unified Mapped RAM Cache L2 en E ID Control Status Register CSR 31 16 0x0203 4 ns C6711DGDP 250 5 ns C6711DGDP 200 Cycle Time ns and C6711DZDP 200 6 ns C6711DGDPA 167 and C6711DZDPA 167 1 201 V Voltage SIS 1 4 250 000 PLL Options CLKIN frequency multiplie

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