Delta Tau PMAC MINI PCI Reference Manual
Contents
1. TRANSFERRED FOR ANY REASON THIS DOCUMENT IS TO BE USED 5V Luna vccaL 3P3V ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS 2 OF DELTA TAU DATA SYSTEMS INC ALL RIGHTS TO DESIGNS AND NOTEI IN our BA 1 INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC S POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE z RESET x ABOVE AGREEMENT o PINIT TNETLIST CHANGE z Se porem ib MODDIRAD t K K MODC IRQC teg 3P3V MODB IROB TANT TANT NOTE2 90 R11 R12 MODA IRQA 76 56309 PH80 DE cz cs calcio len Les fca _ cra Tour 3116c150 TA Ger e ur J r Mr Hr pur Pie pur ie c al ca n GND NOTE2 GND TCK EAE UESU PSP EXER o es F2 l v TDO 1 9 TDI ol ol el ce 1UF 2iw 9 vH 1UF 1 fal A VRI va BSCIZ S5FZ103N 73 c75 q RP1 5V LM1117MPX 3 3 3P3V C 002RX BSCii 1UF bur mur bur C32 ote c2 H 3 OR MC33269ST 3 3 32 768kh BSIDT ji vccaL TUF T 3 us BSRDT u28 AUF 1UF 3 3KSIP10C IN OUT 4 1 sco f STDO LT vec Ls er ES H 2 x2 GND Gem SRDO 1 11 mc Hu m NE Jom EREEDELBR n S0T 223 cae Ae C104 BRE dl SCH2. E2 Dual Ported RAM Port Select Q Q Jump pin 2 to 3 to access DPRAM through JEXP expansion port PMAC 1 PC with Option 2 DPRAM board E Point and Description Default Physical Layout E2 Jump pin 1 to 2 to access DPRAM from baseboard Pins 2 and 3 jumpered with PMAC 1 PC base board only Pins 1 and 2 jumpered when used on all other 3 base boards E4 E6 Power Up Reset Load Source E Point and Description Default Physical Layout Remove jumper E4 No E4 jumper installed SC Ej E jump E5 pin 1 to 2 jump E6 pin 2 to 3 to read flash IC on power up reset Other combinations are for factory use only the board will not operate in any other configuration E5 and E6 jump pin 1 to 2 E7 Firmware Reload Enable bus port Remove jumper for normal operation E Point and Description Default Physical Layout E7 Jump pin 1 to 2 to reload firmware through serial or No jumper installed Flex CPU Board Jumper Descriptions 11 Flex CPU Piggyback Board Hardware Reference E10A B C Flash Memory Bank Select E Point and Description Default Physical Layout E10A Remove all 3 jumpers to select flash memory bank No jumpers installed with factory installed firmware Use other configuration to select one of the 7 other flash memory banks 12 Flex C
3. SES ed OE2 TR2 DO 28 OF Bags BD00 B D1 22 BD01 B A14 B14 oB D2 E MD p BD02 B D3 ET aS Bis BD03 B D4 1 gos ao Ee 1 BDo4 B D5 33 BD05 B A10 B10 D6 tH GND GND BD06 B D7 36 B9 BD07 B DB Sa ke Ss BD08 B D9 38 Ag Er BD09 B D10 1 3 eno Eileen apio B DT AL 45 BS BDI1_B iH Ad B4 D12 1 ay och E 1 B012 B D13 Fake e BD13 B D14 1 zg CND GND 3 T1 B014 B A1 B1 D15 4L 50 Bo 2 BD15 B BO OE1 TIRI IDT74FCT164245TPA TSSOPA8 U23 250 DEZ TIR2 24 BRD D16 2a OF Big BD16 B D 212 N Bia bee BD17 B D18 T GND GND it BD18 B A13 B13 D19 20 A Bis 19 BD19 B D20 1 20 CC cec VOCE 1 8D20 B D21 33 AM EM BD21 B D22 I4W GND enD 5 3 ep B D23 36 9 Bg BD23_B BAOO ar pe BA00 B BAO1 38 Ac AJJET BAOT B BA02 ted D one rt BA02 B BA03 41 8 BA03 B iH A B4 BA04 aa ACOA NODE rg 1 Bang B BX Y 44 A2 B2 5 BX Y B BPHA 48 GND oN L3 f PHa B BSER PTERA Ble SER B 4 4 q 061 TIRI H d IDT74FCT164245TPA GND TSSOP48 GND i Ai9XiYP 8 U17 A18 vec AT A17 GND 1063 1 wc vssHe 4 AIS A16 7 JUF BAIS A16 ce l 0 AUF A15 Ate vss o 3P3v l BATA ae ks BBRCS K BBRCS A14 BAT3 CE Boa BRD A14 A14 O
4. GND OD 16 Bam xd ESCH ad SEIT STOO EL SRDO Ditz Dig EN c23 TA n 17 BA c28 BSRDI BOOTEN imm Au p11 raa a Ji MAAE BRIS SH D20 D21 E ER s T X E vcc vec SC10 D21 AT 30 NES CO BATZ eats l rol 9 BSCIZ SCHT H3 Seb Ut 021 Tes D22 TXD 1UF A13 28 BA13 1UF BSCKI G AG D23 2 TAD H a13 B13 A BA13 10KSIP10C SE SCk1 DSP56311GC150 D23 Re 2 CIS T MA 27 GND GND BATA mm 8p3V 1 PHA A i Sa A pus AT C36 A RIS AT 26 M14 Bil BA15 SERA 2 M14 AZ ND ak 5 T A15 Bis Z2 BA15 TIO1 A2 AS 6 OE2 TIR2 e TE ag HH H BG P13d ne A EL A4 1UF TALCX16245 DE ITEM BS A kis AS uaa U4B usc TSSOP48 3P3V FLASHCS P12 A Paa AG BA P GUARD BAND us GUARD BAND DRAMCS AAI AT INIT 1 4 amp RESET idor i PRAMCE AA2 ar Hi 4 CPUGIK 474 OF m EXTAL GUARD BAND Nd Cas A Lus AQ 10K 8014 J J 8014 HACK 46 pa y HIS ATO TAACTIA 74ACT14 Q4 T4ACT14 ES B1 FOE RN XTAL A10 an on GND a inne areas S5FZ103N EXTAL EXTAL Att Hi A 6014 n TSPSV AISXIYP 44 BXY SPV vecaLo e 5 Mo G14 d A2 B2 BXIY ES CLKOUT A12 C24 WR 4 BWR c27 N10 G12 AT H e 7 A3 B3 BWR BCLK AB 7 U J 4 Cai F1 C42 C43 zd E13 AJA GND 2N7002 Gisp 3P3V RD 41 Mg on 8 BRD RD l ei POLY Me PEU Ms F14 A5 C35 SEN RPSB SOT23 l 1UF BAOS 40115 B5 HE BAOS A SC 1UF UF ATUF PS CAP ato LEI AS WDTC d 1 KI AT 1 GND 1 GNDP A17 1KSIP6I KSIP6I 2 us E A6 BAO6 A GNDO P6 GNDP1 RD RE DIUE FLASHCS BAOT 37 I WR E 2 BSCAN Bam A BROTA GND Do
5. Ad ee we bii 2 exp wo D hi 16V 18V EE 1H 35444734 E EE f NC NC 2 10 L_PRDY emp TANT TANT soc GND i S_ ira CTS pil 10 RTS RTS tue EEETEETTTEREEEREEEEERETE daw ZB re uc eeh zz89020002990099009200899 1 2 evo x2 e 9 les cts HH BOX J5 SSS 8S8S SSSSSSSSS 33839 d ji TDI GND GND eee SE MAX3100CEE v2 L Q GND __BHO Do oe co cn gt HO po LEI D0 4 m BHI Hi p1 222 PT MAX3232ECWE 3P3V BHZ Dis Dz TP2 R3 ECS 36 20 5P 22p 22pf SOL16 TCK Ur BH3 e D2 Pcia D3 3 6864Mhz 4 H3 D3 741 6 R A TIRI H 1 BH 00 NS da na pois M AO 474 QE1 BAOO ADS SOS P2 His ps 813 DS SIRQ 1K i i AT 48 4 ES BAOT BHS Ni C12 De Al B1 BAO1 H6 D6 RESET 45 GND GND l 4 Bi RG p A13 BT 9 TMS USES AZ E BAOZ PV BHAD M3 B12 DS GND A2 B2 BA02 HAO D8 GE c22 AS 43 BAD C29 BHAT M A12 DS BANDING REQ D ES Kee ji WA A SCKO BHAZ HAT pe D10 A EY pi MR DE Aa 4L VOC vec BAS ibg rol 9 BB MODD IRGD HA2 D10 Ay Dit TRST 1UF AS p Be Ba Kee 1UF BHDS sg nes D11 eio Diz A aS as 85 iz BAOS 10KSIP10C BHRAW HDS D12 D13 g MM BE A Li Ra HEADER14 NO8 AG GND GND BAS i BHACK HRW D13 Bu 56 B6 D pre 2 BRIS EHREG HACK D44 B30 PB i cns 585 ar B7 BAOT OA AES BAND HREQ pwp m st B8 BA08 AAE E So xD p16 A AS ES BG BTD Ga BS Dir A9 B9 H BA09 BAAT E SRDO TXD D17 ma i eg a es LOB mu s Pav A0
6. CTS 1UF STDT SRDT 24A SCEI SCT 3P3V SCH o IRQB TAACTS2 4 S 1 S014 RPA CSa WAITT U24B 3 3KSIP10C BRD A VSPOTVTIBAOT Lem BRD KBRD_A u27 D7 BRXD hdd aci 18 RXD TAACTA BCIS 2 pe 1 CIS amp BPHA S014 SER A l 4149 amp Ce BSER 1SMC5 0AT3 PHA A 1 a Eis BPHA GND T4ACT14 T4ACT14 c82 U24C BHAZ i 8 BG HAZ S014 SO14 25v o GND PRAM MEMORY P BHAD ij Gr HAD P BHAD p Bu HAD U26F U26E MODDIRAD 9 1 TROB 4 AT B7 000000 00FFFF Fi 64K TIT ee ge a irmware SO14 RESET mal Do c87 T4ACT14 74ACT1A 040000 50403FF U Writt Ph 1K px EH TA eom Pon Ser FI en ase TSSOP20 AUF i BRD EE KBRD B ee U26D 040400 040BFF User Written Servo 2K ji RESETS Keeser B Stee TAACT32 GND E y 050000 05FFFF Plcc Standard Memory Option 64K E Se fis igor DSP563XX CPU Piggyback Board m ize Document Number lov ER F 1 Link D S 050000 S0BFFFF Plcc Extended Memory Option 448K tan 603605 322P Date Thursday September 19 2002 Eheet 1 of z 7 A H z 3 z 1 8 THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU DATA SYSTEMS INC AND IS LOANED SUBJECT TO RETURN UPON DEMAND TITLE TO THIS DOCUMENT IS NEVER SOLD OR TRANSFERRED FOR ANY REASON THIS DOCUMENT IS TO BE USED ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS OF DELTA TAU DATA SYSTEMS INC ALL RIGHTS TO DESIGNS AND INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC POSSESSI
7. Installation XE J OPERATION OF THE FLEX CPU viectossiveiresacosissdovosesssdo sbon sees sins tn sens tu seta tuse to sons osere enses suse tasse diosa sser To sasasi 7 Operation as Non Turbo E 7 Operation asd Turbo CPU eterne Tode as So a Ka ER 9 FLEX CPU BOARD JUMPER DESCRIPTIONS ee eeeeeee eese teens entes etas tn senses tasses snae ta sone tasas enses ens en sensns 11 EI e 11 E2 Dual Ported RAM Port Select esee teret rerit esent unie thi nt rte nonet rte e eta eee cba des 11 E4 E6 Power Up Reset Load Source 11 EZ Firmware Reload Enable dtt eii etie eet teer be L 11 EIOA B C Flash Memory Bank Select 12 CONNECTOR SUMMARY 13 CONNECTOR SUN TOU N 15 J8 JRS232 10 Pin Connector eese esee eese en nnne nennen nennen enn nn enne trs rennen rennen ener nennen nnns 15 SCHEMATICS Table of Contents i Flex CPU Piggyback Board Hardware Reference Table of Contents Flex CPU Piggyback Board Hardware Reference INTRODUCTION The Flex CPU piggyback board Part f 300 603605 10x for the PMAC PMAC2 and Turbo PMAC PMAC 2 families of boards provides new high end capabilities for these controllers and uses newer components with longer product lifetimes It can be manufactured in a wide variety of configurations and can be used in the following products PMAC 1 PC PMAC 1 PCI PMAC 1 VME PM
8. in software by new variable I46 If this variable is set to 0 PMAC firmware looks at the jumpers E48 on a PMAC 1 E2 and E4 on a PMAO2 to set the operational frequency retaining backward compatibility for 40 60 and SO MHz operation If 146 is set to a value greater than 0 the operational frequency is set to 1OMHz 146 1 regardless of the jumper setting If the desired operational frequency is higher than the maximum rated frequency for that CPU the operational frequency will be reduced to the rated maximum It is always possible to operate the Flex CPU board at a frequency below its rated maximum On a Flex CPU board configured for Option 5AF with 40 MHz maximum frequency 146 should be set to 3 to operate the CPU at its maximum rated frequency On a Flex CPU board configured for Option SCF with 80 MHz maximum frequency 146 should be set to 7 to operate the CPU at its maximum rated frequency On a Flex CPU board configured for Option 5EF with 160 MHz maximum frequency 146 should be set to 15 to operate the CPU at its maximum rated frequency I46 is only used at power up reset so to change the operational frequency set a new value of 146 issue a SAVE command to store this value in non volatile flash memory then issue a command to reset the controller To determine the frequency at which the CPU is actually operating issue the TYPE command to the PMAC The PMAC will respond with five data items the last of which is CLK
9. these ICs fill the smaller footprint in these locations leaving an open pin on the board on each end of each side When the Flex CPU is built for ISA bus or VME bus baseboards the P3 connector consists of a 36 pin header on the solder side for direct connection to the baseboard and a 10 pin header on the component side for cable connection of the extra signals required for dual ported RAM interface When the Flex CPU is built for PCI bus baseboards the P3 connector consists only of a 56 pin header on the solder side for direct connection of all signals to the baseboard Turbo CPU Further Options If an expanded memory configuration Option 5x3 is ordered larger RAM ICs are installed in locations U11 U12 U13 U14 U15 U16 occupying the full footprints in these locations If the Option 9T auxiliary serial port is ordered for the Turbo PMAC controller an RS 232 serial port is provided on the CPU board to supplement the serial port on the baseboard The key components are ICs in U28 and U29 and the connector J8 The Option 16A battery backed parameter RAM provides a bank of non volatile memory for the controller Its key components are RAM ICs in U17 U18 and U19 and a battery in BTI Board Configuration 3 Flex CPU Piggyback Board Hardware Reference Board Configuration Flex CPU Piggyback Board Hardware Reference HARDWARE SETUP Flex CPU Board Jumper Configuration Watchdog Timer Jumper Jumper E1 on th
10. 1 WR WE Bam WE BA02 Air B liaqg 9 BA02 SS BAQ3 A16 yee GND C62 BAQ3 M7 Bags co BAQA A15 n Se BAOS A14 4 10 3P3v J 1UF BA05 A15 vss BAOG A13 BAQ6 A1 BAO7 o SEL Ate A13 vec HZ BAOS ATI 4 GND C63 BAO8 A12 BA09 A10 A TUS BA09 S BATO AQ 28 3P3y_ 1UF BA10 A10 vss BATI AB BA11 A9 BA12 AT Q BA12 e BAT3 A6 Q D7 BA13 AT D7 BA14 A5 G 2 D6 BA14 A6 D6 BA15 A4 6 D5 BA15 S Bx A3 4 5 De D4 BX Y A4 D4 A2 D3 A3 D3 A1 4 De A2 D2 Eu A1 pi H ba AT9XIYP AD DO DO KM68V4002 SOJ36 E10 FLASH BANK SELECT 3p3V O e R15 R16 33K 23 3K E10A lo o2 34 E10B A 16 o2 E10C 16 o 4 A U10 A22 A24 WP FLASHCS a FLASHCS Pa i 2q CE1 WE S PA20 PADD 4 320 Sts FS PA19 PAIS 5 A19 pais l PA18 PANS 6 A18 Da7 l i PA17 PAU ZI A17 DQ14 a PA16 PAI Bt A16 Doe l 2 3P3V 5V 9 vec GND 48 pes 10 A15 DQ13 i E ii BAT A14 Das 121413 DQ12 45 BAT2 1a A12 Dou l 4 14 43 CEO vcca RESET l ed VPEN GND 42_ wen Ar jii BAT 18 a10 DQ10 He E 19 A09 Daz l 8 BAQB 20 7 Aog vec 22 BAG 4 21 end Dag r 227307 pat 39 BAO 23 1406 pag LA WI BAS 24 A05 Dao H32 SOLDER BADI ZB A04 A00 32 26 p31 4 JUMPER BAO2 2 ne SE ten BA01 28 A01 CE2 H2 a E28F320J3A jer c78 TSOP56 AUF AUF 5V ENEE RF o GND CWl 1 TO FOR 28F320J3A Wl 2 TO 3 FOR 28F320J5A u20 cs A KES A 450 DEI TIRI PROS x 12 B
11. 400 19200 28800 38400 57600 76800 115200 Operation of the Flex CPU Flex CPU Piggyback Board Hardware Reference For a PMAC2 board with a saved value of 0 for 146 the serial baud rate is determined by the combination of I54 and the CPU frequency on a PMAC2 board as shown in the following table These settings maintain backward compatibility I54 Baud Rate for Baud Rate for Baud Rate for 40 MHz CPU 60 MHz CPU 80 MHz CPU 0 60 Disabled 1200 1 900 0 05 900 1800 CO 19 2 2400 3 3600 0 19 4 4800 5 7200 0 38 6 9600 7 14 400 0 75 8 19 200 9 28 800 1 5 10 38 400 1 57 600 3 0 12 76 800 13 115 200 6 0 14 153 600 15 DISABLED Not an exact baud rate e With the Flex CPU the card number 0 15 for serial addressing of multiple cards on a daisy chain serial cable is determined by variable IO even on PMAC 1 boards This has always been the case for PMAC2 boards but with other CPU boards the card number on PMAC 1 boards has been determined by the settings of jumpers E40 E43 Jumpers E40 E43 on a PMAC 1 board with the Flex CPU still determine the direction of the phase and servo clocks all of these jumpers must be ON for the card to use its internally generated clock signals and to output these on the serial port connector if any of these jumpers is OFF the card will expect to input these clock signals from the serial port connecto
12. 9 4 H BA09 bel BAO8 A POLY CAP GND 1 PRAMCS EE A9 i BAO9 A GND T 5 TAPIV BATO SD pn 18 BATU A EA TAPIV T Nd MMBD301LT1 S WR c25 BATI 32 41 Bry IZ BAIT A Sea en TPI ND RPSC k 18 ku GND 1KSIP6I 3 tl vec vec GND HSIPENOS BAZ 3n NCE Co GER SEN l SE cat 1UF BAIS 29 A12 Bi ER A 1UF ar Us UD O1UF ri 1 z E MMBT3906LT1 16 t BATA Fa beg Eon BAT A FAM PV 1 L S0723 NG NS Es a l S wDo i BATS 26 E 868 g A REN EKWA voe Dua o Gi S014 E o2 TIR Bi Te MODE NMI DT Taner TALCX16245 ToL RST pit GND TSSOP48 Ra ce NC NC Fo E1 100k T 35v 8 GND rst L ve o lant DS12318 c2 11 10 d GND E14 SOL 16 EL T 30 1UF 8014 MODA IRQA m 30 4 T4ACT14 MODB IROB i DEM E MODCIIRQC Ll ji Us 9 BOOTEN sno l 85 BHO SOT amp 1 4 H1 po L Al SIRQ 36 BHZ BIXD D MMBD301LT1 Hz BH2 Dos BH3 BSCTI 9 AW 130 D2 D2A Di DIA bag BHS CS BHA 7 ien LED JW LED WE LED H4 BH4 SC 3 3KSIP10C 3P3V Vbat M GRN GRN Jy RED y RED L3 l a ia i s BH E asv Som Ss Re M e H7 BH7 i C33 9 HRW BHRW i 0 IS BHDS D Ee T A DUAL FOOTPRINT o5 RS REA R6 REA B DI Vout A4 LA13 LA13 vec quan e Vout d 1K 1K 1K 1K PA16 GUARD BAND x A5 PA16 Hi PA16 as Pate HE PAT Slab Memory Range p Braet u A7 pats 24 LS PA18 d dec R7 nm 4 B pato 22 FA PA19 l GND ox H 100 IE 1 A ilvour Bat L A9 PA20 PA20 i PA m a PA21 er MHIRISEA J 6608 3 6V BAT MMBD301LT1 Lal vce RS L RESET RESET A11 VMECS 34 s
13. AC2 PC PMAC2 PCI PMAC2 VME Turbo PMAC 1 PC Turbo PMAC 1 PCI Turbo PMAC 1 VME Turbo PMAC2 PC Turbo PMAC2 PCI Turbo PMAC2 VME On the regular non Turbo PMAC 1 and PMAC2 boards the Flex CPU is provided automatically when any of the following CPU options are ordered e Option SAF 40 MHz CPU with 128k x 24 internal SRAM e Option SCF 80 MHz CPU with 128k x 24 internal SRAM e Option 5EF 160 MHz CPU with 128k x 24 internal SRAM The Flex CPU board is not provided if Option 4x or 5x is not ordered or if Option 4A 5A 5B or 5C is ordered On Turbo PMAC 1 and Turbo PMAC2 boards the Flex CPU may be provided when any of the following CPU options is ordered Option 5C0 80 MHz DSP56303 CPU with 8k x 24 internal SRAM 256k x 24 external SRAM Option 5C3 80 MHz DSP56303 CPU with 8k x 24 internal SRAM 1M x 24 external SRAM Option 5D0 100 MHz DSP56309 CPU with 34k x 24 internal SRAM 256k x 24 external SRAM Option 5D3 100 MHz DSP56309 CPU with 34k x 24 internal SRAM 1M x 24 external SRAM In these cases however the older Turbo only CPU piggyback board may also be provided On Turbo PMAC 1 and Turbo PMAC2 boards the Flex CPU will be provided automatically when either of the following CPU options is ordered e Option SEO 160 MHz DSP56309 CPU with 128k x 24 internal SRAM 256k x 24 external SRAM e Option 5E3 160 MHz DSP56309 CPU with 128k x 24 internal SRAM 1M x 24 external SRAM Introduction 1 Flex CPU Piggyback Board Hard
14. BWR A bi 38 BD10 B BD11 B A RUA BD12_B BD13 B BATA A BD14 B BD15 B BA14 A Banda PARA BD16 B BD17 B BAOG A l BD18 B BD19 B BA06 A SS BAOB A 14 03 BD20_B BD21 B Bonn 20 BATO A me BD22 B BD23 B Danos Q0 DPRCS nt BAO0 B BAO1 B VSPO1VT28A01 BA02 B BA03 B GND BAQA B BXN B CS2 CS3 CS2 CS04 CS06 Coe CS04 CS10 CS12 C06 CS10 CS14 CS16 KEE Kg BA12_B BAi3 B d an 8 C MRE BRD B BRD B RESET B WAIT2 RESET B K ep B PHA B KKWAIT2 D sh2 sch G Delta Tau Data Systems Inc Title DSP563XX CPU MEMORY UO SECTION Bize Document Number e 603605 322P Date Thursday September 19 2002 Sheet 2 8
15. DOOA D1 46 A 3 BDOTA 45 4 8P3V DZ 4g GND GND BDT A c45 D a3 Ae BDOS A ll Di 42 VCCA VCCB H BDA L8 _BDO4 A AUF S05 ane BD05 A 1 D6 3p GND GND 1 pros 11 BUS A D7 aras BDO7 A D8 3a i3 BDOBA DS ER 15 BDOSTA 25 1 A0 T t 8P3V D10 aar gha GND 18 BD10 A C46 Dit 32 AN B10 12 BDITA 5 S11 vcca vccB H il 2012 l 30 BD12 A AUF D13 29 Al Big 20 BD13 A T Did a GND GND Z1 spi A 22 BDi4 A Dis 268 JA14 Bid BD15 A 1 A15 B15 m AME 1 kO oE2 T R2 24 9 IDT74FCT164245TPA TSSOPA8 U21 D16 Ska TRI ESI Di6 47 l 2 BULA Dro py BDI A 45 4 T 8P3V Di8 44 GND GND BD18 A c47 D19 43 Pc 6 BD19 T Ji D20 M VOCA AC A BD20 A AUF D21 40 pe 9 BD21_A T D22 P GND GND e BD22 A D23 37 46 12 BD23 BAOO 36154 13 BAC A BA01 35158 14 BAC A ki 8P3V BAO2 en Kat ap ja BAG A BAOS 32 17 BAOSA kari BAQ3 Set B11 Di BAO3 A TI BAQA Em VCCA VCCB 15 BAO4 A 1UF BXIY 29 12 B12 20 BXWA 28 A13 B13 22 GND GND LAT 27 LA12 tA A14 B14 DAE E LA13 A3 AIS B15 23 EAT9 9 250 oE2 TIR2 IDT74FCT164245TPA O GND I NETLIST CHANGE TSSOP48 3P3V 5V o U22 9 IOCS B 25d Lat BRD
16. E AS A13 vec BATZ B A13 we p22 BWR AXE 4 A12 BAM 4 M2 vop l 21 E A11 BA10 A10 AT BAO AM A10 vss A10 A9 BA08 6 A9 A9 AB NA BAO ye AT ae p La D23 BAOG ER Da l 21 D23 AG al ne be 28 D22 BAQ5 6 Bac l 20 D22 A5 ae be 28 D21 BA04 7 jc SCHIER D21 A 4 25 D20 BAO3 8 Q5 Fis D20 A4 D4 A4 DQ4 A3 12 D19 BA02 9 17 D19 A3 D3 A3 DQ3 A2 4 11 D18 BAOT 10 15 D18 A2 D2 A2 DQ2 A1 A1 D1 8 D17 BAQO 11 A1 Dal 14 D17 AO AO Do r D16 BX Y 12 A0 DQO 13 D16 KM68V4002 KM68V1000BL 70 SOJ36 SOJ SOP32 GND U15 400MIL RD Ed D WE C54 AT9XIYP 8 As vec U18 II A17 AT GND C66 tle vss He 4 at A16 BAIS A16 ce L30 AUF A15 y 10 BATA cE BBRCS A15 vss A15 CE A14 BAT3 CE PA BRD A14 A14 OE Als A13 vec E 8 A13 WE BWR A12 4 GND C67 BAT 4 3 Vout A12 e A12 VDD AM A11 7 iUF BATO A11 A10 eu vss L28 3P3v l BAOS y A9 BA08 6 A9 A9 AB be BAO AS AT AS p Lao D15 BAOG SIA Da l 21 D15 AG 6 29 D14 BA05 6 20 D14 AG De 6 DQ6 AS As De 26 D13 BAQA 7 Das l 12 D13 A4 4 25 D12 BA03 rae 18 D12 A4 D4 A4 DQ4 A3 12 Dii BA02 9 17 D11 A3 D3 A3 DQ3 A2 4 11 D10 BAOT 10 15 D10 A2 D2 A2 DQ2 A1 A1 D1 8 D9 BAOO 11 A1 pat 14 D9 AO AO Do H E BX Y 12 A0 Dao H D8 KM68V4002 KM68V1000BL 70 SOJ36 SOJ SOP32 GND U14 400MIL RD S WR OF C55 A19XIYP 8 As Vee U19 J AL A17 GND ce Lne vss Ha 4 ll Ae A16 Ti BAIS A16 ce l 80 AUF A15 d 40 43P3v TUF BAT4 ce BBRCS A15 vss A15 CE A14 BAT3 CE DA BRD A14 A14 OE A13 A13 vec BAT2 8 A13 WE B
17. HARDWARE REFERENCE MANUAL Flex CPU Piggyback Board DELTA TAU Data Systems Inc NEW IDEAS IN MOTION Single Source Machine Control Power Flexibility Ease of Use 21314 Lassen Street Chatsworth CA 91311 Tel 818 998 2095 Fax 818 998 7807 www deltatau com Copyright Information 2003 Delta Tau Data Systems Inc All rights reserved This document is furnished for the customers of Delta Tau Data Systems Inc Other uses are unauthorized without written permission of Delta Tau Data Systems Inc Information contained in this manual may be updated from time to time due to product improvements etc and may not conform in every respect to former issues To report errors or inconsistencies call or email Delta Tau Data Systems Inc Technical Support Phone 818 717 5656 Fax 818 998 7807 Email support deltatau com Website http www deltatau com Operating Conditions All Delta Tau Data Systems Inc motion controller products accessories and amplifiers contain static sensitive components that can be damaged by incorrect handling When installing or handling Delta Tau Data Systems Inc products avoid contact with highly insulated materials Only qualified personnel should be allowed to handle this equipment In the case of industrial applications we expect our products to be protected from hazardous or conductive materials and or environments that could cause harm to the controller by damag
18. ON OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE ABOVE AGREEMENT U11 400MIL CE RD BO OE WR A 3d WE Ax A18 vec GND C58 A15 A AUF AG AO A14 B45 aye vss o 3P3V AT A13 33 Al A14 AD A12 32 43 27 A2 A3 ATI 24 ZE GND C59 AS A12 P Ad A10 23 A11 Ti ES nS 2 28 43P3v J 1UF AS A10 vss A6 AB 21 Aa A9 P AT AT 20 ag AB AG 17 Q D23 AB AT D7 A9 A5 16 9 D22 jie A6 D6 A10 A4 15 6 D21 A10 A5 D5 ATI A3 14 D20 A11 A4 D4 A12 A2 5 D19 A12 A3 D3 A13 At 4 D18 A13 A2 D2 Ad A14 AO E r bi L8 D17 A4 AS AT9XIYP FE DO D16 ae A17 en KM68V4002 SOJ36 A19XIYP X U12 400MIL Do amp Bi cE DI et OE 02 53 WE d D3 83 A18 vec GND C60 D4 R DA A17 D5 pe A 10 ne S A15 vss D eB A14 at pe BB A13 vec GND cei DS A12 a D10 D10 A10 A11 Da Dit A9 28 43P3v J 1UF D11 A10 vss D12 AB D12 AQ D12 DI AT 0 As D14 A6 Q D15 D14 A7 D7 D14 ro S 9 D14 D15 A6 D6 D16 A4 6 D13 D16 A5 D5 D17 A3 4 D12 D17 A4 D4 D18 A2 D11 D18 A3 D3 D19 AT 4 D10 D19 A2 D2 D20 SE 8 A1 Di D9 D20 Dat AT9XIYP AD DO D8 D22 DE KM68V4002 SOJ36 U13 400MIL i cE Koo BA00 RD OE BAO
19. PU Board Jumper Descriptions Flex CPU Piggyback Board Hardware Reference CONNECTOR SUMMARY J2 JEXP Expansion Port 50 pin IDC header for Delta Tau accessory boards J5 JTAG OnCE Port for factory use only J6 JSIO Port for factory use only J7 JISP Port for factory use only J8 Auxiliary Serial Port 10 pin IDC header P1 Stack Connector Internal connections to main PMAC board P3 Stack Connector Internal connections to main PMAC board Pinout shown in next section Connector Summary 13 Flex CPU Piggyback Board Hardware Reference 14 Connector Summary Flex CPU Piggyback Board Hardware Reference CONNECTOR PINOUTS J8 JRS232 10 Pin Connector NA Front View Pin Symbol Function Description Notes 1 N C No Connect 2 DTR Bidirect Data Terminal Readv Tied to DSR 3 TXD Input Receive Data Host transmit data 4 CTS Input Clear to Send Host readv bit 3 RXD Output Send Data Host receive data 6 RTS Output Request to Send PMAC ready bit 7 DSR Bidirect Data Set Ready Tied to DTR 8 N C No Connect 9 GND Common PMAC Common 10 45V Output 5VDC Supply Power supply out The JRS232 connector provided with Option 9T on a Turbo PMAC is an auxiliary serial port that can be used independently of the standard main serial port and other communications ports It can be connected with a straight across flat cable to a DB 9
20. WR A12 4 GND c65 BAT 4 32 Vout A12 ae A12 VDD AT E Hur BATO A A10 A vss 128 3P3V BA09 an A9 BA08 6 A9 A9 AB 0 As BAO AT hs p l 0 D7 BA06 5 45 para D7 AG 6 29 D6 BAOS 6 Q7 20 D6 AG De 6 DQ6 AS 26 D5 BAO4 I 19 D5 AS D5 A5 DQ5 A4 4 ES D4 BAOS 8 18 D4 A4 D4 A4 DQ4 A3 12 D3 BA02 9 17 D3 A3 D3 A3 DQ3 A2 4 11 D2 BAO1 10 15 D2 A2 D2 A2 DQ2 A1 AT D1 8 D1 BA00 11 M Dal 14 D1 AO AO Do DO BX Y 12 AO DQO 13 DO KM68V4002 KM68V1000BL 70 SOJ36 SOJ SOP32 GND W2 JUMPER SELECTION JUMPER 2 3 for Standard PMAC1 and PMAC2 JUMPER 1 2 for TURBO ON SOLDER SIDE P3 P3 P3 30 P3 32 P3 34 P3 36 BA13A BA15A J4 02 J4 04 J4 06 J4 08 J4 10 BD01 A Q BDO3 A BD05 A 4 BD07 A 6 BD09 A 8 BD11 A Q BD13_A BD15 A 4 BD17 A 6 BD19 A 8 BD21 A Q BD23 A 4 BAO1 A 6 BAO3 A 8 BX Y A OOOCOOOOOOCOOCOOOOOOOOOOOOOOOOO cst BRD_A BA13_A BA15 A BA05 A BA07 A BA09 A BATA VMECS SOLDER GATA JUMPER W2 SPARE SPARE BA12 A HB1 5 lo SPARE SPARE 2 SPARE SPARE BD00 A P3 01 P3 02 E EA P3 03 P3 04 Ge P3 05 P3 06 GND BD08 A P307 P308 SC P3 09 P3 10 BD12 P3 11 P3 12 EDDA P3 13 P3 14 EA P3 15 P3 16 BD A P3 17 P3 18 NA P3 19 P3 20 J Ree P3 21 P3 22 e P3 23 P3 24 BD00_B BD01_B BA00_A ES MEE BDO2 B BD03 B BAO2 A peer S BD04 B BD05 B En BD06 B BDO7 B o pl BDOB B BD0S B BWo 20
21. Xn where n is the multiplication factor from the 20 MHz crystal frequency not 10 MHz n should be equivalent to 146 1 2 if I46 is not requesting a frequency greater than the maximum rated for that CPU board n will be 2 for 40 MHz operation 4 for 80 MHz operation and 8 for 160 MHz operation If the CPU s operational frequency has been determined by a non zero setting of I46 the serial communications baud rate is determined at power up reset by variable I54 alone according to the following table Operation of the Flex CPU Flex CPU Piggyback Board Hardware Reference I54 Baud Rate I54 Baud Rate 9600 14 400 19 200 28 800 38 400 57 600 776 800 7200 15 115 200 Note that these values can be different from those used on PMAC2 boards with jumper set CPU frequencies see below If the saved value of 146 is 0 so the CPU s operational frequency is determined by jumper settings then the serial baud rate is determined by a combination of the setting of jumpers E44 E47 and the CPU frequency on a PMAC 1 board as shown in the following table These settings maintain backward compatibility E44 N OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF Not an exact baud rate E45 E46 E47 Baud Rate Baud Rate Baud Rate for for for 20MHz 40MHz 60MHz Disabled ON ON JON Lu j600 X 900 1200 OFF JON ON o0 1200 1800 2400 3600 4800 7200 9600 14
22. connector with the standard RS 232 pinout Connector Pinouts 8 THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU DATA SYSTEMS INC AND IS LOANED SUBJECT TO RETURN UPON DEMAND TITLE TO THIS DOCUMENT IS NEVER SOLD OR
23. e Turbo CPU board must be OFF for the watchdog timer to operate This is a very important safety feature so it is vital that this jumper be OFF in normal operation E1 should be put ON only to debug problems with the watchdog timer circuit Dual Ported RAM Source Jumper Jumper E2 must connect pins 1 and 2 to access dual ported RAM non Turbo addresses Dxxx Turbo addresses 06xxxx from the baseboard If it is desired to use the Option 2 DPRAM on the baseboard jumper E2 must be in this setting All Delta Tau base boards except the PMAC 1 PC board have the option for installing DPRAM on the base board Jumper E2 must connect pins 2 and 3 to access dual ported RAM non Turbo addresses Dxxx Turbo addresses 06xxxx through the JEXP expansion port If it is desired to use DPRAM on an external accessory board jumper E2 must be in this setting The PMAC 1 PC base board part 602191 10x does not have the option for installing on board DPRAM it requires the external Option 2 DPRAM board part 602240 10x for this functionality Use of this DPRAM board interfacing through the JEXP port requires E2 to connect pins 2 and 3 Power Up State Jumpers Jumper E4 on the Turbo CPU board must be OFF jumper E5 must be ON and jumper E6 must be ON in order for the CPU to copy the firmware from flash memory into active RAM on power up reset This is necessary for normal operation of the card Other settings are for factory use only Firmware Load Jumpe
24. ing components or causing electrical shorts When our products are used in an industrial environment install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture abnormal ambient temperatures and conductive materials If Delta Tau Data Systems Inc products are directly exposed to hazardous or conductive materials and or environments we cannot guarantee their operation Flex CPU Piggyback Board Hardware Reference Table of Contents INTRODUCTION occ T dd edaa za 1 BOARD CONFIGURATION en some en ena 3 Non Turbo CPU Base Configuration eese eene tenete teen neen eret nr tn tn enne enne tenete enne nn mann tnn 3 Non Turbo CPU Further Options eese rna anna tna En entren enne trte teet trennen ne 3 Turbo CPU Base Configuration eese e ana a o et rente enne enne tene tnet tree te entrent 3 Turbo CPU Further Options Gm 3 HARDWARE SETUP Ls HM 5 Flex CPU Board Jumper Configuration uae ten fli pa eere eet sa A de oe Rp c eb xenon 2 Watchdog Timer JUMP er REO o Dual Ported RAM Source Jump r eege etes tee ini kai eee iss aie e pue Se a e ene va 2 IIO e SII NT 2 Firmware Lodd Jumper EENS a aue ru ea ND CU e e RE E va 2 Flash Memory Bank Select Jumpers esses eese eene enne tnn tatna rna nat nt tra enne en nette tene trennen ten 5
25. itive components Make sure proper ESD protection is employed Hardware Setup 5 Flex CPU Piggyback Board Hardware Reference Hardware Setup Flex CPU Piggyback Board Hardware Reference OPERATION OF THE FLEX CPU Operation as Non Turbo CPU When used as a non Turbo CPU the Flex CPU board operates in a manner that is fundamentally compatible with older CPU designs However there are a few issues to note The Flex CPU requires the use of V1 17 or newer firmware There are few differences between the previous V1 16H firmware and the V1 17 firmware other than the addition of internal support for the Flex CPU design Due to more advanced processor logic and the internal integration of all memory the Flex CPU will operate significantly faster than older non Turbo CPU designs even for equivalent CPU frequencies The Flex CPU in a non Turbo configuration will generally operate more than twice as fast as older non Turbo CPUs running at the same frequency This will result in significantly faster cycle times for background tasks such as PLC programs the frequency of interrupt driven foreground tasks is not affected although the increased computational speeds permit higher frequencies for these tasks Generally this will not be a problem but if existing programs controlled timing by computational delay e g number of loops waiting operational differences may occur The operational frequency of the CPU can now be set
26. or28 CEO b BBRCS E As pared biz cni c102 VIB GUARD BAND ON GEO KBBRCS A14 can D 1OCS A TES YS Veo 114 3 4 cop cu BBRAMCS A15 1ocs1 p30 IOCS B C100 1 TRST p a AUF 1UF om Gun GE DI Am vec 4 RI MMBD301LT1 MAXT95SCSA 4 Ls 1 49 6608Mhz S08 c15 Ne RD TDO NC GND CLK 19 6608Mhz an 1UF 1 1UF C16 E Q2 x WR TCK NC P TRI 1 CS0 19 6608MHz 014 10 O1FARAD C17 1UF dur 2N7002 5V Gnas PRACT MS Garg 48 E L3 ST gar GND DIP14WIDE T4ACT14 DES SOT23 FLASHCS PROMCS TDI CS2 Es GND 4 _ 4 Le A E l Sr GPUcLKvO E i EN SI A U30 330SIP8I E e 3P3V GND BSTDI 2 La 1 STD1 RESET NC Gi ei O cao NETLIST CHANGE BSRDT AQ B0 FT 4 SRDT BSCAN NC CS4 Hp A1 B1 40 Cem BSCKT 4 16 5 A SCKI GOEO NC Cem BSC12 A En Ap SEB SC12 GOE1 NC CS04 ug 1UF BSCIT 6 43 B3 74 SCH Y CS00 Can A4 B4 CS06 WAIT1 E BIXD 1 TD z i A os zB 4 d BHREG HREQ NC Ce pas C812 Ce WAIT2 lt lt WAIT2 21 AT B7 H4 a vecio Ce di DSt NC7SZ00 1 R 0 VCCIO ESCH CS14 4 TR vec VCCIO csis b i SIE Gd SOT23 5 3 2 oE GND He VE IO BRCLK 933 BRCIK RP7 RPB C88 NC WDTC L MES VMECS Sale 9 3 3KSIP10C 3 3KSIP10C PC raat our NC NC H3 EM E E END d GND GND WDTC GND GND GE I GND GND ND GND GND ISPLSIZOGAE DECODE H A PITAFCTIGZASATA o U26C TSOP100 GND GND TSSOPA8 GND dad 196608M GUARD BANDING REQ D rd HACK c20 RXD ok TAACT14 DO eno S SO14 HRIW
27. r If jumper E7 on the CPU board is ON during power up reset the board comes up in bootstrap mode which permits loading new firmware into the flash memory IC on the board When the PMAC Executive program tries to establish communications with a board in this mode it will automatically detect that the board is in bootstrap mode and ask you what file you want to download as the new firmware Jumper E7 must be OFF during power up reset for the board to come up in normal operational mode Flash Memory Bank Select Jumpers The flash memory IC in location U10 on the Flex CPU board has the capacity for eight separate banks of firmware only one of which can be used at any given time The eight combinations of settings for jumpers E10A E10B and E10C select which bank of the flash memory is used In the factory production process firmware is loaded only into Bank 0 which is selected by having all of these jumpers OFF Installation The Flex CPU board installs on the base controller board using the P1 and P3 stack connectors on the solder side of the CPU board The CPU board can be further secured to the base board with a standoff and screw through the central hole When a complete PMAC or Turbo PMAC controller is purchased this assembly is done at the factory In the case of retrofits or updates to existing controllers this assembly is easy to do in the field ESD Warning The Flex CPU board and PMAC controller boards contain static sens
28. r and its watchdog timer will trip immediately if it does not receive these signals Operation as a Turbo CPU When used as a Turbo CPU the Flex CPU is fully compatible with older CPU designs It does permit higher speed configurations Option 5Ex at 160 MHz which offer significantly higher performance both due to increased operation frequency and added internal memory Variable I52 determines the actual operating frequency of the Turbo CPU The operational frequency is set to IOMHz 152 1 152 should be set to 7 to operate an Option 5Cx board at its maximum rated frequency of 80 MHz it should be set to 9 to operate an Option 5Dx board at its maximum rated frequency of 100 MHz it should be set to 15 to operate an Option 5Ex board at is maximum rated frequency of 160 MHz 152 is used only at power up reset so to change the operational frequency set a new value of 152 issue a SAVE command to store this value in non volatile flash memory then issue a command to reset the controller Operation of the Flex CPU 9 Flex CPU Piggyback Board Hardware Reference 10 Operation of the Flex CPU Flex CPU Piggyback Board Hardware Reference FLEX CPU BOARD JUMPER DESCRIPTIONS E1 Watchdog Disable Jumper 5 purposes only Remove jumper to enable Watchdog timer E Point and Description Default Physical Layout E1 Jump pin 1 to 2 to disable Watchdog timer for test No jumper installed
29. ware Reference Introduction Flex CPU Piggyback Board Hardware Reference BOARD CONFIGURATION Non Turbo CPU Base Configuration When assembled for a non Turbo CPU the DSP IC in U1 of the Flex CPU board contains all of the memory required for operation Therefore there are no ICs installed in the locations for external RAM U11 U12 U13 U14 U15 and U16 The CPU is available in several speed options 40 MHz Option 5AF 80 MHz Option 5CF and 160 MHz Option 5EF The maximum frequency of operation is indicated with a sticker on the CPU in U1 When the Flex CPU is built for ISA bus or VME bus baseboards the P3 connector consists of a 36 pin header on the solder side for direct connection to the baseboard and a 10 pin header on the component side for cable connection of the extra signals required for dual ported RAM interface When the Flex CPU is built for PCI bus baseboards the P3 connector consists only of a 56 pin header on the solder side for direct connection of all signals to the baseboard Non Turbo CPU Further Options The Option 16 battery backed parameter RAM provides a bank of non volatile memory for the controller Its key components are RAM ICs in U17 U18 and U19 and a battery in BTI Turbo CPU Base Configuration When assembled for a Turbo CPU section the Flex CPU board contains external RAM ICs in locations U11 U12 U13 U14 U15 U16 With the standard memory configuration Option 5x0
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